1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
36 "Enable ARMv8 PMUv3 Performance Monitors extension">;
38 /// Cyclone has register move instructions which are "free".
39 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
40 "Has zero-cycle register moves">;
42 /// Cyclone has instructions which zero registers for "free".
43 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
44 "Has zero-cycle zeroing instructions">;
46 def FeatureStrictAlign : SubtargetFeature<"strict-align",
47 "StrictAlign", "true",
48 "Disallow all unaligned memory "
51 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
52 "Reserve X18, making it unavailable "
55 //===----------------------------------------------------------------------===//
59 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
60 "Support ARM v8.1a instructions", [FeatureCRC]>;
62 //===----------------------------------------------------------------------===//
63 // Register File Description
64 //===----------------------------------------------------------------------===//
66 include "AArch64RegisterInfo.td"
67 include "AArch64CallingConvention.td"
69 //===----------------------------------------------------------------------===//
70 // Instruction Descriptions
71 //===----------------------------------------------------------------------===//
73 include "AArch64Schedule.td"
74 include "AArch64InstrInfo.td"
76 def AArch64InstrInfo : InstrInfo;
78 //===----------------------------------------------------------------------===//
79 // AArch64 Processors supported.
81 include "AArch64SchedA53.td"
82 include "AArch64SchedA57.td"
83 include "AArch64SchedCyclone.td"
85 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
86 "Cortex-A53 ARM processors",
93 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
94 "Cortex-A57 ARM processors",
101 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
108 FeatureZCRegMove, FeatureZCZeroing]>;
110 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
115 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
116 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
117 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
118 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
119 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
121 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125 def GenericAsmParserVariant : AsmParserVariant {
127 string Name = "generic";
128 string BreakCharacters = ".";
131 def AppleAsmParserVariant : AsmParserVariant {
133 string Name = "apple-neon";
134 string BreakCharacters = ".";
137 //===----------------------------------------------------------------------===//
139 //===----------------------------------------------------------------------===//
140 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
141 // AsmWriter bits get associated with the correct class.
142 def GenericAsmWriter : AsmWriter {
143 string AsmWriterClassName = "InstPrinter";
144 int PassSubtarget = 1;
146 bit isMCAsmWriter = 1;
149 def AppleAsmWriter : AsmWriter {
150 let AsmWriterClassName = "AppleInstPrinter";
151 int PassSubtarget = 1;
153 int isMCAsmWriter = 1;
156 //===----------------------------------------------------------------------===//
157 // Target Declaration
158 //===----------------------------------------------------------------------===//
160 def AArch64 : Target {
161 let InstructionSet = AArch64InstrInfo;
162 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
163 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];