1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
36 "Enable ARMv8 PMUv3 Performance Monitors extension">;
38 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
39 "Full FP16", [FeatureFPARMv8]>;
41 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
42 "Enable Statistical Profiling extension">;
44 /// Cyclone has register move instructions which are "free".
45 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
46 "Has zero-cycle register moves">;
48 /// Cyclone has instructions which zero registers for "free".
49 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
50 "Has zero-cycle zeroing instructions">;
52 def FeatureStrictAlign : SubtargetFeature<"strict-align",
53 "StrictAlign", "true",
54 "Disallow all unaligned memory "
57 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
58 "Reserve X18, making it unavailable "
61 //===----------------------------------------------------------------------===//
65 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
66 "Support ARM v8.1a instructions", [FeatureCRC]>;
68 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
69 "Support ARM v8.2a instructions", [HasV8_1aOps]>;
71 //===----------------------------------------------------------------------===//
72 // Register File Description
73 //===----------------------------------------------------------------------===//
75 include "AArch64RegisterInfo.td"
76 include "AArch64CallingConvention.td"
78 //===----------------------------------------------------------------------===//
79 // Instruction Descriptions
80 //===----------------------------------------------------------------------===//
82 include "AArch64Schedule.td"
83 include "AArch64InstrInfo.td"
85 def AArch64InstrInfo : InstrInfo;
87 //===----------------------------------------------------------------------===//
88 // AArch64 Processors supported.
90 include "AArch64SchedA53.td"
91 include "AArch64SchedA57.td"
92 include "AArch64SchedCyclone.td"
93 include "AArch64SchedM1.td"
95 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
96 "Cortex-A35 ARM processors",
103 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
104 "Cortex-A53 ARM processors",
111 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
112 "Cortex-A57 ARM processors",
119 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
126 FeatureZCRegMove, FeatureZCZeroing]>;
128 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
129 "Samsung Exynos-M1 processors",
136 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
141 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
142 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
143 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
144 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
145 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
146 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
147 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
148 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
150 //===----------------------------------------------------------------------===//
152 //===----------------------------------------------------------------------===//
154 def GenericAsmParserVariant : AsmParserVariant {
156 string Name = "generic";
157 string BreakCharacters = ".";
160 def AppleAsmParserVariant : AsmParserVariant {
162 string Name = "apple-neon";
163 string BreakCharacters = ".";
166 //===----------------------------------------------------------------------===//
168 //===----------------------------------------------------------------------===//
169 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
170 // AsmWriter bits get associated with the correct class.
171 def GenericAsmWriter : AsmWriter {
172 string AsmWriterClassName = "InstPrinter";
173 int PassSubtarget = 1;
175 bit isMCAsmWriter = 1;
178 def AppleAsmWriter : AsmWriter {
179 let AsmWriterClassName = "AppleInstPrinter";
180 int PassSubtarget = 1;
182 int isMCAsmWriter = 1;
185 //===----------------------------------------------------------------------===//
186 // Target Declaration
187 //===----------------------------------------------------------------------===//
189 def AArch64 : Target {
190 let InstructionSet = AArch64InstrInfo;
191 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
192 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];