lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions">;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 /// Cyclone has register move instructions which are "free".
  36 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  37                                         "Has zero-cycle register moves">;
  38
  39 /// Cyclone has instructions which zero registers for "free".
  40 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  41                                         "Has zero-cycle zeroing instructions">;
  42
  43 //===----------------------------------------------------------------------===//
  44 // Register File Description
  45 //===----------------------------------------------------------------------===//
  46
  47 include "AArch64RegisterInfo.td"
  48 include "AArch64CallingConvention.td"
  49
  50 //===----------------------------------------------------------------------===//
  51 // Instruction Descriptions
  52 //===----------------------------------------------------------------------===//
  53
  54 include "AArch64Schedule.td"
  55 include "AArch64InstrInfo.td"
  56
  57 def AArch64InstrInfo : InstrInfo;
  58
  59 //===----------------------------------------------------------------------===//
  60 // AArch64 Processors supported.
  61 //
  62 include "AArch64SchedA53.td"
  63 include "AArch64SchedA57.td"
  64 include "AArch64SchedCyclone.td"
  65
  66 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
  67                                    "Cortex-A53 ARM processors",
  68                                    [FeatureFPARMv8,
  69                                    FeatureNEON,
  70                                    FeatureCrypto,
  71                                    FeatureCRC]>;
  72
  73 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
  74                                    "Cortex-A57 ARM processors",
  75                                    [FeatureFPARMv8,
  76                                    FeatureNEON,
  77                                    FeatureCrypto,
  78                                    FeatureCRC]>;
  79
  80 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
  81                                    "Cyclone",
  82                                    [FeatureFPARMv8,
  83                                    FeatureNEON,
  84                                    FeatureCrypto,
  85                                    FeatureCRC,
  86                                    FeatureZCRegMove, FeatureZCZeroing]>;
  87
  88 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
  89                                               FeatureNEON,
  90                                               FeatureCRC]>;
  91
  92 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
  93 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
  94 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
  95 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
  96 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
  97
  98 //===----------------------------------------------------------------------===//
  99 // Assembly parser
 100 //===----------------------------------------------------------------------===//
 101
 102 def GenericAsmParserVariant : AsmParserVariant {
 103   int Variant = 0;
 104   string Name = "generic";
 105 }
 106
 107 def AppleAsmParserVariant : AsmParserVariant {
 108   int Variant = 1;
 109   string Name = "apple-neon";
 110 }
 111
 112 //===----------------------------------------------------------------------===//
 113 // Assembly printer
 114 //===----------------------------------------------------------------------===//
 115 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 116 // AsmWriter bits get associated with the correct class.
 117 def GenericAsmWriter : AsmWriter {
 118   string AsmWriterClassName  = "InstPrinter";
 119   int Variant = 0;
 120   bit isMCAsmWriter = 1;
 121 }
 122
 123 def AppleAsmWriter : AsmWriter {
 124   let AsmWriterClassName = "AppleInstPrinter";
 125   int Variant = 1;
 126   int isMCAsmWriter = 1;
 127 }
 128
 129 //===----------------------------------------------------------------------===//
 130 // Target Declaration
 131 //===----------------------------------------------------------------------===//
 132
 133 def AArch64 : Target {
 134   let InstructionSet = AArch64InstrInfo;
 135   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 136   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 137 }