1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
36 "Enable ARMv8 PMUv3 Performance Monitors extension">;
38 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
39 "Full FP16", [FeatureFPARMv8]>;
41 /// Cyclone has register move instructions which are "free".
42 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
43 "Has zero-cycle register moves">;
45 /// Cyclone has instructions which zero registers for "free".
46 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
47 "Has zero-cycle zeroing instructions">;
49 def FeatureStrictAlign : SubtargetFeature<"strict-align",
50 "StrictAlign", "true",
51 "Disallow all unaligned memory "
54 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
55 "Reserve X18, making it unavailable "
58 //===----------------------------------------------------------------------===//
62 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
63 "Support ARM v8.1a instructions", [FeatureCRC]>;
65 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
66 "Support ARM v8.2a instructions", [HasV8_1aOps]>;
68 //===----------------------------------------------------------------------===//
69 // Register File Description
70 //===----------------------------------------------------------------------===//
72 include "AArch64RegisterInfo.td"
73 include "AArch64CallingConvention.td"
75 //===----------------------------------------------------------------------===//
76 // Instruction Descriptions
77 //===----------------------------------------------------------------------===//
79 include "AArch64Schedule.td"
80 include "AArch64InstrInfo.td"
82 def AArch64InstrInfo : InstrInfo;
84 //===----------------------------------------------------------------------===//
85 // AArch64 Processors supported.
87 include "AArch64SchedA53.td"
88 include "AArch64SchedA57.td"
89 include "AArch64SchedCyclone.td"
91 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
92 "Cortex-A53 ARM processors",
99 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
100 "Cortex-A57 ARM processors",
107 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
114 FeatureZCRegMove, FeatureZCZeroing]>;
116 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
121 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
122 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
123 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
124 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
125 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
127 //===----------------------------------------------------------------------===//
129 //===----------------------------------------------------------------------===//
131 def GenericAsmParserVariant : AsmParserVariant {
133 string Name = "generic";
134 string BreakCharacters = ".";
137 def AppleAsmParserVariant : AsmParserVariant {
139 string Name = "apple-neon";
140 string BreakCharacters = ".";
143 //===----------------------------------------------------------------------===//
145 //===----------------------------------------------------------------------===//
146 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
147 // AsmWriter bits get associated with the correct class.
148 def GenericAsmWriter : AsmWriter {
149 string AsmWriterClassName = "InstPrinter";
150 int PassSubtarget = 1;
152 bit isMCAsmWriter = 1;
155 def AppleAsmWriter : AsmWriter {
156 let AsmWriterClassName = "AppleInstPrinter";
157 int PassSubtarget = 1;
159 int isMCAsmWriter = 1;
162 //===----------------------------------------------------------------------===//
163 // Target Declaration
164 //===----------------------------------------------------------------------===//
166 def AArch64 : Target {
167 let InstructionSet = AArch64InstrInfo;
168 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
169 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];