1 //===-- AArch64A53Fix835769.cpp -------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass changes code to work around Cortex-A53 erratum 835769.
10 // It works around it by inserting a nop instruction in code sequences that
11 // in some circumstances may trigger the erratum.
12 // It inserts a nop instruction between a sequence of the following 2 classes
14 // instr 1: mem-instr (including loads, stores and prefetches).
15 // instr 2: non-SIMD integer multiply-accumulate writing 64-bit X registers.
16 //===----------------------------------------------------------------------===//
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
32 #define DEBUG_TYPE "aarch64-fix-cortex-a53-835769"
34 STATISTIC(NumNopsAdded, "Number of Nops added to work around erratum 835769");
36 //===----------------------------------------------------------------------===//
39 // Is the instruction a match for the instruction that comes first in the
40 // sequence of instructions that can trigger the erratum?
41 static bool isFirstInstructionInSequence(MachineInstr *MI) {
42 // Must return true if this instruction is a load, a store or a prefetch.
43 switch (MI->getOpcode()) {
45 case AArch64::PRFMroW:
46 case AArch64::PRFMroX:
51 return MI->mayLoadOrStore();
55 // Is the instruction a match for the instruction that comes second in the
56 // sequence that can trigger the erratum?
57 static bool isSecondInstructionInSequence(MachineInstr *MI) {
58 // Must return true for non-SIMD integer multiply-accumulates, writing
59 // to a 64-bit register.
60 switch (MI->getOpcode()) {
61 // Erratum cannot be triggered when the destination register is 32 bits,
62 // therefore only include the following.
63 case AArch64::MSUBXrrr:
64 case AArch64::MADDXrrr:
65 case AArch64::SMADDLrrr:
66 case AArch64::SMSUBLrrr:
67 case AArch64::UMADDLrrr:
68 case AArch64::UMSUBLrrr:
69 // Erratum can only be triggered by multiply-adds, not by regular
70 // non-accumulating multiplies, i.e. when Ra=XZR='11111'
71 return MI->getOperand(3).getReg() != AArch64::XZR;
78 //===----------------------------------------------------------------------===//
81 class AArch64A53Fix835769 : public MachineFunctionPass {
82 const TargetInstrInfo *TII;
86 explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {}
88 bool runOnMachineFunction(MachineFunction &F) override;
90 const char *getPassName() const override {
91 return "Workaround A53 erratum 835769 pass";
94 void getAnalysisUsage(AnalysisUsage &AU) const override {
96 MachineFunctionPass::getAnalysisUsage(AU);
100 bool runOnBasicBlock(MachineBasicBlock &MBB);
102 char AArch64A53Fix835769::ID = 0;
104 } // end anonymous namespace
106 //===----------------------------------------------------------------------===//
109 AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) {
110 DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n");
111 bool Changed = false;
112 TII = F.getSubtarget().getInstrInfo();
114 for (auto &MBB : F) {
115 Changed |= runOnBasicBlock(MBB);
120 // Return the block that was fallen through to get to MBB, if any,
121 // otherwise nullptr.
122 static MachineBasicBlock *getBBFallenThrough(MachineBasicBlock *MBB,
123 const TargetInstrInfo *TII) {
124 // Get the previous machine basic block in the function.
125 MachineFunction::iterator MBBI = *MBB;
127 // Can't go off top of function.
128 if (MBBI == MBB->getParent()->begin())
131 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
132 SmallVector<MachineOperand, 2> Cond;
134 MachineBasicBlock *PrevBB = std::prev(MBBI);
135 for (MachineBasicBlock *S : MBB->predecessors())
136 if (S == PrevBB && !TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond) &&
143 // Iterate through fallen through blocks trying to find a previous non-pseudo if
144 // there is one, otherwise return nullptr. Only look for instructions in
145 // previous blocks, not the current block, since we only use this to look at
147 static MachineInstr *getLastNonPseudo(MachineBasicBlock &MBB,
148 const TargetInstrInfo *TII) {
149 MachineBasicBlock *FMBB = &MBB;
151 // If there is no non-pseudo in the current block, loop back around and try
152 // the previous block (if there is one).
153 while ((FMBB = getBBFallenThrough(FMBB, TII))) {
154 for (auto I = FMBB->rbegin(), E = FMBB->rend(); I != E; ++I) {
160 // There was no previous non-pseudo in the fallen through blocks
164 static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI,
165 const TargetInstrInfo *TII) {
166 // If we are the first instruction of the block, put the NOP at the end of
167 // the previous fallthrough block
168 if (MI == &MBB.front()) {
169 MachineInstr *I = getLastNonPseudo(MBB, TII);
170 assert(I && "Expected instruction");
171 DebugLoc DL = I->getDebugLoc();
172 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
175 DebugLoc DL = MI->getDebugLoc();
176 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
183 AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) {
184 bool Changed = false;
185 DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n");
187 // First, scan the basic block, looking for a sequence of 2 instructions
188 // that match the conditions under which the erratum may trigger.
190 // List of terminating instructions in matching sequences
191 std::vector<MachineInstr*> Sequences;
193 MachineInstr *PrevInstr = nullptr;
195 // Try and find the last non-pseudo instruction in any fallen through blocks,
196 // if there isn't one, then we use nullptr to represent that.
197 PrevInstr = getLastNonPseudo(MBB, TII);
199 for (auto &MI : MBB) {
200 MachineInstr *CurrInstr = &MI;
201 DEBUG(dbgs() << " Examining: " << MI);
203 DEBUG(dbgs() << " PrevInstr: " << *PrevInstr
204 << " CurrInstr: " << *CurrInstr
205 << " isFirstInstructionInSequence(PrevInstr): "
206 << isFirstInstructionInSequence(PrevInstr) << "\n"
207 << " isSecondInstructionInSequence(CurrInstr): "
208 << isSecondInstructionInSequence(CurrInstr) << "\n");
209 if (isFirstInstructionInSequence(PrevInstr) &&
210 isSecondInstructionInSequence(CurrInstr)) {
211 DEBUG(dbgs() << " ** pattern found at Idx " << Idx << "!\n");
212 Sequences.push_back(CurrInstr);
215 if (!CurrInstr->isPseudo())
216 PrevInstr = CurrInstr;
220 DEBUG(dbgs() << "Scan complete, "<< Sequences.size()
221 << " occurences of pattern found.\n");
223 // Then update the basic block, inserting nops between the detected sequences.
224 for (auto &MI : Sequences) {
226 insertNopBeforeInstruction(MBB, MI, TII);
232 // Factory function used by AArch64TargetMachine to add the pass to
234 FunctionPass *llvm::createAArch64A53Fix835769() {
235 return new AArch64A53Fix835769();