1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to the AArch64 assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/AArch64AddressingModes.h"
17 #include "AArch64MCInstLower.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64Subtarget.h"
21 #include "InstPrinter/AArch64InstPrinter.h"
22 #include "MCTargetDesc/AArch64MCExpr.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/AsmPrinter.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCLinkerOptimizationHint.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
45 #define DEBUG_TYPE "asm-printer"
49 class AArch64AsmPrinter : public AsmPrinter {
50 AArch64MCInstLower MCInstLowering;
54 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
55 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
56 SM(*this), AArch64FI(nullptr) {}
58 const char *getPassName() const override {
59 return "AArch64 Assembly Printer";
62 /// \brief Wrapper for MCInstLowering.lowerOperand() for the
63 /// tblgen'erated pseudo lowering.
64 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
65 return MCInstLowering.lowerOperand(MO, MCOp);
68 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
69 const MachineInstr &MI);
70 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
71 const MachineInstr &MI);
72 /// \brief tblgen'erated driver function for lowering simple MI->MC
73 /// pseudo instructions.
74 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
75 const MachineInstr *MI);
77 void EmitInstruction(const MachineInstr *MI) override;
79 void getAnalysisUsage(AnalysisUsage &AU) const override {
80 AsmPrinter::getAnalysisUsage(AU);
84 bool runOnMachineFunction(MachineFunction &F) override {
85 AArch64FI = F.getInfo<AArch64FunctionInfo>();
86 return AsmPrinter::runOnMachineFunction(F);
90 MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
91 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
92 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
93 bool printAsmRegInClass(const MachineOperand &MO,
94 const TargetRegisterClass *RC, bool isVector,
97 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
98 unsigned AsmVariant, const char *ExtraCode,
99 raw_ostream &O) override;
100 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
101 unsigned AsmVariant, const char *ExtraCode,
102 raw_ostream &O) override;
104 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
106 void EmitFunctionBodyEnd() override;
108 MCSymbol *GetCPISymbol(unsigned CPID) const override;
109 void EmitEndOfAsmFile(Module &M) override;
110 AArch64FunctionInfo *AArch64FI;
112 /// \brief Emit the LOHs contained in AArch64FI.
115 typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
116 MInstToMCSymbol LOHInstToLabel;
119 } // end of anonymous namespace
121 //===----------------------------------------------------------------------===//
123 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
124 const Triple &TT = TM.getTargetTriple();
125 if (TT.isOSBinFormatMachO()) {
126 // Funny Darwin hack: This flag tells the linker that no global symbols
127 // contain code that falls through to other global symbols (e.g. the obvious
128 // implementation of multiple entry points). If this doesn't occur, the
129 // linker can safely perform dead code stripping. Since LLVM never
130 // generates code that does this, it is always safe to set.
131 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
132 SM.serializeToStackMapSection();
137 AArch64AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
138 MachineLocation Location;
139 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
140 // Frame address. Currently handles register +- offset only.
141 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
142 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
144 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
149 void AArch64AsmPrinter::EmitLOHs() {
150 SmallVector<MCSymbol *, 3> MCArgs;
152 for (const auto &D : AArch64FI->getLOHContainer()) {
153 for (const MachineInstr *MI : D.getArgs()) {
154 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
155 assert(LabelIt != LOHInstToLabel.end() &&
156 "Label hasn't been inserted for LOH related instruction");
157 MCArgs.push_back(LabelIt->second);
159 OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
164 void AArch64AsmPrinter::EmitFunctionBodyEnd() {
165 if (!AArch64FI->getLOHRelated().empty())
169 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
170 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
171 // Darwin uses a linker-private symbol name for constant-pools (to
172 // avoid addends on the relocation?), ELF has no such concept and
173 // uses a normal private symbol.
174 if (getDataLayout().getLinkerPrivateGlobalPrefix()[0])
175 return OutContext.getOrCreateSymbol(
176 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
177 Twine(getFunctionNumber()) + "_" + Twine(CPID));
179 return OutContext.getOrCreateSymbol(
180 Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
181 Twine(getFunctionNumber()) + "_" + Twine(CPID));
184 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
186 const MachineOperand &MO = MI->getOperand(OpNum);
187 switch (MO.getType()) {
189 llvm_unreachable("<unknown operand type>");
190 case MachineOperand::MO_Register: {
191 unsigned Reg = MO.getReg();
192 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
193 assert(!MO.getSubReg() && "Subregs should be eliminated!");
194 O << AArch64InstPrinter::getRegisterName(Reg);
197 case MachineOperand::MO_Immediate: {
198 int64_t Imm = MO.getImm();
202 case MachineOperand::MO_GlobalAddress: {
203 const GlobalValue *GV = MO.getGlobal();
204 MCSymbol *Sym = getSymbol(GV);
206 // FIXME: Can we get anything other than a plain symbol here?
207 assert(!MO.getTargetFlags() && "Unknown operand target flag!");
210 printOffset(MO.getOffset(), O);
216 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
218 unsigned Reg = MO.getReg();
221 return true; // Unknown mode.
223 Reg = getWRegFromXReg(Reg);
226 Reg = getXRegFromWReg(Reg);
230 O << AArch64InstPrinter::getRegisterName(Reg);
234 // Prints the register in MO using class RC using the offset in the
235 // new register class. This should not be used for cross class
237 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
238 const TargetRegisterClass *RC,
239 bool isVector, raw_ostream &O) {
240 assert(MO.isReg() && "Should only get here with a register!");
241 const AArch64RegisterInfo *RI =
242 MF->getSubtarget<AArch64Subtarget>().getRegisterInfo();
243 unsigned Reg = MO.getReg();
244 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
245 assert(RI->regsOverlap(RegToPrint, Reg));
246 O << AArch64InstPrinter::getRegisterName(
247 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
251 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
253 const char *ExtraCode, raw_ostream &O) {
254 const MachineOperand &MO = MI->getOperand(OpNum);
256 // First try the generic code, which knows about modifiers like 'c' and 'n'.
257 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
260 // Does this asm operand have a single letter operand modifier?
261 if (ExtraCode && ExtraCode[0]) {
262 if (ExtraCode[1] != 0)
263 return true; // Unknown modifier.
265 switch (ExtraCode[0]) {
267 return true; // Unknown modifier.
268 case 'w': // Print W register
269 case 'x': // Print X register
271 return printAsmMRegister(MO, ExtraCode[0], O);
272 if (MO.isImm() && MO.getImm() == 0) {
273 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
274 O << AArch64InstPrinter::getRegisterName(Reg);
277 printOperand(MI, OpNum, O);
279 case 'b': // Print B register.
280 case 'h': // Print H register.
281 case 's': // Print S register.
282 case 'd': // Print D register.
283 case 'q': // Print Q register.
285 const TargetRegisterClass *RC;
286 switch (ExtraCode[0]) {
288 RC = &AArch64::FPR8RegClass;
291 RC = &AArch64::FPR16RegClass;
294 RC = &AArch64::FPR32RegClass;
297 RC = &AArch64::FPR64RegClass;
300 RC = &AArch64::FPR128RegClass;
305 return printAsmRegInClass(MO, RC, false /* vector */, O);
307 printOperand(MI, OpNum, O);
312 // According to ARM, we should emit x and v registers unless we have a
315 unsigned Reg = MO.getReg();
317 // If this is a w or x register, print an x register.
318 if (AArch64::GPR32allRegClass.contains(Reg) ||
319 AArch64::GPR64allRegClass.contains(Reg))
320 return printAsmMRegister(MO, 'x', O);
322 // If this is a b, h, s, d, or q register, print it as a v register.
323 return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
327 printOperand(MI, OpNum, O);
331 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
334 const char *ExtraCode,
336 if (ExtraCode && ExtraCode[0])
337 return true; // Unknown modifier.
339 const MachineOperand &MO = MI->getOperand(OpNum);
340 assert(MO.isReg() && "unexpected inline asm memory operand");
341 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
345 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
347 unsigned NOps = MI->getNumOperands();
349 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
350 // cast away const; DIetc do not take const operands for some reason.
351 OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
354 // Frame address. Currently handles register +- offset only.
355 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
357 printOperand(MI, 0, OS);
359 printOperand(MI, 1, OS);
362 printOperand(MI, NOps - 2, OS);
365 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
366 const MachineInstr &MI) {
367 unsigned NumNOPBytes = MI.getOperand(1).getImm();
369 SM.recordStackMap(MI);
370 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
372 // Scan ahead to trim the shadow.
373 const MachineBasicBlock &MBB = *MI.getParent();
374 MachineBasicBlock::const_iterator MII(MI);
376 while (NumNOPBytes > 0) {
377 if (MII == MBB.end() || MII->isCall() ||
378 MII->getOpcode() == AArch64::DBG_VALUE ||
379 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
380 MII->getOpcode() == TargetOpcode::STACKMAP)
387 for (unsigned i = 0; i < NumNOPBytes; i += 4)
388 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
391 // Lower a patchpoint of the form:
392 // [<def>], <id>, <numBytes>, <target>, <numArgs>
393 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
394 const MachineInstr &MI) {
395 SM.recordPatchPoint(MI);
397 PatchPointOpers Opers(&MI);
399 int64_t CallTarget = Opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
400 unsigned EncodedBytes = 0;
402 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
403 "High 16 bits of call target should be zero.");
404 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
406 // Materialize the jump address:
407 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZWi)
409 .addImm((CallTarget >> 32) & 0xFFFF)
411 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
414 .addImm((CallTarget >> 16) & 0xFFFF)
416 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
419 .addImm(CallTarget & 0xFFFF)
421 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
424 unsigned NumBytes = Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
425 assert(NumBytes >= EncodedBytes &&
426 "Patchpoint can't request size less than the length of a call.");
427 assert((NumBytes - EncodedBytes) % 4 == 0 &&
428 "Invalid number of NOP bytes requested!");
429 for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
430 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
433 // Simple pseudo-instructions have their lowering (with expansion to real
434 // instructions) auto-generated.
435 #include "AArch64GenMCPseudoLowering.inc"
437 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
438 // Do any auto-generated pseudo lowerings.
439 if (emitPseudoExpansionLowering(*OutStreamer, MI))
442 if (AArch64FI->getLOHRelated().count(MI)) {
443 // Generate a label for LOH related instruction
444 MCSymbol *LOHLabel = createTempSymbol("loh");
445 // Associate the instruction with the label
446 LOHInstToLabel[MI] = LOHLabel;
447 OutStreamer->EmitLabel(LOHLabel);
450 // Do any manual lowerings.
451 switch (MI->getOpcode()) {
454 case AArch64::DBG_VALUE: {
455 if (isVerbose() && OutStreamer->hasRawTextSupport()) {
456 SmallString<128> TmpStr;
457 raw_svector_ostream OS(TmpStr);
458 PrintDebugValueComment(MI, OS);
459 OutStreamer->EmitRawText(StringRef(OS.str()));
464 // Tail calls use pseudo instructions so they have the proper code-gen
465 // attributes (isCall, isReturn, etc.). We lower them to the real
467 case AArch64::TCRETURNri: {
469 TmpInst.setOpcode(AArch64::BR);
470 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
471 EmitToStreamer(*OutStreamer, TmpInst);
474 case AArch64::TCRETURNdi: {
476 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
478 TmpInst.setOpcode(AArch64::B);
479 TmpInst.addOperand(Dest);
480 EmitToStreamer(*OutStreamer, TmpInst);
483 case AArch64::TLSDESC_CALLSEQ: {
485 /// adrp x0, :tlsdesc:var
486 /// ldr x1, [x0, #:tlsdesc_lo12:var]
487 /// add x0, x0, #:tlsdesc_lo12:var
490 /// (TPIDR_EL0 offset now in x0)
491 const MachineOperand &MO_Sym = MI->getOperand(0);
492 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
493 MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
494 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
496 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
497 MCInstLowering.lowerOperand(MO_Sym, Sym);
498 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
499 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
502 Adrp.setOpcode(AArch64::ADRP);
503 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
504 Adrp.addOperand(SymTLSDesc);
505 EmitToStreamer(*OutStreamer, Adrp);
508 Ldr.setOpcode(AArch64::LDRXui);
509 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
510 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
511 Ldr.addOperand(SymTLSDescLo12);
512 Ldr.addOperand(MCOperand::createImm(0));
513 EmitToStreamer(*OutStreamer, Ldr);
516 Add.setOpcode(AArch64::ADDXri);
517 Add.addOperand(MCOperand::createReg(AArch64::X0));
518 Add.addOperand(MCOperand::createReg(AArch64::X0));
519 Add.addOperand(SymTLSDescLo12);
520 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
521 EmitToStreamer(*OutStreamer, Add);
523 // Emit a relocation-annotation. This expands to no code, but requests
524 // the following instruction gets an R_AARCH64_TLSDESC_CALL.
526 TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
527 TLSDescCall.addOperand(Sym);
528 EmitToStreamer(*OutStreamer, TLSDescCall);
531 Blr.setOpcode(AArch64::BLR);
532 Blr.addOperand(MCOperand::createReg(AArch64::X1));
533 EmitToStreamer(*OutStreamer, Blr);
538 case TargetOpcode::STACKMAP:
539 return LowerSTACKMAP(*OutStreamer, SM, *MI);
541 case TargetOpcode::PATCHPOINT:
542 return LowerPATCHPOINT(*OutStreamer, SM, *MI);
545 // Finally, do the automated lowerings for everything else.
547 MCInstLowering.Lower(MI, TmpInst);
548 EmitToStreamer(*OutStreamer, TmpInst);
551 // Force static initialization.
552 extern "C" void LLVMInitializeAArch64AsmPrinter() {
553 RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget);
554 RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget);
555 RegisterAsmPrinter<AArch64AsmPrinter> Z(TheARM64Target);