1 //=== AArch64CallingConv.h - Custom Calling Convention Routines -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the custom routines for the AArch64 Calling Convention
11 // that aren't done by tablegen.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
19 #include "AArch64InstrInfo.h"
20 #include "AArch64Subtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetInstrInfo.h"
28 static const uint16_t XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
29 AArch64::X3, AArch64::X4, AArch64::X5,
30 AArch64::X6, AArch64::X7};
31 static const uint16_t SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
32 AArch64::S3, AArch64::S4, AArch64::S5,
33 AArch64::S6, AArch64::S7};
34 static const uint16_t DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
35 AArch64::D3, AArch64::D4, AArch64::D5,
36 AArch64::D6, AArch64::D7};
37 static const uint16_t QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
38 AArch64::Q3, AArch64::Q4, AArch64::Q5,
39 AArch64::Q6, AArch64::Q7};
41 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
42 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
43 CCState &State, unsigned SlotAlign) {
44 unsigned Size = LocVT.getSizeInBits() / 8;
45 unsigned StackAlign = State.getMachineFunction()
48 ->getStackAlignment();
49 unsigned Align = std::min(ArgFlags.getOrigAlign(), StackAlign);
51 for (auto &It : PendingMembers) {
52 It.convertToMem(State.AllocateStack(Size, std::max(Align, SlotAlign)));
57 // All pending members have now been allocated
58 PendingMembers.clear();
62 /// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An
63 /// [N x Ty] type must still be contiguous in memory though.
64 static bool CC_AArch64_Custom_Stack_Block(
65 unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
66 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
67 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
69 // Add the argument to the list to be allocated once we know the size of the
71 PendingMembers.push_back(
72 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
74 if (!ArgFlags.isInConsecutiveRegsLast())
77 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8);
80 /// Given an [N x Ty] block, it should be passed in a consecutive sequence of
81 /// registers. If no such sequence is available, mark the rest of the registers
82 /// of that type as used and place the argument on the stack.
83 static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
86 // Try to allocate a contiguous block of registers, each of the correct
87 // size to hold one member.
88 ArrayRef<uint16_t> RegList;
89 if (LocVT.SimpleTy == MVT::i64)
91 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
93 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
95 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
98 // Not an array we want to split up after all.
102 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
104 // Add the argument to the list to be allocated once we know the size of the
106 PendingMembers.push_back(
107 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
109 if (!ArgFlags.isInConsecutiveRegsLast())
112 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
114 for (auto &It : PendingMembers) {
115 It.convertToReg(RegResult);
119 PendingMembers.clear();
123 // Mark all regs in the class as unavailable
124 for (auto Reg : RegList)
125 State.AllocateReg(Reg);
127 const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
128 State.getMachineFunction().getSubtarget());
129 unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;
131 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);