1 //=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for AArch64 architecture.
12 //===----------------------------------------------------------------------===//
14 /// CCIfAlign - Match of the original alignment of the arg
15 class CCIfAlign<string Align, CCAction A> :
16 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
17 /// CCIfBigEndian - Match only if we're in big endian mode.
18 class CCIfBigEndian<CCAction A> :
19 CCIf<"State.getTarget().getDataLayout()->isBigEndian()", A>;
21 //===----------------------------------------------------------------------===//
22 // ARM AAPCS64 Calling Convention
23 //===----------------------------------------------------------------------===//
25 def CC_AArch64_AAPCS : CallingConv<[
26 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
27 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
29 // Big endian vectors must be passed as if they were 1-element vectors so that
30 // their lanes are in a consistent order.
31 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
32 CCBitConvertToType<f64>>>,
33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
34 CCBitConvertToType<f128>>>,
36 // An SRet is passed in X8, not X0 like a normal pointer parameter.
37 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
39 // Put ByVal arguments directly on the stack. Minimum size and alignment of a
41 CCIfByVal<CCPassByVal<8, 8>>,
43 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
44 // up to eight each of GPR and FPR.
45 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
46 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
47 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
48 // i128 is split to two i64s, we can't fit half to register X7.
49 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
52 // i128 is split to two i64s, and its stack alignment is 16 bytes.
53 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
55 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
56 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
57 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
58 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
59 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
60 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
61 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
62 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
63 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
64 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
65 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
67 // If more than will fit in registers, pass them on the stack instead.
68 CCIfType<[i1, i8, i16], CCAssignToStack<8, 8>>,
69 CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
70 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
71 CCAssignToStack<8, 8>>,
72 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
73 CCAssignToStack<16, 16>>
76 def RetCC_AArch64_AAPCS : CallingConv<[
77 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
78 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
80 // Big endian vectors must be passed as if they were 1-element vectors so that
81 // their lanes are in a consistent order.
82 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
83 CCBitConvertToType<f64>>>,
84 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
85 CCBitConvertToType<f128>>>,
87 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
88 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
89 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
90 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
91 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
92 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
93 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
94 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
95 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
96 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
97 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
98 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
99 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
103 // Darwin uses a calling convention which differs in only two ways
104 // from the standard one at this level:
105 // + i128s (i.e. split i64s) don't need even registers.
106 // + Stack slots are sized as needed rather than being at least 64-bit.
107 def CC_AArch64_DarwinPCS : CallingConv<[
108 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
109 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
111 // An SRet is passed in X8, not X0 like a normal pointer parameter.
112 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
114 // Put ByVal arguments directly on the stack. Minimum size and alignment of a
116 CCIfByVal<CCPassByVal<8, 8>>,
118 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
119 // up to eight each of GPR and FPR.
120 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
121 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
122 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
123 // i128 is split to two i64s, we can't fit half to register X7.
125 CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6],
126 [W0, W1, W2, W3, W4, W5, W6]>>>,
127 // i128 is split to two i64s, and its stack alignment is 16 bytes.
128 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
130 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
131 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
132 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
133 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
134 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
135 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
136 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
137 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
138 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
139 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
140 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
142 // If more than will fit in registers, pass them on the stack instead.
143 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,
144 CCIf<"ValVT == MVT::i16", CCAssignToStack<2, 2>>,
145 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
146 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
147 CCAssignToStack<8, 8>>,
148 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
151 def CC_AArch64_DarwinPCS_VarArg : CallingConv<[
152 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
153 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
155 // Handle all scalar types as either i64 or f64.
156 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
157 CCIfType<[f32], CCPromoteToType<f64>>,
159 // Everything is on the stack.
160 // i128 is split to two i64s, and its stack alignment is 16 bytes.
161 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
162 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32], CCAssignToStack<8, 8>>,
163 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
166 // The WebKit_JS calling convention only passes the first argument (the callee)
167 // in register and the remaining arguments on stack. We allow 32bit stack slots,
168 // so that WebKit can write partial values in the stack and define the other
169 // 32bit quantity as undef.
170 def CC_AArch64_WebKit_JS : CallingConv<[
171 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
172 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
173 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
174 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
176 // Pass the remaining arguments on the stack instead.
177 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
178 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
181 def RetCC_AArch64_WebKit_JS : CallingConv<[
182 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
183 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
184 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
185 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
186 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
187 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
188 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
189 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
192 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
193 // presumably a callee to someone. External functions may not do so, but this
194 // is currently safe since BL has LR as an implicit-def and what happens after a
195 // tail call doesn't matter.
197 // It would be better to model its preservation semantics properly (create a
198 // vreg on entry, use it in RET & tail call generation; make that vreg def if we
199 // end up saving LR as part of a call frame). Watch this space...
200 def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
201 X23, X24, X25, X26, X27, X28,
203 D12, D13, D14, D15)>;
205 // Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
206 // 'this' and the pointer return value are both passed in X0 in these cases,
207 // this can be partially modelled by treating X0 as a callee-saved register;
208 // only the resulting RegMask is used; the SaveList is ignored
210 // (For generic ARM 64-bit ABI code, clang will not generate constructors or
211 // destructors with 'this' returns, so this RegMask will not be used in that
213 def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
215 // The function used by Darwin to obtain the address of a thread-local variable
216 // guarantees more than a normal AAPCS function. x16 and x17 are used on the
217 // fast path for calculation, but other registers except X0 (argument/return)
218 // and LR (it is a call, after all) are preserved.
219 def CSR_AArch64_TLS_Darwin
220 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
222 (sequence "Q%u", 0, 31))>;
224 // The ELF stub used for TLS-descriptor access saves every feasible
225 // register. Only X0 and LR are clobbered.
226 def CSR_AArch64_TLS_ELF
227 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
228 (sequence "Q%u", 0, 31))>;
230 def CSR_AArch64_AllRegs
231 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
232 (sequence "X%u", 0, 28), FP, LR, SP,
233 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31),
234 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
235 (sequence "Q%u", 0, 31))>;