1 //=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for AArch64 architecture.
12 //===----------------------------------------------------------------------===//
14 /// CCIfAlign - Match of the original alignment of the arg
15 class CCIfAlign<string Align, CCAction A> :
16 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
17 /// CCIfBigEndian - Match only if we're in big endian mode.
18 class CCIfBigEndian<CCAction A> :
19 CCIf<"State.getMachineFunction().getSubtarget().getDataLayout()->isBigEndian()", A>;
21 //===----------------------------------------------------------------------===//
22 // ARM AAPCS64 Calling Convention
23 //===----------------------------------------------------------------------===//
25 def CC_AArch64_AAPCS : CallingConv<[
26 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
27 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
29 // Big endian vectors must be passed as if they were 1-element vectors so that
30 // their lanes are in a consistent order.
31 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
32 CCBitConvertToType<f64>>>,
33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
34 CCBitConvertToType<f128>>>,
36 // An SRet is passed in X8, not X0 like a normal pointer parameter.
37 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
39 // Put ByVal arguments directly on the stack. Minimum size and alignment of a
41 CCIfByVal<CCPassByVal<8, 8>>,
43 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
44 // up to eight each of GPR and FPR.
45 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
46 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
47 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
48 // i128 is split to two i64s, we can't fit half to register X7.
49 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
52 // i128 is split to two i64s, and its stack alignment is 16 bytes.
53 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
55 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
56 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
57 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
58 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
59 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
60 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
61 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
62 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
63 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
64 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
65 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
66 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
67 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
69 // If more than will fit in registers, pass them on the stack instead.
70 CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
71 CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
72 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
73 CCAssignToStack<8, 8>>,
74 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
75 CCAssignToStack<16, 16>>
78 def RetCC_AArch64_AAPCS : CallingConv<[
79 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
80 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
82 // Big endian vectors must be passed as if they were 1-element vectors so that
83 // their lanes are in a consistent order.
84 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
85 CCBitConvertToType<f64>>>,
86 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
87 CCBitConvertToType<f128>>>,
89 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
90 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
91 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
92 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
93 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
94 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
95 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
96 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
97 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
98 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
99 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
100 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
101 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
102 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
103 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
107 // Darwin uses a calling convention which differs in only two ways
108 // from the standard one at this level:
109 // + i128s (i.e. split i64s) don't need even registers.
110 // + Stack slots are sized as needed rather than being at least 64-bit.
111 def CC_AArch64_DarwinPCS : CallingConv<[
112 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
113 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
115 // An SRet is passed in X8, not X0 like a normal pointer parameter.
116 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
118 // Put ByVal arguments directly on the stack. Minimum size and alignment of a
120 CCIfByVal<CCPassByVal<8, 8>>,
122 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
123 // up to eight each of GPR and FPR.
124 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
125 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
126 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
127 // i128 is split to two i64s, we can't fit half to register X7.
129 CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6],
130 [W0, W1, W2, W3, W4, W5, W6]>>>,
131 // i128 is split to two i64s, and its stack alignment is 16 bytes.
132 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
134 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
135 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
136 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
137 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
138 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
139 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
140 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
141 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
142 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
143 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
144 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
145 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
146 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
148 // If more than will fit in registers, pass them on the stack instead.
149 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,
150 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16", CCAssignToStack<2, 2>>,
151 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
152 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
153 CCAssignToStack<8, 8>>,
154 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
157 def CC_AArch64_DarwinPCS_VarArg : CallingConv<[
158 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
159 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
161 // Handle all scalar types as either i64 or f64.
162 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
163 CCIfType<[f16, f32], CCPromoteToType<f64>>,
165 // Everything is on the stack.
166 // i128 is split to two i64s, and its stack alignment is 16 bytes.
167 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
168 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32], CCAssignToStack<8, 8>>,
169 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
172 // The WebKit_JS calling convention only passes the first argument (the callee)
173 // in register and the remaining arguments on stack. We allow 32bit stack slots,
174 // so that WebKit can write partial values in the stack and define the other
175 // 32bit quantity as undef.
176 def CC_AArch64_WebKit_JS : CallingConv<[
177 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
178 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
179 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
180 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
182 // Pass the remaining arguments on the stack instead.
183 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
184 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
187 def RetCC_AArch64_WebKit_JS : CallingConv<[
188 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
189 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
190 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
191 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
192 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
193 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
194 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
195 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
198 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
199 // presumably a callee to someone. External functions may not do so, but this
200 // is currently safe since BL has LR as an implicit-def and what happens after a
201 // tail call doesn't matter.
203 // It would be better to model its preservation semantics properly (create a
204 // vreg on entry, use it in RET & tail call generation; make that vreg def if we
205 // end up saving LR as part of a call frame). Watch this space...
206 def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
207 X23, X24, X25, X26, X27, X28,
209 D12, D13, D14, D15)>;
211 // Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
212 // 'this' and the pointer return value are both passed in X0 in these cases,
213 // this can be partially modelled by treating X0 as a callee-saved register;
214 // only the resulting RegMask is used; the SaveList is ignored
216 // (For generic ARM 64-bit ABI code, clang will not generate constructors or
217 // destructors with 'this' returns, so this RegMask will not be used in that
219 def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
221 // The function used by Darwin to obtain the address of a thread-local variable
222 // guarantees more than a normal AAPCS function. x16 and x17 are used on the
223 // fast path for calculation, but other registers except X0 (argument/return)
224 // and LR (it is a call, after all) are preserved.
225 def CSR_AArch64_TLS_Darwin
226 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
228 (sequence "Q%u", 0, 31))>;
230 // The ELF stub used for TLS-descriptor access saves every feasible
231 // register. Only X0 and LR are clobbered.
232 def CSR_AArch64_TLS_ELF
233 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
234 (sequence "Q%u", 0, 31))>;
236 def CSR_AArch64_AllRegs
237 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
238 (sequence "X%u", 0, 28), FP, LR, SP,
239 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31),
240 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
241 (sequence "Q%u", 0, 31))>;