1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64TargetMachine.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64CallingConv.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/CommandLine.h"
43 class AArch64FastISel : public FastISel {
61 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
62 void setKind(BaseKind K) { Kind = K; }
63 BaseKind getKind() const { return Kind; }
64 bool isRegBase() const { return Kind == RegBase; }
65 bool isFIBase() const { return Kind == FrameIndexBase; }
66 void setReg(unsigned Reg) {
67 assert(isRegBase() && "Invalid base register access!");
70 unsigned getReg() const {
71 assert(isRegBase() && "Invalid base register access!");
74 void setFI(unsigned FI) {
75 assert(isFIBase() && "Invalid base frame index access!");
78 unsigned getFI() const {
79 assert(isFIBase() && "Invalid base frame index access!");
82 void setOffset(int64_t O) { Offset = O; }
83 int64_t getOffset() { return Offset; }
85 bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
88 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
89 /// make the right decision when generating code for different targets.
90 const AArch64Subtarget *Subtarget;
94 // Selection routines.
95 bool SelectLoad(const Instruction *I);
96 bool SelectStore(const Instruction *I);
97 bool SelectBranch(const Instruction *I);
98 bool SelectIndirectBr(const Instruction *I);
99 bool SelectCmp(const Instruction *I);
100 bool SelectSelect(const Instruction *I);
101 bool SelectFPExt(const Instruction *I);
102 bool SelectFPTrunc(const Instruction *I);
103 bool SelectFPToInt(const Instruction *I, bool Signed);
104 bool SelectIntToFP(const Instruction *I, bool Signed);
105 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
106 bool SelectCall(const Instruction *I, const char *IntrMemName);
107 bool SelectIntrinsicCall(const IntrinsicInst &I);
108 bool SelectRet(const Instruction *I);
109 bool SelectTrunc(const Instruction *I);
110 bool SelectIntExt(const Instruction *I);
111 bool SelectMul(const Instruction *I);
113 // Utility helper routines.
114 bool isTypeLegal(Type *Ty, MVT &VT);
115 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
116 bool ComputeAddress(const Value *Obj, Address &Addr);
117 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
119 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
120 unsigned Flags, bool UseUnscaled);
121 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
122 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
125 bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
126 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
127 bool UseUnscaled = false);
128 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
129 bool UseUnscaled = false);
130 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
131 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
133 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
134 unsigned AArch64MaterializeGV(const GlobalValue *GV);
136 // Call handling routines.
138 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
139 bool ProcessCallArgs(SmallVectorImpl<Value *> &Args,
140 SmallVectorImpl<unsigned> &ArgRegs,
141 SmallVectorImpl<MVT> &ArgVTs,
142 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
143 SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC,
145 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
146 const Instruction *I, CallingConv::ID CC, unsigned &NumBytes);
149 // Backend specific FastISel code.
150 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
151 unsigned TargetMaterializeConstant(const Constant *C) override;
153 explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
154 const TargetLibraryInfo *libInfo)
155 : FastISel(funcInfo, libInfo) {
156 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
157 Context = &funcInfo.Fn->getContext();
160 bool TargetSelectInstruction(const Instruction *I) override;
162 #include "AArch64GenFastISel.inc"
165 } // end anonymous namespace
167 #include "AArch64GenCallingConv.inc"
169 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
170 if (CC == CallingConv::WebKit_JS)
171 return CC_AArch64_WebKit_JS;
172 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
175 unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
176 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
177 "Alloca should always return a pointer.");
179 // Don't handle dynamic allocas.
180 if (!FuncInfo.StaticAllocaMap.count(AI))
183 DenseMap<const AllocaInst *, int>::iterator SI =
184 FuncInfo.StaticAllocaMap.find(AI);
186 if (SI != FuncInfo.StaticAllocaMap.end()) {
187 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
190 .addFrameIndex(SI->second)
199 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
200 if (VT != MVT::f32 && VT != MVT::f64)
203 const APFloat Val = CFP->getValueAPF();
204 bool is64bit = (VT == MVT::f64);
206 // This checks to see if we can use FMOV instructions to materialize
207 // a constant, otherwise we have to materialize via the constant pool.
208 if (TLI.isFPImmLegal(Val, VT)) {
212 Imm = AArch64_AM::getFP64Imm(Val);
213 Opc = AArch64::FMOVDi;
215 Imm = AArch64_AM::getFP32Imm(Val);
216 Opc = AArch64::FMOVSi;
218 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
224 // Materialize via constant pool. MachineConstantPool wants an explicit
226 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
228 Align = DL.getTypeAllocSize(CFP->getType());
230 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
231 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
233 ADRPReg).addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGE);
235 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
236 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
237 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
239 .addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
243 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
244 // We can't handle thread-local variables quickly yet. Unfortunately we have
245 // to peer through any aliases to find out if that rule applies.
246 const GlobalValue *TLSGV = GV;
247 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
248 TLSGV = GA->getAliasee();
250 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(TLSGV))
251 if (GVar->isThreadLocal())
254 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
256 EVT DestEVT = TLI.getValueType(GV->getType(), true);
257 if (!DestEVT.isSimple())
260 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
263 if (OpFlags & AArch64II::MO_GOT) {
265 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
267 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
269 ResultReg = createResultReg(&AArch64::GPR64RegClass);
270 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
273 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
278 ADRPReg).addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
280 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
281 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
284 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
290 unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
291 EVT CEVT = TLI.getValueType(C->getType(), true);
293 // Only handle simple types.
294 if (!CEVT.isSimple())
296 MVT VT = CEVT.getSimpleVT();
298 // FIXME: Handle ConstantInt.
299 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
300 return AArch64MaterializeFP(CFP, VT);
301 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
302 return AArch64MaterializeGV(GV);
307 // Computes the address to get to an object.
308 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
309 const User *U = nullptr;
310 unsigned Opcode = Instruction::UserOp1;
311 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
312 // Don't walk into other basic blocks unless the object is an alloca from
313 // another block, otherwise it may not have a virtual register assigned.
314 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
315 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
316 Opcode = I->getOpcode();
319 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
320 Opcode = C->getOpcode();
324 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
325 if (Ty->getAddressSpace() > 255)
326 // Fast instruction selection doesn't support the special
333 case Instruction::BitCast: {
334 // Look through bitcasts.
335 return ComputeAddress(U->getOperand(0), Addr);
337 case Instruction::IntToPtr: {
338 // Look past no-op inttoptrs.
339 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
340 return ComputeAddress(U->getOperand(0), Addr);
343 case Instruction::PtrToInt: {
344 // Look past no-op ptrtoints.
345 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
346 return ComputeAddress(U->getOperand(0), Addr);
349 case Instruction::GetElementPtr: {
350 Address SavedAddr = Addr;
351 uint64_t TmpOffset = Addr.getOffset();
353 // Iterate through the GEP folding the constants into offsets where
355 gep_type_iterator GTI = gep_type_begin(U);
356 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
358 const Value *Op = *i;
359 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
360 const StructLayout *SL = DL.getStructLayout(STy);
361 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
362 TmpOffset += SL->getElementOffset(Idx);
364 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
366 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
367 // Constant-offset addressing.
368 TmpOffset += CI->getSExtValue() * S;
371 if (canFoldAddIntoGEP(U, Op)) {
372 // A compatible add with a constant operand. Fold the constant.
374 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
375 TmpOffset += CI->getSExtValue() * S;
376 // Iterate on the other operand.
377 Op = cast<AddOperator>(Op)->getOperand(0);
381 goto unsupported_gep;
386 // Try to grab the base operand now.
387 Addr.setOffset(TmpOffset);
388 if (ComputeAddress(U->getOperand(0), Addr))
391 // We failed, restore everything and try the other options.
397 case Instruction::Alloca: {
398 const AllocaInst *AI = cast<AllocaInst>(Obj);
399 DenseMap<const AllocaInst *, int>::iterator SI =
400 FuncInfo.StaticAllocaMap.find(AI);
401 if (SI != FuncInfo.StaticAllocaMap.end()) {
402 Addr.setKind(Address::FrameIndexBase);
403 Addr.setFI(SI->second);
410 // Try to get this in a register if nothing else has worked.
412 Addr.setReg(getRegForValue(Obj));
413 return Addr.isValid();
416 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
417 EVT evt = TLI.getValueType(Ty, true);
419 // Only handle simple types.
420 if (evt == MVT::Other || !evt.isSimple())
422 VT = evt.getSimpleVT();
424 // This is a legal type, but it's not something we handle in fast-isel.
428 // Handle all other legal types, i.e. a register that will directly hold this
430 return TLI.isTypeLegal(VT);
433 bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
434 if (isTypeLegal(Ty, VT))
437 // If this is a type than can be sign or zero-extended to a basic operation
438 // go ahead and accept it now. For stores, this reflects truncation.
439 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
445 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
446 int64_t ScaleFactor, bool UseUnscaled) {
447 bool needsLowering = false;
448 int64_t Offset = Addr.getOffset();
449 switch (VT.SimpleTy) {
460 // Using scaled, 12-bit, unsigned immediate offsets.
461 needsLowering = ((Offset & 0xfff) != Offset);
463 // Using unscaled, 9-bit, signed immediate offsets.
464 needsLowering = (Offset > 256 || Offset < -256);
468 // FIXME: If this is a stack pointer and the offset needs to be simplified
469 // then put the alloca address into a register, set the base type back to
470 // register and continue. This should almost never happen.
471 if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
475 // Since the offset is too large for the load/store instruction get the
476 // reg+offset into a register.
478 uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
479 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
480 UnscaledOffset, MVT::i64);
483 Addr.setReg(ResultReg);
489 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
490 const MachineInstrBuilder &MIB,
491 unsigned Flags, bool UseUnscaled) {
492 int64_t Offset = Addr.getOffset();
493 // Frame base works a bit differently. Handle it separately.
494 if (Addr.getKind() == Address::FrameIndexBase) {
495 int FI = Addr.getFI();
496 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
497 // and alignment should be based on the VT.
498 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
499 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
500 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
501 // Now add the rest of the operands.
502 MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
504 // Now add the rest of the operands.
505 MIB.addReg(Addr.getReg());
510 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
512 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
513 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
514 if (!UseUnscaled && Addr.getOffset() < 0)
518 const TargetRegisterClass *RC;
520 int64_t ScaleFactor = 0;
521 switch (VT.SimpleTy) {
526 // Intentional fall-through.
528 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
529 RC = &AArch64::GPR32RegClass;
533 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
534 RC = &AArch64::GPR32RegClass;
538 Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
539 RC = &AArch64::GPR32RegClass;
543 Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
544 RC = &AArch64::GPR64RegClass;
548 Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
549 RC = TLI.getRegClassFor(VT);
553 Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
554 RC = TLI.getRegClassFor(VT);
560 int64_t Offset = Addr.getOffset();
561 if (Offset & (ScaleFactor - 1))
562 // Retry using an unscaled, 9-bit, signed immediate offset.
563 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
565 Addr.setOffset(Offset / ScaleFactor);
568 // Simplify this down to something we can handle.
569 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
572 // Create the base instruction, then add the operands.
573 ResultReg = createResultReg(RC);
574 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
575 TII.get(Opc), ResultReg);
576 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
578 // Loading an i1 requires special handling.
580 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
581 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
582 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
585 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
591 bool AArch64FastISel::SelectLoad(const Instruction *I) {
593 // Verify we have a legal type before going any further. Currently, we handle
594 // simple types that will directly fit in a register (i32/f32/i64/f64) or
595 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
596 if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
599 // See if we can handle this address.
601 if (!ComputeAddress(I->getOperand(0), Addr))
605 if (!EmitLoad(VT, ResultReg, Addr))
608 UpdateValueMap(I, ResultReg);
612 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
614 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
615 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
616 if (!UseUnscaled && Addr.getOffset() < 0)
621 int64_t ScaleFactor = 0;
622 // Using scaled, 12-bit, unsigned immediate offsets.
623 switch (VT.SimpleTy) {
629 StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
633 StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
637 StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
641 StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
645 StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
649 StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
655 int64_t Offset = Addr.getOffset();
656 if (Offset & (ScaleFactor - 1))
657 // Retry using an unscaled, 9-bit, signed immediate offset.
658 return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
660 Addr.setOffset(Offset / ScaleFactor);
663 // Simplify this down to something we can handle.
664 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
667 // Storing an i1 requires special handling.
669 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
670 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
671 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
674 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
677 // Create the base instruction, then add the operands.
678 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
679 TII.get(StrOpc)).addReg(SrcReg);
680 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
684 bool AArch64FastISel::SelectStore(const Instruction *I) {
686 Value *Op0 = I->getOperand(0);
687 // Verify we have a legal type before going any further. Currently, we handle
688 // simple types that will directly fit in a register (i32/f32/i64/f64) or
689 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
690 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
691 cast<StoreInst>(I)->isAtomic())
694 // Get the value to be stored into a register.
695 unsigned SrcReg = getRegForValue(Op0);
699 // See if we can handle this address.
701 if (!ComputeAddress(I->getOperand(1), Addr))
704 if (!EmitStore(VT, SrcReg, Addr))
709 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
711 case CmpInst::FCMP_ONE:
712 case CmpInst::FCMP_UEQ:
714 // AL is our "false" for now. The other two need more compares.
715 return AArch64CC::AL;
716 case CmpInst::ICMP_EQ:
717 case CmpInst::FCMP_OEQ:
718 return AArch64CC::EQ;
719 case CmpInst::ICMP_SGT:
720 case CmpInst::FCMP_OGT:
721 return AArch64CC::GT;
722 case CmpInst::ICMP_SGE:
723 case CmpInst::FCMP_OGE:
724 return AArch64CC::GE;
725 case CmpInst::ICMP_UGT:
726 case CmpInst::FCMP_UGT:
727 return AArch64CC::HI;
728 case CmpInst::FCMP_OLT:
729 return AArch64CC::MI;
730 case CmpInst::ICMP_ULE:
731 case CmpInst::FCMP_OLE:
732 return AArch64CC::LS;
733 case CmpInst::FCMP_ORD:
734 return AArch64CC::VC;
735 case CmpInst::FCMP_UNO:
736 return AArch64CC::VS;
737 case CmpInst::FCMP_UGE:
738 return AArch64CC::PL;
739 case CmpInst::ICMP_SLT:
740 case CmpInst::FCMP_ULT:
741 return AArch64CC::LT;
742 case CmpInst::ICMP_SLE:
743 case CmpInst::FCMP_ULE:
744 return AArch64CC::LE;
745 case CmpInst::FCMP_UNE:
746 case CmpInst::ICMP_NE:
747 return AArch64CC::NE;
748 case CmpInst::ICMP_UGE:
749 return AArch64CC::HS;
750 case CmpInst::ICMP_ULT:
751 return AArch64CC::LO;
755 bool AArch64FastISel::SelectBranch(const Instruction *I) {
756 const BranchInst *BI = cast<BranchInst>(I);
757 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
758 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
760 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
761 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
762 // We may not handle every CC for now.
763 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
764 if (CC == AArch64CC::AL)
768 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
772 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
775 FuncInfo.MBB->addSuccessor(TBB);
777 FastEmitBranch(FBB, DbgLoc);
780 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
782 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
783 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
784 unsigned CondReg = getRegForValue(TI->getOperand(0));
788 // Issue an extract_subreg to get the lower 32-bits.
789 if (SrcVT == MVT::i64)
790 CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
793 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
794 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
795 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
796 TII.get(AArch64::ANDWri), ANDReg)
798 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
799 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
800 TII.get(AArch64::SUBSWri))
806 unsigned CC = AArch64CC::NE;
807 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
811 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
814 FuncInfo.MBB->addSuccessor(TBB);
815 FastEmitBranch(FBB, DbgLoc);
818 } else if (const ConstantInt *CI =
819 dyn_cast<ConstantInt>(BI->getCondition())) {
820 uint64_t Imm = CI->getZExtValue();
821 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
824 FuncInfo.MBB->addSuccessor(Target);
828 unsigned CondReg = getRegForValue(BI->getCondition());
832 // We've been divorced from our compare! Our block was split, and
833 // now our compare lives in a predecessor block. We musn't
834 // re-compare here, as the children of the compare aren't guaranteed
835 // live across the block boundary (we *could* check for this).
836 // Regardless, the compare has been done in the predecessor block,
837 // and it left a value for us in a virtual register. Ergo, we test
838 // the one-bit value left in the virtual register.
839 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
845 unsigned CC = AArch64CC::NE;
846 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
851 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
854 FuncInfo.MBB->addSuccessor(TBB);
855 FastEmitBranch(FBB, DbgLoc);
859 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
860 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
861 unsigned AddrReg = getRegForValue(BI->getOperand(0));
865 // Emit the indirect branch.
866 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
869 // Make sure the CFG is up-to-date.
870 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
871 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
876 bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
877 Type *Ty = Src1Value->getType();
878 EVT SrcEVT = TLI.getValueType(Ty, true);
879 if (!SrcEVT.isSimple())
881 MVT SrcVT = SrcEVT.getSimpleVT();
883 // Check to see if the 2nd operand is a constant that we can encode directly
887 bool isNegativeImm = false;
888 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
889 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
890 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
891 const APInt &CIVal = ConstInt->getValue();
893 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
894 if (CIVal.isNegative()) {
895 isNegativeImm = true;
898 // FIXME: We can handle more immediates using shifts.
899 UseImm = ((Imm & 0xfff) == Imm);
901 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
902 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
903 if (ConstFP->isZero() && !ConstFP->isNegative())
910 bool needsExt = false;
911 switch (SrcVT.SimpleTy) {
918 // Intentional fall-through.
922 CmpOpc = isNegativeImm ? AArch64::ADDSWri : AArch64::SUBSWri;
924 CmpOpc = AArch64::SUBSWrr;
929 CmpOpc = isNegativeImm ? AArch64::ADDSXri : AArch64::SUBSXri;
931 CmpOpc = AArch64::SUBSXrr;
935 CmpOpc = UseImm ? AArch64::FCMPSri : AArch64::FCMPSrr;
939 CmpOpc = UseImm ? AArch64::FCMPDri : AArch64::FCMPDrr;
943 unsigned SrcReg1 = getRegForValue(Src1Value);
949 SrcReg2 = getRegForValue(Src2Value);
954 // We have i1, i8, or i16, we need to either zero extend or sign extend.
956 SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
960 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
968 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
980 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
983 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
990 bool AArch64FastISel::SelectCmp(const Instruction *I) {
991 const CmpInst *CI = cast<CmpInst>(I);
993 // We may not handle every CC for now.
994 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
995 if (CC == AArch64CC::AL)
999 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1002 // Now set a register based on the comparison.
1003 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1004 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1005 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1007 .addReg(AArch64::WZR)
1008 .addReg(AArch64::WZR)
1009 .addImm(invertedCC);
1011 UpdateValueMap(I, ResultReg);
1015 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1016 const SelectInst *SI = cast<SelectInst>(I);
1018 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1019 if (!DestEVT.isSimple())
1022 MVT DestVT = DestEVT.getSimpleVT();
1023 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1027 unsigned CondReg = getRegForValue(SI->getCondition());
1030 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1033 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1038 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1039 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1043 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1045 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
1052 switch (DestVT.SimpleTy) {
1056 SelectOpc = AArch64::CSELWr;
1059 SelectOpc = AArch64::CSELXr;
1062 SelectOpc = AArch64::FCSELSrrr;
1065 SelectOpc = AArch64::FCSELDrrr;
1069 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
1074 .addImm(AArch64CC::NE);
1076 UpdateValueMap(I, ResultReg);
1080 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1081 Value *V = I->getOperand(0);
1082 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1085 unsigned Op = getRegForValue(V);
1089 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1090 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1091 ResultReg).addReg(Op);
1092 UpdateValueMap(I, ResultReg);
1096 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1097 Value *V = I->getOperand(0);
1098 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1101 unsigned Op = getRegForValue(V);
1105 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1106 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
1107 ResultReg).addReg(Op);
1108 UpdateValueMap(I, ResultReg);
1112 // FPToUI and FPToSI
1113 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
1115 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1118 unsigned SrcReg = getRegForValue(I->getOperand(0));
1122 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1123 if (SrcVT == MVT::f128)
1127 if (SrcVT == MVT::f64) {
1129 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1131 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1134 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1136 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1138 unsigned ResultReg = createResultReg(
1139 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1142 UpdateValueMap(I, ResultReg);
1146 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
1148 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1150 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1151 "Unexpected value type.");
1153 unsigned SrcReg = getRegForValue(I->getOperand(0));
1157 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1159 // Handle sign-extension.
1160 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1162 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
1167 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1168 : &AArch64::GPR32RegClass);
1171 if (SrcVT == MVT::i64) {
1173 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1175 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1178 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1180 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1183 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1186 UpdateValueMap(I, ResultReg);
1190 bool AArch64FastISel::ProcessCallArgs(
1191 SmallVectorImpl<Value *> &Args, SmallVectorImpl<unsigned> &ArgRegs,
1192 SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1193 SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC,
1194 unsigned &NumBytes) {
1195 SmallVector<CCValAssign, 16> ArgLocs;
1196 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1197 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1199 // Get a count of how many bytes are to be pushed on the stack.
1200 NumBytes = CCInfo.getNextStackOffset();
1202 // Issue CALLSEQ_START
1203 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1204 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
1207 // Process the args.
1208 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1209 CCValAssign &VA = ArgLocs[i];
1210 unsigned Arg = ArgRegs[VA.getValNo()];
1211 MVT ArgVT = ArgVTs[VA.getValNo()];
1213 // Handle arg promotion: SExt, ZExt, AExt.
1214 switch (VA.getLocInfo()) {
1215 case CCValAssign::Full:
1217 case CCValAssign::SExt: {
1218 MVT DestVT = VA.getLocVT();
1220 Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ false);
1226 case CCValAssign::AExt:
1227 // Intentional fall-through.
1228 case CCValAssign::ZExt: {
1229 MVT DestVT = VA.getLocVT();
1231 Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ true);
1238 llvm_unreachable("Unknown arg promotion!");
1241 // Now copy/store arg to correct locations.
1242 if (VA.isRegLoc() && !VA.needsCustom()) {
1243 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1244 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1245 RegArgs.push_back(VA.getLocReg());
1246 } else if (VA.needsCustom()) {
1247 // FIXME: Handle custom args.
1250 assert(VA.isMemLoc() && "Assuming store on stack.");
1252 // Need to store on the stack.
1253 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1255 unsigned BEAlign = 0;
1256 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1257 BEAlign = 8 - ArgSize;
1260 Addr.setKind(Address::RegBase);
1261 Addr.setReg(AArch64::SP);
1262 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1264 if (!EmitStore(ArgVT, Arg, Addr))
1271 bool AArch64FastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1272 const Instruction *I, CallingConv::ID CC,
1273 unsigned &NumBytes) {
1274 // Issue CALLSEQ_END
1275 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1276 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1280 // Now the return value.
1281 if (RetVT != MVT::isVoid) {
1282 SmallVector<CCValAssign, 16> RVLocs;
1283 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1284 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
1286 // Only handle a single return value.
1287 if (RVLocs.size() != 1)
1290 // Copy all of the result registers out of their specified physreg.
1291 MVT CopyVT = RVLocs[0].getValVT();
1292 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1293 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1294 TII.get(TargetOpcode::COPY),
1295 ResultReg).addReg(RVLocs[0].getLocReg());
1296 UsedRegs.push_back(RVLocs[0].getLocReg());
1298 // Finally update the result.
1299 UpdateValueMap(I, ResultReg);
1305 bool AArch64FastISel::SelectCall(const Instruction *I,
1306 const char *IntrMemName = nullptr) {
1307 const CallInst *CI = cast<CallInst>(I);
1308 const Value *Callee = CI->getCalledValue();
1310 // Don't handle inline asm or intrinsics.
1311 if (isa<InlineAsm>(Callee))
1314 // Only handle global variable Callees.
1315 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1319 // Check the calling convention.
1320 ImmutableCallSite CS(CI);
1321 CallingConv::ID CC = CS.getCallingConv();
1323 // Let SDISel handle vararg functions.
1324 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1325 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1326 if (FTy->isVarArg())
1329 // Handle *simple* calls for now.
1331 Type *RetTy = I->getType();
1332 if (RetTy->isVoidTy())
1333 RetVT = MVT::isVoid;
1334 else if (!isTypeLegal(RetTy, RetVT))
1337 // Set up the argument vectors.
1338 SmallVector<Value *, 8> Args;
1339 SmallVector<unsigned, 8> ArgRegs;
1340 SmallVector<MVT, 8> ArgVTs;
1341 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1342 Args.reserve(CS.arg_size());
1343 ArgRegs.reserve(CS.arg_size());
1344 ArgVTs.reserve(CS.arg_size());
1345 ArgFlags.reserve(CS.arg_size());
1347 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1349 // If we're lowering a memory intrinsic instead of a regular call, skip the
1350 // last two arguments, which shouldn't be passed to the underlying function.
1351 if (IntrMemName && e - i <= 2)
1354 unsigned Arg = getRegForValue(*i);
1358 ISD::ArgFlagsTy Flags;
1359 unsigned AttrInd = i - CS.arg_begin() + 1;
1360 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1362 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1365 // FIXME: Only handle *easy* calls for now.
1366 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1367 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1368 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1369 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1373 Type *ArgTy = (*i)->getType();
1374 if (!isTypeLegal(ArgTy, ArgVT) &&
1375 !(ArgVT == MVT::i1 || ArgVT == MVT::i8 || ArgVT == MVT::i16))
1378 // We don't handle vector parameters yet.
1379 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1382 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
1383 Flags.setOrigAlign(OriginalAlignment);
1386 ArgRegs.push_back(Arg);
1387 ArgVTs.push_back(ArgVT);
1388 ArgFlags.push_back(Flags);
1391 // Handle the arguments now that we've gotten them.
1392 SmallVector<unsigned, 4> RegArgs;
1394 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1398 MachineInstrBuilder MIB;
1399 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BL));
1401 MIB.addGlobalAddress(GV, 0, 0);
1403 MIB.addExternalSymbol(IntrMemName, 0);
1405 // Add implicit physical register uses to the call.
1406 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1407 MIB.addReg(RegArgs[i], RegState::Implicit);
1409 // Add a register mask with the call-preserved registers.
1410 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1411 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
1413 // Finish off the call including any return values.
1414 SmallVector<unsigned, 4> UsedRegs;
1415 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes))
1418 // Set all unused physreg defs as dead.
1419 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1424 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
1426 return Len / Alignment <= 4;
1431 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
1432 uint64_t Len, unsigned Alignment) {
1433 // Make sure we don't bloat code by inlining very large memcpy's.
1434 if (!IsMemCpySmall(Len, Alignment))
1437 int64_t UnscaledOffset = 0;
1438 Address OrigDest = Dest;
1439 Address OrigSrc = Src;
1443 if (!Alignment || Alignment >= 8) {
1454 // Bound based on alignment.
1455 if (Len >= 4 && Alignment == 4)
1457 else if (Len >= 2 && Alignment == 2)
1466 RV = EmitLoad(VT, ResultReg, Src);
1467 assert(RV == true && "Should be able to handle this load.");
1468 RV = EmitStore(VT, ResultReg, Dest);
1469 assert(RV == true && "Should be able to handle this store.");
1472 int64_t Size = VT.getSizeInBits() / 8;
1474 UnscaledOffset += Size;
1476 // We need to recompute the unscaled offset for each iteration.
1477 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
1478 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
1484 bool AArch64FastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
1485 // FIXME: Handle more intrinsics.
1486 switch (I.getIntrinsicID()) {
1489 case Intrinsic::memcpy:
1490 case Intrinsic::memmove: {
1491 const MemTransferInst &MTI = cast<MemTransferInst>(I);
1492 // Don't handle volatile.
1493 if (MTI.isVolatile())
1496 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
1497 // we would emit dead code because we don't currently handle memmoves.
1498 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
1499 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
1500 // Small memcpy's are common enough that we want to do them without a call
1502 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
1503 unsigned Alignment = MTI.getAlignment();
1504 if (IsMemCpySmall(Len, Alignment)) {
1506 if (!ComputeAddress(MTI.getRawDest(), Dest) ||
1507 !ComputeAddress(MTI.getRawSource(), Src))
1509 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
1514 if (!MTI.getLength()->getType()->isIntegerTy(64))
1517 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
1518 // Fast instruction selection doesn't support the special
1522 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
1523 return SelectCall(&I, IntrMemName);
1525 case Intrinsic::memset: {
1526 const MemSetInst &MSI = cast<MemSetInst>(I);
1527 // Don't handle volatile.
1528 if (MSI.isVolatile())
1531 if (!MSI.getLength()->getType()->isIntegerTy(64))
1534 if (MSI.getDestAddressSpace() > 255)
1535 // Fast instruction selection doesn't support the special
1539 return SelectCall(&I, "memset");
1541 case Intrinsic::trap: {
1542 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
1550 bool AArch64FastISel::SelectRet(const Instruction *I) {
1551 const ReturnInst *Ret = cast<ReturnInst>(I);
1552 const Function &F = *I->getParent()->getParent();
1554 if (!FuncInfo.CanLowerReturn)
1560 // Build a list of return value registers.
1561 SmallVector<unsigned, 4> RetRegs;
1563 if (Ret->getNumOperands() > 0) {
1564 CallingConv::ID CC = F.getCallingConv();
1565 SmallVector<ISD::OutputArg, 4> Outs;
1566 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1568 // Analyze operands of the call, assigning locations to each operand.
1569 SmallVector<CCValAssign, 16> ValLocs;
1570 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
1572 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
1573 : RetCC_AArch64_AAPCS;
1574 CCInfo.AnalyzeReturn(Outs, RetCC);
1576 // Only handle a single return value for now.
1577 if (ValLocs.size() != 1)
1580 CCValAssign &VA = ValLocs[0];
1581 const Value *RV = Ret->getOperand(0);
1583 // Don't bother handling odd stuff for now.
1584 if (VA.getLocInfo() != CCValAssign::Full)
1586 // Only handle register returns for now.
1589 unsigned Reg = getRegForValue(RV);
1593 unsigned SrcReg = Reg + VA.getValNo();
1594 unsigned DestReg = VA.getLocReg();
1595 // Avoid a cross-class copy. This is very unlikely.
1596 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1599 EVT RVEVT = TLI.getValueType(RV->getType());
1600 if (!RVEVT.isSimple())
1603 // Vectors (of > 1 lane) in big endian need tricky handling.
1604 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
1607 MVT RVVT = RVEVT.getSimpleVT();
1608 if (RVVT == MVT::f128)
1610 MVT DestVT = VA.getValVT();
1611 // Special handling for extended integers.
1612 if (RVVT != DestVT) {
1613 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1616 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1619 bool isZExt = Outs[0].Flags.isZExt();
1620 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1627 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1629 // Add register to return instruction.
1630 RetRegs.push_back(VA.getLocReg());
1633 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1634 TII.get(AArch64::RET_ReallyLR));
1635 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1636 MIB.addReg(RetRegs[i], RegState::Implicit);
1640 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
1641 Type *DestTy = I->getType();
1642 Value *Op = I->getOperand(0);
1643 Type *SrcTy = Op->getType();
1645 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1646 EVT DestEVT = TLI.getValueType(DestTy, true);
1647 if (!SrcEVT.isSimple())
1649 if (!DestEVT.isSimple())
1652 MVT SrcVT = SrcEVT.getSimpleVT();
1653 MVT DestVT = DestEVT.getSimpleVT();
1655 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1658 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
1662 unsigned SrcReg = getRegForValue(Op);
1666 // If we're truncating from i64 to a smaller non-legal type then generate an
1667 // AND. Otherwise, we know the high bits are undefined and a truncate doesn't
1668 // generate any code.
1669 if (SrcVT == MVT::i64) {
1671 switch (DestVT.SimpleTy) {
1673 // Trunc i64 to i32 is handled by the target-independent fast-isel.
1685 // Issue an extract_subreg to get the lower 32-bits.
1686 unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
1688 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
1689 // Create the AND instruction which performs the actual truncation.
1690 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1691 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1694 .addImm(AArch64_AM::encodeLogicalImmediate(Mask, 32));
1698 UpdateValueMap(I, SrcReg);
1702 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
1703 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
1704 DestVT == MVT::i64) &&
1705 "Unexpected value type.");
1706 // Handle i8 and i16 as i32.
1707 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1711 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1712 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
1713 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1716 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1718 if (DestVT == MVT::i64) {
1719 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
1720 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
1721 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1722 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1723 TII.get(AArch64::SUBREG_TO_REG), Reg64)
1726 .addImm(AArch64::sub_32);
1731 if (DestVT == MVT::i64) {
1732 // FIXME: We're SExt i1 to i64.
1735 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1736 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
1745 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1747 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
1751 switch (SrcVT.SimpleTy) {
1755 return Emiti1Ext(SrcReg, DestVT, isZExt);
1757 if (DestVT == MVT::i64)
1758 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1760 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
1764 if (DestVT == MVT::i64)
1765 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1767 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
1771 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
1772 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1777 // Handle i8 and i16 as i32.
1778 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1780 else if (DestVT == MVT::i64) {
1781 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1782 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1783 TII.get(AArch64::SUBREG_TO_REG), Src64)
1786 .addImm(AArch64::sub_32);
1790 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1791 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1799 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
1800 // On ARM, in general, integer casts don't involve legal types; this code
1801 // handles promotable integers. The high bits for a type smaller than
1802 // the register size are assumed to be undefined.
1803 Type *DestTy = I->getType();
1804 Value *Src = I->getOperand(0);
1805 Type *SrcTy = Src->getType();
1807 bool isZExt = isa<ZExtInst>(I);
1808 unsigned SrcReg = getRegForValue(Src);
1812 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1813 EVT DestEVT = TLI.getValueType(DestTy, true);
1814 if (!SrcEVT.isSimple())
1816 if (!DestEVT.isSimple())
1819 MVT SrcVT = SrcEVT.getSimpleVT();
1820 MVT DestVT = DestEVT.getSimpleVT();
1821 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
1824 UpdateValueMap(I, ResultReg);
1828 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
1829 EVT DestEVT = TLI.getValueType(I->getType(), true);
1830 if (!DestEVT.isSimple())
1833 MVT DestVT = DestEVT.getSimpleVT();
1834 if (DestVT != MVT::i64 && DestVT != MVT::i32)
1838 bool is64bit = (DestVT == MVT::i64);
1839 switch (ISDOpcode) {
1843 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
1846 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
1849 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
1850 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1854 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1858 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
1859 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
1862 // The remainder is computed as numerator - (quotient * denominator) using the
1863 // MSUB instruction.
1864 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
1869 UpdateValueMap(I, ResultReg);
1873 bool AArch64FastISel::SelectMul(const Instruction *I) {
1874 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1875 if (!SrcEVT.isSimple())
1877 MVT SrcVT = SrcEVT.getSimpleVT();
1879 // Must be simple value type. Don't handle vectors.
1880 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1886 switch (SrcVT.SimpleTy) {
1892 ZReg = AArch64::WZR;
1893 Opc = AArch64::MADDWrrr;
1896 ZReg = AArch64::XZR;
1897 Opc = AArch64::MADDXrrr;
1901 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1905 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1909 // Create the base instruction, then add the operands.
1910 unsigned ResultReg = createResultReg(TLI.getRegClassFor(SrcVT));
1911 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1915 UpdateValueMap(I, ResultReg);
1919 bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
1920 switch (I->getOpcode()) {
1923 case Instruction::Load:
1924 return SelectLoad(I);
1925 case Instruction::Store:
1926 return SelectStore(I);
1927 case Instruction::Br:
1928 return SelectBranch(I);
1929 case Instruction::IndirectBr:
1930 return SelectIndirectBr(I);
1931 case Instruction::FCmp:
1932 case Instruction::ICmp:
1933 return SelectCmp(I);
1934 case Instruction::Select:
1935 return SelectSelect(I);
1936 case Instruction::FPExt:
1937 return SelectFPExt(I);
1938 case Instruction::FPTrunc:
1939 return SelectFPTrunc(I);
1940 case Instruction::FPToSI:
1941 return SelectFPToInt(I, /*Signed=*/true);
1942 case Instruction::FPToUI:
1943 return SelectFPToInt(I, /*Signed=*/false);
1944 case Instruction::SIToFP:
1945 return SelectIntToFP(I, /*Signed=*/true);
1946 case Instruction::UIToFP:
1947 return SelectIntToFP(I, /*Signed=*/false);
1948 case Instruction::SRem:
1949 return SelectRem(I, ISD::SREM);
1950 case Instruction::URem:
1951 return SelectRem(I, ISD::UREM);
1952 case Instruction::Call:
1953 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
1954 return SelectIntrinsicCall(*II);
1955 return SelectCall(I);
1956 case Instruction::Ret:
1957 return SelectRet(I);
1958 case Instruction::Trunc:
1959 return SelectTrunc(I);
1960 case Instruction::ZExt:
1961 case Instruction::SExt:
1962 return SelectIntExt(I);
1963 case Instruction::Mul:
1964 // FIXME: This really should be handled by the target-independent selector.
1965 return SelectMul(I);
1968 // Silence warnings.
1969 (void)&CC_AArch64_DarwinPCS_VarArg;
1973 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
1974 const TargetLibraryInfo *libInfo) {
1975 return new AArch64FastISel(funcInfo, libInfo);