1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64TargetMachine.h"
18 #include "AArch64Subtarget.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GetElementPtrTypeIterator.h"
32 #include "llvm/IR/GlobalAlias.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/CommandLine.h"
42 class AArch64FastISel : public FastISel {
60 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
61 void setKind(BaseKind K) { Kind = K; }
62 BaseKind getKind() const { return Kind; }
63 bool isRegBase() const { return Kind == RegBase; }
64 bool isFIBase() const { return Kind == FrameIndexBase; }
65 void setReg(unsigned Reg) {
66 assert(isRegBase() && "Invalid base register access!");
69 unsigned getReg() const {
70 assert(isRegBase() && "Invalid base register access!");
73 void setFI(unsigned FI) {
74 assert(isFIBase() && "Invalid base frame index access!");
77 unsigned getFI() const {
78 assert(isFIBase() && "Invalid base frame index access!");
81 void setOffset(int64_t O) { Offset = O; }
82 int64_t getOffset() { return Offset; }
84 bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
87 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
88 /// make the right decision when generating code for different targets.
89 const AArch64Subtarget *Subtarget;
93 // Selection routines.
94 bool SelectLoad(const Instruction *I);
95 bool SelectStore(const Instruction *I);
96 bool SelectBranch(const Instruction *I);
97 bool SelectIndirectBr(const Instruction *I);
98 bool SelectCmp(const Instruction *I);
99 bool SelectSelect(const Instruction *I);
100 bool SelectFPExt(const Instruction *I);
101 bool SelectFPTrunc(const Instruction *I);
102 bool SelectFPToInt(const Instruction *I, bool Signed);
103 bool SelectIntToFP(const Instruction *I, bool Signed);
104 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
105 bool SelectCall(const Instruction *I, const char *IntrMemName);
106 bool SelectIntrinsicCall(const IntrinsicInst &I);
107 bool SelectRet(const Instruction *I);
108 bool SelectTrunc(const Instruction *I);
109 bool SelectIntExt(const Instruction *I);
110 bool SelectMul(const Instruction *I);
112 // Utility helper routines.
113 bool isTypeLegal(Type *Ty, MVT &VT);
114 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
115 bool ComputeAddress(const Value *Obj, Address &Addr);
116 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
118 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
119 unsigned Flags, bool UseUnscaled);
120 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
121 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
124 bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
126 bool UseUnscaled = false);
127 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
128 bool UseUnscaled = false);
129 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
130 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
132 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
133 unsigned AArch64MaterializeGV(const GlobalValue *GV);
135 // Call handling routines.
137 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
138 bool ProcessCallArgs(SmallVectorImpl<Value *> &Args,
139 SmallVectorImpl<unsigned> &ArgRegs,
140 SmallVectorImpl<MVT> &ArgVTs,
141 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
142 SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC,
144 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
145 const Instruction *I, CallingConv::ID CC, unsigned &NumBytes);
148 // Backend specific FastISel code.
149 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
150 unsigned TargetMaterializeConstant(const Constant *C) override;
152 explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
153 const TargetLibraryInfo *libInfo)
154 : FastISel(funcInfo, libInfo) {
155 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
156 Context = &funcInfo.Fn->getContext();
159 bool TargetSelectInstruction(const Instruction *I) override;
161 #include "AArch64GenFastISel.inc"
164 } // end anonymous namespace
166 #include "AArch64GenCallingConv.inc"
168 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
169 if (CC == CallingConv::WebKit_JS)
170 return CC_AArch64_WebKit_JS;
171 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
174 unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
175 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
176 "Alloca should always return a pointer.");
178 // Don't handle dynamic allocas.
179 if (!FuncInfo.StaticAllocaMap.count(AI))
182 DenseMap<const AllocaInst *, int>::iterator SI =
183 FuncInfo.StaticAllocaMap.find(AI);
185 if (SI != FuncInfo.StaticAllocaMap.end()) {
186 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
189 .addFrameIndex(SI->second)
198 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
199 if (VT != MVT::f32 && VT != MVT::f64)
202 const APFloat Val = CFP->getValueAPF();
203 bool is64bit = (VT == MVT::f64);
205 // This checks to see if we can use FMOV instructions to materialize
206 // a constant, otherwise we have to materialize via the constant pool.
207 if (TLI.isFPImmLegal(Val, VT)) {
211 Imm = AArch64_AM::getFP64Imm(Val);
212 Opc = AArch64::FMOVDi;
214 Imm = AArch64_AM::getFP32Imm(Val);
215 Opc = AArch64::FMOVSi;
217 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
223 // Materialize via constant pool. MachineConstantPool wants an explicit
225 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
227 Align = DL.getTypeAllocSize(CFP->getType());
229 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
230 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
232 ADRPReg).addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGE);
234 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
238 .addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
242 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
243 // We can't handle thread-local variables quickly yet.
244 if (GV->isThreadLocal())
247 // MachO still uses GOT for large code-model accesses, but ELF requires
248 // movz/movk sequences, which FastISel doesn't handle yet.
249 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
252 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
254 EVT DestEVT = TLI.getValueType(GV->getType(), true);
255 if (!DestEVT.isSimple())
258 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
261 if (OpFlags & AArch64II::MO_GOT) {
263 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
265 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
267 ResultReg = createResultReg(&AArch64::GPR64RegClass);
268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
271 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
275 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
276 ADRPReg).addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
278 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
279 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
282 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
288 unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
289 EVT CEVT = TLI.getValueType(C->getType(), true);
291 // Only handle simple types.
292 if (!CEVT.isSimple())
294 MVT VT = CEVT.getSimpleVT();
296 // FIXME: Handle ConstantInt.
297 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
298 return AArch64MaterializeFP(CFP, VT);
299 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
300 return AArch64MaterializeGV(GV);
305 // Computes the address to get to an object.
306 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
307 const User *U = nullptr;
308 unsigned Opcode = Instruction::UserOp1;
309 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
310 // Don't walk into other basic blocks unless the object is an alloca from
311 // another block, otherwise it may not have a virtual register assigned.
312 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
313 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
314 Opcode = I->getOpcode();
317 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
318 Opcode = C->getOpcode();
322 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
323 if (Ty->getAddressSpace() > 255)
324 // Fast instruction selection doesn't support the special
331 case Instruction::BitCast: {
332 // Look through bitcasts.
333 return ComputeAddress(U->getOperand(0), Addr);
335 case Instruction::IntToPtr: {
336 // Look past no-op inttoptrs.
337 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
338 return ComputeAddress(U->getOperand(0), Addr);
341 case Instruction::PtrToInt: {
342 // Look past no-op ptrtoints.
343 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
344 return ComputeAddress(U->getOperand(0), Addr);
347 case Instruction::GetElementPtr: {
348 Address SavedAddr = Addr;
349 uint64_t TmpOffset = Addr.getOffset();
351 // Iterate through the GEP folding the constants into offsets where
353 gep_type_iterator GTI = gep_type_begin(U);
354 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
356 const Value *Op = *i;
357 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
358 const StructLayout *SL = DL.getStructLayout(STy);
359 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
360 TmpOffset += SL->getElementOffset(Idx);
362 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
364 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
365 // Constant-offset addressing.
366 TmpOffset += CI->getSExtValue() * S;
369 if (canFoldAddIntoGEP(U, Op)) {
370 // A compatible add with a constant operand. Fold the constant.
372 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
373 TmpOffset += CI->getSExtValue() * S;
374 // Iterate on the other operand.
375 Op = cast<AddOperator>(Op)->getOperand(0);
379 goto unsupported_gep;
384 // Try to grab the base operand now.
385 Addr.setOffset(TmpOffset);
386 if (ComputeAddress(U->getOperand(0), Addr))
389 // We failed, restore everything and try the other options.
395 case Instruction::Alloca: {
396 const AllocaInst *AI = cast<AllocaInst>(Obj);
397 DenseMap<const AllocaInst *, int>::iterator SI =
398 FuncInfo.StaticAllocaMap.find(AI);
399 if (SI != FuncInfo.StaticAllocaMap.end()) {
400 Addr.setKind(Address::FrameIndexBase);
401 Addr.setFI(SI->second);
408 // Try to get this in a register if nothing else has worked.
410 Addr.setReg(getRegForValue(Obj));
411 return Addr.isValid();
414 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
415 EVT evt = TLI.getValueType(Ty, true);
417 // Only handle simple types.
418 if (evt == MVT::Other || !evt.isSimple())
420 VT = evt.getSimpleVT();
422 // This is a legal type, but it's not something we handle in fast-isel.
426 // Handle all other legal types, i.e. a register that will directly hold this
428 return TLI.isTypeLegal(VT);
431 bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
432 if (isTypeLegal(Ty, VT))
435 // If this is a type than can be sign or zero-extended to a basic operation
436 // go ahead and accept it now. For stores, this reflects truncation.
437 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
443 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
444 int64_t ScaleFactor, bool UseUnscaled) {
445 bool needsLowering = false;
446 int64_t Offset = Addr.getOffset();
447 switch (VT.SimpleTy) {
458 // Using scaled, 12-bit, unsigned immediate offsets.
459 needsLowering = ((Offset & 0xfff) != Offset);
461 // Using unscaled, 9-bit, signed immediate offsets.
462 needsLowering = (Offset > 256 || Offset < -256);
466 // FIXME: If this is a stack pointer and the offset needs to be simplified
467 // then put the alloca address into a register, set the base type back to
468 // register and continue. This should almost never happen.
469 if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
473 // Since the offset is too large for the load/store instruction get the
474 // reg+offset into a register.
476 uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
477 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
478 UnscaledOffset, MVT::i64);
481 Addr.setReg(ResultReg);
487 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
488 const MachineInstrBuilder &MIB,
489 unsigned Flags, bool UseUnscaled) {
490 int64_t Offset = Addr.getOffset();
491 // Frame base works a bit differently. Handle it separately.
492 if (Addr.getKind() == Address::FrameIndexBase) {
493 int FI = Addr.getFI();
494 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
495 // and alignment should be based on the VT.
496 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
497 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
498 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
499 // Now add the rest of the operands.
500 MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
502 // Now add the rest of the operands.
503 MIB.addReg(Addr.getReg());
508 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
510 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
511 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
512 if (!UseUnscaled && Addr.getOffset() < 0)
516 const TargetRegisterClass *RC;
518 int64_t ScaleFactor = 0;
519 switch (VT.SimpleTy) {
524 // Intentional fall-through.
526 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
527 RC = &AArch64::GPR32RegClass;
531 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
532 RC = &AArch64::GPR32RegClass;
536 Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
537 RC = &AArch64::GPR32RegClass;
541 Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
542 RC = &AArch64::GPR64RegClass;
546 Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
547 RC = TLI.getRegClassFor(VT);
551 Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
552 RC = TLI.getRegClassFor(VT);
558 int64_t Offset = Addr.getOffset();
559 if (Offset & (ScaleFactor - 1))
560 // Retry using an unscaled, 9-bit, signed immediate offset.
561 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
563 Addr.setOffset(Offset / ScaleFactor);
566 // Simplify this down to something we can handle.
567 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
570 // Create the base instruction, then add the operands.
571 ResultReg = createResultReg(RC);
572 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
573 TII.get(Opc), ResultReg);
574 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
576 // Loading an i1 requires special handling.
578 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
579 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
580 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
583 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
589 bool AArch64FastISel::SelectLoad(const Instruction *I) {
591 // Verify we have a legal type before going any further. Currently, we handle
592 // simple types that will directly fit in a register (i32/f32/i64/f64) or
593 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
594 if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
597 // See if we can handle this address.
599 if (!ComputeAddress(I->getOperand(0), Addr))
603 if (!EmitLoad(VT, ResultReg, Addr))
606 UpdateValueMap(I, ResultReg);
610 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
612 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
613 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
614 if (!UseUnscaled && Addr.getOffset() < 0)
619 int64_t ScaleFactor = 0;
620 // Using scaled, 12-bit, unsigned immediate offsets.
621 switch (VT.SimpleTy) {
627 StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
631 StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
635 StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
639 StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
643 StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
647 StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
653 int64_t Offset = Addr.getOffset();
654 if (Offset & (ScaleFactor - 1))
655 // Retry using an unscaled, 9-bit, signed immediate offset.
656 return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
658 Addr.setOffset(Offset / ScaleFactor);
661 // Simplify this down to something we can handle.
662 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
665 // Storing an i1 requires special handling.
667 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
668 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
672 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
675 // Create the base instruction, then add the operands.
676 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
677 TII.get(StrOpc)).addReg(SrcReg);
678 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
682 bool AArch64FastISel::SelectStore(const Instruction *I) {
684 Value *Op0 = I->getOperand(0);
685 // Verify we have a legal type before going any further. Currently, we handle
686 // simple types that will directly fit in a register (i32/f32/i64/f64) or
687 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
688 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
689 cast<StoreInst>(I)->isAtomic())
692 // Get the value to be stored into a register.
693 unsigned SrcReg = getRegForValue(Op0);
697 // See if we can handle this address.
699 if (!ComputeAddress(I->getOperand(1), Addr))
702 if (!EmitStore(VT, SrcReg, Addr))
707 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
709 case CmpInst::FCMP_ONE:
710 case CmpInst::FCMP_UEQ:
712 // AL is our "false" for now. The other two need more compares.
713 return AArch64CC::AL;
714 case CmpInst::ICMP_EQ:
715 case CmpInst::FCMP_OEQ:
716 return AArch64CC::EQ;
717 case CmpInst::ICMP_SGT:
718 case CmpInst::FCMP_OGT:
719 return AArch64CC::GT;
720 case CmpInst::ICMP_SGE:
721 case CmpInst::FCMP_OGE:
722 return AArch64CC::GE;
723 case CmpInst::ICMP_UGT:
724 case CmpInst::FCMP_UGT:
725 return AArch64CC::HI;
726 case CmpInst::FCMP_OLT:
727 return AArch64CC::MI;
728 case CmpInst::ICMP_ULE:
729 case CmpInst::FCMP_OLE:
730 return AArch64CC::LS;
731 case CmpInst::FCMP_ORD:
732 return AArch64CC::VC;
733 case CmpInst::FCMP_UNO:
734 return AArch64CC::VS;
735 case CmpInst::FCMP_UGE:
736 return AArch64CC::PL;
737 case CmpInst::ICMP_SLT:
738 case CmpInst::FCMP_ULT:
739 return AArch64CC::LT;
740 case CmpInst::ICMP_SLE:
741 case CmpInst::FCMP_ULE:
742 return AArch64CC::LE;
743 case CmpInst::FCMP_UNE:
744 case CmpInst::ICMP_NE:
745 return AArch64CC::NE;
746 case CmpInst::ICMP_UGE:
747 return AArch64CC::HS;
748 case CmpInst::ICMP_ULT:
749 return AArch64CC::LO;
753 bool AArch64FastISel::SelectBranch(const Instruction *I) {
754 const BranchInst *BI = cast<BranchInst>(I);
755 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
756 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
758 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
759 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
760 // We may not handle every CC for now.
761 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
762 if (CC == AArch64CC::AL)
766 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
770 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
773 FuncInfo.MBB->addSuccessor(TBB);
775 FastEmitBranch(FBB, DbgLoc);
778 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
780 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
781 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
782 unsigned CondReg = getRegForValue(TI->getOperand(0));
786 // Issue an extract_subreg to get the lower 32-bits.
787 if (SrcVT == MVT::i64)
788 CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
791 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
792 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
793 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
794 TII.get(AArch64::ANDWri), ANDReg)
796 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
797 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
798 TII.get(AArch64::SUBSWri))
804 unsigned CC = AArch64CC::NE;
805 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
809 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
812 FuncInfo.MBB->addSuccessor(TBB);
813 FastEmitBranch(FBB, DbgLoc);
816 } else if (const ConstantInt *CI =
817 dyn_cast<ConstantInt>(BI->getCondition())) {
818 uint64_t Imm = CI->getZExtValue();
819 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
820 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
822 FuncInfo.MBB->addSuccessor(Target);
826 unsigned CondReg = getRegForValue(BI->getCondition());
830 // We've been divorced from our compare! Our block was split, and
831 // now our compare lives in a predecessor block. We musn't
832 // re-compare here, as the children of the compare aren't guaranteed
833 // live across the block boundary (we *could* check for this).
834 // Regardless, the compare has been done in the predecessor block,
835 // and it left a value for us in a virtual register. Ergo, we test
836 // the one-bit value left in the virtual register.
837 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
843 unsigned CC = AArch64CC::NE;
844 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
852 FuncInfo.MBB->addSuccessor(TBB);
853 FastEmitBranch(FBB, DbgLoc);
857 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
858 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
859 unsigned AddrReg = getRegForValue(BI->getOperand(0));
863 // Emit the indirect branch.
864 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
867 // Make sure the CFG is up-to-date.
868 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
869 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
874 bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
875 Type *Ty = Src1Value->getType();
876 EVT SrcEVT = TLI.getValueType(Ty, true);
877 if (!SrcEVT.isSimple())
879 MVT SrcVT = SrcEVT.getSimpleVT();
881 // Check to see if the 2nd operand is a constant that we can encode directly
885 bool isNegativeImm = false;
886 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
887 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
888 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
889 const APInt &CIVal = ConstInt->getValue();
891 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
892 if (CIVal.isNegative()) {
893 isNegativeImm = true;
896 // FIXME: We can handle more immediates using shifts.
897 UseImm = ((Imm & 0xfff) == Imm);
899 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
900 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
901 if (ConstFP->isZero() && !ConstFP->isNegative())
908 bool needsExt = false;
909 switch (SrcVT.SimpleTy) {
916 // Intentional fall-through.
920 CmpOpc = isNegativeImm ? AArch64::ADDSWri : AArch64::SUBSWri;
922 CmpOpc = AArch64::SUBSWrr;
927 CmpOpc = isNegativeImm ? AArch64::ADDSXri : AArch64::SUBSXri;
929 CmpOpc = AArch64::SUBSXrr;
933 CmpOpc = UseImm ? AArch64::FCMPSri : AArch64::FCMPSrr;
937 CmpOpc = UseImm ? AArch64::FCMPDri : AArch64::FCMPDrr;
941 unsigned SrcReg1 = getRegForValue(Src1Value);
947 SrcReg2 = getRegForValue(Src2Value);
952 // We have i1, i8, or i16, we need to either zero extend or sign extend.
954 SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
958 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
966 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
972 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
981 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
988 bool AArch64FastISel::SelectCmp(const Instruction *I) {
989 const CmpInst *CI = cast<CmpInst>(I);
991 // We may not handle every CC for now.
992 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
993 if (CC == AArch64CC::AL)
997 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1000 // Now set a register based on the comparison.
1001 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1002 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1005 .addReg(AArch64::WZR)
1006 .addReg(AArch64::WZR)
1007 .addImm(invertedCC);
1009 UpdateValueMap(I, ResultReg);
1013 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1014 const SelectInst *SI = cast<SelectInst>(I);
1016 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1017 if (!DestEVT.isSimple())
1020 MVT DestVT = DestEVT.getSimpleVT();
1021 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1025 unsigned CondReg = getRegForValue(SI->getCondition());
1028 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1031 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1036 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1037 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1038 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1041 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1043 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
1050 switch (DestVT.SimpleTy) {
1054 SelectOpc = AArch64::CSELWr;
1057 SelectOpc = AArch64::CSELXr;
1060 SelectOpc = AArch64::FCSELSrrr;
1063 SelectOpc = AArch64::FCSELDrrr;
1067 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1068 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
1072 .addImm(AArch64CC::NE);
1074 UpdateValueMap(I, ResultReg);
1078 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1079 Value *V = I->getOperand(0);
1080 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1083 unsigned Op = getRegForValue(V);
1087 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1088 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1089 ResultReg).addReg(Op);
1090 UpdateValueMap(I, ResultReg);
1094 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1095 Value *V = I->getOperand(0);
1096 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1099 unsigned Op = getRegForValue(V);
1103 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1104 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
1105 ResultReg).addReg(Op);
1106 UpdateValueMap(I, ResultReg);
1110 // FPToUI and FPToSI
1111 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
1113 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1116 unsigned SrcReg = getRegForValue(I->getOperand(0));
1120 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1121 if (SrcVT == MVT::f128)
1125 if (SrcVT == MVT::f64) {
1127 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1129 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1132 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1134 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1136 unsigned ResultReg = createResultReg(
1137 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1140 UpdateValueMap(I, ResultReg);
1144 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
1146 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1148 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1149 "Unexpected value type.");
1151 unsigned SrcReg = getRegForValue(I->getOperand(0));
1155 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1157 // Handle sign-extension.
1158 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1160 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
1165 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1166 : &AArch64::GPR32RegClass);
1169 if (SrcVT == MVT::i64) {
1171 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1173 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1176 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1178 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1181 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1184 UpdateValueMap(I, ResultReg);
1188 bool AArch64FastISel::ProcessCallArgs(
1189 SmallVectorImpl<Value *> &Args, SmallVectorImpl<unsigned> &ArgRegs,
1190 SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1191 SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC,
1192 unsigned &NumBytes) {
1193 SmallVector<CCValAssign, 16> ArgLocs;
1194 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1195 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1197 // Get a count of how many bytes are to be pushed on the stack.
1198 NumBytes = CCInfo.getNextStackOffset();
1200 // Issue CALLSEQ_START
1201 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
1205 // Process the args.
1206 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1207 CCValAssign &VA = ArgLocs[i];
1208 unsigned Arg = ArgRegs[VA.getValNo()];
1209 MVT ArgVT = ArgVTs[VA.getValNo()];
1211 // Handle arg promotion: SExt, ZExt, AExt.
1212 switch (VA.getLocInfo()) {
1213 case CCValAssign::Full:
1215 case CCValAssign::SExt: {
1216 MVT DestVT = VA.getLocVT();
1218 Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ false);
1223 case CCValAssign::AExt:
1224 // Intentional fall-through.
1225 case CCValAssign::ZExt: {
1226 MVT DestVT = VA.getLocVT();
1228 Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ true);
1234 llvm_unreachable("Unknown arg promotion!");
1237 // Now copy/store arg to correct locations.
1238 if (VA.isRegLoc() && !VA.needsCustom()) {
1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1240 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1241 RegArgs.push_back(VA.getLocReg());
1242 } else if (VA.needsCustom()) {
1243 // FIXME: Handle custom args.
1246 assert(VA.isMemLoc() && "Assuming store on stack.");
1248 // Need to store on the stack.
1249 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
1251 unsigned BEAlign = 0;
1252 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1253 BEAlign = 8 - ArgSize;
1256 Addr.setKind(Address::RegBase);
1257 Addr.setReg(AArch64::SP);
1258 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1260 if (!EmitStore(ArgVT, Arg, Addr))
1267 bool AArch64FastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1268 const Instruction *I, CallingConv::ID CC,
1269 unsigned &NumBytes) {
1270 // Issue CALLSEQ_END
1271 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1272 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1276 // Now the return value.
1277 if (RetVT != MVT::isVoid) {
1278 SmallVector<CCValAssign, 16> RVLocs;
1279 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1280 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
1282 // Only handle a single return value.
1283 if (RVLocs.size() != 1)
1286 // Copy all of the result registers out of their specified physreg.
1287 MVT CopyVT = RVLocs[0].getValVT();
1288 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1290 TII.get(TargetOpcode::COPY),
1291 ResultReg).addReg(RVLocs[0].getLocReg());
1292 UsedRegs.push_back(RVLocs[0].getLocReg());
1294 // Finally update the result.
1295 UpdateValueMap(I, ResultReg);
1301 bool AArch64FastISel::SelectCall(const Instruction *I,
1302 const char *IntrMemName = nullptr) {
1303 const CallInst *CI = cast<CallInst>(I);
1304 const Value *Callee = CI->getCalledValue();
1306 // Don't handle inline asm or intrinsics.
1307 if (isa<InlineAsm>(Callee))
1310 // Only handle global variable Callees.
1311 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1315 // Check the calling convention.
1316 ImmutableCallSite CS(CI);
1317 CallingConv::ID CC = CS.getCallingConv();
1319 // Let SDISel handle vararg functions.
1320 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1321 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1322 if (FTy->isVarArg())
1325 // Handle *simple* calls for now.
1327 Type *RetTy = I->getType();
1328 if (RetTy->isVoidTy())
1329 RetVT = MVT::isVoid;
1330 else if (!isTypeLegal(RetTy, RetVT))
1333 // Set up the argument vectors.
1334 SmallVector<Value *, 8> Args;
1335 SmallVector<unsigned, 8> ArgRegs;
1336 SmallVector<MVT, 8> ArgVTs;
1337 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1338 Args.reserve(CS.arg_size());
1339 ArgRegs.reserve(CS.arg_size());
1340 ArgVTs.reserve(CS.arg_size());
1341 ArgFlags.reserve(CS.arg_size());
1343 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1345 // If we're lowering a memory intrinsic instead of a regular call, skip the
1346 // last two arguments, which shouldn't be passed to the underlying function.
1347 if (IntrMemName && e - i <= 2)
1350 unsigned Arg = getRegForValue(*i);
1354 ISD::ArgFlagsTy Flags;
1355 unsigned AttrInd = i - CS.arg_begin() + 1;
1356 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1358 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1361 // FIXME: Only handle *easy* calls for now.
1362 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1363 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1364 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1365 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1369 Type *ArgTy = (*i)->getType();
1370 if (!isTypeLegal(ArgTy, ArgVT) &&
1371 !(ArgVT == MVT::i1 || ArgVT == MVT::i8 || ArgVT == MVT::i16))
1374 // We don't handle vector parameters yet.
1375 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1378 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
1379 Flags.setOrigAlign(OriginalAlignment);
1382 ArgRegs.push_back(Arg);
1383 ArgVTs.push_back(ArgVT);
1384 ArgFlags.push_back(Flags);
1387 // Handle the arguments now that we've gotten them.
1388 SmallVector<unsigned, 4> RegArgs;
1390 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1394 MachineInstrBuilder MIB;
1395 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BL));
1397 MIB.addGlobalAddress(GV, 0, 0);
1399 MIB.addExternalSymbol(IntrMemName, 0);
1401 // Add implicit physical register uses to the call.
1402 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1403 MIB.addReg(RegArgs[i], RegState::Implicit);
1405 // Add a register mask with the call-preserved registers.
1406 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1407 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
1409 // Finish off the call including any return values.
1410 SmallVector<unsigned, 4> UsedRegs;
1411 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes))
1414 // Set all unused physreg defs as dead.
1415 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1420 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
1422 return Len / Alignment <= 4;
1427 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
1428 uint64_t Len, unsigned Alignment) {
1429 // Make sure we don't bloat code by inlining very large memcpy's.
1430 if (!IsMemCpySmall(Len, Alignment))
1433 int64_t UnscaledOffset = 0;
1434 Address OrigDest = Dest;
1435 Address OrigSrc = Src;
1439 if (!Alignment || Alignment >= 8) {
1450 // Bound based on alignment.
1451 if (Len >= 4 && Alignment == 4)
1453 else if (Len >= 2 && Alignment == 2)
1462 RV = EmitLoad(VT, ResultReg, Src);
1463 assert(RV == true && "Should be able to handle this load.");
1464 RV = EmitStore(VT, ResultReg, Dest);
1465 assert(RV == true && "Should be able to handle this store.");
1468 int64_t Size = VT.getSizeInBits() / 8;
1470 UnscaledOffset += Size;
1472 // We need to recompute the unscaled offset for each iteration.
1473 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
1474 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
1480 bool AArch64FastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
1481 // FIXME: Handle more intrinsics.
1482 switch (I.getIntrinsicID()) {
1485 case Intrinsic::memcpy:
1486 case Intrinsic::memmove: {
1487 const MemTransferInst &MTI = cast<MemTransferInst>(I);
1488 // Don't handle volatile.
1489 if (MTI.isVolatile())
1492 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
1493 // we would emit dead code because we don't currently handle memmoves.
1494 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
1495 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
1496 // Small memcpy's are common enough that we want to do them without a call
1498 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
1499 unsigned Alignment = MTI.getAlignment();
1500 if (IsMemCpySmall(Len, Alignment)) {
1502 if (!ComputeAddress(MTI.getRawDest(), Dest) ||
1503 !ComputeAddress(MTI.getRawSource(), Src))
1505 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
1510 if (!MTI.getLength()->getType()->isIntegerTy(64))
1513 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
1514 // Fast instruction selection doesn't support the special
1518 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
1519 return SelectCall(&I, IntrMemName);
1521 case Intrinsic::memset: {
1522 const MemSetInst &MSI = cast<MemSetInst>(I);
1523 // Don't handle volatile.
1524 if (MSI.isVolatile())
1527 if (!MSI.getLength()->getType()->isIntegerTy(64))
1530 if (MSI.getDestAddressSpace() > 255)
1531 // Fast instruction selection doesn't support the special
1535 return SelectCall(&I, "memset");
1537 case Intrinsic::trap: {
1538 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
1546 bool AArch64FastISel::SelectRet(const Instruction *I) {
1547 const ReturnInst *Ret = cast<ReturnInst>(I);
1548 const Function &F = *I->getParent()->getParent();
1550 if (!FuncInfo.CanLowerReturn)
1556 // Build a list of return value registers.
1557 SmallVector<unsigned, 4> RetRegs;
1559 if (Ret->getNumOperands() > 0) {
1560 CallingConv::ID CC = F.getCallingConv();
1561 SmallVector<ISD::OutputArg, 4> Outs;
1562 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1564 // Analyze operands of the call, assigning locations to each operand.
1565 SmallVector<CCValAssign, 16> ValLocs;
1566 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
1568 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
1569 : RetCC_AArch64_AAPCS;
1570 CCInfo.AnalyzeReturn(Outs, RetCC);
1572 // Only handle a single return value for now.
1573 if (ValLocs.size() != 1)
1576 CCValAssign &VA = ValLocs[0];
1577 const Value *RV = Ret->getOperand(0);
1579 // Don't bother handling odd stuff for now.
1580 if (VA.getLocInfo() != CCValAssign::Full)
1582 // Only handle register returns for now.
1585 unsigned Reg = getRegForValue(RV);
1589 unsigned SrcReg = Reg + VA.getValNo();
1590 unsigned DestReg = VA.getLocReg();
1591 // Avoid a cross-class copy. This is very unlikely.
1592 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1595 EVT RVEVT = TLI.getValueType(RV->getType());
1596 if (!RVEVT.isSimple())
1599 // Vectors (of > 1 lane) in big endian need tricky handling.
1600 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
1603 MVT RVVT = RVEVT.getSimpleVT();
1604 if (RVVT == MVT::f128)
1606 MVT DestVT = VA.getValVT();
1607 // Special handling for extended integers.
1608 if (RVVT != DestVT) {
1609 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1612 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1615 bool isZExt = Outs[0].Flags.isZExt();
1616 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1622 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1623 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1625 // Add register to return instruction.
1626 RetRegs.push_back(VA.getLocReg());
1629 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1630 TII.get(AArch64::RET_ReallyLR));
1631 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1632 MIB.addReg(RetRegs[i], RegState::Implicit);
1636 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
1637 Type *DestTy = I->getType();
1638 Value *Op = I->getOperand(0);
1639 Type *SrcTy = Op->getType();
1641 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1642 EVT DestEVT = TLI.getValueType(DestTy, true);
1643 if (!SrcEVT.isSimple())
1645 if (!DestEVT.isSimple())
1648 MVT SrcVT = SrcEVT.getSimpleVT();
1649 MVT DestVT = DestEVT.getSimpleVT();
1651 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1654 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
1658 unsigned SrcReg = getRegForValue(Op);
1662 // If we're truncating from i64 to a smaller non-legal type then generate an
1663 // AND. Otherwise, we know the high bits are undefined and a truncate doesn't
1664 // generate any code.
1665 if (SrcVT == MVT::i64) {
1667 switch (DestVT.SimpleTy) {
1669 // Trunc i64 to i32 is handled by the target-independent fast-isel.
1681 // Issue an extract_subreg to get the lower 32-bits.
1682 unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
1684 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
1685 // Create the AND instruction which performs the actual truncation.
1686 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1687 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1690 .addImm(AArch64_AM::encodeLogicalImmediate(Mask, 32));
1694 UpdateValueMap(I, SrcReg);
1698 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
1699 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
1700 DestVT == MVT::i64) &&
1701 "Unexpected value type.");
1702 // Handle i8 and i16 as i32.
1703 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1707 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1708 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
1709 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1712 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1714 if (DestVT == MVT::i64) {
1715 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
1716 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
1717 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1718 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1719 TII.get(AArch64::SUBREG_TO_REG), Reg64)
1722 .addImm(AArch64::sub_32);
1727 if (DestVT == MVT::i64) {
1728 // FIXME: We're SExt i1 to i64.
1731 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1732 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
1741 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1743 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
1747 switch (SrcVT.SimpleTy) {
1751 return Emiti1Ext(SrcReg, DestVT, isZExt);
1753 if (DestVT == MVT::i64)
1754 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1756 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
1760 if (DestVT == MVT::i64)
1761 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1763 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
1767 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
1768 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1773 // Handle i8 and i16 as i32.
1774 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1776 else if (DestVT == MVT::i64) {
1777 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1778 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1779 TII.get(AArch64::SUBREG_TO_REG), Src64)
1782 .addImm(AArch64::sub_32);
1786 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1787 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1795 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
1796 // On ARM, in general, integer casts don't involve legal types; this code
1797 // handles promotable integers. The high bits for a type smaller than
1798 // the register size are assumed to be undefined.
1799 Type *DestTy = I->getType();
1800 Value *Src = I->getOperand(0);
1801 Type *SrcTy = Src->getType();
1803 bool isZExt = isa<ZExtInst>(I);
1804 unsigned SrcReg = getRegForValue(Src);
1808 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1809 EVT DestEVT = TLI.getValueType(DestTy, true);
1810 if (!SrcEVT.isSimple())
1812 if (!DestEVT.isSimple())
1815 MVT SrcVT = SrcEVT.getSimpleVT();
1816 MVT DestVT = DestEVT.getSimpleVT();
1817 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
1820 UpdateValueMap(I, ResultReg);
1824 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
1825 EVT DestEVT = TLI.getValueType(I->getType(), true);
1826 if (!DestEVT.isSimple())
1829 MVT DestVT = DestEVT.getSimpleVT();
1830 if (DestVT != MVT::i64 && DestVT != MVT::i32)
1834 bool is64bit = (DestVT == MVT::i64);
1835 switch (ISDOpcode) {
1839 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
1842 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
1845 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
1846 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1850 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1854 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
1855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
1858 // The remainder is computed as numerator - (quotient * denominator) using the
1859 // MSUB instruction.
1860 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1861 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
1865 UpdateValueMap(I, ResultReg);
1869 bool AArch64FastISel::SelectMul(const Instruction *I) {
1870 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1871 if (!SrcEVT.isSimple())
1873 MVT SrcVT = SrcEVT.getSimpleVT();
1875 // Must be simple value type. Don't handle vectors.
1876 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1882 switch (SrcVT.SimpleTy) {
1888 ZReg = AArch64::WZR;
1889 Opc = AArch64::MADDWrrr;
1892 ZReg = AArch64::XZR;
1893 Opc = AArch64::MADDXrrr;
1897 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1901 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1905 // Create the base instruction, then add the operands.
1906 unsigned ResultReg = createResultReg(TLI.getRegClassFor(SrcVT));
1907 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1911 UpdateValueMap(I, ResultReg);
1915 bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
1916 switch (I->getOpcode()) {
1919 case Instruction::Load:
1920 return SelectLoad(I);
1921 case Instruction::Store:
1922 return SelectStore(I);
1923 case Instruction::Br:
1924 return SelectBranch(I);
1925 case Instruction::IndirectBr:
1926 return SelectIndirectBr(I);
1927 case Instruction::FCmp:
1928 case Instruction::ICmp:
1929 return SelectCmp(I);
1930 case Instruction::Select:
1931 return SelectSelect(I);
1932 case Instruction::FPExt:
1933 return SelectFPExt(I);
1934 case Instruction::FPTrunc:
1935 return SelectFPTrunc(I);
1936 case Instruction::FPToSI:
1937 return SelectFPToInt(I, /*Signed=*/true);
1938 case Instruction::FPToUI:
1939 return SelectFPToInt(I, /*Signed=*/false);
1940 case Instruction::SIToFP:
1941 return SelectIntToFP(I, /*Signed=*/true);
1942 case Instruction::UIToFP:
1943 return SelectIntToFP(I, /*Signed=*/false);
1944 case Instruction::SRem:
1945 return SelectRem(I, ISD::SREM);
1946 case Instruction::URem:
1947 return SelectRem(I, ISD::UREM);
1948 case Instruction::Call:
1949 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
1950 return SelectIntrinsicCall(*II);
1951 return SelectCall(I);
1952 case Instruction::Ret:
1953 return SelectRet(I);
1954 case Instruction::Trunc:
1955 return SelectTrunc(I);
1956 case Instruction::ZExt:
1957 case Instruction::SExt:
1958 return SelectIntExt(I);
1959 case Instruction::Mul:
1960 // FIXME: This really should be handled by the target-independent selector.
1961 return SelectMul(I);
1964 // Silence warnings.
1965 (void)&CC_AArch64_DarwinPCS_VarArg;
1969 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
1970 const TargetLibraryInfo *libInfo) {
1971 return new AArch64FastISel(funcInfo, libInfo);