1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/CommandLine.h"
43 class AArch64FastISel : public FastISel {
53 AArch64_AM::ShiftExtendType ExtType;
61 const GlobalValue *GV;
64 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
65 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
66 void setKind(BaseKind K) { Kind = K; }
67 BaseKind getKind() const { return Kind; }
68 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
69 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
70 bool isRegBase() const { return Kind == RegBase; }
71 bool isFIBase() const { return Kind == FrameIndexBase; }
72 void setReg(unsigned Reg) {
73 assert(isRegBase() && "Invalid base register access!");
76 unsigned getReg() const {
77 assert(isRegBase() && "Invalid base register access!");
80 void setOffsetReg(unsigned Reg) {
81 assert(isRegBase() && "Invalid offset register access!");
84 unsigned getOffsetReg() const {
85 assert(isRegBase() && "Invalid offset register access!");
88 void setFI(unsigned FI) {
89 assert(isFIBase() && "Invalid base frame index access!");
92 unsigned getFI() const {
93 assert(isFIBase() && "Invalid base frame index access!");
96 void setOffset(int64_t O) { Offset = O; }
97 int64_t getOffset() { return Offset; }
98 void setShift(unsigned S) { Shift = S; }
99 unsigned getShift() { return Shift; }
101 void setGlobalValue(const GlobalValue *G) { GV = G; }
102 const GlobalValue *getGlobalValue() { return GV; }
105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
106 /// make the right decision when generating code for different targets.
107 const AArch64Subtarget *Subtarget;
108 LLVMContext *Context;
110 bool fastLowerArguments() override;
111 bool fastLowerCall(CallLoweringInfo &CLI) override;
112 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
115 // Selection routines.
116 bool selectAddSub(const Instruction *I);
117 bool selectLogicalOp(const Instruction *I);
118 bool SelectLoad(const Instruction *I);
119 bool SelectStore(const Instruction *I);
120 bool SelectBranch(const Instruction *I);
121 bool SelectIndirectBr(const Instruction *I);
122 bool SelectCmp(const Instruction *I);
123 bool SelectSelect(const Instruction *I);
124 bool SelectFPExt(const Instruction *I);
125 bool SelectFPTrunc(const Instruction *I);
126 bool SelectFPToInt(const Instruction *I, bool Signed);
127 bool SelectIntToFP(const Instruction *I, bool Signed);
128 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
129 bool SelectRet(const Instruction *I);
130 bool SelectTrunc(const Instruction *I);
131 bool SelectIntExt(const Instruction *I);
132 bool SelectMul(const Instruction *I);
133 bool SelectShift(const Instruction *I);
134 bool SelectBitCast(const Instruction *I);
136 // Utility helper routines.
137 bool isTypeLegal(Type *Ty, MVT &VT);
138 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
139 bool isValueAvailable(const Value *V) const;
140 bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
141 bool ComputeCallAddress(const Value *V, Address &Addr);
142 bool SimplifyAddress(Address &Addr, MVT VT);
143 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
144 unsigned Flags, unsigned ScaleFactor,
145 MachineMemOperand *MMO);
146 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
147 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
149 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
152 // Emit helper routines.
153 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
154 const Value *RHS, bool SetFlags = false,
155 bool WantResult = true, bool IsZExt = false);
156 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
157 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
158 bool SetFlags = false, bool WantResult = true);
159 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
160 bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
161 bool WantResult = true);
162 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
163 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
164 AArch64_AM::ShiftExtendType ShiftType,
165 uint64_t ShiftImm, bool SetFlags = false,
166 bool WantResult = true);
167 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
168 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
169 AArch64_AM::ShiftExtendType ExtType,
170 uint64_t ShiftImm, bool SetFlags = false,
171 bool WantResult = true);
174 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
175 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
176 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
177 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
178 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
179 MachineMemOperand *MMO = nullptr);
180 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
181 MachineMemOperand *MMO = nullptr);
182 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
183 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
184 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
185 bool SetFlags = false, bool WantResult = true,
186 bool IsZExt = false);
187 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
188 bool SetFlags = false, bool WantResult = true,
189 bool IsZExt = false);
190 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
191 unsigned RHSReg, bool RHSIsKill, bool WantResult = true);
192 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
193 unsigned RHSReg, bool RHSIsKill,
194 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
195 bool WantResult = true);
196 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
198 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
199 bool LHSIsKill, uint64_t Imm);
200 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
201 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
203 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
204 unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
205 unsigned Op1, bool Op1IsKill);
206 unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
207 unsigned Op1, bool Op1IsKill);
208 unsigned Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
209 unsigned Op1, bool Op1IsKill);
210 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
211 unsigned Op1Reg, bool Op1IsKill);
212 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
213 uint64_t Imm, bool IsZExt = true);
214 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
215 unsigned Op1Reg, bool Op1IsKill);
216 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
217 uint64_t Imm, bool IsZExt = true);
218 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219 unsigned Op1Reg, bool Op1IsKill);
220 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221 uint64_t Imm, bool IsZExt = false);
223 unsigned AArch64MaterializeInt(const ConstantInt *CI, MVT VT);
224 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
225 unsigned AArch64MaterializeGV(const GlobalValue *GV);
227 // Call handling routines.
229 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
230 bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
232 bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
235 // Backend specific FastISel code.
236 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
237 unsigned fastMaterializeConstant(const Constant *C) override;
238 unsigned fastMaterializeFloatZero(const ConstantFP* CF) override;
240 explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
241 const TargetLibraryInfo *LibInfo)
242 : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
243 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
244 Context = &FuncInfo.Fn->getContext();
247 bool fastSelectInstruction(const Instruction *I) override;
249 #include "AArch64GenFastISel.inc"
252 } // end anonymous namespace
254 #include "AArch64GenCallingConv.inc"
256 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
257 if (CC == CallingConv::WebKit_JS)
258 return CC_AArch64_WebKit_JS;
259 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
262 unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
263 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
264 "Alloca should always return a pointer.");
266 // Don't handle dynamic allocas.
267 if (!FuncInfo.StaticAllocaMap.count(AI))
270 DenseMap<const AllocaInst *, int>::iterator SI =
271 FuncInfo.StaticAllocaMap.find(AI);
273 if (SI != FuncInfo.StaticAllocaMap.end()) {
274 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
275 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
277 .addFrameIndex(SI->second)
286 unsigned AArch64FastISel::AArch64MaterializeInt(const ConstantInt *CI, MVT VT) {
291 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
293 // Create a copy from the zero register to materialize a "0" value.
294 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
295 : &AArch64::GPR32RegClass;
296 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
297 unsigned ResultReg = createResultReg(RC);
298 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
299 ResultReg).addReg(ZeroReg, getKillRegState(true));
303 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
304 // Positive zero (+0.0) has to be materialized with a fmov from the zero
305 // register, because the immediate version of fmov cannot encode zero.
306 if (CFP->isNullValue())
307 return fastMaterializeFloatZero(CFP);
309 if (VT != MVT::f32 && VT != MVT::f64)
312 const APFloat Val = CFP->getValueAPF();
313 bool Is64Bit = (VT == MVT::f64);
314 // This checks to see if we can use FMOV instructions to materialize
315 // a constant, otherwise we have to materialize via the constant pool.
316 if (TLI.isFPImmLegal(Val, VT)) {
318 Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
319 assert((Imm != -1) && "Cannot encode floating-point constant.");
320 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
321 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
324 // Materialize via constant pool. MachineConstantPool wants an explicit
326 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
328 Align = DL.getTypeAllocSize(CFP->getType());
330 unsigned CPI = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
331 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
332 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
333 ADRPReg).addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGE);
335 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui;
336 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
339 .addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
343 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
344 // We can't handle thread-local variables quickly yet.
345 if (GV->isThreadLocal())
348 // MachO still uses GOT for large code-model accesses, but ELF requires
349 // movz/movk sequences, which FastISel doesn't handle yet.
350 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
353 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
355 EVT DestEVT = TLI.getValueType(GV->getType(), true);
356 if (!DestEVT.isSimple())
359 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
362 if (OpFlags & AArch64II::MO_GOT) {
364 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
366 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
368 ResultReg = createResultReg(&AArch64::GPR64RegClass);
369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
372 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
374 } else if (OpFlags & AArch64II::MO_CONSTPOOL) {
375 // We can't handle addresses loaded from a constant pool quickly yet.
379 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
381 .addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
383 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
384 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
387 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
393 unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
394 EVT CEVT = TLI.getValueType(C->getType(), true);
396 // Only handle simple types.
397 if (!CEVT.isSimple())
399 MVT VT = CEVT.getSimpleVT();
401 if (const auto *CI = dyn_cast<ConstantInt>(C))
402 return AArch64MaterializeInt(CI, VT);
403 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
404 return AArch64MaterializeFP(CFP, VT);
405 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
406 return AArch64MaterializeGV(GV);
411 unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
412 assert(CFP->isNullValue() &&
413 "Floating-point constant is not a positive zero.");
415 if (!isTypeLegal(CFP->getType(), VT))
418 if (VT != MVT::f32 && VT != MVT::f64)
421 bool Is64Bit = (VT == MVT::f64);
422 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
423 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
424 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
427 // Computes the address to get to an object.
428 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
430 const User *U = nullptr;
431 unsigned Opcode = Instruction::UserOp1;
432 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
433 // Don't walk into other basic blocks unless the object is an alloca from
434 // another block, otherwise it may not have a virtual register assigned.
435 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
436 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
437 Opcode = I->getOpcode();
440 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
441 Opcode = C->getOpcode();
445 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
446 if (Ty->getAddressSpace() > 255)
447 // Fast instruction selection doesn't support the special
454 case Instruction::BitCast: {
455 // Look through bitcasts.
456 return ComputeAddress(U->getOperand(0), Addr, Ty);
458 case Instruction::IntToPtr: {
459 // Look past no-op inttoptrs.
460 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
461 return ComputeAddress(U->getOperand(0), Addr, Ty);
464 case Instruction::PtrToInt: {
465 // Look past no-op ptrtoints.
466 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
467 return ComputeAddress(U->getOperand(0), Addr, Ty);
470 case Instruction::GetElementPtr: {
471 Address SavedAddr = Addr;
472 uint64_t TmpOffset = Addr.getOffset();
474 // Iterate through the GEP folding the constants into offsets where
476 gep_type_iterator GTI = gep_type_begin(U);
477 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
479 const Value *Op = *i;
480 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
481 const StructLayout *SL = DL.getStructLayout(STy);
482 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
483 TmpOffset += SL->getElementOffset(Idx);
485 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
487 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
488 // Constant-offset addressing.
489 TmpOffset += CI->getSExtValue() * S;
492 if (canFoldAddIntoGEP(U, Op)) {
493 // A compatible add with a constant operand. Fold the constant.
495 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
496 TmpOffset += CI->getSExtValue() * S;
497 // Iterate on the other operand.
498 Op = cast<AddOperator>(Op)->getOperand(0);
502 goto unsupported_gep;
507 // Try to grab the base operand now.
508 Addr.setOffset(TmpOffset);
509 if (ComputeAddress(U->getOperand(0), Addr, Ty))
512 // We failed, restore everything and try the other options.
518 case Instruction::Alloca: {
519 const AllocaInst *AI = cast<AllocaInst>(Obj);
520 DenseMap<const AllocaInst *, int>::iterator SI =
521 FuncInfo.StaticAllocaMap.find(AI);
522 if (SI != FuncInfo.StaticAllocaMap.end()) {
523 Addr.setKind(Address::FrameIndexBase);
524 Addr.setFI(SI->second);
529 case Instruction::Add: {
530 // Adds of constants are common and easy enough.
531 const Value *LHS = U->getOperand(0);
532 const Value *RHS = U->getOperand(1);
534 if (isa<ConstantInt>(LHS))
537 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
538 Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
539 return ComputeAddress(LHS, Addr, Ty);
542 Address Backup = Addr;
543 if (ComputeAddress(LHS, Addr, Ty) && ComputeAddress(RHS, Addr, Ty))
549 case Instruction::Shl:
550 if (Addr.getOffsetReg())
553 if (const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
554 unsigned Val = CI->getZExtValue();
555 if (Val < 1 || Val > 3)
558 uint64_t NumBytes = 0;
559 if (Ty && Ty->isSized()) {
560 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
561 NumBytes = NumBits / 8;
562 if (!isPowerOf2_64(NumBits))
566 if (NumBytes != (1ULL << Val))
570 Addr.setExtendType(AArch64_AM::LSL);
572 if (const auto *I = dyn_cast<Instruction>(U->getOperand(0)))
573 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
576 if (const auto *ZE = dyn_cast<ZExtInst>(U))
577 if (ZE->getOperand(0)->getType()->isIntegerTy(32))
578 Addr.setExtendType(AArch64_AM::UXTW);
580 if (const auto *SE = dyn_cast<SExtInst>(U))
581 if (SE->getOperand(0)->getType()->isIntegerTy(32))
582 Addr.setExtendType(AArch64_AM::SXTW);
584 unsigned Reg = getRegForValue(U->getOperand(0));
587 Addr.setOffsetReg(Reg);
594 if (!Addr.getOffsetReg()) {
595 unsigned Reg = getRegForValue(Obj);
598 Addr.setOffsetReg(Reg);
604 unsigned Reg = getRegForValue(Obj);
611 bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
612 const User *U = nullptr;
613 unsigned Opcode = Instruction::UserOp1;
616 if (const auto *I = dyn_cast<Instruction>(V)) {
617 Opcode = I->getOpcode();
619 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
620 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
621 Opcode = C->getOpcode();
627 case Instruction::BitCast:
628 // Look past bitcasts if its operand is in the same BB.
630 return ComputeCallAddress(U->getOperand(0), Addr);
632 case Instruction::IntToPtr:
633 // Look past no-op inttoptrs if its operand is in the same BB.
635 TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
636 return ComputeCallAddress(U->getOperand(0), Addr);
638 case Instruction::PtrToInt:
639 // Look past no-op ptrtoints if its operand is in the same BB.
641 TLI.getValueType(U->getType()) == TLI.getPointerTy())
642 return ComputeCallAddress(U->getOperand(0), Addr);
646 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
647 Addr.setGlobalValue(GV);
651 // If all else fails, try to materialize the value in a register.
652 if (!Addr.getGlobalValue()) {
653 Addr.setReg(getRegForValue(V));
654 return Addr.getReg() != 0;
661 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
662 EVT evt = TLI.getValueType(Ty, true);
664 // Only handle simple types.
665 if (evt == MVT::Other || !evt.isSimple())
667 VT = evt.getSimpleVT();
669 // This is a legal type, but it's not something we handle in fast-isel.
673 // Handle all other legal types, i.e. a register that will directly hold this
675 return TLI.isTypeLegal(VT);
678 /// \brief Determine if the value type is supported by FastISel.
680 /// FastISel for AArch64 can handle more value types than are legal. This adds
681 /// simple value type such as i1, i8, and i16.
682 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
683 if (Ty->isVectorTy() && !IsVectorAllowed)
686 if (isTypeLegal(Ty, VT))
689 // If this is a type than can be sign or zero-extended to a basic operation
690 // go ahead and accept it now.
691 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
697 bool AArch64FastISel::isValueAvailable(const Value *V) const {
698 if (!isa<Instruction>(V))
701 const auto *I = cast<Instruction>(V);
702 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
708 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
709 unsigned ScaleFactor;
710 switch (VT.SimpleTy) {
711 default: return false;
712 case MVT::i1: // fall-through
713 case MVT::i8: ScaleFactor = 1; break;
714 case MVT::i16: ScaleFactor = 2; break;
715 case MVT::i32: // fall-through
716 case MVT::f32: ScaleFactor = 4; break;
717 case MVT::i64: // fall-through
718 case MVT::f64: ScaleFactor = 8; break;
721 bool ImmediateOffsetNeedsLowering = false;
722 bool RegisterOffsetNeedsLowering = false;
723 int64_t Offset = Addr.getOffset();
724 if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
725 ImmediateOffsetNeedsLowering = true;
726 else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
727 !isUInt<12>(Offset / ScaleFactor))
728 ImmediateOffsetNeedsLowering = true;
730 // Cannot encode an offset register and an immediate offset in the same
731 // instruction. Fold the immediate offset into the load/store instruction and
732 // emit an additonal add to take care of the offset register.
733 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.isRegBase() &&
735 RegisterOffsetNeedsLowering = true;
737 // Cannot encode zero register as base.
738 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())
739 RegisterOffsetNeedsLowering = true;
741 // If this is a stack pointer and the offset needs to be simplified then put
742 // the alloca address into a register, set the base type back to register and
743 // continue. This should almost never happen.
744 if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
745 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
746 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
748 .addFrameIndex(Addr.getFI())
751 Addr.setKind(Address::RegBase);
752 Addr.setReg(ResultReg);
755 if (RegisterOffsetNeedsLowering) {
756 unsigned ResultReg = 0;
758 if (Addr.getExtendType() == AArch64_AM::SXTW ||
759 Addr.getExtendType() == AArch64_AM::UXTW )
760 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
761 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
762 /*TODO:IsKill=*/false, Addr.getExtendType(),
765 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
766 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
767 /*TODO:IsKill=*/false, AArch64_AM::LSL,
770 if (Addr.getExtendType() == AArch64_AM::UXTW)
771 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
772 /*Op0IsKill=*/false, Addr.getShift(),
774 else if (Addr.getExtendType() == AArch64_AM::SXTW)
775 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
776 /*Op0IsKill=*/false, Addr.getShift(),
779 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
780 /*Op0IsKill=*/false, Addr.getShift());
785 Addr.setReg(ResultReg);
786 Addr.setOffsetReg(0);
788 Addr.setExtendType(AArch64_AM::InvalidShiftExtend);
791 // Since the offset is too large for the load/store instruction get the
792 // reg+offset into a register.
793 if (ImmediateOffsetNeedsLowering) {
794 unsigned ResultReg = 0;
796 ResultReg = fastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(),
797 /*IsKill=*/false, Offset, MVT::i64);
799 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
803 Addr.setReg(ResultReg);
809 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
810 const MachineInstrBuilder &MIB,
812 unsigned ScaleFactor,
813 MachineMemOperand *MMO) {
814 int64_t Offset = Addr.getOffset() / ScaleFactor;
815 // Frame base works a bit differently. Handle it separately.
816 if (Addr.isFIBase()) {
817 int FI = Addr.getFI();
818 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
819 // and alignment should be based on the VT.
820 MMO = FuncInfo.MF->getMachineMemOperand(
821 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
822 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
823 // Now add the rest of the operands.
824 MIB.addFrameIndex(FI).addImm(Offset);
826 assert(Addr.isRegBase() && "Unexpected address kind.");
827 const MCInstrDesc &II = MIB->getDesc();
828 unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
830 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
832 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
833 if (Addr.getOffsetReg()) {
834 assert(Addr.getOffset() == 0 && "Unexpected offset");
835 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
836 Addr.getExtendType() == AArch64_AM::SXTX;
837 MIB.addReg(Addr.getReg());
838 MIB.addReg(Addr.getOffsetReg());
839 MIB.addImm(IsSigned);
840 MIB.addImm(Addr.getShift() != 0);
842 MIB.addReg(Addr.getReg());
848 MIB.addMemOperand(MMO);
851 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
852 const Value *RHS, bool SetFlags,
853 bool WantResult, bool IsZExt) {
854 AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
855 bool NeedExtend = false;
856 switch (RetVT.SimpleTy) {
864 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
868 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
870 case MVT::i32: // fall-through
875 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
877 // Canonicalize immediates to the RHS first.
878 if (UseAdd && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
881 // Canonicalize shift immediate to the RHS.
882 if (UseAdd && isValueAvailable(LHS))
883 if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
884 if (isa<ConstantInt>(SI->getOperand(1)))
885 if (SI->getOpcode() == Instruction::Shl ||
886 SI->getOpcode() == Instruction::LShr ||
887 SI->getOpcode() == Instruction::AShr )
890 unsigned LHSReg = getRegForValue(LHS);
893 bool LHSIsKill = hasTrivialKill(LHS);
896 LHSReg = EmitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
898 unsigned ResultReg = 0;
899 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
900 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
902 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
903 SetFlags, WantResult);
905 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
911 // Only extend the RHS within the instruction if there is a valid extend type.
912 if (ExtendType != AArch64_AM::InvalidShiftExtend && isValueAvailable(RHS)) {
913 if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
914 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
915 if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
916 unsigned RHSReg = getRegForValue(SI->getOperand(0));
919 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
920 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
921 RHSIsKill, ExtendType, C->getZExtValue(),
922 SetFlags, WantResult);
924 unsigned RHSReg = getRegForValue(RHS);
927 bool RHSIsKill = hasTrivialKill(RHS);
928 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
929 ExtendType, 0, SetFlags, WantResult);
932 // Check if the shift can be folded into the instruction.
933 if (isValueAvailable(RHS))
934 if (const auto *SI = dyn_cast<BinaryOperator>(RHS)) {
935 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
936 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend;
937 switch (SI->getOpcode()) {
939 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
940 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
941 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break;
943 uint64_t ShiftVal = C->getZExtValue();
944 if (ShiftType != AArch64_AM::InvalidShiftExtend) {
945 unsigned RHSReg = getRegForValue(SI->getOperand(0));
948 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
949 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
950 RHSIsKill, ShiftType, ShiftVal, SetFlags,
956 unsigned RHSReg = getRegForValue(RHS);
959 bool RHSIsKill = hasTrivialKill(RHS);
962 RHSReg = EmitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
964 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
965 SetFlags, WantResult);
968 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
969 bool LHSIsKill, unsigned RHSReg,
970 bool RHSIsKill, bool SetFlags,
972 assert(LHSReg && RHSReg && "Invalid register number.");
974 if (RetVT != MVT::i32 && RetVT != MVT::i64)
977 static const unsigned OpcTable[2][2][2] = {
978 { { AArch64::SUBWrr, AArch64::SUBXrr },
979 { AArch64::ADDWrr, AArch64::ADDXrr } },
980 { { AArch64::SUBSWrr, AArch64::SUBSXrr },
981 { AArch64::ADDSWrr, AArch64::ADDSXrr } }
983 bool Is64Bit = RetVT == MVT::i64;
984 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
985 const TargetRegisterClass *RC =
986 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
989 ResultReg = createResultReg(RC);
991 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
993 const MCInstrDesc &II = TII.get(Opc);
994 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
995 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
996 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
997 .addReg(LHSReg, getKillRegState(LHSIsKill))
998 .addReg(RHSReg, getKillRegState(RHSIsKill));
1002 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1003 bool LHSIsKill, uint64_t Imm,
1004 bool SetFlags, bool WantResult) {
1005 assert(LHSReg && "Invalid register number.");
1007 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1011 if (isUInt<12>(Imm))
1013 else if ((Imm & 0xfff000) == Imm) {
1019 static const unsigned OpcTable[2][2][2] = {
1020 { { AArch64::SUBWri, AArch64::SUBXri },
1021 { AArch64::ADDWri, AArch64::ADDXri } },
1022 { { AArch64::SUBSWri, AArch64::SUBSXri },
1023 { AArch64::ADDSWri, AArch64::ADDSXri } }
1025 bool Is64Bit = RetVT == MVT::i64;
1026 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1027 const TargetRegisterClass *RC;
1029 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1031 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1034 ResultReg = createResultReg(RC);
1036 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1038 const MCInstrDesc &II = TII.get(Opc);
1039 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1041 .addReg(LHSReg, getKillRegState(LHSIsKill))
1043 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1047 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1048 bool LHSIsKill, unsigned RHSReg,
1050 AArch64_AM::ShiftExtendType ShiftType,
1051 uint64_t ShiftImm, bool SetFlags,
1053 assert(LHSReg && RHSReg && "Invalid register number.");
1055 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1058 static const unsigned OpcTable[2][2][2] = {
1059 { { AArch64::SUBWrs, AArch64::SUBXrs },
1060 { AArch64::ADDWrs, AArch64::ADDXrs } },
1061 { { AArch64::SUBSWrs, AArch64::SUBSXrs },
1062 { AArch64::ADDSWrs, AArch64::ADDSXrs } }
1064 bool Is64Bit = RetVT == MVT::i64;
1065 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1066 const TargetRegisterClass *RC =
1067 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1070 ResultReg = createResultReg(RC);
1072 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1074 const MCInstrDesc &II = TII.get(Opc);
1075 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1076 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1078 .addReg(LHSReg, getKillRegState(LHSIsKill))
1079 .addReg(RHSReg, getKillRegState(RHSIsKill))
1080 .addImm(getShifterImm(ShiftType, ShiftImm));
1084 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1085 bool LHSIsKill, unsigned RHSReg,
1087 AArch64_AM::ShiftExtendType ExtType,
1088 uint64_t ShiftImm, bool SetFlags,
1090 assert(LHSReg && RHSReg && "Invalid register number.");
1092 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1095 static const unsigned OpcTable[2][2][2] = {
1096 { { AArch64::SUBWrx, AArch64::SUBXrx },
1097 { AArch64::ADDWrx, AArch64::ADDXrx } },
1098 { { AArch64::SUBSWrx, AArch64::SUBSXrx },
1099 { AArch64::ADDSWrx, AArch64::ADDSXrx } }
1101 bool Is64Bit = RetVT == MVT::i64;
1102 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1103 const TargetRegisterClass *RC = nullptr;
1105 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1107 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1110 ResultReg = createResultReg(RC);
1112 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1114 const MCInstrDesc &II = TII.get(Opc);
1115 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1116 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1117 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1118 .addReg(LHSReg, getKillRegState(LHSIsKill))
1119 .addReg(RHSReg, getKillRegState(RHSIsKill))
1120 .addImm(getArithExtendImm(ExtType, ShiftImm));
1124 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1125 Type *Ty = LHS->getType();
1126 EVT EVT = TLI.getValueType(Ty, true);
1127 if (!EVT.isSimple())
1129 MVT VT = EVT.getSimpleVT();
1131 switch (VT.SimpleTy) {
1139 return emitICmp(VT, LHS, RHS, IsZExt);
1142 return emitFCmp(VT, LHS, RHS);
1146 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1148 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1152 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1154 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1155 /*SetFlags=*/true, /*WantResult=*/false) != 0;
1158 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1159 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1162 // Check to see if the 2nd operand is a constant that we can encode directly
1164 bool UseImm = false;
1165 if (const auto *CFP = dyn_cast<ConstantFP>(RHS))
1166 if (CFP->isZero() && !CFP->isNegative())
1169 unsigned LHSReg = getRegForValue(LHS);
1172 bool LHSIsKill = hasTrivialKill(LHS);
1175 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1176 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1177 .addReg(LHSReg, getKillRegState(LHSIsKill));
1181 unsigned RHSReg = getRegForValue(RHS);
1184 bool RHSIsKill = hasTrivialKill(RHS);
1186 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1188 .addReg(LHSReg, getKillRegState(LHSIsKill))
1189 .addReg(RHSReg, getKillRegState(RHSIsKill));
1193 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1194 bool SetFlags, bool WantResult, bool IsZExt) {
1195 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1199 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1200 bool SetFlags, bool WantResult, bool IsZExt) {
1201 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1205 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1206 bool LHSIsKill, unsigned RHSReg,
1207 bool RHSIsKill, bool WantResult) {
1208 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1209 RHSIsKill, /*SetFlags=*/true, WantResult);
1212 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1213 bool LHSIsKill, unsigned RHSReg,
1215 AArch64_AM::ShiftExtendType ShiftType,
1216 uint64_t ShiftImm, bool WantResult) {
1217 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1218 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true,
1222 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1223 const Value *LHS, const Value *RHS) {
1224 // Canonicalize immediates to the RHS first.
1225 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
1226 std::swap(LHS, RHS);
1228 // Canonicalize shift immediate to the RHS.
1229 if (isValueAvailable(LHS))
1230 if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
1231 if (isa<ConstantInt>(SI->getOperand(1)))
1232 if (SI->getOpcode() == Instruction::Shl)
1233 std::swap(LHS, RHS);
1235 unsigned LHSReg = getRegForValue(LHS);
1238 bool LHSIsKill = hasTrivialKill(LHS);
1240 unsigned ResultReg = 0;
1241 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1242 uint64_t Imm = C->getZExtValue();
1243 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1248 // Check if the shift can be folded into the instruction.
1249 if (isValueAvailable(RHS))
1250 if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
1251 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
1252 if (SI->getOpcode() == Instruction::Shl) {
1253 uint64_t ShiftVal = C->getZExtValue();
1254 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1257 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1258 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1259 RHSIsKill, ShiftVal);
1262 unsigned RHSReg = getRegForValue(RHS);
1265 bool RHSIsKill = hasTrivialKill(RHS);
1267 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1268 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1269 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1270 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1271 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1276 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1277 unsigned LHSReg, bool LHSIsKill,
1279 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1280 "ISD nodes are not consecutive!");
1281 static const unsigned OpcTable[3][2] = {
1282 { AArch64::ANDWri, AArch64::ANDXri },
1283 { AArch64::ORRWri, AArch64::ORRXri },
1284 { AArch64::EORWri, AArch64::EORXri }
1286 const TargetRegisterClass *RC;
1289 switch (RetVT.SimpleTy) {
1296 unsigned Idx = ISDOpc - ISD::AND;
1297 Opc = OpcTable[Idx][0];
1298 RC = &AArch64::GPR32spRegClass;
1303 Opc = OpcTable[ISDOpc - ISD::AND][1];
1304 RC = &AArch64::GPR64spRegClass;
1309 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1312 unsigned ResultReg =
1313 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,
1314 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
1315 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1316 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1317 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1322 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1323 unsigned LHSReg, bool LHSIsKill,
1324 unsigned RHSReg, bool RHSIsKill,
1325 uint64_t ShiftImm) {
1326 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1327 "ISD nodes are not consecutive!");
1328 static const unsigned OpcTable[3][2] = {
1329 { AArch64::ANDWrs, AArch64::ANDXrs },
1330 { AArch64::ORRWrs, AArch64::ORRXrs },
1331 { AArch64::EORWrs, AArch64::EORXrs }
1333 const TargetRegisterClass *RC;
1335 switch (RetVT.SimpleTy) {
1342 Opc = OpcTable[ISDOpc - ISD::AND][0];
1343 RC = &AArch64::GPR32RegClass;
1346 Opc = OpcTable[ISDOpc - ISD::AND][1];
1347 RC = &AArch64::GPR64RegClass;
1350 unsigned ResultReg =
1351 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1352 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
1353 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1354 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1355 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1360 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1362 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1365 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
1366 MachineMemOperand *MMO) {
1367 // Simplify this down to something we can handle.
1368 if (!SimplifyAddress(Addr, VT))
1371 unsigned ScaleFactor;
1372 switch (VT.SimpleTy) {
1373 default: llvm_unreachable("Unexpected value type.");
1374 case MVT::i1: // fall-through
1375 case MVT::i8: ScaleFactor = 1; break;
1376 case MVT::i16: ScaleFactor = 2; break;
1377 case MVT::i32: // fall-through
1378 case MVT::f32: ScaleFactor = 4; break;
1379 case MVT::i64: // fall-through
1380 case MVT::f64: ScaleFactor = 8; break;
1383 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1384 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1385 bool UseScaled = true;
1386 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1391 static const unsigned OpcTable[4][6] = {
1392 { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, AArch64::LDURXi,
1393 AArch64::LDURSi, AArch64::LDURDi },
1394 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, AArch64::LDRXui,
1395 AArch64::LDRSui, AArch64::LDRDui },
1396 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, AArch64::LDRXroX,
1397 AArch64::LDRSroX, AArch64::LDRDroX },
1398 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, AArch64::LDRXroW,
1399 AArch64::LDRSroW, AArch64::LDRDroW }
1403 const TargetRegisterClass *RC;
1404 bool VTIsi1 = false;
1405 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1406 Addr.getOffsetReg();
1407 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1408 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1409 Addr.getExtendType() == AArch64_AM::SXTW)
1412 switch (VT.SimpleTy) {
1413 default: llvm_unreachable("Unexpected value type.");
1414 case MVT::i1: VTIsi1 = true; // Intentional fall-through.
1415 case MVT::i8: Opc = OpcTable[Idx][0]; RC = &AArch64::GPR32RegClass; break;
1416 case MVT::i16: Opc = OpcTable[Idx][1]; RC = &AArch64::GPR32RegClass; break;
1417 case MVT::i32: Opc = OpcTable[Idx][2]; RC = &AArch64::GPR32RegClass; break;
1418 case MVT::i64: Opc = OpcTable[Idx][3]; RC = &AArch64::GPR64RegClass; break;
1419 case MVT::f32: Opc = OpcTable[Idx][4]; RC = &AArch64::FPR32RegClass; break;
1420 case MVT::f64: Opc = OpcTable[Idx][5]; RC = &AArch64::FPR64RegClass; break;
1423 // Create the base instruction, then add the operands.
1424 ResultReg = createResultReg(RC);
1425 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1426 TII.get(Opc), ResultReg);
1427 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
1429 // Loading an i1 requires special handling.
1431 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1432 assert(ANDReg && "Unexpected AND instruction emission failure.");
1438 bool AArch64FastISel::selectAddSub(const Instruction *I) {
1440 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1444 return selectOperator(I, I->getOpcode());
1447 switch (I->getOpcode()) {
1449 llvm_unreachable("Unexpected instruction.");
1450 case Instruction::Add:
1451 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1453 case Instruction::Sub:
1454 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1460 updateValueMap(I, ResultReg);
1464 bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
1466 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1470 return selectOperator(I, I->getOpcode());
1473 switch (I->getOpcode()) {
1475 llvm_unreachable("Unexpected instruction.");
1476 case Instruction::And:
1477 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1479 case Instruction::Or:
1480 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1482 case Instruction::Xor:
1483 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1489 updateValueMap(I, ResultReg);
1493 bool AArch64FastISel::SelectLoad(const Instruction *I) {
1495 // Verify we have a legal type before going any further. Currently, we handle
1496 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1497 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1498 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) ||
1499 cast<LoadInst>(I)->isAtomic())
1502 // See if we can handle this address.
1504 if (!ComputeAddress(I->getOperand(0), Addr, I->getType()))
1508 if (!EmitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
1511 updateValueMap(I, ResultReg);
1515 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
1516 MachineMemOperand *MMO) {
1517 // Simplify this down to something we can handle.
1518 if (!SimplifyAddress(Addr, VT))
1521 unsigned ScaleFactor;
1522 switch (VT.SimpleTy) {
1523 default: llvm_unreachable("Unexpected value type.");
1524 case MVT::i1: // fall-through
1525 case MVT::i8: ScaleFactor = 1; break;
1526 case MVT::i16: ScaleFactor = 2; break;
1527 case MVT::i32: // fall-through
1528 case MVT::f32: ScaleFactor = 4; break;
1529 case MVT::i64: // fall-through
1530 case MVT::f64: ScaleFactor = 8; break;
1533 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1534 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1535 bool UseScaled = true;
1536 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1542 static const unsigned OpcTable[4][6] = {
1543 { AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
1544 AArch64::STURSi, AArch64::STURDi },
1545 { AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
1546 AArch64::STRSui, AArch64::STRDui },
1547 { AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
1548 AArch64::STRSroX, AArch64::STRDroX },
1549 { AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
1550 AArch64::STRSroW, AArch64::STRDroW }
1555 bool VTIsi1 = false;
1556 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1557 Addr.getOffsetReg();
1558 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1559 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1560 Addr.getExtendType() == AArch64_AM::SXTW)
1563 switch (VT.SimpleTy) {
1564 default: llvm_unreachable("Unexpected value type.");
1565 case MVT::i1: VTIsi1 = true;
1566 case MVT::i8: Opc = OpcTable[Idx][0]; break;
1567 case MVT::i16: Opc = OpcTable[Idx][1]; break;
1568 case MVT::i32: Opc = OpcTable[Idx][2]; break;
1569 case MVT::i64: Opc = OpcTable[Idx][3]; break;
1570 case MVT::f32: Opc = OpcTable[Idx][4]; break;
1571 case MVT::f64: Opc = OpcTable[Idx][5]; break;
1574 // Storing an i1 requires special handling.
1575 if (VTIsi1 && SrcReg != AArch64::WZR) {
1576 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
1577 assert(ANDReg && "Unexpected AND instruction emission failure.");
1580 // Create the base instruction, then add the operands.
1581 const MCInstrDesc &II = TII.get(Opc);
1582 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
1583 MachineInstrBuilder MIB =
1584 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
1585 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
1590 bool AArch64FastISel::SelectStore(const Instruction *I) {
1592 const Value *Op0 = I->getOperand(0);
1593 // Verify we have a legal type before going any further. Currently, we handle
1594 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1595 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1596 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) ||
1597 cast<StoreInst>(I)->isAtomic())
1600 // Get the value to be stored into a register. Use the zero register directly
1601 // when possible to avoid an unnecessary copy and a wasted register.
1602 unsigned SrcReg = 0;
1603 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
1605 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1606 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
1607 if (CF->isZero() && !CF->isNegative()) {
1608 VT = MVT::getIntegerVT(VT.getSizeInBits());
1609 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1614 SrcReg = getRegForValue(Op0);
1619 // See if we can handle this address.
1621 if (!ComputeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
1624 if (!EmitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
1629 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
1631 case CmpInst::FCMP_ONE:
1632 case CmpInst::FCMP_UEQ:
1634 // AL is our "false" for now. The other two need more compares.
1635 return AArch64CC::AL;
1636 case CmpInst::ICMP_EQ:
1637 case CmpInst::FCMP_OEQ:
1638 return AArch64CC::EQ;
1639 case CmpInst::ICMP_SGT:
1640 case CmpInst::FCMP_OGT:
1641 return AArch64CC::GT;
1642 case CmpInst::ICMP_SGE:
1643 case CmpInst::FCMP_OGE:
1644 return AArch64CC::GE;
1645 case CmpInst::ICMP_UGT:
1646 case CmpInst::FCMP_UGT:
1647 return AArch64CC::HI;
1648 case CmpInst::FCMP_OLT:
1649 return AArch64CC::MI;
1650 case CmpInst::ICMP_ULE:
1651 case CmpInst::FCMP_OLE:
1652 return AArch64CC::LS;
1653 case CmpInst::FCMP_ORD:
1654 return AArch64CC::VC;
1655 case CmpInst::FCMP_UNO:
1656 return AArch64CC::VS;
1657 case CmpInst::FCMP_UGE:
1658 return AArch64CC::PL;
1659 case CmpInst::ICMP_SLT:
1660 case CmpInst::FCMP_ULT:
1661 return AArch64CC::LT;
1662 case CmpInst::ICMP_SLE:
1663 case CmpInst::FCMP_ULE:
1664 return AArch64CC::LE;
1665 case CmpInst::FCMP_UNE:
1666 case CmpInst::ICMP_NE:
1667 return AArch64CC::NE;
1668 case CmpInst::ICMP_UGE:
1669 return AArch64CC::HS;
1670 case CmpInst::ICMP_ULT:
1671 return AArch64CC::LO;
1675 bool AArch64FastISel::SelectBranch(const Instruction *I) {
1676 const BranchInst *BI = cast<BranchInst>(I);
1677 if (BI->isUnconditional()) {
1678 MachineBasicBlock *MSucc = FuncInfo.MBBMap[BI->getSuccessor(0)];
1679 fastEmitBranch(MSucc, BI->getDebugLoc());
1683 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1684 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1686 AArch64CC::CondCode CC = AArch64CC::NE;
1687 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1688 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1689 // We may not handle every CC for now.
1690 CC = getCompareCC(CI->getPredicate());
1691 if (CC == AArch64CC::AL)
1695 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1703 // Obtain the branch weight and add the TrueBB to the successor list.
1704 uint32_t BranchWeight = 0;
1706 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1707 TBB->getBasicBlock());
1708 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1710 fastEmitBranch(FBB, DbgLoc);
1713 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1715 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1716 (isTypeSupported(TI->getOperand(0)->getType(), SrcVT))) {
1717 unsigned CondReg = getRegForValue(TI->getOperand(0));
1720 bool CondIsKill = hasTrivialKill(TI->getOperand(0));
1722 // Issue an extract_subreg to get the lower 32-bits.
1723 if (SrcVT == MVT::i64) {
1724 CondReg = fastEmitInst_extractsubreg(MVT::i32, CondReg, CondIsKill,
1729 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
1730 assert(ANDReg && "Unexpected AND instruction emission failure.");
1731 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
1733 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1734 std::swap(TBB, FBB);
1737 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1741 // Obtain the branch weight and add the TrueBB to the successor list.
1742 uint32_t BranchWeight = 0;
1744 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1745 TBB->getBasicBlock());
1746 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1748 fastEmitBranch(FBB, DbgLoc);
1751 } else if (const ConstantInt *CI =
1752 dyn_cast<ConstantInt>(BI->getCondition())) {
1753 uint64_t Imm = CI->getZExtValue();
1754 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1755 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
1758 // Obtain the branch weight and add the target to the successor list.
1759 uint32_t BranchWeight = 0;
1761 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1762 Target->getBasicBlock());
1763 FuncInfo.MBB->addSuccessor(Target, BranchWeight);
1765 } else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
1766 // Fake request the condition, otherwise the intrinsic might be completely
1768 unsigned CondReg = getRegForValue(BI->getCondition());
1773 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1777 // Obtain the branch weight and add the TrueBB to the successor list.
1778 uint32_t BranchWeight = 0;
1780 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1781 TBB->getBasicBlock());
1782 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1784 fastEmitBranch(FBB, DbgLoc);
1788 unsigned CondReg = getRegForValue(BI->getCondition());
1791 bool CondRegIsKill = hasTrivialKill(BI->getCondition());
1793 // We've been divorced from our compare! Our block was split, and
1794 // now our compare lives in a predecessor block. We musn't
1795 // re-compare here, as the children of the compare aren't guaranteed
1796 // live across the block boundary (we *could* check for this).
1797 // Regardless, the compare has been done in the predecessor block,
1798 // and it left a value for us in a virtual register. Ergo, we test
1799 // the one-bit value left in the virtual register.
1800 emitICmp_ri(MVT::i32, CondReg, CondRegIsKill, 0);
1802 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1803 std::swap(TBB, FBB);
1807 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1811 // Obtain the branch weight and add the TrueBB to the successor list.
1812 uint32_t BranchWeight = 0;
1814 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1815 TBB->getBasicBlock());
1816 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1818 fastEmitBranch(FBB, DbgLoc);
1822 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
1823 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
1824 unsigned AddrReg = getRegForValue(BI->getOperand(0));
1828 // Emit the indirect branch.
1829 const MCInstrDesc &II = TII.get(AArch64::BR);
1830 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
1831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
1833 // Make sure the CFG is up-to-date.
1834 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
1835 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
1840 bool AArch64FastISel::SelectCmp(const Instruction *I) {
1841 const CmpInst *CI = cast<CmpInst>(I);
1843 // Try to optimize or fold the cmp.
1844 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1845 unsigned ResultReg = 0;
1846 switch (Predicate) {
1849 case CmpInst::FCMP_FALSE:
1850 ResultReg = createResultReg(&AArch64::GPR32RegClass);
1851 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1852 TII.get(TargetOpcode::COPY), ResultReg)
1853 .addReg(AArch64::WZR, getKillRegState(true));
1855 case CmpInst::FCMP_TRUE:
1856 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
1861 updateValueMap(I, ResultReg);
1866 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1869 ResultReg = createResultReg(&AArch64::GPR32RegClass);
1871 // FCMP_UEQ and FCMP_ONE cannot be checked with a single instruction. These
1872 // condition codes are inverted, because they are used by CSINC.
1873 static unsigned CondCodeTable[2][2] = {
1874 { AArch64CC::NE, AArch64CC::VC },
1875 { AArch64CC::PL, AArch64CC::LE }
1877 unsigned *CondCodes = nullptr;
1878 switch (Predicate) {
1881 case CmpInst::FCMP_UEQ:
1882 CondCodes = &CondCodeTable[0][0];
1884 case CmpInst::FCMP_ONE:
1885 CondCodes = &CondCodeTable[1][0];
1890 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass);
1891 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1893 .addReg(AArch64::WZR, getKillRegState(true))
1894 .addReg(AArch64::WZR, getKillRegState(true))
1895 .addImm(CondCodes[0]);
1896 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1898 .addReg(TmpReg1, getKillRegState(true))
1899 .addReg(AArch64::WZR, getKillRegState(true))
1900 .addImm(CondCodes[1]);
1902 updateValueMap(I, ResultReg);
1906 // Now set a register based on the comparison.
1907 AArch64CC::CondCode CC = getCompareCC(Predicate);
1908 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
1909 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1910 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1912 .addReg(AArch64::WZR, getKillRegState(true))
1913 .addReg(AArch64::WZR, getKillRegState(true))
1914 .addImm(invertedCC);
1916 updateValueMap(I, ResultReg);
1920 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1921 const SelectInst *SI = cast<SelectInst>(I);
1923 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1924 if (!DestEVT.isSimple())
1927 MVT DestVT = DestEVT.getSimpleVT();
1928 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1933 const TargetRegisterClass *RC = nullptr;
1934 switch (DestVT.SimpleTy) {
1935 default: return false;
1937 SelectOpc = AArch64::CSELWr; RC = &AArch64::GPR32RegClass; break;
1939 SelectOpc = AArch64::CSELXr; RC = &AArch64::GPR64RegClass; break;
1941 SelectOpc = AArch64::FCSELSrrr; RC = &AArch64::FPR32RegClass; break;
1943 SelectOpc = AArch64::FCSELDrrr; RC = &AArch64::FPR64RegClass; break;
1946 const Value *Cond = SI->getCondition();
1947 bool NeedTest = true;
1948 AArch64CC::CondCode CC = AArch64CC::NE;
1949 if (foldXALUIntrinsic(CC, I, Cond))
1952 unsigned CondReg = getRegForValue(Cond);
1955 bool CondIsKill = hasTrivialKill(Cond);
1958 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
1959 assert(ANDReg && "Unexpected AND instruction emission failure.");
1960 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
1963 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1964 bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
1966 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1967 bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
1969 if (!TrueReg || !FalseReg)
1972 unsigned ResultReg = fastEmitInst_rri(SelectOpc, RC, TrueReg, TrueIsKill,
1973 FalseReg, FalseIsKill, CC);
1974 updateValueMap(I, ResultReg);
1978 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1979 Value *V = I->getOperand(0);
1980 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1983 unsigned Op = getRegForValue(V);
1987 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1988 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1989 ResultReg).addReg(Op);
1990 updateValueMap(I, ResultReg);
1994 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1995 Value *V = I->getOperand(0);
1996 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1999 unsigned Op = getRegForValue(V);
2003 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
2004 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
2005 ResultReg).addReg(Op);
2006 updateValueMap(I, ResultReg);
2010 // FPToUI and FPToSI
2011 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
2013 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2016 unsigned SrcReg = getRegForValue(I->getOperand(0));
2020 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2021 if (SrcVT == MVT::f128)
2025 if (SrcVT == MVT::f64) {
2027 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2029 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2032 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2034 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2036 unsigned ResultReg = createResultReg(
2037 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2038 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2040 updateValueMap(I, ResultReg);
2044 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
2046 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2048 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2049 "Unexpected value type.");
2051 unsigned SrcReg = getRegForValue(I->getOperand(0));
2054 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
2056 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2058 // Handle sign-extension.
2059 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
2061 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2068 if (SrcVT == MVT::i64) {
2070 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2072 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2075 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2077 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2080 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2082 updateValueMap(I, ResultReg);
2086 bool AArch64FastISel::fastLowerArguments() {
2087 if (!FuncInfo.CanLowerReturn)
2090 const Function *F = FuncInfo.Fn;
2094 CallingConv::ID CC = F->getCallingConv();
2095 if (CC != CallingConv::C)
2098 // Only handle simple cases like i1/i8/i16/i32/i64/f32/f64 of up to 8 GPR and
2100 unsigned GPRCnt = 0;
2101 unsigned FPRCnt = 0;
2103 for (auto const &Arg : F->args()) {
2104 // The first argument is at index 1.
2106 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
2107 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
2108 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
2109 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
2112 Type *ArgTy = Arg.getType();
2113 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
2116 EVT ArgVT = TLI.getValueType(ArgTy);
2117 if (!ArgVT.isSimple()) return false;
2118 switch (ArgVT.getSimpleVT().SimpleTy) {
2119 default: return false;
2134 if (GPRCnt > 8 || FPRCnt > 8)
2138 static const MCPhysReg Registers[5][8] = {
2139 { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
2140 AArch64::W5, AArch64::W6, AArch64::W7 },
2141 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
2142 AArch64::X5, AArch64::X6, AArch64::X7 },
2143 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
2144 AArch64::H5, AArch64::H6, AArch64::H7 },
2145 { AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
2146 AArch64::S5, AArch64::S6, AArch64::S7 },
2147 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
2148 AArch64::D5, AArch64::D6, AArch64::D7 }
2151 unsigned GPRIdx = 0;
2152 unsigned FPRIdx = 0;
2153 for (auto const &Arg : F->args()) {
2154 MVT VT = TLI.getSimpleValueType(Arg.getType());
2156 const TargetRegisterClass *RC = nullptr;
2157 switch (VT.SimpleTy) {
2158 default: llvm_unreachable("Unexpected value type.");
2161 case MVT::i16: VT = MVT::i32; // fall-through
2163 SrcReg = Registers[0][GPRIdx++]; RC = &AArch64::GPR32RegClass; break;
2165 SrcReg = Registers[1][GPRIdx++]; RC = &AArch64::GPR64RegClass; break;
2167 SrcReg = Registers[2][FPRIdx++]; RC = &AArch64::FPR16RegClass; break;
2169 SrcReg = Registers[3][FPRIdx++]; RC = &AArch64::FPR32RegClass; break;
2171 SrcReg = Registers[4][FPRIdx++]; RC = &AArch64::FPR64RegClass; break;
2174 // Skip unused arguments.
2175 if (Arg.use_empty()) {
2176 updateValueMap(&Arg, 0);
2180 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
2181 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
2182 // Without this, EmitLiveInCopies may eliminate the livein if its only
2183 // use is a bitcast (which isn't turned into an instruction).
2184 unsigned ResultReg = createResultReg(RC);
2185 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2186 TII.get(TargetOpcode::COPY), ResultReg)
2187 .addReg(DstReg, getKillRegState(true));
2188 updateValueMap(&Arg, ResultReg);
2193 bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
2194 SmallVectorImpl<MVT> &OutVTs,
2195 unsigned &NumBytes) {
2196 CallingConv::ID CC = CLI.CallConv;
2197 SmallVector<CCValAssign, 16> ArgLocs;
2198 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
2199 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
2201 // Get a count of how many bytes are to be pushed on the stack.
2202 NumBytes = CCInfo.getNextStackOffset();
2204 // Issue CALLSEQ_START
2205 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2206 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
2209 // Process the args.
2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2211 CCValAssign &VA = ArgLocs[i];
2212 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
2213 MVT ArgVT = OutVTs[VA.getValNo()];
2215 unsigned ArgReg = getRegForValue(ArgVal);
2219 // Handle arg promotion: SExt, ZExt, AExt.
2220 switch (VA.getLocInfo()) {
2221 case CCValAssign::Full:
2223 case CCValAssign::SExt: {
2224 MVT DestVT = VA.getLocVT();
2226 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2231 case CCValAssign::AExt:
2232 // Intentional fall-through.
2233 case CCValAssign::ZExt: {
2234 MVT DestVT = VA.getLocVT();
2236 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
2242 llvm_unreachable("Unknown arg promotion!");
2245 // Now copy/store arg to correct locations.
2246 if (VA.isRegLoc() && !VA.needsCustom()) {
2247 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2248 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
2249 CLI.OutRegs.push_back(VA.getLocReg());
2250 } else if (VA.needsCustom()) {
2251 // FIXME: Handle custom args.
2254 assert(VA.isMemLoc() && "Assuming store on stack.");
2256 // Don't emit stores for undef values.
2257 if (isa<UndefValue>(ArgVal))
2260 // Need to store on the stack.
2261 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
2263 unsigned BEAlign = 0;
2264 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2265 BEAlign = 8 - ArgSize;
2268 Addr.setKind(Address::RegBase);
2269 Addr.setReg(AArch64::SP);
2270 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
2272 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
2273 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2274 MachinePointerInfo::getStack(Addr.getOffset()),
2275 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
2277 if (!EmitStore(ArgVT, ArgReg, Addr, MMO))
2284 bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
2285 unsigned NumBytes) {
2286 CallingConv::ID CC = CLI.CallConv;
2288 // Issue CALLSEQ_END
2289 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2290 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
2291 .addImm(NumBytes).addImm(0);
2293 // Now the return value.
2294 if (RetVT != MVT::isVoid) {
2295 SmallVector<CCValAssign, 16> RVLocs;
2296 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2297 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
2299 // Only handle a single return value.
2300 if (RVLocs.size() != 1)
2303 // Copy all of the result registers out of their specified physreg.
2304 MVT CopyVT = RVLocs[0].getValVT();
2305 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
2306 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2307 TII.get(TargetOpcode::COPY), ResultReg)
2308 .addReg(RVLocs[0].getLocReg());
2309 CLI.InRegs.push_back(RVLocs[0].getLocReg());
2311 CLI.ResultReg = ResultReg;
2312 CLI.NumResultRegs = 1;
2318 bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
2319 CallingConv::ID CC = CLI.CallConv;
2320 bool IsTailCall = CLI.IsTailCall;
2321 bool IsVarArg = CLI.IsVarArg;
2322 const Value *Callee = CLI.Callee;
2323 const char *SymName = CLI.SymName;
2325 // Allow SelectionDAG isel to handle tail calls.
2329 CodeModel::Model CM = TM.getCodeModel();
2330 // Only support the small and large code model.
2331 if (CM != CodeModel::Small && CM != CodeModel::Large)
2334 // FIXME: Add large code model support for ELF.
2335 if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
2338 // Let SDISel handle vararg functions.
2342 // FIXME: Only handle *simple* calls for now.
2344 if (CLI.RetTy->isVoidTy())
2345 RetVT = MVT::isVoid;
2346 else if (!isTypeLegal(CLI.RetTy, RetVT))
2349 for (auto Flag : CLI.OutFlags)
2350 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
2353 // Set up the argument vectors.
2354 SmallVector<MVT, 16> OutVTs;
2355 OutVTs.reserve(CLI.OutVals.size());
2357 for (auto *Val : CLI.OutVals) {
2359 if (!isTypeLegal(Val->getType(), VT) &&
2360 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
2363 // We don't handle vector parameters yet.
2364 if (VT.isVector() || VT.getSizeInBits() > 64)
2367 OutVTs.push_back(VT);
2371 if (!ComputeCallAddress(Callee, Addr))
2374 // Handle the arguments now that we've gotten them.
2376 if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
2380 MachineInstrBuilder MIB;
2381 if (CM == CodeModel::Small) {
2382 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
2383 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
2385 MIB.addExternalSymbol(SymName, 0);
2386 else if (Addr.getGlobalValue())
2387 MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
2388 else if (Addr.getReg()) {
2389 unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
2394 unsigned CallReg = 0;
2396 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
2397 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
2399 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGE);
2401 CallReg = createResultReg(&AArch64::GPR64RegClass);
2402 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
2405 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
2407 } else if (Addr.getGlobalValue()) {
2408 CallReg = AArch64MaterializeGV(Addr.getGlobalValue());
2409 } else if (Addr.getReg())
2410 CallReg = Addr.getReg();
2415 const MCInstrDesc &II = TII.get(AArch64::BLR);
2416 CallReg = constrainOperandRegClass(II, CallReg, 0);
2417 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
2420 // Add implicit physical register uses to the call.
2421 for (auto Reg : CLI.OutRegs)
2422 MIB.addReg(Reg, RegState::Implicit);
2424 // Add a register mask with the call-preserved registers.
2425 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2426 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2430 // Finish off the call including any return values.
2431 return FinishCall(CLI, RetVT, NumBytes);
2434 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
2436 return Len / Alignment <= 4;
2441 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
2442 uint64_t Len, unsigned Alignment) {
2443 // Make sure we don't bloat code by inlining very large memcpy's.
2444 if (!IsMemCpySmall(Len, Alignment))
2447 int64_t UnscaledOffset = 0;
2448 Address OrigDest = Dest;
2449 Address OrigSrc = Src;
2453 if (!Alignment || Alignment >= 8) {
2464 // Bound based on alignment.
2465 if (Len >= 4 && Alignment == 4)
2467 else if (Len >= 2 && Alignment == 2)
2476 RV = EmitLoad(VT, ResultReg, Src);
2480 RV = EmitStore(VT, ResultReg, Dest);
2484 int64_t Size = VT.getSizeInBits() / 8;
2486 UnscaledOffset += Size;
2488 // We need to recompute the unscaled offset for each iteration.
2489 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
2490 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
2496 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
2497 /// into the user. The condition code will only be updated on success.
2498 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
2499 const Instruction *I,
2500 const Value *Cond) {
2501 if (!isa<ExtractValueInst>(Cond))
2504 const auto *EV = cast<ExtractValueInst>(Cond);
2505 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
2508 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
2510 const Function *Callee = II->getCalledFunction();
2512 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
2513 if (!isTypeLegal(RetTy, RetVT))
2516 if (RetVT != MVT::i32 && RetVT != MVT::i64)
2519 AArch64CC::CondCode TmpCC;
2520 switch (II->getIntrinsicID()) {
2521 default: return false;
2522 case Intrinsic::sadd_with_overflow:
2523 case Intrinsic::ssub_with_overflow: TmpCC = AArch64CC::VS; break;
2524 case Intrinsic::uadd_with_overflow: TmpCC = AArch64CC::HS; break;
2525 case Intrinsic::usub_with_overflow: TmpCC = AArch64CC::LO; break;
2526 case Intrinsic::smul_with_overflow:
2527 case Intrinsic::umul_with_overflow: TmpCC = AArch64CC::NE; break;
2530 // Check if both instructions are in the same basic block.
2531 if (II->getParent() != I->getParent())
2534 // Make sure nothing is in the way
2535 BasicBlock::const_iterator Start = I;
2536 BasicBlock::const_iterator End = II;
2537 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
2538 // We only expect extractvalue instructions between the intrinsic and the
2539 // instruction to be selected.
2540 if (!isa<ExtractValueInst>(Itr))
2543 // Check that the extractvalue operand comes from the intrinsic.
2544 const auto *EVI = cast<ExtractValueInst>(Itr);
2545 if (EVI->getAggregateOperand() != II)
2553 bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
2554 // FIXME: Handle more intrinsics.
2555 switch (II->getIntrinsicID()) {
2556 default: return false;
2557 case Intrinsic::frameaddress: {
2558 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2559 MFI->setFrameAddressIsTaken(true);
2561 const AArch64RegisterInfo *RegInfo =
2562 static_cast<const AArch64RegisterInfo *>(
2563 TM.getSubtargetImpl()->getRegisterInfo());
2564 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2565 unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2566 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2567 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
2568 // Recursively load frame address
2574 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
2576 DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
2577 SrcReg, /*IsKill=*/true, 0);
2578 assert(DestReg && "Unexpected LDR instruction emission failure.");
2582 updateValueMap(II, SrcReg);
2585 case Intrinsic::memcpy:
2586 case Intrinsic::memmove: {
2587 const auto *MTI = cast<MemTransferInst>(II);
2588 // Don't handle volatile.
2589 if (MTI->isVolatile())
2592 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2593 // we would emit dead code because we don't currently handle memmoves.
2594 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
2595 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
2596 // Small memcpy's are common enough that we want to do them without a call
2598 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
2599 unsigned Alignment = MTI->getAlignment();
2600 if (IsMemCpySmall(Len, Alignment)) {
2602 if (!ComputeAddress(MTI->getRawDest(), Dest) ||
2603 !ComputeAddress(MTI->getRawSource(), Src))
2605 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2610 if (!MTI->getLength()->getType()->isIntegerTy(64))
2613 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
2614 // Fast instruction selection doesn't support the special
2618 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
2619 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
2621 case Intrinsic::memset: {
2622 const MemSetInst *MSI = cast<MemSetInst>(II);
2623 // Don't handle volatile.
2624 if (MSI->isVolatile())
2627 if (!MSI->getLength()->getType()->isIntegerTy(64))
2630 if (MSI->getDestAddressSpace() > 255)
2631 // Fast instruction selection doesn't support the special
2635 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
2637 case Intrinsic::trap: {
2638 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
2642 case Intrinsic::sqrt: {
2643 Type *RetTy = II->getCalledFunction()->getReturnType();
2646 if (!isTypeLegal(RetTy, VT))
2649 unsigned Op0Reg = getRegForValue(II->getOperand(0));
2652 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
2654 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
2658 updateValueMap(II, ResultReg);
2661 case Intrinsic::sadd_with_overflow:
2662 case Intrinsic::uadd_with_overflow:
2663 case Intrinsic::ssub_with_overflow:
2664 case Intrinsic::usub_with_overflow:
2665 case Intrinsic::smul_with_overflow:
2666 case Intrinsic::umul_with_overflow: {
2667 // This implements the basic lowering of the xalu with overflow intrinsics.
2668 const Function *Callee = II->getCalledFunction();
2669 auto *Ty = cast<StructType>(Callee->getReturnType());
2670 Type *RetTy = Ty->getTypeAtIndex(0U);
2673 if (!isTypeLegal(RetTy, VT))
2676 if (VT != MVT::i32 && VT != MVT::i64)
2679 const Value *LHS = II->getArgOperand(0);
2680 const Value *RHS = II->getArgOperand(1);
2681 // Canonicalize immediate to the RHS.
2682 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
2683 isCommutativeIntrinsic(II))
2684 std::swap(LHS, RHS);
2686 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
2687 AArch64CC::CondCode CC = AArch64CC::Invalid;
2688 switch (II->getIntrinsicID()) {
2689 default: llvm_unreachable("Unexpected intrinsic!");
2690 case Intrinsic::sadd_with_overflow:
2691 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
2694 case Intrinsic::uadd_with_overflow:
2695 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
2698 case Intrinsic::ssub_with_overflow:
2699 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
2702 case Intrinsic::usub_with_overflow:
2703 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
2706 case Intrinsic::smul_with_overflow: {
2708 unsigned LHSReg = getRegForValue(LHS);
2711 bool LHSIsKill = hasTrivialKill(LHS);
2713 unsigned RHSReg = getRegForValue(RHS);
2716 bool RHSIsKill = hasTrivialKill(RHS);
2718 if (VT == MVT::i32) {
2719 MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2720 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
2721 /*IsKill=*/false, 32);
2722 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
2724 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
2726 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
2727 AArch64_AM::ASR, 31, /*WantResult=*/false);
2729 assert(VT == MVT::i64 && "Unexpected value type.");
2730 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2731 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
2733 emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
2734 AArch64_AM::ASR, 63, /*WantResult=*/false);
2738 case Intrinsic::umul_with_overflow: {
2740 unsigned LHSReg = getRegForValue(LHS);
2743 bool LHSIsKill = hasTrivialKill(LHS);
2745 unsigned RHSReg = getRegForValue(RHS);
2748 bool RHSIsKill = hasTrivialKill(RHS);
2750 if (VT == MVT::i32) {
2751 MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2752 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
2753 /*IsKill=*/false, AArch64_AM::LSR, 32,
2754 /*WantResult=*/false);
2755 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
2758 assert(VT == MVT::i64 && "Unexpected value type.");
2759 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2760 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
2762 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
2763 /*IsKill=*/false, /*WantResult=*/false);
2770 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
2771 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2772 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
2775 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
2776 AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
2777 /*IsKill=*/true, getInvertedCondCode(CC));
2778 assert((ResultReg1 + 1) == ResultReg2 &&
2779 "Nonconsecutive result registers.");
2780 updateValueMap(II, ResultReg1, 2);
2787 bool AArch64FastISel::SelectRet(const Instruction *I) {
2788 const ReturnInst *Ret = cast<ReturnInst>(I);
2789 const Function &F = *I->getParent()->getParent();
2791 if (!FuncInfo.CanLowerReturn)
2797 // Build a list of return value registers.
2798 SmallVector<unsigned, 4> RetRegs;
2800 if (Ret->getNumOperands() > 0) {
2801 CallingConv::ID CC = F.getCallingConv();
2802 SmallVector<ISD::OutputArg, 4> Outs;
2803 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2805 // Analyze operands of the call, assigning locations to each operand.
2806 SmallVector<CCValAssign, 16> ValLocs;
2807 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2808 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
2809 : RetCC_AArch64_AAPCS;
2810 CCInfo.AnalyzeReturn(Outs, RetCC);
2812 // Only handle a single return value for now.
2813 if (ValLocs.size() != 1)
2816 CCValAssign &VA = ValLocs[0];
2817 const Value *RV = Ret->getOperand(0);
2819 // Don't bother handling odd stuff for now.
2820 if (VA.getLocInfo() != CCValAssign::Full)
2822 // Only handle register returns for now.
2825 unsigned Reg = getRegForValue(RV);
2829 unsigned SrcReg = Reg + VA.getValNo();
2830 unsigned DestReg = VA.getLocReg();
2831 // Avoid a cross-class copy. This is very unlikely.
2832 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
2835 EVT RVEVT = TLI.getValueType(RV->getType());
2836 if (!RVEVT.isSimple())
2839 // Vectors (of > 1 lane) in big endian need tricky handling.
2840 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
2843 MVT RVVT = RVEVT.getSimpleVT();
2844 if (RVVT == MVT::f128)
2846 MVT DestVT = VA.getValVT();
2847 // Special handling for extended integers.
2848 if (RVVT != DestVT) {
2849 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2852 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
2855 bool isZExt = Outs[0].Flags.isZExt();
2856 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
2862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2863 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
2865 // Add register to return instruction.
2866 RetRegs.push_back(VA.getLocReg());
2869 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2870 TII.get(AArch64::RET_ReallyLR));
2871 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2872 MIB.addReg(RetRegs[i], RegState::Implicit);
2876 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
2877 Type *DestTy = I->getType();
2878 Value *Op = I->getOperand(0);
2879 Type *SrcTy = Op->getType();
2881 EVT SrcEVT = TLI.getValueType(SrcTy, true);
2882 EVT DestEVT = TLI.getValueType(DestTy, true);
2883 if (!SrcEVT.isSimple())
2885 if (!DestEVT.isSimple())
2888 MVT SrcVT = SrcEVT.getSimpleVT();
2889 MVT DestVT = DestEVT.getSimpleVT();
2891 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
2894 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
2898 unsigned SrcReg = getRegForValue(Op);
2901 bool SrcIsKill = hasTrivialKill(Op);
2903 // If we're truncating from i64 to a smaller non-legal type then generate an
2904 // AND. Otherwise, we know the high bits are undefined and a truncate only
2905 // generate a COPY. We cannot mark the source register also as result
2906 // register, because this can incorrectly transfer the kill flag onto the
2909 if (SrcVT == MVT::i64) {
2911 switch (DestVT.SimpleTy) {
2913 // Trunc i64 to i32 is handled by the target-independent fast-isel.
2925 // Issue an extract_subreg to get the lower 32-bits.
2926 unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
2928 // Create the AND instruction which performs the actual truncation.
2929 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
2930 assert(ResultReg && "Unexpected AND instruction emission failure.");
2932 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2933 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2934 TII.get(TargetOpcode::COPY), ResultReg)
2935 .addReg(SrcReg, getKillRegState(SrcIsKill));
2938 updateValueMap(I, ResultReg);
2942 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
2943 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
2944 DestVT == MVT::i64) &&
2945 "Unexpected value type.");
2946 // Handle i8 and i16 as i32.
2947 if (DestVT == MVT::i8 || DestVT == MVT::i16)
2951 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
2952 assert(ResultReg && "Unexpected AND instruction emission failure.");
2953 if (DestVT == MVT::i64) {
2954 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
2955 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
2956 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2958 TII.get(AArch64::SUBREG_TO_REG), Reg64)
2961 .addImm(AArch64::sub_32);
2966 if (DestVT == MVT::i64) {
2967 // FIXME: We're SExt i1 to i64.
2970 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
2971 /*TODO:IsKill=*/false, 0, 0);
2975 unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2976 unsigned Op1, bool Op1IsKill) {
2978 switch (RetVT.SimpleTy) {
2984 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
2986 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
2989 const TargetRegisterClass *RC =
2990 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
2991 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
2992 /*IsKill=*/ZReg, true);
2995 unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2996 unsigned Op1, bool Op1IsKill) {
2997 if (RetVT != MVT::i64)
3000 return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
3001 Op0, Op0IsKill, Op1, Op1IsKill,
3002 AArch64::XZR, /*IsKill=*/true);
3005 unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3006 unsigned Op1, bool Op1IsKill) {
3007 if (RetVT != MVT::i64)
3010 return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
3011 Op0, Op0IsKill, Op1, Op1IsKill,
3012 AArch64::XZR, /*IsKill=*/true);
3015 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3016 unsigned Op1Reg, bool Op1IsKill) {
3018 bool NeedTrunc = false;
3020 switch (RetVT.SimpleTy) {
3022 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
3023 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
3024 case MVT::i32: Opc = AArch64::LSLVWr; break;
3025 case MVT::i64: Opc = AArch64::LSLVXr; break;
3028 const TargetRegisterClass *RC =
3029 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3031 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3034 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3037 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3041 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3042 bool Op0IsKill, uint64_t Shift,
3044 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3045 "Unexpected source/return type pair.");
3046 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3047 SrcVT == MVT::i64) && "Unexpected source value type.");
3048 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3049 RetVT == MVT::i64) && "Unexpected return value type.");
3051 bool Is64Bit = (RetVT == MVT::i64);
3052 unsigned RegSize = Is64Bit ? 64 : 32;
3053 unsigned DstBits = RetVT.getSizeInBits();
3054 unsigned SrcBits = SrcVT.getSizeInBits();
3056 // Don't deal with undefined shifts.
3057 if (Shift >= DstBits)
3060 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3061 // {S|U}BFM Wd, Wn, #r, #s
3062 // Wd<32+s-r,32-r> = Wn<s:0> when r > s
3064 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3065 // %2 = shl i16 %1, 4
3066 // Wd<32+7-28,32-28> = Wn<7:0> <- clamp s to 7
3067 // 0b1111_1111_1111_1111__1111_1010_1010_0000 sext
3068 // 0b0000_0000_0000_0000__0000_0101_0101_0000 sext | zext
3069 // 0b0000_0000_0000_0000__0000_1010_1010_0000 zext
3071 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3072 // %2 = shl i16 %1, 8
3073 // Wd<32+7-24,32-24> = Wn<7:0>
3074 // 0b1111_1111_1111_1111__1010_1010_0000_0000 sext
3075 // 0b0000_0000_0000_0000__0101_0101_0000_0000 sext | zext
3076 // 0b0000_0000_0000_0000__1010_1010_0000_0000 zext
3078 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3079 // %2 = shl i16 %1, 12
3080 // Wd<32+3-20,32-20> = Wn<3:0>
3081 // 0b1111_1111_1111_1111__1010_0000_0000_0000 sext
3082 // 0b0000_0000_0000_0000__0101_0000_0000_0000 sext | zext
3083 // 0b0000_0000_0000_0000__1010_0000_0000_0000 zext
3085 unsigned ImmR = RegSize - Shift;
3086 // Limit the width to the length of the source type.
3087 unsigned ImmS = std::min<unsigned>(SrcBits - 1, DstBits - 1 - Shift);
3088 static const unsigned OpcTable[2][2] = {
3089 {AArch64::SBFMWri, AArch64::SBFMXri},
3090 {AArch64::UBFMWri, AArch64::UBFMXri}
3092 unsigned Opc = OpcTable[IsZext][Is64Bit];
3093 const TargetRegisterClass *RC =
3094 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3095 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3096 unsigned TmpReg = MRI.createVirtualRegister(RC);
3097 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3098 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3100 .addReg(Op0, getKillRegState(Op0IsKill))
3101 .addImm(AArch64::sub_32);
3105 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3108 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3109 unsigned Op1Reg, bool Op1IsKill) {
3111 bool NeedTrunc = false;
3113 switch (RetVT.SimpleTy) {
3115 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
3116 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
3117 case MVT::i32: Opc = AArch64::LSRVWr; break;
3118 case MVT::i64: Opc = AArch64::LSRVXr; break;
3121 const TargetRegisterClass *RC =
3122 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3124 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
3125 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3126 Op0IsKill = Op1IsKill = true;
3128 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3131 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3135 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3136 bool Op0IsKill, uint64_t Shift,
3138 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3139 "Unexpected source/return type pair.");
3140 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3141 SrcVT == MVT::i64) && "Unexpected source value type.");
3142 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3143 RetVT == MVT::i64) && "Unexpected return value type.");
3145 bool Is64Bit = (RetVT == MVT::i64);
3146 unsigned RegSize = Is64Bit ? 64 : 32;
3147 unsigned DstBits = RetVT.getSizeInBits();
3148 unsigned SrcBits = SrcVT.getSizeInBits();
3150 // Don't deal with undefined shifts.
3151 if (Shift >= DstBits)
3154 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3155 // {S|U}BFM Wd, Wn, #r, #s
3156 // Wd<s-r:0> = Wn<s:r> when r <= s
3158 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3159 // %2 = lshr i16 %1, 4
3160 // Wd<7-4:0> = Wn<7:4>
3161 // 0b0000_0000_0000_0000__0000_1111_1111_1010 sext
3162 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3163 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3165 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3166 // %2 = lshr i16 %1, 8
3167 // Wd<7-7,0> = Wn<7:7>
3168 // 0b0000_0000_0000_0000__0000_0000_1111_1111 sext
3169 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3170 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3172 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3173 // %2 = lshr i16 %1, 12
3174 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3175 // 0b0000_0000_0000_0000__0000_0000_0000_1111 sext
3176 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3177 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3179 if (Shift >= SrcBits && IsZExt)
3180 return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
3183 // It is not possible to fold a sign-extend into the LShr instruction. In this
3184 // case emit a sign-extend.
3186 Op0 = EmitIntExt(SrcVT, Op0, RetVT, IsZExt);
3191 SrcBits = SrcVT.getSizeInBits();
3195 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3196 unsigned ImmS = SrcBits - 1;
3197 static const unsigned OpcTable[2][2] = {
3198 {AArch64::SBFMWri, AArch64::SBFMXri},
3199 {AArch64::UBFMWri, AArch64::UBFMXri}
3201 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3202 const TargetRegisterClass *RC =
3203 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3204 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3205 unsigned TmpReg = MRI.createVirtualRegister(RC);
3206 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3207 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3209 .addReg(Op0, getKillRegState(Op0IsKill))
3210 .addImm(AArch64::sub_32);
3214 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3217 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3218 unsigned Op1Reg, bool Op1IsKill) {
3220 bool NeedTrunc = false;
3222 switch (RetVT.SimpleTy) {
3224 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
3225 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
3226 case MVT::i32: Opc = AArch64::ASRVWr; break;
3227 case MVT::i64: Opc = AArch64::ASRVXr; break;
3230 const TargetRegisterClass *RC =
3231 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3233 Op0Reg = EmitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
3234 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3235 Op0IsKill = Op1IsKill = true;
3237 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3240 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3244 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3245 bool Op0IsKill, uint64_t Shift,
3247 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3248 "Unexpected source/return type pair.");
3249 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3250 SrcVT == MVT::i64) && "Unexpected source value type.");
3251 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3252 RetVT == MVT::i64) && "Unexpected return value type.");
3254 bool Is64Bit = (RetVT == MVT::i64);
3255 unsigned RegSize = Is64Bit ? 64 : 32;
3256 unsigned DstBits = RetVT.getSizeInBits();
3257 unsigned SrcBits = SrcVT.getSizeInBits();
3259 // Don't deal with undefined shifts.
3260 if (Shift >= DstBits)
3263 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3264 // {S|U}BFM Wd, Wn, #r, #s
3265 // Wd<s-r:0> = Wn<s:r> when r <= s
3267 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3268 // %2 = ashr i16 %1, 4
3269 // Wd<7-4:0> = Wn<7:4>
3270 // 0b1111_1111_1111_1111__1111_1111_1111_1010 sext
3271 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3272 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3274 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3275 // %2 = ashr i16 %1, 8
3276 // Wd<7-7,0> = Wn<7:7>
3277 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3278 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3279 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3281 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3282 // %2 = ashr i16 %1, 12
3283 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3284 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3285 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3286 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3288 if (Shift >= SrcBits && IsZExt)
3289 return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
3292 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3293 unsigned ImmS = SrcBits - 1;
3294 static const unsigned OpcTable[2][2] = {
3295 {AArch64::SBFMWri, AArch64::SBFMXri},
3296 {AArch64::UBFMWri, AArch64::UBFMXri}
3298 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3299 const TargetRegisterClass *RC =
3300 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3301 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3302 unsigned TmpReg = MRI.createVirtualRegister(RC);
3303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3304 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3306 .addReg(Op0, getKillRegState(Op0IsKill))
3307 .addImm(AArch64::sub_32);
3311 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3314 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
3316 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
3318 // FastISel does not have plumbing to deal with extensions where the SrcVT or
3319 // DestVT are odd things, so test to make sure that they are both types we can
3320 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
3321 // bail out to SelectionDAG.
3322 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
3323 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
3324 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
3325 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
3331 switch (SrcVT.SimpleTy) {
3335 return Emiti1Ext(SrcReg, DestVT, isZExt);
3337 if (DestVT == MVT::i64)
3338 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3340 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
3344 if (DestVT == MVT::i64)
3345 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3347 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
3351 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
3352 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3357 // Handle i8 and i16 as i32.
3358 if (DestVT == MVT::i8 || DestVT == MVT::i16)
3360 else if (DestVT == MVT::i64) {
3361 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3363 TII.get(AArch64::SUBREG_TO_REG), Src64)
3366 .addImm(AArch64::sub_32);
3370 const TargetRegisterClass *RC =
3371 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3372 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
3375 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
3376 // On ARM, in general, integer casts don't involve legal types; this code
3377 // handles promotable integers. The high bits for a type smaller than
3378 // the register size are assumed to be undefined.
3379 Type *DestTy = I->getType();
3380 Value *Src = I->getOperand(0);
3381 Type *SrcTy = Src->getType();
3383 bool isZExt = isa<ZExtInst>(I);
3384 unsigned SrcReg = getRegForValue(Src);
3388 EVT SrcEVT = TLI.getValueType(SrcTy, true);
3389 EVT DestEVT = TLI.getValueType(DestTy, true);
3390 if (!SrcEVT.isSimple())
3392 if (!DestEVT.isSimple())
3395 MVT SrcVT = SrcEVT.getSimpleVT();
3396 MVT DestVT = DestEVT.getSimpleVT();
3397 unsigned ResultReg = 0;
3399 // Check if it is an argument and if it is already zero/sign-extended.
3400 if (const auto *Arg = dyn_cast<Argument>(Src)) {
3401 if ((isZExt && Arg->hasZExtAttr()) || (!isZExt && Arg->hasSExtAttr())) {
3402 if (DestVT == MVT::i64) {
3403 ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
3404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3405 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
3408 .addImm(AArch64::sub_32);
3415 ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
3420 updateValueMap(I, ResultReg);
3424 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
3425 EVT DestEVT = TLI.getValueType(I->getType(), true);
3426 if (!DestEVT.isSimple())
3429 MVT DestVT = DestEVT.getSimpleVT();
3430 if (DestVT != MVT::i64 && DestVT != MVT::i32)
3434 bool is64bit = (DestVT == MVT::i64);
3435 switch (ISDOpcode) {
3439 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
3442 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
3445 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
3446 unsigned Src0Reg = getRegForValue(I->getOperand(0));
3449 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
3451 unsigned Src1Reg = getRegForValue(I->getOperand(1));
3454 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
3456 const TargetRegisterClass *RC =
3457 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3458 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
3459 Src1Reg, /*IsKill=*/false);
3460 assert(QuotReg && "Unexpected DIV instruction emission failure.");
3461 // The remainder is computed as numerator - (quotient * denominator) using the
3462 // MSUB instruction.
3463 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
3464 Src1Reg, Src1IsKill, Src0Reg,
3466 updateValueMap(I, ResultReg);
3470 bool AArch64FastISel::SelectMul(const Instruction *I) {
3471 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
3472 if (!SrcEVT.isSimple())
3474 MVT SrcVT = SrcEVT.getSimpleVT();
3476 // Must be simple value type. Don't handle vectors.
3477 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3481 unsigned Src0Reg = getRegForValue(I->getOperand(0));
3484 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
3486 unsigned Src1Reg = getRegForValue(I->getOperand(1));
3489 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
3491 unsigned ResultReg =
3492 Emit_MUL_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
3497 updateValueMap(I, ResultReg);
3501 bool AArch64FastISel::SelectShift(const Instruction *I) {
3503 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
3506 if (RetVT.isVector())
3507 return selectOperator(I, I->getOpcode());
3509 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
3510 unsigned ResultReg = 0;
3511 uint64_t ShiftVal = C->getZExtValue();
3513 bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
3514 const Value *Op0 = I->getOperand(0);
3515 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
3517 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
3520 Op0 = ZExt->getOperand(0);
3522 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
3524 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
3527 Op0 = SExt->getOperand(0);
3531 unsigned Op0Reg = getRegForValue(Op0);
3534 bool Op0IsKill = hasTrivialKill(Op0);
3536 switch (I->getOpcode()) {
3537 default: llvm_unreachable("Unexpected instruction.");
3538 case Instruction::Shl:
3539 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3541 case Instruction::AShr:
3542 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3544 case Instruction::LShr:
3545 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3551 updateValueMap(I, ResultReg);
3555 unsigned Op0Reg = getRegForValue(I->getOperand(0));
3558 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
3560 unsigned Op1Reg = getRegForValue(I->getOperand(1));
3563 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
3565 unsigned ResultReg = 0;
3566 switch (I->getOpcode()) {
3567 default: llvm_unreachable("Unexpected instruction.");
3568 case Instruction::Shl:
3569 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3571 case Instruction::AShr:
3572 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3574 case Instruction::LShr:
3575 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3582 updateValueMap(I, ResultReg);
3586 bool AArch64FastISel::SelectBitCast(const Instruction *I) {
3589 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
3591 if (!isTypeLegal(I->getType(), RetVT))
3595 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
3596 Opc = AArch64::FMOVWSr;
3597 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
3598 Opc = AArch64::FMOVXDr;
3599 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
3600 Opc = AArch64::FMOVSWr;
3601 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
3602 Opc = AArch64::FMOVDXr;
3606 const TargetRegisterClass *RC = nullptr;
3607 switch (RetVT.SimpleTy) {
3608 default: llvm_unreachable("Unexpected value type.");
3609 case MVT::i32: RC = &AArch64::GPR32RegClass; break;
3610 case MVT::i64: RC = &AArch64::GPR64RegClass; break;
3611 case MVT::f32: RC = &AArch64::FPR32RegClass; break;
3612 case MVT::f64: RC = &AArch64::FPR64RegClass; break;
3614 unsigned Op0Reg = getRegForValue(I->getOperand(0));
3617 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
3618 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
3623 updateValueMap(I, ResultReg);
3627 bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
3628 switch (I->getOpcode()) {
3631 case Instruction::Add:
3632 case Instruction::Sub:
3633 return selectAddSub(I);
3634 case Instruction::Mul:
3635 if (!selectBinaryOp(I, ISD::MUL))
3636 return SelectMul(I);
3638 case Instruction::SRem:
3639 if (!selectBinaryOp(I, ISD::SREM))
3640 return SelectRem(I, ISD::SREM);
3642 case Instruction::URem:
3643 if (!selectBinaryOp(I, ISD::UREM))
3644 return SelectRem(I, ISD::UREM);
3646 case Instruction::Shl:
3647 case Instruction::LShr:
3648 case Instruction::AShr:
3649 return SelectShift(I);
3650 case Instruction::And:
3651 case Instruction::Or:
3652 case Instruction::Xor:
3653 return selectLogicalOp(I);
3654 case Instruction::Br:
3655 return SelectBranch(I);
3656 case Instruction::IndirectBr:
3657 return SelectIndirectBr(I);
3658 case Instruction::BitCast:
3659 if (!FastISel::selectBitCast(I))
3660 return SelectBitCast(I);
3662 case Instruction::FPToSI:
3663 if (!selectCast(I, ISD::FP_TO_SINT))
3664 return SelectFPToInt(I, /*Signed=*/true);
3666 case Instruction::FPToUI:
3667 return SelectFPToInt(I, /*Signed=*/false);
3668 case Instruction::ZExt:
3669 if (!selectCast(I, ISD::ZERO_EXTEND))
3670 return SelectIntExt(I);
3672 case Instruction::SExt:
3673 if (!selectCast(I, ISD::SIGN_EXTEND))
3674 return SelectIntExt(I);
3676 case Instruction::Trunc:
3677 if (!selectCast(I, ISD::TRUNCATE))
3678 return SelectTrunc(I);
3680 case Instruction::FPExt:
3681 return SelectFPExt(I);
3682 case Instruction::FPTrunc:
3683 return SelectFPTrunc(I);
3684 case Instruction::SIToFP:
3685 if (!selectCast(I, ISD::SINT_TO_FP))
3686 return SelectIntToFP(I, /*Signed=*/true);
3688 case Instruction::UIToFP:
3689 return SelectIntToFP(I, /*Signed=*/false);
3690 case Instruction::Load:
3691 return SelectLoad(I);
3692 case Instruction::Store:
3693 return SelectStore(I);
3694 case Instruction::FCmp:
3695 case Instruction::ICmp:
3696 return SelectCmp(I);
3697 case Instruction::Select:
3698 return SelectSelect(I);
3699 case Instruction::Ret:
3700 return SelectRet(I);
3703 // fall-back to target-independent instruction selection.
3704 return selectOperator(I, I->getOpcode());
3705 // Silence warnings.
3706 (void)&CC_AArch64_DarwinPCS_VarArg;
3710 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
3711 const TargetLibraryInfo *libInfo) {
3712 return new AArch64FastISel(funcInfo, libInfo);