1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/CommandLine.h"
43 class AArch64FastISel final : public FastISel {
53 AArch64_AM::ShiftExtendType ExtType;
61 const GlobalValue *GV;
64 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
65 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
66 void setKind(BaseKind K) { Kind = K; }
67 BaseKind getKind() const { return Kind; }
68 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
69 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
70 bool isRegBase() const { return Kind == RegBase; }
71 bool isFIBase() const { return Kind == FrameIndexBase; }
72 void setReg(unsigned Reg) {
73 assert(isRegBase() && "Invalid base register access!");
76 unsigned getReg() const {
77 assert(isRegBase() && "Invalid base register access!");
80 void setOffsetReg(unsigned Reg) {
81 assert(isRegBase() && "Invalid offset register access!");
84 unsigned getOffsetReg() const {
85 assert(isRegBase() && "Invalid offset register access!");
88 void setFI(unsigned FI) {
89 assert(isFIBase() && "Invalid base frame index access!");
92 unsigned getFI() const {
93 assert(isFIBase() && "Invalid base frame index access!");
96 void setOffset(int64_t O) { Offset = O; }
97 int64_t getOffset() { return Offset; }
98 void setShift(unsigned S) { Shift = S; }
99 unsigned getShift() { return Shift; }
101 void setGlobalValue(const GlobalValue *G) { GV = G; }
102 const GlobalValue *getGlobalValue() { return GV; }
105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
106 /// make the right decision when generating code for different targets.
107 const AArch64Subtarget *Subtarget;
108 LLVMContext *Context;
110 bool fastLowerArguments() override;
111 bool fastLowerCall(CallLoweringInfo &CLI) override;
112 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
115 // Selection routines.
116 bool selectAddSub(const Instruction *I);
117 bool selectLogicalOp(const Instruction *I);
118 bool selectLoad(const Instruction *I);
119 bool selectStore(const Instruction *I);
120 bool selectBranch(const Instruction *I);
121 bool selectIndirectBr(const Instruction *I);
122 bool selectCmp(const Instruction *I);
123 bool selectSelect(const Instruction *I);
124 bool selectFPExt(const Instruction *I);
125 bool selectFPTrunc(const Instruction *I);
126 bool selectFPToInt(const Instruction *I, bool Signed);
127 bool selectIntToFP(const Instruction *I, bool Signed);
128 bool selectRem(const Instruction *I, unsigned ISDOpcode);
129 bool selectRet(const Instruction *I);
130 bool selectTrunc(const Instruction *I);
131 bool selectIntExt(const Instruction *I);
132 bool selectMul(const Instruction *I);
133 bool selectShift(const Instruction *I);
134 bool selectBitCast(const Instruction *I);
135 bool selectFRem(const Instruction *I);
136 bool selectSDiv(const Instruction *I);
137 bool selectGetElementPtr(const Instruction *I);
139 // Utility helper routines.
140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
142 bool isValueAvailable(const Value *V) const;
143 bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
144 bool computeCallAddress(const Value *V, Address &Addr);
145 bool simplifyAddress(Address &Addr, MVT VT);
146 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
147 unsigned Flags, unsigned ScaleFactor,
148 MachineMemOperand *MMO);
149 bool isMemCpySmall(uint64_t Len, unsigned Alignment);
150 bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
152 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
154 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
156 // Emit helper routines.
157 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
158 const Value *RHS, bool SetFlags = false,
159 bool WantResult = true, bool IsZExt = false);
160 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
161 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
162 bool SetFlags = false, bool WantResult = true);
163 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
165 bool WantResult = true);
166 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
168 AArch64_AM::ShiftExtendType ShiftType,
169 uint64_t ShiftImm, bool SetFlags = false,
170 bool WantResult = true);
171 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
173 AArch64_AM::ShiftExtendType ExtType,
174 uint64_t ShiftImm, bool SetFlags = false,
175 bool WantResult = true);
178 bool emitCompareAndBranch(const BranchInst *BI);
179 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
180 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
181 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
182 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
183 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
184 MachineMemOperand *MMO = nullptr);
185 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
186 MachineMemOperand *MMO = nullptr);
187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
190 bool SetFlags = false, bool WantResult = true,
191 bool IsZExt = false);
192 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
193 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
194 bool SetFlags = false, bool WantResult = true,
195 bool IsZExt = false);
196 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
197 unsigned RHSReg, bool RHSIsKill, bool WantResult = true);
198 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199 unsigned RHSReg, bool RHSIsKill,
200 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
201 bool WantResult = true);
202 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
204 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
205 bool LHSIsKill, uint64_t Imm);
206 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
207 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
209 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
210 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
211 unsigned Op1, bool Op1IsKill);
212 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213 unsigned Op1, bool Op1IsKill);
214 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215 unsigned Op1, bool Op1IsKill);
216 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
217 unsigned Op1Reg, bool Op1IsKill);
218 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
219 uint64_t Imm, bool IsZExt = true);
220 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
221 unsigned Op1Reg, bool Op1IsKill);
222 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
223 uint64_t Imm, bool IsZExt = true);
224 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
225 unsigned Op1Reg, bool Op1IsKill);
226 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
227 uint64_t Imm, bool IsZExt = false);
229 unsigned materializeInt(const ConstantInt *CI, MVT VT);
230 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
231 unsigned materializeGV(const GlobalValue *GV);
233 // Call handling routines.
235 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
236 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
238 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
241 // Backend specific FastISel code.
242 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
243 unsigned fastMaterializeConstant(const Constant *C) override;
244 unsigned fastMaterializeFloatZero(const ConstantFP* CF) override;
246 explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
247 const TargetLibraryInfo *LibInfo)
248 : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
249 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
250 Context = &FuncInfo.Fn->getContext();
253 bool fastSelectInstruction(const Instruction *I) override;
255 #include "AArch64GenFastISel.inc"
258 } // end anonymous namespace
260 #include "AArch64GenCallingConv.inc"
262 /// \brief Check if the sign-/zero-extend will be a noop.
263 static bool isIntExtFree(const Instruction *I) {
264 assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
265 "Unexpected integer extend instruction.");
266 assert(!I->getType()->isVectorTy() && I->getType()->isIntegerTy() &&
267 "Unexpected value type.");
268 bool IsZExt = isa<ZExtInst>(I);
270 if (const auto *LI = dyn_cast<LoadInst>(I->getOperand(0)))
274 if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0)))
275 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
281 /// \brief Determine the implicit scale factor that is applied by a memory
282 /// operation for a given value type.
283 static unsigned getImplicitScaleFactor(MVT VT) {
284 switch (VT.SimpleTy) {
287 case MVT::i1: // fall-through
292 case MVT::i32: // fall-through
295 case MVT::i64: // fall-through
301 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
302 if (CC == CallingConv::WebKit_JS)
303 return CC_AArch64_WebKit_JS;
304 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
307 unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
308 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
309 "Alloca should always return a pointer.");
311 // Don't handle dynamic allocas.
312 if (!FuncInfo.StaticAllocaMap.count(AI))
315 DenseMap<const AllocaInst *, int>::iterator SI =
316 FuncInfo.StaticAllocaMap.find(AI);
318 if (SI != FuncInfo.StaticAllocaMap.end()) {
319 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
322 .addFrameIndex(SI->second)
331 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
336 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
338 // Create a copy from the zero register to materialize a "0" value.
339 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
340 : &AArch64::GPR32RegClass;
341 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
342 unsigned ResultReg = createResultReg(RC);
343 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
344 ResultReg).addReg(ZeroReg, getKillRegState(true));
348 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
349 // Positive zero (+0.0) has to be materialized with a fmov from the zero
350 // register, because the immediate version of fmov cannot encode zero.
351 if (CFP->isNullValue())
352 return fastMaterializeFloatZero(CFP);
354 if (VT != MVT::f32 && VT != MVT::f64)
357 const APFloat Val = CFP->getValueAPF();
358 bool Is64Bit = (VT == MVT::f64);
359 // This checks to see if we can use FMOV instructions to materialize
360 // a constant, otherwise we have to materialize via the constant pool.
361 if (TLI.isFPImmLegal(Val, VT)) {
363 Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
364 assert((Imm != -1) && "Cannot encode floating-point constant.");
365 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
366 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
369 // Materialize via constant pool. MachineConstantPool wants an explicit
371 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
373 Align = DL.getTypeAllocSize(CFP->getType());
375 unsigned CPI = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
376 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
377 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
378 ADRPReg).addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGE);
380 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui;
381 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
382 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
384 .addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
388 unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
389 // We can't handle thread-local variables quickly yet.
390 if (GV->isThreadLocal())
393 // MachO still uses GOT for large code-model accesses, but ELF requires
394 // movz/movk sequences, which FastISel doesn't handle yet.
395 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
398 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
400 EVT DestEVT = TLI.getValueType(GV->getType(), true);
401 if (!DestEVT.isSimple())
404 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
407 if (OpFlags & AArch64II::MO_GOT) {
409 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
411 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
413 ResultReg = createResultReg(&AArch64::GPR64RegClass);
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
417 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
419 } else if (OpFlags & AArch64II::MO_CONSTPOOL) {
420 // We can't handle addresses loaded from a constant pool quickly yet.
424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
426 .addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
428 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
429 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
432 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
438 unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
439 EVT CEVT = TLI.getValueType(C->getType(), true);
441 // Only handle simple types.
442 if (!CEVT.isSimple())
444 MVT VT = CEVT.getSimpleVT();
446 if (const auto *CI = dyn_cast<ConstantInt>(C))
447 return materializeInt(CI, VT);
448 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
449 return materializeFP(CFP, VT);
450 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
451 return materializeGV(GV);
456 unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
457 assert(CFP->isNullValue() &&
458 "Floating-point constant is not a positive zero.");
460 if (!isTypeLegal(CFP->getType(), VT))
463 if (VT != MVT::f32 && VT != MVT::f64)
466 bool Is64Bit = (VT == MVT::f64);
467 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
468 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
469 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
472 /// \brief Check if the multiply is by a power-of-2 constant.
473 static bool isMulPowOf2(const Value *I) {
474 if (const auto *MI = dyn_cast<MulOperator>(I)) {
475 if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(0)))
476 if (C->getValue().isPowerOf2())
478 if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(1)))
479 if (C->getValue().isPowerOf2())
485 // Computes the address to get to an object.
486 bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
488 const User *U = nullptr;
489 unsigned Opcode = Instruction::UserOp1;
490 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
491 // Don't walk into other basic blocks unless the object is an alloca from
492 // another block, otherwise it may not have a virtual register assigned.
493 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
494 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
495 Opcode = I->getOpcode();
498 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
499 Opcode = C->getOpcode();
503 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
504 if (Ty->getAddressSpace() > 255)
505 // Fast instruction selection doesn't support the special
512 case Instruction::BitCast: {
513 // Look through bitcasts.
514 return computeAddress(U->getOperand(0), Addr, Ty);
516 case Instruction::IntToPtr: {
517 // Look past no-op inttoptrs.
518 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
519 return computeAddress(U->getOperand(0), Addr, Ty);
522 case Instruction::PtrToInt: {
523 // Look past no-op ptrtoints.
524 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
525 return computeAddress(U->getOperand(0), Addr, Ty);
528 case Instruction::GetElementPtr: {
529 Address SavedAddr = Addr;
530 uint64_t TmpOffset = Addr.getOffset();
532 // Iterate through the GEP folding the constants into offsets where
534 gep_type_iterator GTI = gep_type_begin(U);
535 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
537 const Value *Op = *i;
538 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
539 const StructLayout *SL = DL.getStructLayout(STy);
540 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
541 TmpOffset += SL->getElementOffset(Idx);
543 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
545 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
546 // Constant-offset addressing.
547 TmpOffset += CI->getSExtValue() * S;
550 if (canFoldAddIntoGEP(U, Op)) {
551 // A compatible add with a constant operand. Fold the constant.
553 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
554 TmpOffset += CI->getSExtValue() * S;
555 // Iterate on the other operand.
556 Op = cast<AddOperator>(Op)->getOperand(0);
560 goto unsupported_gep;
565 // Try to grab the base operand now.
566 Addr.setOffset(TmpOffset);
567 if (computeAddress(U->getOperand(0), Addr, Ty))
570 // We failed, restore everything and try the other options.
576 case Instruction::Alloca: {
577 const AllocaInst *AI = cast<AllocaInst>(Obj);
578 DenseMap<const AllocaInst *, int>::iterator SI =
579 FuncInfo.StaticAllocaMap.find(AI);
580 if (SI != FuncInfo.StaticAllocaMap.end()) {
581 Addr.setKind(Address::FrameIndexBase);
582 Addr.setFI(SI->second);
587 case Instruction::Add: {
588 // Adds of constants are common and easy enough.
589 const Value *LHS = U->getOperand(0);
590 const Value *RHS = U->getOperand(1);
592 if (isa<ConstantInt>(LHS))
595 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
596 Addr.setOffset(Addr.getOffset() + CI->getSExtValue());
597 return computeAddress(LHS, Addr, Ty);
600 Address Backup = Addr;
601 if (computeAddress(LHS, Addr, Ty) && computeAddress(RHS, Addr, Ty))
607 case Instruction::Sub: {
608 // Subs of constants are common and easy enough.
609 const Value *LHS = U->getOperand(0);
610 const Value *RHS = U->getOperand(1);
612 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
613 Addr.setOffset(Addr.getOffset() - CI->getSExtValue());
614 return computeAddress(LHS, Addr, Ty);
618 case Instruction::Shl: {
619 if (Addr.getOffsetReg())
622 const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1));
626 unsigned Val = CI->getZExtValue();
627 if (Val < 1 || Val > 3)
630 uint64_t NumBytes = 0;
631 if (Ty && Ty->isSized()) {
632 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
633 NumBytes = NumBits / 8;
634 if (!isPowerOf2_64(NumBits))
638 if (NumBytes != (1ULL << Val))
642 Addr.setExtendType(AArch64_AM::LSL);
644 const Value *Src = U->getOperand(0);
645 if (const auto *I = dyn_cast<Instruction>(Src))
646 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
649 // Fold the zext or sext when it won't become a noop.
650 if (const auto *ZE = dyn_cast<ZExtInst>(Src)) {
651 if (!isIntExtFree(ZE) && ZE->getOperand(0)->getType()->isIntegerTy(32)) {
652 Addr.setExtendType(AArch64_AM::UXTW);
653 Src = ZE->getOperand(0);
655 } else if (const auto *SE = dyn_cast<SExtInst>(Src)) {
656 if (!isIntExtFree(SE) && SE->getOperand(0)->getType()->isIntegerTy(32)) {
657 Addr.setExtendType(AArch64_AM::SXTW);
658 Src = SE->getOperand(0);
662 if (const auto *AI = dyn_cast<BinaryOperator>(Src))
663 if (AI->getOpcode() == Instruction::And) {
664 const Value *LHS = AI->getOperand(0);
665 const Value *RHS = AI->getOperand(1);
667 if (const auto *C = dyn_cast<ConstantInt>(LHS))
668 if (C->getValue() == 0xffffffff)
671 if (const auto *C = dyn_cast<ConstantInt>(RHS))
672 if (C->getValue() == 0xffffffff) {
673 Addr.setExtendType(AArch64_AM::UXTW);
674 unsigned Reg = getRegForValue(LHS);
677 bool RegIsKill = hasTrivialKill(LHS);
678 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
680 Addr.setOffsetReg(Reg);
685 unsigned Reg = getRegForValue(Src);
688 Addr.setOffsetReg(Reg);
691 case Instruction::Mul: {
692 if (Addr.getOffsetReg())
698 const Value *LHS = U->getOperand(0);
699 const Value *RHS = U->getOperand(1);
701 // Canonicalize power-of-2 value to the RHS.
702 if (const auto *C = dyn_cast<ConstantInt>(LHS))
703 if (C->getValue().isPowerOf2())
706 assert(isa<ConstantInt>(RHS) && "Expected an ConstantInt.");
707 const auto *C = cast<ConstantInt>(RHS);
708 unsigned Val = C->getValue().logBase2();
709 if (Val < 1 || Val > 3)
712 uint64_t NumBytes = 0;
713 if (Ty && Ty->isSized()) {
714 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
715 NumBytes = NumBits / 8;
716 if (!isPowerOf2_64(NumBits))
720 if (NumBytes != (1ULL << Val))
724 Addr.setExtendType(AArch64_AM::LSL);
726 const Value *Src = LHS;
727 if (const auto *I = dyn_cast<Instruction>(Src))
728 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
732 // Fold the zext or sext when it won't become a noop.
733 if (const auto *ZE = dyn_cast<ZExtInst>(Src)) {
734 if (!isIntExtFree(ZE) && ZE->getOperand(0)->getType()->isIntegerTy(32)) {
735 Addr.setExtendType(AArch64_AM::UXTW);
736 Src = ZE->getOperand(0);
738 } else if (const auto *SE = dyn_cast<SExtInst>(Src)) {
739 if (!isIntExtFree(SE) && SE->getOperand(0)->getType()->isIntegerTy(32)) {
740 Addr.setExtendType(AArch64_AM::SXTW);
741 Src = SE->getOperand(0);
745 unsigned Reg = getRegForValue(Src);
748 Addr.setOffsetReg(Reg);
751 case Instruction::And: {
752 if (Addr.getOffsetReg())
755 if (DL.getTypeSizeInBits(Ty) != 8)
758 const Value *LHS = U->getOperand(0);
759 const Value *RHS = U->getOperand(1);
761 if (const auto *C = dyn_cast<ConstantInt>(LHS))
762 if (C->getValue() == 0xffffffff)
765 if (const auto *C = dyn_cast<ConstantInt>(RHS))
766 if (C->getValue() == 0xffffffff) {
768 Addr.setExtendType(AArch64_AM::LSL);
769 Addr.setExtendType(AArch64_AM::UXTW);
771 unsigned Reg = getRegForValue(LHS);
774 bool RegIsKill = hasTrivialKill(LHS);
775 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
777 Addr.setOffsetReg(Reg);
782 case Instruction::SExt:
783 case Instruction::ZExt: {
784 if (!Addr.getReg() || Addr.getOffsetReg())
787 const Value *Src = nullptr;
788 // Fold the zext or sext when it won't become a noop.
789 if (const auto *ZE = dyn_cast<ZExtInst>(U)) {
790 if (!isIntExtFree(ZE) && ZE->getOperand(0)->getType()->isIntegerTy(32)) {
791 Addr.setExtendType(AArch64_AM::UXTW);
792 Src = ZE->getOperand(0);
794 } else if (const auto *SE = dyn_cast<SExtInst>(U)) {
795 if (!isIntExtFree(SE) && SE->getOperand(0)->getType()->isIntegerTy(32)) {
796 Addr.setExtendType(AArch64_AM::SXTW);
797 Src = SE->getOperand(0);
805 unsigned Reg = getRegForValue(Src);
808 Addr.setOffsetReg(Reg);
814 if (!Addr.getOffsetReg()) {
815 unsigned Reg = getRegForValue(Obj);
818 Addr.setOffsetReg(Reg);
824 unsigned Reg = getRegForValue(Obj);
831 bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
832 const User *U = nullptr;
833 unsigned Opcode = Instruction::UserOp1;
836 if (const auto *I = dyn_cast<Instruction>(V)) {
837 Opcode = I->getOpcode();
839 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
840 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
841 Opcode = C->getOpcode();
847 case Instruction::BitCast:
848 // Look past bitcasts if its operand is in the same BB.
850 return computeCallAddress(U->getOperand(0), Addr);
852 case Instruction::IntToPtr:
853 // Look past no-op inttoptrs if its operand is in the same BB.
855 TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
856 return computeCallAddress(U->getOperand(0), Addr);
858 case Instruction::PtrToInt:
859 // Look past no-op ptrtoints if its operand is in the same BB.
861 TLI.getValueType(U->getType()) == TLI.getPointerTy())
862 return computeCallAddress(U->getOperand(0), Addr);
866 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
867 Addr.setGlobalValue(GV);
871 // If all else fails, try to materialize the value in a register.
872 if (!Addr.getGlobalValue()) {
873 Addr.setReg(getRegForValue(V));
874 return Addr.getReg() != 0;
881 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
882 EVT evt = TLI.getValueType(Ty, true);
884 // Only handle simple types.
885 if (evt == MVT::Other || !evt.isSimple())
887 VT = evt.getSimpleVT();
889 // This is a legal type, but it's not something we handle in fast-isel.
893 // Handle all other legal types, i.e. a register that will directly hold this
895 return TLI.isTypeLegal(VT);
898 /// \brief Determine if the value type is supported by FastISel.
900 /// FastISel for AArch64 can handle more value types than are legal. This adds
901 /// simple value type such as i1, i8, and i16.
902 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
903 if (Ty->isVectorTy() && !IsVectorAllowed)
906 if (isTypeLegal(Ty, VT))
909 // If this is a type than can be sign or zero-extended to a basic operation
910 // go ahead and accept it now.
911 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
917 bool AArch64FastISel::isValueAvailable(const Value *V) const {
918 if (!isa<Instruction>(V))
921 const auto *I = cast<Instruction>(V);
922 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
928 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
929 unsigned ScaleFactor = getImplicitScaleFactor(VT);
933 bool ImmediateOffsetNeedsLowering = false;
934 bool RegisterOffsetNeedsLowering = false;
935 int64_t Offset = Addr.getOffset();
936 if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
937 ImmediateOffsetNeedsLowering = true;
938 else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
939 !isUInt<12>(Offset / ScaleFactor))
940 ImmediateOffsetNeedsLowering = true;
942 // Cannot encode an offset register and an immediate offset in the same
943 // instruction. Fold the immediate offset into the load/store instruction and
944 // emit an additonal add to take care of the offset register.
945 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.isRegBase() &&
947 RegisterOffsetNeedsLowering = true;
949 // Cannot encode zero register as base.
950 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())
951 RegisterOffsetNeedsLowering = true;
953 // If this is a stack pointer and the offset needs to be simplified then put
954 // the alloca address into a register, set the base type back to register and
955 // continue. This should almost never happen.
956 if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
957 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
958 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
960 .addFrameIndex(Addr.getFI())
963 Addr.setKind(Address::RegBase);
964 Addr.setReg(ResultReg);
967 if (RegisterOffsetNeedsLowering) {
968 unsigned ResultReg = 0;
970 if (Addr.getExtendType() == AArch64_AM::SXTW ||
971 Addr.getExtendType() == AArch64_AM::UXTW )
972 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
973 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
974 /*TODO:IsKill=*/false, Addr.getExtendType(),
977 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
978 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
979 /*TODO:IsKill=*/false, AArch64_AM::LSL,
982 if (Addr.getExtendType() == AArch64_AM::UXTW)
983 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
984 /*Op0IsKill=*/false, Addr.getShift(),
986 else if (Addr.getExtendType() == AArch64_AM::SXTW)
987 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
988 /*Op0IsKill=*/false, Addr.getShift(),
991 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
992 /*Op0IsKill=*/false, Addr.getShift());
997 Addr.setReg(ResultReg);
998 Addr.setOffsetReg(0);
1000 Addr.setExtendType(AArch64_AM::InvalidShiftExtend);
1003 // Since the offset is too large for the load/store instruction get the
1004 // reg+offset into a register.
1005 if (ImmediateOffsetNeedsLowering) {
1008 // Try to fold the immediate into the add instruction.
1009 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset);
1011 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
1015 Addr.setReg(ResultReg);
1021 void AArch64FastISel::addLoadStoreOperands(Address &Addr,
1022 const MachineInstrBuilder &MIB,
1024 unsigned ScaleFactor,
1025 MachineMemOperand *MMO) {
1026 int64_t Offset = Addr.getOffset() / ScaleFactor;
1027 // Frame base works a bit differently. Handle it separately.
1028 if (Addr.isFIBase()) {
1029 int FI = Addr.getFI();
1030 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
1031 // and alignment should be based on the VT.
1032 MMO = FuncInfo.MF->getMachineMemOperand(
1033 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
1034 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
1035 // Now add the rest of the operands.
1036 MIB.addFrameIndex(FI).addImm(Offset);
1038 assert(Addr.isRegBase() && "Unexpected address kind.");
1039 const MCInstrDesc &II = MIB->getDesc();
1040 unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
1042 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
1044 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
1045 if (Addr.getOffsetReg()) {
1046 assert(Addr.getOffset() == 0 && "Unexpected offset");
1047 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
1048 Addr.getExtendType() == AArch64_AM::SXTX;
1049 MIB.addReg(Addr.getReg());
1050 MIB.addReg(Addr.getOffsetReg());
1051 MIB.addImm(IsSigned);
1052 MIB.addImm(Addr.getShift() != 0);
1054 MIB.addReg(Addr.getReg());
1060 MIB.addMemOperand(MMO);
1063 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1064 const Value *RHS, bool SetFlags,
1065 bool WantResult, bool IsZExt) {
1066 AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
1067 bool NeedExtend = false;
1068 switch (RetVT.SimpleTy) {
1076 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1080 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1082 case MVT::i32: // fall-through
1087 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1089 // Canonicalize immediates to the RHS first.
1090 if (UseAdd && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
1091 std::swap(LHS, RHS);
1093 // Canonicalize mul by power of 2 to the RHS.
1094 if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1095 if (isMulPowOf2(LHS))
1096 std::swap(LHS, RHS);
1098 // Canonicalize shift immediate to the RHS.
1099 if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1100 if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
1101 if (isa<ConstantInt>(SI->getOperand(1)))
1102 if (SI->getOpcode() == Instruction::Shl ||
1103 SI->getOpcode() == Instruction::LShr ||
1104 SI->getOpcode() == Instruction::AShr )
1105 std::swap(LHS, RHS);
1107 unsigned LHSReg = getRegForValue(LHS);
1110 bool LHSIsKill = hasTrivialKill(LHS);
1113 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1115 unsigned ResultReg = 0;
1116 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1117 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1118 if (C->isNegative())
1119 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1120 SetFlags, WantResult);
1122 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1128 // Only extend the RHS within the instruction if there is a valid extend type.
1129 if (ExtendType != AArch64_AM::InvalidShiftExtend && RHS->hasOneUse() &&
1130 isValueAvailable(RHS)) {
1131 if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
1132 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
1133 if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
1134 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1137 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1138 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1139 RHSIsKill, ExtendType, C->getZExtValue(),
1140 SetFlags, WantResult);
1142 unsigned RHSReg = getRegForValue(RHS);
1145 bool RHSIsKill = hasTrivialKill(RHS);
1146 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1147 ExtendType, 0, SetFlags, WantResult);
1150 // Check if the mul can be folded into the instruction.
1151 if (RHS->hasOneUse() && isValueAvailable(RHS))
1152 if (isMulPowOf2(RHS)) {
1153 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0);
1154 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1);
1156 if (const auto *C = dyn_cast<ConstantInt>(MulLHS))
1157 if (C->getValue().isPowerOf2())
1158 std::swap(MulLHS, MulRHS);
1160 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1161 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1162 unsigned RHSReg = getRegForValue(MulLHS);
1165 bool RHSIsKill = hasTrivialKill(MulLHS);
1166 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1167 AArch64_AM::LSL, ShiftVal, SetFlags, WantResult);
1170 // Check if the shift can be folded into the instruction.
1171 if (RHS->hasOneUse() && isValueAvailable(RHS))
1172 if (const auto *SI = dyn_cast<BinaryOperator>(RHS)) {
1173 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
1174 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend;
1175 switch (SI->getOpcode()) {
1177 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
1178 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
1179 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break;
1181 uint64_t ShiftVal = C->getZExtValue();
1182 if (ShiftType != AArch64_AM::InvalidShiftExtend) {
1183 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1186 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1187 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1188 RHSIsKill, ShiftType, ShiftVal, SetFlags,
1194 unsigned RHSReg = getRegForValue(RHS);
1197 bool RHSIsKill = hasTrivialKill(RHS);
1200 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1202 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1203 SetFlags, WantResult);
1206 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1207 bool LHSIsKill, unsigned RHSReg,
1208 bool RHSIsKill, bool SetFlags,
1210 assert(LHSReg && RHSReg && "Invalid register number.");
1212 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1215 static const unsigned OpcTable[2][2][2] = {
1216 { { AArch64::SUBWrr, AArch64::SUBXrr },
1217 { AArch64::ADDWrr, AArch64::ADDXrr } },
1218 { { AArch64::SUBSWrr, AArch64::SUBSXrr },
1219 { AArch64::ADDSWrr, AArch64::ADDSXrr } }
1221 bool Is64Bit = RetVT == MVT::i64;
1222 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1223 const TargetRegisterClass *RC =
1224 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1227 ResultReg = createResultReg(RC);
1229 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1231 const MCInstrDesc &II = TII.get(Opc);
1232 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1233 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1235 .addReg(LHSReg, getKillRegState(LHSIsKill))
1236 .addReg(RHSReg, getKillRegState(RHSIsKill));
1240 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1241 bool LHSIsKill, uint64_t Imm,
1242 bool SetFlags, bool WantResult) {
1243 assert(LHSReg && "Invalid register number.");
1245 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1249 if (isUInt<12>(Imm))
1251 else if ((Imm & 0xfff000) == Imm) {
1257 static const unsigned OpcTable[2][2][2] = {
1258 { { AArch64::SUBWri, AArch64::SUBXri },
1259 { AArch64::ADDWri, AArch64::ADDXri } },
1260 { { AArch64::SUBSWri, AArch64::SUBSXri },
1261 { AArch64::ADDSWri, AArch64::ADDSXri } }
1263 bool Is64Bit = RetVT == MVT::i64;
1264 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1265 const TargetRegisterClass *RC;
1267 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1269 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1272 ResultReg = createResultReg(RC);
1274 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1276 const MCInstrDesc &II = TII.get(Opc);
1277 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1279 .addReg(LHSReg, getKillRegState(LHSIsKill))
1281 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1285 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1286 bool LHSIsKill, unsigned RHSReg,
1288 AArch64_AM::ShiftExtendType ShiftType,
1289 uint64_t ShiftImm, bool SetFlags,
1291 assert(LHSReg && RHSReg && "Invalid register number.");
1293 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1296 static const unsigned OpcTable[2][2][2] = {
1297 { { AArch64::SUBWrs, AArch64::SUBXrs },
1298 { AArch64::ADDWrs, AArch64::ADDXrs } },
1299 { { AArch64::SUBSWrs, AArch64::SUBSXrs },
1300 { AArch64::ADDSWrs, AArch64::ADDSXrs } }
1302 bool Is64Bit = RetVT == MVT::i64;
1303 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1304 const TargetRegisterClass *RC =
1305 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1308 ResultReg = createResultReg(RC);
1310 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1312 const MCInstrDesc &II = TII.get(Opc);
1313 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1314 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1315 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1316 .addReg(LHSReg, getKillRegState(LHSIsKill))
1317 .addReg(RHSReg, getKillRegState(RHSIsKill))
1318 .addImm(getShifterImm(ShiftType, ShiftImm));
1322 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1323 bool LHSIsKill, unsigned RHSReg,
1325 AArch64_AM::ShiftExtendType ExtType,
1326 uint64_t ShiftImm, bool SetFlags,
1328 assert(LHSReg && RHSReg && "Invalid register number.");
1330 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1333 static const unsigned OpcTable[2][2][2] = {
1334 { { AArch64::SUBWrx, AArch64::SUBXrx },
1335 { AArch64::ADDWrx, AArch64::ADDXrx } },
1336 { { AArch64::SUBSWrx, AArch64::SUBSXrx },
1337 { AArch64::ADDSWrx, AArch64::ADDSXrx } }
1339 bool Is64Bit = RetVT == MVT::i64;
1340 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1341 const TargetRegisterClass *RC = nullptr;
1343 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1345 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1348 ResultReg = createResultReg(RC);
1350 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1352 const MCInstrDesc &II = TII.get(Opc);
1353 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1354 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1355 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1356 .addReg(LHSReg, getKillRegState(LHSIsKill))
1357 .addReg(RHSReg, getKillRegState(RHSIsKill))
1358 .addImm(getArithExtendImm(ExtType, ShiftImm));
1362 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1363 Type *Ty = LHS->getType();
1364 EVT EVT = TLI.getValueType(Ty, true);
1365 if (!EVT.isSimple())
1367 MVT VT = EVT.getSimpleVT();
1369 switch (VT.SimpleTy) {
1377 return emitICmp(VT, LHS, RHS, IsZExt);
1380 return emitFCmp(VT, LHS, RHS);
1384 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1386 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1390 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1392 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1393 /*SetFlags=*/true, /*WantResult=*/false) != 0;
1396 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1397 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1400 // Check to see if the 2nd operand is a constant that we can encode directly
1402 bool UseImm = false;
1403 if (const auto *CFP = dyn_cast<ConstantFP>(RHS))
1404 if (CFP->isZero() && !CFP->isNegative())
1407 unsigned LHSReg = getRegForValue(LHS);
1410 bool LHSIsKill = hasTrivialKill(LHS);
1413 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1415 .addReg(LHSReg, getKillRegState(LHSIsKill));
1419 unsigned RHSReg = getRegForValue(RHS);
1422 bool RHSIsKill = hasTrivialKill(RHS);
1424 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1425 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1426 .addReg(LHSReg, getKillRegState(LHSIsKill))
1427 .addReg(RHSReg, getKillRegState(RHSIsKill));
1431 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1432 bool SetFlags, bool WantResult, bool IsZExt) {
1433 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1437 /// \brief This method is a wrapper to simplify add emission.
1439 /// First try to emit an add with an immediate operand using emitAddSub_ri. If
1440 /// that fails, then try to materialize the immediate into a register and use
1441 /// emitAddSub_rr instead.
1442 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,
1446 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1448 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1453 unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm);
1457 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
1461 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1462 bool SetFlags, bool WantResult, bool IsZExt) {
1463 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1467 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1468 bool LHSIsKill, unsigned RHSReg,
1469 bool RHSIsKill, bool WantResult) {
1470 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1471 RHSIsKill, /*SetFlags=*/true, WantResult);
1474 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1475 bool LHSIsKill, unsigned RHSReg,
1477 AArch64_AM::ShiftExtendType ShiftType,
1478 uint64_t ShiftImm, bool WantResult) {
1479 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1480 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true,
1484 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1485 const Value *LHS, const Value *RHS) {
1486 // Canonicalize immediates to the RHS first.
1487 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
1488 std::swap(LHS, RHS);
1490 // Canonicalize mul by power-of-2 to the RHS.
1491 if (LHS->hasOneUse() && isValueAvailable(LHS))
1492 if (isMulPowOf2(LHS))
1493 std::swap(LHS, RHS);
1495 // Canonicalize shift immediate to the RHS.
1496 if (LHS->hasOneUse() && isValueAvailable(LHS))
1497 if (const auto *SI = dyn_cast<ShlOperator>(LHS))
1498 if (isa<ConstantInt>(SI->getOperand(1)))
1499 std::swap(LHS, RHS);
1501 unsigned LHSReg = getRegForValue(LHS);
1504 bool LHSIsKill = hasTrivialKill(LHS);
1506 unsigned ResultReg = 0;
1507 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1508 uint64_t Imm = C->getZExtValue();
1509 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1514 // Check if the mul can be folded into the instruction.
1515 if (RHS->hasOneUse() && isValueAvailable(RHS))
1516 if (isMulPowOf2(RHS)) {
1517 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0);
1518 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1);
1520 if (const auto *C = dyn_cast<ConstantInt>(MulLHS))
1521 if (C->getValue().isPowerOf2())
1522 std::swap(MulLHS, MulRHS);
1524 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1525 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1527 unsigned RHSReg = getRegForValue(MulLHS);
1530 bool RHSIsKill = hasTrivialKill(MulLHS);
1531 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1532 RHSIsKill, ShiftVal);
1535 // Check if the shift can be folded into the instruction.
1536 if (RHS->hasOneUse() && isValueAvailable(RHS))
1537 if (const auto *SI = dyn_cast<ShlOperator>(RHS))
1538 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
1539 uint64_t ShiftVal = C->getZExtValue();
1540 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1543 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1544 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1545 RHSIsKill, ShiftVal);
1548 unsigned RHSReg = getRegForValue(RHS);
1551 bool RHSIsKill = hasTrivialKill(RHS);
1553 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1554 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1555 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1556 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1557 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1562 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1563 unsigned LHSReg, bool LHSIsKill,
1565 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1566 "ISD nodes are not consecutive!");
1567 static const unsigned OpcTable[3][2] = {
1568 { AArch64::ANDWri, AArch64::ANDXri },
1569 { AArch64::ORRWri, AArch64::ORRXri },
1570 { AArch64::EORWri, AArch64::EORXri }
1572 const TargetRegisterClass *RC;
1575 switch (RetVT.SimpleTy) {
1582 unsigned Idx = ISDOpc - ISD::AND;
1583 Opc = OpcTable[Idx][0];
1584 RC = &AArch64::GPR32spRegClass;
1589 Opc = OpcTable[ISDOpc - ISD::AND][1];
1590 RC = &AArch64::GPR64spRegClass;
1595 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1598 unsigned ResultReg =
1599 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,
1600 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
1601 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1602 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1603 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1608 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1609 unsigned LHSReg, bool LHSIsKill,
1610 unsigned RHSReg, bool RHSIsKill,
1611 uint64_t ShiftImm) {
1612 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1613 "ISD nodes are not consecutive!");
1614 static const unsigned OpcTable[3][2] = {
1615 { AArch64::ANDWrs, AArch64::ANDXrs },
1616 { AArch64::ORRWrs, AArch64::ORRXrs },
1617 { AArch64::EORWrs, AArch64::EORXrs }
1619 const TargetRegisterClass *RC;
1621 switch (RetVT.SimpleTy) {
1628 Opc = OpcTable[ISDOpc - ISD::AND][0];
1629 RC = &AArch64::GPR32RegClass;
1632 Opc = OpcTable[ISDOpc - ISD::AND][1];
1633 RC = &AArch64::GPR64RegClass;
1636 unsigned ResultReg =
1637 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1638 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
1639 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1640 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1641 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1646 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1648 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1651 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1652 bool WantZExt, MachineMemOperand *MMO) {
1653 // Simplify this down to something we can handle.
1654 if (!simplifyAddress(Addr, VT))
1657 unsigned ScaleFactor = getImplicitScaleFactor(VT);
1659 llvm_unreachable("Unexpected value type.");
1661 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1662 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1663 bool UseScaled = true;
1664 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1669 static const unsigned GPOpcTable[2][8][4] = {
1671 { { AArch64::LDURSBWi, AArch64::LDURSHWi, AArch64::LDURWi,
1673 { AArch64::LDURSBXi, AArch64::LDURSHXi, AArch64::LDURSWi,
1675 { AArch64::LDRSBWui, AArch64::LDRSHWui, AArch64::LDRWui,
1677 { AArch64::LDRSBXui, AArch64::LDRSHXui, AArch64::LDRSWui,
1679 { AArch64::LDRSBWroX, AArch64::LDRSHWroX, AArch64::LDRWroX,
1681 { AArch64::LDRSBXroX, AArch64::LDRSHXroX, AArch64::LDRSWroX,
1683 { AArch64::LDRSBWroW, AArch64::LDRSHWroW, AArch64::LDRWroW,
1685 { AArch64::LDRSBXroW, AArch64::LDRSHXroW, AArch64::LDRSWroW,
1689 { { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
1691 { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
1693 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
1695 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
1697 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
1699 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
1701 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
1703 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
1708 static const unsigned FPOpcTable[4][2] = {
1709 { AArch64::LDURSi, AArch64::LDURDi },
1710 { AArch64::LDRSui, AArch64::LDRDui },
1711 { AArch64::LDRSroX, AArch64::LDRDroX },
1712 { AArch64::LDRSroW, AArch64::LDRDroW }
1716 const TargetRegisterClass *RC;
1717 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1718 Addr.getOffsetReg();
1719 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1720 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1721 Addr.getExtendType() == AArch64_AM::SXTW)
1724 bool IsRet64Bit = RetVT == MVT::i64;
1725 switch (VT.SimpleTy) {
1727 llvm_unreachable("Unexpected value type.");
1728 case MVT::i1: // Intentional fall-through.
1730 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][0];
1731 RC = (IsRet64Bit && !WantZExt) ?
1732 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1735 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][1];
1736 RC = (IsRet64Bit && !WantZExt) ?
1737 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1740 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][2];
1741 RC = (IsRet64Bit && !WantZExt) ?
1742 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1745 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][3];
1746 RC = &AArch64::GPR64RegClass;
1749 Opc = FPOpcTable[Idx][0];
1750 RC = &AArch64::FPR32RegClass;
1753 Opc = FPOpcTable[Idx][1];
1754 RC = &AArch64::FPR64RegClass;
1758 // Create the base instruction, then add the operands.
1759 unsigned ResultReg = createResultReg(RC);
1760 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1761 TII.get(Opc), ResultReg);
1762 addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
1764 // Loading an i1 requires special handling.
1765 if (VT == MVT::i1) {
1766 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1767 assert(ANDReg && "Unexpected AND instruction emission failure.");
1771 // For zero-extending loads to 64bit we emit a 32bit load and then convert
1772 // the 32bit reg to a 64bit reg.
1773 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
1774 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
1775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1776 TII.get(AArch64::SUBREG_TO_REG), Reg64)
1778 .addReg(ResultReg, getKillRegState(true))
1779 .addImm(AArch64::sub_32);
1785 bool AArch64FastISel::selectAddSub(const Instruction *I) {
1787 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1791 return selectOperator(I, I->getOpcode());
1794 switch (I->getOpcode()) {
1796 llvm_unreachable("Unexpected instruction.");
1797 case Instruction::Add:
1798 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1800 case Instruction::Sub:
1801 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1807 updateValueMap(I, ResultReg);
1811 bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
1813 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1817 return selectOperator(I, I->getOpcode());
1820 switch (I->getOpcode()) {
1822 llvm_unreachable("Unexpected instruction.");
1823 case Instruction::And:
1824 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1826 case Instruction::Or:
1827 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1829 case Instruction::Xor:
1830 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1836 updateValueMap(I, ResultReg);
1840 bool AArch64FastISel::selectLoad(const Instruction *I) {
1842 // Verify we have a legal type before going any further. Currently, we handle
1843 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1844 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1845 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) ||
1846 cast<LoadInst>(I)->isAtomic())
1849 // See if we can handle this address.
1851 if (!computeAddress(I->getOperand(0), Addr, I->getType()))
1854 // Fold the following sign-/zero-extend into the load instruction.
1855 bool WantZExt = true;
1857 const Value *IntExtVal = nullptr;
1858 if (I->hasOneUse()) {
1859 if (const auto *ZE = dyn_cast<ZExtInst>(I->use_begin()->getUser())) {
1860 if (isTypeSupported(ZE->getType(), RetVT))
1864 } else if (const auto *SE = dyn_cast<SExtInst>(I->use_begin()->getUser())) {
1865 if (isTypeSupported(SE->getType(), RetVT))
1873 unsigned ResultReg =
1874 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
1878 // There are a few different cases we have to handle, because the load or the
1879 // sign-/zero-extend might not be selected by FastISel if we fall-back to
1880 // SelectionDAG. There is also an ordering issue when both instructions are in
1881 // different basic blocks.
1882 // 1.) The load instruction is selected by FastISel, but the integer extend
1883 // not. This usually happens when the integer extend is in a different
1884 // basic block and SelectionDAG took over for that basic block.
1885 // 2.) The load instruction is selected before the integer extend. This only
1886 // happens when the integer extend is in a different basic block.
1887 // 3.) The load instruction is selected by SelectionDAG and the integer extend
1888 // by FastISel. This happens if there are instructions between the load
1889 // and the integer extend that couldn't be selected by FastISel.
1891 // The integer extend hasn't been emitted yet. FastISel or SelectionDAG
1892 // could select it. Emit a copy to subreg if necessary. FastISel will remove
1893 // it when it selects the integer extend.
1894 unsigned Reg = lookUpRegForValue(IntExtVal);
1896 if (RetVT == MVT::i64 && VT <= MVT::i32) {
1898 // Delete the last emitted instruction from emitLoad (SUBREG_TO_REG).
1899 std::prev(FuncInfo.InsertPt)->eraseFromParent();
1900 ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg();
1902 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
1906 updateValueMap(I, ResultReg);
1910 // The integer extend has already been emitted - delete all the instructions
1911 // that have been emitted by the integer extend lowering code and use the
1912 // result from the load instruction directly.
1914 auto *MI = MRI.getUniqueVRegDef(Reg);
1918 for (auto &Opnd : MI->uses()) {
1920 Reg = Opnd.getReg();
1924 MI->eraseFromParent();
1926 updateValueMap(IntExtVal, ResultReg);
1930 updateValueMap(I, ResultReg);
1934 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
1935 MachineMemOperand *MMO) {
1936 // Simplify this down to something we can handle.
1937 if (!simplifyAddress(Addr, VT))
1940 unsigned ScaleFactor = getImplicitScaleFactor(VT);
1942 llvm_unreachable("Unexpected value type.");
1944 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1945 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1946 bool UseScaled = true;
1947 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1952 static const unsigned OpcTable[4][6] = {
1953 { AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
1954 AArch64::STURSi, AArch64::STURDi },
1955 { AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
1956 AArch64::STRSui, AArch64::STRDui },
1957 { AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
1958 AArch64::STRSroX, AArch64::STRDroX },
1959 { AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
1960 AArch64::STRSroW, AArch64::STRDroW }
1964 bool VTIsi1 = false;
1965 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1966 Addr.getOffsetReg();
1967 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1968 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1969 Addr.getExtendType() == AArch64_AM::SXTW)
1972 switch (VT.SimpleTy) {
1973 default: llvm_unreachable("Unexpected value type.");
1974 case MVT::i1: VTIsi1 = true;
1975 case MVT::i8: Opc = OpcTable[Idx][0]; break;
1976 case MVT::i16: Opc = OpcTable[Idx][1]; break;
1977 case MVT::i32: Opc = OpcTable[Idx][2]; break;
1978 case MVT::i64: Opc = OpcTable[Idx][3]; break;
1979 case MVT::f32: Opc = OpcTable[Idx][4]; break;
1980 case MVT::f64: Opc = OpcTable[Idx][5]; break;
1983 // Storing an i1 requires special handling.
1984 if (VTIsi1 && SrcReg != AArch64::WZR) {
1985 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
1986 assert(ANDReg && "Unexpected AND instruction emission failure.");
1989 // Create the base instruction, then add the operands.
1990 const MCInstrDesc &II = TII.get(Opc);
1991 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
1992 MachineInstrBuilder MIB =
1993 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
1994 addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
1999 bool AArch64FastISel::selectStore(const Instruction *I) {
2001 const Value *Op0 = I->getOperand(0);
2002 // Verify we have a legal type before going any further. Currently, we handle
2003 // simple types that will directly fit in a register (i32/f32/i64/f64) or
2004 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
2005 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) ||
2006 cast<StoreInst>(I)->isAtomic())
2009 // Get the value to be stored into a register. Use the zero register directly
2010 // when possible to avoid an unnecessary copy and a wasted register.
2011 unsigned SrcReg = 0;
2012 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
2014 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2015 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
2016 if (CF->isZero() && !CF->isNegative()) {
2017 VT = MVT::getIntegerVT(VT.getSizeInBits());
2018 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2023 SrcReg = getRegForValue(Op0);
2028 // See if we can handle this address.
2030 if (!computeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
2033 if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
2038 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
2040 case CmpInst::FCMP_ONE:
2041 case CmpInst::FCMP_UEQ:
2043 // AL is our "false" for now. The other two need more compares.
2044 return AArch64CC::AL;
2045 case CmpInst::ICMP_EQ:
2046 case CmpInst::FCMP_OEQ:
2047 return AArch64CC::EQ;
2048 case CmpInst::ICMP_SGT:
2049 case CmpInst::FCMP_OGT:
2050 return AArch64CC::GT;
2051 case CmpInst::ICMP_SGE:
2052 case CmpInst::FCMP_OGE:
2053 return AArch64CC::GE;
2054 case CmpInst::ICMP_UGT:
2055 case CmpInst::FCMP_UGT:
2056 return AArch64CC::HI;
2057 case CmpInst::FCMP_OLT:
2058 return AArch64CC::MI;
2059 case CmpInst::ICMP_ULE:
2060 case CmpInst::FCMP_OLE:
2061 return AArch64CC::LS;
2062 case CmpInst::FCMP_ORD:
2063 return AArch64CC::VC;
2064 case CmpInst::FCMP_UNO:
2065 return AArch64CC::VS;
2066 case CmpInst::FCMP_UGE:
2067 return AArch64CC::PL;
2068 case CmpInst::ICMP_SLT:
2069 case CmpInst::FCMP_ULT:
2070 return AArch64CC::LT;
2071 case CmpInst::ICMP_SLE:
2072 case CmpInst::FCMP_ULE:
2073 return AArch64CC::LE;
2074 case CmpInst::FCMP_UNE:
2075 case CmpInst::ICMP_NE:
2076 return AArch64CC::NE;
2077 case CmpInst::ICMP_UGE:
2078 return AArch64CC::HS;
2079 case CmpInst::ICMP_ULT:
2080 return AArch64CC::LO;
2084 /// \brief Try to emit a combined compare-and-branch instruction.
2085 bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
2086 assert(isa<CmpInst>(BI->getCondition()) && "Expected cmp instruction");
2087 const CmpInst *CI = cast<CmpInst>(BI->getCondition());
2088 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2090 const Value *LHS = CI->getOperand(0);
2091 const Value *RHS = CI->getOperand(1);
2093 Type *Ty = LHS->getType();
2094 if (!Ty->isIntegerTy())
2097 unsigned BW = cast<IntegerType>(Ty)->getBitWidth();
2098 if (BW != 1 && BW != 8 && BW != 16 && BW != 32 && BW != 64)
2101 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
2102 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
2104 // Try to take advantage of fallthrough opportunities.
2105 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2106 std::swap(TBB, FBB);
2107 Predicate = CmpInst::getInversePredicate(Predicate);
2112 if ((Predicate == CmpInst::ICMP_EQ) || (Predicate == CmpInst::ICMP_NE)) {
2113 if (const auto *C = dyn_cast<ConstantInt>(LHS))
2114 if (C->isNullValue())
2115 std::swap(LHS, RHS);
2117 if (!isa<ConstantInt>(RHS))
2120 if (!cast<ConstantInt>(RHS)->isNullValue())
2123 if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
2124 if (AI->getOpcode() == Instruction::And) {
2125 const Value *AndLHS = AI->getOperand(0);
2126 const Value *AndRHS = AI->getOperand(1);
2128 if (const auto *C = dyn_cast<ConstantInt>(AndLHS))
2129 if (C->getValue().isPowerOf2())
2130 std::swap(AndLHS, AndRHS);
2132 if (const auto *C = dyn_cast<ConstantInt>(AndRHS))
2133 if (C->getValue().isPowerOf2()) {
2134 TestBit = C->getValue().logBase2();
2138 IsCmpNE = Predicate == CmpInst::ICMP_NE;
2139 } else if (Predicate == CmpInst::ICMP_SLT) {
2140 if (!isa<ConstantInt>(RHS))
2143 if (!cast<ConstantInt>(RHS)->isNullValue())
2148 } else if (Predicate == CmpInst::ICMP_SGT) {
2149 if (!isa<ConstantInt>(RHS))
2152 if (cast<ConstantInt>(RHS)->getValue() != -1)
2160 static const unsigned OpcTable[2][2][2] = {
2161 { {AArch64::CBZW, AArch64::CBZX },
2162 {AArch64::CBNZW, AArch64::CBNZX} },
2163 { {AArch64::TBZW, AArch64::TBZX },
2164 {AArch64::TBNZW, AArch64::TBNZX} }
2167 bool IsBitTest = TestBit != -1;
2168 bool Is64Bit = BW == 64;
2169 if (TestBit < 32 && TestBit >= 0)
2172 unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
2173 const MCInstrDesc &II = TII.get(Opc);
2175 unsigned SrcReg = getRegForValue(LHS);
2178 bool SrcIsKill = hasTrivialKill(LHS);
2180 if (BW == 64 && !Is64Bit)
2181 SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
2184 if ((BW < 32) && !IsBitTest) {
2185 EVT CmpEVT = TLI.getValueType(Ty, true);
2187 emitIntExt(CmpEVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ true);
2190 // Emit the combined compare and branch instruction.
2191 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
2192 MachineInstrBuilder MIB =
2193 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
2194 .addReg(SrcReg, getKillRegState(SrcIsKill));
2196 MIB.addImm(TestBit);
2199 // Obtain the branch weight and add the TrueBB to the successor list.
2200 uint32_t BranchWeight = 0;
2202 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2203 TBB->getBasicBlock());
2204 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2205 fastEmitBranch(FBB, DbgLoc);
2210 bool AArch64FastISel::selectBranch(const Instruction *I) {
2211 const BranchInst *BI = cast<BranchInst>(I);
2212 if (BI->isUnconditional()) {
2213 MachineBasicBlock *MSucc = FuncInfo.MBBMap[BI->getSuccessor(0)];
2214 fastEmitBranch(MSucc, BI->getDebugLoc());
2218 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
2219 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
2221 AArch64CC::CondCode CC = AArch64CC::NE;
2222 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
2223 if (CI->hasOneUse() && isValueAvailable(CI)) {
2224 // Try to optimize or fold the cmp.
2225 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2226 switch (Predicate) {
2229 case CmpInst::FCMP_FALSE:
2230 fastEmitBranch(FBB, DbgLoc);
2232 case CmpInst::FCMP_TRUE:
2233 fastEmitBranch(TBB, DbgLoc);
2237 // Try to emit a combined compare-and-branch first.
2238 if (emitCompareAndBranch(BI))
2241 // Try to take advantage of fallthrough opportunities.
2242 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2243 std::swap(TBB, FBB);
2244 Predicate = CmpInst::getInversePredicate(Predicate);
2248 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
2251 // FCMP_UEQ and FCMP_ONE cannot be checked with a single branch
2253 CC = getCompareCC(Predicate);
2254 AArch64CC::CondCode ExtraCC = AArch64CC::AL;
2255 switch (Predicate) {
2258 case CmpInst::FCMP_UEQ:
2259 ExtraCC = AArch64CC::EQ;
2262 case CmpInst::FCMP_ONE:
2263 ExtraCC = AArch64CC::MI;
2267 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2269 // Emit the extra branch for FCMP_UEQ and FCMP_ONE.
2270 if (ExtraCC != AArch64CC::AL) {
2271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2281 // Obtain the branch weight and add the TrueBB to the successor list.
2282 uint32_t BranchWeight = 0;
2284 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2285 TBB->getBasicBlock());
2286 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2288 fastEmitBranch(FBB, DbgLoc);
2291 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
2293 if (TI->hasOneUse() && isValueAvailable(TI) &&
2294 isTypeSupported(TI->getOperand(0)->getType(), SrcVT)) {
2295 unsigned CondReg = getRegForValue(TI->getOperand(0));
2298 bool CondIsKill = hasTrivialKill(TI->getOperand(0));
2300 // Issue an extract_subreg to get the lower 32-bits.
2301 if (SrcVT == MVT::i64) {
2302 CondReg = fastEmitInst_extractsubreg(MVT::i32, CondReg, CondIsKill,
2307 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
2308 assert(ANDReg && "Unexpected AND instruction emission failure.");
2309 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
2311 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2312 std::swap(TBB, FBB);
2315 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2319 // Obtain the branch weight and add the TrueBB to the successor list.
2320 uint32_t BranchWeight = 0;
2322 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2323 TBB->getBasicBlock());
2324 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2326 fastEmitBranch(FBB, DbgLoc);
2329 } else if (const auto *CI = dyn_cast<ConstantInt>(BI->getCondition())) {
2330 uint64_t Imm = CI->getZExtValue();
2331 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
2332 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
2335 // Obtain the branch weight and add the target to the successor list.
2336 uint32_t BranchWeight = 0;
2338 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2339 Target->getBasicBlock());
2340 FuncInfo.MBB->addSuccessor(Target, BranchWeight);
2342 } else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
2343 // Fake request the condition, otherwise the intrinsic might be completely
2345 unsigned CondReg = getRegForValue(BI->getCondition());
2350 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2354 // Obtain the branch weight and add the TrueBB to the successor list.
2355 uint32_t BranchWeight = 0;
2357 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2358 TBB->getBasicBlock());
2359 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2361 fastEmitBranch(FBB, DbgLoc);
2365 unsigned CondReg = getRegForValue(BI->getCondition());
2368 bool CondRegIsKill = hasTrivialKill(BI->getCondition());
2370 // We've been divorced from our compare! Our block was split, and
2371 // now our compare lives in a predecessor block. We musn't
2372 // re-compare here, as the children of the compare aren't guaranteed
2373 // live across the block boundary (we *could* check for this).
2374 // Regardless, the compare has been done in the predecessor block,
2375 // and it left a value for us in a virtual register. Ergo, we test
2376 // the one-bit value left in the virtual register.
2377 emitICmp_ri(MVT::i32, CondReg, CondRegIsKill, 0);
2379 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2380 std::swap(TBB, FBB);
2384 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2388 // Obtain the branch weight and add the TrueBB to the successor list.
2389 uint32_t BranchWeight = 0;
2391 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2392 TBB->getBasicBlock());
2393 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2395 fastEmitBranch(FBB, DbgLoc);
2399 bool AArch64FastISel::selectIndirectBr(const Instruction *I) {
2400 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
2401 unsigned AddrReg = getRegForValue(BI->getOperand(0));
2405 // Emit the indirect branch.
2406 const MCInstrDesc &II = TII.get(AArch64::BR);
2407 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
2408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
2410 // Make sure the CFG is up-to-date.
2411 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
2412 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
2417 bool AArch64FastISel::selectCmp(const Instruction *I) {
2418 const CmpInst *CI = cast<CmpInst>(I);
2420 // Try to optimize or fold the cmp.
2421 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2422 unsigned ResultReg = 0;
2423 switch (Predicate) {
2426 case CmpInst::FCMP_FALSE:
2427 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2429 TII.get(TargetOpcode::COPY), ResultReg)
2430 .addReg(AArch64::WZR, getKillRegState(true));
2432 case CmpInst::FCMP_TRUE:
2433 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2438 updateValueMap(I, ResultReg);
2443 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
2446 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2448 // FCMP_UEQ and FCMP_ONE cannot be checked with a single instruction. These
2449 // condition codes are inverted, because they are used by CSINC.
2450 static unsigned CondCodeTable[2][2] = {
2451 { AArch64CC::NE, AArch64CC::VC },
2452 { AArch64CC::PL, AArch64CC::LE }
2454 unsigned *CondCodes = nullptr;
2455 switch (Predicate) {
2458 case CmpInst::FCMP_UEQ:
2459 CondCodes = &CondCodeTable[0][0];
2461 case CmpInst::FCMP_ONE:
2462 CondCodes = &CondCodeTable[1][0];
2467 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass);
2468 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2470 .addReg(AArch64::WZR, getKillRegState(true))
2471 .addReg(AArch64::WZR, getKillRegState(true))
2472 .addImm(CondCodes[0]);
2473 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2475 .addReg(TmpReg1, getKillRegState(true))
2476 .addReg(AArch64::WZR, getKillRegState(true))
2477 .addImm(CondCodes[1]);
2479 updateValueMap(I, ResultReg);
2483 // Now set a register based on the comparison.
2484 AArch64CC::CondCode CC = getCompareCC(Predicate);
2485 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2486 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
2487 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2489 .addReg(AArch64::WZR, getKillRegState(true))
2490 .addReg(AArch64::WZR, getKillRegState(true))
2491 .addImm(invertedCC);
2493 updateValueMap(I, ResultReg);
2497 bool AArch64FastISel::selectSelect(const Instruction *I) {
2498 const SelectInst *SI = cast<SelectInst>(I);
2500 EVT DestEVT = TLI.getValueType(SI->getType(), true);
2501 if (!DestEVT.isSimple())
2504 MVT DestVT = DestEVT.getSimpleVT();
2505 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
2510 const TargetRegisterClass *RC = nullptr;
2511 switch (DestVT.SimpleTy) {
2512 default: return false;
2514 SelectOpc = AArch64::CSELWr; RC = &AArch64::GPR32RegClass; break;
2516 SelectOpc = AArch64::CSELXr; RC = &AArch64::GPR64RegClass; break;
2518 SelectOpc = AArch64::FCSELSrrr; RC = &AArch64::FPR32RegClass; break;
2520 SelectOpc = AArch64::FCSELDrrr; RC = &AArch64::FPR64RegClass; break;
2523 const Value *Cond = SI->getCondition();
2524 bool NeedTest = true;
2525 AArch64CC::CondCode CC = AArch64CC::NE;
2526 if (foldXALUIntrinsic(CC, I, Cond))
2529 unsigned CondReg = getRegForValue(Cond);
2532 bool CondIsKill = hasTrivialKill(Cond);
2535 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
2536 assert(ANDReg && "Unexpected AND instruction emission failure.");
2537 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
2540 unsigned TrueReg = getRegForValue(SI->getTrueValue());
2541 bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
2543 unsigned FalseReg = getRegForValue(SI->getFalseValue());
2544 bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
2546 if (!TrueReg || !FalseReg)
2549 unsigned ResultReg = fastEmitInst_rri(SelectOpc, RC, TrueReg, TrueIsKill,
2550 FalseReg, FalseIsKill, CC);
2551 updateValueMap(I, ResultReg);
2555 bool AArch64FastISel::selectFPExt(const Instruction *I) {
2556 Value *V = I->getOperand(0);
2557 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
2560 unsigned Op = getRegForValue(V);
2564 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
2565 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
2566 ResultReg).addReg(Op);
2567 updateValueMap(I, ResultReg);
2571 bool AArch64FastISel::selectFPTrunc(const Instruction *I) {
2572 Value *V = I->getOperand(0);
2573 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
2576 unsigned Op = getRegForValue(V);
2580 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
2581 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
2582 ResultReg).addReg(Op);
2583 updateValueMap(I, ResultReg);
2587 // FPToUI and FPToSI
2588 bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {
2590 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2593 unsigned SrcReg = getRegForValue(I->getOperand(0));
2597 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2598 if (SrcVT == MVT::f128)
2602 if (SrcVT == MVT::f64) {
2604 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2606 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2609 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2611 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2613 unsigned ResultReg = createResultReg(
2614 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2615 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2617 updateValueMap(I, ResultReg);
2621 bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) {
2623 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2625 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2626 "Unexpected value type.");
2628 unsigned SrcReg = getRegForValue(I->getOperand(0));
2631 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
2633 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2635 // Handle sign-extension.
2636 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
2638 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2645 if (SrcVT == MVT::i64) {
2647 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2649 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2652 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2654 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2657 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2659 updateValueMap(I, ResultReg);
2663 bool AArch64FastISel::fastLowerArguments() {
2664 if (!FuncInfo.CanLowerReturn)
2667 const Function *F = FuncInfo.Fn;
2671 CallingConv::ID CC = F->getCallingConv();
2672 if (CC != CallingConv::C)
2675 // Only handle simple cases of up to 8 GPR and FPR each.
2676 unsigned GPRCnt = 0;
2677 unsigned FPRCnt = 0;
2679 for (auto const &Arg : F->args()) {
2680 // The first argument is at index 1.
2682 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
2683 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
2684 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
2685 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
2688 Type *ArgTy = Arg.getType();
2689 if (ArgTy->isStructTy() || ArgTy->isArrayTy())
2692 EVT ArgVT = TLI.getValueType(ArgTy);
2693 if (!ArgVT.isSimple())
2696 MVT VT = ArgVT.getSimpleVT().SimpleTy;
2697 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8())
2700 if (VT.isVector() &&
2701 (!Subtarget->hasNEON() || !Subtarget->isLittleEndian()))
2704 if (VT >= MVT::i1 && VT <= MVT::i64)
2706 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() ||
2707 VT.is128BitVector())
2712 if (GPRCnt > 8 || FPRCnt > 8)
2716 static const MCPhysReg Registers[6][8] = {
2717 { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
2718 AArch64::W5, AArch64::W6, AArch64::W7 },
2719 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
2720 AArch64::X5, AArch64::X6, AArch64::X7 },
2721 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
2722 AArch64::H5, AArch64::H6, AArch64::H7 },
2723 { AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
2724 AArch64::S5, AArch64::S6, AArch64::S7 },
2725 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
2726 AArch64::D5, AArch64::D6, AArch64::D7 },
2727 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
2728 AArch64::Q5, AArch64::Q6, AArch64::Q7 }
2731 unsigned GPRIdx = 0;
2732 unsigned FPRIdx = 0;
2733 for (auto const &Arg : F->args()) {
2734 MVT VT = TLI.getSimpleValueType(Arg.getType());
2736 const TargetRegisterClass *RC;
2737 if (VT >= MVT::i1 && VT <= MVT::i32) {
2738 SrcReg = Registers[0][GPRIdx++];
2739 RC = &AArch64::GPR32RegClass;
2741 } else if (VT == MVT::i64) {
2742 SrcReg = Registers[1][GPRIdx++];
2743 RC = &AArch64::GPR64RegClass;
2744 } else if (VT == MVT::f16) {
2745 SrcReg = Registers[2][FPRIdx++];
2746 RC = &AArch64::FPR16RegClass;
2747 } else if (VT == MVT::f32) {
2748 SrcReg = Registers[3][FPRIdx++];
2749 RC = &AArch64::FPR32RegClass;
2750 } else if ((VT == MVT::f64) || VT.is64BitVector()) {
2751 SrcReg = Registers[4][FPRIdx++];
2752 RC = &AArch64::FPR64RegClass;
2753 } else if (VT.is128BitVector()) {
2754 SrcReg = Registers[5][FPRIdx++];
2755 RC = &AArch64::FPR128RegClass;
2757 llvm_unreachable("Unexpected value type.");
2759 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
2760 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
2761 // Without this, EmitLiveInCopies may eliminate the livein if its only
2762 // use is a bitcast (which isn't turned into an instruction).
2763 unsigned ResultReg = createResultReg(RC);
2764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2765 TII.get(TargetOpcode::COPY), ResultReg)
2766 .addReg(DstReg, getKillRegState(true));
2767 updateValueMap(&Arg, ResultReg);
2772 bool AArch64FastISel::processCallArgs(CallLoweringInfo &CLI,
2773 SmallVectorImpl<MVT> &OutVTs,
2774 unsigned &NumBytes) {
2775 CallingConv::ID CC = CLI.CallConv;
2776 SmallVector<CCValAssign, 16> ArgLocs;
2777 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
2778 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
2780 // Get a count of how many bytes are to be pushed on the stack.
2781 NumBytes = CCInfo.getNextStackOffset();
2783 // Issue CALLSEQ_START
2784 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2785 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
2788 // Process the args.
2789 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2790 CCValAssign &VA = ArgLocs[i];
2791 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
2792 MVT ArgVT = OutVTs[VA.getValNo()];
2794 unsigned ArgReg = getRegForValue(ArgVal);
2798 // Handle arg promotion: SExt, ZExt, AExt.
2799 switch (VA.getLocInfo()) {
2800 case CCValAssign::Full:
2802 case CCValAssign::SExt: {
2803 MVT DestVT = VA.getLocVT();
2805 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2810 case CCValAssign::AExt:
2811 // Intentional fall-through.
2812 case CCValAssign::ZExt: {
2813 MVT DestVT = VA.getLocVT();
2815 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
2821 llvm_unreachable("Unknown arg promotion!");
2824 // Now copy/store arg to correct locations.
2825 if (VA.isRegLoc() && !VA.needsCustom()) {
2826 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2827 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
2828 CLI.OutRegs.push_back(VA.getLocReg());
2829 } else if (VA.needsCustom()) {
2830 // FIXME: Handle custom args.
2833 assert(VA.isMemLoc() && "Assuming store on stack.");
2835 // Don't emit stores for undef values.
2836 if (isa<UndefValue>(ArgVal))
2839 // Need to store on the stack.
2840 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
2842 unsigned BEAlign = 0;
2843 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2844 BEAlign = 8 - ArgSize;
2847 Addr.setKind(Address::RegBase);
2848 Addr.setReg(AArch64::SP);
2849 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
2851 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
2852 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2853 MachinePointerInfo::getStack(Addr.getOffset()),
2854 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
2856 if (!emitStore(ArgVT, ArgReg, Addr, MMO))
2863 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
2864 unsigned NumBytes) {
2865 CallingConv::ID CC = CLI.CallConv;
2867 // Issue CALLSEQ_END
2868 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2869 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
2870 .addImm(NumBytes).addImm(0);
2872 // Now the return value.
2873 if (RetVT != MVT::isVoid) {
2874 SmallVector<CCValAssign, 16> RVLocs;
2875 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2876 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
2878 // Only handle a single return value.
2879 if (RVLocs.size() != 1)
2882 // Copy all of the result registers out of their specified physreg.
2883 MVT CopyVT = RVLocs[0].getValVT();
2884 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
2885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2886 TII.get(TargetOpcode::COPY), ResultReg)
2887 .addReg(RVLocs[0].getLocReg());
2888 CLI.InRegs.push_back(RVLocs[0].getLocReg());
2890 CLI.ResultReg = ResultReg;
2891 CLI.NumResultRegs = 1;
2897 bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
2898 CallingConv::ID CC = CLI.CallConv;
2899 bool IsTailCall = CLI.IsTailCall;
2900 bool IsVarArg = CLI.IsVarArg;
2901 const Value *Callee = CLI.Callee;
2902 const char *SymName = CLI.SymName;
2904 if (!Callee && !SymName)
2907 // Allow SelectionDAG isel to handle tail calls.
2911 CodeModel::Model CM = TM.getCodeModel();
2912 // Only support the small and large code model.
2913 if (CM != CodeModel::Small && CM != CodeModel::Large)
2916 // FIXME: Add large code model support for ELF.
2917 if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
2920 // Let SDISel handle vararg functions.
2924 // FIXME: Only handle *simple* calls for now.
2926 if (CLI.RetTy->isVoidTy())
2927 RetVT = MVT::isVoid;
2928 else if (!isTypeLegal(CLI.RetTy, RetVT))
2931 for (auto Flag : CLI.OutFlags)
2932 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
2935 // Set up the argument vectors.
2936 SmallVector<MVT, 16> OutVTs;
2937 OutVTs.reserve(CLI.OutVals.size());
2939 for (auto *Val : CLI.OutVals) {
2941 if (!isTypeLegal(Val->getType(), VT) &&
2942 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
2945 // We don't handle vector parameters yet.
2946 if (VT.isVector() || VT.getSizeInBits() > 64)
2949 OutVTs.push_back(VT);
2953 if (Callee && !computeCallAddress(Callee, Addr))
2956 // Handle the arguments now that we've gotten them.
2958 if (!processCallArgs(CLI, OutVTs, NumBytes))
2962 MachineInstrBuilder MIB;
2963 if (CM == CodeModel::Small) {
2964 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
2965 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
2967 MIB.addExternalSymbol(SymName, 0);
2968 else if (Addr.getGlobalValue())
2969 MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
2970 else if (Addr.getReg()) {
2971 unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
2976 unsigned CallReg = 0;
2978 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
2979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
2981 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGE);
2983 CallReg = createResultReg(&AArch64::GPR64RegClass);
2984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
2987 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
2989 } else if (Addr.getGlobalValue())
2990 CallReg = materializeGV(Addr.getGlobalValue());
2991 else if (Addr.getReg())
2992 CallReg = Addr.getReg();
2997 const MCInstrDesc &II = TII.get(AArch64::BLR);
2998 CallReg = constrainOperandRegClass(II, CallReg, 0);
2999 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
3002 // Add implicit physical register uses to the call.
3003 for (auto Reg : CLI.OutRegs)
3004 MIB.addReg(Reg, RegState::Implicit);
3006 // Add a register mask with the call-preserved registers.
3007 // Proper defs for return values will be added by setPhysRegsDeadExcept().
3008 MIB.addRegMask(TRI.getCallPreservedMask(CC));
3012 // Finish off the call including any return values.
3013 return finishCall(CLI, RetVT, NumBytes);
3016 bool AArch64FastISel::isMemCpySmall(uint64_t Len, unsigned Alignment) {
3018 return Len / Alignment <= 4;
3023 bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
3024 uint64_t Len, unsigned Alignment) {
3025 // Make sure we don't bloat code by inlining very large memcpy's.
3026 if (!isMemCpySmall(Len, Alignment))
3029 int64_t UnscaledOffset = 0;
3030 Address OrigDest = Dest;
3031 Address OrigSrc = Src;
3035 if (!Alignment || Alignment >= 8) {
3046 // Bound based on alignment.
3047 if (Len >= 4 && Alignment == 4)
3049 else if (Len >= 2 && Alignment == 2)
3056 unsigned ResultReg = emitLoad(VT, VT, Src);
3060 if (!emitStore(VT, ResultReg, Dest))
3063 int64_t Size = VT.getSizeInBits() / 8;
3065 UnscaledOffset += Size;
3067 // We need to recompute the unscaled offset for each iteration.
3068 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
3069 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
3075 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
3076 /// into the user. The condition code will only be updated on success.
3077 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
3078 const Instruction *I,
3079 const Value *Cond) {
3080 if (!isa<ExtractValueInst>(Cond))
3083 const auto *EV = cast<ExtractValueInst>(Cond);
3084 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
3087 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
3089 const Function *Callee = II->getCalledFunction();
3091 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
3092 if (!isTypeLegal(RetTy, RetVT))
3095 if (RetVT != MVT::i32 && RetVT != MVT::i64)
3098 const Value *LHS = II->getArgOperand(0);
3099 const Value *RHS = II->getArgOperand(1);
3101 // Canonicalize immediate to the RHS.
3102 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
3103 isCommutativeIntrinsic(II))
3104 std::swap(LHS, RHS);
3106 // Simplify multiplies.
3107 unsigned IID = II->getIntrinsicID();
3111 case Intrinsic::smul_with_overflow:
3112 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3113 if (C->getValue() == 2)
3114 IID = Intrinsic::sadd_with_overflow;
3116 case Intrinsic::umul_with_overflow:
3117 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3118 if (C->getValue() == 2)
3119 IID = Intrinsic::uadd_with_overflow;
3123 AArch64CC::CondCode TmpCC;
3127 case Intrinsic::sadd_with_overflow:
3128 case Intrinsic::ssub_with_overflow:
3129 TmpCC = AArch64CC::VS;
3131 case Intrinsic::uadd_with_overflow:
3132 TmpCC = AArch64CC::HS;
3134 case Intrinsic::usub_with_overflow:
3135 TmpCC = AArch64CC::LO;
3137 case Intrinsic::smul_with_overflow:
3138 case Intrinsic::umul_with_overflow:
3139 TmpCC = AArch64CC::NE;
3143 // Check if both instructions are in the same basic block.
3144 if (!isValueAvailable(II))
3147 // Make sure nothing is in the way
3148 BasicBlock::const_iterator Start = I;
3149 BasicBlock::const_iterator End = II;
3150 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
3151 // We only expect extractvalue instructions between the intrinsic and the
3152 // instruction to be selected.
3153 if (!isa<ExtractValueInst>(Itr))
3156 // Check that the extractvalue operand comes from the intrinsic.
3157 const auto *EVI = cast<ExtractValueInst>(Itr);
3158 if (EVI->getAggregateOperand() != II)
3166 bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
3167 // FIXME: Handle more intrinsics.
3168 switch (II->getIntrinsicID()) {
3169 default: return false;
3170 case Intrinsic::frameaddress: {
3171 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
3172 MFI->setFrameAddressIsTaken(true);
3174 const AArch64RegisterInfo *RegInfo =
3175 static_cast<const AArch64RegisterInfo *>(
3176 TM.getSubtargetImpl()->getRegisterInfo());
3177 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
3178 unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3180 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
3181 // Recursively load frame address
3187 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
3189 DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
3190 SrcReg, /*IsKill=*/true, 0);
3191 assert(DestReg && "Unexpected LDR instruction emission failure.");
3195 updateValueMap(II, SrcReg);
3198 case Intrinsic::memcpy:
3199 case Intrinsic::memmove: {
3200 const auto *MTI = cast<MemTransferInst>(II);
3201 // Don't handle volatile.
3202 if (MTI->isVolatile())
3205 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
3206 // we would emit dead code because we don't currently handle memmoves.
3207 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
3208 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
3209 // Small memcpy's are common enough that we want to do them without a call
3211 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
3212 unsigned Alignment = MTI->getAlignment();
3213 if (isMemCpySmall(Len, Alignment)) {
3215 if (!computeAddress(MTI->getRawDest(), Dest) ||
3216 !computeAddress(MTI->getRawSource(), Src))
3218 if (tryEmitSmallMemCpy(Dest, Src, Len, Alignment))
3223 if (!MTI->getLength()->getType()->isIntegerTy(64))
3226 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
3227 // Fast instruction selection doesn't support the special
3231 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
3232 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
3234 case Intrinsic::memset: {
3235 const MemSetInst *MSI = cast<MemSetInst>(II);
3236 // Don't handle volatile.
3237 if (MSI->isVolatile())
3240 if (!MSI->getLength()->getType()->isIntegerTy(64))
3243 if (MSI->getDestAddressSpace() > 255)
3244 // Fast instruction selection doesn't support the special
3248 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
3250 case Intrinsic::sin:
3251 case Intrinsic::cos:
3252 case Intrinsic::pow: {
3254 if (!isTypeLegal(II->getType(), RetVT))
3257 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3260 static const RTLIB::Libcall LibCallTable[3][2] = {
3261 { RTLIB::SIN_F32, RTLIB::SIN_F64 },
3262 { RTLIB::COS_F32, RTLIB::COS_F64 },
3263 { RTLIB::POW_F32, RTLIB::POW_F64 }
3266 bool Is64Bit = RetVT == MVT::f64;
3267 switch (II->getIntrinsicID()) {
3269 llvm_unreachable("Unexpected intrinsic.");
3270 case Intrinsic::sin:
3271 LC = LibCallTable[0][Is64Bit];
3273 case Intrinsic::cos:
3274 LC = LibCallTable[1][Is64Bit];
3276 case Intrinsic::pow:
3277 LC = LibCallTable[2][Is64Bit];
3282 Args.reserve(II->getNumArgOperands());
3284 // Populate the argument list.
3285 for (auto &Arg : II->arg_operands()) {
3288 Entry.Ty = Arg->getType();
3289 Args.push_back(Entry);
3292 CallLoweringInfo CLI;
3293 CLI.setCallee(TLI.getLibcallCallingConv(LC), II->getType(),
3294 TLI.getLibcallName(LC), std::move(Args));
3295 if (!lowerCallTo(CLI))
3297 updateValueMap(II, CLI.ResultReg);
3300 case Intrinsic::trap: {
3301 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3305 case Intrinsic::sqrt: {
3306 Type *RetTy = II->getCalledFunction()->getReturnType();
3309 if (!isTypeLegal(RetTy, VT))
3312 unsigned Op0Reg = getRegForValue(II->getOperand(0));
3315 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
3317 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
3321 updateValueMap(II, ResultReg);
3324 case Intrinsic::sadd_with_overflow:
3325 case Intrinsic::uadd_with_overflow:
3326 case Intrinsic::ssub_with_overflow:
3327 case Intrinsic::usub_with_overflow:
3328 case Intrinsic::smul_with_overflow:
3329 case Intrinsic::umul_with_overflow: {
3330 // This implements the basic lowering of the xalu with overflow intrinsics.
3331 const Function *Callee = II->getCalledFunction();
3332 auto *Ty = cast<StructType>(Callee->getReturnType());
3333 Type *RetTy = Ty->getTypeAtIndex(0U);
3336 if (!isTypeLegal(RetTy, VT))
3339 if (VT != MVT::i32 && VT != MVT::i64)
3342 const Value *LHS = II->getArgOperand(0);
3343 const Value *RHS = II->getArgOperand(1);
3344 // Canonicalize immediate to the RHS.
3345 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
3346 isCommutativeIntrinsic(II))
3347 std::swap(LHS, RHS);
3349 // Simplify multiplies.
3350 unsigned IID = II->getIntrinsicID();
3354 case Intrinsic::smul_with_overflow:
3355 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3356 if (C->getValue() == 2) {
3357 IID = Intrinsic::sadd_with_overflow;
3361 case Intrinsic::umul_with_overflow:
3362 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3363 if (C->getValue() == 2) {
3364 IID = Intrinsic::uadd_with_overflow;
3370 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
3371 AArch64CC::CondCode CC = AArch64CC::Invalid;
3373 default: llvm_unreachable("Unexpected intrinsic!");
3374 case Intrinsic::sadd_with_overflow:
3375 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3378 case Intrinsic::uadd_with_overflow:
3379 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3382 case Intrinsic::ssub_with_overflow:
3383 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3386 case Intrinsic::usub_with_overflow:
3387 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3390 case Intrinsic::smul_with_overflow: {
3392 unsigned LHSReg = getRegForValue(LHS);
3395 bool LHSIsKill = hasTrivialKill(LHS);
3397 unsigned RHSReg = getRegForValue(RHS);
3400 bool RHSIsKill = hasTrivialKill(RHS);
3402 if (VT == MVT::i32) {
3403 MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3404 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
3405 /*IsKill=*/false, 32);
3406 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
3408 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
3410 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
3411 AArch64_AM::ASR, 31, /*WantResult=*/false);
3413 assert(VT == MVT::i64 && "Unexpected value type.");
3414 MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3415 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
3417 emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
3418 AArch64_AM::ASR, 63, /*WantResult=*/false);
3422 case Intrinsic::umul_with_overflow: {
3424 unsigned LHSReg = getRegForValue(LHS);
3427 bool LHSIsKill = hasTrivialKill(LHS);
3429 unsigned RHSReg = getRegForValue(RHS);
3432 bool RHSIsKill = hasTrivialKill(RHS);
3434 if (VT == MVT::i32) {
3435 MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3436 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
3437 /*IsKill=*/false, AArch64_AM::LSR, 32,
3438 /*WantResult=*/false);
3439 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
3442 assert(VT == MVT::i64 && "Unexpected value type.");
3443 MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3444 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
3446 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
3447 /*IsKill=*/false, /*WantResult=*/false);
3454 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
3455 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3456 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3459 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
3460 AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
3461 /*IsKill=*/true, getInvertedCondCode(CC));
3463 assert((ResultReg1 + 1) == ResultReg2 &&
3464 "Nonconsecutive result registers.");
3465 updateValueMap(II, ResultReg1, 2);
3472 bool AArch64FastISel::selectRet(const Instruction *I) {
3473 const ReturnInst *Ret = cast<ReturnInst>(I);
3474 const Function &F = *I->getParent()->getParent();
3476 if (!FuncInfo.CanLowerReturn)
3482 // Build a list of return value registers.
3483 SmallVector<unsigned, 4> RetRegs;
3485 if (Ret->getNumOperands() > 0) {
3486 CallingConv::ID CC = F.getCallingConv();
3487 SmallVector<ISD::OutputArg, 4> Outs;
3488 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
3490 // Analyze operands of the call, assigning locations to each operand.
3491 SmallVector<CCValAssign, 16> ValLocs;
3492 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
3493 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
3494 : RetCC_AArch64_AAPCS;
3495 CCInfo.AnalyzeReturn(Outs, RetCC);
3497 // Only handle a single return value for now.
3498 if (ValLocs.size() != 1)
3501 CCValAssign &VA = ValLocs[0];
3502 const Value *RV = Ret->getOperand(0);
3504 // Don't bother handling odd stuff for now.
3505 if ((VA.getLocInfo() != CCValAssign::Full) &&
3506 (VA.getLocInfo() != CCValAssign::BCvt))
3509 // Only handle register returns for now.
3513 unsigned Reg = getRegForValue(RV);
3517 unsigned SrcReg = Reg + VA.getValNo();
3518 unsigned DestReg = VA.getLocReg();
3519 // Avoid a cross-class copy. This is very unlikely.
3520 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
3523 EVT RVEVT = TLI.getValueType(RV->getType());
3524 if (!RVEVT.isSimple())
3527 // Vectors (of > 1 lane) in big endian need tricky handling.
3528 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
3529 !Subtarget->isLittleEndian())
3532 MVT RVVT = RVEVT.getSimpleVT();
3533 if (RVVT == MVT::f128)
3536 MVT DestVT = VA.getValVT();
3537 // Special handling for extended integers.
3538 if (RVVT != DestVT) {
3539 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
3542 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3545 bool IsZExt = Outs[0].Flags.isZExt();
3546 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3552 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3553 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3555 // Add register to return instruction.
3556 RetRegs.push_back(VA.getLocReg());
3559 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3560 TII.get(AArch64::RET_ReallyLR));
3561 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
3562 MIB.addReg(RetRegs[i], RegState::Implicit);
3566 bool AArch64FastISel::selectTrunc(const Instruction *I) {
3567 Type *DestTy = I->getType();
3568 Value *Op = I->getOperand(0);
3569 Type *SrcTy = Op->getType();
3571 EVT SrcEVT = TLI.getValueType(SrcTy, true);
3572 EVT DestEVT = TLI.getValueType(DestTy, true);
3573 if (!SrcEVT.isSimple())
3575 if (!DestEVT.isSimple())
3578 MVT SrcVT = SrcEVT.getSimpleVT();
3579 MVT DestVT = DestEVT.getSimpleVT();
3581 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3584 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3588 unsigned SrcReg = getRegForValue(Op);
3591 bool SrcIsKill = hasTrivialKill(Op);
3593 // If we're truncating from i64 to a smaller non-legal type then generate an
3594 // AND. Otherwise, we know the high bits are undefined and a truncate only
3595 // generate a COPY. We cannot mark the source register also as result
3596 // register, because this can incorrectly transfer the kill flag onto the
3599 if (SrcVT == MVT::i64) {
3601 switch (DestVT.SimpleTy) {
3603 // Trunc i64 to i32 is handled by the target-independent fast-isel.
3615 // Issue an extract_subreg to get the lower 32-bits.
3616 unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
3618 // Create the AND instruction which performs the actual truncation.
3619 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
3620 assert(ResultReg && "Unexpected AND instruction emission failure.");
3622 ResultReg = createResultReg(&AArch64::GPR32RegClass);
3623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3624 TII.get(TargetOpcode::COPY), ResultReg)
3625 .addReg(SrcReg, getKillRegState(SrcIsKill));
3628 updateValueMap(I, ResultReg);
3632 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
3633 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
3634 DestVT == MVT::i64) &&
3635 "Unexpected value type.");
3636 // Handle i8 and i16 as i32.
3637 if (DestVT == MVT::i8 || DestVT == MVT::i16)
3641 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
3642 assert(ResultReg && "Unexpected AND instruction emission failure.");
3643 if (DestVT == MVT::i64) {
3644 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
3645 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
3646 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3647 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3648 TII.get(AArch64::SUBREG_TO_REG), Reg64)
3651 .addImm(AArch64::sub_32);
3656 if (DestVT == MVT::i64) {
3657 // FIXME: We're SExt i1 to i64.
3660 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
3661 /*TODO:IsKill=*/false, 0, 0);
3665 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3666 unsigned Op1, bool Op1IsKill) {
3668 switch (RetVT.SimpleTy) {
3674 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
3676 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
3679 const TargetRegisterClass *RC =
3680 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3681 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
3682 /*IsKill=*/ZReg, true);
3685 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3686 unsigned Op1, bool Op1IsKill) {
3687 if (RetVT != MVT::i64)
3690 return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
3691 Op0, Op0IsKill, Op1, Op1IsKill,
3692 AArch64::XZR, /*IsKill=*/true);
3695 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3696 unsigned Op1, bool Op1IsKill) {
3697 if (RetVT != MVT::i64)
3700 return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
3701 Op0, Op0IsKill, Op1, Op1IsKill,
3702 AArch64::XZR, /*IsKill=*/true);
3705 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3706 unsigned Op1Reg, bool Op1IsKill) {
3708 bool NeedTrunc = false;
3710 switch (RetVT.SimpleTy) {
3712 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
3713 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
3714 case MVT::i32: Opc = AArch64::LSLVWr; break;
3715 case MVT::i64: Opc = AArch64::LSLVXr; break;
3718 const TargetRegisterClass *RC =
3719 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3721 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3724 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3727 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3731 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3732 bool Op0IsKill, uint64_t Shift,
3734 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3735 "Unexpected source/return type pair.");
3736 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
3737 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
3738 "Unexpected source value type.");
3739 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3740 RetVT == MVT::i64) && "Unexpected return value type.");
3742 bool Is64Bit = (RetVT == MVT::i64);
3743 unsigned RegSize = Is64Bit ? 64 : 32;
3744 unsigned DstBits = RetVT.getSizeInBits();
3745 unsigned SrcBits = SrcVT.getSizeInBits();
3747 // Don't deal with undefined shifts.
3748 if (Shift >= DstBits)
3751 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3752 // {S|U}BFM Wd, Wn, #r, #s
3753 // Wd<32+s-r,32-r> = Wn<s:0> when r > s
3755 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3756 // %2 = shl i16 %1, 4
3757 // Wd<32+7-28,32-28> = Wn<7:0> <- clamp s to 7
3758 // 0b1111_1111_1111_1111__1111_1010_1010_0000 sext
3759 // 0b0000_0000_0000_0000__0000_0101_0101_0000 sext | zext
3760 // 0b0000_0000_0000_0000__0000_1010_1010_0000 zext
3762 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3763 // %2 = shl i16 %1, 8
3764 // Wd<32+7-24,32-24> = Wn<7:0>
3765 // 0b1111_1111_1111_1111__1010_1010_0000_0000 sext
3766 // 0b0000_0000_0000_0000__0101_0101_0000_0000 sext | zext
3767 // 0b0000_0000_0000_0000__1010_1010_0000_0000 zext
3769 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3770 // %2 = shl i16 %1, 12
3771 // Wd<32+3-20,32-20> = Wn<3:0>
3772 // 0b1111_1111_1111_1111__1010_0000_0000_0000 sext
3773 // 0b0000_0000_0000_0000__0101_0000_0000_0000 sext | zext
3774 // 0b0000_0000_0000_0000__1010_0000_0000_0000 zext
3776 unsigned ImmR = RegSize - Shift;
3777 // Limit the width to the length of the source type.
3778 unsigned ImmS = std::min<unsigned>(SrcBits - 1, DstBits - 1 - Shift);
3779 static const unsigned OpcTable[2][2] = {
3780 {AArch64::SBFMWri, AArch64::SBFMXri},
3781 {AArch64::UBFMWri, AArch64::UBFMXri}
3783 unsigned Opc = OpcTable[IsZext][Is64Bit];
3784 const TargetRegisterClass *RC =
3785 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3786 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3787 unsigned TmpReg = MRI.createVirtualRegister(RC);
3788 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3789 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3791 .addReg(Op0, getKillRegState(Op0IsKill))
3792 .addImm(AArch64::sub_32);
3796 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3799 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3800 unsigned Op1Reg, bool Op1IsKill) {
3802 bool NeedTrunc = false;
3804 switch (RetVT.SimpleTy) {
3806 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
3807 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
3808 case MVT::i32: Opc = AArch64::LSRVWr; break;
3809 case MVT::i64: Opc = AArch64::LSRVXr; break;
3812 const TargetRegisterClass *RC =
3813 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3815 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
3816 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3817 Op0IsKill = Op1IsKill = true;
3819 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3822 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3826 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3827 bool Op0IsKill, uint64_t Shift,
3829 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3830 "Unexpected source/return type pair.");
3831 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3832 SrcVT == MVT::i64) && "Unexpected source value type.");
3833 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3834 RetVT == MVT::i64) && "Unexpected return value type.");
3836 bool Is64Bit = (RetVT == MVT::i64);
3837 unsigned RegSize = Is64Bit ? 64 : 32;
3838 unsigned DstBits = RetVT.getSizeInBits();
3839 unsigned SrcBits = SrcVT.getSizeInBits();
3841 // Don't deal with undefined shifts.
3842 if (Shift >= DstBits)
3845 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3846 // {S|U}BFM Wd, Wn, #r, #s
3847 // Wd<s-r:0> = Wn<s:r> when r <= s
3849 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3850 // %2 = lshr i16 %1, 4
3851 // Wd<7-4:0> = Wn<7:4>
3852 // 0b0000_0000_0000_0000__0000_1111_1111_1010 sext
3853 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3854 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3856 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3857 // %2 = lshr i16 %1, 8
3858 // Wd<7-7,0> = Wn<7:7>
3859 // 0b0000_0000_0000_0000__0000_0000_1111_1111 sext
3860 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3861 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3863 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3864 // %2 = lshr i16 %1, 12
3865 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3866 // 0b0000_0000_0000_0000__0000_0000_0000_1111 sext
3867 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3868 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3870 if (Shift >= SrcBits && IsZExt)
3871 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
3873 // It is not possible to fold a sign-extend into the LShr instruction. In this
3874 // case emit a sign-extend.
3876 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
3881 SrcBits = SrcVT.getSizeInBits();
3885 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3886 unsigned ImmS = SrcBits - 1;
3887 static const unsigned OpcTable[2][2] = {
3888 {AArch64::SBFMWri, AArch64::SBFMXri},
3889 {AArch64::UBFMWri, AArch64::UBFMXri}
3891 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3892 const TargetRegisterClass *RC =
3893 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3894 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3895 unsigned TmpReg = MRI.createVirtualRegister(RC);
3896 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3897 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3899 .addReg(Op0, getKillRegState(Op0IsKill))
3900 .addImm(AArch64::sub_32);
3904 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3907 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3908 unsigned Op1Reg, bool Op1IsKill) {
3910 bool NeedTrunc = false;
3912 switch (RetVT.SimpleTy) {
3914 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
3915 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
3916 case MVT::i32: Opc = AArch64::ASRVWr; break;
3917 case MVT::i64: Opc = AArch64::ASRVXr; break;
3920 const TargetRegisterClass *RC =
3921 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3923 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
3924 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3925 Op0IsKill = Op1IsKill = true;
3927 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3930 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3934 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3935 bool Op0IsKill, uint64_t Shift,
3937 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3938 "Unexpected source/return type pair.");
3939 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3940 SrcVT == MVT::i64) && "Unexpected source value type.");
3941 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3942 RetVT == MVT::i64) && "Unexpected return value type.");
3944 bool Is64Bit = (RetVT == MVT::i64);
3945 unsigned RegSize = Is64Bit ? 64 : 32;
3946 unsigned DstBits = RetVT.getSizeInBits();
3947 unsigned SrcBits = SrcVT.getSizeInBits();
3949 // Don't deal with undefined shifts.
3950 if (Shift >= DstBits)
3953 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3954 // {S|U}BFM Wd, Wn, #r, #s
3955 // Wd<s-r:0> = Wn<s:r> when r <= s
3957 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3958 // %2 = ashr i16 %1, 4
3959 // Wd<7-4:0> = Wn<7:4>
3960 // 0b1111_1111_1111_1111__1111_1111_1111_1010 sext
3961 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3962 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3964 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3965 // %2 = ashr i16 %1, 8
3966 // Wd<7-7,0> = Wn<7:7>
3967 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3968 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3969 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3971 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3972 // %2 = ashr i16 %1, 12
3973 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3974 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3975 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3976 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3978 if (Shift >= SrcBits && IsZExt)
3979 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
3981 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3982 unsigned ImmS = SrcBits - 1;
3983 static const unsigned OpcTable[2][2] = {
3984 {AArch64::SBFMWri, AArch64::SBFMXri},
3985 {AArch64::UBFMWri, AArch64::UBFMXri}
3987 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3988 const TargetRegisterClass *RC =
3989 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3990 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3991 unsigned TmpReg = MRI.createVirtualRegister(RC);
3992 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3993 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3995 .addReg(Op0, getKillRegState(Op0IsKill))
3996 .addImm(AArch64::sub_32);
4000 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4003 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4005 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
4007 // FastISel does not have plumbing to deal with extensions where the SrcVT or
4008 // DestVT are odd things, so test to make sure that they are both types we can
4009 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4010 // bail out to SelectionDAG.
4011 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
4012 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
4013 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
4014 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
4020 switch (SrcVT.SimpleTy) {
4024 return emiti1Ext(SrcReg, DestVT, IsZExt);
4026 if (DestVT == MVT::i64)
4027 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4029 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4033 if (DestVT == MVT::i64)
4034 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4036 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4040 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4041 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4046 // Handle i8 and i16 as i32.
4047 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4049 else if (DestVT == MVT::i64) {
4050 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
4051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4052 TII.get(AArch64::SUBREG_TO_REG), Src64)
4055 .addImm(AArch64::sub_32);
4059 const TargetRegisterClass *RC =
4060 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4061 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
4064 static bool isZExtLoad(const MachineInstr *LI) {
4065 switch (LI->getOpcode()) {
4068 case AArch64::LDURBBi:
4069 case AArch64::LDURHHi:
4070 case AArch64::LDURWi:
4071 case AArch64::LDRBBui:
4072 case AArch64::LDRHHui:
4073 case AArch64::LDRWui:
4074 case AArch64::LDRBBroX:
4075 case AArch64::LDRHHroX:
4076 case AArch64::LDRWroX:
4077 case AArch64::LDRBBroW:
4078 case AArch64::LDRHHroW:
4079 case AArch64::LDRWroW:
4084 static bool isSExtLoad(const MachineInstr *LI) {
4085 switch (LI->getOpcode()) {
4088 case AArch64::LDURSBWi:
4089 case AArch64::LDURSHWi:
4090 case AArch64::LDURSBXi:
4091 case AArch64::LDURSHXi:
4092 case AArch64::LDURSWi:
4093 case AArch64::LDRSBWui:
4094 case AArch64::LDRSHWui:
4095 case AArch64::LDRSBXui:
4096 case AArch64::LDRSHXui:
4097 case AArch64::LDRSWui:
4098 case AArch64::LDRSBWroX:
4099 case AArch64::LDRSHWroX:
4100 case AArch64::LDRSBXroX:
4101 case AArch64::LDRSHXroX:
4102 case AArch64::LDRSWroX:
4103 case AArch64::LDRSBWroW:
4104 case AArch64::LDRSHWroW:
4105 case AArch64::LDRSBXroW:
4106 case AArch64::LDRSHXroW:
4107 case AArch64::LDRSWroW:
4112 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
4114 const auto *LI = dyn_cast<LoadInst>(I->getOperand(0));
4115 if (!LI || !LI->hasOneUse())
4118 // Check if the load instruction has already been selected.
4119 unsigned Reg = lookUpRegForValue(LI);
4123 MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
4127 // Check if the correct load instruction has been emitted - SelectionDAG might
4128 // have emitted a zero-extending load, but we need a sign-extending load.
4129 bool IsZExt = isa<ZExtInst>(I);
4130 const auto *LoadMI = MI;
4131 if (LoadMI->getOpcode() == TargetOpcode::COPY &&
4132 LoadMI->getOperand(1).getSubReg() == AArch64::sub_32) {
4133 unsigned LoadReg = MI->getOperand(1).getReg();
4134 LoadMI = MRI.getUniqueVRegDef(LoadReg);
4135 assert(LoadMI && "Expected valid instruction");
4137 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
4140 // Nothing to be done.
4141 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4142 updateValueMap(I, Reg);
4147 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
4148 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4149 TII.get(AArch64::SUBREG_TO_REG), Reg64)
4151 .addReg(Reg, getKillRegState(true))
4152 .addImm(AArch64::sub_32);
4155 assert((MI->getOpcode() == TargetOpcode::COPY &&
4156 MI->getOperand(1).getSubReg() == AArch64::sub_32) &&
4157 "Expected copy instruction");
4158 Reg = MI->getOperand(1).getReg();
4159 MI->eraseFromParent();
4161 updateValueMap(I, Reg);
4165 bool AArch64FastISel::selectIntExt(const Instruction *I) {
4166 assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
4167 "Unexpected integer extend instruction.");
4170 if (!isTypeSupported(I->getType(), RetVT))
4173 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
4176 // Try to optimize already sign-/zero-extended values from load instructions.
4177 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4180 unsigned SrcReg = getRegForValue(I->getOperand(0));
4183 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
4185 // Try to optimize already sign-/zero-extended values from function arguments.
4186 bool IsZExt = isa<ZExtInst>(I);
4187 if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0))) {
4188 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
4189 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4190 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
4191 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4192 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
4194 .addReg(SrcReg, getKillRegState(SrcIsKill))
4195 .addImm(AArch64::sub_32);
4198 updateValueMap(I, SrcReg);
4203 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4207 updateValueMap(I, ResultReg);
4211 bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {
4212 EVT DestEVT = TLI.getValueType(I->getType(), true);
4213 if (!DestEVT.isSimple())
4216 MVT DestVT = DestEVT.getSimpleVT();
4217 if (DestVT != MVT::i64 && DestVT != MVT::i32)
4221 bool Is64bit = (DestVT == MVT::i64);
4222 switch (ISDOpcode) {
4226 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
4229 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
4232 unsigned MSubOpc = Is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
4233 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4236 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4238 unsigned Src1Reg = getRegForValue(I->getOperand(1));
4241 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
4243 const TargetRegisterClass *RC =
4244 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4245 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
4246 Src1Reg, /*IsKill=*/false);
4247 assert(QuotReg && "Unexpected DIV instruction emission failure.");
4248 // The remainder is computed as numerator - (quotient * denominator) using the
4249 // MSUB instruction.
4250 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
4251 Src1Reg, Src1IsKill, Src0Reg,
4253 updateValueMap(I, ResultReg);
4257 bool AArch64FastISel::selectMul(const Instruction *I) {
4259 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
4263 return selectBinaryOp(I, ISD::MUL);
4265 const Value *Src0 = I->getOperand(0);
4266 const Value *Src1 = I->getOperand(1);
4267 if (const auto *C = dyn_cast<ConstantInt>(Src0))
4268 if (C->getValue().isPowerOf2())
4269 std::swap(Src0, Src1);
4271 // Try to simplify to a shift instruction.
4272 if (const auto *C = dyn_cast<ConstantInt>(Src1))
4273 if (C->getValue().isPowerOf2()) {
4274 uint64_t ShiftVal = C->getValue().logBase2();
4277 if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) {
4278 if (!isIntExtFree(ZExt)) {
4280 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) {
4283 Src0 = ZExt->getOperand(0);
4286 } else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) {
4287 if (!isIntExtFree(SExt)) {
4289 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) {
4292 Src0 = SExt->getOperand(0);
4297 unsigned Src0Reg = getRegForValue(Src0);
4300 bool Src0IsKill = hasTrivialKill(Src0);
4302 unsigned ResultReg =
4303 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);
4306 updateValueMap(I, ResultReg);
4311 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4314 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4316 unsigned Src1Reg = getRegForValue(I->getOperand(1));
4319 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
4321 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
4326 updateValueMap(I, ResultReg);
4330 bool AArch64FastISel::selectShift(const Instruction *I) {
4332 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
4335 if (RetVT.isVector())
4336 return selectOperator(I, I->getOpcode());
4338 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
4339 unsigned ResultReg = 0;
4340 uint64_t ShiftVal = C->getZExtValue();
4342 bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
4343 const Value *Op0 = I->getOperand(0);
4344 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
4345 if (!isIntExtFree(ZExt)) {
4347 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
4350 Op0 = ZExt->getOperand(0);
4353 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
4354 if (!isIntExtFree(SExt)) {
4356 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
4359 Op0 = SExt->getOperand(0);
4364 unsigned Op0Reg = getRegForValue(Op0);
4367 bool Op0IsKill = hasTrivialKill(Op0);
4369 switch (I->getOpcode()) {
4370 default: llvm_unreachable("Unexpected instruction.");
4371 case Instruction::Shl:
4372 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4374 case Instruction::AShr:
4375 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4377 case Instruction::LShr:
4378 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4384 updateValueMap(I, ResultReg);
4388 unsigned Op0Reg = getRegForValue(I->getOperand(0));
4391 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4393 unsigned Op1Reg = getRegForValue(I->getOperand(1));
4396 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
4398 unsigned ResultReg = 0;
4399 switch (I->getOpcode()) {
4400 default: llvm_unreachable("Unexpected instruction.");
4401 case Instruction::Shl:
4402 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4404 case Instruction::AShr:
4405 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4407 case Instruction::LShr:
4408 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4415 updateValueMap(I, ResultReg);
4419 bool AArch64FastISel::selectBitCast(const Instruction *I) {
4422 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
4424 if (!isTypeLegal(I->getType(), RetVT))
4428 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4429 Opc = AArch64::FMOVWSr;
4430 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4431 Opc = AArch64::FMOVXDr;
4432 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4433 Opc = AArch64::FMOVSWr;
4434 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4435 Opc = AArch64::FMOVDXr;
4439 const TargetRegisterClass *RC = nullptr;
4440 switch (RetVT.SimpleTy) {
4441 default: llvm_unreachable("Unexpected value type.");
4442 case MVT::i32: RC = &AArch64::GPR32RegClass; break;
4443 case MVT::i64: RC = &AArch64::GPR64RegClass; break;
4444 case MVT::f32: RC = &AArch64::FPR32RegClass; break;
4445 case MVT::f64: RC = &AArch64::FPR64RegClass; break;
4447 unsigned Op0Reg = getRegForValue(I->getOperand(0));
4450 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4451 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
4456 updateValueMap(I, ResultReg);
4460 bool AArch64FastISel::selectFRem(const Instruction *I) {
4462 if (!isTypeLegal(I->getType(), RetVT))
4466 switch (RetVT.SimpleTy) {
4470 LC = RTLIB::REM_F32;
4473 LC = RTLIB::REM_F64;
4478 Args.reserve(I->getNumOperands());
4480 // Populate the argument list.
4481 for (auto &Arg : I->operands()) {
4484 Entry.Ty = Arg->getType();
4485 Args.push_back(Entry);
4488 CallLoweringInfo CLI;
4489 CLI.setCallee(TLI.getLibcallCallingConv(LC), I->getType(),
4490 TLI.getLibcallName(LC), std::move(Args));
4491 if (!lowerCallTo(CLI))
4493 updateValueMap(I, CLI.ResultReg);
4497 bool AArch64FastISel::selectSDiv(const Instruction *I) {
4499 if (!isTypeLegal(I->getType(), VT))
4502 if (!isa<ConstantInt>(I->getOperand(1)))
4503 return selectBinaryOp(I, ISD::SDIV);
4505 const APInt &C = cast<ConstantInt>(I->getOperand(1))->getValue();
4506 if ((VT != MVT::i32 && VT != MVT::i64) || !C ||
4507 !(C.isPowerOf2() || (-C).isPowerOf2()))
4508 return selectBinaryOp(I, ISD::SDIV);
4510 unsigned Lg2 = C.countTrailingZeros();
4511 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4514 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4516 if (cast<BinaryOperator>(I)->isExact()) {
4517 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2);
4520 updateValueMap(I, ResultReg);
4524 int64_t Pow2MinusOne = (1ULL << Lg2) - 1;
4525 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne);
4529 // (Src0 < 0) ? Pow2 - 1 : 0;
4530 if (!emitICmp_ri(VT, Src0Reg, /*IsKill=*/false, 0))
4534 const TargetRegisterClass *RC;
4535 if (VT == MVT::i64) {
4536 SelectOpc = AArch64::CSELXr;
4537 RC = &AArch64::GPR64RegClass;
4539 SelectOpc = AArch64::CSELWr;
4540 RC = &AArch64::GPR32RegClass;
4542 unsigned SelectReg =
4543 fastEmitInst_rri(SelectOpc, RC, AddReg, /*IsKill=*/true, Src0Reg,
4544 Src0IsKill, AArch64CC::LT);
4548 // Divide by Pow2 --> ashr. If we're dividing by a negative value we must also
4549 // negate the result.
4550 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
4553 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
4554 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2);
4556 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2);
4561 updateValueMap(I, ResultReg);
4565 /// This is mostly a copy of the existing FastISel GEP code, but we have to
4566 /// duplicate it for AArch64, because otherwise we would bail out even for
4567 /// simple cases. This is because the standard fastEmit functions don't cover
4568 /// MUL at all and ADD is lowered very inefficientily.
4569 bool AArch64FastISel::selectGetElementPtr(const Instruction *I) {
4570 unsigned N = getRegForValue(I->getOperand(0));
4573 bool NIsKill = hasTrivialKill(I->getOperand(0));
4575 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
4576 // into a single N = N + TotalOffset.
4577 uint64_t TotalOffs = 0;
4578 Type *Ty = I->getOperand(0)->getType();
4579 MVT VT = TLI.getPointerTy();
4580 for (auto OI = std::next(I->op_begin()), E = I->op_end(); OI != E; ++OI) {
4581 const Value *Idx = *OI;
4582 if (auto *StTy = dyn_cast<StructType>(Ty)) {
4583 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
4586 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
4587 Ty = StTy->getElementType(Field);
4589 Ty = cast<SequentialType>(Ty)->getElementType();
4590 // If this is a constant subscript, handle it quickly.
4591 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
4596 DL.getTypeAllocSize(Ty) * cast<ConstantInt>(CI)->getSExtValue();
4600 N = emitAdd_ri_(VT, N, NIsKill, TotalOffs);
4607 // N = N + Idx * ElementSize;
4608 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
4609 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
4610 unsigned IdxN = Pair.first;
4611 bool IdxNIsKill = Pair.second;
4615 if (ElementSize != 1) {
4616 unsigned C = fastEmit_i(VT, VT, ISD::Constant, ElementSize);
4619 IdxN = emitMul_rr(VT, IdxN, IdxNIsKill, C, true);
4624 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
4630 N = emitAdd_ri_(VT, N, NIsKill, TotalOffs);
4634 updateValueMap(I, N);
4638 bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
4639 switch (I->getOpcode()) {
4642 case Instruction::Add:
4643 case Instruction::Sub:
4644 return selectAddSub(I);
4645 case Instruction::Mul:
4646 return selectMul(I);
4647 case Instruction::SDiv:
4648 return selectSDiv(I);
4649 case Instruction::SRem:
4650 if (!selectBinaryOp(I, ISD::SREM))
4651 return selectRem(I, ISD::SREM);
4653 case Instruction::URem:
4654 if (!selectBinaryOp(I, ISD::UREM))
4655 return selectRem(I, ISD::UREM);
4657 case Instruction::Shl:
4658 case Instruction::LShr:
4659 case Instruction::AShr:
4660 return selectShift(I);
4661 case Instruction::And:
4662 case Instruction::Or:
4663 case Instruction::Xor:
4664 return selectLogicalOp(I);
4665 case Instruction::Br:
4666 return selectBranch(I);
4667 case Instruction::IndirectBr:
4668 return selectIndirectBr(I);
4669 case Instruction::BitCast:
4670 if (!FastISel::selectBitCast(I))
4671 return selectBitCast(I);
4673 case Instruction::FPToSI:
4674 if (!selectCast(I, ISD::FP_TO_SINT))
4675 return selectFPToInt(I, /*Signed=*/true);
4677 case Instruction::FPToUI:
4678 return selectFPToInt(I, /*Signed=*/false);
4679 case Instruction::ZExt:
4680 case Instruction::SExt:
4681 return selectIntExt(I);
4682 case Instruction::Trunc:
4683 if (!selectCast(I, ISD::TRUNCATE))
4684 return selectTrunc(I);
4686 case Instruction::FPExt:
4687 return selectFPExt(I);
4688 case Instruction::FPTrunc:
4689 return selectFPTrunc(I);
4690 case Instruction::SIToFP:
4691 if (!selectCast(I, ISD::SINT_TO_FP))
4692 return selectIntToFP(I, /*Signed=*/true);
4694 case Instruction::UIToFP:
4695 return selectIntToFP(I, /*Signed=*/false);
4696 case Instruction::Load:
4697 return selectLoad(I);
4698 case Instruction::Store:
4699 return selectStore(I);
4700 case Instruction::FCmp:
4701 case Instruction::ICmp:
4702 return selectCmp(I);
4703 case Instruction::Select:
4704 return selectSelect(I);
4705 case Instruction::Ret:
4706 return selectRet(I);
4707 case Instruction::FRem:
4708 return selectFRem(I);
4709 case Instruction::GetElementPtr:
4710 return selectGetElementPtr(I);
4713 // fall-back to target-independent instruction selection.
4714 return selectOperator(I, I->getOpcode());
4715 // Silence warnings.
4716 (void)&CC_AArch64_DarwinPCS_VarArg;
4720 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo,
4721 const TargetLibraryInfo *LibInfo) {
4722 return new AArch64FastISel(FuncInfo, LibInfo);