1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
12 // On AArch64, stack frames are structured as follows:
14 // The stack grows downward.
16 // All of the individual frame areas on the frame below are optional, i.e. it's
17 // possible to create a function so that the particular area isn't present
20 // At function entry, the "frame" looks as follows:
23 // |-----------------------------------|
25 // | arguments passed on the stack |
27 // |-----------------------------------| <- sp
31 // After the prologue has run, the frame has the following general structure.
32 // Note that this doesn't depict the case where a red-zone is used. Also,
33 // technically the last frame area (VLAs) doesn't get created until in the
34 // main function body, after the prologue is run. However, it's depicted here
38 // |-----------------------------------|
40 // | arguments passed on the stack |
42 // |-----------------------------------|
44 // | prev_fp, prev_lr |
45 // | (a.k.a. "frame record") |
46 // |-----------------------------------| <- fp(=x29)
48 // | other callee-saved registers |
50 // |-----------------------------------|
51 // |.empty.space.to.make.part.below....|
52 // |.aligned.in.case.it.needs.more.than| (size of this area is unknown at
53 // |.the.standard.16-byte.alignment....| compile time; if present)
54 // |-----------------------------------|
56 // | local variables of fixed size |
57 // | including spill slots |
58 // |-----------------------------------| <- bp(not defined by ABI,
59 // |.variable-sized.local.variables....| LLVM chooses X19)
60 // |.(VLAs)............................| (size of this area is unknown at
61 // |...................................| compile time)
62 // |-----------------------------------| <- sp
66 // To access the data in a frame, at-compile time, a constant offset must be
67 // computable from one of the pointers (fp, bp, sp) to access it. The size
68 // of the areas with a dotted background cannot be computed at compile-time
69 // if they are present, making it required to have all three of fp, bp and
70 // sp to be set up to be able to access all contents in the frame areas,
71 // assuming all of the frame areas are non-empty.
73 // For most functions, some of the frame areas are empty. For those functions,
74 // it may not be necessary to set up fp or bp:
75 // * A base pointer is definitely needed when there are both VLAs and local
76 // variables with more-than-default alignment requirements.
77 // * A frame pointer is definitely needed when there are local variables with
78 // more-than-default alignment requirements.
80 // In some cases when a base pointer is not strictly needed, it is generated
81 // anyway when offsets from the frame pointer to access local variables become
82 // so large that the offset can't be encoded in the immediate fields of loads
85 // FIXME: also explain the redzone concept.
86 // FIXME: also explain the concept of reserved call frames.
88 //===----------------------------------------------------------------------===//
90 #include "AArch64FrameLowering.h"
91 #include "AArch64InstrInfo.h"
92 #include "AArch64MachineFunctionInfo.h"
93 #include "AArch64Subtarget.h"
94 #include "AArch64TargetMachine.h"
95 #include "llvm/ADT/Statistic.h"
96 #include "llvm/CodeGen/MachineFrameInfo.h"
97 #include "llvm/CodeGen/MachineFunction.h"
98 #include "llvm/CodeGen/MachineInstrBuilder.h"
99 #include "llvm/CodeGen/MachineModuleInfo.h"
100 #include "llvm/CodeGen/MachineRegisterInfo.h"
101 #include "llvm/CodeGen/RegisterScavenging.h"
102 #include "llvm/IR/DataLayout.h"
103 #include "llvm/IR/Function.h"
104 #include "llvm/Support/CommandLine.h"
105 #include "llvm/Support/Debug.h"
106 #include "llvm/Support/raw_ostream.h"
108 using namespace llvm;
110 #define DEBUG_TYPE "frame-info"
112 static cl::opt<bool> EnableRedZone("aarch64-redzone",
113 cl::desc("enable use of redzone on AArch64"),
114 cl::init(false), cl::Hidden);
116 STATISTIC(NumRedZoneFunctions, "Number of functions using red zone");
118 bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
121 // Don't use the red zone if the function explicitly asks us not to.
122 // This is typically used for kernel code.
123 if (MF.getFunction()->hasFnAttribute(Attribute::NoRedZone))
126 const MachineFrameInfo *MFI = MF.getFrameInfo();
127 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
128 unsigned NumBytes = AFI->getLocalStackSize();
130 // Note: currently hasFP() is always true for hasCalls(), but that's an
131 // implementation detail of the current code, not a strict requirement,
132 // so stay safe here and check both.
133 if (MFI->hasCalls() || hasFP(MF) || NumBytes > 128)
138 /// hasFP - Return true if the specified function should have a dedicated frame
139 /// pointer register.
140 bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
141 const MachineFrameInfo *MFI = MF.getFrameInfo();
142 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
143 return (MFI->hasCalls() || MFI->hasVarSizedObjects() ||
144 MFI->isFrameAddressTaken() || MFI->hasStackMap() ||
145 MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF));
148 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
149 /// not required, we reserve argument space for call sites in the function
150 /// immediately on entry to the current function. This eliminates the need for
151 /// add/sub sp brackets around call sites. Returns true if the call frame is
152 /// included as part of the stack frame.
154 AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
155 return !MF.getFrameInfo()->hasVarSizedObjects();
158 void AArch64FrameLowering::eliminateCallFramePseudoInstr(
159 MachineFunction &MF, MachineBasicBlock &MBB,
160 MachineBasicBlock::iterator I) const {
161 const AArch64InstrInfo *TII =
162 static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
163 DebugLoc DL = I->getDebugLoc();
164 unsigned Opc = I->getOpcode();
165 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
166 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
168 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
169 if (!TFI->hasReservedCallFrame(MF)) {
170 unsigned Align = getStackAlignment();
172 int64_t Amount = I->getOperand(0).getImm();
173 Amount = RoundUpToAlignment(Amount, Align);
177 // N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
178 // doesn't have to pop anything), then the first operand will be zero too so
179 // this adjustment is a no-op.
180 if (CalleePopAmount == 0) {
181 // FIXME: in-function stack adjustment for calls is limited to 24-bits
182 // because there's no guaranteed temporary register available.
184 // ADD/SUB (immediate) has only LSL #0 and LSL #12 available.
185 // 1) For offset <= 12-bit, we use LSL #0
186 // 2) For 12-bit <= offset <= 24-bit, we use two instructions. One uses
187 // LSL #0, and the other uses LSL #12.
189 // Mostly call frames will be allocated at the start of a function so
190 // this is OK, but it is a limitation that needs dealing with.
191 assert(Amount > -0xffffff && Amount < 0xffffff && "call frame too large");
192 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
194 } else if (CalleePopAmount != 0) {
195 // If the calling convention demands that the callee pops arguments from the
196 // stack, we want to add it back if we have a reserved call frame.
197 assert(CalleePopAmount < 0xffffff && "call frame too large");
198 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
204 void AArch64FrameLowering::emitCalleeSavedFrameMoves(
205 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
206 unsigned FramePtr) const {
207 MachineFunction &MF = *MBB.getParent();
208 MachineFrameInfo *MFI = MF.getFrameInfo();
209 MachineModuleInfo &MMI = MF.getMMI();
210 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
211 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
212 DebugLoc DL = MBB.findDebugLoc(MBBI);
214 // Add callee saved registers to move list.
215 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
219 const DataLayout &TD = MF.getDataLayout();
220 bool HasFP = hasFP(MF);
222 // Calculate amount of bytes used for return address storing.
223 int stackGrowth = -TD.getPointerSize(0);
225 // Calculate offsets.
226 int64_t saveAreaOffset = (HasFP ? 2 : 1) * stackGrowth;
227 unsigned TotalSkipped = 0;
228 for (const auto &Info : CSI) {
229 unsigned Reg = Info.getReg();
230 int64_t Offset = MFI->getObjectOffset(Info.getFrameIdx()) -
231 getOffsetOfLocalArea() + saveAreaOffset;
233 // Don't output a new CFI directive if we're re-saving the frame pointer or
234 // link register. This happens when the PrologEpilogInserter has inserted an
235 // extra "STP" of the frame pointer and link register -- the "emitPrologue"
236 // method automatically generates the directives when frame pointers are
237 // used. If we generate CFI directives for the extra "STP"s, the linker will
238 // lose track of the correct values for the frame pointer and link register.
239 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) {
240 TotalSkipped += stackGrowth;
244 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
245 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
246 nullptr, DwarfReg, Offset - TotalSkipped));
247 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
248 .addCFIIndex(CFIIndex)
249 .setMIFlags(MachineInstr::FrameSetup);
253 /// Get FPOffset by analyzing the first instruction.
254 static int getFPOffsetInPrologue(MachineInstr *MBBI) {
255 // First instruction must a) allocate the stack and b) have an immediate
256 // that is a multiple of -2.
257 assert(((MBBI->getOpcode() == AArch64::STPXpre ||
258 MBBI->getOpcode() == AArch64::STPDpre) &&
259 MBBI->getOperand(3).getReg() == AArch64::SP &&
260 MBBI->getOperand(4).getImm() < 0 &&
261 (MBBI->getOperand(4).getImm() & 1) == 0));
263 // Frame pointer is fp = sp - 16. Since the STPXpre subtracts the space
264 // required for the callee saved register area we get the frame pointer
265 // by addding that offset - 16 = -getImm()*8 - 2*8 = -(getImm() + 2) * 8.
266 int FPOffset = -(MBBI->getOperand(4).getImm() + 2) * 8;
267 assert(FPOffset >= 0 && "Bad Framepointer Offset");
271 static bool isCSSave(MachineInstr *MBBI) {
272 return MBBI->getOpcode() == AArch64::STPXi ||
273 MBBI->getOpcode() == AArch64::STPDi ||
274 MBBI->getOpcode() == AArch64::STPXpre ||
275 MBBI->getOpcode() == AArch64::STPDpre;
278 void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
279 MachineBasicBlock &MBB) const {
280 MachineBasicBlock::iterator MBBI = MBB.begin();
281 const MachineFrameInfo *MFI = MF.getFrameInfo();
282 const Function *Fn = MF.getFunction();
283 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
284 MF.getSubtarget().getRegisterInfo());
285 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
286 MachineModuleInfo &MMI = MF.getMMI();
287 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
288 bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
289 bool HasFP = hasFP(MF);
290 DebugLoc DL = MBB.findDebugLoc(MBBI);
292 // All calls are tail calls in GHC calling conv, and functions have no
293 // prologue/epilogue.
294 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
297 int NumBytes = (int)MFI->getStackSize();
298 if (!AFI->hasStackFrame()) {
299 assert(!HasFP && "unexpected function without stack frame but with FP");
301 // All of the stack allocation is for locals.
302 AFI->setLocalStackSize(NumBytes);
304 // Label used to tie together the PROLOG_LABEL and the MachineMoves.
305 MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
307 // REDZONE: If the stack size is less than 128 bytes, we don't need
308 // to actually allocate.
309 if (NumBytes && !canUseRedZone(MF)) {
310 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
311 MachineInstr::FrameSetup);
313 // Encode the stack size of the leaf function.
314 unsigned CFIIndex = MMI.addFrameInst(
315 MCCFIInstruction::createDefCfaOffset(FrameLabel, -NumBytes));
316 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
317 .addCFIIndex(CFIIndex)
318 .setMIFlags(MachineInstr::FrameSetup);
319 } else if (NumBytes) {
320 ++NumRedZoneFunctions;
326 // Only set up FP if we actually need to.
329 FPOffset = getFPOffsetInPrologue(MBBI);
331 // Move past the saves of the callee-saved registers.
332 while (isCSSave(MBBI)) {
336 assert(NumBytes >= 0 && "Negative stack allocation size!?");
338 // Issue sub fp, sp, FPOffset or
339 // mov fp,sp when FPOffset is zero.
340 // Note: All stores of callee-saved registers are marked as "FrameSetup".
341 // This code marks the instruction(s) that set the FP also.
342 emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
343 MachineInstr::FrameSetup);
346 // All of the remaining stack allocations are for locals.
347 AFI->setLocalStackSize(NumBytes);
349 // Allocate space for the rest of the frame.
351 const unsigned Alignment = MFI->getMaxAlignment();
352 const bool NeedsRealignment = RegInfo->needsStackRealignment(MF);
353 unsigned scratchSPReg = AArch64::SP;
354 if (NumBytes && NeedsRealignment) {
355 // Use the first callee-saved register as a scratch register.
356 scratchSPReg = AArch64::X9;
359 // If we're a leaf function, try using the red zone.
360 if (NumBytes && !canUseRedZone(MF))
361 // FIXME: in the case of dynamic re-alignment, NumBytes doesn't have
362 // the correct value here, as NumBytes also includes padding bytes,
363 // which shouldn't be counted here.
364 emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP, -NumBytes, TII,
365 MachineInstr::FrameSetup);
367 if (NumBytes && NeedsRealignment) {
368 const unsigned NrBitsToZero = countTrailingZeros(Alignment);
369 assert(NrBitsToZero > 1);
370 assert(scratchSPReg != AArch64::SP);
372 // SUB X9, SP, NumBytes
373 // -- X9 is temporary register, so shouldn't contain any live data here,
374 // -- free to use. This is already produced by emitFrameOffset above.
375 // AND SP, X9, 0b11111...0000
376 // The logical immediates have a non-trivial encoding. The following
377 // formula computes the encoded immediate with all ones but
378 // NrBitsToZero zero bits as least significant bits.
379 uint32_t andMaskEncoded =
381 | ((64-NrBitsToZero) << 6) // immr
382 | ((64-NrBitsToZero-1) << 0) // imms
384 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
385 .addReg(scratchSPReg, RegState::Kill)
386 .addImm(andMaskEncoded);
389 // If we need a base pointer, set it up here. It's whatever the value of the
390 // stack pointer is at this point. Any variable size objects will be allocated
391 // after this, so we can still use the base pointer to reference locals.
393 // FIXME: Clarify FrameSetup flags here.
394 // Note: Use emitFrameOffset() like above for FP if the FrameSetup flag is
396 if (RegInfo->hasBasePointer(MF)) {
397 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
401 if (needsFrameMoves) {
402 const DataLayout &TD = MF.getDataLayout();
403 const int StackGrowth = -TD.getPointerSize(0);
404 unsigned FramePtr = RegInfo->getFrameRegister(MF);
405 // An example of the prologue:
412 // .cfi_personality 155, ___gxx_personality_v0
414 // .cfi_lsda 16, Lexception33
416 // stp xa,bx, [sp, -#offset]!
418 // stp x28, x27, [sp, #offset-32]
419 // stp fp, lr, [sp, #offset-16]
420 // add fp, sp, #offset - 16
424 // +-------------------------------------------+
425 // 10000 | ........ | ........ | ........ | ........ |
426 // 10004 | ........ | ........ | ........ | ........ |
427 // +-------------------------------------------+
428 // 10008 | ........ | ........ | ........ | ........ |
429 // 1000c | ........ | ........ | ........ | ........ |
430 // +===========================================+
431 // 10010 | X28 Register |
432 // 10014 | X28 Register |
433 // +-------------------------------------------+
434 // 10018 | X27 Register |
435 // 1001c | X27 Register |
436 // +===========================================+
437 // 10020 | Frame Pointer |
438 // 10024 | Frame Pointer |
439 // +-------------------------------------------+
440 // 10028 | Link Register |
441 // 1002c | Link Register |
442 // +===========================================+
443 // 10030 | ........ | ........ | ........ | ........ |
444 // 10034 | ........ | ........ | ........ | ........ |
445 // +-------------------------------------------+
446 // 10038 | ........ | ........ | ........ | ........ |
447 // 1003c | ........ | ........ | ........ | ........ |
448 // +-------------------------------------------+
450 // [sp] = 10030 :: >>initial value<<
451 // sp = 10020 :: stp fp, lr, [sp, #-16]!
452 // fp = sp == 10020 :: mov fp, sp
453 // [sp] == 10020 :: stp x28, x27, [sp, #-16]!
454 // sp == 10010 :: >>final value<<
456 // The frame pointer (w29) points to address 10020. If we use an offset of
457 // '16' from 'w29', we get the CFI offsets of -8 for w30, -16 for w29, -24
458 // for w27, and -32 for w28:
461 // .cfi_def_cfa w29, 16
463 // .cfi_offset w30, -8
465 // .cfi_offset w29, -16
467 // .cfi_offset w27, -24
469 // .cfi_offset w28, -32
472 // Define the current CFA rule to use the provided FP.
473 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
474 unsigned CFIIndex = MMI.addFrameInst(
475 MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth));
476 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
477 .addCFIIndex(CFIIndex)
478 .setMIFlags(MachineInstr::FrameSetup);
480 // Record the location of the stored LR
481 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
482 CFIIndex = MMI.addFrameInst(
483 MCCFIInstruction::createOffset(nullptr, LR, StackGrowth));
484 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
485 .addCFIIndex(CFIIndex)
486 .setMIFlags(MachineInstr::FrameSetup);
488 // Record the location of the stored FP
489 CFIIndex = MMI.addFrameInst(
490 MCCFIInstruction::createOffset(nullptr, Reg, 2 * StackGrowth));
491 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
492 .addCFIIndex(CFIIndex)
493 .setMIFlags(MachineInstr::FrameSetup);
495 // Encode the stack size of the leaf function.
496 unsigned CFIIndex = MMI.addFrameInst(
497 MCCFIInstruction::createDefCfaOffset(nullptr, -MFI->getStackSize()));
498 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
499 .addCFIIndex(CFIIndex)
500 .setMIFlags(MachineInstr::FrameSetup);
503 // Now emit the moves for whatever callee saved regs we have.
504 emitCalleeSavedFrameMoves(MBB, MBBI, FramePtr);
508 static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) {
509 for (unsigned i = 0; CSRegs[i]; ++i)
510 if (Reg == CSRegs[i])
515 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
517 if (MI->getOpcode() == AArch64::LDPXpost ||
518 MI->getOpcode() == AArch64::LDPDpost)
521 if (MI->getOpcode() == AArch64::LDPXpost ||
522 MI->getOpcode() == AArch64::LDPDpost ||
523 MI->getOpcode() == AArch64::LDPXi || MI->getOpcode() == AArch64::LDPDi) {
524 if (!isCalleeSavedRegister(MI->getOperand(RtIdx).getReg(), CSRegs) ||
525 !isCalleeSavedRegister(MI->getOperand(RtIdx + 1).getReg(), CSRegs) ||
526 MI->getOperand(RtIdx + 2).getReg() != AArch64::SP)
534 void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
535 MachineBasicBlock &MBB) const {
536 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
537 MachineFrameInfo *MFI = MF.getFrameInfo();
538 const AArch64InstrInfo *TII =
539 static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
540 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
541 MF.getSubtarget().getRegisterInfo());
543 bool IsTailCallReturn = false;
544 if (MBB.end() != MBBI) {
545 DL = MBBI->getDebugLoc();
546 unsigned RetOpcode = MBBI->getOpcode();
547 IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
548 RetOpcode == AArch64::TCRETURNri;
550 int NumBytes = MFI->getStackSize();
551 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
553 // All calls are tail calls in GHC calling conv, and functions have no
554 // prologue/epilogue.
555 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
558 // Initial and residual are named for consistency with the prologue. Note that
559 // in the epilogue, the residual adjustment is executed first.
560 uint64_t ArgumentPopSize = 0;
561 if (IsTailCallReturn) {
562 MachineOperand &StackAdjust = MBBI->getOperand(1);
564 // For a tail-call in a callee-pops-arguments environment, some or all of
565 // the stack may actually be in use for the call's arguments, this is
566 // calculated during LowerCall and consumed here...
567 ArgumentPopSize = StackAdjust.getImm();
569 // ... otherwise the amount to pop is *all* of the argument space,
570 // conveniently stored in the MachineFunctionInfo by
571 // LowerFormalArguments. This will, of course, be zero for the C calling
573 ArgumentPopSize = AFI->getArgumentStackToRestore();
576 // The stack frame should be like below,
578 // ---------------------- ---
580 // | BytesInStackArgArea| CalleeArgStackSize
581 // | (NumReusableBytes) | (of tail call)
584 // ---------------------| --- |
586 // | CalleeSavedReg | | |
587 // | (NumRestores * 16) | | |
589 // ---------------------| | NumBytes
590 // | | StackSize (StackAdjustUp)
591 // | LocalStackSize | | |
592 // | (covering callee | | |
595 // ---------------------- --- ---
597 // So NumBytes = StackSize + BytesInStackArgArea - CalleeArgStackSize
598 // = StackSize + ArgumentPopSize
600 // AArch64TargetLowering::LowerCall figures out ArgumentPopSize and keeps
601 // it as the 2nd argument of AArch64ISD::TC_RETURN.
602 NumBytes += ArgumentPopSize;
604 unsigned NumRestores = 0;
605 // Move past the restores of the callee-saved registers.
606 MachineBasicBlock::iterator LastPopI = MBB.getFirstTerminator();
607 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
608 if (LastPopI != MBB.begin()) {
612 } while (LastPopI != MBB.begin() && isCSRestore(LastPopI, CSRegs));
613 if (!isCSRestore(LastPopI, CSRegs)) {
618 NumBytes -= NumRestores * 16;
619 assert(NumBytes >= 0 && "Negative stack allocation size!?");
622 // If this was a redzone leaf function, we don't need to restore the
624 if (!canUseRedZone(MF))
625 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes,
630 // Restore the original stack pointer.
631 // FIXME: Rather than doing the math here, we should instead just use
632 // non-post-indexed loads for the restores if we aren't actually going to
633 // be able to save any instructions.
634 if (NumBytes || MFI->hasVarSizedObjects())
635 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
636 -(NumRestores - 1) * 16, TII, MachineInstr::NoFlags);
639 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
640 /// debug info. It's the same as what we use for resolving the code-gen
641 /// references for now. FIXME: This can go wrong when references are
642 /// SP-relative and simple call frames aren't used.
643 int AArch64FrameLowering::getFrameIndexReference(const MachineFunction &MF,
645 unsigned &FrameReg) const {
646 return resolveFrameIndexReference(MF, FI, FrameReg);
649 int AArch64FrameLowering::resolveFrameIndexReference(const MachineFunction &MF,
650 int FI, unsigned &FrameReg,
651 bool PreferFP) const {
652 const MachineFrameInfo *MFI = MF.getFrameInfo();
653 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
654 MF.getSubtarget().getRegisterInfo());
655 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
656 int FPOffset = MFI->getObjectOffset(FI) + 16;
657 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
658 bool isFixed = MFI->isFixedObjectIndex(FI);
660 // Use frame pointer to reference fixed objects. Use it for locals if
661 // there are VLAs or a dynamically realigned SP (and thus the SP isn't
662 // reliable as a base). Make sure useFPForScavengingIndex() does the
663 // right thing for the emergency spill slot.
665 if (AFI->hasStackFrame()) {
666 // Note: Keeping the following as multiple 'if' statements rather than
667 // merging to a single expression for readability.
669 // Argument access should always use the FP.
672 } else if (hasFP(MF) && !RegInfo->hasBasePointer(MF) &&
673 !RegInfo->needsStackRealignment(MF)) {
674 // Use SP or FP, whichever gives us the best chance of the offset
675 // being in range for direct access. If the FPOffset is positive,
676 // that'll always be best, as the SP will be even further away.
677 // If the FPOffset is negative, we have to keep in mind that the
678 // available offset range for negative offsets is smaller than for
679 // positive ones. If we have variable sized objects, we're stuck with
680 // using the FP regardless, though, as the SP offset is unknown
681 // and we don't have a base pointer available. If an offset is
682 // available via the FP and the SP, use whichever is closest.
683 if (PreferFP || MFI->hasVarSizedObjects() || FPOffset >= 0 ||
684 (FPOffset >= -256 && Offset > -FPOffset))
689 assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) &&
690 "In the presence of dynamic stack pointer realignment, "
691 "non-argument objects cannot be accessed through the frame pointer");
694 FrameReg = RegInfo->getFrameRegister(MF);
698 // Use the base pointer if we have one.
699 if (RegInfo->hasBasePointer(MF))
700 FrameReg = RegInfo->getBaseRegister();
702 FrameReg = AArch64::SP;
703 // If we're using the red zone for this function, the SP won't actually
704 // be adjusted, so the offsets will be negative. They're also all
705 // within range of the signed 9-bit immediate instructions.
706 if (canUseRedZone(MF))
707 Offset -= AFI->getLocalStackSize();
713 static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
714 if (Reg != AArch64::LR)
715 return getKillRegState(true);
717 // LR maybe referred to later by an @llvm.returnaddress intrinsic.
718 bool LRLiveIn = MF.getRegInfo().isLiveIn(AArch64::LR);
719 bool LRKill = !(LRLiveIn && MF.getFrameInfo()->isReturnAddressTaken());
720 return getKillRegState(LRKill);
723 bool AArch64FrameLowering::spillCalleeSavedRegisters(
724 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
725 const std::vector<CalleeSavedInfo> &CSI,
726 const TargetRegisterInfo *TRI) const {
727 MachineFunction &MF = *MBB.getParent();
728 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
729 unsigned Count = CSI.size();
731 assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
734 DL = MI->getDebugLoc();
736 for (unsigned i = 0; i < Count; i += 2) {
737 unsigned idx = Count - i - 2;
738 unsigned Reg1 = CSI[idx].getReg();
739 unsigned Reg2 = CSI[idx + 1].getReg();
740 // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
741 // list to come in sorted by frame index so that we can issue the store
742 // pair instructions directly. Assert if we see anything otherwise.
744 // The order of the registers in the list is controlled by
745 // getCalleeSavedRegs(), so they will always be in-order, as well.
746 assert(CSI[idx].getFrameIdx() + 1 == CSI[idx + 1].getFrameIdx() &&
747 "Out of order callee saved regs!");
749 assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
750 assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
751 // Issue sequence of non-sp increment and pi sp spills for cs regs. The
752 // first spill is a pre-increment that allocates the stack.
754 // stp x22, x21, [sp, #-48]! // addImm(-6)
755 // stp x20, x19, [sp, #16] // addImm(+2)
756 // stp fp, lr, [sp, #32] // addImm(+4)
757 // Rationale: This sequence saves uop updates compared to a sequence of
758 // pre-increment spills like stp xi,xj,[sp,#-16]!
759 // Note: Similar rational and sequence for restores in epilog.
760 if (AArch64::GPR64RegClass.contains(Reg1)) {
761 assert(AArch64::GPR64RegClass.contains(Reg2) &&
762 "Expected GPR64 callee-saved register pair!");
763 // For first spill use pre-increment store.
765 StrOpc = AArch64::STPXpre;
767 StrOpc = AArch64::STPXi;
768 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
769 assert(AArch64::FPR64RegClass.contains(Reg2) &&
770 "Expected FPR64 callee-saved register pair!");
771 // For first spill use pre-increment store.
773 StrOpc = AArch64::STPDpre;
775 StrOpc = AArch64::STPDi;
777 llvm_unreachable("Unexpected callee saved register!");
778 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
779 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
780 << ", " << CSI[idx + 1].getFrameIdx() << ")\n");
781 // Compute offset: i = 0 => offset = -Count;
782 // i = 2 => offset = -(Count - 2) + Count = 2 = i; etc.
783 const int Offset = (i == 0) ? -Count : i;
784 assert((Offset >= -64 && Offset <= 63) &&
785 "Offset out of bounds for STP immediate");
786 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
787 if (StrOpc == AArch64::STPDpre || StrOpc == AArch64::STPXpre)
788 MIB.addReg(AArch64::SP, RegState::Define);
792 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
793 .addReg(Reg1, getPrologueDeath(MF, Reg1))
795 .addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit
796 .setMIFlag(MachineInstr::FrameSetup);
801 bool AArch64FrameLowering::restoreCalleeSavedRegisters(
802 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
803 const std::vector<CalleeSavedInfo> &CSI,
804 const TargetRegisterInfo *TRI) const {
805 MachineFunction &MF = *MBB.getParent();
806 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
807 unsigned Count = CSI.size();
809 assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
812 DL = MI->getDebugLoc();
814 for (unsigned i = 0; i < Count; i += 2) {
815 unsigned Reg1 = CSI[i].getReg();
816 unsigned Reg2 = CSI[i + 1].getReg();
817 // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
818 // list to come in sorted by frame index so that we can issue the store
819 // pair instructions directly. Assert if we see anything otherwise.
820 assert(CSI[i].getFrameIdx() + 1 == CSI[i + 1].getFrameIdx() &&
821 "Out of order callee saved regs!");
822 // Issue sequence of non-sp increment and sp-pi restores for cs regs. Only
823 // the last load is sp-pi post-increment and de-allocates the stack:
825 // ldp fp, lr, [sp, #32] // addImm(+4)
826 // ldp x20, x19, [sp, #16] // addImm(+2)
827 // ldp x22, x21, [sp], #48 // addImm(+6)
828 // Note: see comment in spillCalleeSavedRegisters()
831 assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
832 assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
833 if (AArch64::GPR64RegClass.contains(Reg1)) {
834 assert(AArch64::GPR64RegClass.contains(Reg2) &&
835 "Expected GPR64 callee-saved register pair!");
837 LdrOpc = AArch64::LDPXpost;
839 LdrOpc = AArch64::LDPXi;
840 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
841 assert(AArch64::FPR64RegClass.contains(Reg2) &&
842 "Expected FPR64 callee-saved register pair!");
844 LdrOpc = AArch64::LDPDpost;
846 LdrOpc = AArch64::LDPDi;
848 llvm_unreachable("Unexpected callee saved register!");
849 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
850 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx()
851 << ", " << CSI[i + 1].getFrameIdx() << ")\n");
853 // Compute offset: i = 0 => offset = Count - 2; i = 2 => offset = Count - 4;
855 const int Offset = (i == Count - 2) ? Count : Count - i - 2;
856 assert((Offset >= -64 && Offset <= 63) &&
857 "Offset out of bounds for LDP immediate");
858 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
859 if (LdrOpc == AArch64::LDPXpost || LdrOpc == AArch64::LDPDpost)
860 MIB.addReg(AArch64::SP, RegState::Define);
862 MIB.addReg(Reg2, getDefRegState(true))
863 .addReg(Reg1, getDefRegState(true))
865 .addImm(Offset); // [sp], #offset * 8 or [sp, #offset * 8]
866 // where the factor * 8 is implicit
871 void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
872 BitVector &SavedRegs,
873 RegScavenger *RS) const {
874 // All calls are tail calls in GHC calling conv, and functions have no
875 // prologue/epilogue.
876 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
879 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
880 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
881 MF.getSubtarget().getRegisterInfo());
882 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
883 SmallVector<unsigned, 4> UnspilledCSGPRs;
884 SmallVector<unsigned, 4> UnspilledCSFPRs;
886 // The frame record needs to be created by saving the appropriate registers
888 SavedRegs.set(AArch64::FP);
889 SavedRegs.set(AArch64::LR);
892 // Spill the BasePtr if it's used. Do this first thing so that the
893 // getCalleeSavedRegs() below will get the right answer.
894 if (RegInfo->hasBasePointer(MF))
895 SavedRegs.set(RegInfo->getBaseRegister());
897 if (RegInfo->needsStackRealignment(MF) && !RegInfo->hasBasePointer(MF))
898 SavedRegs.set(AArch64::X9);
900 // If any callee-saved registers are used, the frame cannot be eliminated.
901 unsigned NumGPRSpilled = 0;
902 unsigned NumFPRSpilled = 0;
903 bool ExtraCSSpill = false;
904 bool CanEliminateFrame = true;
905 DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:");
906 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
908 // Check pairs of consecutive callee-saved registers.
909 for (unsigned i = 0; CSRegs[i]; i += 2) {
910 assert(CSRegs[i + 1] && "Odd number of callee-saved registers!");
912 const unsigned OddReg = CSRegs[i];
913 const unsigned EvenReg = CSRegs[i + 1];
914 assert((AArch64::GPR64RegClass.contains(OddReg) &&
915 AArch64::GPR64RegClass.contains(EvenReg)) ^
916 (AArch64::FPR64RegClass.contains(OddReg) &&
917 AArch64::FPR64RegClass.contains(EvenReg)) &&
918 "Register class mismatch!");
920 const bool OddRegUsed = SavedRegs.test(OddReg);
921 const bool EvenRegUsed = SavedRegs.test(EvenReg);
923 // Early exit if none of the registers in the register pair is actually
925 if (!OddRegUsed && !EvenRegUsed) {
926 if (AArch64::GPR64RegClass.contains(OddReg)) {
927 UnspilledCSGPRs.push_back(OddReg);
928 UnspilledCSGPRs.push_back(EvenReg);
930 UnspilledCSFPRs.push_back(OddReg);
931 UnspilledCSFPRs.push_back(EvenReg);
936 unsigned Reg = AArch64::NoRegister;
937 // If only one of the registers of the register pair is used, make sure to
938 // mark the other one as used as well.
939 if (OddRegUsed ^ EvenRegUsed) {
940 // Find out which register is the additional spill.
941 Reg = OddRegUsed ? EvenReg : OddReg;
945 DEBUG(dbgs() << ' ' << PrintReg(OddReg, RegInfo));
946 DEBUG(dbgs() << ' ' << PrintReg(EvenReg, RegInfo));
948 assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) ||
949 (RegInfo->getEncodingValue(OddReg) + 1 ==
950 RegInfo->getEncodingValue(EvenReg))) &&
951 "Register pair of non-adjacent registers!");
952 if (AArch64::GPR64RegClass.contains(OddReg)) {
954 // If it's not a reserved register, we can use it in lieu of an
955 // emergency spill slot for the register scavenger.
956 // FIXME: It would be better to instead keep looking and choose another
957 // unspilled register that isn't reserved, if there is one.
958 if (Reg != AArch64::NoRegister && !RegInfo->isReservedReg(MF, Reg))
963 CanEliminateFrame = false;
966 // FIXME: Set BigStack if any stack slot references may be out of range.
967 // For now, just conservatively guestimate based on unscaled indexing
968 // range. We'll end up allocating an unnecessary spill slot a lot, but
969 // realistically that's not a big deal at this stage of the game.
970 // The CSR spill slots have not been allocated yet, so estimateStackSize
971 // won't include them.
972 MachineFrameInfo *MFI = MF.getFrameInfo();
974 MFI->estimateStackSize(MF) + 8 * (NumGPRSpilled + NumFPRSpilled);
975 DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n");
976 bool BigStack = (CFSize >= 256);
977 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
978 AFI->setHasStackFrame(true);
980 // Estimate if we might need to scavenge a register at some point in order
981 // to materialize a stack offset. If so, either spill one additional
982 // callee-saved register or reserve a special spill slot to facilitate
983 // register scavenging. If we already spilled an extra callee-saved register
984 // above to keep the number of spills even, we don't need to do anything else
986 if (BigStack && !ExtraCSSpill) {
988 // If we're adding a register to spill here, we have to add two of them
989 // to keep the number of regs to spill even.
990 assert(((UnspilledCSGPRs.size() & 1) == 0) && "Odd number of registers!");
992 while (!UnspilledCSGPRs.empty() && Count < 2) {
993 unsigned Reg = UnspilledCSGPRs.back();
994 UnspilledCSGPRs.pop_back();
995 DEBUG(dbgs() << "Spilling " << PrintReg(Reg, RegInfo)
996 << " to get a scratch register.\n");
1002 // If we didn't find an extra callee-saved register to spill, create
1003 // an emergency spill slot.
1004 if (!ExtraCSSpill) {
1005 const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
1006 int FI = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false);
1007 RS->addScavengingFrameIndex(FI);
1008 DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
1009 << " as the emergency spill slot.\n");