1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the AArch64 target.
12 //===----------------------------------------------------------------------===//
15 #include "AArch64InstrInfo.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetMachine.h"
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/ADT/APSInt.h"
20 #include "llvm/CodeGen/SelectionDAGISel.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "aarch64-isel"
29 //===--------------------------------------------------------------------===//
30 /// AArch64 specific code to select AArch64 machine instructions for
31 /// SelectionDAG operations.
35 class AArch64DAGToDAGISel : public SelectionDAGISel {
36 AArch64TargetMachine &TM;
38 /// Keep a pointer to the AArch64Subtarget around so that we can
39 /// make the right decision when generating code for different targets.
40 const AArch64Subtarget *Subtarget;
43 explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
44 CodeGenOpt::Level OptLevel)
45 : SelectionDAGISel(tm, OptLevel), TM(tm),
46 Subtarget(&TM.getSubtarget<AArch64Subtarget>()) {
49 virtual const char *getPassName() const {
50 return "AArch64 Instruction Selection";
53 // Include the pieces autogenerated from the target description.
54 #include "AArch64GenDAGISel.inc"
56 template<unsigned MemSize>
57 bool SelectOffsetUImm12(SDValue N, SDValue &UImm12) {
58 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
59 if (!CN || CN->getZExtValue() % MemSize != 0
60 || CN->getZExtValue() / MemSize > 0xfff)
63 UImm12 = CurDAG->getTargetConstant(CN->getZExtValue() / MemSize, MVT::i64);
67 template<unsigned RegWidth>
68 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
69 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
72 /// Used for pre-lowered address-reference nodes, so we already know
73 /// the fields match. This operand's job is simply to add an
74 /// appropriate shift operand to the MOVZ/MOVK instruction.
75 template<unsigned LogShift>
76 bool SelectMOVWAddressRef(SDValue N, SDValue &Imm, SDValue &Shift) {
78 Shift = CurDAG->getTargetConstant(LogShift, MVT::i32);
82 bool SelectFPZeroOperand(SDValue N, SDValue &Dummy);
84 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
87 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
89 std::vector<SDValue> &OutOps);
91 bool SelectLogicalImm(SDValue N, SDValue &Imm);
93 template<unsigned RegWidth>
94 bool SelectTSTBOperand(SDValue N, SDValue &FixedPos) {
95 return SelectTSTBOperand(N, FixedPos, RegWidth);
98 bool SelectTSTBOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth);
100 SDNode *SelectAtomic(SDNode *N, unsigned Op8, unsigned Op16, unsigned Op32,
103 /// Put the given constant into a pool and return a DAG which will give its
105 SDValue getConstantPoolItemAddress(SDLoc DL, const Constant *CV);
107 SDNode *TrySelectToMoveImm(SDNode *N);
108 SDNode *LowerToFPLitPool(SDNode *Node);
109 SDNode *SelectToLitPool(SDNode *N);
111 SDNode* Select(SDNode*);
113 /// Get the opcode for table lookup instruction
114 unsigned getTBLOpc(bool IsExt, bool Is64Bit, unsigned NumOfVec);
116 /// Select NEON table lookup intrinsics. NumVecs should be 1, 2, 3 or 4.
117 /// IsExt is to indicate if the result will be extended with an argument.
118 SDNode *SelectVTBL(SDNode *N, unsigned NumVecs, bool IsExt);
120 /// Select NEON load intrinsics. NumVecs should be 1, 2, 3 or 4.
121 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
122 const uint16_t *Opcode);
124 /// Select NEON store intrinsics. NumVecs should be 1, 2, 3 or 4.
125 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
126 const uint16_t *Opcodes);
128 /// Form sequences of consecutive 64/128-bit registers for use in NEON
129 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
130 /// between 1 and 4 elements. If it contains a single element that is returned
131 /// unchanged; otherwise a REG_SEQUENCE value is returned.
132 SDValue createDTuple(ArrayRef<SDValue> Vecs);
133 SDValue createQTuple(ArrayRef<SDValue> Vecs);
135 /// Generic helper for the createDTuple/createQTuple
136 /// functions. Those should almost always be called instead.
137 SDValue createTuple(ArrayRef<SDValue> Vecs, unsigned RegClassIDs[],
140 /// Select NEON load-duplicate intrinsics. NumVecs should be 2, 3 or 4.
141 /// The opcode array specifies the instructions used for load.
142 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
143 const uint16_t *Opcodes);
145 /// Select NEON load/store lane intrinsics. NumVecs should be 2, 3 or 4.
146 /// The opcode arrays specify the instructions used for load/store.
147 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
148 unsigned NumVecs, const uint16_t *Opcodes);
150 SDValue getTargetSubregToReg(int SRIdx, SDLoc DL, EVT VT, EVT VTD,
156 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
158 const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
159 if (!CN) return false;
161 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
162 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
165 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
166 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
170 // fbits is between 1 and 64 in the worst-case, which means the fmul
171 // could have 2^64 as an actual operand. Need 65 bits of precision.
172 APSInt IntVal(65, true);
173 CN->getValueAPF().convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
175 // N.b. isPowerOf2 also checks for > 0.
176 if (!IsExact || !IntVal.isPowerOf2()) return false;
177 unsigned FBits = IntVal.logBase2();
179 // Checks above should have guaranteed that we haven't lost information in
180 // finding FBits, but it must still be in range.
181 if (FBits == 0 || FBits > RegWidth) return false;
183 FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);
188 AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
190 std::vector<SDValue> &OutOps) {
191 switch (ConstraintCode) {
192 default: llvm_unreachable("Unrecognised AArch64 memory constraint");
194 // FIXME: more freedom is actually permitted for 'm'. We can go
195 // hunting for a base and an offset if we want. Of course, since
196 // we don't really know how the operand is going to be used we're
197 // probably restricted to the load/store pair's simm7 as an offset
200 OutOps.push_back(Op);
207 AArch64DAGToDAGISel::SelectFPZeroOperand(SDValue N, SDValue &Dummy) {
208 ConstantFPSDNode *Imm = dyn_cast<ConstantFPSDNode>(N);
209 if (!Imm || !Imm->getValueAPF().isPosZero())
212 // Doesn't actually carry any information, but keeps TableGen quiet.
213 Dummy = CurDAG->getTargetConstant(0, MVT::i32);
217 bool AArch64DAGToDAGISel::SelectLogicalImm(SDValue N, SDValue &Imm) {
219 uint32_t RegWidth = N.getValueType().getSizeInBits();
221 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
222 if (!CN) return false;
224 if (!A64Imms::isLogicalImm(RegWidth, CN->getZExtValue(), Bits))
227 Imm = CurDAG->getTargetConstant(Bits, MVT::i32);
231 SDNode *AArch64DAGToDAGISel::TrySelectToMoveImm(SDNode *Node) {
234 EVT DestType = Node->getValueType(0);
235 unsigned DestWidth = DestType.getSizeInBits();
240 uint32_t LogicalBits;
242 uint64_t BitPat = cast<ConstantSDNode>(Node)->getZExtValue();
243 if (A64Imms::isMOVZImm(DestWidth, BitPat, UImm16, Shift)) {
245 MOVOpcode = DestWidth == 64 ? AArch64::MOVZxii : AArch64::MOVZwii;
246 } else if (A64Imms::isMOVNImm(DestWidth, BitPat, UImm16, Shift)) {
248 MOVOpcode = DestWidth == 64 ? AArch64::MOVNxii : AArch64::MOVNwii;
249 } else if (DestWidth == 64 && A64Imms::isMOVNImm(32, BitPat, UImm16, Shift)) {
250 // To get something like 0x0000_0000_ffff_1234 into a 64-bit register we can
251 // use a 32-bit instruction: "movn w0, 0xedbc".
253 MOVOpcode = AArch64::MOVNwii;
254 } else if (A64Imms::isLogicalImm(DestWidth, BitPat, LogicalBits)) {
255 MOVOpcode = DestWidth == 64 ? AArch64::ORRxxi : AArch64::ORRwwi;
256 uint16_t ZR = DestWidth == 64 ? AArch64::XZR : AArch64::WZR;
258 return CurDAG->getMachineNode(MOVOpcode, dl, DestType,
259 CurDAG->getRegister(ZR, DestType),
260 CurDAG->getTargetConstant(LogicalBits, MVT::i32));
262 // Can't handle it in one instruction. There's scope for permitting two (or
263 // more) instructions, but that'll need more thought.
267 ResNode = CurDAG->getMachineNode(MOVOpcode, dl, MOVType,
268 CurDAG->getTargetConstant(UImm16, MVT::i32),
269 CurDAG->getTargetConstant(Shift, MVT::i32));
271 if (MOVType != DestType) {
272 ResNode = CurDAG->getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
273 MVT::i64, MVT::i32, MVT::Other,
274 CurDAG->getTargetConstant(0, MVT::i64),
276 CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32));
283 AArch64DAGToDAGISel::getConstantPoolItemAddress(SDLoc DL,
284 const Constant *CV) {
285 EVT PtrVT = getTargetLowering()->getPointerTy();
287 switch (getTargetLowering()->getTargetMachine().getCodeModel()) {
288 case CodeModel::Small: {
290 getTargetLowering()->getDataLayout()->getABITypeAlignment(CV->getType());
291 return CurDAG->getNode(
292 AArch64ISD::WrapperSmall, DL, PtrVT,
293 CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_NO_FLAG),
294 CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_LO12),
295 CurDAG->getConstant(Alignment, MVT::i32));
297 case CodeModel::Large: {
299 LitAddr = CurDAG->getMachineNode(
300 AArch64::MOVZxii, DL, PtrVT,
301 CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
302 CurDAG->getTargetConstant(3, MVT::i32));
303 LitAddr = CurDAG->getMachineNode(
304 AArch64::MOVKxii, DL, PtrVT, SDValue(LitAddr, 0),
305 CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
306 CurDAG->getTargetConstant(2, MVT::i32));
307 LitAddr = CurDAG->getMachineNode(
308 AArch64::MOVKxii, DL, PtrVT, SDValue(LitAddr, 0),
309 CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
310 CurDAG->getTargetConstant(1, MVT::i32));
311 LitAddr = CurDAG->getMachineNode(
312 AArch64::MOVKxii, DL, PtrVT, SDValue(LitAddr, 0),
313 CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC),
314 CurDAG->getTargetConstant(0, MVT::i32));
315 return SDValue(LitAddr, 0);
318 llvm_unreachable("Only small and large code models supported now");
322 SDNode *AArch64DAGToDAGISel::SelectToLitPool(SDNode *Node) {
324 uint64_t UnsignedVal = cast<ConstantSDNode>(Node)->getZExtValue();
325 int64_t SignedVal = cast<ConstantSDNode>(Node)->getSExtValue();
326 EVT DestType = Node->getValueType(0);
328 // Since we may end up loading a 64-bit constant from a 32-bit entry the
329 // constant in the pool may have a different type to the eventual node.
330 ISD::LoadExtType Extension;
333 assert((DestType == MVT::i64 || DestType == MVT::i32)
334 && "Only expect integer constants at the moment");
336 if (DestType == MVT::i32) {
337 Extension = ISD::NON_EXTLOAD;
339 } else if (UnsignedVal <= UINT32_MAX) {
340 Extension = ISD::ZEXTLOAD;
342 } else if (SignedVal >= INT32_MIN && SignedVal <= INT32_MAX) {
343 Extension = ISD::SEXTLOAD;
346 Extension = ISD::NON_EXTLOAD;
350 Constant *CV = ConstantInt::get(Type::getIntNTy(*CurDAG->getContext(),
351 MemType.getSizeInBits()),
353 SDValue PoolAddr = getConstantPoolItemAddress(DL, CV);
355 getTargetLowering()->getDataLayout()->getABITypeAlignment(CV->getType());
357 return CurDAG->getExtLoad(Extension, DL, DestType, CurDAG->getEntryNode(),
359 MachinePointerInfo::getConstantPool(), MemType,
360 /* isVolatile = */ false,
361 /* isNonTemporal = */ false,
362 Alignment).getNode();
365 SDNode *AArch64DAGToDAGISel::LowerToFPLitPool(SDNode *Node) {
367 const ConstantFP *FV = cast<ConstantFPSDNode>(Node)->getConstantFPValue();
368 EVT DestType = Node->getValueType(0);
371 getTargetLowering()->getDataLayout()->getABITypeAlignment(FV->getType());
372 SDValue PoolAddr = getConstantPoolItemAddress(DL, FV);
374 return CurDAG->getLoad(DestType, DL, CurDAG->getEntryNode(), PoolAddr,
375 MachinePointerInfo::getConstantPool(),
376 /* isVolatile = */ false,
377 /* isNonTemporal = */ false,
378 /* isInvariant = */ true,
379 Alignment).getNode();
383 AArch64DAGToDAGISel::SelectTSTBOperand(SDValue N, SDValue &FixedPos,
385 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
386 if (!CN) return false;
388 uint64_t Val = CN->getZExtValue();
390 if (!isPowerOf2_64(Val)) return false;
392 unsigned TestedBit = Log2_64(Val);
393 // Checks above should have guaranteed that we haven't lost information in
394 // finding TestedBit, but it must still be in range.
395 if (TestedBit >= RegWidth) return false;
397 FixedPos = CurDAG->getTargetConstant(TestedBit, MVT::i64);
401 SDNode *AArch64DAGToDAGISel::SelectAtomic(SDNode *Node, unsigned Op8,
402 unsigned Op16,unsigned Op32,
404 // Mostly direct translation to the given operations, except that we preserve
405 // the AtomicOrdering for use later on.
406 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
407 EVT VT = AN->getMemoryVT();
412 else if (VT == MVT::i16)
414 else if (VT == MVT::i32)
416 else if (VT == MVT::i64)
419 llvm_unreachable("Unexpected atomic operation");
421 SmallVector<SDValue, 4> Ops;
422 for (unsigned i = 1; i < AN->getNumOperands(); ++i)
423 Ops.push_back(AN->getOperand(i));
425 Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
426 Ops.push_back(AN->getOperand(0)); // Chain moves to the end
428 return CurDAG->SelectNodeTo(Node, Op, AN->getValueType(0), MVT::Other, Ops);
431 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
432 static unsigned RegClassIDs[] = { AArch64::DPairRegClassID,
433 AArch64::DTripleRegClassID,
434 AArch64::DQuadRegClassID };
435 static unsigned SubRegs[] = { AArch64::dsub_0, AArch64::dsub_1,
436 AArch64::dsub_2, AArch64::dsub_3 };
438 return createTuple(Regs, RegClassIDs, SubRegs);
441 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
442 static unsigned RegClassIDs[] = { AArch64::QPairRegClassID,
443 AArch64::QTripleRegClassID,
444 AArch64::QQuadRegClassID };
445 static unsigned SubRegs[] = { AArch64::qsub_0, AArch64::qsub_1,
446 AArch64::qsub_2, AArch64::qsub_3 };
448 return createTuple(Regs, RegClassIDs, SubRegs);
451 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
452 unsigned RegClassIDs[],
453 unsigned SubRegs[]) {
454 // There's no special register-class for a vector-list of 1 element: it's just
456 if (Regs.size() == 1)
459 assert(Regs.size() >= 2 && Regs.size() <= 4);
461 SDLoc DL(Regs[0].getNode());
463 SmallVector<SDValue, 4> Ops;
465 // First operand of REG_SEQUENCE is the desired RegClass.
467 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));
469 // Then we get pairs of source & subregister-position for the components.
470 for (unsigned i = 0; i < Regs.size(); ++i) {
471 Ops.push_back(Regs[i]);
472 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
476 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
477 return SDValue(N, 0);
481 // Get the register stride update opcode of a VLD/VST instruction that
482 // is otherwise equivalent to the given fixed stride updating instruction.
483 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
486 case AArch64::LD1WB_8B_fixed: return AArch64::LD1WB_8B_register;
487 case AArch64::LD1WB_4H_fixed: return AArch64::LD1WB_4H_register;
488 case AArch64::LD1WB_2S_fixed: return AArch64::LD1WB_2S_register;
489 case AArch64::LD1WB_1D_fixed: return AArch64::LD1WB_1D_register;
490 case AArch64::LD1WB_16B_fixed: return AArch64::LD1WB_16B_register;
491 case AArch64::LD1WB_8H_fixed: return AArch64::LD1WB_8H_register;
492 case AArch64::LD1WB_4S_fixed: return AArch64::LD1WB_4S_register;
493 case AArch64::LD1WB_2D_fixed: return AArch64::LD1WB_2D_register;
495 case AArch64::LD2WB_8B_fixed: return AArch64::LD2WB_8B_register;
496 case AArch64::LD2WB_4H_fixed: return AArch64::LD2WB_4H_register;
497 case AArch64::LD2WB_2S_fixed: return AArch64::LD2WB_2S_register;
498 case AArch64::LD2WB_16B_fixed: return AArch64::LD2WB_16B_register;
499 case AArch64::LD2WB_8H_fixed: return AArch64::LD2WB_8H_register;
500 case AArch64::LD2WB_4S_fixed: return AArch64::LD2WB_4S_register;
501 case AArch64::LD2WB_2D_fixed: return AArch64::LD2WB_2D_register;
503 case AArch64::LD3WB_8B_fixed: return AArch64::LD3WB_8B_register;
504 case AArch64::LD3WB_4H_fixed: return AArch64::LD3WB_4H_register;
505 case AArch64::LD3WB_2S_fixed: return AArch64::LD3WB_2S_register;
506 case AArch64::LD3WB_16B_fixed: return AArch64::LD3WB_16B_register;
507 case AArch64::LD3WB_8H_fixed: return AArch64::LD3WB_8H_register;
508 case AArch64::LD3WB_4S_fixed: return AArch64::LD3WB_4S_register;
509 case AArch64::LD3WB_2D_fixed: return AArch64::LD3WB_2D_register;
511 case AArch64::LD4WB_8B_fixed: return AArch64::LD4WB_8B_register;
512 case AArch64::LD4WB_4H_fixed: return AArch64::LD4WB_4H_register;
513 case AArch64::LD4WB_2S_fixed: return AArch64::LD4WB_2S_register;
514 case AArch64::LD4WB_16B_fixed: return AArch64::LD4WB_16B_register;
515 case AArch64::LD4WB_8H_fixed: return AArch64::LD4WB_8H_register;
516 case AArch64::LD4WB_4S_fixed: return AArch64::LD4WB_4S_register;
517 case AArch64::LD4WB_2D_fixed: return AArch64::LD4WB_2D_register;
519 case AArch64::LD1x2WB_8B_fixed: return AArch64::LD1x2WB_8B_register;
520 case AArch64::LD1x2WB_4H_fixed: return AArch64::LD1x2WB_4H_register;
521 case AArch64::LD1x2WB_2S_fixed: return AArch64::LD1x2WB_2S_register;
522 case AArch64::LD1x2WB_1D_fixed: return AArch64::LD1x2WB_1D_register;
523 case AArch64::LD1x2WB_16B_fixed: return AArch64::LD1x2WB_16B_register;
524 case AArch64::LD1x2WB_8H_fixed: return AArch64::LD1x2WB_8H_register;
525 case AArch64::LD1x2WB_4S_fixed: return AArch64::LD1x2WB_4S_register;
526 case AArch64::LD1x2WB_2D_fixed: return AArch64::LD1x2WB_2D_register;
528 case AArch64::LD1x3WB_8B_fixed: return AArch64::LD1x3WB_8B_register;
529 case AArch64::LD1x3WB_4H_fixed: return AArch64::LD1x3WB_4H_register;
530 case AArch64::LD1x3WB_2S_fixed: return AArch64::LD1x3WB_2S_register;
531 case AArch64::LD1x3WB_1D_fixed: return AArch64::LD1x3WB_1D_register;
532 case AArch64::LD1x3WB_16B_fixed: return AArch64::LD1x3WB_16B_register;
533 case AArch64::LD1x3WB_8H_fixed: return AArch64::LD1x3WB_8H_register;
534 case AArch64::LD1x3WB_4S_fixed: return AArch64::LD1x3WB_4S_register;
535 case AArch64::LD1x3WB_2D_fixed: return AArch64::LD1x3WB_2D_register;
537 case AArch64::LD1x4WB_8B_fixed: return AArch64::LD1x4WB_8B_register;
538 case AArch64::LD1x4WB_4H_fixed: return AArch64::LD1x4WB_4H_register;
539 case AArch64::LD1x4WB_2S_fixed: return AArch64::LD1x4WB_2S_register;
540 case AArch64::LD1x4WB_1D_fixed: return AArch64::LD1x4WB_1D_register;
541 case AArch64::LD1x4WB_16B_fixed: return AArch64::LD1x4WB_16B_register;
542 case AArch64::LD1x4WB_8H_fixed: return AArch64::LD1x4WB_8H_register;
543 case AArch64::LD1x4WB_4S_fixed: return AArch64::LD1x4WB_4S_register;
544 case AArch64::LD1x4WB_2D_fixed: return AArch64::LD1x4WB_2D_register;
546 case AArch64::ST1WB_8B_fixed: return AArch64::ST1WB_8B_register;
547 case AArch64::ST1WB_4H_fixed: return AArch64::ST1WB_4H_register;
548 case AArch64::ST1WB_2S_fixed: return AArch64::ST1WB_2S_register;
549 case AArch64::ST1WB_1D_fixed: return AArch64::ST1WB_1D_register;
550 case AArch64::ST1WB_16B_fixed: return AArch64::ST1WB_16B_register;
551 case AArch64::ST1WB_8H_fixed: return AArch64::ST1WB_8H_register;
552 case AArch64::ST1WB_4S_fixed: return AArch64::ST1WB_4S_register;
553 case AArch64::ST1WB_2D_fixed: return AArch64::ST1WB_2D_register;
555 case AArch64::ST2WB_8B_fixed: return AArch64::ST2WB_8B_register;
556 case AArch64::ST2WB_4H_fixed: return AArch64::ST2WB_4H_register;
557 case AArch64::ST2WB_2S_fixed: return AArch64::ST2WB_2S_register;
558 case AArch64::ST2WB_16B_fixed: return AArch64::ST2WB_16B_register;
559 case AArch64::ST2WB_8H_fixed: return AArch64::ST2WB_8H_register;
560 case AArch64::ST2WB_4S_fixed: return AArch64::ST2WB_4S_register;
561 case AArch64::ST2WB_2D_fixed: return AArch64::ST2WB_2D_register;
563 case AArch64::ST3WB_8B_fixed: return AArch64::ST3WB_8B_register;
564 case AArch64::ST3WB_4H_fixed: return AArch64::ST3WB_4H_register;
565 case AArch64::ST3WB_2S_fixed: return AArch64::ST3WB_2S_register;
566 case AArch64::ST3WB_16B_fixed: return AArch64::ST3WB_16B_register;
567 case AArch64::ST3WB_8H_fixed: return AArch64::ST3WB_8H_register;
568 case AArch64::ST3WB_4S_fixed: return AArch64::ST3WB_4S_register;
569 case AArch64::ST3WB_2D_fixed: return AArch64::ST3WB_2D_register;
571 case AArch64::ST4WB_8B_fixed: return AArch64::ST4WB_8B_register;
572 case AArch64::ST4WB_4H_fixed: return AArch64::ST4WB_4H_register;
573 case AArch64::ST4WB_2S_fixed: return AArch64::ST4WB_2S_register;
574 case AArch64::ST4WB_16B_fixed: return AArch64::ST4WB_16B_register;
575 case AArch64::ST4WB_8H_fixed: return AArch64::ST4WB_8H_register;
576 case AArch64::ST4WB_4S_fixed: return AArch64::ST4WB_4S_register;
577 case AArch64::ST4WB_2D_fixed: return AArch64::ST4WB_2D_register;
579 case AArch64::ST1x2WB_8B_fixed: return AArch64::ST1x2WB_8B_register;
580 case AArch64::ST1x2WB_4H_fixed: return AArch64::ST1x2WB_4H_register;
581 case AArch64::ST1x2WB_2S_fixed: return AArch64::ST1x2WB_2S_register;
582 case AArch64::ST1x2WB_1D_fixed: return AArch64::ST1x2WB_1D_register;
583 case AArch64::ST1x2WB_16B_fixed: return AArch64::ST1x2WB_16B_register;
584 case AArch64::ST1x2WB_8H_fixed: return AArch64::ST1x2WB_8H_register;
585 case AArch64::ST1x2WB_4S_fixed: return AArch64::ST1x2WB_4S_register;
586 case AArch64::ST1x2WB_2D_fixed: return AArch64::ST1x2WB_2D_register;
588 case AArch64::ST1x3WB_8B_fixed: return AArch64::ST1x3WB_8B_register;
589 case AArch64::ST1x3WB_4H_fixed: return AArch64::ST1x3WB_4H_register;
590 case AArch64::ST1x3WB_2S_fixed: return AArch64::ST1x3WB_2S_register;
591 case AArch64::ST1x3WB_1D_fixed: return AArch64::ST1x3WB_1D_register;
592 case AArch64::ST1x3WB_16B_fixed: return AArch64::ST1x3WB_16B_register;
593 case AArch64::ST1x3WB_8H_fixed: return AArch64::ST1x3WB_8H_register;
594 case AArch64::ST1x3WB_4S_fixed: return AArch64::ST1x3WB_4S_register;
595 case AArch64::ST1x3WB_2D_fixed: return AArch64::ST1x3WB_2D_register;
597 case AArch64::ST1x4WB_8B_fixed: return AArch64::ST1x4WB_8B_register;
598 case AArch64::ST1x4WB_4H_fixed: return AArch64::ST1x4WB_4H_register;
599 case AArch64::ST1x4WB_2S_fixed: return AArch64::ST1x4WB_2S_register;
600 case AArch64::ST1x4WB_1D_fixed: return AArch64::ST1x4WB_1D_register;
601 case AArch64::ST1x4WB_16B_fixed: return AArch64::ST1x4WB_16B_register;
602 case AArch64::ST1x4WB_8H_fixed: return AArch64::ST1x4WB_8H_register;
603 case AArch64::ST1x4WB_4S_fixed: return AArch64::ST1x4WB_4S_register;
604 case AArch64::ST1x4WB_2D_fixed: return AArch64::ST1x4WB_2D_register;
606 // Post-index of duplicate loads
607 case AArch64::LD2R_WB_8B_fixed: return AArch64::LD2R_WB_8B_register;
608 case AArch64::LD2R_WB_4H_fixed: return AArch64::LD2R_WB_4H_register;
609 case AArch64::LD2R_WB_2S_fixed: return AArch64::LD2R_WB_2S_register;
610 case AArch64::LD2R_WB_1D_fixed: return AArch64::LD2R_WB_1D_register;
611 case AArch64::LD2R_WB_16B_fixed: return AArch64::LD2R_WB_16B_register;
612 case AArch64::LD2R_WB_8H_fixed: return AArch64::LD2R_WB_8H_register;
613 case AArch64::LD2R_WB_4S_fixed: return AArch64::LD2R_WB_4S_register;
614 case AArch64::LD2R_WB_2D_fixed: return AArch64::LD2R_WB_2D_register;
616 case AArch64::LD3R_WB_8B_fixed: return AArch64::LD3R_WB_8B_register;
617 case AArch64::LD3R_WB_4H_fixed: return AArch64::LD3R_WB_4H_register;
618 case AArch64::LD3R_WB_2S_fixed: return AArch64::LD3R_WB_2S_register;
619 case AArch64::LD3R_WB_1D_fixed: return AArch64::LD3R_WB_1D_register;
620 case AArch64::LD3R_WB_16B_fixed: return AArch64::LD3R_WB_16B_register;
621 case AArch64::LD3R_WB_8H_fixed: return AArch64::LD3R_WB_8H_register;
622 case AArch64::LD3R_WB_4S_fixed: return AArch64::LD3R_WB_4S_register;
623 case AArch64::LD3R_WB_2D_fixed: return AArch64::LD3R_WB_2D_register;
625 case AArch64::LD4R_WB_8B_fixed: return AArch64::LD4R_WB_8B_register;
626 case AArch64::LD4R_WB_4H_fixed: return AArch64::LD4R_WB_4H_register;
627 case AArch64::LD4R_WB_2S_fixed: return AArch64::LD4R_WB_2S_register;
628 case AArch64::LD4R_WB_1D_fixed: return AArch64::LD4R_WB_1D_register;
629 case AArch64::LD4R_WB_16B_fixed: return AArch64::LD4R_WB_16B_register;
630 case AArch64::LD4R_WB_8H_fixed: return AArch64::LD4R_WB_8H_register;
631 case AArch64::LD4R_WB_4S_fixed: return AArch64::LD4R_WB_4S_register;
632 case AArch64::LD4R_WB_2D_fixed: return AArch64::LD4R_WB_2D_register;
634 // Post-index of lane loads
635 case AArch64::LD2LN_WB_B_fixed: return AArch64::LD2LN_WB_B_register;
636 case AArch64::LD2LN_WB_H_fixed: return AArch64::LD2LN_WB_H_register;
637 case AArch64::LD2LN_WB_S_fixed: return AArch64::LD2LN_WB_S_register;
638 case AArch64::LD2LN_WB_D_fixed: return AArch64::LD2LN_WB_D_register;
640 case AArch64::LD3LN_WB_B_fixed: return AArch64::LD3LN_WB_B_register;
641 case AArch64::LD3LN_WB_H_fixed: return AArch64::LD3LN_WB_H_register;
642 case AArch64::LD3LN_WB_S_fixed: return AArch64::LD3LN_WB_S_register;
643 case AArch64::LD3LN_WB_D_fixed: return AArch64::LD3LN_WB_D_register;
645 case AArch64::LD4LN_WB_B_fixed: return AArch64::LD4LN_WB_B_register;
646 case AArch64::LD4LN_WB_H_fixed: return AArch64::LD4LN_WB_H_register;
647 case AArch64::LD4LN_WB_S_fixed: return AArch64::LD4LN_WB_S_register;
648 case AArch64::LD4LN_WB_D_fixed: return AArch64::LD4LN_WB_D_register;
650 // Post-index of lane stores
651 case AArch64::ST2LN_WB_B_fixed: return AArch64::ST2LN_WB_B_register;
652 case AArch64::ST2LN_WB_H_fixed: return AArch64::ST2LN_WB_H_register;
653 case AArch64::ST2LN_WB_S_fixed: return AArch64::ST2LN_WB_S_register;
654 case AArch64::ST2LN_WB_D_fixed: return AArch64::ST2LN_WB_D_register;
656 case AArch64::ST3LN_WB_B_fixed: return AArch64::ST3LN_WB_B_register;
657 case AArch64::ST3LN_WB_H_fixed: return AArch64::ST3LN_WB_H_register;
658 case AArch64::ST3LN_WB_S_fixed: return AArch64::ST3LN_WB_S_register;
659 case AArch64::ST3LN_WB_D_fixed: return AArch64::ST3LN_WB_D_register;
661 case AArch64::ST4LN_WB_B_fixed: return AArch64::ST4LN_WB_B_register;
662 case AArch64::ST4LN_WB_H_fixed: return AArch64::ST4LN_WB_H_register;
663 case AArch64::ST4LN_WB_S_fixed: return AArch64::ST4LN_WB_S_register;
664 case AArch64::ST4LN_WB_D_fixed: return AArch64::ST4LN_WB_D_register;
666 return Opc; // If not one we handle, return it unchanged.
669 SDNode *AArch64DAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating,
671 const uint16_t *Opcodes) {
672 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
674 EVT VT = N->getValueType(0);
675 unsigned OpcodeIndex;
676 bool is64BitVector = VT.is64BitVector();
677 switch (VT.getScalarType().getSizeInBits()) {
678 case 8: OpcodeIndex = is64BitVector ? 0 : 4; break;
679 case 16: OpcodeIndex = is64BitVector ? 1 : 5; break;
680 case 32: OpcodeIndex = is64BitVector ? 2 : 6; break;
681 case 64: OpcodeIndex = is64BitVector ? 3 : 7; break;
682 default: llvm_unreachable("unhandled vector load type");
684 unsigned Opc = Opcodes[OpcodeIndex];
686 SmallVector<SDValue, 2> Ops;
687 unsigned AddrOpIdx = isUpdating ? 1 : 2;
688 Ops.push_back(N->getOperand(AddrOpIdx)); // Push back the Memory Address
691 SDValue Inc = N->getOperand(AddrOpIdx + 1);
692 if (!isa<ConstantSDNode>(Inc.getNode())) // Increment in Register
693 Opc = getVLDSTRegisterUpdateOpcode(Opc);
697 Ops.push_back(N->getOperand(0)); // Push back the Chain
699 SmallVector<EVT, 3> ResTys;
700 // Push back the type of return super register
702 ResTys.push_back(VT);
703 else if (NumVecs == 3)
704 ResTys.push_back(MVT::Untyped);
706 EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,
707 is64BitVector ? NumVecs : NumVecs * 2);
708 ResTys.push_back(ResTy);
712 ResTys.push_back(MVT::i64); // Type of the updated register
713 ResTys.push_back(MVT::Other); // Type of the Chain
715 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
717 // Transfer memoperands.
718 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
719 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
720 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
725 // If NumVecs > 1, the return result is a super register containing 2-4
726 // consecutive vector registers.
727 SDValue SuperReg = SDValue(VLd, 0);
729 unsigned Sub0 = is64BitVector ? AArch64::dsub_0 : AArch64::qsub_0;
730 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
731 ReplaceUses(SDValue(N, Vec),
732 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
733 // Update users of the Chain
734 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
736 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
741 SDNode *AArch64DAGToDAGISel::SelectVST(SDNode *N, bool isUpdating,
743 const uint16_t *Opcodes) {
744 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
747 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
748 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
750 unsigned AddrOpIdx = isUpdating ? 1 : 2;
751 unsigned Vec0Idx = 3;
752 EVT VT = N->getOperand(Vec0Idx).getValueType();
753 unsigned OpcodeIndex;
754 bool is64BitVector = VT.is64BitVector();
755 switch (VT.getScalarType().getSizeInBits()) {
756 case 8: OpcodeIndex = is64BitVector ? 0 : 4; break;
757 case 16: OpcodeIndex = is64BitVector ? 1 : 5; break;
758 case 32: OpcodeIndex = is64BitVector ? 2 : 6; break;
759 case 64: OpcodeIndex = is64BitVector ? 3 : 7; break;
760 default: llvm_unreachable("unhandled vector store type");
762 unsigned Opc = Opcodes[OpcodeIndex];
764 SmallVector<EVT, 2> ResTys;
766 ResTys.push_back(MVT::i64);
767 ResTys.push_back(MVT::Other); // Type for the Chain
769 SmallVector<SDValue, 6> Ops;
770 Ops.push_back(N->getOperand(AddrOpIdx)); // Push back the Memory Address
773 SDValue Inc = N->getOperand(AddrOpIdx + 1);
774 if (!isa<ConstantSDNode>(Inc.getNode())) // Increment in Register
775 Opc = getVLDSTRegisterUpdateOpcode(Opc);
779 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Idx,
780 N->op_begin() + Vec0Idx + NumVecs);
781 SDValue SrcReg = is64BitVector ? createDTuple(Regs) : createQTuple(Regs);
782 Ops.push_back(SrcReg);
784 // Push back the Chain
785 Ops.push_back(N->getOperand(0));
787 // Transfer memoperands.
788 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
789 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
795 AArch64DAGToDAGISel::getTargetSubregToReg(int SRIdx, SDLoc DL, EVT VT, EVT VTD,
797 SDNode *Reg = CurDAG->getMachineNode(TargetOpcode::SUBREG_TO_REG, DL,
799 CurDAG->getTargetConstant(0, MVT::i64),
801 CurDAG->getTargetConstant(AArch64::sub_64, MVT::i32));
802 return SDValue(Reg, 0);
805 SDNode *AArch64DAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
807 const uint16_t *Opcodes) {
808 assert(NumVecs >=2 && NumVecs <= 4 && "Load Dup NumVecs out-of-range");
811 EVT VT = N->getValueType(0);
812 unsigned OpcodeIndex;
813 bool is64BitVector = VT.is64BitVector();
814 switch (VT.getScalarType().getSizeInBits()) {
815 case 8: OpcodeIndex = is64BitVector ? 0 : 4; break;
816 case 16: OpcodeIndex = is64BitVector ? 1 : 5; break;
817 case 32: OpcodeIndex = is64BitVector ? 2 : 6; break;
818 case 64: OpcodeIndex = is64BitVector ? 3 : 7; break;
819 default: llvm_unreachable("unhandled vector duplicate lane load type");
821 unsigned Opc = Opcodes[OpcodeIndex];
824 SmallVector<SDValue, 6> Ops;
825 Ops.push_back(N->getOperand(1)); // Push back the Memory Address
827 SDValue Inc = N->getOperand(2);
828 if (!isa<ConstantSDNode>(Inc.getNode())) // Increment in Register
829 Opc = getVLDSTRegisterUpdateOpcode(Opc);
832 Ops.push_back(N->getOperand(0)); // Push back the Chain
834 SmallVector<EVT, 3> ResTys;
835 // Push back the type of return super register
837 ResTys.push_back(MVT::Untyped);
839 EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,
840 is64BitVector ? NumVecs : NumVecs * 2);
841 ResTys.push_back(ResTy);
844 ResTys.push_back(MVT::i64); // Type of the updated register
845 ResTys.push_back(MVT::Other); // Type of the Chain
846 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
848 // Transfer memoperands.
849 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
850 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
851 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
853 SuperReg = SDValue(VLdDup, 0);
854 unsigned Sub0 = is64BitVector ? AArch64::dsub_0 : AArch64::qsub_0;
855 // Update uses of each registers in super register
856 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
857 ReplaceUses(SDValue(N, Vec),
858 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
859 // Update uses of the Chain
860 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
862 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
866 // We only have 128-bit vector type of load/store lane instructions.
867 // If it is 64-bit vector, we also select it to the 128-bit instructions.
868 // Just use SUBREG_TO_REG to adapt the input to 128-bit vector and
869 // EXTRACT_SUBREG to get the 64-bit vector from the 128-bit vector output.
870 SDNode *AArch64DAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
871 bool isUpdating, unsigned NumVecs,
872 const uint16_t *Opcodes) {
873 assert(NumVecs >= 2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
875 unsigned AddrOpIdx = isUpdating ? 1 : 2;
876 unsigned Vec0Idx = 3;
878 SDValue Chain = N->getOperand(0);
880 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
881 EVT VT = N->getOperand(Vec0Idx).getValueType();
882 bool is64BitVector = VT.is64BitVector();
883 EVT VT64; // 64-bit Vector Type
887 VT = EVT::getVectorVT(*CurDAG->getContext(), VT.getVectorElementType(),
888 VT.getVectorNumElements() * 2);
891 unsigned OpcodeIndex;
892 switch (VT.getScalarType().getSizeInBits()) {
893 case 8: OpcodeIndex = 0; break;
894 case 16: OpcodeIndex = 1; break;
895 case 32: OpcodeIndex = 2; break;
896 case 64: OpcodeIndex = 3; break;
897 default: llvm_unreachable("unhandled vector lane load/store type");
899 unsigned Opc = Opcodes[OpcodeIndex];
901 SmallVector<EVT, 3> ResTys;
903 // Push back the type of return super register
905 ResTys.push_back(MVT::Untyped);
907 EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,
908 is64BitVector ? NumVecs : NumVecs * 2);
909 ResTys.push_back(ResTy);
913 ResTys.push_back(MVT::i64); // Type of the updated register
914 ResTys.push_back(MVT::Other); // Type of Chain
915 SmallVector<SDValue, 5> Ops;
916 Ops.push_back(N->getOperand(AddrOpIdx)); // Push back the Memory Address
918 SDValue Inc = N->getOperand(AddrOpIdx + 1);
919 if (!isa<ConstantSDNode>(Inc.getNode())) // Increment in Register
920 Opc = getVLDSTRegisterUpdateOpcode(Opc);
924 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Idx,
925 N->op_begin() + Vec0Idx + NumVecs);
927 for (unsigned i = 0; i < Regs.size(); i++)
928 Regs[i] = getTargetSubregToReg(AArch64::sub_64, dl, VT, VT64, Regs[i]);
929 SDValue SuperReg = createQTuple(Regs);
931 Ops.push_back(SuperReg); // Source Reg
932 SDValue LaneValue = CurDAG->getTargetConstant(Lane, MVT::i32);
933 Ops.push_back(LaneValue);
934 Ops.push_back(Chain); // Push back the Chain
936 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
937 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
938 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
939 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
943 // Extract the subregisters.
944 SuperReg = SDValue(VLdLn, 0);
945 unsigned Sub0 = AArch64::qsub_0;
946 // Update uses of each registers in super register
947 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
948 SDValue SUB0 = CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg);
950 SUB0 = CurDAG->getTargetExtractSubreg(AArch64::sub_64, dl, VT64, SUB0);
952 ReplaceUses(SDValue(N, Vec), SUB0);
954 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
956 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
960 unsigned AArch64DAGToDAGISel::getTBLOpc(bool IsExt, bool Is64Bit,
962 assert(NumOfVec >= 1 && NumOfVec <= 4 && "VST NumVecs out-of-range");
970 Opc = Is64Bit ? AArch64::TBX1_8b : AArch64::TBX1_16b;
972 Opc = Is64Bit ? AArch64::TBL1_8b : AArch64::TBL1_16b;
976 Opc = Is64Bit ? AArch64::TBX2_8b : AArch64::TBX2_16b;
978 Opc = Is64Bit ? AArch64::TBL2_8b : AArch64::TBL2_16b;
982 Opc = Is64Bit ? AArch64::TBX3_8b : AArch64::TBX3_16b;
984 Opc = Is64Bit ? AArch64::TBL3_8b : AArch64::TBL3_16b;
988 Opc = Is64Bit ? AArch64::TBX4_8b : AArch64::TBX4_16b;
990 Opc = Is64Bit ? AArch64::TBL4_8b : AArch64::TBL4_16b;
997 SDNode *AArch64DAGToDAGISel::SelectVTBL(SDNode *N, unsigned NumVecs,
999 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1002 // Check the element of look up table is 64-bit or not
1003 unsigned Vec0Idx = IsExt ? 2 : 1;
1004 assert(!N->getOperand(Vec0Idx + 0).getValueType().is64BitVector() &&
1005 "The element of lookup table for vtbl and vtbx must be 128-bit");
1007 // Check the return value type is 64-bit or not
1008 EVT ResVT = N->getValueType(0);
1009 bool is64BitRes = ResVT.is64BitVector();
1011 // Create new SDValue for vector list
1012 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Idx,
1013 N->op_begin() + Vec0Idx + NumVecs);
1014 SDValue TblReg = createQTuple(Regs);
1015 unsigned Opc = getTBLOpc(IsExt, is64BitRes, NumVecs);
1017 SmallVector<SDValue, 3> Ops;
1019 Ops.push_back(N->getOperand(1));
1020 Ops.push_back(TblReg);
1021 Ops.push_back(N->getOperand(Vec0Idx + NumVecs));
1022 return CurDAG->getMachineNode(Opc, dl, ResVT, Ops);
1025 SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
1026 // Dump information about the Node being selected
1027 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << "\n");
1029 if (Node->isMachineOpcode()) {
1030 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
1031 Node->setNodeId(-1);
1035 switch (Node->getOpcode()) {
1036 case ISD::ATOMIC_LOAD_ADD:
1037 return SelectAtomic(Node,
1038 AArch64::ATOMIC_LOAD_ADD_I8,
1039 AArch64::ATOMIC_LOAD_ADD_I16,
1040 AArch64::ATOMIC_LOAD_ADD_I32,
1041 AArch64::ATOMIC_LOAD_ADD_I64);
1042 case ISD::ATOMIC_LOAD_SUB:
1043 return SelectAtomic(Node,
1044 AArch64::ATOMIC_LOAD_SUB_I8,
1045 AArch64::ATOMIC_LOAD_SUB_I16,
1046 AArch64::ATOMIC_LOAD_SUB_I32,
1047 AArch64::ATOMIC_LOAD_SUB_I64);
1048 case ISD::ATOMIC_LOAD_AND:
1049 return SelectAtomic(Node,
1050 AArch64::ATOMIC_LOAD_AND_I8,
1051 AArch64::ATOMIC_LOAD_AND_I16,
1052 AArch64::ATOMIC_LOAD_AND_I32,
1053 AArch64::ATOMIC_LOAD_AND_I64);
1054 case ISD::ATOMIC_LOAD_OR:
1055 return SelectAtomic(Node,
1056 AArch64::ATOMIC_LOAD_OR_I8,
1057 AArch64::ATOMIC_LOAD_OR_I16,
1058 AArch64::ATOMIC_LOAD_OR_I32,
1059 AArch64::ATOMIC_LOAD_OR_I64);
1060 case ISD::ATOMIC_LOAD_XOR:
1061 return SelectAtomic(Node,
1062 AArch64::ATOMIC_LOAD_XOR_I8,
1063 AArch64::ATOMIC_LOAD_XOR_I16,
1064 AArch64::ATOMIC_LOAD_XOR_I32,
1065 AArch64::ATOMIC_LOAD_XOR_I64);
1066 case ISD::ATOMIC_LOAD_NAND:
1067 return SelectAtomic(Node,
1068 AArch64::ATOMIC_LOAD_NAND_I8,
1069 AArch64::ATOMIC_LOAD_NAND_I16,
1070 AArch64::ATOMIC_LOAD_NAND_I32,
1071 AArch64::ATOMIC_LOAD_NAND_I64);
1072 case ISD::ATOMIC_LOAD_MIN:
1073 return SelectAtomic(Node,
1074 AArch64::ATOMIC_LOAD_MIN_I8,
1075 AArch64::ATOMIC_LOAD_MIN_I16,
1076 AArch64::ATOMIC_LOAD_MIN_I32,
1077 AArch64::ATOMIC_LOAD_MIN_I64);
1078 case ISD::ATOMIC_LOAD_MAX:
1079 return SelectAtomic(Node,
1080 AArch64::ATOMIC_LOAD_MAX_I8,
1081 AArch64::ATOMIC_LOAD_MAX_I16,
1082 AArch64::ATOMIC_LOAD_MAX_I32,
1083 AArch64::ATOMIC_LOAD_MAX_I64);
1084 case ISD::ATOMIC_LOAD_UMIN:
1085 return SelectAtomic(Node,
1086 AArch64::ATOMIC_LOAD_UMIN_I8,
1087 AArch64::ATOMIC_LOAD_UMIN_I16,
1088 AArch64::ATOMIC_LOAD_UMIN_I32,
1089 AArch64::ATOMIC_LOAD_UMIN_I64);
1090 case ISD::ATOMIC_LOAD_UMAX:
1091 return SelectAtomic(Node,
1092 AArch64::ATOMIC_LOAD_UMAX_I8,
1093 AArch64::ATOMIC_LOAD_UMAX_I16,
1094 AArch64::ATOMIC_LOAD_UMAX_I32,
1095 AArch64::ATOMIC_LOAD_UMAX_I64);
1096 case ISD::ATOMIC_SWAP:
1097 return SelectAtomic(Node,
1098 AArch64::ATOMIC_SWAP_I8,
1099 AArch64::ATOMIC_SWAP_I16,
1100 AArch64::ATOMIC_SWAP_I32,
1101 AArch64::ATOMIC_SWAP_I64);
1102 case ISD::ATOMIC_CMP_SWAP:
1103 return SelectAtomic(Node,
1104 AArch64::ATOMIC_CMP_SWAP_I8,
1105 AArch64::ATOMIC_CMP_SWAP_I16,
1106 AArch64::ATOMIC_CMP_SWAP_I32,
1107 AArch64::ATOMIC_CMP_SWAP_I64);
1108 case ISD::FrameIndex: {
1109 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
1110 EVT PtrTy = getTargetLowering()->getPointerTy();
1111 SDValue TFI = CurDAG->getTargetFrameIndex(FI, PtrTy);
1112 return CurDAG->SelectNodeTo(Node, AArch64::ADDxxi_lsl0_s, PtrTy,
1113 TFI, CurDAG->getTargetConstant(0, PtrTy));
1115 case ISD::Constant: {
1116 SDNode *ResNode = nullptr;
1117 if (cast<ConstantSDNode>(Node)->getZExtValue() == 0) {
1118 // XZR and WZR are probably even better than an actual move: most of the
1119 // time they can be folded into another instruction with *no* cost.
1121 EVT Ty = Node->getValueType(0);
1122 assert((Ty == MVT::i32 || Ty == MVT::i64) && "unexpected type");
1123 uint16_t Register = Ty == MVT::i32 ? AArch64::WZR : AArch64::XZR;
1124 ResNode = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1126 Register, Ty).getNode();
1129 // Next best option is a move-immediate, see if we can do that.
1131 ResNode = TrySelectToMoveImm(Node);
1137 // If even that fails we fall back to a lit-pool entry at the moment. Future
1138 // tuning may change this to a sequence of MOVZ/MOVN/MOVK instructions.
1139 ResNode = SelectToLitPool(Node);
1140 assert(ResNode && "We need *some* way to materialise a constant");
1142 // We want to continue selection at this point since the litpool access
1143 // generated used generic nodes for simplicity.
1144 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1148 case ISD::ConstantFP: {
1149 if (A64Imms::isFPImm(cast<ConstantFPSDNode>(Node)->getValueAPF())) {
1150 // FMOV will take care of it from TableGen
1154 SDNode *ResNode = LowerToFPLitPool(Node);
1155 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1157 // We want to continue selection at this point since the litpool access
1158 // generated used generic nodes for simplicity.
1162 case AArch64ISD::NEON_LD1_UPD: {
1163 static const uint16_t Opcodes[] = {
1164 AArch64::LD1WB_8B_fixed, AArch64::LD1WB_4H_fixed,
1165 AArch64::LD1WB_2S_fixed, AArch64::LD1WB_1D_fixed,
1166 AArch64::LD1WB_16B_fixed, AArch64::LD1WB_8H_fixed,
1167 AArch64::LD1WB_4S_fixed, AArch64::LD1WB_2D_fixed
1169 return SelectVLD(Node, true, 1, Opcodes);
1171 case AArch64ISD::NEON_LD2_UPD: {
1172 static const uint16_t Opcodes[] = {
1173 AArch64::LD2WB_8B_fixed, AArch64::LD2WB_4H_fixed,
1174 AArch64::LD2WB_2S_fixed, AArch64::LD1x2WB_1D_fixed,
1175 AArch64::LD2WB_16B_fixed, AArch64::LD2WB_8H_fixed,
1176 AArch64::LD2WB_4S_fixed, AArch64::LD2WB_2D_fixed
1178 return SelectVLD(Node, true, 2, Opcodes);
1180 case AArch64ISD::NEON_LD3_UPD: {
1181 static const uint16_t Opcodes[] = {
1182 AArch64::LD3WB_8B_fixed, AArch64::LD3WB_4H_fixed,
1183 AArch64::LD3WB_2S_fixed, AArch64::LD1x3WB_1D_fixed,
1184 AArch64::LD3WB_16B_fixed, AArch64::LD3WB_8H_fixed,
1185 AArch64::LD3WB_4S_fixed, AArch64::LD3WB_2D_fixed
1187 return SelectVLD(Node, true, 3, Opcodes);
1189 case AArch64ISD::NEON_LD4_UPD: {
1190 static const uint16_t Opcodes[] = {
1191 AArch64::LD4WB_8B_fixed, AArch64::LD4WB_4H_fixed,
1192 AArch64::LD4WB_2S_fixed, AArch64::LD1x4WB_1D_fixed,
1193 AArch64::LD4WB_16B_fixed, AArch64::LD4WB_8H_fixed,
1194 AArch64::LD4WB_4S_fixed, AArch64::LD4WB_2D_fixed
1196 return SelectVLD(Node, true, 4, Opcodes);
1198 case AArch64ISD::NEON_LD1x2_UPD: {
1199 static const uint16_t Opcodes[] = {
1200 AArch64::LD1x2WB_8B_fixed, AArch64::LD1x2WB_4H_fixed,
1201 AArch64::LD1x2WB_2S_fixed, AArch64::LD1x2WB_1D_fixed,
1202 AArch64::LD1x2WB_16B_fixed, AArch64::LD1x2WB_8H_fixed,
1203 AArch64::LD1x2WB_4S_fixed, AArch64::LD1x2WB_2D_fixed
1205 return SelectVLD(Node, true, 2, Opcodes);
1207 case AArch64ISD::NEON_LD1x3_UPD: {
1208 static const uint16_t Opcodes[] = {
1209 AArch64::LD1x3WB_8B_fixed, AArch64::LD1x3WB_4H_fixed,
1210 AArch64::LD1x3WB_2S_fixed, AArch64::LD1x3WB_1D_fixed,
1211 AArch64::LD1x3WB_16B_fixed, AArch64::LD1x3WB_8H_fixed,
1212 AArch64::LD1x3WB_4S_fixed, AArch64::LD1x3WB_2D_fixed
1214 return SelectVLD(Node, true, 3, Opcodes);
1216 case AArch64ISD::NEON_LD1x4_UPD: {
1217 static const uint16_t Opcodes[] = {
1218 AArch64::LD1x4WB_8B_fixed, AArch64::LD1x4WB_4H_fixed,
1219 AArch64::LD1x4WB_2S_fixed, AArch64::LD1x4WB_1D_fixed,
1220 AArch64::LD1x4WB_16B_fixed, AArch64::LD1x4WB_8H_fixed,
1221 AArch64::LD1x4WB_4S_fixed, AArch64::LD1x4WB_2D_fixed
1223 return SelectVLD(Node, true, 4, Opcodes);
1225 case AArch64ISD::NEON_ST1_UPD: {
1226 static const uint16_t Opcodes[] = {
1227 AArch64::ST1WB_8B_fixed, AArch64::ST1WB_4H_fixed,
1228 AArch64::ST1WB_2S_fixed, AArch64::ST1WB_1D_fixed,
1229 AArch64::ST1WB_16B_fixed, AArch64::ST1WB_8H_fixed,
1230 AArch64::ST1WB_4S_fixed, AArch64::ST1WB_2D_fixed
1232 return SelectVST(Node, true, 1, Opcodes);
1234 case AArch64ISD::NEON_ST2_UPD: {
1235 static const uint16_t Opcodes[] = {
1236 AArch64::ST2WB_8B_fixed, AArch64::ST2WB_4H_fixed,
1237 AArch64::ST2WB_2S_fixed, AArch64::ST1x2WB_1D_fixed,
1238 AArch64::ST2WB_16B_fixed, AArch64::ST2WB_8H_fixed,
1239 AArch64::ST2WB_4S_fixed, AArch64::ST2WB_2D_fixed
1241 return SelectVST(Node, true, 2, Opcodes);
1243 case AArch64ISD::NEON_ST3_UPD: {
1244 static const uint16_t Opcodes[] = {
1245 AArch64::ST3WB_8B_fixed, AArch64::ST3WB_4H_fixed,
1246 AArch64::ST3WB_2S_fixed, AArch64::ST1x3WB_1D_fixed,
1247 AArch64::ST3WB_16B_fixed, AArch64::ST3WB_8H_fixed,
1248 AArch64::ST3WB_4S_fixed, AArch64::ST3WB_2D_fixed
1250 return SelectVST(Node, true, 3, Opcodes);
1252 case AArch64ISD::NEON_ST4_UPD: {
1253 static const uint16_t Opcodes[] = {
1254 AArch64::ST4WB_8B_fixed, AArch64::ST4WB_4H_fixed,
1255 AArch64::ST4WB_2S_fixed, AArch64::ST1x4WB_1D_fixed,
1256 AArch64::ST4WB_16B_fixed, AArch64::ST4WB_8H_fixed,
1257 AArch64::ST4WB_4S_fixed, AArch64::ST4WB_2D_fixed
1259 return SelectVST(Node, true, 4, Opcodes);
1261 case AArch64ISD::NEON_LD2DUP: {
1262 static const uint16_t Opcodes[] = {
1263 AArch64::LD2R_8B, AArch64::LD2R_4H, AArch64::LD2R_2S,
1264 AArch64::LD2R_1D, AArch64::LD2R_16B, AArch64::LD2R_8H,
1265 AArch64::LD2R_4S, AArch64::LD2R_2D
1267 return SelectVLDDup(Node, false, 2, Opcodes);
1269 case AArch64ISD::NEON_LD3DUP: {
1270 static const uint16_t Opcodes[] = {
1271 AArch64::LD3R_8B, AArch64::LD3R_4H, AArch64::LD3R_2S,
1272 AArch64::LD3R_1D, AArch64::LD3R_16B, AArch64::LD3R_8H,
1273 AArch64::LD3R_4S, AArch64::LD3R_2D
1275 return SelectVLDDup(Node, false, 3, Opcodes);
1277 case AArch64ISD::NEON_LD4DUP: {
1278 static const uint16_t Opcodes[] = {
1279 AArch64::LD4R_8B, AArch64::LD4R_4H, AArch64::LD4R_2S,
1280 AArch64::LD4R_1D, AArch64::LD4R_16B, AArch64::LD4R_8H,
1281 AArch64::LD4R_4S, AArch64::LD4R_2D
1283 return SelectVLDDup(Node, false, 4, Opcodes);
1285 case AArch64ISD::NEON_LD2DUP_UPD: {
1286 static const uint16_t Opcodes[] = {
1287 AArch64::LD2R_WB_8B_fixed, AArch64::LD2R_WB_4H_fixed,
1288 AArch64::LD2R_WB_2S_fixed, AArch64::LD2R_WB_1D_fixed,
1289 AArch64::LD2R_WB_16B_fixed, AArch64::LD2R_WB_8H_fixed,
1290 AArch64::LD2R_WB_4S_fixed, AArch64::LD2R_WB_2D_fixed
1292 return SelectVLDDup(Node, true, 2, Opcodes);
1294 case AArch64ISD::NEON_LD3DUP_UPD: {
1295 static const uint16_t Opcodes[] = {
1296 AArch64::LD3R_WB_8B_fixed, AArch64::LD3R_WB_4H_fixed,
1297 AArch64::LD3R_WB_2S_fixed, AArch64::LD3R_WB_1D_fixed,
1298 AArch64::LD3R_WB_16B_fixed, AArch64::LD3R_WB_8H_fixed,
1299 AArch64::LD3R_WB_4S_fixed, AArch64::LD3R_WB_2D_fixed
1301 return SelectVLDDup(Node, true, 3, Opcodes);
1303 case AArch64ISD::NEON_LD4DUP_UPD: {
1304 static const uint16_t Opcodes[] = {
1305 AArch64::LD4R_WB_8B_fixed, AArch64::LD4R_WB_4H_fixed,
1306 AArch64::LD4R_WB_2S_fixed, AArch64::LD4R_WB_1D_fixed,
1307 AArch64::LD4R_WB_16B_fixed, AArch64::LD4R_WB_8H_fixed,
1308 AArch64::LD4R_WB_4S_fixed, AArch64::LD4R_WB_2D_fixed
1310 return SelectVLDDup(Node, true, 4, Opcodes);
1312 case AArch64ISD::NEON_LD2LN_UPD: {
1313 static const uint16_t Opcodes[] = {
1314 AArch64::LD2LN_WB_B_fixed, AArch64::LD2LN_WB_H_fixed,
1315 AArch64::LD2LN_WB_S_fixed, AArch64::LD2LN_WB_D_fixed
1317 return SelectVLDSTLane(Node, true, true, 2, Opcodes);
1319 case AArch64ISD::NEON_LD3LN_UPD: {
1320 static const uint16_t Opcodes[] = {
1321 AArch64::LD3LN_WB_B_fixed, AArch64::LD3LN_WB_H_fixed,
1322 AArch64::LD3LN_WB_S_fixed, AArch64::LD3LN_WB_D_fixed
1324 return SelectVLDSTLane(Node, true, true, 3, Opcodes);
1326 case AArch64ISD::NEON_LD4LN_UPD: {
1327 static const uint16_t Opcodes[] = {
1328 AArch64::LD4LN_WB_B_fixed, AArch64::LD4LN_WB_H_fixed,
1329 AArch64::LD4LN_WB_S_fixed, AArch64::LD4LN_WB_D_fixed
1331 return SelectVLDSTLane(Node, true, true, 4, Opcodes);
1333 case AArch64ISD::NEON_ST2LN_UPD: {
1334 static const uint16_t Opcodes[] = {
1335 AArch64::ST2LN_WB_B_fixed, AArch64::ST2LN_WB_H_fixed,
1336 AArch64::ST2LN_WB_S_fixed, AArch64::ST2LN_WB_D_fixed
1338 return SelectVLDSTLane(Node, false, true, 2, Opcodes);
1340 case AArch64ISD::NEON_ST3LN_UPD: {
1341 static const uint16_t Opcodes[] = {
1342 AArch64::ST3LN_WB_B_fixed, AArch64::ST3LN_WB_H_fixed,
1343 AArch64::ST3LN_WB_S_fixed, AArch64::ST3LN_WB_D_fixed
1345 return SelectVLDSTLane(Node, false, true, 3, Opcodes);
1347 case AArch64ISD::NEON_ST4LN_UPD: {
1348 static const uint16_t Opcodes[] = {
1349 AArch64::ST4LN_WB_B_fixed, AArch64::ST4LN_WB_H_fixed,
1350 AArch64::ST4LN_WB_S_fixed, AArch64::ST4LN_WB_D_fixed
1352 return SelectVLDSTLane(Node, false, true, 4, Opcodes);
1354 case AArch64ISD::NEON_ST1x2_UPD: {
1355 static const uint16_t Opcodes[] = {
1356 AArch64::ST1x2WB_8B_fixed, AArch64::ST1x2WB_4H_fixed,
1357 AArch64::ST1x2WB_2S_fixed, AArch64::ST1x2WB_1D_fixed,
1358 AArch64::ST1x2WB_16B_fixed, AArch64::ST1x2WB_8H_fixed,
1359 AArch64::ST1x2WB_4S_fixed, AArch64::ST1x2WB_2D_fixed
1361 return SelectVST(Node, true, 2, Opcodes);
1363 case AArch64ISD::NEON_ST1x3_UPD: {
1364 static const uint16_t Opcodes[] = {
1365 AArch64::ST1x3WB_8B_fixed, AArch64::ST1x3WB_4H_fixed,
1366 AArch64::ST1x3WB_2S_fixed, AArch64::ST1x3WB_1D_fixed,
1367 AArch64::ST1x3WB_16B_fixed, AArch64::ST1x3WB_8H_fixed,
1368 AArch64::ST1x3WB_4S_fixed, AArch64::ST1x3WB_2D_fixed
1370 return SelectVST(Node, true, 3, Opcodes);
1372 case AArch64ISD::NEON_ST1x4_UPD: {
1373 static const uint16_t Opcodes[] = {
1374 AArch64::ST1x4WB_8B_fixed, AArch64::ST1x4WB_4H_fixed,
1375 AArch64::ST1x4WB_2S_fixed, AArch64::ST1x4WB_1D_fixed,
1376 AArch64::ST1x4WB_16B_fixed, AArch64::ST1x4WB_8H_fixed,
1377 AArch64::ST1x4WB_4S_fixed, AArch64::ST1x4WB_2D_fixed
1379 return SelectVST(Node, true, 4, Opcodes);
1381 case ISD::INTRINSIC_WO_CHAIN: {
1382 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
1387 case Intrinsic::aarch64_neon_vtbx1:
1389 case Intrinsic::aarch64_neon_vtbl1:
1390 return SelectVTBL(Node, 1, IsExt);
1391 case Intrinsic::aarch64_neon_vtbx2:
1393 case Intrinsic::aarch64_neon_vtbl2:
1394 return SelectVTBL(Node, 2, IsExt);
1395 case Intrinsic::aarch64_neon_vtbx3:
1397 case Intrinsic::aarch64_neon_vtbl3:
1398 return SelectVTBL(Node, 3, IsExt);
1399 case Intrinsic::aarch64_neon_vtbx4:
1401 case Intrinsic::aarch64_neon_vtbl4:
1402 return SelectVTBL(Node, 4, IsExt);
1406 case ISD::INTRINSIC_VOID:
1407 case ISD::INTRINSIC_W_CHAIN: {
1408 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
1412 case Intrinsic::arm_neon_vld1: {
1413 static const uint16_t Opcodes[] = {
1414 AArch64::LD1_8B, AArch64::LD1_4H, AArch64::LD1_2S, AArch64::LD1_1D,
1415 AArch64::LD1_16B, AArch64::LD1_8H, AArch64::LD1_4S, AArch64::LD1_2D
1417 return SelectVLD(Node, false, 1, Opcodes);
1419 case Intrinsic::arm_neon_vld2: {
1420 static const uint16_t Opcodes[] = {
1421 AArch64::LD2_8B, AArch64::LD2_4H, AArch64::LD2_2S, AArch64::LD1x2_1D,
1422 AArch64::LD2_16B, AArch64::LD2_8H, AArch64::LD2_4S, AArch64::LD2_2D
1424 return SelectVLD(Node, false, 2, Opcodes);
1426 case Intrinsic::arm_neon_vld3: {
1427 static const uint16_t Opcodes[] = {
1428 AArch64::LD3_8B, AArch64::LD3_4H, AArch64::LD3_2S, AArch64::LD1x3_1D,
1429 AArch64::LD3_16B, AArch64::LD3_8H, AArch64::LD3_4S, AArch64::LD3_2D
1431 return SelectVLD(Node, false, 3, Opcodes);
1433 case Intrinsic::arm_neon_vld4: {
1434 static const uint16_t Opcodes[] = {
1435 AArch64::LD4_8B, AArch64::LD4_4H, AArch64::LD4_2S, AArch64::LD1x4_1D,
1436 AArch64::LD4_16B, AArch64::LD4_8H, AArch64::LD4_4S, AArch64::LD4_2D
1438 return SelectVLD(Node, false, 4, Opcodes);
1440 case Intrinsic::aarch64_neon_vld1x2: {
1441 static const uint16_t Opcodes[] = {
1442 AArch64::LD1x2_8B, AArch64::LD1x2_4H, AArch64::LD1x2_2S,
1443 AArch64::LD1x2_1D, AArch64::LD1x2_16B, AArch64::LD1x2_8H,
1444 AArch64::LD1x2_4S, AArch64::LD1x2_2D
1446 return SelectVLD(Node, false, 2, Opcodes);
1448 case Intrinsic::aarch64_neon_vld1x3: {
1449 static const uint16_t Opcodes[] = {
1450 AArch64::LD1x3_8B, AArch64::LD1x3_4H, AArch64::LD1x3_2S,
1451 AArch64::LD1x3_1D, AArch64::LD1x3_16B, AArch64::LD1x3_8H,
1452 AArch64::LD1x3_4S, AArch64::LD1x3_2D
1454 return SelectVLD(Node, false, 3, Opcodes);
1456 case Intrinsic::aarch64_neon_vld1x4: {
1457 static const uint16_t Opcodes[] = {
1458 AArch64::LD1x4_8B, AArch64::LD1x4_4H, AArch64::LD1x4_2S,
1459 AArch64::LD1x4_1D, AArch64::LD1x4_16B, AArch64::LD1x4_8H,
1460 AArch64::LD1x4_4S, AArch64::LD1x4_2D
1462 return SelectVLD(Node, false, 4, Opcodes);
1464 case Intrinsic::arm_neon_vst1: {
1465 static const uint16_t Opcodes[] = {
1466 AArch64::ST1_8B, AArch64::ST1_4H, AArch64::ST1_2S, AArch64::ST1_1D,
1467 AArch64::ST1_16B, AArch64::ST1_8H, AArch64::ST1_4S, AArch64::ST1_2D
1469 return SelectVST(Node, false, 1, Opcodes);
1471 case Intrinsic::arm_neon_vst2: {
1472 static const uint16_t Opcodes[] = {
1473 AArch64::ST2_8B, AArch64::ST2_4H, AArch64::ST2_2S, AArch64::ST1x2_1D,
1474 AArch64::ST2_16B, AArch64::ST2_8H, AArch64::ST2_4S, AArch64::ST2_2D
1476 return SelectVST(Node, false, 2, Opcodes);
1478 case Intrinsic::arm_neon_vst3: {
1479 static const uint16_t Opcodes[] = {
1480 AArch64::ST3_8B, AArch64::ST3_4H, AArch64::ST3_2S, AArch64::ST1x3_1D,
1481 AArch64::ST3_16B, AArch64::ST3_8H, AArch64::ST3_4S, AArch64::ST3_2D
1483 return SelectVST(Node, false, 3, Opcodes);
1485 case Intrinsic::arm_neon_vst4: {
1486 static const uint16_t Opcodes[] = {
1487 AArch64::ST4_8B, AArch64::ST4_4H, AArch64::ST4_2S, AArch64::ST1x4_1D,
1488 AArch64::ST4_16B, AArch64::ST4_8H, AArch64::ST4_4S, AArch64::ST4_2D
1490 return SelectVST(Node, false, 4, Opcodes);
1492 case Intrinsic::aarch64_neon_vst1x2: {
1493 static const uint16_t Opcodes[] = {
1494 AArch64::ST1x2_8B, AArch64::ST1x2_4H, AArch64::ST1x2_2S,
1495 AArch64::ST1x2_1D, AArch64::ST1x2_16B, AArch64::ST1x2_8H,
1496 AArch64::ST1x2_4S, AArch64::ST1x2_2D
1498 return SelectVST(Node, false, 2, Opcodes);
1500 case Intrinsic::aarch64_neon_vst1x3: {
1501 static const uint16_t Opcodes[] = {
1502 AArch64::ST1x3_8B, AArch64::ST1x3_4H, AArch64::ST1x3_2S,
1503 AArch64::ST1x3_1D, AArch64::ST1x3_16B, AArch64::ST1x3_8H,
1504 AArch64::ST1x3_4S, AArch64::ST1x3_2D
1506 return SelectVST(Node, false, 3, Opcodes);
1508 case Intrinsic::aarch64_neon_vst1x4: {
1509 static const uint16_t Opcodes[] = {
1510 AArch64::ST1x4_8B, AArch64::ST1x4_4H, AArch64::ST1x4_2S,
1511 AArch64::ST1x4_1D, AArch64::ST1x4_16B, AArch64::ST1x4_8H,
1512 AArch64::ST1x4_4S, AArch64::ST1x4_2D
1514 return SelectVST(Node, false, 4, Opcodes);
1516 case Intrinsic::arm_neon_vld2lane: {
1517 static const uint16_t Opcodes[] = {
1518 AArch64::LD2LN_B, AArch64::LD2LN_H, AArch64::LD2LN_S, AArch64::LD2LN_D
1520 return SelectVLDSTLane(Node, true, false, 2, Opcodes);
1522 case Intrinsic::arm_neon_vld3lane: {
1523 static const uint16_t Opcodes[] = {
1524 AArch64::LD3LN_B, AArch64::LD3LN_H, AArch64::LD3LN_S, AArch64::LD3LN_D
1526 return SelectVLDSTLane(Node, true, false, 3, Opcodes);
1528 case Intrinsic::arm_neon_vld4lane: {
1529 static const uint16_t Opcodes[] = {
1530 AArch64::LD4LN_B, AArch64::LD4LN_H, AArch64::LD4LN_S, AArch64::LD4LN_D
1532 return SelectVLDSTLane(Node, true, false, 4, Opcodes);
1534 case Intrinsic::arm_neon_vst2lane: {
1535 static const uint16_t Opcodes[] = {
1536 AArch64::ST2LN_B, AArch64::ST2LN_H, AArch64::ST2LN_S, AArch64::ST2LN_D
1538 return SelectVLDSTLane(Node, false, false, 2, Opcodes);
1540 case Intrinsic::arm_neon_vst3lane: {
1541 static const uint16_t Opcodes[] = {
1542 AArch64::ST3LN_B, AArch64::ST3LN_H, AArch64::ST3LN_S, AArch64::ST3LN_D
1544 return SelectVLDSTLane(Node, false, false, 3, Opcodes);
1546 case Intrinsic::arm_neon_vst4lane: {
1547 static const uint16_t Opcodes[] = {
1548 AArch64::ST4LN_B, AArch64::ST4LN_H, AArch64::ST4LN_S, AArch64::ST4LN_D
1550 return SelectVLDSTLane(Node, false, false, 4, Opcodes);
1552 } // End of switch IntNo
1554 } // End of case ISD::INTRINSIC_VOID and :ISD::INTRINSIC_W_CHAIN
1556 break; // Let generic code handle it
1559 SDNode *ResNode = SelectCode(Node);
1561 DEBUG(dbgs() << "=> ";
1562 if (ResNode == NULL || ResNode == Node)
1565 ResNode->dump(CurDAG);
1571 /// This pass converts a legalized DAG into a AArch64-specific DAG, ready for
1572 /// instruction scheduling.
1573 FunctionPass *llvm::createAArch64ISelDAG(AArch64TargetMachine &TM,
1574 CodeGenOpt::Level OptLevel) {
1575 return new AArch64DAGToDAGISel(TM, OptLevel);