1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
46 static cl::opt<AlignMode>
47 Align(cl::desc("Load/store alignment support"),
48 cl::Hidden, cl::init(NoStrictAlign),
50 clEnumValN(StrictAlign, "aarch64-strict-align",
51 "Disallow all unaligned memory accesses"),
52 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
53 "Allow unaligned memory accesses"),
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
64 cl::desc("Allow AArch64 SLI/SRI formation"),
67 //===----------------------------------------------------------------------===//
68 // AArch64 Lowering public interface.
69 //===----------------------------------------------------------------------===//
70 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
71 if (TT.isOSBinFormatMachO())
72 return new AArch64_MachoTargetObjectFile();
74 return new AArch64_ELFTargetObjectFile();
77 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
79 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82 // we have to make something up. Arbitrarily, choose ZeroOrOne.
83 setBooleanContents(ZeroOrOneBooleanContent);
84 // When comparing vectors the result sets the different elements in the
85 // vector to all-one or all-zero.
86 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
92 if (Subtarget->hasFPARMv8()) {
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
99 if (Subtarget->hasNEON()) {
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102 // Someone set us up the NEON.
103 addDRTypeForNEON(MVT::v2f32);
104 addDRTypeForNEON(MVT::v8i8);
105 addDRTypeForNEON(MVT::v4i16);
106 addDRTypeForNEON(MVT::v2i32);
107 addDRTypeForNEON(MVT::v1i64);
108 addDRTypeForNEON(MVT::v1f64);
110 addQRTypeForNEON(MVT::v4f32);
111 addQRTypeForNEON(MVT::v2f64);
112 addQRTypeForNEON(MVT::v16i8);
113 addQRTypeForNEON(MVT::v8i16);
114 addQRTypeForNEON(MVT::v4i32);
115 addQRTypeForNEON(MVT::v2i64);
118 // Compute derived properties from the register classes
119 computeRegisterProperties();
121 // Provide all sorts of operation actions
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
141 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
142 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::FREM, MVT::f32, Expand);
149 setOperationAction(ISD::FREM, MVT::f64, Expand);
150 setOperationAction(ISD::FREM, MVT::f80, Expand);
152 // Custom lowering hooks are needed for XOR
153 // to fold it into CSINC/CSINV.
154 setOperationAction(ISD::XOR, MVT::i32, Custom);
155 setOperationAction(ISD::XOR, MVT::i64, Custom);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
158 // there's a valid register class, so we need custom operations in most cases.
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
198 // Variable arguments.
199 setOperationAction(ISD::VASTART, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Custom);
201 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
202 setOperationAction(ISD::VAEND, MVT::Other, Expand);
204 // Variable-sized objects.
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
209 // Exception handling.
210 // FIXME: These are guesses. Has this been defined yet?
211 setExceptionPointerRegister(AArch64::X0);
212 setExceptionSelectorRegister(AArch64::X1);
214 // Constant pool entries
215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
221 setOperationAction(ISD::ADDC, MVT::i32, Custom);
222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
223 setOperationAction(ISD::SUBC, MVT::i32, Custom);
224 setOperationAction(ISD::SUBE, MVT::i32, Custom);
225 setOperationAction(ISD::ADDC, MVT::i64, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
227 setOperationAction(ISD::SUBC, MVT::i64, Custom);
228 setOperationAction(ISD::SUBE, MVT::i64, Custom);
230 // AArch64 lacks both left-rotate and popcount instructions.
231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
234 // AArch64 doesn't have {U|S}MUL_LOHI.
235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240 // counterparts, which AArch64 supports directly.
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
247 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::SREM, MVT::i64, Expand);
253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::UREM, MVT::i32, Expand);
256 setOperationAction(ISD::UREM, MVT::i64, Expand);
258 // Custom lower Add/Sub/Mul with overflow.
259 setOperationAction(ISD::SADDO, MVT::i32, Custom);
260 setOperationAction(ISD::SADDO, MVT::i64, Custom);
261 setOperationAction(ISD::UADDO, MVT::i32, Custom);
262 setOperationAction(ISD::UADDO, MVT::i64, Custom);
263 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
265 setOperationAction(ISD::USUBO, MVT::i32, Custom);
266 setOperationAction(ISD::USUBO, MVT::i64, Custom);
267 setOperationAction(ISD::SMULO, MVT::i32, Custom);
268 setOperationAction(ISD::SMULO, MVT::i64, Custom);
269 setOperationAction(ISD::UMULO, MVT::i32, Custom);
270 setOperationAction(ISD::UMULO, MVT::i64, Custom);
272 setOperationAction(ISD::FSIN, MVT::f32, Expand);
273 setOperationAction(ISD::FSIN, MVT::f64, Expand);
274 setOperationAction(ISD::FCOS, MVT::f32, Expand);
275 setOperationAction(ISD::FCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FPOW, MVT::f32, Expand);
277 setOperationAction(ISD::FPOW, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
281 // AArch64 has implementations of a lot of rounding-like FP operations.
282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284 MVT Ty = RoundingTypes[I];
285 setOperationAction(ISD::FFLOOR, Ty, Legal);
286 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
287 setOperationAction(ISD::FCEIL, Ty, Legal);
288 setOperationAction(ISD::FRINT, Ty, Legal);
289 setOperationAction(ISD::FTRUNC, Ty, Legal);
290 setOperationAction(ISD::FROUND, Ty, Legal);
293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
295 if (Subtarget->isTargetMachO()) {
296 // For iOS, we don't want to the normal expansion of a libcall to
297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
306 // AArch64 does not have floating-point extending loads, i1 sign-extending
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
308 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
309 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
312 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
315 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
319 // Indexed loads and stores are supported.
320 for (unsigned im = (unsigned)ISD::PRE_INC;
321 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
322 setIndexedLoadAction(im, MVT::i8, Legal);
323 setIndexedLoadAction(im, MVT::i16, Legal);
324 setIndexedLoadAction(im, MVT::i32, Legal);
325 setIndexedLoadAction(im, MVT::i64, Legal);
326 setIndexedLoadAction(im, MVT::f64, Legal);
327 setIndexedLoadAction(im, MVT::f32, Legal);
328 setIndexedStoreAction(im, MVT::i8, Legal);
329 setIndexedStoreAction(im, MVT::i16, Legal);
330 setIndexedStoreAction(im, MVT::i32, Legal);
331 setIndexedStoreAction(im, MVT::i64, Legal);
332 setIndexedStoreAction(im, MVT::f64, Legal);
333 setIndexedStoreAction(im, MVT::f32, Legal);
337 setOperationAction(ISD::TRAP, MVT::Other, Legal);
339 // We combine OR nodes for bitfield operations.
340 setTargetDAGCombine(ISD::OR);
342 // Vector add and sub nodes may conceal a high-half opportunity.
343 // Also, try to fold ADD into CSINC/CSINV..
344 setTargetDAGCombine(ISD::ADD);
345 setTargetDAGCombine(ISD::SUB);
347 setTargetDAGCombine(ISD::XOR);
348 setTargetDAGCombine(ISD::SINT_TO_FP);
349 setTargetDAGCombine(ISD::UINT_TO_FP);
351 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
353 setTargetDAGCombine(ISD::ANY_EXTEND);
354 setTargetDAGCombine(ISD::ZERO_EXTEND);
355 setTargetDAGCombine(ISD::SIGN_EXTEND);
356 setTargetDAGCombine(ISD::BITCAST);
357 setTargetDAGCombine(ISD::CONCAT_VECTORS);
358 setTargetDAGCombine(ISD::STORE);
360 setTargetDAGCombine(ISD::MUL);
362 setTargetDAGCombine(ISD::SELECT);
363 setTargetDAGCombine(ISD::VSELECT);
365 setTargetDAGCombine(ISD::INTRINSIC_VOID);
366 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
367 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
369 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
370 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
371 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
373 setStackPointerRegisterToSaveRestore(AArch64::SP);
375 setSchedulingPreference(Sched::Hybrid);
378 MaskAndBranchFoldingIsLegal = true;
380 setMinFunctionAlignment(2);
382 RequireStrictAlign = (Align == StrictAlign);
384 setHasExtractBitsInsn(true);
386 if (Subtarget->hasNEON()) {
387 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
388 // silliness like this:
389 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
390 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
391 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
394 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
395 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
396 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
398 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
400 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
401 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
402 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
403 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
404 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
408 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
410 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
411 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
413 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
415 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
416 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
418 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
421 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
423 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
424 // elements smaller than i32, so promote the input to i32 first.
425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
426 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
429 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
430 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
431 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
435 // AArch64 doesn't have MUL.2d:
436 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
437 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
438 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
439 // Likewise, narrowing and extending vector loads/stores aren't handled
441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
442 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
444 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
447 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
448 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
452 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
454 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
455 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
456 setTruncStoreAction((MVT::SimpleValueType)VT,
457 (MVT::SimpleValueType)InnerVT, Expand);
458 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
463 // AArch64 has implementations of a lot of rounding-like FP operations.
464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
465 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
466 MVT Ty = RoundingVecTypes[I];
467 setOperationAction(ISD::FFLOOR, Ty, Legal);
468 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
469 setOperationAction(ISD::FCEIL, Ty, Legal);
470 setOperationAction(ISD::FRINT, Ty, Legal);
471 setOperationAction(ISD::FTRUNC, Ty, Legal);
472 setOperationAction(ISD::FROUND, Ty, Legal);
477 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
478 if (VT == MVT::v2f32) {
479 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
480 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
482 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
483 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
484 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
485 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
486 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
488 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
489 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
492 // Mark vector float intrinsics as expand.
493 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
494 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
495 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
506 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
518 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
519 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
521 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
523 // CNT supports only B element sizes.
524 if (VT != MVT::v8i8 && VT != MVT::v16i8)
525 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
527 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
533 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
534 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
536 if (Subtarget->isLittleEndian()) {
537 for (unsigned im = (unsigned)ISD::PRE_INC;
538 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
539 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
540 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
545 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
546 addRegisterClass(VT, &AArch64::FPR64RegClass);
547 addTypeForNEON(VT, MVT::v2i32);
550 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
551 addRegisterClass(VT, &AArch64::FPR128RegClass);
552 addTypeForNEON(VT, MVT::v4i32);
555 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
558 return VT.changeVectorElementTypeToInteger();
561 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
562 /// Mask are known to be either zero or one and return them in the
563 /// KnownZero/KnownOne bitsets.
564 void AArch64TargetLowering::computeKnownBitsForTargetNode(
565 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
566 const SelectionDAG &DAG, unsigned Depth) const {
567 switch (Op.getOpcode()) {
570 case AArch64ISD::CSEL: {
571 APInt KnownZero2, KnownOne2;
572 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
573 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
574 KnownZero &= KnownZero2;
575 KnownOne &= KnownOne2;
578 case ISD::INTRINSIC_W_CHAIN: {
579 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
580 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
583 case Intrinsic::aarch64_ldaxr:
584 case Intrinsic::aarch64_ldxr: {
585 unsigned BitWidth = KnownOne.getBitWidth();
586 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
587 unsigned MemBits = VT.getScalarType().getSizeInBits();
588 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
594 case ISD::INTRINSIC_WO_CHAIN:
595 case ISD::INTRINSIC_VOID: {
596 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
600 case Intrinsic::aarch64_neon_umaxv:
601 case Intrinsic::aarch64_neon_uminv: {
602 // Figure out the datatype of the vector operand. The UMINV instruction
603 // will zero extend the result, so we can mark as known zero all the
604 // bits larger than the element datatype. 32-bit or larget doesn't need
605 // this as those are legal types and will be handled by isel directly.
606 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
607 unsigned BitWidth = KnownZero.getBitWidth();
608 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
609 assert(BitWidth >= 8 && "Unexpected width!");
610 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
612 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
613 assert(BitWidth >= 16 && "Unexpected width!");
614 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
624 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
628 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
629 // FIXME: On AArch64, this depends on the type.
630 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
631 // and the offset has to be a multiple of the related size in bytes.
636 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
637 const TargetLibraryInfo *libInfo) const {
638 return AArch64::createFastISel(funcInfo, libInfo);
641 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
645 case AArch64ISD::CALL: return "AArch64ISD::CALL";
646 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
647 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
648 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
649 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
650 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
651 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
652 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
653 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
654 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
655 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
656 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
657 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
658 case AArch64ISD::ADC: return "AArch64ISD::ADC";
659 case AArch64ISD::SBC: return "AArch64ISD::SBC";
660 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
661 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
662 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
663 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
664 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
665 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
666 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
667 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
668 case AArch64ISD::DUP: return "AArch64ISD::DUP";
669 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
670 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
671 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
672 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
673 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
674 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
675 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
676 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
677 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
678 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
679 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
680 case AArch64ISD::BICi: return "AArch64ISD::BICi";
681 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
682 case AArch64ISD::BSL: return "AArch64ISD::BSL";
683 case AArch64ISD::NEG: return "AArch64ISD::NEG";
684 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
685 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
686 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
687 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
688 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
689 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
690 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
691 case AArch64ISD::REV16: return "AArch64ISD::REV16";
692 case AArch64ISD::REV32: return "AArch64ISD::REV32";
693 case AArch64ISD::REV64: return "AArch64ISD::REV64";
694 case AArch64ISD::EXT: return "AArch64ISD::EXT";
695 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
696 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
697 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
698 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
699 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
700 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
701 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
702 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
703 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
704 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
705 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
706 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
707 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
708 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
709 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
710 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
711 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
712 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
713 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
714 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
715 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
716 case AArch64ISD::NOT: return "AArch64ISD::NOT";
717 case AArch64ISD::BIT: return "AArch64ISD::BIT";
718 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
719 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
720 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
721 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
722 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
723 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
724 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
725 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
726 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
727 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
728 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
729 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
730 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
731 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
732 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
733 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
734 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
735 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
736 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
737 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
738 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
739 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
740 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
741 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
742 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
743 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
744 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
745 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
746 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
747 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
748 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
749 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
750 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
751 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
752 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
753 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
758 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
759 MachineBasicBlock *MBB) const {
760 // We materialise the F128CSEL pseudo-instruction as some control flow and a
764 // [... previous instrs leading to comparison ...]
770 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
772 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
773 MachineFunction *MF = MBB->getParent();
774 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
775 DebugLoc DL = MI->getDebugLoc();
776 MachineFunction::iterator It = MBB;
779 unsigned DestReg = MI->getOperand(0).getReg();
780 unsigned IfTrueReg = MI->getOperand(1).getReg();
781 unsigned IfFalseReg = MI->getOperand(2).getReg();
782 unsigned CondCode = MI->getOperand(3).getImm();
783 bool NZCVKilled = MI->getOperand(4).isKill();
785 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
786 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MF->insert(It, TrueBB);
788 MF->insert(It, EndBB);
790 // Transfer rest of current basic-block to EndBB
791 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
793 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
795 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
796 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
797 MBB->addSuccessor(TrueBB);
798 MBB->addSuccessor(EndBB);
800 // TrueBB falls through to the end.
801 TrueBB->addSuccessor(EndBB);
804 TrueBB->addLiveIn(AArch64::NZCV);
805 EndBB->addLiveIn(AArch64::NZCV);
808 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
814 MI->eraseFromParent();
819 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
820 MachineBasicBlock *BB) const {
821 switch (MI->getOpcode()) {
826 llvm_unreachable("Unexpected instruction for custom inserter!");
828 case AArch64::F128CSEL:
829 return EmitF128CSEL(MI, BB);
831 case TargetOpcode::STACKMAP:
832 case TargetOpcode::PATCHPOINT:
833 return emitPatchPoint(MI, BB);
837 //===----------------------------------------------------------------------===//
838 // AArch64 Lowering private implementation.
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
847 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
850 llvm_unreachable("Unknown condition code!");
852 return AArch64CC::NE;
854 return AArch64CC::EQ;
856 return AArch64CC::GT;
858 return AArch64CC::GE;
860 return AArch64CC::LT;
862 return AArch64CC::LE;
864 return AArch64CC::HI;
866 return AArch64CC::HS;
868 return AArch64CC::LO;
870 return AArch64CC::LS;
874 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
875 static void changeFPCCToAArch64CC(ISD::CondCode CC,
876 AArch64CC::CondCode &CondCode,
877 AArch64CC::CondCode &CondCode2) {
878 CondCode2 = AArch64CC::AL;
881 llvm_unreachable("Unknown FP condition!");
884 CondCode = AArch64CC::EQ;
888 CondCode = AArch64CC::GT;
892 CondCode = AArch64CC::GE;
895 CondCode = AArch64CC::MI;
898 CondCode = AArch64CC::LS;
901 CondCode = AArch64CC::MI;
902 CondCode2 = AArch64CC::GT;
905 CondCode = AArch64CC::VC;
908 CondCode = AArch64CC::VS;
911 CondCode = AArch64CC::EQ;
912 CondCode2 = AArch64CC::VS;
915 CondCode = AArch64CC::HI;
918 CondCode = AArch64CC::PL;
922 CondCode = AArch64CC::LT;
926 CondCode = AArch64CC::LE;
930 CondCode = AArch64CC::NE;
935 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
936 /// CC usable with the vector instructions. Fewer operations are available
937 /// without a real NZCV register, so we have to use less efficient combinations
938 /// to get the same effect.
939 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
940 AArch64CC::CondCode &CondCode,
941 AArch64CC::CondCode &CondCode2,
946 // Mostly the scalar mappings work fine.
947 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
950 Invert = true; // Fallthrough
952 CondCode = AArch64CC::MI;
953 CondCode2 = AArch64CC::GE;
960 // All of the compare-mask comparisons are ordered, but we can switch
961 // between the two by a double inversion. E.g. ULE == !OGT.
963 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
968 static bool isLegalArithImmed(uint64_t C) {
969 // Matches AArch64DAGToDAGISel::SelectArithImmed().
970 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
973 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
974 SDLoc dl, SelectionDAG &DAG) {
975 EVT VT = LHS.getValueType();
977 if (VT.isFloatingPoint())
978 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
980 // The CMP instruction is just an alias for SUBS, and representing it as
981 // SUBS means that it's possible to get CSE with subtract operations.
982 // A later phase can perform the optimization of setting the destination
983 // register to WZR/XZR if it ends up being unused.
984 unsigned Opcode = AArch64ISD::SUBS;
986 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
987 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
988 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
989 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
990 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
991 // can be set differently by this operation. It comes down to whether
992 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
993 // everything is fine. If not then the optimization is wrong. Thus general
994 // comparisons are only valid if op2 != 0.
996 // So, finally, the only LLVM-native comparisons that don't mention C and V
997 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
998 // the absence of information about op2.
999 Opcode = AArch64ISD::ADDS;
1000 RHS = RHS.getOperand(1);
1001 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1002 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1003 !isUnsignedIntSetCC(CC)) {
1004 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1005 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1006 // of the signed comparisons.
1007 Opcode = AArch64ISD::ANDS;
1008 RHS = LHS.getOperand(1);
1009 LHS = LHS.getOperand(0);
1012 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1016 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1017 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1018 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1019 EVT VT = RHS.getValueType();
1020 uint64_t C = RHSC->getZExtValue();
1021 if (!isLegalArithImmed(C)) {
1022 // Constant does not fit, try adjusting it by one?
1028 if ((VT == MVT::i32 && C != 0x80000000 &&
1029 isLegalArithImmed((uint32_t)(C - 1))) ||
1030 (VT == MVT::i64 && C != 0x80000000ULL &&
1031 isLegalArithImmed(C - 1ULL))) {
1032 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1033 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1034 RHS = DAG.getConstant(C, VT);
1039 if ((VT == MVT::i32 && C != 0 &&
1040 isLegalArithImmed((uint32_t)(C - 1))) ||
1041 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1042 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1043 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1044 RHS = DAG.getConstant(C, VT);
1049 if ((VT == MVT::i32 && C != 0x7fffffff &&
1050 isLegalArithImmed((uint32_t)(C + 1))) ||
1051 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1052 isLegalArithImmed(C + 1ULL))) {
1053 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1054 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1055 RHS = DAG.getConstant(C, VT);
1060 if ((VT == MVT::i32 && C != 0xffffffff &&
1061 isLegalArithImmed((uint32_t)(C + 1))) ||
1062 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1063 isLegalArithImmed(C + 1ULL))) {
1064 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1065 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1066 RHS = DAG.getConstant(C, VT);
1073 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1074 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1075 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1079 static std::pair<SDValue, SDValue>
1080 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1081 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1082 "Unsupported value type");
1083 SDValue Value, Overflow;
1085 SDValue LHS = Op.getOperand(0);
1086 SDValue RHS = Op.getOperand(1);
1088 switch (Op.getOpcode()) {
1090 llvm_unreachable("Unknown overflow instruction!");
1092 Opc = AArch64ISD::ADDS;
1096 Opc = AArch64ISD::ADDS;
1100 Opc = AArch64ISD::SUBS;
1104 Opc = AArch64ISD::SUBS;
1107 // Multiply needs a little bit extra work.
1111 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1112 if (Op.getValueType() == MVT::i32) {
1113 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1114 // For a 32 bit multiply with overflow check we want the instruction
1115 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1116 // need to generate the following pattern:
1117 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1118 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1119 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1120 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1121 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1122 DAG.getConstant(0, MVT::i64));
1123 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1124 // operation. We need to clear out the upper 32 bits, because we used a
1125 // widening multiply that wrote all 64 bits. In the end this should be a
1127 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1129 // The signed overflow check requires more than just a simple check for
1130 // any bit set in the upper 32 bits of the result. These bits could be
1131 // just the sign bits of a negative number. To perform the overflow
1132 // check we have to arithmetic shift right the 32nd bit of the result by
1133 // 31 bits. Then we compare the result to the upper 32 bits.
1134 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1135 DAG.getConstant(32, MVT::i64));
1136 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1137 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1138 DAG.getConstant(31, MVT::i64));
1139 // It is important that LowerBits is last, otherwise the arithmetic
1140 // shift will not be folded into the compare (SUBS).
1141 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1142 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1145 // The overflow check for unsigned multiply is easy. We only need to
1146 // check if any of the upper 32 bits are set. This can be done with a
1147 // CMP (shifted register). For that we need to generate the following
1149 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1150 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1151 DAG.getConstant(32, MVT::i64));
1152 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1154 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1155 UpperBits).getValue(1);
1159 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1160 // For the 64 bit multiply
1161 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1163 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1164 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1165 DAG.getConstant(63, MVT::i64));
1166 // It is important that LowerBits is last, otherwise the arithmetic
1167 // shift will not be folded into the compare (SUBS).
1168 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1169 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1172 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1173 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1175 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1176 UpperBits).getValue(1);
1183 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1185 // Emit the AArch64 operation with overflow check.
1186 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1187 Overflow = Value.getValue(1);
1189 return std::make_pair(Value, Overflow);
1192 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1193 RTLIB::Libcall Call) const {
1194 SmallVector<SDValue, 2> Ops;
1195 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1196 Ops.push_back(Op.getOperand(i));
1198 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1202 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1203 SDValue Sel = Op.getOperand(0);
1204 SDValue Other = Op.getOperand(1);
1206 // If neither operand is a SELECT_CC, give up.
1207 if (Sel.getOpcode() != ISD::SELECT_CC)
1208 std::swap(Sel, Other);
1209 if (Sel.getOpcode() != ISD::SELECT_CC)
1212 // The folding we want to perform is:
1213 // (xor x, (select_cc a, b, cc, 0, -1) )
1215 // (csel x, (xor x, -1), cc ...)
1217 // The latter will get matched to a CSINV instruction.
1219 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1220 SDValue LHS = Sel.getOperand(0);
1221 SDValue RHS = Sel.getOperand(1);
1222 SDValue TVal = Sel.getOperand(2);
1223 SDValue FVal = Sel.getOperand(3);
1226 // FIXME: This could be generalized to non-integer comparisons.
1227 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1230 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1231 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1233 // The the values aren't constants, this isn't the pattern we're looking for.
1234 if (!CFVal || !CTVal)
1237 // We can commute the SELECT_CC by inverting the condition. This
1238 // might be needed to make this fit into a CSINV pattern.
1239 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1240 std::swap(TVal, FVal);
1241 std::swap(CTVal, CFVal);
1242 CC = ISD::getSetCCInverse(CC, true);
1245 // If the constants line up, perform the transform!
1246 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1248 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1251 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1252 DAG.getConstant(-1ULL, Other.getValueType()));
1254 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1261 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1262 EVT VT = Op.getValueType();
1264 // Let legalize expand this if it isn't a legal type yet.
1265 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1268 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1271 bool ExtraOp = false;
1272 switch (Op.getOpcode()) {
1274 llvm_unreachable("Invalid code");
1276 Opc = AArch64ISD::ADDS;
1279 Opc = AArch64ISD::SUBS;
1282 Opc = AArch64ISD::ADCS;
1286 Opc = AArch64ISD::SBCS;
1292 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1293 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1297 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1298 // Let legalize expand this if it isn't a legal type yet.
1299 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1302 AArch64CC::CondCode CC;
1303 // The actual operation that sets the overflow or carry flag.
1304 SDValue Value, Overflow;
1305 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1307 // We use 0 and 1 as false and true values.
1308 SDValue TVal = DAG.getConstant(1, MVT::i32);
1309 SDValue FVal = DAG.getConstant(0, MVT::i32);
1311 // We use an inverted condition, because the conditional select is inverted
1312 // too. This will allow it to be selected to a single instruction:
1313 // CSINC Wd, WZR, WZR, invert(cond).
1314 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1315 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1318 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1319 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1322 // Prefetch operands are:
1323 // 1: Address to prefetch
1325 // 3: int locality (0 = no locality ... 3 = extreme locality)
1326 // 4: bool isDataCache
1327 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1329 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1330 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1331 // The data thing is not used.
1332 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1334 bool IsStream = !Locality;
1335 // When the locality number is set
1337 // The front-end should have filtered out the out-of-range values
1338 assert(Locality <= 3 && "Prefetch locality out-of-range");
1339 // The locality degree is the opposite of the cache speed.
1340 // Put the number the other way around.
1341 // The encoding starts at 0 for level 1
1342 Locality = 3 - Locality;
1345 // built the mask value encoding the expected behavior.
1346 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1347 (Locality << 1) | // Cache level bits
1348 (unsigned)IsStream; // Stream bit
1349 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1350 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1353 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1354 SelectionDAG &DAG) const {
1355 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1358 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1360 return LowerF128Call(Op, DAG, LC);
1363 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1364 SelectionDAG &DAG) const {
1365 if (Op.getOperand(0).getValueType() != MVT::f128) {
1366 // It's legal except when f128 is involved
1371 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1373 // FP_ROUND node has a second operand indicating whether it is known to be
1374 // precise. That doesn't take part in the LibCall so we can't directly use
1376 SDValue SrcVal = Op.getOperand(0);
1377 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1378 /*isSigned*/ false, SDLoc(Op)).first;
1381 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1382 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1383 // Any additional optimization in this function should be recorded
1384 // in the cost tables.
1385 EVT InVT = Op.getOperand(0).getValueType();
1386 EVT VT = Op.getValueType();
1388 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1391 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1393 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1396 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1398 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1399 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1402 // Type changing conversions are illegal.
1406 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1407 SelectionDAG &DAG) const {
1408 if (Op.getOperand(0).getValueType().isVector())
1409 return LowerVectorFP_TO_INT(Op, DAG);
1411 if (Op.getOperand(0).getValueType() != MVT::f128) {
1412 // It's legal except when f128 is involved
1417 if (Op.getOpcode() == ISD::FP_TO_SINT)
1418 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1420 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1422 SmallVector<SDValue, 2> Ops;
1423 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1424 Ops.push_back(Op.getOperand(i));
1426 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1430 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1431 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1432 // Any additional optimization in this function should be recorded
1433 // in the cost tables.
1434 EVT VT = Op.getValueType();
1436 SDValue In = Op.getOperand(0);
1437 EVT InVT = In.getValueType();
1439 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1441 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1442 InVT.getVectorNumElements());
1443 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1444 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1447 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1449 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1450 EVT CastVT = VT.changeVectorElementTypeToInteger();
1451 In = DAG.getNode(CastOpc, dl, CastVT, In);
1452 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1458 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1459 SelectionDAG &DAG) const {
1460 if (Op.getValueType().isVector())
1461 return LowerVectorINT_TO_FP(Op, DAG);
1463 // i128 conversions are libcalls.
1464 if (Op.getOperand(0).getValueType() == MVT::i128)
1467 // Other conversions are legal, unless it's to the completely software-based
1469 if (Op.getValueType() != MVT::f128)
1473 if (Op.getOpcode() == ISD::SINT_TO_FP)
1474 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1476 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1478 return LowerF128Call(Op, DAG, LC);
1481 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1482 SelectionDAG &DAG) const {
1483 // For iOS, we want to call an alternative entry point: __sincos_stret,
1484 // which returns the values in two S / D registers.
1486 SDValue Arg = Op.getOperand(0);
1487 EVT ArgVT = Arg.getValueType();
1488 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1495 Entry.isSExt = false;
1496 Entry.isZExt = false;
1497 Args.push_back(Entry);
1499 const char *LibcallName =
1500 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1501 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1503 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1504 TargetLowering::CallLoweringInfo CLI(DAG);
1505 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1506 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1508 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1509 return CallResult.first;
1512 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1513 SelectionDAG &DAG) const {
1514 switch (Op.getOpcode()) {
1516 llvm_unreachable("unimplemented operand");
1518 case ISD::GlobalAddress:
1519 return LowerGlobalAddress(Op, DAG);
1520 case ISD::GlobalTLSAddress:
1521 return LowerGlobalTLSAddress(Op, DAG);
1523 return LowerSETCC(Op, DAG);
1525 return LowerBR_CC(Op, DAG);
1527 return LowerSELECT(Op, DAG);
1528 case ISD::SELECT_CC:
1529 return LowerSELECT_CC(Op, DAG);
1530 case ISD::JumpTable:
1531 return LowerJumpTable(Op, DAG);
1532 case ISD::ConstantPool:
1533 return LowerConstantPool(Op, DAG);
1534 case ISD::BlockAddress:
1535 return LowerBlockAddress(Op, DAG);
1537 return LowerVASTART(Op, DAG);
1539 return LowerVACOPY(Op, DAG);
1541 return LowerVAARG(Op, DAG);
1546 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1553 return LowerXALUO(Op, DAG);
1555 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1557 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1559 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1561 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1563 return LowerFP_ROUND(Op, DAG);
1564 case ISD::FP_EXTEND:
1565 return LowerFP_EXTEND(Op, DAG);
1566 case ISD::FRAMEADDR:
1567 return LowerFRAMEADDR(Op, DAG);
1568 case ISD::RETURNADDR:
1569 return LowerRETURNADDR(Op, DAG);
1570 case ISD::INSERT_VECTOR_ELT:
1571 return LowerINSERT_VECTOR_ELT(Op, DAG);
1572 case ISD::EXTRACT_VECTOR_ELT:
1573 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1574 case ISD::BUILD_VECTOR:
1575 return LowerBUILD_VECTOR(Op, DAG);
1576 case ISD::VECTOR_SHUFFLE:
1577 return LowerVECTOR_SHUFFLE(Op, DAG);
1578 case ISD::EXTRACT_SUBVECTOR:
1579 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1583 return LowerVectorSRA_SRL_SHL(Op, DAG);
1584 case ISD::SHL_PARTS:
1585 return LowerShiftLeftParts(Op, DAG);
1586 case ISD::SRL_PARTS:
1587 case ISD::SRA_PARTS:
1588 return LowerShiftRightParts(Op, DAG);
1590 return LowerCTPOP(Op, DAG);
1591 case ISD::FCOPYSIGN:
1592 return LowerFCOPYSIGN(Op, DAG);
1594 return LowerVectorAND(Op, DAG);
1596 return LowerVectorOR(Op, DAG);
1598 return LowerXOR(Op, DAG);
1600 return LowerPREFETCH(Op, DAG);
1601 case ISD::SINT_TO_FP:
1602 case ISD::UINT_TO_FP:
1603 return LowerINT_TO_FP(Op, DAG);
1604 case ISD::FP_TO_SINT:
1605 case ISD::FP_TO_UINT:
1606 return LowerFP_TO_INT(Op, DAG);
1608 return LowerFSINCOS(Op, DAG);
1612 /// getFunctionAlignment - Return the Log2 alignment of this function.
1613 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1617 //===----------------------------------------------------------------------===//
1618 // Calling Convention Implementation
1619 //===----------------------------------------------------------------------===//
1621 #include "AArch64GenCallingConv.inc"
1623 /// Selects the correct CCAssignFn for a the given CallingConvention
1625 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1626 bool IsVarArg) const {
1629 llvm_unreachable("Unsupported calling convention.");
1630 case CallingConv::WebKit_JS:
1631 return CC_AArch64_WebKit_JS;
1632 case CallingConv::C:
1633 case CallingConv::Fast:
1634 if (!Subtarget->isTargetDarwin())
1635 return CC_AArch64_AAPCS;
1636 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1640 SDValue AArch64TargetLowering::LowerFormalArguments(
1641 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1642 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1643 SmallVectorImpl<SDValue> &InVals) const {
1644 MachineFunction &MF = DAG.getMachineFunction();
1645 MachineFrameInfo *MFI = MF.getFrameInfo();
1647 // Assign locations to all of the incoming arguments.
1648 SmallVector<CCValAssign, 16> ArgLocs;
1649 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1650 getTargetMachine(), ArgLocs, *DAG.getContext());
1652 // At this point, Ins[].VT may already be promoted to i32. To correctly
1653 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1654 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1655 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1656 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1658 unsigned NumArgs = Ins.size();
1659 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1660 unsigned CurArgIdx = 0;
1661 for (unsigned i = 0; i != NumArgs; ++i) {
1662 MVT ValVT = Ins[i].VT;
1663 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1664 CurArgIdx = Ins[i].OrigArgIndex;
1666 // Get type of the original argument.
1667 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1668 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1669 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1670 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1672 else if (ActualMVT == MVT::i16)
1675 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1677 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1678 assert(!Res && "Call operand has unhandled type");
1681 assert(ArgLocs.size() == Ins.size());
1682 SmallVector<SDValue, 16> ArgValues;
1683 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1684 CCValAssign &VA = ArgLocs[i];
1686 if (Ins[i].Flags.isByVal()) {
1687 // Byval is used for HFAs in the PCS, but the system should work in a
1688 // non-compliant manner for larger structs.
1689 EVT PtrTy = getPointerTy();
1690 int Size = Ins[i].Flags.getByValSize();
1691 unsigned NumRegs = (Size + 7) / 8;
1693 // FIXME: This works on big-endian for composite byvals, which are the common
1694 // case. It should also work for fundamental types too.
1696 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1697 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1698 InVals.push_back(FrameIdxN);
1703 if (VA.isRegLoc()) {
1704 // Arguments stored in registers.
1705 EVT RegVT = VA.getLocVT();
1708 const TargetRegisterClass *RC;
1710 if (RegVT == MVT::i32)
1711 RC = &AArch64::GPR32RegClass;
1712 else if (RegVT == MVT::i64)
1713 RC = &AArch64::GPR64RegClass;
1714 else if (RegVT == MVT::f16)
1715 RC = &AArch64::FPR16RegClass;
1716 else if (RegVT == MVT::f32)
1717 RC = &AArch64::FPR32RegClass;
1718 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1719 RC = &AArch64::FPR64RegClass;
1720 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1721 RC = &AArch64::FPR128RegClass;
1723 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1725 // Transform the arguments in physical registers into virtual ones.
1726 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1727 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1729 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1730 // to 64 bits. Insert an assert[sz]ext to capture this, then
1731 // truncate to the right size.
1732 switch (VA.getLocInfo()) {
1734 llvm_unreachable("Unknown loc info!");
1735 case CCValAssign::Full:
1737 case CCValAssign::BCvt:
1738 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1740 case CCValAssign::AExt:
1741 case CCValAssign::SExt:
1742 case CCValAssign::ZExt:
1743 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1744 // nodes after our lowering.
1745 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1749 InVals.push_back(ArgValue);
1751 } else { // VA.isRegLoc()
1752 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1753 unsigned ArgOffset = VA.getLocMemOffset();
1754 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1756 uint32_t BEAlign = 0;
1757 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1758 BEAlign = 8 - ArgSize;
1760 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1762 // Create load nodes to retrieve arguments from the stack.
1763 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1766 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1767 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1768 MVT MemVT = VA.getValVT();
1770 switch (VA.getLocInfo()) {
1773 case CCValAssign::BCvt:
1774 MemVT = VA.getLocVT();
1776 case CCValAssign::SExt:
1777 ExtType = ISD::SEXTLOAD;
1779 case CCValAssign::ZExt:
1780 ExtType = ISD::ZEXTLOAD;
1782 case CCValAssign::AExt:
1783 ExtType = ISD::EXTLOAD;
1787 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1788 MachinePointerInfo::getFixedStack(FI),
1789 MemVT, false, false, false, nullptr);
1791 InVals.push_back(ArgValue);
1797 if (!Subtarget->isTargetDarwin()) {
1798 // The AAPCS variadic function ABI is identical to the non-variadic
1799 // one. As a result there may be more arguments in registers and we should
1800 // save them for future reference.
1801 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1804 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1805 // This will point to the next argument passed via stack.
1806 unsigned StackOffset = CCInfo.getNextStackOffset();
1807 // We currently pass all varargs at 8-byte alignment.
1808 StackOffset = ((StackOffset + 7) & ~7);
1809 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1812 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1813 unsigned StackArgSize = CCInfo.getNextStackOffset();
1814 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1815 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1816 // This is a non-standard ABI so by fiat I say we're allowed to make full
1817 // use of the stack area to be popped, which must be aligned to 16 bytes in
1819 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1821 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1822 // a multiple of 16.
1823 FuncInfo->setArgumentStackToRestore(StackArgSize);
1825 // This realignment carries over to the available bytes below. Our own
1826 // callers will guarantee the space is free by giving an aligned value to
1829 // Even if we're not expected to free up the space, it's useful to know how
1830 // much is there while considering tail calls (because we can reuse it).
1831 FuncInfo->setBytesInStackArgArea(StackArgSize);
1836 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1837 SelectionDAG &DAG, SDLoc DL,
1838 SDValue &Chain) const {
1839 MachineFunction &MF = DAG.getMachineFunction();
1840 MachineFrameInfo *MFI = MF.getFrameInfo();
1841 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1843 SmallVector<SDValue, 8> MemOps;
1845 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1846 AArch64::X3, AArch64::X4, AArch64::X5,
1847 AArch64::X6, AArch64::X7 };
1848 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1849 unsigned FirstVariadicGPR =
1850 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1852 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1854 if (GPRSaveSize != 0) {
1855 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1857 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1859 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1860 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1861 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1863 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1864 MachinePointerInfo::getStack(i * 8), false, false, 0);
1865 MemOps.push_back(Store);
1866 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1867 DAG.getConstant(8, getPointerTy()));
1870 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1871 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1873 if (Subtarget->hasFPARMv8()) {
1874 static const MCPhysReg FPRArgRegs[] = {
1875 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1876 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1877 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1878 unsigned FirstVariadicFPR =
1879 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1881 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1883 if (FPRSaveSize != 0) {
1884 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1886 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1888 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1889 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1890 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1893 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1894 MachinePointerInfo::getStack(i * 16), false, false, 0);
1895 MemOps.push_back(Store);
1896 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1897 DAG.getConstant(16, getPointerTy()));
1900 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1901 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1904 if (!MemOps.empty()) {
1905 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1909 /// LowerCallResult - Lower the result values of a call into the
1910 /// appropriate copies out of appropriate physical registers.
1911 SDValue AArch64TargetLowering::LowerCallResult(
1912 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1913 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1914 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1915 SDValue ThisVal) const {
1916 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1917 ? RetCC_AArch64_WebKit_JS
1918 : RetCC_AArch64_AAPCS;
1919 // Assign locations to each value returned by this call.
1920 SmallVector<CCValAssign, 16> RVLocs;
1921 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1922 getTargetMachine(), RVLocs, *DAG.getContext());
1923 CCInfo.AnalyzeCallResult(Ins, RetCC);
1925 // Copy all of the result registers out of their specified physreg.
1926 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1927 CCValAssign VA = RVLocs[i];
1929 // Pass 'this' value directly from the argument to return value, to avoid
1930 // reg unit interference
1931 if (i == 0 && isThisReturn) {
1932 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1933 "unexpected return calling convention register assignment");
1934 InVals.push_back(ThisVal);
1939 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1940 Chain = Val.getValue(1);
1941 InFlag = Val.getValue(2);
1943 switch (VA.getLocInfo()) {
1945 llvm_unreachable("Unknown loc info!");
1946 case CCValAssign::Full:
1948 case CCValAssign::BCvt:
1949 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1953 InVals.push_back(Val);
1959 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1960 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1961 bool isCalleeStructRet, bool isCallerStructRet,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 const SmallVectorImpl<SDValue> &OutVals,
1964 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1965 // For CallingConv::C this function knows whether the ABI needs
1966 // changing. That's not true for other conventions so they will have to opt in
1968 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1971 const MachineFunction &MF = DAG.getMachineFunction();
1972 const Function *CallerF = MF.getFunction();
1973 CallingConv::ID CallerCC = CallerF->getCallingConv();
1974 bool CCMatch = CallerCC == CalleeCC;
1976 // Byval parameters hand the function a pointer directly into the stack area
1977 // we want to reuse during a tail call. Working around this *is* possible (see
1978 // X86) but less efficient and uglier in LowerCall.
1979 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1980 e = CallerF->arg_end();
1982 if (i->hasByValAttr())
1985 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1986 if (IsTailCallConvention(CalleeCC) && CCMatch)
1991 // Now we search for cases where we can use a tail call without changing the
1992 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1995 // I want anyone implementing a new calling convention to think long and hard
1996 // about this assert.
1997 assert((!isVarArg || CalleeCC == CallingConv::C) &&
1998 "Unexpected variadic calling convention");
2000 if (isVarArg && !Outs.empty()) {
2001 // At least two cases here: if caller is fastcc then we can't have any
2002 // memory arguments (we'd be expected to clean up the stack afterwards). If
2003 // caller is C then we could potentially use its argument area.
2005 // FIXME: for now we take the most conservative of these in both cases:
2006 // disallow all variadic memory operands.
2007 SmallVector<CCValAssign, 16> ArgLocs;
2008 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2009 getTargetMachine(), ArgLocs, *DAG.getContext());
2011 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2013 if (!ArgLocs[i].isRegLoc())
2017 // If the calling conventions do not match, then we'd better make sure the
2018 // results are returned in the same way as what the caller expects.
2020 SmallVector<CCValAssign, 16> RVLocs1;
2021 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2022 getTargetMachine(), RVLocs1, *DAG.getContext());
2023 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2025 SmallVector<CCValAssign, 16> RVLocs2;
2026 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2027 getTargetMachine(), RVLocs2, *DAG.getContext());
2028 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2030 if (RVLocs1.size() != RVLocs2.size())
2032 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2033 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2035 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2037 if (RVLocs1[i].isRegLoc()) {
2038 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2041 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2047 // Nothing more to check if the callee is taking no arguments
2051 SmallVector<CCValAssign, 16> ArgLocs;
2052 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2053 getTargetMachine(), ArgLocs, *DAG.getContext());
2055 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2057 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2059 // If the stack arguments for this call would fit into our own save area then
2060 // the call can be made tail.
2061 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2064 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2066 MachineFrameInfo *MFI,
2067 int ClobberedFI) const {
2068 SmallVector<SDValue, 8> ArgChains;
2069 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2070 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2072 // Include the original chain at the beginning of the list. When this is
2073 // used by target LowerCall hooks, this helps legalize find the
2074 // CALLSEQ_BEGIN node.
2075 ArgChains.push_back(Chain);
2077 // Add a chain value for each stack argument corresponding
2078 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2079 UE = DAG.getEntryNode().getNode()->use_end();
2081 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2082 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2083 if (FI->getIndex() < 0) {
2084 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2085 int64_t InLastByte = InFirstByte;
2086 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2088 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2089 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2090 ArgChains.push_back(SDValue(L, 1));
2093 // Build a tokenfactor for all the chains.
2094 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2097 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2098 bool TailCallOpt) const {
2099 return CallCC == CallingConv::Fast && TailCallOpt;
2102 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2103 return CallCC == CallingConv::Fast;
2106 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2107 /// and add input and output parameter nodes.
2109 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2110 SmallVectorImpl<SDValue> &InVals) const {
2111 SelectionDAG &DAG = CLI.DAG;
2113 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2114 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2115 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2116 SDValue Chain = CLI.Chain;
2117 SDValue Callee = CLI.Callee;
2118 bool &IsTailCall = CLI.IsTailCall;
2119 CallingConv::ID CallConv = CLI.CallConv;
2120 bool IsVarArg = CLI.IsVarArg;
2122 MachineFunction &MF = DAG.getMachineFunction();
2123 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2124 bool IsThisReturn = false;
2126 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2127 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2128 bool IsSibCall = false;
2131 // Check if it's really possible to do a tail call.
2132 IsTailCall = isEligibleForTailCallOptimization(
2133 Callee, CallConv, IsVarArg, IsStructRet,
2134 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2135 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2136 report_fatal_error("failed to perform tail call elimination on a call "
2137 "site marked musttail");
2139 // A sibling call is one where we're under the usual C ABI and not planning
2140 // to change that but can still do a tail call:
2141 if (!TailCallOpt && IsTailCall)
2148 // Analyze operands of the call, assigning locations to each operand.
2149 SmallVector<CCValAssign, 16> ArgLocs;
2150 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2151 getTargetMachine(), ArgLocs, *DAG.getContext());
2154 // Handle fixed and variable vector arguments differently.
2155 // Variable vector arguments always go into memory.
2156 unsigned NumArgs = Outs.size();
2158 for (unsigned i = 0; i != NumArgs; ++i) {
2159 MVT ArgVT = Outs[i].VT;
2160 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2161 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2162 /*IsVarArg=*/ !Outs[i].IsFixed);
2163 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2164 assert(!Res && "Call operand has unhandled type");
2168 // At this point, Outs[].VT may already be promoted to i32. To correctly
2169 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2170 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2171 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2172 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2174 unsigned NumArgs = Outs.size();
2175 for (unsigned i = 0; i != NumArgs; ++i) {
2176 MVT ValVT = Outs[i].VT;
2177 // Get type of the original argument.
2178 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2179 /*AllowUnknown*/ true);
2180 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2181 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2182 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2183 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2185 else if (ActualMVT == MVT::i16)
2188 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2189 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2190 assert(!Res && "Call operand has unhandled type");
2195 // Get a count of how many bytes are to be pushed on the stack.
2196 unsigned NumBytes = CCInfo.getNextStackOffset();
2199 // Since we're not changing the ABI to make this a tail call, the memory
2200 // operands are already available in the caller's incoming argument space.
2204 // FPDiff is the byte offset of the call's argument area from the callee's.
2205 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2206 // by this amount for a tail call. In a sibling call it must be 0 because the
2207 // caller will deallocate the entire stack and the callee still expects its
2208 // arguments to begin at SP+0. Completely unused for non-tail calls.
2211 if (IsTailCall && !IsSibCall) {
2212 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2214 // Since callee will pop argument stack as a tail call, we must keep the
2215 // popped size 16-byte aligned.
2216 NumBytes = RoundUpToAlignment(NumBytes, 16);
2218 // FPDiff will be negative if this tail call requires more space than we
2219 // would automatically have in our incoming argument space. Positive if we
2220 // can actually shrink the stack.
2221 FPDiff = NumReusableBytes - NumBytes;
2223 // The stack pointer must be 16-byte aligned at all times it's used for a
2224 // memory operation, which in practice means at *all* times and in
2225 // particular across call boundaries. Therefore our own arguments started at
2226 // a 16-byte aligned SP and the delta applied for the tail call should
2227 // satisfy the same constraint.
2228 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2231 // Adjust the stack pointer for the new arguments...
2232 // These operations are automatically eliminated by the prolog/epilog pass
2235 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2237 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2239 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2240 SmallVector<SDValue, 8> MemOpChains;
2242 // Walk the register/memloc assignments, inserting copies/loads.
2243 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2244 ++i, ++realArgIdx) {
2245 CCValAssign &VA = ArgLocs[i];
2246 SDValue Arg = OutVals[realArgIdx];
2247 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2249 // Promote the value if needed.
2250 switch (VA.getLocInfo()) {
2252 llvm_unreachable("Unknown loc info!");
2253 case CCValAssign::Full:
2255 case CCValAssign::SExt:
2256 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2258 case CCValAssign::ZExt:
2259 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2261 case CCValAssign::AExt:
2262 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2263 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2264 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2265 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2267 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2269 case CCValAssign::BCvt:
2270 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2272 case CCValAssign::FPExt:
2273 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2277 if (VA.isRegLoc()) {
2278 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2279 assert(VA.getLocVT() == MVT::i64 &&
2280 "unexpected calling convention register assignment");
2281 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2282 "unexpected use of 'returned'");
2283 IsThisReturn = true;
2285 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2287 assert(VA.isMemLoc());
2290 MachinePointerInfo DstInfo;
2292 // FIXME: This works on big-endian for composite byvals, which are the
2293 // common case. It should also work for fundamental types too.
2294 uint32_t BEAlign = 0;
2295 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2296 : VA.getLocVT().getSizeInBits();
2297 OpSize = (OpSize + 7) / 8;
2298 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2300 BEAlign = 8 - OpSize;
2302 unsigned LocMemOffset = VA.getLocMemOffset();
2303 int32_t Offset = LocMemOffset + BEAlign;
2304 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2305 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2308 Offset = Offset + FPDiff;
2309 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2311 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2312 DstInfo = MachinePointerInfo::getFixedStack(FI);
2314 // Make sure any stack arguments overlapping with where we're storing
2315 // are loaded before this eventual operation. Otherwise they'll be
2317 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2319 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2321 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2322 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2325 if (Outs[i].Flags.isByVal()) {
2327 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2328 SDValue Cpy = DAG.getMemcpy(
2329 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2330 /*isVolatile = */ false,
2331 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2333 MemOpChains.push_back(Cpy);
2335 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2336 // promoted to a legal register type i32, we should truncate Arg back to
2338 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2339 VA.getValVT() == MVT::i16)
2340 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2343 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2344 MemOpChains.push_back(Store);
2349 if (!MemOpChains.empty())
2350 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2352 // Build a sequence of copy-to-reg nodes chained together with token chain
2353 // and flag operands which copy the outgoing args into the appropriate regs.
2355 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2356 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2357 RegsToPass[i].second, InFlag);
2358 InFlag = Chain.getValue(1);
2361 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2362 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2363 // node so that legalize doesn't hack it.
2364 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2365 Subtarget->isTargetMachO()) {
2366 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2367 const GlobalValue *GV = G->getGlobal();
2368 bool InternalLinkage = GV->hasInternalLinkage();
2369 if (InternalLinkage)
2370 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2372 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2374 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2376 } else if (ExternalSymbolSDNode *S =
2377 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2378 const char *Sym = S->getSymbol();
2380 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2381 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2383 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2384 const GlobalValue *GV = G->getGlobal();
2385 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2386 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2387 const char *Sym = S->getSymbol();
2388 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2391 // We don't usually want to end the call-sequence here because we would tidy
2392 // the frame up *after* the call, however in the ABI-changing tail-call case
2393 // we've carefully laid out the parameters so that when sp is reset they'll be
2394 // in the correct location.
2395 if (IsTailCall && !IsSibCall) {
2396 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2397 DAG.getIntPtrConstant(0, true), InFlag, DL);
2398 InFlag = Chain.getValue(1);
2401 std::vector<SDValue> Ops;
2402 Ops.push_back(Chain);
2403 Ops.push_back(Callee);
2406 // Each tail call may have to adjust the stack by a different amount, so
2407 // this information must travel along with the operation for eventual
2408 // consumption by emitEpilogue.
2409 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2412 // Add argument registers to the end of the list so that they are known live
2414 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2415 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2416 RegsToPass[i].second.getValueType()));
2418 // Add a register mask operand representing the call-preserved registers.
2419 const uint32_t *Mask;
2420 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2421 const AArch64RegisterInfo *ARI =
2422 static_cast<const AArch64RegisterInfo *>(TRI);
2424 // For 'this' returns, use the X0-preserving mask if applicable
2425 Mask = ARI->getThisReturnPreservedMask(CallConv);
2427 IsThisReturn = false;
2428 Mask = ARI->getCallPreservedMask(CallConv);
2431 Mask = ARI->getCallPreservedMask(CallConv);
2433 assert(Mask && "Missing call preserved mask for calling convention");
2434 Ops.push_back(DAG.getRegisterMask(Mask));
2436 if (InFlag.getNode())
2437 Ops.push_back(InFlag);
2439 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2441 // If we're doing a tall call, use a TC_RETURN here rather than an
2442 // actual call instruction.
2444 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2446 // Returns a chain and a flag for retval copy to use.
2447 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2448 InFlag = Chain.getValue(1);
2450 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2451 ? RoundUpToAlignment(NumBytes, 16)
2454 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2455 DAG.getIntPtrConstant(CalleePopBytes, true),
2458 InFlag = Chain.getValue(1);
2460 // Handle result values, copying them out of physregs into vregs that we
2462 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2463 InVals, IsThisReturn,
2464 IsThisReturn ? OutVals[0] : SDValue());
2467 bool AArch64TargetLowering::CanLowerReturn(
2468 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2469 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2470 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2471 ? RetCC_AArch64_WebKit_JS
2472 : RetCC_AArch64_AAPCS;
2473 SmallVector<CCValAssign, 16> RVLocs;
2474 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2475 return CCInfo.CheckReturn(Outs, RetCC);
2479 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2481 const SmallVectorImpl<ISD::OutputArg> &Outs,
2482 const SmallVectorImpl<SDValue> &OutVals,
2483 SDLoc DL, SelectionDAG &DAG) const {
2484 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2485 ? RetCC_AArch64_WebKit_JS
2486 : RetCC_AArch64_AAPCS;
2487 SmallVector<CCValAssign, 16> RVLocs;
2488 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2489 getTargetMachine(), RVLocs, *DAG.getContext());
2490 CCInfo.AnalyzeReturn(Outs, RetCC);
2492 // Copy the result values into the output registers.
2494 SmallVector<SDValue, 4> RetOps(1, Chain);
2495 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2496 ++i, ++realRVLocIdx) {
2497 CCValAssign &VA = RVLocs[i];
2498 assert(VA.isRegLoc() && "Can only return in registers!");
2499 SDValue Arg = OutVals[realRVLocIdx];
2501 switch (VA.getLocInfo()) {
2503 llvm_unreachable("Unknown loc info!");
2504 case CCValAssign::Full:
2505 if (Outs[i].ArgVT == MVT::i1) {
2506 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2507 // value. This is strictly redundant on Darwin (which uses "zeroext
2508 // i1"), but will be optimised out before ISel.
2509 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2510 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2513 case CCValAssign::BCvt:
2514 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2518 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2519 Flag = Chain.getValue(1);
2520 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2523 RetOps[0] = Chain; // Update chain.
2525 // Add the flag if we have it.
2527 RetOps.push_back(Flag);
2529 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2532 //===----------------------------------------------------------------------===//
2533 // Other Lowering Code
2534 //===----------------------------------------------------------------------===//
2536 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2537 SelectionDAG &DAG) const {
2538 EVT PtrVT = getPointerTy();
2540 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2541 unsigned char OpFlags =
2542 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2544 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2545 "unexpected offset in global node");
2547 // This also catched the large code model case for Darwin.
2548 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2549 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2550 // FIXME: Once remat is capable of dealing with instructions with register
2551 // operands, expand this into two nodes instead of using a wrapper node.
2552 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2555 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2556 const unsigned char MO_NC = AArch64II::MO_NC;
2558 AArch64ISD::WrapperLarge, DL, PtrVT,
2559 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2560 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2561 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2562 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2564 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2565 // the only correct model on Darwin.
2566 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2567 OpFlags | AArch64II::MO_PAGE);
2568 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2569 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2571 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2572 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2576 /// \brief Convert a TLS address reference into the correct sequence of loads
2577 /// and calls to compute the variable's address (for Darwin, currently) and
2578 /// return an SDValue containing the final node.
2580 /// Darwin only has one TLS scheme which must be capable of dealing with the
2581 /// fully general situation, in the worst case. This means:
2582 /// + "extern __thread" declaration.
2583 /// + Defined in a possibly unknown dynamic library.
2585 /// The general system is that each __thread variable has a [3 x i64] descriptor
2586 /// which contains information used by the runtime to calculate the address. The
2587 /// only part of this the compiler needs to know about is the first xword, which
2588 /// contains a function pointer that must be called with the address of the
2589 /// entire descriptor in "x0".
2591 /// Since this descriptor may be in a different unit, in general even the
2592 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2594 /// adrp x0, _var@TLVPPAGE
2595 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2596 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2597 /// ; the function pointer
2598 /// blr x1 ; Uses descriptor address in x0
2599 /// ; Address of _var is now in x0.
2601 /// If the address of _var's descriptor *is* known to the linker, then it can
2602 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2603 /// a slight efficiency gain.
2605 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2606 SelectionDAG &DAG) const {
2607 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2610 MVT PtrVT = getPointerTy();
2611 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2614 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2615 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2617 // The first entry in the descriptor is a function pointer that we must call
2618 // to obtain the address of the variable.
2619 SDValue Chain = DAG.getEntryNode();
2620 SDValue FuncTLVGet =
2621 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2622 false, true, true, 8);
2623 Chain = FuncTLVGet.getValue(1);
2625 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2626 MFI->setAdjustsStack(true);
2628 // TLS calls preserve all registers except those that absolutely must be
2629 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2631 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2632 const AArch64RegisterInfo *ARI =
2633 static_cast<const AArch64RegisterInfo *>(TRI);
2634 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2636 // Finally, we can make the call. This is just a degenerate version of a
2637 // normal AArch64 call node: x0 takes the address of the descriptor, and
2638 // returns the address of the variable in this thread.
2639 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2641 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2642 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2643 DAG.getRegisterMask(Mask), Chain.getValue(1));
2644 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2647 /// When accessing thread-local variables under either the general-dynamic or
2648 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2649 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2650 /// is a function pointer to carry out the resolution. This function takes the
2651 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2652 /// other registers (except LR, NZCV) are preserved.
2654 /// Thus, the ideal call sequence on AArch64 is:
2656 /// adrp x0, :tlsdesc:thread_var
2657 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2658 /// add x0, x0, :tlsdesc_lo12:thread_var
2659 /// .tlsdesccall thread_var
2661 /// (TPIDR_EL0 offset now in x0).
2663 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2664 /// relocation to help the linker relax this sequence if it turns out to be too
2667 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2669 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2670 SDValue DescAddr, SDLoc DL,
2671 SelectionDAG &DAG) const {
2672 EVT PtrVT = getPointerTy();
2674 // The function we need to call is simply the first entry in the GOT for this
2675 // descriptor, load it in preparation.
2676 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2678 // TLS calls preserve all registers except those that absolutely must be
2679 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2681 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2682 const AArch64RegisterInfo *ARI =
2683 static_cast<const AArch64RegisterInfo *>(TRI);
2684 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2686 // The function takes only one argument: the address of the descriptor itself
2688 SDValue Glue, Chain;
2689 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2690 Glue = Chain.getValue(1);
2692 // We're now ready to populate the argument list, as with a normal call:
2693 SmallVector<SDValue, 6> Ops;
2694 Ops.push_back(Chain);
2695 Ops.push_back(Func);
2696 Ops.push_back(SymAddr);
2697 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2698 Ops.push_back(DAG.getRegisterMask(Mask));
2699 Ops.push_back(Glue);
2701 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2702 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2703 Glue = Chain.getValue(1);
2705 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2709 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2710 SelectionDAG &DAG) const {
2711 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2712 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2713 "ELF TLS only supported in small memory model");
2714 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2716 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2719 EVT PtrVT = getPointerTy();
2721 const GlobalValue *GV = GA->getGlobal();
2723 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2725 if (Model == TLSModel::LocalExec) {
2726 SDValue HiVar = DAG.getTargetGlobalAddress(
2727 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2728 SDValue LoVar = DAG.getTargetGlobalAddress(
2730 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2732 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2733 DAG.getTargetConstant(16, MVT::i32)),
2735 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2736 DAG.getTargetConstant(0, MVT::i32)),
2738 } else if (Model == TLSModel::InitialExec) {
2739 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2740 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2741 } else if (Model == TLSModel::LocalDynamic) {
2742 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2743 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2744 // the beginning of the module's TLS region, followed by a DTPREL offset
2747 // These accesses will need deduplicating if there's more than one.
2748 AArch64FunctionInfo *MFI =
2749 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2750 MFI->incNumLocalDynamicTLSAccesses();
2752 // Accesses used in this sequence go via the TLS descriptor which lives in
2753 // the GOT. Prepare an address we can use to handle this.
2754 SDValue HiDesc = DAG.getTargetExternalSymbol(
2755 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2756 SDValue LoDesc = DAG.getTargetExternalSymbol(
2757 "_TLS_MODULE_BASE_", PtrVT,
2758 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2760 // First argument to the descriptor call is the address of the descriptor
2762 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2763 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2765 // The call needs a relocation too for linker relaxation. It doesn't make
2766 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2768 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2771 // Now we can calculate the offset from TPIDR_EL0 to this module's
2772 // thread-local area.
2773 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2775 // Now use :dtprel_whatever: operations to calculate this variable's offset
2776 // in its thread-storage area.
2777 SDValue HiVar = DAG.getTargetGlobalAddress(
2778 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2779 SDValue LoVar = DAG.getTargetGlobalAddress(
2780 GV, DL, MVT::i64, 0,
2781 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2784 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2785 DAG.getTargetConstant(16, MVT::i32)),
2788 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2789 DAG.getTargetConstant(0, MVT::i32)),
2792 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2793 } else if (Model == TLSModel::GeneralDynamic) {
2794 // Accesses used in this sequence go via the TLS descriptor which lives in
2795 // the GOT. Prepare an address we can use to handle this.
2796 SDValue HiDesc = DAG.getTargetGlobalAddress(
2797 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2798 SDValue LoDesc = DAG.getTargetGlobalAddress(
2800 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2802 // First argument to the descriptor call is the address of the descriptor
2804 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2805 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2807 // The call needs a relocation too for linker relaxation. It doesn't make
2808 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2811 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2813 // Finally we can make a call to calculate the offset from tpidr_el0.
2814 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2816 llvm_unreachable("Unsupported ELF TLS access model");
2818 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2821 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2822 SelectionDAG &DAG) const {
2823 if (Subtarget->isTargetDarwin())
2824 return LowerDarwinGlobalTLSAddress(Op, DAG);
2825 else if (Subtarget->isTargetELF())
2826 return LowerELFGlobalTLSAddress(Op, DAG);
2828 llvm_unreachable("Unexpected platform trying to use TLS");
2830 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2831 SDValue Chain = Op.getOperand(0);
2832 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2833 SDValue LHS = Op.getOperand(2);
2834 SDValue RHS = Op.getOperand(3);
2835 SDValue Dest = Op.getOperand(4);
2838 // Handle f128 first, since lowering it will result in comparing the return
2839 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2840 // is expecting to deal with.
2841 if (LHS.getValueType() == MVT::f128) {
2842 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2844 // If softenSetCCOperands returned a scalar, we need to compare the result
2845 // against zero to select between true and false values.
2846 if (!RHS.getNode()) {
2847 RHS = DAG.getConstant(0, LHS.getValueType());
2852 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2854 unsigned Opc = LHS.getOpcode();
2855 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2856 cast<ConstantSDNode>(RHS)->isOne() &&
2857 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2858 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2859 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2860 "Unexpected condition code.");
2861 // Only lower legal XALUO ops.
2862 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2865 // The actual operation with overflow check.
2866 AArch64CC::CondCode OFCC;
2867 SDValue Value, Overflow;
2868 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2870 if (CC == ISD::SETNE)
2871 OFCC = getInvertedCondCode(OFCC);
2872 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2874 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2878 if (LHS.getValueType().isInteger()) {
2879 assert((LHS.getValueType() == RHS.getValueType()) &&
2880 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2882 // If the RHS of the comparison is zero, we can potentially fold this
2883 // to a specialized branch.
2884 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2885 if (RHSC && RHSC->getZExtValue() == 0) {
2886 if (CC == ISD::SETEQ) {
2887 // See if we can use a TBZ to fold in an AND as well.
2888 // TBZ has a smaller branch displacement than CBZ. If the offset is
2889 // out of bounds, a late MI-layer pass rewrites branches.
2890 // 403.gcc is an example that hits this case.
2891 if (LHS.getOpcode() == ISD::AND &&
2892 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2893 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2894 SDValue Test = LHS.getOperand(0);
2895 uint64_t Mask = LHS.getConstantOperandVal(1);
2897 // TBZ only operates on i64's, but the ext should be free.
2898 if (Test.getValueType() == MVT::i32)
2899 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2901 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2902 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2905 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2906 } else if (CC == ISD::SETNE) {
2907 // See if we can use a TBZ to fold in an AND as well.
2908 // TBZ has a smaller branch displacement than CBZ. If the offset is
2909 // out of bounds, a late MI-layer pass rewrites branches.
2910 // 403.gcc is an example that hits this case.
2911 if (LHS.getOpcode() == ISD::AND &&
2912 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2913 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2914 SDValue Test = LHS.getOperand(0);
2915 uint64_t Mask = LHS.getConstantOperandVal(1);
2917 // TBNZ only operates on i64's, but the ext should be free.
2918 if (Test.getValueType() == MVT::i32)
2919 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2921 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2922 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2925 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2930 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2931 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2935 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2937 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2938 // clean. Some of them require two branches to implement.
2939 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2940 AArch64CC::CondCode CC1, CC2;
2941 changeFPCCToAArch64CC(CC, CC1, CC2);
2942 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2944 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2945 if (CC2 != AArch64CC::AL) {
2946 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2947 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2954 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2955 SelectionDAG &DAG) const {
2956 EVT VT = Op.getValueType();
2959 SDValue In1 = Op.getOperand(0);
2960 SDValue In2 = Op.getOperand(1);
2961 EVT SrcVT = In2.getValueType();
2963 if (SrcVT == MVT::f32 && VT == MVT::f64)
2964 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2965 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2966 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2968 // FIXME: Src type is different, bail out for now. Can VT really be a
2975 SDValue EltMask, VecVal1, VecVal2;
2976 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2979 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2981 if (!VT.isVector()) {
2982 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2983 DAG.getUNDEF(VecVT), In1);
2984 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2985 DAG.getUNDEF(VecVT), In2);
2987 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2988 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2990 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
2994 // We want to materialize a mask with the the high bit set, but the AdvSIMD
2995 // immediate moves cannot materialize that in a single instruction for
2996 // 64-bit elements. Instead, materialize zero and then negate it.
2997 EltMask = DAG.getConstant(0, EltVT);
2999 if (!VT.isVector()) {
3000 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3001 DAG.getUNDEF(VecVT), In1);
3002 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3003 DAG.getUNDEF(VecVT), In2);
3005 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3006 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3009 llvm_unreachable("Invalid type for copysign!");
3012 std::vector<SDValue> BuildVectorOps;
3013 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3014 BuildVectorOps.push_back(EltMask);
3016 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3018 // If we couldn't materialize the mask above, then the mask vector will be
3019 // the zero vector, and we need to negate it here.
3020 if (VT == MVT::f64 || VT == MVT::v2f64) {
3021 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3022 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3023 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3027 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3030 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3031 else if (VT == MVT::f64)
3032 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3034 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3037 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3038 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3039 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3042 // While there is no integer popcount instruction, it can
3043 // be more efficiently lowered to the following sequence that uses
3044 // AdvSIMD registers/instructions as long as the copies to/from
3045 // the AdvSIMD registers are cheap.
3046 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3047 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3048 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3049 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3050 SDValue Val = Op.getOperand(0);
3052 EVT VT = Op.getValueType();
3053 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3056 if (VT == MVT::i32) {
3057 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3058 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3061 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3064 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3065 SDValue UaddLV = DAG.getNode(
3066 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3067 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3070 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3074 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3076 if (Op.getValueType().isVector())
3077 return LowerVSETCC(Op, DAG);
3079 SDValue LHS = Op.getOperand(0);
3080 SDValue RHS = Op.getOperand(1);
3081 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3084 // We chose ZeroOrOneBooleanContents, so use zero and one.
3085 EVT VT = Op.getValueType();
3086 SDValue TVal = DAG.getConstant(1, VT);
3087 SDValue FVal = DAG.getConstant(0, VT);
3089 // Handle f128 first, since one possible outcome is a normal integer
3090 // comparison which gets picked up by the next if statement.
3091 if (LHS.getValueType() == MVT::f128) {
3092 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3094 // If softenSetCCOperands returned a scalar, use it.
3095 if (!RHS.getNode()) {
3096 assert(LHS.getValueType() == Op.getValueType() &&
3097 "Unexpected setcc expansion!");
3102 if (LHS.getValueType().isInteger()) {
3105 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3107 // Note that we inverted the condition above, so we reverse the order of
3108 // the true and false operands here. This will allow the setcc to be
3109 // matched to a single CSINC instruction.
3110 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3113 // Now we know we're dealing with FP values.
3114 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3116 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3117 // and do the comparison.
3118 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3120 AArch64CC::CondCode CC1, CC2;
3121 changeFPCCToAArch64CC(CC, CC1, CC2);
3122 if (CC2 == AArch64CC::AL) {
3123 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3124 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3126 // Note that we inverted the condition above, so we reverse the order of
3127 // the true and false operands here. This will allow the setcc to be
3128 // matched to a single CSINC instruction.
3129 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3131 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3132 // totally clean. Some of them require two CSELs to implement. As is in
3133 // this case, we emit the first CSEL and then emit a second using the output
3134 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3136 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3137 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3139 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3141 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3142 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3146 /// A SELECT_CC operation is really some kind of max or min if both values being
3147 /// compared are, in some sense, equal to the results in either case. However,
3148 /// it is permissible to compare f32 values and produce directly extended f64
3151 /// Extending the comparison operands would also be allowed, but is less likely
3152 /// to happen in practice since their use is right here. Note that truncate
3153 /// operations would *not* be semantically equivalent.
3154 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3158 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3159 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3160 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3161 Result.getValueType() == MVT::f64) {
3163 APFloat CmpVal = CCmp->getValueAPF();
3164 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3165 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3168 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3171 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3172 SelectionDAG &DAG) const {
3173 SDValue CC = Op->getOperand(0);
3174 SDValue TVal = Op->getOperand(1);
3175 SDValue FVal = Op->getOperand(2);
3178 unsigned Opc = CC.getOpcode();
3179 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3181 if (CC.getResNo() == 1 &&
3182 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3183 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3184 // Only lower legal XALUO ops.
3185 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3188 AArch64CC::CondCode OFCC;
3189 SDValue Value, Overflow;
3190 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3191 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3193 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3197 if (CC.getOpcode() == ISD::SETCC)
3198 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3199 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3201 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3205 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3206 SelectionDAG &DAG) const {
3207 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3208 SDValue LHS = Op.getOperand(0);
3209 SDValue RHS = Op.getOperand(1);
3210 SDValue TVal = Op.getOperand(2);
3211 SDValue FVal = Op.getOperand(3);
3214 // Handle f128 first, because it will result in a comparison of some RTLIB
3215 // call result against zero.
3216 if (LHS.getValueType() == MVT::f128) {
3217 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3219 // If softenSetCCOperands returned a scalar, we need to compare the result
3220 // against zero to select between true and false values.
3221 if (!RHS.getNode()) {
3222 RHS = DAG.getConstant(0, LHS.getValueType());
3227 // Handle integers first.
3228 if (LHS.getValueType().isInteger()) {
3229 assert((LHS.getValueType() == RHS.getValueType()) &&
3230 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3232 unsigned Opcode = AArch64ISD::CSEL;
3234 // If both the TVal and the FVal are constants, see if we can swap them in
3235 // order to for a CSINV or CSINC out of them.
3236 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3237 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3239 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3240 std::swap(TVal, FVal);
3241 std::swap(CTVal, CFVal);
3242 CC = ISD::getSetCCInverse(CC, true);
3243 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3244 std::swap(TVal, FVal);
3245 std::swap(CTVal, CFVal);
3246 CC = ISD::getSetCCInverse(CC, true);
3247 } else if (TVal.getOpcode() == ISD::XOR) {
3248 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3249 // with a CSINV rather than a CSEL.
3250 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3252 if (CVal && CVal->isAllOnesValue()) {
3253 std::swap(TVal, FVal);
3254 std::swap(CTVal, CFVal);
3255 CC = ISD::getSetCCInverse(CC, true);
3257 } else if (TVal.getOpcode() == ISD::SUB) {
3258 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3259 // that we can match with a CSNEG rather than a CSEL.
3260 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3262 if (CVal && CVal->isNullValue()) {
3263 std::swap(TVal, FVal);
3264 std::swap(CTVal, CFVal);
3265 CC = ISD::getSetCCInverse(CC, true);
3267 } else if (CTVal && CFVal) {
3268 const int64_t TrueVal = CTVal->getSExtValue();
3269 const int64_t FalseVal = CFVal->getSExtValue();
3272 // If both TVal and FVal are constants, see if FVal is the
3273 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3274 // instead of a CSEL in that case.
3275 if (TrueVal == ~FalseVal) {
3276 Opcode = AArch64ISD::CSINV;
3277 } else if (TrueVal == -FalseVal) {
3278 Opcode = AArch64ISD::CSNEG;
3279 } else if (TVal.getValueType() == MVT::i32) {
3280 // If our operands are only 32-bit wide, make sure we use 32-bit
3281 // arithmetic for the check whether we can use CSINC. This ensures that
3282 // the addition in the check will wrap around properly in case there is
3283 // an overflow (which would not be the case if we do the check with
3284 // 64-bit arithmetic).
3285 const uint32_t TrueVal32 = CTVal->getZExtValue();
3286 const uint32_t FalseVal32 = CFVal->getZExtValue();
3288 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3289 Opcode = AArch64ISD::CSINC;
3291 if (TrueVal32 > FalseVal32) {
3295 // 64-bit check whether we can use CSINC.
3296 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3297 Opcode = AArch64ISD::CSINC;
3299 if (TrueVal > FalseVal) {
3304 // Swap TVal and FVal if necessary.
3306 std::swap(TVal, FVal);
3307 std::swap(CTVal, CFVal);
3308 CC = ISD::getSetCCInverse(CC, true);
3311 if (Opcode != AArch64ISD::CSEL) {
3312 // Drop FVal since we can get its value by simply inverting/negating
3319 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3321 EVT VT = Op.getValueType();
3322 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3325 // Now we know we're dealing with FP values.
3326 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3327 assert(LHS.getValueType() == RHS.getValueType());
3328 EVT VT = Op.getValueType();
3330 // Try to match this select into a max/min operation, which have dedicated
3331 // opcode in the instruction set.
3332 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3334 if (getTargetMachine().Options.NoNaNsFPMath) {
3335 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3336 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3337 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3338 CC = ISD::getSetCCSwappedOperands(CC);
3339 std::swap(MinMaxLHS, MinMaxRHS);
3342 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3343 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3353 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3361 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3367 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3368 // and do the comparison.
3369 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3371 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3372 // clean. Some of them require two CSELs to implement.
3373 AArch64CC::CondCode CC1, CC2;
3374 changeFPCCToAArch64CC(CC, CC1, CC2);
3375 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3376 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3378 // If we need a second CSEL, emit it, using the output of the first as the
3379 // RHS. We're effectively OR'ing the two CC's together.
3380 if (CC2 != AArch64CC::AL) {
3381 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3382 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3385 // Otherwise, return the output of the first CSEL.
3389 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3390 SelectionDAG &DAG) const {
3391 // Jump table entries as PC relative offsets. No additional tweaking
3392 // is necessary here. Just get the address of the jump table.
3393 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3394 EVT PtrVT = getPointerTy();
3397 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3398 !Subtarget->isTargetMachO()) {
3399 const unsigned char MO_NC = AArch64II::MO_NC;
3401 AArch64ISD::WrapperLarge, DL, PtrVT,
3402 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3403 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3404 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3405 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3406 AArch64II::MO_G0 | MO_NC));
3410 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3411 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3412 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3413 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3414 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3417 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3418 SelectionDAG &DAG) const {
3419 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3420 EVT PtrVT = getPointerTy();
3423 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3424 // Use the GOT for the large code model on iOS.
3425 if (Subtarget->isTargetMachO()) {
3426 SDValue GotAddr = DAG.getTargetConstantPool(
3427 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3429 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3432 const unsigned char MO_NC = AArch64II::MO_NC;
3434 AArch64ISD::WrapperLarge, DL, PtrVT,
3435 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3436 CP->getOffset(), AArch64II::MO_G3),
3437 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3438 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3439 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3440 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3441 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3442 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3444 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3445 // ELF, the only valid one on Darwin.
3447 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3448 CP->getOffset(), AArch64II::MO_PAGE);
3449 SDValue Lo = DAG.getTargetConstantPool(
3450 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3451 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3453 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3454 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3458 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3459 SelectionDAG &DAG) const {
3460 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3461 EVT PtrVT = getPointerTy();
3463 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3464 !Subtarget->isTargetMachO()) {
3465 const unsigned char MO_NC = AArch64II::MO_NC;
3467 AArch64ISD::WrapperLarge, DL, PtrVT,
3468 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3469 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3470 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3471 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3473 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3474 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3476 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3477 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3481 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3482 SelectionDAG &DAG) const {
3483 AArch64FunctionInfo *FuncInfo =
3484 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3488 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3489 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3490 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3491 MachinePointerInfo(SV), false, false, 0);
3494 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3495 SelectionDAG &DAG) const {
3496 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3497 // Standard, section B.3.
3498 MachineFunction &MF = DAG.getMachineFunction();
3499 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3502 SDValue Chain = Op.getOperand(0);
3503 SDValue VAList = Op.getOperand(1);
3504 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3505 SmallVector<SDValue, 4> MemOps;
3507 // void *__stack at offset 0
3509 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3510 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3511 MachinePointerInfo(SV), false, false, 8));
3513 // void *__gr_top at offset 8
3514 int GPRSize = FuncInfo->getVarArgsGPRSize();
3516 SDValue GRTop, GRTopAddr;
3518 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3519 DAG.getConstant(8, getPointerTy()));
3521 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3522 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3523 DAG.getConstant(GPRSize, getPointerTy()));
3525 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3526 MachinePointerInfo(SV, 8), false, false, 8));
3529 // void *__vr_top at offset 16
3530 int FPRSize = FuncInfo->getVarArgsFPRSize();
3532 SDValue VRTop, VRTopAddr;
3533 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3534 DAG.getConstant(16, getPointerTy()));
3536 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3537 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3538 DAG.getConstant(FPRSize, getPointerTy()));
3540 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3541 MachinePointerInfo(SV, 16), false, false, 8));
3544 // int __gr_offs at offset 24
3545 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3546 DAG.getConstant(24, getPointerTy()));
3547 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3548 GROffsAddr, MachinePointerInfo(SV, 24), false,
3551 // int __vr_offs at offset 28
3552 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3553 DAG.getConstant(28, getPointerTy()));
3554 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3555 VROffsAddr, MachinePointerInfo(SV, 28), false,
3558 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3561 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3562 SelectionDAG &DAG) const {
3563 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3564 : LowerAAPCS_VASTART(Op, DAG);
3567 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3568 SelectionDAG &DAG) const {
3569 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3571 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3572 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3573 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3575 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3576 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3577 8, false, false, MachinePointerInfo(DestSV),
3578 MachinePointerInfo(SrcSV));
3581 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3582 assert(Subtarget->isTargetDarwin() &&
3583 "automatic va_arg instruction only works on Darwin");
3585 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3586 EVT VT = Op.getValueType();
3588 SDValue Chain = Op.getOperand(0);
3589 SDValue Addr = Op.getOperand(1);
3590 unsigned Align = Op.getConstantOperandVal(3);
3592 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3593 MachinePointerInfo(V), false, false, false, 0);
3594 Chain = VAList.getValue(1);
3597 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3598 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3599 DAG.getConstant(Align - 1, getPointerTy()));
3600 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3601 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3604 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3605 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3607 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3608 // up to 64 bits. At the very least, we have to increase the striding of the
3609 // vaargs list to match this, and for FP values we need to introduce
3610 // FP_ROUND nodes as well.
3611 if (VT.isInteger() && !VT.isVector())
3613 bool NeedFPTrunc = false;
3614 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3619 // Increment the pointer, VAList, to the next vaarg
3620 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3621 DAG.getConstant(ArgSize, getPointerTy()));
3622 // Store the incremented VAList to the legalized pointer
3623 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3626 // Load the actual argument out of the pointer VAList
3628 // Load the value as an f64.
3629 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3630 MachinePointerInfo(), false, false, false, 0);
3631 // Round the value down to an f32.
3632 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3633 DAG.getIntPtrConstant(1));
3634 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3635 // Merge the rounded value with the chain output of the load.
3636 return DAG.getMergeValues(Ops, DL);
3639 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3643 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3644 SelectionDAG &DAG) const {
3645 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3646 MFI->setFrameAddressIsTaken(true);
3648 EVT VT = Op.getValueType();
3650 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3652 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3654 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3655 MachinePointerInfo(), false, false, false, 0);
3659 // FIXME? Maybe this could be a TableGen attribute on some registers and
3660 // this table could be generated automatically from RegInfo.
3661 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3663 unsigned Reg = StringSwitch<unsigned>(RegName)
3664 .Case("sp", AArch64::SP)
3668 report_fatal_error("Invalid register name global variable");
3671 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3672 SelectionDAG &DAG) const {
3673 MachineFunction &MF = DAG.getMachineFunction();
3674 MachineFrameInfo *MFI = MF.getFrameInfo();
3675 MFI->setReturnAddressIsTaken(true);
3677 EVT VT = Op.getValueType();
3679 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3681 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3682 SDValue Offset = DAG.getConstant(8, getPointerTy());
3683 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3684 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3685 MachinePointerInfo(), false, false, false, 0);
3688 // Return LR, which contains the return address. Mark it an implicit live-in.
3689 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3690 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3693 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3694 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3695 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3696 SelectionDAG &DAG) const {
3697 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3698 EVT VT = Op.getValueType();
3699 unsigned VTBits = VT.getSizeInBits();
3701 SDValue ShOpLo = Op.getOperand(0);
3702 SDValue ShOpHi = Op.getOperand(1);
3703 SDValue ShAmt = Op.getOperand(2);
3705 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3707 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3709 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3710 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3711 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3712 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3713 DAG.getConstant(VTBits, MVT::i64));
3714 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3716 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3717 ISD::SETGE, dl, DAG);
3718 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3720 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3721 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3723 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3725 // AArch64 shifts larger than the register width are wrapped rather than
3726 // clamped, so we can't just emit "hi >> x".
3727 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3728 SDValue TrueValHi = Opc == ISD::SRA
3729 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3730 DAG.getConstant(VTBits - 1, MVT::i64))
3731 : DAG.getConstant(0, VT);
3733 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3735 SDValue Ops[2] = { Lo, Hi };
3736 return DAG.getMergeValues(Ops, dl);
3739 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3740 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3741 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3742 SelectionDAG &DAG) const {
3743 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3744 EVT VT = Op.getValueType();
3745 unsigned VTBits = VT.getSizeInBits();
3747 SDValue ShOpLo = Op.getOperand(0);
3748 SDValue ShOpHi = Op.getOperand(1);
3749 SDValue ShAmt = Op.getOperand(2);
3752 assert(Op.getOpcode() == ISD::SHL_PARTS);
3753 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3754 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3755 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3756 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3757 DAG.getConstant(VTBits, MVT::i64));
3758 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3759 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3761 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3763 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3764 ISD::SETGE, dl, DAG);
3765 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3767 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3769 // AArch64 shifts of larger than register sizes are wrapped rather than
3770 // clamped, so we can't just emit "lo << a" if a is too big.
3771 SDValue TrueValLo = DAG.getConstant(0, VT);
3772 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3774 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3776 SDValue Ops[2] = { Lo, Hi };
3777 return DAG.getMergeValues(Ops, dl);
3780 bool AArch64TargetLowering::isOffsetFoldingLegal(
3781 const GlobalAddressSDNode *GA) const {
3782 // The AArch64 target doesn't support folding offsets into global addresses.
3786 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3787 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3788 // FIXME: We should be able to handle f128 as well with a clever lowering.
3789 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3793 return AArch64_AM::getFP64Imm(Imm) != -1;
3794 else if (VT == MVT::f32)
3795 return AArch64_AM::getFP32Imm(Imm) != -1;
3799 //===----------------------------------------------------------------------===//
3800 // AArch64 Optimization Hooks
3801 //===----------------------------------------------------------------------===//
3803 //===----------------------------------------------------------------------===//
3804 // AArch64 Inline Assembly Support
3805 //===----------------------------------------------------------------------===//
3807 // Table of Constraints
3808 // TODO: This is the current set of constraints supported by ARM for the
3809 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3811 // r - A general register
3812 // w - An FP/SIMD register of some size in the range v0-v31
3813 // x - An FP/SIMD register of some size in the range v0-v15
3814 // I - Constant that can be used with an ADD instruction
3815 // J - Constant that can be used with a SUB instruction
3816 // K - Constant that can be used with a 32-bit logical instruction
3817 // L - Constant that can be used with a 64-bit logical instruction
3818 // M - Constant that can be used as a 32-bit MOV immediate
3819 // N - Constant that can be used as a 64-bit MOV immediate
3820 // Q - A memory reference with base register and no offset
3821 // S - A symbolic address
3822 // Y - Floating point constant zero
3823 // Z - Integer constant zero
3825 // Note that general register operands will be output using their 64-bit x
3826 // register name, whatever the size of the variable, unless the asm operand
3827 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3828 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3831 /// getConstraintType - Given a constraint letter, return the type of
3832 /// constraint it is for this target.
3833 AArch64TargetLowering::ConstraintType
3834 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3835 if (Constraint.size() == 1) {
3836 switch (Constraint[0]) {
3843 return C_RegisterClass;
3844 // An address with a single base register. Due to the way we
3845 // currently handle addresses it is the same as 'r'.
3850 return TargetLowering::getConstraintType(Constraint);
3853 /// Examine constraint type and operand type and determine a weight value.
3854 /// This object must already have been set up with the operand type
3855 /// and the current alternative constraint selected.
3856 TargetLowering::ConstraintWeight
3857 AArch64TargetLowering::getSingleConstraintMatchWeight(
3858 AsmOperandInfo &info, const char *constraint) const {
3859 ConstraintWeight weight = CW_Invalid;
3860 Value *CallOperandVal = info.CallOperandVal;
3861 // If we don't have a value, we can't do a match,
3862 // but allow it at the lowest weight.
3863 if (!CallOperandVal)
3865 Type *type = CallOperandVal->getType();
3866 // Look at the constraint type.
3867 switch (*constraint) {
3869 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3873 if (type->isFloatingPointTy() || type->isVectorTy())
3874 weight = CW_Register;
3877 weight = CW_Constant;
3883 std::pair<unsigned, const TargetRegisterClass *>
3884 AArch64TargetLowering::getRegForInlineAsmConstraint(
3885 const std::string &Constraint, MVT VT) const {
3886 if (Constraint.size() == 1) {
3887 switch (Constraint[0]) {
3889 if (VT.getSizeInBits() == 64)
3890 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3891 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3894 return std::make_pair(0U, &AArch64::FPR32RegClass);
3895 if (VT.getSizeInBits() == 64)
3896 return std::make_pair(0U, &AArch64::FPR64RegClass);
3897 if (VT.getSizeInBits() == 128)
3898 return std::make_pair(0U, &AArch64::FPR128RegClass);
3900 // The instructions that this constraint is designed for can
3901 // only take 128-bit registers so just use that regclass.
3903 if (VT.getSizeInBits() == 128)
3904 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3908 if (StringRef("{cc}").equals_lower(Constraint))
3909 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3911 // Use the default implementation in TargetLowering to convert the register
3912 // constraint into a member of a register class.
3913 std::pair<unsigned, const TargetRegisterClass *> Res;
3914 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3916 // Not found as a standard register?
3918 unsigned Size = Constraint.size();
3919 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3920 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3921 const std::string Reg =
3922 std::string(&Constraint[2], &Constraint[Size - 1]);
3923 int RegNo = atoi(Reg.c_str());
3924 if (RegNo >= 0 && RegNo <= 31) {
3925 // v0 - v31 are aliases of q0 - q31.
3926 // By default we'll emit v0-v31 for this unless there's a modifier where
3927 // we'll emit the correct register as well.
3928 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3929 Res.second = &AArch64::FPR128RegClass;
3937 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3938 /// vector. If it is invalid, don't add anything to Ops.
3939 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3940 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3941 SelectionDAG &DAG) const {
3944 // Currently only support length 1 constraints.
3945 if (Constraint.length() != 1)
3948 char ConstraintLetter = Constraint[0];
3949 switch (ConstraintLetter) {
3953 // This set of constraints deal with valid constants for various instructions.
3954 // Validate and return a target constant for them if we can.
3956 // 'z' maps to xzr or wzr so it needs an input of 0.
3957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3958 if (!C || C->getZExtValue() != 0)
3961 if (Op.getValueType() == MVT::i64)
3962 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3964 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3974 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3978 // Grab the value and do some validation.
3979 uint64_t CVal = C->getZExtValue();
3980 switch (ConstraintLetter) {
3981 // The I constraint applies only to simple ADD or SUB immediate operands:
3982 // i.e. 0 to 4095 with optional shift by 12
3983 // The J constraint applies only to ADD or SUB immediates that would be
3984 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3985 // instruction [or vice versa], in other words -1 to -4095 with optional
3986 // left shift by 12.
3988 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
3992 uint64_t NVal = -C->getSExtValue();
3993 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
3997 // The K and L constraints apply *only* to logical immediates, including
3998 // what used to be the MOVI alias for ORR (though the MOVI alias has now
3999 // been removed and MOV should be used). So these constraints have to
4000 // distinguish between bit patterns that are valid 32-bit or 64-bit
4001 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4002 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4005 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4009 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4012 // The M and N constraints are a superset of K and L respectively, for use
4013 // with the MOV (immediate) alias. As well as the logical immediates they
4014 // also match 32 or 64-bit immediates that can be loaded either using a
4015 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4016 // (M) or 64-bit 0x1234000000000000 (N) etc.
4017 // As a note some of this code is liberally stolen from the asm parser.
4019 if (!isUInt<32>(CVal))
4021 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4023 if ((CVal & 0xFFFF) == CVal)
4025 if ((CVal & 0xFFFF0000ULL) == CVal)
4027 uint64_t NCVal = ~(uint32_t)CVal;
4028 if ((NCVal & 0xFFFFULL) == NCVal)
4030 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4035 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4037 if ((CVal & 0xFFFFULL) == CVal)
4039 if ((CVal & 0xFFFF0000ULL) == CVal)
4041 if ((CVal & 0xFFFF00000000ULL) == CVal)
4043 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4045 uint64_t NCVal = ~CVal;
4046 if ((NCVal & 0xFFFFULL) == NCVal)
4048 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4050 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4052 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4060 // All assembler immediates are 64-bit integers.
4061 Result = DAG.getTargetConstant(CVal, MVT::i64);
4065 if (Result.getNode()) {
4066 Ops.push_back(Result);
4070 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4073 //===----------------------------------------------------------------------===//
4074 // AArch64 Advanced SIMD Support
4075 //===----------------------------------------------------------------------===//
4077 /// WidenVector - Given a value in the V64 register class, produce the
4078 /// equivalent value in the V128 register class.
4079 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4080 EVT VT = V64Reg.getValueType();
4081 unsigned NarrowSize = VT.getVectorNumElements();
4082 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4083 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4086 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4087 V64Reg, DAG.getConstant(0, MVT::i32));
4090 /// getExtFactor - Determine the adjustment factor for the position when
4091 /// generating an "extract from vector registers" instruction.
4092 static unsigned getExtFactor(SDValue &V) {
4093 EVT EltType = V.getValueType().getVectorElementType();
4094 return EltType.getSizeInBits() / 8;
4097 /// NarrowVector - Given a value in the V128 register class, produce the
4098 /// equivalent value in the V64 register class.
4099 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4100 EVT VT = V128Reg.getValueType();
4101 unsigned WideSize = VT.getVectorNumElements();
4102 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4103 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4106 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4109 // Gather data to see if the operation can be modelled as a
4110 // shuffle in combination with VEXTs.
4111 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4112 SelectionDAG &DAG) const {
4113 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4115 EVT VT = Op.getValueType();
4116 unsigned NumElts = VT.getVectorNumElements();
4118 SmallVector<SDValue, 2> SourceVecs;
4119 SmallVector<unsigned, 2> MinElts;
4120 SmallVector<unsigned, 2> MaxElts;
4122 for (unsigned i = 0; i < NumElts; ++i) {
4123 SDValue V = Op.getOperand(i);
4124 if (V.getOpcode() == ISD::UNDEF)
4126 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4127 // A shuffle can only come from building a vector from various
4128 // elements of other vectors.
4132 // Record this extraction against the appropriate vector if possible...
4133 SDValue SourceVec = V.getOperand(0);
4134 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4135 bool FoundSource = false;
4136 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4137 if (SourceVecs[j] == SourceVec) {
4138 if (MinElts[j] > EltNo)
4140 if (MaxElts[j] < EltNo)
4147 // Or record a new source if not...
4149 SourceVecs.push_back(SourceVec);
4150 MinElts.push_back(EltNo);
4151 MaxElts.push_back(EltNo);
4155 // Currently only do something sane when at most two source vectors
4157 if (SourceVecs.size() > 2)
4160 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4161 int VEXTOffsets[2] = { 0, 0 };
4162 int OffsetMultipliers[2] = { 1, 1 };
4164 // This loop extracts the usage patterns of the source vectors
4165 // and prepares appropriate SDValues for a shuffle if possible.
4166 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4167 unsigned NumSrcElts = SourceVecs[i].getValueType().getVectorNumElements();
4168 SDValue CurSource = SourceVecs[i];
4169 if (SourceVecs[i].getValueType().getVectorElementType() !=
4170 VT.getVectorElementType()) {
4171 // It may hit this case if SourceVecs[i] is AssertSext/AssertZext.
4172 // Then bitcast it to the vector which holds asserted element type,
4173 // and record the multiplier of element width between SourceVecs and
4174 // Build_vector which is needed to extract the correct lanes later.
4176 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4177 SourceVecs[i].getValueSizeInBits() /
4178 VT.getVectorElementType().getSizeInBits());
4180 CurSource = DAG.getNode(ISD::BITCAST, dl, CastVT, SourceVecs[i]);
4181 OffsetMultipliers[i] = CastVT.getVectorNumElements() / NumSrcElts;
4182 NumSrcElts *= OffsetMultipliers[i];
4183 MaxElts[i] *= OffsetMultipliers[i];
4184 MinElts[i] *= OffsetMultipliers[i];
4187 if (CurSource.getValueType() == VT) {
4188 // No VEXT necessary
4189 ShuffleSrcs[i] = CurSource;
4192 } else if (NumSrcElts < NumElts) {
4193 // We can pad out the smaller vector for free, so if it's part of a
4195 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, CurSource,
4196 DAG.getUNDEF(CurSource.getValueType()));
4200 // Since only 64-bit and 128-bit vectors are legal on ARM and
4201 // we've eliminated the other cases...
4202 assert(NumSrcElts == 2 * NumElts &&
4203 "unexpected vector sizes in ReconstructShuffle");
4205 if (MaxElts[i] - MinElts[i] >= NumElts) {
4206 // Span too large for a VEXT to cope
4210 if (MinElts[i] >= NumElts) {
4211 // The extraction can just take the second half
4212 VEXTOffsets[i] = NumElts;
4213 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4214 DAG.getIntPtrConstant(NumElts));
4215 } else if (MaxElts[i] < NumElts) {
4216 // The extraction can just take the first half
4218 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4219 DAG.getIntPtrConstant(0));
4221 // An actual VEXT is needed
4222 VEXTOffsets[i] = MinElts[i];
4223 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4224 DAG.getIntPtrConstant(0));
4225 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4226 DAG.getIntPtrConstant(NumElts));
4227 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4228 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4229 DAG.getConstant(Imm, MVT::i32));
4233 SmallVector<int, 8> Mask;
4235 for (unsigned i = 0; i < NumElts; ++i) {
4236 SDValue Entry = Op.getOperand(i);
4237 if (Entry.getOpcode() == ISD::UNDEF) {
4242 SDValue ExtractVec = Entry.getOperand(0);
4244 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4245 if (ExtractVec == SourceVecs[0]) {
4246 Mask.push_back(ExtractElt * OffsetMultipliers[0] - VEXTOffsets[0]);
4248 Mask.push_back(ExtractElt * OffsetMultipliers[1] + NumElts -
4253 // Final check before we try to produce nonsense...
4254 if (isShuffleMaskLegal(Mask, VT))
4255 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4261 // check if an EXT instruction can handle the shuffle mask when the
4262 // vector sources of the shuffle are the same.
4263 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4264 unsigned NumElts = VT.getVectorNumElements();
4266 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4272 // If this is a VEXT shuffle, the immediate value is the index of the first
4273 // element. The other shuffle indices must be the successive elements after
4275 unsigned ExpectedElt = Imm;
4276 for (unsigned i = 1; i < NumElts; ++i) {
4277 // Increment the expected index. If it wraps around, just follow it
4278 // back to index zero and keep going.
4280 if (ExpectedElt == NumElts)
4284 continue; // ignore UNDEF indices
4285 if (ExpectedElt != static_cast<unsigned>(M[i]))
4292 // check if an EXT instruction can handle the shuffle mask when the
4293 // vector sources of the shuffle are different.
4294 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4296 // Look for the first non-undef element.
4297 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4298 [](int Elt) {return Elt >= 0;});
4300 // Benefit form APInt to handle overflow when calculating expected element.
4301 unsigned NumElts = VT.getVectorNumElements();
4302 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4303 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4304 // The following shuffle indices must be the successive elements after the
4305 // first real element.
4306 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4307 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4308 if (FirstWrongElt != M.end())
4311 // The index of an EXT is the first element if it is not UNDEF.
4312 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4313 // value of the first element. E.g.
4314 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4315 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4316 // ExpectedElt is the last mask index plus 1.
4317 Imm = ExpectedElt.getZExtValue();
4319 // There are two difference cases requiring to reverse input vectors.
4320 // For example, for vector <4 x i32> we have the following cases,
4321 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4322 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4323 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4324 // to reverse two input vectors.
4333 /// isREVMask - Check if a vector shuffle corresponds to a REV
4334 /// instruction with the specified blocksize. (The order of the elements
4335 /// within each block of the vector is reversed.)
4336 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4337 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4338 "Only possible block sizes for REV are: 16, 32, 64");
4340 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4344 unsigned NumElts = VT.getVectorNumElements();
4345 unsigned BlockElts = M[0] + 1;
4346 // If the first shuffle index is UNDEF, be optimistic.
4348 BlockElts = BlockSize / EltSz;
4350 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4353 for (unsigned i = 0; i < NumElts; ++i) {
4355 continue; // ignore UNDEF indices
4356 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4363 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4364 unsigned NumElts = VT.getVectorNumElements();
4365 WhichResult = (M[0] == 0 ? 0 : 1);
4366 unsigned Idx = WhichResult * NumElts / 2;
4367 for (unsigned i = 0; i != NumElts; i += 2) {
4368 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4369 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4377 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4378 unsigned NumElts = VT.getVectorNumElements();
4379 WhichResult = (M[0] == 0 ? 0 : 1);
4380 for (unsigned i = 0; i != NumElts; ++i) {
4382 continue; // ignore UNDEF indices
4383 if ((unsigned)M[i] != 2 * i + WhichResult)
4390 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4391 unsigned NumElts = VT.getVectorNumElements();
4392 WhichResult = (M[0] == 0 ? 0 : 1);
4393 for (unsigned i = 0; i < NumElts; i += 2) {
4394 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4395 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4401 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4402 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4403 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4404 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4405 unsigned NumElts = VT.getVectorNumElements();
4406 WhichResult = (M[0] == 0 ? 0 : 1);
4407 unsigned Idx = WhichResult * NumElts / 2;
4408 for (unsigned i = 0; i != NumElts; i += 2) {
4409 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4410 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4418 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4419 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4420 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4421 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4422 unsigned Half = VT.getVectorNumElements() / 2;
4423 WhichResult = (M[0] == 0 ? 0 : 1);
4424 for (unsigned j = 0; j != 2; ++j) {
4425 unsigned Idx = WhichResult;
4426 for (unsigned i = 0; i != Half; ++i) {
4427 int MIdx = M[i + j * Half];
4428 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4437 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4438 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4439 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4440 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4441 unsigned NumElts = VT.getVectorNumElements();
4442 WhichResult = (M[0] == 0 ? 0 : 1);
4443 for (unsigned i = 0; i < NumElts; i += 2) {
4444 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4445 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4451 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4452 bool &DstIsLeft, int &Anomaly) {
4453 if (M.size() != static_cast<size_t>(NumInputElements))
4456 int NumLHSMatch = 0, NumRHSMatch = 0;
4457 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4459 for (int i = 0; i < NumInputElements; ++i) {
4469 LastLHSMismatch = i;
4471 if (M[i] == i + NumInputElements)
4474 LastRHSMismatch = i;
4477 if (NumLHSMatch == NumInputElements - 1) {
4479 Anomaly = LastLHSMismatch;
4481 } else if (NumRHSMatch == NumInputElements - 1) {
4483 Anomaly = LastRHSMismatch;
4490 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4491 if (VT.getSizeInBits() != 128)
4494 unsigned NumElts = VT.getVectorNumElements();
4496 for (int I = 0, E = NumElts / 2; I != E; I++) {
4501 int Offset = NumElts / 2;
4502 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4503 if (Mask[I] != I + SplitLHS * Offset)
4510 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4512 EVT VT = Op.getValueType();
4513 SDValue V0 = Op.getOperand(0);
4514 SDValue V1 = Op.getOperand(1);
4515 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4517 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4518 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4521 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4523 if (!isConcatMask(Mask, VT, SplitV0))
4526 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4527 VT.getVectorNumElements() / 2);
4529 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4530 DAG.getConstant(0, MVT::i64));
4532 if (V1.getValueType().getSizeInBits() == 128) {
4533 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4534 DAG.getConstant(0, MVT::i64));
4536 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4539 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4540 /// the specified operations to build the shuffle.
4541 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4542 SDValue RHS, SelectionDAG &DAG,
4544 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4545 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4546 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4549 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4558 OP_VUZPL, // VUZP, left result
4559 OP_VUZPR, // VUZP, right result
4560 OP_VZIPL, // VZIP, left result
4561 OP_VZIPR, // VZIP, right result
4562 OP_VTRNL, // VTRN, left result
4563 OP_VTRNR // VTRN, right result
4566 if (OpNum == OP_COPY) {
4567 if (LHSID == (1 * 9 + 2) * 9 + 3)
4569 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4573 SDValue OpLHS, OpRHS;
4574 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4575 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4576 EVT VT = OpLHS.getValueType();
4580 llvm_unreachable("Unknown shuffle opcode!");
4582 // VREV divides the vector in half and swaps within the half.
4583 if (VT.getVectorElementType() == MVT::i32 ||
4584 VT.getVectorElementType() == MVT::f32)
4585 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4586 // vrev <4 x i16> -> REV32
4587 if (VT.getVectorElementType() == MVT::i16)
4588 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4589 // vrev <4 x i8> -> REV16
4590 assert(VT.getVectorElementType() == MVT::i8);
4591 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4596 EVT EltTy = VT.getVectorElementType();
4598 if (EltTy == MVT::i8)
4599 Opcode = AArch64ISD::DUPLANE8;
4600 else if (EltTy == MVT::i16)
4601 Opcode = AArch64ISD::DUPLANE16;
4602 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4603 Opcode = AArch64ISD::DUPLANE32;
4604 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4605 Opcode = AArch64ISD::DUPLANE64;
4607 llvm_unreachable("Invalid vector element type?");
4609 if (VT.getSizeInBits() == 64)
4610 OpLHS = WidenVector(OpLHS, DAG);
4611 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4612 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4617 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4618 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4619 DAG.getConstant(Imm, MVT::i32));
4622 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4625 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4628 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4631 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4634 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4637 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4642 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4643 SelectionDAG &DAG) {
4644 // Check to see if we can use the TBL instruction.
4645 SDValue V1 = Op.getOperand(0);
4646 SDValue V2 = Op.getOperand(1);
4649 EVT EltVT = Op.getValueType().getVectorElementType();
4650 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4652 SmallVector<SDValue, 8> TBLMask;
4653 for (int Val : ShuffleMask) {
4654 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4655 unsigned Offset = Byte + Val * BytesPerElt;
4656 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4660 MVT IndexVT = MVT::v8i8;
4661 unsigned IndexLen = 8;
4662 if (Op.getValueType().getSizeInBits() == 128) {
4663 IndexVT = MVT::v16i8;
4667 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4668 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4671 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4673 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4674 Shuffle = DAG.getNode(
4675 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4676 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4677 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4678 makeArrayRef(TBLMask.data(), IndexLen)));
4680 if (IndexLen == 8) {
4681 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4682 Shuffle = DAG.getNode(
4683 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4684 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4685 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4686 makeArrayRef(TBLMask.data(), IndexLen)));
4688 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4689 // cannot currently represent the register constraints on the input
4691 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4692 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4693 // &TBLMask[0], IndexLen));
4694 Shuffle = DAG.getNode(
4695 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4696 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4697 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4698 makeArrayRef(TBLMask.data(), IndexLen)));
4701 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4704 static unsigned getDUPLANEOp(EVT EltType) {
4705 if (EltType == MVT::i8)
4706 return AArch64ISD::DUPLANE8;
4707 if (EltType == MVT::i16)
4708 return AArch64ISD::DUPLANE16;
4709 if (EltType == MVT::i32 || EltType == MVT::f32)
4710 return AArch64ISD::DUPLANE32;
4711 if (EltType == MVT::i64 || EltType == MVT::f64)
4712 return AArch64ISD::DUPLANE64;
4714 llvm_unreachable("Invalid vector element type?");
4717 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4718 SelectionDAG &DAG) const {
4720 EVT VT = Op.getValueType();
4722 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4724 // Convert shuffles that are directly supported on NEON to target-specific
4725 // DAG nodes, instead of keeping them as shuffles and matching them again
4726 // during code selection. This is more efficient and avoids the possibility
4727 // of inconsistencies between legalization and selection.
4728 ArrayRef<int> ShuffleMask = SVN->getMask();
4730 SDValue V1 = Op.getOperand(0);
4731 SDValue V2 = Op.getOperand(1);
4733 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4734 V1.getValueType().getSimpleVT())) {
4735 int Lane = SVN->getSplatIndex();
4736 // If this is undef splat, generate it via "just" vdup, if possible.
4740 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4741 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4743 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4744 // constant. If so, we can just reference the lane's definition directly.
4745 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4746 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4747 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4749 // Otherwise, duplicate from the lane of the input vector.
4750 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4752 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4753 // to make a vector of the same size as this SHUFFLE. We can ignore the
4754 // extract entirely, and canonicalise the concat using WidenVector.
4755 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4756 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4757 V1 = V1.getOperand(0);
4758 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4759 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4760 Lane -= Idx * VT.getVectorNumElements() / 2;
4761 V1 = WidenVector(V1.getOperand(Idx), DAG);
4762 } else if (VT.getSizeInBits() == 64)
4763 V1 = WidenVector(V1, DAG);
4765 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4768 if (isREVMask(ShuffleMask, VT, 64))
4769 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4770 if (isREVMask(ShuffleMask, VT, 32))
4771 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4772 if (isREVMask(ShuffleMask, VT, 16))
4773 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4775 bool ReverseEXT = false;
4777 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4780 Imm *= getExtFactor(V1);
4781 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4782 DAG.getConstant(Imm, MVT::i32));
4783 } else if (V2->getOpcode() == ISD::UNDEF &&
4784 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4785 Imm *= getExtFactor(V1);
4786 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4787 DAG.getConstant(Imm, MVT::i32));
4790 unsigned WhichResult;
4791 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4792 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4793 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4795 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4796 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4797 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4799 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4800 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4801 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4804 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4805 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4806 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4808 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4809 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4810 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4812 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4813 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4814 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4817 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4818 if (Concat.getNode())
4823 int NumInputElements = V1.getValueType().getVectorNumElements();
4824 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4825 SDValue DstVec = DstIsLeft ? V1 : V2;
4826 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4828 SDValue SrcVec = V1;
4829 int SrcLane = ShuffleMask[Anomaly];
4830 if (SrcLane >= NumInputElements) {
4832 SrcLane -= VT.getVectorNumElements();
4834 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4836 EVT ScalarVT = VT.getVectorElementType();
4837 if (ScalarVT.getSizeInBits() < 32)
4838 ScalarVT = MVT::i32;
4841 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4842 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4846 // If the shuffle is not directly supported and it has 4 elements, use
4847 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4848 unsigned NumElts = VT.getVectorNumElements();
4850 unsigned PFIndexes[4];
4851 for (unsigned i = 0; i != 4; ++i) {
4852 if (ShuffleMask[i] < 0)
4855 PFIndexes[i] = ShuffleMask[i];
4858 // Compute the index in the perfect shuffle table.
4859 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4860 PFIndexes[2] * 9 + PFIndexes[3];
4861 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4862 unsigned Cost = (PFEntry >> 30);
4865 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4868 return GenerateTBL(Op, ShuffleMask, DAG);
4871 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4873 EVT VT = BVN->getValueType(0);
4874 APInt SplatBits, SplatUndef;
4875 unsigned SplatBitSize;
4877 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4878 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4880 for (unsigned i = 0; i < NumSplats; ++i) {
4881 CnstBits <<= SplatBitSize;
4882 UndefBits <<= SplatBitSize;
4883 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4884 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4893 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4894 SelectionDAG &DAG) const {
4895 BuildVectorSDNode *BVN =
4896 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4897 SDValue LHS = Op.getOperand(0);
4899 EVT VT = Op.getValueType();
4904 APInt CnstBits(VT.getSizeInBits(), 0);
4905 APInt UndefBits(VT.getSizeInBits(), 0);
4906 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4907 // We only have BIC vector immediate instruction, which is and-not.
4908 CnstBits = ~CnstBits;
4910 // We make use of a little bit of goto ickiness in order to avoid having to
4911 // duplicate the immediate matching logic for the undef toggled case.
4912 bool SecondTry = false;
4915 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4916 CnstBits = CnstBits.zextOrTrunc(64);
4917 uint64_t CnstVal = CnstBits.getZExtValue();
4919 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4920 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4921 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4922 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4923 DAG.getConstant(CnstVal, MVT::i32),
4924 DAG.getConstant(0, MVT::i32));
4925 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4928 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4929 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4930 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4931 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4932 DAG.getConstant(CnstVal, MVT::i32),
4933 DAG.getConstant(8, MVT::i32));
4934 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4937 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4938 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4939 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4940 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4941 DAG.getConstant(CnstVal, MVT::i32),
4942 DAG.getConstant(16, MVT::i32));
4943 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4946 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4947 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4948 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4949 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4950 DAG.getConstant(CnstVal, MVT::i32),
4951 DAG.getConstant(24, MVT::i32));
4952 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4955 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4956 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4957 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4958 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4959 DAG.getConstant(CnstVal, MVT::i32),
4960 DAG.getConstant(0, MVT::i32));
4961 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4964 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4965 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4966 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4967 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4968 DAG.getConstant(CnstVal, MVT::i32),
4969 DAG.getConstant(8, MVT::i32));
4970 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4977 CnstBits = ~UndefBits;
4981 // We can always fall back to a non-immediate AND.
4986 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4987 // consists of only the same constant int value, returned in reference arg
4989 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4990 uint64_t &ConstVal) {
4991 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4994 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4997 EVT VT = Bvec->getValueType(0);
4998 unsigned NumElts = VT.getVectorNumElements();
4999 for (unsigned i = 1; i < NumElts; ++i)
5000 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5002 ConstVal = FirstElt->getZExtValue();
5006 static unsigned getIntrinsicID(const SDNode *N) {
5007 unsigned Opcode = N->getOpcode();
5010 return Intrinsic::not_intrinsic;
5011 case ISD::INTRINSIC_WO_CHAIN: {
5012 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5013 if (IID < Intrinsic::num_intrinsics)
5015 return Intrinsic::not_intrinsic;
5020 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5021 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5022 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5023 // Also, logical shift right -> sri, with the same structure.
5024 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5025 EVT VT = N->getValueType(0);
5032 // Is the first op an AND?
5033 const SDValue And = N->getOperand(0);
5034 if (And.getOpcode() != ISD::AND)
5037 // Is the second op an shl or lshr?
5038 SDValue Shift = N->getOperand(1);
5039 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5040 // or AArch64ISD::VLSHR vector, #shift
5041 unsigned ShiftOpc = Shift.getOpcode();
5042 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5044 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5046 // Is the shift amount constant?
5047 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5051 // Is the and mask vector all constant?
5053 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5056 // Is C1 == ~C2, taking into account how much one can shift elements of a
5058 uint64_t C2 = C2node->getZExtValue();
5059 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5060 if (C2 > ElemSizeInBits)
5062 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5063 if ((C1 & ElemMask) != (~C2 & ElemMask))
5066 SDValue X = And.getOperand(0);
5067 SDValue Y = Shift.getOperand(0);
5070 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5072 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5073 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5075 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5076 DEBUG(N->dump(&DAG));
5077 DEBUG(dbgs() << "into: \n");
5078 DEBUG(ResultSLI->dump(&DAG));
5084 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5085 SelectionDAG &DAG) const {
5086 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5087 if (EnableAArch64SlrGeneration) {
5088 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5093 BuildVectorSDNode *BVN =
5094 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5095 SDValue LHS = Op.getOperand(1);
5097 EVT VT = Op.getValueType();
5099 // OR commutes, so try swapping the operands.
5101 LHS = Op.getOperand(0);
5102 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5107 APInt CnstBits(VT.getSizeInBits(), 0);
5108 APInt UndefBits(VT.getSizeInBits(), 0);
5109 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5110 // We make use of a little bit of goto ickiness in order to avoid having to
5111 // duplicate the immediate matching logic for the undef toggled case.
5112 bool SecondTry = false;
5115 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5116 CnstBits = CnstBits.zextOrTrunc(64);
5117 uint64_t CnstVal = CnstBits.getZExtValue();
5119 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5120 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5121 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5122 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5123 DAG.getConstant(CnstVal, MVT::i32),
5124 DAG.getConstant(0, MVT::i32));
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5128 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5129 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5130 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5131 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5132 DAG.getConstant(CnstVal, MVT::i32),
5133 DAG.getConstant(8, MVT::i32));
5134 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5137 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5138 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5139 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5140 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5141 DAG.getConstant(CnstVal, MVT::i32),
5142 DAG.getConstant(16, MVT::i32));
5143 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5146 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5147 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5148 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5149 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5150 DAG.getConstant(CnstVal, MVT::i32),
5151 DAG.getConstant(24, MVT::i32));
5152 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5155 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5156 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5157 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5158 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5159 DAG.getConstant(CnstVal, MVT::i32),
5160 DAG.getConstant(0, MVT::i32));
5161 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5164 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5165 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5166 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5167 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5168 DAG.getConstant(CnstVal, MVT::i32),
5169 DAG.getConstant(8, MVT::i32));
5170 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5177 CnstBits = UndefBits;
5181 // We can always fall back to a non-immediate OR.
5186 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5187 // be truncated to fit element width.
5188 static SDValue NormalizeBuildVector(SDValue Op,
5189 SelectionDAG &DAG) {
5190 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5192 EVT VT = Op.getValueType();
5193 EVT EltTy= VT.getVectorElementType();
5195 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5198 SmallVector<SDValue, 16> Ops;
5199 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5200 SDValue Lane = Op.getOperand(I);
5201 if (Lane.getOpcode() == ISD::Constant) {
5202 APInt LowBits(EltTy.getSizeInBits(),
5203 cast<ConstantSDNode>(Lane)->getZExtValue());
5204 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5206 Ops.push_back(Lane);
5208 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5211 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5212 SelectionDAG &DAG) const {
5214 EVT VT = Op.getValueType();
5215 Op = NormalizeBuildVector(Op, DAG);
5216 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5218 APInt CnstBits(VT.getSizeInBits(), 0);
5219 APInt UndefBits(VT.getSizeInBits(), 0);
5220 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5221 // We make use of a little bit of goto ickiness in order to avoid having to
5222 // duplicate the immediate matching logic for the undef toggled case.
5223 bool SecondTry = false;
5226 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5227 CnstBits = CnstBits.zextOrTrunc(64);
5228 uint64_t CnstVal = CnstBits.getZExtValue();
5230 // Certain magic vector constants (used to express things like NOT
5231 // and NEG) are passed through unmodified. This allows codegen patterns
5232 // for these operations to match. Special-purpose patterns will lower
5233 // these immediates to MOVIs if it proves necessary.
5234 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5237 // The many faces of MOVI...
5238 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5239 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5240 if (VT.getSizeInBits() == 128) {
5241 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5242 DAG.getConstant(CnstVal, MVT::i32));
5243 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5246 // Support the V64 version via subregister insertion.
5247 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5248 DAG.getConstant(CnstVal, MVT::i32));
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5252 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5253 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5254 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5255 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5256 DAG.getConstant(CnstVal, MVT::i32),
5257 DAG.getConstant(0, MVT::i32));
5258 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5261 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5262 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5263 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5264 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5265 DAG.getConstant(CnstVal, MVT::i32),
5266 DAG.getConstant(8, MVT::i32));
5267 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5270 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5271 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5272 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5273 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5274 DAG.getConstant(CnstVal, MVT::i32),
5275 DAG.getConstant(16, MVT::i32));
5276 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5279 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5280 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5281 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5282 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5283 DAG.getConstant(CnstVal, MVT::i32),
5284 DAG.getConstant(24, MVT::i32));
5285 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5288 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5289 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5290 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5291 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5292 DAG.getConstant(CnstVal, MVT::i32),
5293 DAG.getConstant(0, MVT::i32));
5294 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5297 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5298 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5299 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5300 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5301 DAG.getConstant(CnstVal, MVT::i32),
5302 DAG.getConstant(8, MVT::i32));
5303 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5306 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5307 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5308 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5309 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5310 DAG.getConstant(CnstVal, MVT::i32),
5311 DAG.getConstant(264, MVT::i32));
5312 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5315 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5316 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5317 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5318 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5319 DAG.getConstant(CnstVal, MVT::i32),
5320 DAG.getConstant(272, MVT::i32));
5321 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5324 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5325 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5326 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5327 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5328 DAG.getConstant(CnstVal, MVT::i32));
5329 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5332 // The few faces of FMOV...
5333 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5334 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5335 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5336 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5337 DAG.getConstant(CnstVal, MVT::i32));
5338 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5341 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5342 VT.getSizeInBits() == 128) {
5343 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5344 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5345 DAG.getConstant(CnstVal, MVT::i32));
5346 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5349 // The many faces of MVNI...
5351 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5352 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5353 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5354 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5355 DAG.getConstant(CnstVal, MVT::i32),
5356 DAG.getConstant(0, MVT::i32));
5357 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5360 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5361 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5362 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5363 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5364 DAG.getConstant(CnstVal, MVT::i32),
5365 DAG.getConstant(8, MVT::i32));
5366 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5369 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5370 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5371 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5372 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5373 DAG.getConstant(CnstVal, MVT::i32),
5374 DAG.getConstant(16, MVT::i32));
5375 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5378 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5379 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5380 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5381 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5382 DAG.getConstant(CnstVal, MVT::i32),
5383 DAG.getConstant(24, MVT::i32));
5384 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5387 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5388 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5389 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5390 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5391 DAG.getConstant(CnstVal, MVT::i32),
5392 DAG.getConstant(0, MVT::i32));
5393 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5396 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5397 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5398 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5399 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5400 DAG.getConstant(CnstVal, MVT::i32),
5401 DAG.getConstant(8, MVT::i32));
5402 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5405 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5406 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5407 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5408 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5409 DAG.getConstant(CnstVal, MVT::i32),
5410 DAG.getConstant(264, MVT::i32));
5411 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5414 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5415 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5416 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5417 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5418 DAG.getConstant(CnstVal, MVT::i32),
5419 DAG.getConstant(272, MVT::i32));
5420 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5427 CnstBits = UndefBits;
5432 // Scan through the operands to find some interesting properties we can
5434 // 1) If only one value is used, we can use a DUP, or
5435 // 2) if only the low element is not undef, we can just insert that, or
5436 // 3) if only one constant value is used (w/ some non-constant lanes),
5437 // we can splat the constant value into the whole vector then fill
5438 // in the non-constant lanes.
5439 // 4) FIXME: If different constant values are used, but we can intelligently
5440 // select the values we'll be overwriting for the non-constant
5441 // lanes such that we can directly materialize the vector
5442 // some other way (MOVI, e.g.), we can be sneaky.
5443 unsigned NumElts = VT.getVectorNumElements();
5444 bool isOnlyLowElement = true;
5445 bool usesOnlyOneValue = true;
5446 bool usesOnlyOneConstantValue = true;
5447 bool isConstant = true;
5448 unsigned NumConstantLanes = 0;
5450 SDValue ConstantValue;
5451 for (unsigned i = 0; i < NumElts; ++i) {
5452 SDValue V = Op.getOperand(i);
5453 if (V.getOpcode() == ISD::UNDEF)
5456 isOnlyLowElement = false;
5457 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5460 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5462 if (!ConstantValue.getNode())
5464 else if (ConstantValue != V)
5465 usesOnlyOneConstantValue = false;
5468 if (!Value.getNode())
5470 else if (V != Value)
5471 usesOnlyOneValue = false;
5474 if (!Value.getNode())
5475 return DAG.getUNDEF(VT);
5477 if (isOnlyLowElement)
5478 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5480 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5481 // i32 and try again.
5482 if (usesOnlyOneValue) {
5484 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5485 Value.getValueType() != VT)
5486 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5488 // This is actually a DUPLANExx operation, which keeps everything vectory.
5490 // DUPLANE works on 128-bit vectors, widen it if necessary.
5491 SDValue Lane = Value.getOperand(1);
5492 Value = Value.getOperand(0);
5493 if (Value.getValueType().getSizeInBits() == 64)
5494 Value = WidenVector(Value, DAG);
5496 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5497 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5500 if (VT.getVectorElementType().isFloatingPoint()) {
5501 SmallVector<SDValue, 8> Ops;
5503 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5504 for (unsigned i = 0; i < NumElts; ++i)
5505 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5506 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5507 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5508 Val = LowerBUILD_VECTOR(Val, DAG);
5510 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5514 // If there was only one constant value used and for more than one lane,
5515 // start by splatting that value, then replace the non-constant lanes. This
5516 // is better than the default, which will perform a separate initialization
5518 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5519 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5520 // Now insert the non-constant lanes.
5521 for (unsigned i = 0; i < NumElts; ++i) {
5522 SDValue V = Op.getOperand(i);
5523 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5524 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5525 // Note that type legalization likely mucked about with the VT of the
5526 // source operand, so we may have to convert it here before inserting.
5527 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5533 // If all elements are constants and the case above didn't get hit, fall back
5534 // to the default expansion, which will generate a load from the constant
5539 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5541 SDValue shuffle = ReconstructShuffle(Op, DAG);
5542 if (shuffle != SDValue())
5546 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5547 // know the default expansion would otherwise fall back on something even
5548 // worse. For a vector with one or two non-undef values, that's
5549 // scalar_to_vector for the elements followed by a shuffle (provided the
5550 // shuffle is valid for the target) and materialization element by element
5551 // on the stack followed by a load for everything else.
5552 if (!isConstant && !usesOnlyOneValue) {
5553 SDValue Vec = DAG.getUNDEF(VT);
5554 SDValue Op0 = Op.getOperand(0);
5555 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5557 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5558 // a) Avoid a RMW dependency on the full vector register, and
5559 // b) Allow the register coalescer to fold away the copy if the
5560 // value is already in an S or D register.
5561 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5562 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5564 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5565 DAG.getTargetConstant(SubIdx, MVT::i32));
5566 Vec = SDValue(N, 0);
5569 for (; i < NumElts; ++i) {
5570 SDValue V = Op.getOperand(i);
5571 if (V.getOpcode() == ISD::UNDEF)
5573 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5574 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5579 // Just use the default expansion. We failed to find a better alternative.
5583 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5584 SelectionDAG &DAG) const {
5585 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5587 // Check for non-constant lane.
5588 if (!isa<ConstantSDNode>(Op.getOperand(2)))
5591 EVT VT = Op.getOperand(0).getValueType();
5593 // Insertion/extraction are legal for V128 types.
5594 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5595 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5598 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5599 VT != MVT::v1i64 && VT != MVT::v2f32)
5602 // For V64 types, we perform insertion by expanding the value
5603 // to a V128 type and perform the insertion on that.
5605 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5606 EVT WideTy = WideVec.getValueType();
5608 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5609 Op.getOperand(1), Op.getOperand(2));
5610 // Re-narrow the resultant vector.
5611 return NarrowVector(Node, DAG);
5615 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5616 SelectionDAG &DAG) const {
5617 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5619 // Check for non-constant lane.
5620 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5623 EVT VT = Op.getOperand(0).getValueType();
5625 // Insertion/extraction are legal for V128 types.
5626 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5627 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5630 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5631 VT != MVT::v1i64 && VT != MVT::v2f32)
5634 // For V64 types, we perform extraction by expanding the value
5635 // to a V128 type and perform the extraction on that.
5637 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5638 EVT WideTy = WideVec.getValueType();
5640 EVT ExtrTy = WideTy.getVectorElementType();
5641 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5644 // For extractions, we just return the result directly.
5645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5649 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5650 SelectionDAG &DAG) const {
5651 EVT VT = Op.getOperand(0).getValueType();
5657 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5660 unsigned Val = Cst->getZExtValue();
5662 unsigned Size = Op.getValueType().getSizeInBits();
5666 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5669 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5672 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5675 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5678 llvm_unreachable("Unexpected vector type in extract_subvector!");
5681 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5683 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5689 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5691 if (VT.getVectorNumElements() == 4 &&
5692 (VT.is128BitVector() || VT.is64BitVector())) {
5693 unsigned PFIndexes[4];
5694 for (unsigned i = 0; i != 4; ++i) {
5698 PFIndexes[i] = M[i];
5701 // Compute the index in the perfect shuffle table.
5702 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5703 PFIndexes[2] * 9 + PFIndexes[3];
5704 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5705 unsigned Cost = (PFEntry >> 30);
5713 unsigned DummyUnsigned;
5715 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5716 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5717 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5718 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5719 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5720 isZIPMask(M, VT, DummyUnsigned) ||
5721 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5722 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5723 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5724 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5725 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5728 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5729 /// operand of a vector shift operation, where all the elements of the
5730 /// build_vector must have the same constant integer value.
5731 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5732 // Ignore bit_converts.
5733 while (Op.getOpcode() == ISD::BITCAST)
5734 Op = Op.getOperand(0);
5735 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5736 APInt SplatBits, SplatUndef;
5737 unsigned SplatBitSize;
5739 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5740 HasAnyUndefs, ElementBits) ||
5741 SplatBitSize > ElementBits)
5743 Cnt = SplatBits.getSExtValue();
5747 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5748 /// operand of a vector shift left operation. That value must be in the range:
5749 /// 0 <= Value < ElementBits for a left shift; or
5750 /// 0 <= Value <= ElementBits for a long left shift.
5751 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5752 assert(VT.isVector() && "vector shift count is not a vector type");
5753 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5754 if (!getVShiftImm(Op, ElementBits, Cnt))
5756 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5759 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5760 /// operand of a vector shift right operation. For a shift opcode, the value
5761 /// is positive, but for an intrinsic the value count must be negative. The
5762 /// absolute value must be in the range:
5763 /// 1 <= |Value| <= ElementBits for a right shift; or
5764 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5765 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5767 assert(VT.isVector() && "vector shift count is not a vector type");
5768 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5769 if (!getVShiftImm(Op, ElementBits, Cnt))
5773 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5776 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5777 SelectionDAG &DAG) const {
5778 EVT VT = Op.getValueType();
5782 if (!Op.getOperand(1).getValueType().isVector())
5784 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5786 switch (Op.getOpcode()) {
5788 llvm_unreachable("unexpected shift opcode");
5791 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5792 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5793 DAG.getConstant(Cnt, MVT::i32));
5794 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5795 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5796 Op.getOperand(0), Op.getOperand(1));
5799 // Right shift immediate
5800 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5803 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5804 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5805 DAG.getConstant(Cnt, MVT::i32));
5808 // Right shift register. Note, there is not a shift right register
5809 // instruction, but the shift left register instruction takes a signed
5810 // value, where negative numbers specify a right shift.
5811 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5812 : Intrinsic::aarch64_neon_ushl;
5813 // negate the shift amount
5814 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5815 SDValue NegShiftLeft =
5816 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5817 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5818 return NegShiftLeft;
5824 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5825 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5826 SDLoc dl, SelectionDAG &DAG) {
5827 EVT SrcVT = LHS.getValueType();
5829 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5830 APInt CnstBits(VT.getSizeInBits(), 0);
5831 APInt UndefBits(VT.getSizeInBits(), 0);
5832 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5833 bool IsZero = IsCnst && (CnstBits == 0);
5835 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5839 case AArch64CC::NE: {
5842 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5844 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5845 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5849 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5850 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5853 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5854 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5857 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5858 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5861 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5862 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5866 // If we ignore NaNs then we can use to the MI implementation.
5870 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5871 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5878 case AArch64CC::NE: {
5881 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5883 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5884 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5888 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5889 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5892 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5893 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5896 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5897 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5900 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5901 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5903 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5905 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5908 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5909 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5911 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5913 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5917 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5918 SelectionDAG &DAG) const {
5919 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5920 SDValue LHS = Op.getOperand(0);
5921 SDValue RHS = Op.getOperand(1);
5924 if (LHS.getValueType().getVectorElementType().isInteger()) {
5925 assert(LHS.getValueType() == RHS.getValueType());
5926 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5927 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5931 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5932 LHS.getValueType().getVectorElementType() == MVT::f64);
5934 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5935 // clean. Some of them require two branches to implement.
5936 AArch64CC::CondCode CC1, CC2;
5938 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5940 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5942 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5946 if (CC2 != AArch64CC::AL) {
5948 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5949 if (!Cmp2.getNode())
5952 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5956 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5961 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5962 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5963 /// specified in the intrinsic calls.
5964 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5966 unsigned Intrinsic) const {
5967 switch (Intrinsic) {
5968 case Intrinsic::aarch64_neon_ld2:
5969 case Intrinsic::aarch64_neon_ld3:
5970 case Intrinsic::aarch64_neon_ld4:
5971 case Intrinsic::aarch64_neon_ld1x2:
5972 case Intrinsic::aarch64_neon_ld1x3:
5973 case Intrinsic::aarch64_neon_ld1x4:
5974 case Intrinsic::aarch64_neon_ld2lane:
5975 case Intrinsic::aarch64_neon_ld3lane:
5976 case Intrinsic::aarch64_neon_ld4lane:
5977 case Intrinsic::aarch64_neon_ld2r:
5978 case Intrinsic::aarch64_neon_ld3r:
5979 case Intrinsic::aarch64_neon_ld4r: {
5980 Info.opc = ISD::INTRINSIC_W_CHAIN;
5981 // Conservatively set memVT to the entire set of vectors loaded.
5982 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5983 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5984 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5987 Info.vol = false; // volatile loads with NEON intrinsics not supported
5988 Info.readMem = true;
5989 Info.writeMem = false;
5992 case Intrinsic::aarch64_neon_st2:
5993 case Intrinsic::aarch64_neon_st3:
5994 case Intrinsic::aarch64_neon_st4:
5995 case Intrinsic::aarch64_neon_st1x2:
5996 case Intrinsic::aarch64_neon_st1x3:
5997 case Intrinsic::aarch64_neon_st1x4:
5998 case Intrinsic::aarch64_neon_st2lane:
5999 case Intrinsic::aarch64_neon_st3lane:
6000 case Intrinsic::aarch64_neon_st4lane: {
6001 Info.opc = ISD::INTRINSIC_VOID;
6002 // Conservatively set memVT to the entire set of vectors stored.
6003 unsigned NumElts = 0;
6004 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6005 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6006 if (!ArgTy->isVectorTy())
6008 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6010 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6011 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6014 Info.vol = false; // volatile stores with NEON intrinsics not supported
6015 Info.readMem = false;
6016 Info.writeMem = true;
6019 case Intrinsic::aarch64_ldaxr:
6020 case Intrinsic::aarch64_ldxr: {
6021 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6022 Info.opc = ISD::INTRINSIC_W_CHAIN;
6023 Info.memVT = MVT::getVT(PtrTy->getElementType());
6024 Info.ptrVal = I.getArgOperand(0);
6026 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6028 Info.readMem = true;
6029 Info.writeMem = false;
6032 case Intrinsic::aarch64_stlxr:
6033 case Intrinsic::aarch64_stxr: {
6034 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6035 Info.opc = ISD::INTRINSIC_W_CHAIN;
6036 Info.memVT = MVT::getVT(PtrTy->getElementType());
6037 Info.ptrVal = I.getArgOperand(1);
6039 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6041 Info.readMem = false;
6042 Info.writeMem = true;
6045 case Intrinsic::aarch64_ldaxp:
6046 case Intrinsic::aarch64_ldxp: {
6047 Info.opc = ISD::INTRINSIC_W_CHAIN;
6048 Info.memVT = MVT::i128;
6049 Info.ptrVal = I.getArgOperand(0);
6053 Info.readMem = true;
6054 Info.writeMem = false;
6057 case Intrinsic::aarch64_stlxp:
6058 case Intrinsic::aarch64_stxp: {
6059 Info.opc = ISD::INTRINSIC_W_CHAIN;
6060 Info.memVT = MVT::i128;
6061 Info.ptrVal = I.getArgOperand(2);
6065 Info.readMem = false;
6066 Info.writeMem = true;
6076 // Truncations from 64-bit GPR to 32-bit GPR is free.
6077 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6078 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6080 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6081 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6082 return NumBits1 > NumBits2;
6084 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6085 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6087 unsigned NumBits1 = VT1.getSizeInBits();
6088 unsigned NumBits2 = VT2.getSizeInBits();
6089 return NumBits1 > NumBits2;
6092 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6094 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6095 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6097 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6098 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6099 return NumBits1 == 32 && NumBits2 == 64;
6101 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6102 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6104 unsigned NumBits1 = VT1.getSizeInBits();
6105 unsigned NumBits2 = VT2.getSizeInBits();
6106 return NumBits1 == 32 && NumBits2 == 64;
6109 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6110 EVT VT1 = Val.getValueType();
6111 if (isZExtFree(VT1, VT2)) {
6115 if (Val.getOpcode() != ISD::LOAD)
6118 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6119 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6120 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6121 VT1.getSizeInBits() <= 32);
6124 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6125 unsigned &RequiredAligment) const {
6126 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6128 // Cyclone supports unaligned accesses.
6129 RequiredAligment = 0;
6130 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6131 return NumBits == 32 || NumBits == 64;
6134 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6135 unsigned &RequiredAligment) const {
6136 if (!LoadedType.isSimple() ||
6137 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6139 // Cyclone supports unaligned accesses.
6140 RequiredAligment = 0;
6141 unsigned NumBits = LoadedType.getSizeInBits();
6142 return NumBits == 32 || NumBits == 64;
6145 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6146 unsigned AlignCheck) {
6147 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6148 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6151 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6152 unsigned SrcAlign, bool IsMemset,
6155 MachineFunction &MF) const {
6156 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6157 // instruction to materialize the v2i64 zero and one store (with restrictive
6158 // addressing mode). Just do two i64 store of zero-registers.
6160 const Function *F = MF.getFunction();
6161 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6162 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6163 Attribute::NoImplicitFloat) &&
6164 (memOpAlign(SrcAlign, DstAlign, 16) ||
6165 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6168 return Size >= 8 ? MVT::i64 : MVT::i32;
6171 // 12-bit optionally shifted immediates are legal for adds.
6172 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6173 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6178 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6179 // immediates is the same as for an add or a sub.
6180 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6183 return isLegalAddImmediate(Immed);
6186 /// isLegalAddressingMode - Return true if the addressing mode represented
6187 /// by AM is legal for this target, for a load/store of the specified type.
6188 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6190 // AArch64 has five basic addressing modes:
6192 // reg + 9-bit signed offset
6193 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6195 // reg + SIZE_IN_BYTES * reg
6197 // No global is ever allowed as a base.
6201 // No reg+reg+imm addressing.
6202 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6205 // check reg + imm case:
6206 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6207 uint64_t NumBytes = 0;
6208 if (Ty->isSized()) {
6209 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6210 NumBytes = NumBits / 8;
6211 if (!isPowerOf2_64(NumBits))
6216 int64_t Offset = AM.BaseOffs;
6218 // 9-bit signed offset
6219 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6222 // 12-bit unsigned offset
6223 unsigned shift = Log2_64(NumBytes);
6224 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6225 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6226 (Offset >> shift) << shift == Offset)
6231 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6233 if (!AM.Scale || AM.Scale == 1 ||
6234 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6239 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6241 // Scaling factors are not free at all.
6242 // Operands | Rt Latency
6243 // -------------------------------------------
6245 // -------------------------------------------
6246 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6247 // Rt, [Xn, Wm, <extend> #imm] |
6248 if (isLegalAddressingMode(AM, Ty))
6249 // Scale represents reg2 * scale, thus account for 1 if
6250 // it is not equal to 0 or 1.
6251 return AM.Scale != 0 && AM.Scale != 1;
6255 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6256 VT = VT.getScalarType();
6261 switch (VT.getSimpleVT().SimpleTy) {
6273 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6274 // LR is a callee-save register, but we must treat it as clobbered by any call
6275 // site. Hence we include LR in the scratch registers, which are in turn added
6276 // as implicit-defs for stackmaps and patchpoints.
6277 static const MCPhysReg ScratchRegs[] = {
6278 AArch64::X16, AArch64::X17, AArch64::LR, 0
6284 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6285 EVT VT = N->getValueType(0);
6286 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6287 // it with shift to let it be lowered to UBFX.
6288 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6289 isa<ConstantSDNode>(N->getOperand(1))) {
6290 uint64_t TruncMask = N->getConstantOperandVal(1);
6291 if (isMask_64(TruncMask) &&
6292 N->getOperand(0).getOpcode() == ISD::SRL &&
6293 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6299 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6301 assert(Ty->isIntegerTy());
6303 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6307 int64_t Val = Imm.getSExtValue();
6308 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6311 if ((int64_t)Val < 0)
6314 Val &= (1LL << 32) - 1;
6316 unsigned LZ = countLeadingZeros((uint64_t)Val);
6317 unsigned Shift = (63 - LZ) / 16;
6318 // MOVZ is free so return true for one or fewer MOVK.
6319 return (Shift < 3) ? true : false;
6322 // Generate SUBS and CSEL for integer abs.
6323 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6324 EVT VT = N->getValueType(0);
6326 SDValue N0 = N->getOperand(0);
6327 SDValue N1 = N->getOperand(1);
6330 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6331 // and change it to SUB and CSEL.
6332 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6333 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6334 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6335 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6336 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6337 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6339 // Generate SUBS & CSEL.
6341 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6342 N0.getOperand(0), DAG.getConstant(0, VT));
6343 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6344 DAG.getConstant(AArch64CC::PL, MVT::i32),
6345 SDValue(Cmp.getNode(), 1));
6350 // performXorCombine - Attempts to handle integer ABS.
6351 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6352 TargetLowering::DAGCombinerInfo &DCI,
6353 const AArch64Subtarget *Subtarget) {
6354 if (DCI.isBeforeLegalizeOps())
6357 return performIntegerAbsCombine(N, DAG);
6360 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6361 TargetLowering::DAGCombinerInfo &DCI,
6362 const AArch64Subtarget *Subtarget) {
6363 if (DCI.isBeforeLegalizeOps())
6366 // Multiplication of a power of two plus/minus one can be done more
6367 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6368 // future CPUs have a cheaper MADD instruction, this may need to be
6369 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6370 // 64-bit is 5 cycles, so this is always a win.
6371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6372 APInt Value = C->getAPIntValue();
6373 EVT VT = N->getValueType(0);
6374 if (Value.isNonNegative()) {
6375 // (mul x, 2^N + 1) => (add (shl x, N), x)
6376 APInt VM1 = Value - 1;
6377 if (VM1.isPowerOf2()) {
6378 SDValue ShiftedVal =
6379 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6380 DAG.getConstant(VM1.logBase2(), MVT::i64));
6381 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6384 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6385 APInt VP1 = Value + 1;
6386 if (VP1.isPowerOf2()) {
6387 SDValue ShiftedVal =
6388 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6389 DAG.getConstant(VP1.logBase2(), MVT::i64));
6390 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6394 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6395 APInt VNM1 = -Value - 1;
6396 if (VNM1.isPowerOf2()) {
6397 SDValue ShiftedVal =
6398 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6399 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6401 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6402 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6404 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6405 APInt VNP1 = -Value + 1;
6406 if (VNP1.isPowerOf2()) {
6407 SDValue ShiftedVal =
6408 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6409 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6410 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6418 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6419 EVT VT = N->getValueType(0);
6420 if (VT != MVT::f32 && VT != MVT::f64)
6422 // Only optimize when the source and destination types have the same width.
6423 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6426 // If the result of an integer load is only used by an integer-to-float
6427 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6428 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6429 SDValue N0 = N->getOperand(0);
6430 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6431 // Do not change the width of a volatile load.
6432 !cast<LoadSDNode>(N0)->isVolatile()) {
6433 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6434 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6435 LN0->getPointerInfo(), LN0->isVolatile(),
6436 LN0->isNonTemporal(), LN0->isInvariant(),
6437 LN0->getAlignment());
6439 // Make sure successors of the original load stay after it by updating them
6440 // to use the new Chain.
6441 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6444 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6445 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6451 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6452 /// searches for and classifies those shifts.
6453 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6455 if (N.getOpcode() == ISD::SHL)
6457 else if (N.getOpcode() == ISD::SRL)
6462 if (!isa<ConstantSDNode>(N.getOperand(1)))
6465 ShiftAmount = N->getConstantOperandVal(1);
6466 Src = N->getOperand(0);
6470 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6471 /// registers viewed as a high/low pair. This function looks for the pattern:
6472 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6473 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6475 static SDValue tryCombineToEXTR(SDNode *N,
6476 TargetLowering::DAGCombinerInfo &DCI) {
6477 SelectionDAG &DAG = DCI.DAG;
6479 EVT VT = N->getValueType(0);
6481 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6483 if (VT != MVT::i32 && VT != MVT::i64)
6487 uint32_t ShiftLHS = 0;
6489 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6493 uint32_t ShiftRHS = 0;
6495 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6498 // If they're both trying to come from the high part of the register, they're
6499 // not really an EXTR.
6500 if (LHSFromHi == RHSFromHi)
6503 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6507 std::swap(LHS, RHS);
6508 std::swap(ShiftLHS, ShiftRHS);
6511 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6512 DAG.getConstant(ShiftRHS, MVT::i64));
6515 static SDValue tryCombineToBSL(SDNode *N,
6516 TargetLowering::DAGCombinerInfo &DCI) {
6517 EVT VT = N->getValueType(0);
6518 SelectionDAG &DAG = DCI.DAG;
6524 SDValue N0 = N->getOperand(0);
6525 if (N0.getOpcode() != ISD::AND)
6528 SDValue N1 = N->getOperand(1);
6529 if (N1.getOpcode() != ISD::AND)
6532 // We only have to look for constant vectors here since the general, variable
6533 // case can be handled in TableGen.
6534 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6535 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6536 for (int i = 1; i >= 0; --i)
6537 for (int j = 1; j >= 0; --j) {
6538 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6539 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6543 bool FoundMatch = true;
6544 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6545 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6546 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6548 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6555 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6556 N0->getOperand(1 - i), N1->getOperand(1 - j));
6562 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6563 const AArch64Subtarget *Subtarget) {
6564 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6565 if (!EnableAArch64ExtrGeneration)
6567 SelectionDAG &DAG = DCI.DAG;
6568 EVT VT = N->getValueType(0);
6570 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6573 SDValue Res = tryCombineToEXTR(N, DCI);
6577 Res = tryCombineToBSL(N, DCI);
6584 static SDValue performBitcastCombine(SDNode *N,
6585 TargetLowering::DAGCombinerInfo &DCI,
6586 SelectionDAG &DAG) {
6587 // Wait 'til after everything is legalized to try this. That way we have
6588 // legal vector types and such.
6589 if (DCI.isBeforeLegalizeOps())
6592 // Remove extraneous bitcasts around an extract_subvector.
6594 // (v4i16 (bitconvert
6595 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6597 // (extract_subvector ((v8i16 ...), (i64 4)))
6599 // Only interested in 64-bit vectors as the ultimate result.
6600 EVT VT = N->getValueType(0);
6603 if (VT.getSimpleVT().getSizeInBits() != 64)
6605 // Is the operand an extract_subvector starting at the beginning or halfway
6606 // point of the vector? A low half may also come through as an
6607 // EXTRACT_SUBREG, so look for that, too.
6608 SDValue Op0 = N->getOperand(0);
6609 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6610 !(Op0->isMachineOpcode() &&
6611 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6613 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6614 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6615 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6617 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6618 if (idx != AArch64::dsub)
6620 // The dsub reference is equivalent to a lane zero subvector reference.
6623 // Look through the bitcast of the input to the extract.
6624 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6626 SDValue Source = Op0->getOperand(0)->getOperand(0);
6627 // If the source type has twice the number of elements as our destination
6628 // type, we know this is an extract of the high or low half of the vector.
6629 EVT SVT = Source->getValueType(0);
6630 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6633 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6635 // Create the simplified form to just extract the low or high half of the
6636 // vector directly rather than bothering with the bitcasts.
6638 unsigned NumElements = VT.getVectorNumElements();
6640 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6641 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6643 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6644 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6650 static SDValue performConcatVectorsCombine(SDNode *N,
6651 TargetLowering::DAGCombinerInfo &DCI,
6652 SelectionDAG &DAG) {
6653 // Wait 'til after everything is legalized to try this. That way we have
6654 // legal vector types and such.
6655 if (DCI.isBeforeLegalizeOps())
6659 EVT VT = N->getValueType(0);
6661 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6662 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6663 // canonicalise to that.
6664 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6665 assert(VT.getVectorElementType().getSizeInBits() == 64);
6666 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6667 WidenVector(N->getOperand(0), DAG),
6668 DAG.getConstant(0, MVT::i64));
6671 // Canonicalise concat_vectors so that the right-hand vector has as few
6672 // bit-casts as possible before its real operation. The primary matching
6673 // destination for these operations will be the narrowing "2" instructions,
6674 // which depend on the operation being performed on this right-hand vector.
6676 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6678 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6680 SDValue Op1 = N->getOperand(1);
6681 if (Op1->getOpcode() != ISD::BITCAST)
6683 SDValue RHS = Op1->getOperand(0);
6684 MVT RHSTy = RHS.getValueType().getSimpleVT();
6685 // If the RHS is not a vector, this is not the pattern we're looking for.
6686 if (!RHSTy.isVector())
6689 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6691 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6692 RHSTy.getVectorNumElements() * 2);
6694 ISD::BITCAST, dl, VT,
6695 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6696 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6699 static SDValue tryCombineFixedPointConvert(SDNode *N,
6700 TargetLowering::DAGCombinerInfo &DCI,
6701 SelectionDAG &DAG) {
6702 // Wait 'til after everything is legalized to try this. That way we have
6703 // legal vector types and such.
6704 if (DCI.isBeforeLegalizeOps())
6706 // Transform a scalar conversion of a value from a lane extract into a
6707 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6708 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6709 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6711 // The second form interacts better with instruction selection and the
6712 // register allocator to avoid cross-class register copies that aren't
6713 // coalescable due to a lane reference.
6715 // Check the operand and see if it originates from a lane extract.
6716 SDValue Op1 = N->getOperand(1);
6717 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6718 // Yep, no additional predication needed. Perform the transform.
6719 SDValue IID = N->getOperand(0);
6720 SDValue Shift = N->getOperand(2);
6721 SDValue Vec = Op1.getOperand(0);
6722 SDValue Lane = Op1.getOperand(1);
6723 EVT ResTy = N->getValueType(0);
6727 // The vector width should be 128 bits by the time we get here, even
6728 // if it started as 64 bits (the extract_vector handling will have
6730 assert(Vec.getValueType().getSizeInBits() == 128 &&
6731 "unexpected vector size on extract_vector_elt!");
6732 if (Vec.getValueType() == MVT::v4i32)
6733 VecResTy = MVT::v4f32;
6734 else if (Vec.getValueType() == MVT::v2i64)
6735 VecResTy = MVT::v2f64;
6737 llvm_unreachable("unexpected vector type!");
6740 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6741 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6746 // AArch64 high-vector "long" operations are formed by performing the non-high
6747 // version on an extract_subvector of each operand which gets the high half:
6749 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6751 // However, there are cases which don't have an extract_high explicitly, but
6752 // have another operation that can be made compatible with one for free. For
6755 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6757 // This routine does the actual conversion of such DUPs, once outer routines
6758 // have determined that everything else is in order.
6759 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6760 // We can handle most types of duplicate, but the lane ones have an extra
6761 // operand saying *which* lane, so we need to know.
6763 switch (N.getOpcode()) {
6764 case AArch64ISD::DUP:
6767 case AArch64ISD::DUPLANE8:
6768 case AArch64ISD::DUPLANE16:
6769 case AArch64ISD::DUPLANE32:
6770 case AArch64ISD::DUPLANE64:
6777 MVT NarrowTy = N.getSimpleValueType();
6778 if (!NarrowTy.is64BitVector())
6781 MVT ElementTy = NarrowTy.getVectorElementType();
6782 unsigned NumElems = NarrowTy.getVectorNumElements();
6783 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6787 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6790 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6792 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6793 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6796 static bool isEssentiallyExtractSubvector(SDValue N) {
6797 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6800 return N.getOpcode() == ISD::BITCAST &&
6801 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6804 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6805 struct GenericSetCCInfo {
6806 const SDValue *Opnd0;
6807 const SDValue *Opnd1;
6811 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6812 struct AArch64SetCCInfo {
6814 AArch64CC::CondCode CC;
6817 /// \brief Helper structure to keep track of SetCC information.
6819 GenericSetCCInfo Generic;
6820 AArch64SetCCInfo AArch64;
6823 /// \brief Helper structure to be able to read SetCC information. If set to
6824 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6825 /// GenericSetCCInfo.
6826 struct SetCCInfoAndKind {
6831 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6833 /// AArch64 lowered one.
6834 /// \p SetCCInfo is filled accordingly.
6835 /// \post SetCCInfo is meanginfull only when this function returns true.
6836 /// \return True when Op is a kind of SET_CC operation.
6837 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6838 // If this is a setcc, this is straight forward.
6839 if (Op.getOpcode() == ISD::SETCC) {
6840 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6841 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6842 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6843 SetCCInfo.IsAArch64 = false;
6846 // Otherwise, check if this is a matching csel instruction.
6850 if (Op.getOpcode() != AArch64ISD::CSEL)
6852 // Set the information about the operands.
6853 // TODO: we want the operands of the Cmp not the csel
6854 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6855 SetCCInfo.IsAArch64 = true;
6856 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6857 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6859 // Check that the operands matches the constraints:
6860 // (1) Both operands must be constants.
6861 // (2) One must be 1 and the other must be 0.
6862 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6863 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6866 if (!TValue || !FValue)
6870 if (!TValue->isOne()) {
6871 // Update the comparison when we are interested in !cc.
6872 std::swap(TValue, FValue);
6873 SetCCInfo.Info.AArch64.CC =
6874 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6876 return TValue->isOne() && FValue->isNullValue();
6879 // Returns true if Op is setcc or zext of setcc.
6880 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6881 if (isSetCC(Op, Info))
6883 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6884 isSetCC(Op->getOperand(0), Info));
6887 // The folding we want to perform is:
6888 // (add x, [zext] (setcc cc ...) )
6890 // (csel x, (add x, 1), !cc ...)
6892 // The latter will get matched to a CSINC instruction.
6893 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6894 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6895 SDValue LHS = Op->getOperand(0);
6896 SDValue RHS = Op->getOperand(1);
6897 SetCCInfoAndKind InfoAndKind;
6899 // If neither operand is a SET_CC, give up.
6900 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6901 std::swap(LHS, RHS);
6902 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6906 // FIXME: This could be generatized to work for FP comparisons.
6907 EVT CmpVT = InfoAndKind.IsAArch64
6908 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
6909 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6910 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6916 if (InfoAndKind.IsAArch64) {
6917 CCVal = DAG.getConstant(
6918 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
6919 Cmp = *InfoAndKind.Info.AArch64.Cmp;
6921 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6922 *InfoAndKind.Info.Generic.Opnd1,
6923 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6926 EVT VT = Op->getValueType(0);
6927 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6928 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6931 // The basic add/sub long vector instructions have variants with "2" on the end
6932 // which act on the high-half of their inputs. They are normally matched by
6935 // (add (zeroext (extract_high LHS)),
6936 // (zeroext (extract_high RHS)))
6937 // -> uaddl2 vD, vN, vM
6939 // However, if one of the extracts is something like a duplicate, this
6940 // instruction can still be used profitably. This function puts the DAG into a
6941 // more appropriate form for those patterns to trigger.
6942 static SDValue performAddSubLongCombine(SDNode *N,
6943 TargetLowering::DAGCombinerInfo &DCI,
6944 SelectionDAG &DAG) {
6945 if (DCI.isBeforeLegalizeOps())
6948 MVT VT = N->getSimpleValueType(0);
6949 if (!VT.is128BitVector()) {
6950 if (N->getOpcode() == ISD::ADD)
6951 return performSetccAddFolding(N, DAG);
6955 // Make sure both branches are extended in the same way.
6956 SDValue LHS = N->getOperand(0);
6957 SDValue RHS = N->getOperand(1);
6958 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
6959 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
6960 LHS.getOpcode() != RHS.getOpcode())
6963 unsigned ExtType = LHS.getOpcode();
6965 // It's not worth doing if at least one of the inputs isn't already an
6966 // extract, but we don't know which it'll be so we have to try both.
6967 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
6968 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
6972 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6973 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
6974 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
6978 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
6981 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
6984 // Massage DAGs which we can use the high-half "long" operations on into
6985 // something isel will recognize better. E.g.
6987 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
6988 // (aarch64_neon_umull (extract_high (v2i64 vec)))
6989 // (extract_high (v2i64 (dup128 scalar)))))
6991 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
6992 TargetLowering::DAGCombinerInfo &DCI,
6993 SelectionDAG &DAG) {
6994 if (DCI.isBeforeLegalizeOps())
6997 SDValue LHS = N->getOperand(1);
6998 SDValue RHS = N->getOperand(2);
6999 assert(LHS.getValueType().is64BitVector() &&
7000 RHS.getValueType().is64BitVector() &&
7001 "unexpected shape for long operation");
7003 // Either node could be a DUP, but it's not worth doing both of them (you'd
7004 // just as well use the non-high version) so look for a corresponding extract
7005 // operation on the other "wing".
7006 if (isEssentiallyExtractSubvector(LHS)) {
7007 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7010 } else if (isEssentiallyExtractSubvector(RHS)) {
7011 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7016 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7017 N->getOperand(0), LHS, RHS);
7020 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7021 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7022 unsigned ElemBits = ElemTy.getSizeInBits();
7024 int64_t ShiftAmount;
7025 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7026 APInt SplatValue, SplatUndef;
7027 unsigned SplatBitSize;
7029 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7030 HasAnyUndefs, ElemBits) ||
7031 SplatBitSize != ElemBits)
7034 ShiftAmount = SplatValue.getSExtValue();
7035 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7036 ShiftAmount = CVN->getSExtValue();
7044 llvm_unreachable("Unknown shift intrinsic");
7045 case Intrinsic::aarch64_neon_sqshl:
7046 Opcode = AArch64ISD::SQSHL_I;
7047 IsRightShift = false;
7049 case Intrinsic::aarch64_neon_uqshl:
7050 Opcode = AArch64ISD::UQSHL_I;
7051 IsRightShift = false;
7053 case Intrinsic::aarch64_neon_srshl:
7054 Opcode = AArch64ISD::SRSHR_I;
7055 IsRightShift = true;
7057 case Intrinsic::aarch64_neon_urshl:
7058 Opcode = AArch64ISD::URSHR_I;
7059 IsRightShift = true;
7061 case Intrinsic::aarch64_neon_sqshlu:
7062 Opcode = AArch64ISD::SQSHLU_I;
7063 IsRightShift = false;
7067 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7068 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7069 DAG.getConstant(-ShiftAmount, MVT::i32));
7070 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7071 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7072 DAG.getConstant(ShiftAmount, MVT::i32));
7077 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7078 // the intrinsics must be legal and take an i32, this means there's almost
7079 // certainly going to be a zext in the DAG which we can eliminate.
7080 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7081 SDValue AndN = N->getOperand(2);
7082 if (AndN.getOpcode() != ISD::AND)
7085 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7086 if (!CMask || CMask->getZExtValue() != Mask)
7089 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7090 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7093 static SDValue performIntrinsicCombine(SDNode *N,
7094 TargetLowering::DAGCombinerInfo &DCI,
7095 const AArch64Subtarget *Subtarget) {
7096 SelectionDAG &DAG = DCI.DAG;
7097 unsigned IID = getIntrinsicID(N);
7101 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7102 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7103 return tryCombineFixedPointConvert(N, DCI, DAG);
7105 case Intrinsic::aarch64_neon_fmax:
7106 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7107 N->getOperand(1), N->getOperand(2));
7108 case Intrinsic::aarch64_neon_fmin:
7109 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7110 N->getOperand(1), N->getOperand(2));
7111 case Intrinsic::aarch64_neon_smull:
7112 case Intrinsic::aarch64_neon_umull:
7113 case Intrinsic::aarch64_neon_pmull:
7114 case Intrinsic::aarch64_neon_sqdmull:
7115 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7116 case Intrinsic::aarch64_neon_sqshl:
7117 case Intrinsic::aarch64_neon_uqshl:
7118 case Intrinsic::aarch64_neon_sqshlu:
7119 case Intrinsic::aarch64_neon_srshl:
7120 case Intrinsic::aarch64_neon_urshl:
7121 return tryCombineShiftImm(IID, N, DAG);
7122 case Intrinsic::aarch64_crc32b:
7123 case Intrinsic::aarch64_crc32cb:
7124 return tryCombineCRC32(0xff, N, DAG);
7125 case Intrinsic::aarch64_crc32h:
7126 case Intrinsic::aarch64_crc32ch:
7127 return tryCombineCRC32(0xffff, N, DAG);
7132 static SDValue performExtendCombine(SDNode *N,
7133 TargetLowering::DAGCombinerInfo &DCI,
7134 SelectionDAG &DAG) {
7135 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7136 // we can convert that DUP into another extract_high (of a bigger DUP), which
7137 // helps the backend to decide that an sabdl2 would be useful, saving a real
7138 // extract_high operation.
7139 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7140 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7141 SDNode *ABDNode = N->getOperand(0).getNode();
7142 unsigned IID = getIntrinsicID(ABDNode);
7143 if (IID == Intrinsic::aarch64_neon_sabd ||
7144 IID == Intrinsic::aarch64_neon_uabd) {
7145 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7146 if (!NewABD.getNode())
7149 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7154 // This is effectively a custom type legalization for AArch64.
7156 // Type legalization will split an extend of a small, legal, type to a larger
7157 // illegal type by first splitting the destination type, often creating
7158 // illegal source types, which then get legalized in isel-confusing ways,
7159 // leading to really terrible codegen. E.g.,
7160 // %result = v8i32 sext v8i8 %value
7162 // %losrc = extract_subreg %value, ...
7163 // %hisrc = extract_subreg %value, ...
7164 // %lo = v4i32 sext v4i8 %losrc
7165 // %hi = v4i32 sext v4i8 %hisrc
7166 // Things go rapidly downhill from there.
7168 // For AArch64, the [sz]ext vector instructions can only go up one element
7169 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7170 // take two instructions.
7172 // This implies that the most efficient way to do the extend from v8i8
7173 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7174 // the normal splitting to happen for the v8i16->v8i32.
7176 // This is pre-legalization to catch some cases where the default
7177 // type legalization will create ill-tempered code.
7178 if (!DCI.isBeforeLegalizeOps())
7181 // We're only interested in cleaning things up for non-legal vector types
7182 // here. If both the source and destination are legal, things will just
7183 // work naturally without any fiddling.
7184 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7185 EVT ResVT = N->getValueType(0);
7186 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7188 // If the vector type isn't a simple VT, it's beyond the scope of what
7189 // we're worried about here. Let legalization do its thing and hope for
7191 if (!ResVT.isSimple())
7194 SDValue Src = N->getOperand(0);
7195 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7196 // If the source VT is a 64-bit vector, we can play games and get the
7197 // better results we want.
7198 if (SrcVT.getSizeInBits() != 64)
7201 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7202 unsigned ElementCount = SrcVT.getVectorNumElements();
7203 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7205 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7207 // Now split the rest of the operation into two halves, each with a 64
7211 unsigned NumElements = ResVT.getVectorNumElements();
7212 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7213 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7214 ResVT.getVectorElementType(), NumElements / 2);
7216 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7217 LoVT.getVectorNumElements());
7218 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7219 DAG.getIntPtrConstant(0));
7220 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7221 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7222 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7223 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7225 // Now combine the parts back together so we still have a single result
7226 // like the combiner expects.
7227 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7230 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7231 /// value. The load store optimizer pass will merge them to store pair stores.
7232 /// This has better performance than a splat of the scalar followed by a split
7233 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7234 /// followed by an ext.b and two stores.
7235 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7236 SDValue StVal = St->getValue();
7237 EVT VT = StVal.getValueType();
7239 // Don't replace floating point stores, they possibly won't be transformed to
7240 // stp because of the store pair suppress pass.
7241 if (VT.isFloatingPoint())
7244 // Check for insert vector elements.
7245 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7248 // We can express a splat as store pair(s) for 2 or 4 elements.
7249 unsigned NumVecElts = VT.getVectorNumElements();
7250 if (NumVecElts != 4 && NumVecElts != 2)
7252 SDValue SplatVal = StVal.getOperand(1);
7253 unsigned RemainInsertElts = NumVecElts - 1;
7255 // Check that this is a splat.
7256 while (--RemainInsertElts) {
7257 SDValue NextInsertElt = StVal.getOperand(0);
7258 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7260 if (NextInsertElt.getOperand(1) != SplatVal)
7262 StVal = NextInsertElt;
7264 unsigned OrigAlignment = St->getAlignment();
7265 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7266 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7268 // Create scalar stores. This is at least as good as the code sequence for a
7269 // split unaligned store wich is a dup.s, ext.b, and two stores.
7270 // Most of the time the three stores should be replaced by store pair
7271 // instructions (stp).
7273 SDValue BasePtr = St->getBasePtr();
7275 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7276 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7278 unsigned Offset = EltOffset;
7279 while (--NumVecElts) {
7280 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7281 DAG.getConstant(Offset, MVT::i64));
7282 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7283 St->getPointerInfo(), St->isVolatile(),
7284 St->isNonTemporal(), Alignment);
7285 Offset += EltOffset;
7290 static SDValue performSTORECombine(SDNode *N,
7291 TargetLowering::DAGCombinerInfo &DCI,
7293 const AArch64Subtarget *Subtarget) {
7294 if (!DCI.isBeforeLegalize())
7297 StoreSDNode *S = cast<StoreSDNode>(N);
7298 if (S->isVolatile())
7301 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7302 // page boundries. We want to split such stores.
7303 if (!Subtarget->isCyclone())
7306 // Don't split at Oz.
7307 MachineFunction &MF = DAG.getMachineFunction();
7308 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7309 AttributeSet::FunctionIndex, Attribute::MinSize);
7313 SDValue StVal = S->getValue();
7314 EVT VT = StVal.getValueType();
7316 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7317 // those up regresses performance on micro-benchmarks and olden/bh.
7318 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7321 // Split unaligned 16B stores. They are terrible for performance.
7322 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7323 // extensions can use this to mark that it does not want splitting to happen
7324 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7325 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7326 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7327 S->getAlignment() <= 2)
7330 // If we get a splat of a scalar convert this vector store to a store of
7331 // scalars. They will be merged into store pairs thereby removing two
7333 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7334 if (ReplacedSplat != SDValue())
7335 return ReplacedSplat;
7338 unsigned NumElts = VT.getVectorNumElements() / 2;
7339 // Split VT into two.
7341 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7342 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7343 DAG.getIntPtrConstant(0));
7344 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7345 DAG.getIntPtrConstant(NumElts));
7346 SDValue BasePtr = S->getBasePtr();
7348 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7349 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7350 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7351 DAG.getConstant(8, MVT::i64));
7352 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7353 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7357 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7358 /// post-increment LD1R.
7359 static SDValue performPostLD1Combine(SDNode *N,
7360 TargetLowering::DAGCombinerInfo &DCI,
7362 if (DCI.isBeforeLegalizeOps())
7365 SelectionDAG &DAG = DCI.DAG;
7366 EVT VT = N->getValueType(0);
7368 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7369 SDNode *LD = N->getOperand(LoadIdx).getNode();
7370 // If it is not LOAD, can not do such combine.
7371 if (LD->getOpcode() != ISD::LOAD)
7374 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7375 EVT MemVT = LoadSDN->getMemoryVT();
7376 // Check if memory operand is the same type as the vector element.
7377 if (MemVT != VT.getVectorElementType())
7380 // Check if there are other uses. If so, do not combine as it will introduce
7382 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7384 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7390 SDValue Addr = LD->getOperand(1);
7391 SDValue Vector = N->getOperand(0);
7392 // Search for a use of the address operand that is an increment.
7393 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7394 Addr.getNode()->use_end(); UI != UE; ++UI) {
7396 if (User->getOpcode() != ISD::ADD
7397 || UI.getUse().getResNo() != Addr.getResNo())
7400 // Check that the add is independent of the load. Otherwise, folding it
7401 // would create a cycle.
7402 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7404 // Also check that add is not used in the vector operand. This would also
7406 if (User->isPredecessorOf(Vector.getNode()))
7409 // If the increment is a constant, it must match the memory ref size.
7410 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7411 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7412 uint32_t IncVal = CInc->getZExtValue();
7413 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7414 if (IncVal != NumBytes)
7416 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7419 SmallVector<SDValue, 8> Ops;
7420 Ops.push_back(LD->getOperand(0)); // Chain
7422 Ops.push_back(Vector); // The vector to be inserted
7423 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7425 Ops.push_back(Addr);
7428 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7429 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7430 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7431 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7433 LoadSDN->getMemOperand());
7436 std::vector<SDValue> NewResults;
7437 NewResults.push_back(SDValue(LD, 0)); // The result of load
7438 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7439 DCI.CombineTo(LD, NewResults);
7440 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7441 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7448 /// Target-specific DAG combine function for NEON load/store intrinsics
7449 /// to merge base address updates.
7450 static SDValue performNEONPostLDSTCombine(SDNode *N,
7451 TargetLowering::DAGCombinerInfo &DCI,
7452 SelectionDAG &DAG) {
7453 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7456 unsigned AddrOpIdx = N->getNumOperands() - 1;
7457 SDValue Addr = N->getOperand(AddrOpIdx);
7459 // Search for a use of the address operand that is an increment.
7460 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7461 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7463 if (User->getOpcode() != ISD::ADD ||
7464 UI.getUse().getResNo() != Addr.getResNo())
7467 // Check that the add is independent of the load/store. Otherwise, folding
7468 // it would create a cycle.
7469 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7472 // Find the new opcode for the updating load/store.
7473 bool IsStore = false;
7474 bool IsLaneOp = false;
7475 bool IsDupOp = false;
7476 unsigned NewOpc = 0;
7477 unsigned NumVecs = 0;
7478 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7480 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7481 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7483 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7485 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7487 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7488 NumVecs = 2; IsStore = true; break;
7489 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7490 NumVecs = 3; IsStore = true; break;
7491 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7492 NumVecs = 4; IsStore = true; break;
7493 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7495 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7497 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7499 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7500 NumVecs = 2; IsStore = true; break;
7501 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7502 NumVecs = 3; IsStore = true; break;
7503 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7504 NumVecs = 4; IsStore = true; break;
7505 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7506 NumVecs = 2; IsDupOp = true; break;
7507 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7508 NumVecs = 3; IsDupOp = true; break;
7509 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7510 NumVecs = 4; IsDupOp = true; break;
7511 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7512 NumVecs = 2; IsLaneOp = true; break;
7513 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7514 NumVecs = 3; IsLaneOp = true; break;
7515 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7516 NumVecs = 4; IsLaneOp = true; break;
7517 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7518 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7519 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7520 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7521 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7522 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7527 VecTy = N->getOperand(2).getValueType();
7529 VecTy = N->getValueType(0);
7531 // If the increment is a constant, it must match the memory ref size.
7532 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7533 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7534 uint32_t IncVal = CInc->getZExtValue();
7535 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7536 if (IsLaneOp || IsDupOp)
7537 NumBytes /= VecTy.getVectorNumElements();
7538 if (IncVal != NumBytes)
7540 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7542 SmallVector<SDValue, 8> Ops;
7543 Ops.push_back(N->getOperand(0)); // Incoming chain
7544 // Load lane and store have vector list as input.
7545 if (IsLaneOp || IsStore)
7546 for (unsigned i = 2; i < AddrOpIdx; ++i)
7547 Ops.push_back(N->getOperand(i));
7548 Ops.push_back(Addr); // Base register
7553 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7555 for (n = 0; n < NumResultVecs; ++n)
7557 Tys[n++] = MVT::i64; // Type of write back register
7558 Tys[n] = MVT::Other; // Type of the chain
7559 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7561 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7562 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7563 MemInt->getMemoryVT(),
7564 MemInt->getMemOperand());
7567 std::vector<SDValue> NewResults;
7568 for (unsigned i = 0; i < NumResultVecs; ++i) {
7569 NewResults.push_back(SDValue(UpdN.getNode(), i));
7571 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7572 DCI.CombineTo(N, NewResults);
7573 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7580 // Optimize compare with zero and branch.
7581 static SDValue performBRCONDCombine(SDNode *N,
7582 TargetLowering::DAGCombinerInfo &DCI,
7583 SelectionDAG &DAG) {
7584 SDValue Chain = N->getOperand(0);
7585 SDValue Dest = N->getOperand(1);
7586 SDValue CCVal = N->getOperand(2);
7587 SDValue Cmp = N->getOperand(3);
7589 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7590 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7591 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7594 unsigned CmpOpc = Cmp.getOpcode();
7595 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7598 // Only attempt folding if there is only one use of the flag and no use of the
7600 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7603 SDValue LHS = Cmp.getOperand(0);
7604 SDValue RHS = Cmp.getOperand(1);
7606 assert(LHS.getValueType() == RHS.getValueType() &&
7607 "Expected the value type to be the same for both operands!");
7608 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7611 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7612 std::swap(LHS, RHS);
7614 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7617 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7618 LHS.getOpcode() == ISD::SRL)
7621 // Fold the compare into the branch instruction.
7623 if (CC == AArch64CC::EQ)
7624 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7626 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7628 // Do not add new nodes to DAG combiner worklist.
7629 DCI.CombineTo(N, BR, false);
7634 // vselect (v1i1 setcc) ->
7635 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7636 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7637 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7639 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7640 SDValue N0 = N->getOperand(0);
7641 EVT CCVT = N0.getValueType();
7643 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7644 CCVT.getVectorElementType() != MVT::i1)
7647 EVT ResVT = N->getValueType(0);
7648 EVT CmpVT = N0.getOperand(0).getValueType();
7649 // Only combine when the result type is of the same size as the compared
7651 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7654 SDValue IfTrue = N->getOperand(1);
7655 SDValue IfFalse = N->getOperand(2);
7657 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7658 N0.getOperand(0), N0.getOperand(1),
7659 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7660 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7664 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7665 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7666 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7667 /// with a vector one followed by a DUP shuffle on the result.
7668 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7669 SDValue N0 = N->getOperand(0);
7670 EVT ResVT = N->getValueType(0);
7672 if (!N->getOperand(1).getValueType().isVector())
7675 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7680 EVT SrcVT = N0.getOperand(0).getValueType();
7681 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7682 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7683 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7685 // First perform a vector comparison, where lane 0 is the one we're interested
7688 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7690 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7691 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7693 // Now duplicate the comparison mask we want across all other lanes.
7694 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7695 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7696 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7699 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7702 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7703 DAGCombinerInfo &DCI) const {
7704 SelectionDAG &DAG = DCI.DAG;
7705 switch (N->getOpcode()) {
7710 return performAddSubLongCombine(N, DCI, DAG);
7712 return performXorCombine(N, DAG, DCI, Subtarget);
7714 return performMulCombine(N, DAG, DCI, Subtarget);
7715 case ISD::SINT_TO_FP:
7716 case ISD::UINT_TO_FP:
7717 return performIntToFpCombine(N, DAG);
7719 return performORCombine(N, DCI, Subtarget);
7720 case ISD::INTRINSIC_WO_CHAIN:
7721 return performIntrinsicCombine(N, DCI, Subtarget);
7722 case ISD::ANY_EXTEND:
7723 case ISD::ZERO_EXTEND:
7724 case ISD::SIGN_EXTEND:
7725 return performExtendCombine(N, DCI, DAG);
7727 return performBitcastCombine(N, DCI, DAG);
7728 case ISD::CONCAT_VECTORS:
7729 return performConcatVectorsCombine(N, DCI, DAG);
7731 return performSelectCombine(N, DAG);
7733 return performVSelectCombine(N, DCI.DAG);
7735 return performSTORECombine(N, DCI, DAG, Subtarget);
7736 case AArch64ISD::BRCOND:
7737 return performBRCONDCombine(N, DCI, DAG);
7738 case AArch64ISD::DUP:
7739 return performPostLD1Combine(N, DCI, false);
7740 case ISD::INSERT_VECTOR_ELT:
7741 return performPostLD1Combine(N, DCI, true);
7742 case ISD::INTRINSIC_VOID:
7743 case ISD::INTRINSIC_W_CHAIN:
7744 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7745 case Intrinsic::aarch64_neon_ld2:
7746 case Intrinsic::aarch64_neon_ld3:
7747 case Intrinsic::aarch64_neon_ld4:
7748 case Intrinsic::aarch64_neon_ld1x2:
7749 case Intrinsic::aarch64_neon_ld1x3:
7750 case Intrinsic::aarch64_neon_ld1x4:
7751 case Intrinsic::aarch64_neon_ld2lane:
7752 case Intrinsic::aarch64_neon_ld3lane:
7753 case Intrinsic::aarch64_neon_ld4lane:
7754 case Intrinsic::aarch64_neon_ld2r:
7755 case Intrinsic::aarch64_neon_ld3r:
7756 case Intrinsic::aarch64_neon_ld4r:
7757 case Intrinsic::aarch64_neon_st2:
7758 case Intrinsic::aarch64_neon_st3:
7759 case Intrinsic::aarch64_neon_st4:
7760 case Intrinsic::aarch64_neon_st1x2:
7761 case Intrinsic::aarch64_neon_st1x3:
7762 case Intrinsic::aarch64_neon_st1x4:
7763 case Intrinsic::aarch64_neon_st2lane:
7764 case Intrinsic::aarch64_neon_st3lane:
7765 case Intrinsic::aarch64_neon_st4lane:
7766 return performNEONPostLDSTCombine(N, DCI, DAG);
7774 // Check if the return value is used as only a return value, as otherwise
7775 // we can't perform a tail-call. In particular, we need to check for
7776 // target ISD nodes that are returns and any other "odd" constructs
7777 // that the generic analysis code won't necessarily catch.
7778 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7779 SDValue &Chain) const {
7780 if (N->getNumValues() != 1)
7782 if (!N->hasNUsesOfValue(1, 0))
7785 SDValue TCChain = Chain;
7786 SDNode *Copy = *N->use_begin();
7787 if (Copy->getOpcode() == ISD::CopyToReg) {
7788 // If the copy has a glue operand, we conservatively assume it isn't safe to
7789 // perform a tail call.
7790 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7793 TCChain = Copy->getOperand(0);
7794 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7797 bool HasRet = false;
7798 for (SDNode *Node : Copy->uses()) {
7799 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7811 // Return whether the an instruction can potentially be optimized to a tail
7812 // call. This will cause the optimizers to attempt to move, or duplicate,
7813 // return instructions to help enable tail call optimizations for this
7815 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7816 if (!CI->isTailCall())
7822 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7824 ISD::MemIndexedMode &AM,
7826 SelectionDAG &DAG) const {
7827 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7830 Base = Op->getOperand(0);
7831 // All of the indexed addressing mode instructions take a signed
7832 // 9 bit immediate offset.
7833 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7834 int64_t RHSC = (int64_t)RHS->getZExtValue();
7835 if (RHSC >= 256 || RHSC <= -256)
7837 IsInc = (Op->getOpcode() == ISD::ADD);
7838 Offset = Op->getOperand(1);
7844 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7846 ISD::MemIndexedMode &AM,
7847 SelectionDAG &DAG) const {
7850 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7851 VT = LD->getMemoryVT();
7852 Ptr = LD->getBasePtr();
7853 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7854 VT = ST->getMemoryVT();
7855 Ptr = ST->getBasePtr();
7860 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7862 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7866 bool AArch64TargetLowering::getPostIndexedAddressParts(
7867 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7868 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7871 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7872 VT = LD->getMemoryVT();
7873 Ptr = LD->getBasePtr();
7874 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7875 VT = ST->getMemoryVT();
7876 Ptr = ST->getBasePtr();
7881 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7883 // Post-indexing updates the base, so it's not a valid transform
7884 // if that's not the same as the load's pointer.
7887 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7891 void AArch64TargetLowering::ReplaceNodeResults(
7892 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
7893 switch (N->getOpcode()) {
7895 llvm_unreachable("Don't know how to custom expand this");
7896 case ISD::FP_TO_UINT:
7897 case ISD::FP_TO_SINT:
7898 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7899 // Let normal code take care of it by not adding anything to Results.
7904 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7905 // Loads and stores less than 128-bits are already atomic; ones above that
7906 // are doomed anyway, so defer to the default libcall and blame the OS when
7908 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7909 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7910 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7911 return LI->getType()->getPrimitiveSizeInBits() == 128;
7913 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7914 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7917 TargetLoweringBase::LegalizeTypeAction
7918 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
7919 MVT SVT = VT.getSimpleVT();
7920 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
7921 // v4i16, v2i32 instead of to promote.
7922 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
7923 || SVT == MVT::v1f32)
7924 return TypeWidenVector;
7926 return TargetLoweringBase::getPreferredVectorAction(VT);
7929 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7930 AtomicOrdering Ord) const {
7931 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7932 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7934 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7936 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7937 // intrinsic must return {i64, i64} and we have to recombine them into a
7938 // single i128 here.
7939 if (ValTy->getPrimitiveSizeInBits() == 128) {
7941 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
7942 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7944 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7945 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
7947 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
7948 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
7949 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
7950 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
7951 return Builder.CreateOr(
7952 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
7955 Type *Tys[] = { Addr->getType() };
7957 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
7958 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
7960 return Builder.CreateTruncOrBitCast(
7961 Builder.CreateCall(Ldxr, Addr),
7962 cast<PointerType>(Addr->getType())->getElementType());
7965 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
7966 Value *Val, Value *Addr,
7967 AtomicOrdering Ord) const {
7968 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7970 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7972 // Since the intrinsics must have legal type, the i128 intrinsics take two
7973 // parameters: "i64, i64". We must marshal Val into the appropriate form
7975 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
7977 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
7978 Function *Stxr = Intrinsic::getDeclaration(M, Int);
7979 Type *Int64Ty = Type::getInt64Ty(M->getContext());
7981 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
7982 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
7983 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7984 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
7988 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
7989 Type *Tys[] = { Addr->getType() };
7990 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
7992 return Builder.CreateCall2(
7993 Stxr, Builder.CreateZExtOrBitCast(
7994 Val, Stxr->getFunctionType()->getParamType(0)),