1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
50 static cl::opt<AlignMode>
51 Align(cl::desc("Load/store alignment support"),
52 cl::Hidden, cl::init(NoStrictAlign),
54 clEnumValN(StrictAlign, "aarch64-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
57 "Allow unaligned memory accesses"),
60 // Place holder until extr generation is tested fully.
62 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
63 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
67 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
68 cl::desc("Allow AArch64 SLI/SRI formation"),
71 // FIXME: The necessary dtprel relocations don't seem to be supported
72 // well in the GNU bfd and gold linkers at the moment. Therefore, by
73 // default, for now, fall back to GeneralDynamic code generation.
74 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
75 "aarch64-elf-ldtls-generation", cl::Hidden,
76 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
79 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
80 const AArch64Subtarget &STI)
81 : TargetLowering(TM), Subtarget(&STI) {
83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
84 // we have to make something up. Arbitrarily, choose ZeroOrOne.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // When comparing vectors the result sets the different elements in the
87 // vector to all-one or all-zero.
88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
90 // Set up the register classes.
91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
94 if (Subtarget->hasFPARMv8()) {
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
101 if (Subtarget->hasNEON()) {
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
104 // Someone set us up the NEON.
105 addDRTypeForNEON(MVT::v2f32);
106 addDRTypeForNEON(MVT::v8i8);
107 addDRTypeForNEON(MVT::v4i16);
108 addDRTypeForNEON(MVT::v2i32);
109 addDRTypeForNEON(MVT::v1i64);
110 addDRTypeForNEON(MVT::v1f64);
111 addDRTypeForNEON(MVT::v4f16);
113 addQRTypeForNEON(MVT::v4f32);
114 addQRTypeForNEON(MVT::v2f64);
115 addQRTypeForNEON(MVT::v16i8);
116 addQRTypeForNEON(MVT::v8i16);
117 addQRTypeForNEON(MVT::v4i32);
118 addQRTypeForNEON(MVT::v2i64);
119 addQRTypeForNEON(MVT::v8f16);
122 // Compute derived properties from the register classes
123 computeRegisterProperties(Subtarget->getRegisterInfo());
125 // Provide all sorts of operation actions
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
128 setOperationAction(ISD::SETCC, MVT::i32, Custom);
129 setOperationAction(ISD::SETCC, MVT::i64, Custom);
130 setOperationAction(ISD::SETCC, MVT::f32, Custom);
131 setOperationAction(ISD::SETCC, MVT::f64, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::FREM, MVT::f32, Expand);
153 setOperationAction(ISD::FREM, MVT::f64, Expand);
154 setOperationAction(ISD::FREM, MVT::f80, Expand);
156 // Custom lowering hooks are needed for XOR
157 // to fold it into CSINC/CSINV.
158 setOperationAction(ISD::XOR, MVT::i32, Custom);
159 setOperationAction(ISD::XOR, MVT::i64, Custom);
161 // Virtually no operation on f128 is legal, but LLVM can't expand them when
162 // there's a valid register class, so we need custom operations in most cases.
163 setOperationAction(ISD::FABS, MVT::f128, Expand);
164 setOperationAction(ISD::FADD, MVT::f128, Custom);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
166 setOperationAction(ISD::FCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FDIV, MVT::f128, Custom);
168 setOperationAction(ISD::FMA, MVT::f128, Expand);
169 setOperationAction(ISD::FMUL, MVT::f128, Custom);
170 setOperationAction(ISD::FNEG, MVT::f128, Expand);
171 setOperationAction(ISD::FPOW, MVT::f128, Expand);
172 setOperationAction(ISD::FREM, MVT::f128, Expand);
173 setOperationAction(ISD::FRINT, MVT::f128, Expand);
174 setOperationAction(ISD::FSIN, MVT::f128, Expand);
175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
176 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
177 setOperationAction(ISD::FSUB, MVT::f128, Custom);
178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
179 setOperationAction(ISD::SETCC, MVT::f128, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT, MVT::f128, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
185 // Lowering for many of the conversions is actually specified by the non-f128
186 // type. The LowerXXX function will be trivial when f128 isn't involved.
187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
202 // Variable arguments.
203 setOperationAction(ISD::VASTART, MVT::Other, Custom);
204 setOperationAction(ISD::VAARG, MVT::Other, Custom);
205 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
206 setOperationAction(ISD::VAEND, MVT::Other, Expand);
208 // Variable-sized objects.
209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
213 // Exception handling.
214 // FIXME: These are guesses. Has this been defined yet?
215 setExceptionPointerRegister(AArch64::X0);
216 setExceptionSelectorRegister(AArch64::X1);
218 // Constant pool entries
219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
225 setOperationAction(ISD::ADDC, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i32, Custom);
227 setOperationAction(ISD::SUBC, MVT::i32, Custom);
228 setOperationAction(ISD::SUBE, MVT::i32, Custom);
229 setOperationAction(ISD::ADDC, MVT::i64, Custom);
230 setOperationAction(ISD::ADDE, MVT::i64, Custom);
231 setOperationAction(ISD::SUBC, MVT::i64, Custom);
232 setOperationAction(ISD::SUBE, MVT::i64, Custom);
234 // AArch64 lacks both left-rotate and popcount instructions.
235 setOperationAction(ISD::ROTL, MVT::i32, Expand);
236 setOperationAction(ISD::ROTL, MVT::i64, Expand);
238 // AArch64 doesn't have {U|S}MUL_LOHI.
239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
244 // counterparts, which AArch64 supports directly.
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
251 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
256 setOperationAction(ISD::SREM, MVT::i64, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i32, Expand);
260 setOperationAction(ISD::UREM, MVT::i64, Expand);
262 // Custom lower Add/Sub/Mul with overflow.
263 setOperationAction(ISD::SADDO, MVT::i32, Custom);
264 setOperationAction(ISD::SADDO, MVT::i64, Custom);
265 setOperationAction(ISD::UADDO, MVT::i32, Custom);
266 setOperationAction(ISD::UADDO, MVT::i64, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
268 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
269 setOperationAction(ISD::USUBO, MVT::i32, Custom);
270 setOperationAction(ISD::USUBO, MVT::i64, Custom);
271 setOperationAction(ISD::SMULO, MVT::i32, Custom);
272 setOperationAction(ISD::SMULO, MVT::i64, Custom);
273 setOperationAction(ISD::UMULO, MVT::i32, Custom);
274 setOperationAction(ISD::UMULO, MVT::i64, Custom);
276 setOperationAction(ISD::FSIN, MVT::f32, Expand);
277 setOperationAction(ISD::FSIN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FCOS, MVT::f64, Expand);
280 setOperationAction(ISD::FPOW, MVT::f32, Expand);
281 setOperationAction(ISD::FPOW, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285 // f16 is a storage-only type, always promote it to f32.
286 setOperationAction(ISD::SETCC, MVT::f16, Promote);
287 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
289 setOperationAction(ISD::SELECT, MVT::f16, Promote);
290 setOperationAction(ISD::FADD, MVT::f16, Promote);
291 setOperationAction(ISD::FSUB, MVT::f16, Promote);
292 setOperationAction(ISD::FMUL, MVT::f16, Promote);
293 setOperationAction(ISD::FDIV, MVT::f16, Promote);
294 setOperationAction(ISD::FREM, MVT::f16, Promote);
295 setOperationAction(ISD::FMA, MVT::f16, Promote);
296 setOperationAction(ISD::FNEG, MVT::f16, Promote);
297 setOperationAction(ISD::FABS, MVT::f16, Promote);
298 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
299 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
300 setOperationAction(ISD::FCOS, MVT::f16, Promote);
301 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
302 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
303 setOperationAction(ISD::FPOW, MVT::f16, Promote);
304 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
305 setOperationAction(ISD::FRINT, MVT::f16, Promote);
306 setOperationAction(ISD::FSIN, MVT::f16, Promote);
307 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
308 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
309 setOperationAction(ISD::FEXP, MVT::f16, Promote);
310 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
311 setOperationAction(ISD::FLOG, MVT::f16, Promote);
312 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
313 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
314 setOperationAction(ISD::FROUND, MVT::f16, Promote);
315 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
316 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
317 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
319 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
321 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
322 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
323 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
324 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
325 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
326 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
327 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
332 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
334 // Expand all other v4f16 operations.
335 // FIXME: We could generate better code by promoting some operations to
337 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
338 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
339 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
340 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
341 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
342 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
343 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
344 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
345 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
346 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
347 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
348 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
349 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
350 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
351 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
352 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
353 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
354 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
355 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
356 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
357 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
358 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
359 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
360 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
361 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
362 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
365 // v8f16 is also a storage-only type, so expand it.
366 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
367 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
368 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
369 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
370 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
371 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
372 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
373 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
374 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
375 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
376 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
377 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
378 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
379 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
380 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
381 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
382 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
383 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
384 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
385 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
386 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
387 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
388 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
389 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
390 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
391 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
392 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
393 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
394 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
395 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
396 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
398 // AArch64 has implementations of a lot of rounding-like FP operations.
399 for (MVT Ty : {MVT::f32, MVT::f64}) {
400 setOperationAction(ISD::FFLOOR, Ty, Legal);
401 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
402 setOperationAction(ISD::FCEIL, Ty, Legal);
403 setOperationAction(ISD::FRINT, Ty, Legal);
404 setOperationAction(ISD::FTRUNC, Ty, Legal);
405 setOperationAction(ISD::FROUND, Ty, Legal);
408 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
410 if (Subtarget->isTargetMachO()) {
411 // For iOS, we don't want to the normal expansion of a libcall to
412 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
414 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
415 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
417 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
418 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
421 // Make floating-point constants legal for the large code model, so they don't
422 // become loads from the constant pool.
423 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
424 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
425 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
428 // AArch64 does not have floating-point extending loads, i1 sign-extending
429 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
430 for (MVT VT : MVT::fp_valuetypes()) {
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
434 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
436 for (MVT VT : MVT::integer_valuetypes())
437 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
439 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
440 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
441 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
443 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
444 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
445 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
447 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
448 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
450 // Indexed loads and stores are supported.
451 for (unsigned im = (unsigned)ISD::PRE_INC;
452 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
453 setIndexedLoadAction(im, MVT::i8, Legal);
454 setIndexedLoadAction(im, MVT::i16, Legal);
455 setIndexedLoadAction(im, MVT::i32, Legal);
456 setIndexedLoadAction(im, MVT::i64, Legal);
457 setIndexedLoadAction(im, MVT::f64, Legal);
458 setIndexedLoadAction(im, MVT::f32, Legal);
459 setIndexedStoreAction(im, MVT::i8, Legal);
460 setIndexedStoreAction(im, MVT::i16, Legal);
461 setIndexedStoreAction(im, MVT::i32, Legal);
462 setIndexedStoreAction(im, MVT::i64, Legal);
463 setIndexedStoreAction(im, MVT::f64, Legal);
464 setIndexedStoreAction(im, MVT::f32, Legal);
468 setOperationAction(ISD::TRAP, MVT::Other, Legal);
470 // We combine OR nodes for bitfield operations.
471 setTargetDAGCombine(ISD::OR);
473 // Vector add and sub nodes may conceal a high-half opportunity.
474 // Also, try to fold ADD into CSINC/CSINV..
475 setTargetDAGCombine(ISD::ADD);
476 setTargetDAGCombine(ISD::SUB);
478 setTargetDAGCombine(ISD::XOR);
479 setTargetDAGCombine(ISD::SINT_TO_FP);
480 setTargetDAGCombine(ISD::UINT_TO_FP);
482 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
484 setTargetDAGCombine(ISD::ANY_EXTEND);
485 setTargetDAGCombine(ISD::ZERO_EXTEND);
486 setTargetDAGCombine(ISD::SIGN_EXTEND);
487 setTargetDAGCombine(ISD::BITCAST);
488 setTargetDAGCombine(ISD::CONCAT_VECTORS);
489 setTargetDAGCombine(ISD::STORE);
491 setTargetDAGCombine(ISD::MUL);
493 setTargetDAGCombine(ISD::SELECT);
494 setTargetDAGCombine(ISD::VSELECT);
495 setTargetDAGCombine(ISD::SELECT_CC);
497 setTargetDAGCombine(ISD::INTRINSIC_VOID);
498 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
499 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
501 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
502 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
503 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
505 setStackPointerRegisterToSaveRestore(AArch64::SP);
507 setSchedulingPreference(Sched::Hybrid);
510 MaskAndBranchFoldingIsLegal = true;
511 EnableExtLdPromotion = true;
513 setMinFunctionAlignment(2);
515 RequireStrictAlign = (Align == StrictAlign);
517 setHasExtractBitsInsn(true);
519 if (Subtarget->hasNEON()) {
520 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
521 // silliness like this:
522 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
523 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
524 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
525 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
526 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
527 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
528 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
529 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
530 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
531 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
532 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
533 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
534 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
535 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
536 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
537 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
538 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
539 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
540 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
541 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
542 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
543 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
544 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
545 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
546 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
548 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
549 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
550 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
551 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
552 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
554 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
556 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
557 // elements smaller than i32, so promote the input to i32 first.
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
561 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
562 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
563 // -> v8f16 conversions.
564 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
565 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
566 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
567 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
568 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
569 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
570 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
571 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
572 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
573 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
574 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
575 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
576 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
578 // AArch64 doesn't have MUL.2d:
579 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
580 // Custom handling for some quad-vector types to detect MULL.
581 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
582 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
583 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
585 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
586 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
587 // Likewise, narrowing and extending vector loads/stores aren't handled
589 for (MVT VT : MVT::vector_valuetypes()) {
590 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
592 setOperationAction(ISD::MULHS, VT, Expand);
593 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
594 setOperationAction(ISD::MULHU, VT, Expand);
595 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
597 setOperationAction(ISD::BSWAP, VT, Expand);
599 for (MVT InnerVT : MVT::vector_valuetypes()) {
600 setTruncStoreAction(VT, InnerVT, Expand);
601 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
602 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
603 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
607 // AArch64 has implementations of a lot of rounding-like FP operations.
608 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
609 setOperationAction(ISD::FFLOOR, Ty, Legal);
610 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
611 setOperationAction(ISD::FCEIL, Ty, Legal);
612 setOperationAction(ISD::FRINT, Ty, Legal);
613 setOperationAction(ISD::FTRUNC, Ty, Legal);
614 setOperationAction(ISD::FROUND, Ty, Legal);
618 // Prefer likely predicted branches to selects on out-of-order cores.
619 if (Subtarget->isCortexA57())
620 PredictableSelectIsExpensive = true;
623 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
624 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
625 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
626 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
628 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
629 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
630 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
631 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
632 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
634 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
635 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
638 // Mark vector float intrinsics as expand.
639 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
640 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
645 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
647 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
648 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
651 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
653 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
654 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
655 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
656 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
661 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
662 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
664 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
665 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
666 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
667 for (MVT InnerVT : MVT::all_valuetypes())
668 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
670 // CNT supports only B element sizes.
671 if (VT != MVT::v8i8 && VT != MVT::v16i8)
672 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
674 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
675 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
676 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
677 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
678 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
680 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
681 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
683 // [SU][MIN|MAX] are available for all NEON types apart from i64.
684 if (!VT.isFloatingPoint() &&
685 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
686 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
687 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
689 if (Subtarget->isLittleEndian()) {
690 for (unsigned im = (unsigned)ISD::PRE_INC;
691 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
692 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
693 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
698 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
699 addRegisterClass(VT, &AArch64::FPR64RegClass);
700 addTypeForNEON(VT, MVT::v2i32);
703 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
704 addRegisterClass(VT, &AArch64::FPR128RegClass);
705 addTypeForNEON(VT, MVT::v4i32);
708 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
711 return VT.changeVectorElementTypeToInteger();
714 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
715 /// Mask are known to be either zero or one and return them in the
716 /// KnownZero/KnownOne bitsets.
717 void AArch64TargetLowering::computeKnownBitsForTargetNode(
718 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
719 const SelectionDAG &DAG, unsigned Depth) const {
720 switch (Op.getOpcode()) {
723 case AArch64ISD::CSEL: {
724 APInt KnownZero2, KnownOne2;
725 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
726 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
727 KnownZero &= KnownZero2;
728 KnownOne &= KnownOne2;
731 case ISD::INTRINSIC_W_CHAIN: {
732 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
733 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
736 case Intrinsic::aarch64_ldaxr:
737 case Intrinsic::aarch64_ldxr: {
738 unsigned BitWidth = KnownOne.getBitWidth();
739 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
740 unsigned MemBits = VT.getScalarType().getSizeInBits();
741 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
747 case ISD::INTRINSIC_WO_CHAIN:
748 case ISD::INTRINSIC_VOID: {
749 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
753 case Intrinsic::aarch64_neon_umaxv:
754 case Intrinsic::aarch64_neon_uminv: {
755 // Figure out the datatype of the vector operand. The UMINV instruction
756 // will zero extend the result, so we can mark as known zero all the
757 // bits larger than the element datatype. 32-bit or larget doesn't need
758 // this as those are legal types and will be handled by isel directly.
759 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
760 unsigned BitWidth = KnownZero.getBitWidth();
761 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
762 assert(BitWidth >= 8 && "Unexpected width!");
763 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
765 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
766 assert(BitWidth >= 16 && "Unexpected width!");
767 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
777 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
782 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
783 const TargetLibraryInfo *libInfo) const {
784 return AArch64::createFastISel(funcInfo, libInfo);
787 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
788 switch ((AArch64ISD::NodeType)Opcode) {
789 case AArch64ISD::FIRST_NUMBER: break;
790 case AArch64ISD::CALL: return "AArch64ISD::CALL";
791 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
792 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
793 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
794 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
795 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
796 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
797 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
798 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
799 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
800 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
801 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
802 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
803 case AArch64ISD::ADC: return "AArch64ISD::ADC";
804 case AArch64ISD::SBC: return "AArch64ISD::SBC";
805 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
806 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
807 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
808 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
809 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
810 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
811 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
812 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
813 case AArch64ISD::DUP: return "AArch64ISD::DUP";
814 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
815 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
816 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
817 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
818 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
819 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
820 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
821 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
822 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
823 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
824 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
825 case AArch64ISD::BICi: return "AArch64ISD::BICi";
826 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
827 case AArch64ISD::BSL: return "AArch64ISD::BSL";
828 case AArch64ISD::NEG: return "AArch64ISD::NEG";
829 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
830 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
831 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
832 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
833 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
834 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
835 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
836 case AArch64ISD::REV16: return "AArch64ISD::REV16";
837 case AArch64ISD::REV32: return "AArch64ISD::REV32";
838 case AArch64ISD::REV64: return "AArch64ISD::REV64";
839 case AArch64ISD::EXT: return "AArch64ISD::EXT";
840 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
841 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
842 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
843 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
844 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
845 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
846 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
847 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
848 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
849 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
850 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
851 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
852 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
853 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
854 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
855 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
856 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
857 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
858 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
859 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
860 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
861 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
862 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
863 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
864 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
865 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
866 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
867 case AArch64ISD::NOT: return "AArch64ISD::NOT";
868 case AArch64ISD::BIT: return "AArch64ISD::BIT";
869 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
870 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
871 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
872 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
873 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
874 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
875 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
876 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
877 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
878 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
879 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
880 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
881 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
882 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
883 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
884 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
885 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
886 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
887 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
888 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
889 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
890 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
891 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
892 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
893 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
894 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
895 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
896 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
897 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
898 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
899 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
900 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
901 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
902 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
903 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
904 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
905 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
906 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
907 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
908 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
914 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
915 MachineBasicBlock *MBB) const {
916 // We materialise the F128CSEL pseudo-instruction as some control flow and a
920 // [... previous instrs leading to comparison ...]
926 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
928 MachineFunction *MF = MBB->getParent();
929 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
930 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
931 DebugLoc DL = MI->getDebugLoc();
932 MachineFunction::iterator It = MBB;
935 unsigned DestReg = MI->getOperand(0).getReg();
936 unsigned IfTrueReg = MI->getOperand(1).getReg();
937 unsigned IfFalseReg = MI->getOperand(2).getReg();
938 unsigned CondCode = MI->getOperand(3).getImm();
939 bool NZCVKilled = MI->getOperand(4).isKill();
941 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
942 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
943 MF->insert(It, TrueBB);
944 MF->insert(It, EndBB);
946 // Transfer rest of current basic-block to EndBB
947 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
949 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
951 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
952 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
953 MBB->addSuccessor(TrueBB);
954 MBB->addSuccessor(EndBB);
956 // TrueBB falls through to the end.
957 TrueBB->addSuccessor(EndBB);
960 TrueBB->addLiveIn(AArch64::NZCV);
961 EndBB->addLiveIn(AArch64::NZCV);
964 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
970 MI->eraseFromParent();
975 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
976 MachineBasicBlock *BB) const {
977 switch (MI->getOpcode()) {
982 llvm_unreachable("Unexpected instruction for custom inserter!");
984 case AArch64::F128CSEL:
985 return EmitF128CSEL(MI, BB);
987 case TargetOpcode::STACKMAP:
988 case TargetOpcode::PATCHPOINT:
989 return emitPatchPoint(MI, BB);
993 //===----------------------------------------------------------------------===//
994 // AArch64 Lowering private implementation.
995 //===----------------------------------------------------------------------===//
997 //===----------------------------------------------------------------------===//
999 //===----------------------------------------------------------------------===//
1001 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1003 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1006 llvm_unreachable("Unknown condition code!");
1008 return AArch64CC::NE;
1010 return AArch64CC::EQ;
1012 return AArch64CC::GT;
1014 return AArch64CC::GE;
1016 return AArch64CC::LT;
1018 return AArch64CC::LE;
1020 return AArch64CC::HI;
1022 return AArch64CC::HS;
1024 return AArch64CC::LO;
1026 return AArch64CC::LS;
1030 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1031 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1032 AArch64CC::CondCode &CondCode,
1033 AArch64CC::CondCode &CondCode2) {
1034 CondCode2 = AArch64CC::AL;
1037 llvm_unreachable("Unknown FP condition!");
1040 CondCode = AArch64CC::EQ;
1044 CondCode = AArch64CC::GT;
1048 CondCode = AArch64CC::GE;
1051 CondCode = AArch64CC::MI;
1054 CondCode = AArch64CC::LS;
1057 CondCode = AArch64CC::MI;
1058 CondCode2 = AArch64CC::GT;
1061 CondCode = AArch64CC::VC;
1064 CondCode = AArch64CC::VS;
1067 CondCode = AArch64CC::EQ;
1068 CondCode2 = AArch64CC::VS;
1071 CondCode = AArch64CC::HI;
1074 CondCode = AArch64CC::PL;
1078 CondCode = AArch64CC::LT;
1082 CondCode = AArch64CC::LE;
1086 CondCode = AArch64CC::NE;
1091 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1092 /// CC usable with the vector instructions. Fewer operations are available
1093 /// without a real NZCV register, so we have to use less efficient combinations
1094 /// to get the same effect.
1095 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1096 AArch64CC::CondCode &CondCode,
1097 AArch64CC::CondCode &CondCode2,
1102 // Mostly the scalar mappings work fine.
1103 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1106 Invert = true; // Fallthrough
1108 CondCode = AArch64CC::MI;
1109 CondCode2 = AArch64CC::GE;
1116 // All of the compare-mask comparisons are ordered, but we can switch
1117 // between the two by a double inversion. E.g. ULE == !OGT.
1119 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1124 static bool isLegalArithImmed(uint64_t C) {
1125 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1126 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1129 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1130 SDLoc dl, SelectionDAG &DAG) {
1131 EVT VT = LHS.getValueType();
1133 if (VT.isFloatingPoint())
1134 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1136 // The CMP instruction is just an alias for SUBS, and representing it as
1137 // SUBS means that it's possible to get CSE with subtract operations.
1138 // A later phase can perform the optimization of setting the destination
1139 // register to WZR/XZR if it ends up being unused.
1140 unsigned Opcode = AArch64ISD::SUBS;
1142 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1143 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1144 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1145 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1146 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1147 // can be set differently by this operation. It comes down to whether
1148 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1149 // everything is fine. If not then the optimization is wrong. Thus general
1150 // comparisons are only valid if op2 != 0.
1152 // So, finally, the only LLVM-native comparisons that don't mention C and V
1153 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1154 // the absence of information about op2.
1155 Opcode = AArch64ISD::ADDS;
1156 RHS = RHS.getOperand(1);
1157 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1158 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1159 !isUnsignedIntSetCC(CC)) {
1160 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1161 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1162 // of the signed comparisons.
1163 Opcode = AArch64ISD::ANDS;
1164 RHS = LHS.getOperand(1);
1165 LHS = LHS.getOperand(0);
1168 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1172 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1173 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1175 AArch64CC::CondCode AArch64CC;
1176 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1177 EVT VT = RHS.getValueType();
1178 uint64_t C = RHSC->getZExtValue();
1179 if (!isLegalArithImmed(C)) {
1180 // Constant does not fit, try adjusting it by one?
1186 if ((VT == MVT::i32 && C != 0x80000000 &&
1187 isLegalArithImmed((uint32_t)(C - 1))) ||
1188 (VT == MVT::i64 && C != 0x80000000ULL &&
1189 isLegalArithImmed(C - 1ULL))) {
1190 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1191 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1192 RHS = DAG.getConstant(C, dl, VT);
1197 if ((VT == MVT::i32 && C != 0 &&
1198 isLegalArithImmed((uint32_t)(C - 1))) ||
1199 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1200 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1201 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1202 RHS = DAG.getConstant(C, dl, VT);
1207 if ((VT == MVT::i32 && C != INT32_MAX &&
1208 isLegalArithImmed((uint32_t)(C + 1))) ||
1209 (VT == MVT::i64 && C != INT64_MAX &&
1210 isLegalArithImmed(C + 1ULL))) {
1211 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1212 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1213 RHS = DAG.getConstant(C, dl, VT);
1218 if ((VT == MVT::i32 && C != UINT32_MAX &&
1219 isLegalArithImmed((uint32_t)(C + 1))) ||
1220 (VT == MVT::i64 && C != UINT64_MAX &&
1221 isLegalArithImmed(C + 1ULL))) {
1222 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1223 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1224 RHS = DAG.getConstant(C, dl, VT);
1230 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1231 // For the i8 operand, the largest immediate is 255, so this can be easily
1232 // encoded in the compare instruction. For the i16 operand, however, the
1233 // largest immediate cannot be encoded in the compare.
1234 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1235 // constant. For example,
1237 // ldrh w0, [x0, #0]
1240 // ldrsh w0, [x0, #0]
1242 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1243 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1244 // both the LHS and RHS are truely zero extended and to make sure the
1245 // transformation is profitable.
1246 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1247 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1248 isa<LoadSDNode>(LHS)) {
1249 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1250 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1251 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1252 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1253 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1255 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1256 DAG.getValueType(MVT::i16));
1257 Cmp = emitComparison(SExt,
1258 DAG.getConstant(ValueofRHS, dl,
1259 RHS.getValueType()),
1261 AArch64CC = changeIntCCToAArch64CC(CC);
1262 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1268 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1269 AArch64CC = changeIntCCToAArch64CC(CC);
1270 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1274 static std::pair<SDValue, SDValue>
1275 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1276 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1277 "Unsupported value type");
1278 SDValue Value, Overflow;
1280 SDValue LHS = Op.getOperand(0);
1281 SDValue RHS = Op.getOperand(1);
1283 switch (Op.getOpcode()) {
1285 llvm_unreachable("Unknown overflow instruction!");
1287 Opc = AArch64ISD::ADDS;
1291 Opc = AArch64ISD::ADDS;
1295 Opc = AArch64ISD::SUBS;
1299 Opc = AArch64ISD::SUBS;
1302 // Multiply needs a little bit extra work.
1306 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1307 if (Op.getValueType() == MVT::i32) {
1308 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1309 // For a 32 bit multiply with overflow check we want the instruction
1310 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1311 // need to generate the following pattern:
1312 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1313 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1314 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1315 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1316 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1317 DAG.getConstant(0, DL, MVT::i64));
1318 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1319 // operation. We need to clear out the upper 32 bits, because we used a
1320 // widening multiply that wrote all 64 bits. In the end this should be a
1322 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1324 // The signed overflow check requires more than just a simple check for
1325 // any bit set in the upper 32 bits of the result. These bits could be
1326 // just the sign bits of a negative number. To perform the overflow
1327 // check we have to arithmetic shift right the 32nd bit of the result by
1328 // 31 bits. Then we compare the result to the upper 32 bits.
1329 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1330 DAG.getConstant(32, DL, MVT::i64));
1331 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1332 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1333 DAG.getConstant(31, DL, MVT::i64));
1334 // It is important that LowerBits is last, otherwise the arithmetic
1335 // shift will not be folded into the compare (SUBS).
1336 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1337 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1340 // The overflow check for unsigned multiply is easy. We only need to
1341 // check if any of the upper 32 bits are set. This can be done with a
1342 // CMP (shifted register). For that we need to generate the following
1344 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1345 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1346 DAG.getConstant(32, DL, MVT::i64));
1347 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1349 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1350 DAG.getConstant(0, DL, MVT::i64),
1351 UpperBits).getValue(1);
1355 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1356 // For the 64 bit multiply
1357 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1359 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1360 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1361 DAG.getConstant(63, DL, MVT::i64));
1362 // It is important that LowerBits is last, otherwise the arithmetic
1363 // shift will not be folded into the compare (SUBS).
1364 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1365 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1368 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1369 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1371 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1372 DAG.getConstant(0, DL, MVT::i64),
1373 UpperBits).getValue(1);
1380 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1382 // Emit the AArch64 operation with overflow check.
1383 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1384 Overflow = Value.getValue(1);
1386 return std::make_pair(Value, Overflow);
1389 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1390 RTLIB::Libcall Call) const {
1391 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1392 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1396 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1397 SDValue Sel = Op.getOperand(0);
1398 SDValue Other = Op.getOperand(1);
1400 // If neither operand is a SELECT_CC, give up.
1401 if (Sel.getOpcode() != ISD::SELECT_CC)
1402 std::swap(Sel, Other);
1403 if (Sel.getOpcode() != ISD::SELECT_CC)
1406 // The folding we want to perform is:
1407 // (xor x, (select_cc a, b, cc, 0, -1) )
1409 // (csel x, (xor x, -1), cc ...)
1411 // The latter will get matched to a CSINV instruction.
1413 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1414 SDValue LHS = Sel.getOperand(0);
1415 SDValue RHS = Sel.getOperand(1);
1416 SDValue TVal = Sel.getOperand(2);
1417 SDValue FVal = Sel.getOperand(3);
1420 // FIXME: This could be generalized to non-integer comparisons.
1421 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1424 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1425 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1427 // The values aren't constants, this isn't the pattern we're looking for.
1428 if (!CFVal || !CTVal)
1431 // We can commute the SELECT_CC by inverting the condition. This
1432 // might be needed to make this fit into a CSINV pattern.
1433 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1434 std::swap(TVal, FVal);
1435 std::swap(CTVal, CFVal);
1436 CC = ISD::getSetCCInverse(CC, true);
1439 // If the constants line up, perform the transform!
1440 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1442 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1445 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1446 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1448 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1455 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1456 EVT VT = Op.getValueType();
1458 // Let legalize expand this if it isn't a legal type yet.
1459 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1462 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1465 bool ExtraOp = false;
1466 switch (Op.getOpcode()) {
1468 llvm_unreachable("Invalid code");
1470 Opc = AArch64ISD::ADDS;
1473 Opc = AArch64ISD::SUBS;
1476 Opc = AArch64ISD::ADCS;
1480 Opc = AArch64ISD::SBCS;
1486 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1487 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1491 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1492 // Let legalize expand this if it isn't a legal type yet.
1493 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1497 AArch64CC::CondCode CC;
1498 // The actual operation that sets the overflow or carry flag.
1499 SDValue Value, Overflow;
1500 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1502 // We use 0 and 1 as false and true values.
1503 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1504 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1506 // We use an inverted condition, because the conditional select is inverted
1507 // too. This will allow it to be selected to a single instruction:
1508 // CSINC Wd, WZR, WZR, invert(cond).
1509 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1510 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1513 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1514 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1517 // Prefetch operands are:
1518 // 1: Address to prefetch
1520 // 3: int locality (0 = no locality ... 3 = extreme locality)
1521 // 4: bool isDataCache
1522 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1524 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1525 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1526 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1528 bool IsStream = !Locality;
1529 // When the locality number is set
1531 // The front-end should have filtered out the out-of-range values
1532 assert(Locality <= 3 && "Prefetch locality out-of-range");
1533 // The locality degree is the opposite of the cache speed.
1534 // Put the number the other way around.
1535 // The encoding starts at 0 for level 1
1536 Locality = 3 - Locality;
1539 // built the mask value encoding the expected behavior.
1540 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1541 (!IsData << 3) | // IsDataCache bit
1542 (Locality << 1) | // Cache level bits
1543 (unsigned)IsStream; // Stream bit
1544 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1545 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1548 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1549 SelectionDAG &DAG) const {
1550 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1553 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1555 return LowerF128Call(Op, DAG, LC);
1558 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1559 SelectionDAG &DAG) const {
1560 if (Op.getOperand(0).getValueType() != MVT::f128) {
1561 // It's legal except when f128 is involved
1566 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1568 // FP_ROUND node has a second operand indicating whether it is known to be
1569 // precise. That doesn't take part in the LibCall so we can't directly use
1571 SDValue SrcVal = Op.getOperand(0);
1572 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1573 /*isSigned*/ false, SDLoc(Op)).first;
1576 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1577 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1578 // Any additional optimization in this function should be recorded
1579 // in the cost tables.
1580 EVT InVT = Op.getOperand(0).getValueType();
1581 EVT VT = Op.getValueType();
1583 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1586 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1588 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1591 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1594 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1595 VT.getVectorNumElements());
1596 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1597 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1600 // Type changing conversions are illegal.
1604 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1605 SelectionDAG &DAG) const {
1606 if (Op.getOperand(0).getValueType().isVector())
1607 return LowerVectorFP_TO_INT(Op, DAG);
1609 // f16 conversions are promoted to f32.
1610 if (Op.getOperand(0).getValueType() == MVT::f16) {
1613 Op.getOpcode(), dl, Op.getValueType(),
1614 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1617 if (Op.getOperand(0).getValueType() != MVT::f128) {
1618 // It's legal except when f128 is involved
1623 if (Op.getOpcode() == ISD::FP_TO_SINT)
1624 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1626 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1628 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1629 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1633 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1634 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1635 // Any additional optimization in this function should be recorded
1636 // in the cost tables.
1637 EVT VT = Op.getValueType();
1639 SDValue In = Op.getOperand(0);
1640 EVT InVT = In.getValueType();
1642 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1644 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1645 InVT.getVectorNumElements());
1646 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1647 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1650 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1652 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1653 EVT CastVT = VT.changeVectorElementTypeToInteger();
1654 In = DAG.getNode(CastOpc, dl, CastVT, In);
1655 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1661 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1662 SelectionDAG &DAG) const {
1663 if (Op.getValueType().isVector())
1664 return LowerVectorINT_TO_FP(Op, DAG);
1666 // f16 conversions are promoted to f32.
1667 if (Op.getValueType() == MVT::f16) {
1670 ISD::FP_ROUND, dl, MVT::f16,
1671 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1672 DAG.getIntPtrConstant(0, dl));
1675 // i128 conversions are libcalls.
1676 if (Op.getOperand(0).getValueType() == MVT::i128)
1679 // Other conversions are legal, unless it's to the completely software-based
1681 if (Op.getValueType() != MVT::f128)
1685 if (Op.getOpcode() == ISD::SINT_TO_FP)
1686 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1688 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1690 return LowerF128Call(Op, DAG, LC);
1693 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1694 SelectionDAG &DAG) const {
1695 // For iOS, we want to call an alternative entry point: __sincos_stret,
1696 // which returns the values in two S / D registers.
1698 SDValue Arg = Op.getOperand(0);
1699 EVT ArgVT = Arg.getValueType();
1700 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1707 Entry.isSExt = false;
1708 Entry.isZExt = false;
1709 Args.push_back(Entry);
1711 const char *LibcallName =
1712 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1713 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1715 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1716 TargetLowering::CallLoweringInfo CLI(DAG);
1717 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1718 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1720 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1721 return CallResult.first;
1724 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1725 if (Op.getValueType() != MVT::f16)
1728 assert(Op.getOperand(0).getValueType() == MVT::i16);
1731 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1732 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1734 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1735 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1739 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1740 if (OrigVT.getSizeInBits() >= 64)
1743 assert(OrigVT.isSimple() && "Expecting a simple value type");
1745 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1746 switch (OrigSimpleTy) {
1747 default: llvm_unreachable("Unexpected Vector Type");
1756 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1759 unsigned ExtOpcode) {
1760 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1761 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1762 // 64-bits we need to insert a new extension so that it will be 64-bits.
1763 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1764 if (OrigTy.getSizeInBits() >= 64)
1767 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1768 EVT NewVT = getExtensionTo64Bits(OrigTy);
1770 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1773 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1775 EVT VT = N->getValueType(0);
1777 if (N->getOpcode() != ISD::BUILD_VECTOR)
1780 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1781 SDNode *Elt = N->getOperand(i).getNode();
1782 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1783 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1784 unsigned HalfSize = EltSize / 2;
1786 if (!isIntN(HalfSize, C->getSExtValue()))
1789 if (!isUIntN(HalfSize, C->getZExtValue()))
1800 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1801 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1802 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1803 N->getOperand(0)->getValueType(0),
1807 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1808 EVT VT = N->getValueType(0);
1810 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1811 unsigned NumElts = VT.getVectorNumElements();
1812 MVT TruncVT = MVT::getIntegerVT(EltSize);
1813 SmallVector<SDValue, 8> Ops;
1814 for (unsigned i = 0; i != NumElts; ++i) {
1815 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1816 const APInt &CInt = C->getAPIntValue();
1817 // Element types smaller than 32 bits are not legal, so use i32 elements.
1818 // The values are implicitly truncated so sext vs. zext doesn't matter.
1819 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
1821 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1822 MVT::getVectorVT(TruncVT, NumElts), Ops);
1825 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1826 if (N->getOpcode() == ISD::SIGN_EXTEND)
1828 if (isExtendedBUILD_VECTOR(N, DAG, true))
1833 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1834 if (N->getOpcode() == ISD::ZERO_EXTEND)
1836 if (isExtendedBUILD_VECTOR(N, DAG, false))
1841 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1842 unsigned Opcode = N->getOpcode();
1843 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1844 SDNode *N0 = N->getOperand(0).getNode();
1845 SDNode *N1 = N->getOperand(1).getNode();
1846 return N0->hasOneUse() && N1->hasOneUse() &&
1847 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1852 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1853 unsigned Opcode = N->getOpcode();
1854 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1855 SDNode *N0 = N->getOperand(0).getNode();
1856 SDNode *N1 = N->getOperand(1).getNode();
1857 return N0->hasOneUse() && N1->hasOneUse() &&
1858 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1863 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1864 // Multiplications are only custom-lowered for 128-bit vectors so that
1865 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1866 EVT VT = Op.getValueType();
1867 assert(VT.is128BitVector() && VT.isInteger() &&
1868 "unexpected type for custom-lowering ISD::MUL");
1869 SDNode *N0 = Op.getOperand(0).getNode();
1870 SDNode *N1 = Op.getOperand(1).getNode();
1871 unsigned NewOpc = 0;
1873 bool isN0SExt = isSignExtended(N0, DAG);
1874 bool isN1SExt = isSignExtended(N1, DAG);
1875 if (isN0SExt && isN1SExt)
1876 NewOpc = AArch64ISD::SMULL;
1878 bool isN0ZExt = isZeroExtended(N0, DAG);
1879 bool isN1ZExt = isZeroExtended(N1, DAG);
1880 if (isN0ZExt && isN1ZExt)
1881 NewOpc = AArch64ISD::UMULL;
1882 else if (isN1SExt || isN1ZExt) {
1883 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1884 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1885 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1886 NewOpc = AArch64ISD::SMULL;
1888 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1889 NewOpc = AArch64ISD::UMULL;
1891 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1893 NewOpc = AArch64ISD::UMULL;
1899 if (VT == MVT::v2i64)
1900 // Fall through to expand this. It is not legal.
1903 // Other vector multiplications are legal.
1908 // Legalize to a S/UMULL instruction
1911 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1913 Op0 = skipExtensionForVectorMULL(N0, DAG);
1914 assert(Op0.getValueType().is64BitVector() &&
1915 Op1.getValueType().is64BitVector() &&
1916 "unexpected types for extended operands to VMULL");
1917 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1919 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1920 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1921 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1922 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1923 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1924 EVT Op1VT = Op1.getValueType();
1925 return DAG.getNode(N0->getOpcode(), DL, VT,
1926 DAG.getNode(NewOpc, DL, VT,
1927 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1928 DAG.getNode(NewOpc, DL, VT,
1929 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1932 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1933 SelectionDAG &DAG) const {
1934 switch (Op.getOpcode()) {
1936 llvm_unreachable("unimplemented operand");
1939 return LowerBITCAST(Op, DAG);
1940 case ISD::GlobalAddress:
1941 return LowerGlobalAddress(Op, DAG);
1942 case ISD::GlobalTLSAddress:
1943 return LowerGlobalTLSAddress(Op, DAG);
1945 return LowerSETCC(Op, DAG);
1947 return LowerBR_CC(Op, DAG);
1949 return LowerSELECT(Op, DAG);
1950 case ISD::SELECT_CC:
1951 return LowerSELECT_CC(Op, DAG);
1952 case ISD::JumpTable:
1953 return LowerJumpTable(Op, DAG);
1954 case ISD::ConstantPool:
1955 return LowerConstantPool(Op, DAG);
1956 case ISD::BlockAddress:
1957 return LowerBlockAddress(Op, DAG);
1959 return LowerVASTART(Op, DAG);
1961 return LowerVACOPY(Op, DAG);
1963 return LowerVAARG(Op, DAG);
1968 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1975 return LowerXALUO(Op, DAG);
1977 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1979 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1981 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1983 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1985 return LowerFP_ROUND(Op, DAG);
1986 case ISD::FP_EXTEND:
1987 return LowerFP_EXTEND(Op, DAG);
1988 case ISD::FRAMEADDR:
1989 return LowerFRAMEADDR(Op, DAG);
1990 case ISD::RETURNADDR:
1991 return LowerRETURNADDR(Op, DAG);
1992 case ISD::INSERT_VECTOR_ELT:
1993 return LowerINSERT_VECTOR_ELT(Op, DAG);
1994 case ISD::EXTRACT_VECTOR_ELT:
1995 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1996 case ISD::BUILD_VECTOR:
1997 return LowerBUILD_VECTOR(Op, DAG);
1998 case ISD::VECTOR_SHUFFLE:
1999 return LowerVECTOR_SHUFFLE(Op, DAG);
2000 case ISD::EXTRACT_SUBVECTOR:
2001 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2005 return LowerVectorSRA_SRL_SHL(Op, DAG);
2006 case ISD::SHL_PARTS:
2007 return LowerShiftLeftParts(Op, DAG);
2008 case ISD::SRL_PARTS:
2009 case ISD::SRA_PARTS:
2010 return LowerShiftRightParts(Op, DAG);
2012 return LowerCTPOP(Op, DAG);
2013 case ISD::FCOPYSIGN:
2014 return LowerFCOPYSIGN(Op, DAG);
2016 return LowerVectorAND(Op, DAG);
2018 return LowerVectorOR(Op, DAG);
2020 return LowerXOR(Op, DAG);
2022 return LowerPREFETCH(Op, DAG);
2023 case ISD::SINT_TO_FP:
2024 case ISD::UINT_TO_FP:
2025 return LowerINT_TO_FP(Op, DAG);
2026 case ISD::FP_TO_SINT:
2027 case ISD::FP_TO_UINT:
2028 return LowerFP_TO_INT(Op, DAG);
2030 return LowerFSINCOS(Op, DAG);
2032 return LowerMUL(Op, DAG);
2036 /// getFunctionAlignment - Return the Log2 alignment of this function.
2037 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2041 //===----------------------------------------------------------------------===//
2042 // Calling Convention Implementation
2043 //===----------------------------------------------------------------------===//
2045 #include "AArch64GenCallingConv.inc"
2047 /// Selects the correct CCAssignFn for a given CallingConvention value.
2048 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2049 bool IsVarArg) const {
2052 llvm_unreachable("Unsupported calling convention.");
2053 case CallingConv::WebKit_JS:
2054 return CC_AArch64_WebKit_JS;
2055 case CallingConv::GHC:
2056 return CC_AArch64_GHC;
2057 case CallingConv::C:
2058 case CallingConv::Fast:
2059 if (!Subtarget->isTargetDarwin())
2060 return CC_AArch64_AAPCS;
2061 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2065 SDValue AArch64TargetLowering::LowerFormalArguments(
2066 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2067 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2068 SmallVectorImpl<SDValue> &InVals) const {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 MachineFrameInfo *MFI = MF.getFrameInfo();
2072 // Assign locations to all of the incoming arguments.
2073 SmallVector<CCValAssign, 16> ArgLocs;
2074 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2077 // At this point, Ins[].VT may already be promoted to i32. To correctly
2078 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2079 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2080 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2081 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2083 unsigned NumArgs = Ins.size();
2084 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2085 unsigned CurArgIdx = 0;
2086 for (unsigned i = 0; i != NumArgs; ++i) {
2087 MVT ValVT = Ins[i].VT;
2088 if (Ins[i].isOrigArg()) {
2089 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2090 CurArgIdx = Ins[i].getOrigArgIndex();
2092 // Get type of the original argument.
2093 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2094 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2095 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2096 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2098 else if (ActualMVT == MVT::i16)
2101 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2103 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2104 assert(!Res && "Call operand has unhandled type");
2107 assert(ArgLocs.size() == Ins.size());
2108 SmallVector<SDValue, 16> ArgValues;
2109 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2110 CCValAssign &VA = ArgLocs[i];
2112 if (Ins[i].Flags.isByVal()) {
2113 // Byval is used for HFAs in the PCS, but the system should work in a
2114 // non-compliant manner for larger structs.
2115 EVT PtrTy = getPointerTy();
2116 int Size = Ins[i].Flags.getByValSize();
2117 unsigned NumRegs = (Size + 7) / 8;
2119 // FIXME: This works on big-endian for composite byvals, which are the common
2120 // case. It should also work for fundamental types too.
2122 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2123 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2124 InVals.push_back(FrameIdxN);
2129 if (VA.isRegLoc()) {
2130 // Arguments stored in registers.
2131 EVT RegVT = VA.getLocVT();
2134 const TargetRegisterClass *RC;
2136 if (RegVT == MVT::i32)
2137 RC = &AArch64::GPR32RegClass;
2138 else if (RegVT == MVT::i64)
2139 RC = &AArch64::GPR64RegClass;
2140 else if (RegVT == MVT::f16)
2141 RC = &AArch64::FPR16RegClass;
2142 else if (RegVT == MVT::f32)
2143 RC = &AArch64::FPR32RegClass;
2144 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2145 RC = &AArch64::FPR64RegClass;
2146 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2147 RC = &AArch64::FPR128RegClass;
2149 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2151 // Transform the arguments in physical registers into virtual ones.
2152 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2153 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2155 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2156 // to 64 bits. Insert an assert[sz]ext to capture this, then
2157 // truncate to the right size.
2158 switch (VA.getLocInfo()) {
2160 llvm_unreachable("Unknown loc info!");
2161 case CCValAssign::Full:
2163 case CCValAssign::BCvt:
2164 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2166 case CCValAssign::AExt:
2167 case CCValAssign::SExt:
2168 case CCValAssign::ZExt:
2169 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2170 // nodes after our lowering.
2171 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2175 InVals.push_back(ArgValue);
2177 } else { // VA.isRegLoc()
2178 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2179 unsigned ArgOffset = VA.getLocMemOffset();
2180 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2182 uint32_t BEAlign = 0;
2183 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2184 !Ins[i].Flags.isInConsecutiveRegs())
2185 BEAlign = 8 - ArgSize;
2187 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2189 // Create load nodes to retrieve arguments from the stack.
2190 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2193 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2194 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2195 MVT MemVT = VA.getValVT();
2197 switch (VA.getLocInfo()) {
2200 case CCValAssign::BCvt:
2201 MemVT = VA.getLocVT();
2203 case CCValAssign::SExt:
2204 ExtType = ISD::SEXTLOAD;
2206 case CCValAssign::ZExt:
2207 ExtType = ISD::ZEXTLOAD;
2209 case CCValAssign::AExt:
2210 ExtType = ISD::EXTLOAD;
2214 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2215 MachinePointerInfo::getFixedStack(FI),
2216 MemVT, false, false, false, 0);
2218 InVals.push_back(ArgValue);
2224 if (!Subtarget->isTargetDarwin()) {
2225 // The AAPCS variadic function ABI is identical to the non-variadic
2226 // one. As a result there may be more arguments in registers and we should
2227 // save them for future reference.
2228 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2231 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2232 // This will point to the next argument passed via stack.
2233 unsigned StackOffset = CCInfo.getNextStackOffset();
2234 // We currently pass all varargs at 8-byte alignment.
2235 StackOffset = ((StackOffset + 7) & ~7);
2236 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2239 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2240 unsigned StackArgSize = CCInfo.getNextStackOffset();
2241 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2242 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2243 // This is a non-standard ABI so by fiat I say we're allowed to make full
2244 // use of the stack area to be popped, which must be aligned to 16 bytes in
2246 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2248 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2249 // a multiple of 16.
2250 FuncInfo->setArgumentStackToRestore(StackArgSize);
2252 // This realignment carries over to the available bytes below. Our own
2253 // callers will guarantee the space is free by giving an aligned value to
2256 // Even if we're not expected to free up the space, it's useful to know how
2257 // much is there while considering tail calls (because we can reuse it).
2258 FuncInfo->setBytesInStackArgArea(StackArgSize);
2263 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2264 SelectionDAG &DAG, SDLoc DL,
2265 SDValue &Chain) const {
2266 MachineFunction &MF = DAG.getMachineFunction();
2267 MachineFrameInfo *MFI = MF.getFrameInfo();
2268 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2270 SmallVector<SDValue, 8> MemOps;
2272 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2273 AArch64::X3, AArch64::X4, AArch64::X5,
2274 AArch64::X6, AArch64::X7 };
2275 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2276 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2278 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2280 if (GPRSaveSize != 0) {
2281 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2283 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2285 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2286 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2287 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2289 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2290 MachinePointerInfo::getStack(i * 8), false, false, 0);
2291 MemOps.push_back(Store);
2292 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2293 DAG.getConstant(8, DL, getPointerTy()));
2296 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2297 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2299 if (Subtarget->hasFPARMv8()) {
2300 static const MCPhysReg FPRArgRegs[] = {
2301 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2302 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2303 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2304 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2306 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2308 if (FPRSaveSize != 0) {
2309 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2311 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2313 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2314 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2315 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2318 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2319 MachinePointerInfo::getStack(i * 16), false, false, 0);
2320 MemOps.push_back(Store);
2321 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2322 DAG.getConstant(16, DL, getPointerTy()));
2325 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2326 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2329 if (!MemOps.empty()) {
2330 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2334 /// LowerCallResult - Lower the result values of a call into the
2335 /// appropriate copies out of appropriate physical registers.
2336 SDValue AArch64TargetLowering::LowerCallResult(
2337 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2338 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2339 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2340 SDValue ThisVal) const {
2341 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2342 ? RetCC_AArch64_WebKit_JS
2343 : RetCC_AArch64_AAPCS;
2344 // Assign locations to each value returned by this call.
2345 SmallVector<CCValAssign, 16> RVLocs;
2346 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2348 CCInfo.AnalyzeCallResult(Ins, RetCC);
2350 // Copy all of the result registers out of their specified physreg.
2351 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2352 CCValAssign VA = RVLocs[i];
2354 // Pass 'this' value directly from the argument to return value, to avoid
2355 // reg unit interference
2356 if (i == 0 && isThisReturn) {
2357 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2358 "unexpected return calling convention register assignment");
2359 InVals.push_back(ThisVal);
2364 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2365 Chain = Val.getValue(1);
2366 InFlag = Val.getValue(2);
2368 switch (VA.getLocInfo()) {
2370 llvm_unreachable("Unknown loc info!");
2371 case CCValAssign::Full:
2373 case CCValAssign::BCvt:
2374 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2378 InVals.push_back(Val);
2384 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2385 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2386 bool isCalleeStructRet, bool isCallerStructRet,
2387 const SmallVectorImpl<ISD::OutputArg> &Outs,
2388 const SmallVectorImpl<SDValue> &OutVals,
2389 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2390 // For CallingConv::C this function knows whether the ABI needs
2391 // changing. That's not true for other conventions so they will have to opt in
2393 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2396 const MachineFunction &MF = DAG.getMachineFunction();
2397 const Function *CallerF = MF.getFunction();
2398 CallingConv::ID CallerCC = CallerF->getCallingConv();
2399 bool CCMatch = CallerCC == CalleeCC;
2401 // Byval parameters hand the function a pointer directly into the stack area
2402 // we want to reuse during a tail call. Working around this *is* possible (see
2403 // X86) but less efficient and uglier in LowerCall.
2404 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2405 e = CallerF->arg_end();
2407 if (i->hasByValAttr())
2410 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2411 if (IsTailCallConvention(CalleeCC) && CCMatch)
2416 // Externally-defined functions with weak linkage should not be
2417 // tail-called on AArch64 when the OS does not support dynamic
2418 // pre-emption of symbols, as the AAELF spec requires normal calls
2419 // to undefined weak functions to be replaced with a NOP or jump to the
2420 // next instruction. The behaviour of branch instructions in this
2421 // situation (as used for tail calls) is implementation-defined, so we
2422 // cannot rely on the linker replacing the tail call with a return.
2423 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2424 const GlobalValue *GV = G->getGlobal();
2425 const Triple &TT = getTargetMachine().getTargetTriple();
2426 if (GV->hasExternalWeakLinkage() &&
2427 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2431 // Now we search for cases where we can use a tail call without changing the
2432 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2435 // I want anyone implementing a new calling convention to think long and hard
2436 // about this assert.
2437 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2438 "Unexpected variadic calling convention");
2440 if (isVarArg && !Outs.empty()) {
2441 // At least two cases here: if caller is fastcc then we can't have any
2442 // memory arguments (we'd be expected to clean up the stack afterwards). If
2443 // caller is C then we could potentially use its argument area.
2445 // FIXME: for now we take the most conservative of these in both cases:
2446 // disallow all variadic memory operands.
2447 SmallVector<CCValAssign, 16> ArgLocs;
2448 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2451 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2453 if (!ArgLocs[i].isRegLoc())
2457 // If the calling conventions do not match, then we'd better make sure the
2458 // results are returned in the same way as what the caller expects.
2460 SmallVector<CCValAssign, 16> RVLocs1;
2461 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2463 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2465 SmallVector<CCValAssign, 16> RVLocs2;
2466 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2468 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2470 if (RVLocs1.size() != RVLocs2.size())
2472 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2473 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2475 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2477 if (RVLocs1[i].isRegLoc()) {
2478 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2481 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2487 // Nothing more to check if the callee is taking no arguments
2491 SmallVector<CCValAssign, 16> ArgLocs;
2492 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2495 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2497 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2499 // If the stack arguments for this call would fit into our own save area then
2500 // the call can be made tail.
2501 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2504 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2506 MachineFrameInfo *MFI,
2507 int ClobberedFI) const {
2508 SmallVector<SDValue, 8> ArgChains;
2509 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2510 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2512 // Include the original chain at the beginning of the list. When this is
2513 // used by target LowerCall hooks, this helps legalize find the
2514 // CALLSEQ_BEGIN node.
2515 ArgChains.push_back(Chain);
2517 // Add a chain value for each stack argument corresponding
2518 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2519 UE = DAG.getEntryNode().getNode()->use_end();
2521 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2522 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2523 if (FI->getIndex() < 0) {
2524 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2525 int64_t InLastByte = InFirstByte;
2526 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2528 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2529 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2530 ArgChains.push_back(SDValue(L, 1));
2533 // Build a tokenfactor for all the chains.
2534 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2537 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2538 bool TailCallOpt) const {
2539 return CallCC == CallingConv::Fast && TailCallOpt;
2542 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2543 return CallCC == CallingConv::Fast;
2546 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2547 /// and add input and output parameter nodes.
2549 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2550 SmallVectorImpl<SDValue> &InVals) const {
2551 SelectionDAG &DAG = CLI.DAG;
2553 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2554 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2555 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2556 SDValue Chain = CLI.Chain;
2557 SDValue Callee = CLI.Callee;
2558 bool &IsTailCall = CLI.IsTailCall;
2559 CallingConv::ID CallConv = CLI.CallConv;
2560 bool IsVarArg = CLI.IsVarArg;
2562 MachineFunction &MF = DAG.getMachineFunction();
2563 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2564 bool IsThisReturn = false;
2566 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2567 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2568 bool IsSibCall = false;
2571 // Check if it's really possible to do a tail call.
2572 IsTailCall = isEligibleForTailCallOptimization(
2573 Callee, CallConv, IsVarArg, IsStructRet,
2574 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2575 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2576 report_fatal_error("failed to perform tail call elimination on a call "
2577 "site marked musttail");
2579 // A sibling call is one where we're under the usual C ABI and not planning
2580 // to change that but can still do a tail call:
2581 if (!TailCallOpt && IsTailCall)
2588 // Analyze operands of the call, assigning locations to each operand.
2589 SmallVector<CCValAssign, 16> ArgLocs;
2590 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2594 // Handle fixed and variable vector arguments differently.
2595 // Variable vector arguments always go into memory.
2596 unsigned NumArgs = Outs.size();
2598 for (unsigned i = 0; i != NumArgs; ++i) {
2599 MVT ArgVT = Outs[i].VT;
2600 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2601 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2602 /*IsVarArg=*/ !Outs[i].IsFixed);
2603 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2604 assert(!Res && "Call operand has unhandled type");
2608 // At this point, Outs[].VT may already be promoted to i32. To correctly
2609 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2610 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2611 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2612 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2614 unsigned NumArgs = Outs.size();
2615 for (unsigned i = 0; i != NumArgs; ++i) {
2616 MVT ValVT = Outs[i].VT;
2617 // Get type of the original argument.
2618 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2619 /*AllowUnknown*/ true);
2620 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2621 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2622 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2623 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2625 else if (ActualMVT == MVT::i16)
2628 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2629 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2630 assert(!Res && "Call operand has unhandled type");
2635 // Get a count of how many bytes are to be pushed on the stack.
2636 unsigned NumBytes = CCInfo.getNextStackOffset();
2639 // Since we're not changing the ABI to make this a tail call, the memory
2640 // operands are already available in the caller's incoming argument space.
2644 // FPDiff is the byte offset of the call's argument area from the callee's.
2645 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2646 // by this amount for a tail call. In a sibling call it must be 0 because the
2647 // caller will deallocate the entire stack and the callee still expects its
2648 // arguments to begin at SP+0. Completely unused for non-tail calls.
2651 if (IsTailCall && !IsSibCall) {
2652 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2654 // Since callee will pop argument stack as a tail call, we must keep the
2655 // popped size 16-byte aligned.
2656 NumBytes = RoundUpToAlignment(NumBytes, 16);
2658 // FPDiff will be negative if this tail call requires more space than we
2659 // would automatically have in our incoming argument space. Positive if we
2660 // can actually shrink the stack.
2661 FPDiff = NumReusableBytes - NumBytes;
2663 // The stack pointer must be 16-byte aligned at all times it's used for a
2664 // memory operation, which in practice means at *all* times and in
2665 // particular across call boundaries. Therefore our own arguments started at
2666 // a 16-byte aligned SP and the delta applied for the tail call should
2667 // satisfy the same constraint.
2668 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2671 // Adjust the stack pointer for the new arguments...
2672 // These operations are automatically eliminated by the prolog/epilog pass
2674 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2678 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2680 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2681 SmallVector<SDValue, 8> MemOpChains;
2683 // Walk the register/memloc assignments, inserting copies/loads.
2684 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2685 ++i, ++realArgIdx) {
2686 CCValAssign &VA = ArgLocs[i];
2687 SDValue Arg = OutVals[realArgIdx];
2688 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2690 // Promote the value if needed.
2691 switch (VA.getLocInfo()) {
2693 llvm_unreachable("Unknown loc info!");
2694 case CCValAssign::Full:
2696 case CCValAssign::SExt:
2697 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2699 case CCValAssign::ZExt:
2700 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2702 case CCValAssign::AExt:
2703 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2704 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2705 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2706 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2710 case CCValAssign::BCvt:
2711 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2713 case CCValAssign::FPExt:
2714 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2718 if (VA.isRegLoc()) {
2719 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2720 assert(VA.getLocVT() == MVT::i64 &&
2721 "unexpected calling convention register assignment");
2722 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2723 "unexpected use of 'returned'");
2724 IsThisReturn = true;
2726 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2728 assert(VA.isMemLoc());
2731 MachinePointerInfo DstInfo;
2733 // FIXME: This works on big-endian for composite byvals, which are the
2734 // common case. It should also work for fundamental types too.
2735 uint32_t BEAlign = 0;
2736 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2737 : VA.getValVT().getSizeInBits();
2738 OpSize = (OpSize + 7) / 8;
2739 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2740 !Flags.isInConsecutiveRegs()) {
2742 BEAlign = 8 - OpSize;
2744 unsigned LocMemOffset = VA.getLocMemOffset();
2745 int32_t Offset = LocMemOffset + BEAlign;
2746 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2747 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2750 Offset = Offset + FPDiff;
2751 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2753 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2754 DstInfo = MachinePointerInfo::getFixedStack(FI);
2756 // Make sure any stack arguments overlapping with where we're storing
2757 // are loaded before this eventual operation. Otherwise they'll be
2759 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2761 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2763 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2764 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2767 if (Outs[i].Flags.isByVal()) {
2769 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
2770 SDValue Cpy = DAG.getMemcpy(
2771 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2772 /*isVol = */ false, /*AlwaysInline = */ false,
2773 /*isTailCall = */ false,
2774 DstInfo, MachinePointerInfo());
2776 MemOpChains.push_back(Cpy);
2778 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2779 // promoted to a legal register type i32, we should truncate Arg back to
2781 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2782 VA.getValVT() == MVT::i16)
2783 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2786 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2787 MemOpChains.push_back(Store);
2792 if (!MemOpChains.empty())
2793 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2795 // Build a sequence of copy-to-reg nodes chained together with token chain
2796 // and flag operands which copy the outgoing args into the appropriate regs.
2798 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2799 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2800 RegsToPass[i].second, InFlag);
2801 InFlag = Chain.getValue(1);
2804 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2805 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2806 // node so that legalize doesn't hack it.
2807 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2808 Subtarget->isTargetMachO()) {
2809 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2810 const GlobalValue *GV = G->getGlobal();
2811 bool InternalLinkage = GV->hasInternalLinkage();
2812 if (InternalLinkage)
2813 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2815 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2817 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2819 } else if (ExternalSymbolSDNode *S =
2820 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2821 const char *Sym = S->getSymbol();
2823 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2824 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2826 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2827 const GlobalValue *GV = G->getGlobal();
2828 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2829 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2830 const char *Sym = S->getSymbol();
2831 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2834 // We don't usually want to end the call-sequence here because we would tidy
2835 // the frame up *after* the call, however in the ABI-changing tail-call case
2836 // we've carefully laid out the parameters so that when sp is reset they'll be
2837 // in the correct location.
2838 if (IsTailCall && !IsSibCall) {
2839 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2840 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2841 InFlag = Chain.getValue(1);
2844 std::vector<SDValue> Ops;
2845 Ops.push_back(Chain);
2846 Ops.push_back(Callee);
2849 // Each tail call may have to adjust the stack by a different amount, so
2850 // this information must travel along with the operation for eventual
2851 // consumption by emitEpilogue.
2852 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2855 // Add argument registers to the end of the list so that they are known live
2857 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2858 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2859 RegsToPass[i].second.getValueType()));
2861 // Add a register mask operand representing the call-preserved registers.
2862 const uint32_t *Mask;
2863 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2865 // For 'this' returns, use the X0-preserving mask if applicable
2866 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2868 IsThisReturn = false;
2869 Mask = TRI->getCallPreservedMask(MF, CallConv);
2872 Mask = TRI->getCallPreservedMask(MF, CallConv);
2874 assert(Mask && "Missing call preserved mask for calling convention");
2875 Ops.push_back(DAG.getRegisterMask(Mask));
2877 if (InFlag.getNode())
2878 Ops.push_back(InFlag);
2880 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2882 // If we're doing a tall call, use a TC_RETURN here rather than an
2883 // actual call instruction.
2885 MF.getFrameInfo()->setHasTailCall();
2886 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2889 // Returns a chain and a flag for retval copy to use.
2890 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2891 InFlag = Chain.getValue(1);
2893 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2894 ? RoundUpToAlignment(NumBytes, 16)
2897 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2898 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
2901 InFlag = Chain.getValue(1);
2903 // Handle result values, copying them out of physregs into vregs that we
2905 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2906 InVals, IsThisReturn,
2907 IsThisReturn ? OutVals[0] : SDValue());
2910 bool AArch64TargetLowering::CanLowerReturn(
2911 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2912 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2913 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2914 ? RetCC_AArch64_WebKit_JS
2915 : RetCC_AArch64_AAPCS;
2916 SmallVector<CCValAssign, 16> RVLocs;
2917 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2918 return CCInfo.CheckReturn(Outs, RetCC);
2922 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2924 const SmallVectorImpl<ISD::OutputArg> &Outs,
2925 const SmallVectorImpl<SDValue> &OutVals,
2926 SDLoc DL, SelectionDAG &DAG) const {
2927 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2928 ? RetCC_AArch64_WebKit_JS
2929 : RetCC_AArch64_AAPCS;
2930 SmallVector<CCValAssign, 16> RVLocs;
2931 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2933 CCInfo.AnalyzeReturn(Outs, RetCC);
2935 // Copy the result values into the output registers.
2937 SmallVector<SDValue, 4> RetOps(1, Chain);
2938 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2939 ++i, ++realRVLocIdx) {
2940 CCValAssign &VA = RVLocs[i];
2941 assert(VA.isRegLoc() && "Can only return in registers!");
2942 SDValue Arg = OutVals[realRVLocIdx];
2944 switch (VA.getLocInfo()) {
2946 llvm_unreachable("Unknown loc info!");
2947 case CCValAssign::Full:
2948 if (Outs[i].ArgVT == MVT::i1) {
2949 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2950 // value. This is strictly redundant on Darwin (which uses "zeroext
2951 // i1"), but will be optimised out before ISel.
2952 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2953 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2956 case CCValAssign::BCvt:
2957 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2961 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2962 Flag = Chain.getValue(1);
2963 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2966 RetOps[0] = Chain; // Update chain.
2968 // Add the flag if we have it.
2970 RetOps.push_back(Flag);
2972 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2975 //===----------------------------------------------------------------------===//
2976 // Other Lowering Code
2977 //===----------------------------------------------------------------------===//
2979 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2980 SelectionDAG &DAG) const {
2981 EVT PtrVT = getPointerTy();
2983 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2984 const GlobalValue *GV = GN->getGlobal();
2985 unsigned char OpFlags =
2986 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2988 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2989 "unexpected offset in global node");
2991 // This also catched the large code model case for Darwin.
2992 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2993 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2994 // FIXME: Once remat is capable of dealing with instructions with register
2995 // operands, expand this into two nodes instead of using a wrapper node.
2996 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2999 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
3000 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3001 "use of MO_CONSTPOOL only supported on small model");
3002 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3003 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3004 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3005 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3006 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3007 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3008 MachinePointerInfo::getConstantPool(),
3009 /*isVolatile=*/ false,
3010 /*isNonTemporal=*/ true,
3011 /*isInvariant=*/ true, 8);
3012 if (GN->getOffset() != 0)
3013 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3014 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3018 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3019 const unsigned char MO_NC = AArch64II::MO_NC;
3021 AArch64ISD::WrapperLarge, DL, PtrVT,
3022 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3023 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3024 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3025 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3027 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3028 // the only correct model on Darwin.
3029 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3030 OpFlags | AArch64II::MO_PAGE);
3031 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3032 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3034 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3035 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3039 /// \brief Convert a TLS address reference into the correct sequence of loads
3040 /// and calls to compute the variable's address (for Darwin, currently) and
3041 /// return an SDValue containing the final node.
3043 /// Darwin only has one TLS scheme which must be capable of dealing with the
3044 /// fully general situation, in the worst case. This means:
3045 /// + "extern __thread" declaration.
3046 /// + Defined in a possibly unknown dynamic library.
3048 /// The general system is that each __thread variable has a [3 x i64] descriptor
3049 /// which contains information used by the runtime to calculate the address. The
3050 /// only part of this the compiler needs to know about is the first xword, which
3051 /// contains a function pointer that must be called with the address of the
3052 /// entire descriptor in "x0".
3054 /// Since this descriptor may be in a different unit, in general even the
3055 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3057 /// adrp x0, _var@TLVPPAGE
3058 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3059 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3060 /// ; the function pointer
3061 /// blr x1 ; Uses descriptor address in x0
3062 /// ; Address of _var is now in x0.
3064 /// If the address of _var's descriptor *is* known to the linker, then it can
3065 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3066 /// a slight efficiency gain.
3068 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3069 SelectionDAG &DAG) const {
3070 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3073 MVT PtrVT = getPointerTy();
3074 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3077 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3078 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3080 // The first entry in the descriptor is a function pointer that we must call
3081 // to obtain the address of the variable.
3082 SDValue Chain = DAG.getEntryNode();
3083 SDValue FuncTLVGet =
3084 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3085 false, true, true, 8);
3086 Chain = FuncTLVGet.getValue(1);
3088 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3089 MFI->setAdjustsStack(true);
3091 // TLS calls preserve all registers except those that absolutely must be
3092 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3094 const uint32_t *Mask =
3095 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3097 // Finally, we can make the call. This is just a degenerate version of a
3098 // normal AArch64 call node: x0 takes the address of the descriptor, and
3099 // returns the address of the variable in this thread.
3100 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3102 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3103 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3104 DAG.getRegisterMask(Mask), Chain.getValue(1));
3105 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3108 /// When accessing thread-local variables under either the general-dynamic or
3109 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3110 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3111 /// is a function pointer to carry out the resolution.
3113 /// The sequence is:
3114 /// adrp x0, :tlsdesc:var
3115 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3116 /// add x0, x0, #:tlsdesc_lo12:var
3117 /// .tlsdesccall var
3119 /// (TPIDR_EL0 offset now in x0)
3121 /// The above sequence must be produced unscheduled, to enable the linker to
3122 /// optimize/relax this sequence.
3123 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3124 /// above sequence, and expanded really late in the compilation flow, to ensure
3125 /// the sequence is produced as per above.
3126 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3127 SelectionDAG &DAG) const {
3128 EVT PtrVT = getPointerTy();
3130 SDValue Chain = DAG.getEntryNode();
3131 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3133 SmallVector<SDValue, 2> Ops;
3134 Ops.push_back(Chain);
3135 Ops.push_back(SymAddr);
3137 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3138 SDValue Glue = Chain.getValue(1);
3140 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3144 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3145 SelectionDAG &DAG) const {
3146 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3147 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3148 "ELF TLS only supported in small memory model");
3149 // Different choices can be made for the maximum size of the TLS area for a
3150 // module. For the small address model, the default TLS size is 16MiB and the
3151 // maximum TLS size is 4GiB.
3152 // FIXME: add -mtls-size command line option and make it control the 16MiB
3153 // vs. 4GiB code sequence generation.
3154 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3156 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3157 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3158 if (Model == TLSModel::LocalDynamic)
3159 Model = TLSModel::GeneralDynamic;
3163 EVT PtrVT = getPointerTy();
3165 const GlobalValue *GV = GA->getGlobal();
3167 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3169 if (Model == TLSModel::LocalExec) {
3170 SDValue HiVar = DAG.getTargetGlobalAddress(
3171 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3172 SDValue LoVar = DAG.getTargetGlobalAddress(
3174 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3176 SDValue TPWithOff_lo =
3177 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3179 DAG.getTargetConstant(0, DL, MVT::i32)),
3182 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3184 DAG.getTargetConstant(0, DL, MVT::i32)),
3187 } else if (Model == TLSModel::InitialExec) {
3188 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3189 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3190 } else if (Model == TLSModel::LocalDynamic) {
3191 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3192 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3193 // the beginning of the module's TLS region, followed by a DTPREL offset
3196 // These accesses will need deduplicating if there's more than one.
3197 AArch64FunctionInfo *MFI =
3198 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3199 MFI->incNumLocalDynamicTLSAccesses();
3201 // The call needs a relocation too for linker relaxation. It doesn't make
3202 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3204 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3207 // Now we can calculate the offset from TPIDR_EL0 to this module's
3208 // thread-local area.
3209 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3211 // Now use :dtprel_whatever: operations to calculate this variable's offset
3212 // in its thread-storage area.
3213 SDValue HiVar = DAG.getTargetGlobalAddress(
3214 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3215 SDValue LoVar = DAG.getTargetGlobalAddress(
3216 GV, DL, MVT::i64, 0,
3217 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3219 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3220 DAG.getTargetConstant(0, DL, MVT::i32)),
3222 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3223 DAG.getTargetConstant(0, DL, MVT::i32)),
3225 } else if (Model == TLSModel::GeneralDynamic) {
3226 // The call needs a relocation too for linker relaxation. It doesn't make
3227 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3230 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3232 // Finally we can make a call to calculate the offset from tpidr_el0.
3233 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3235 llvm_unreachable("Unsupported ELF TLS access model");
3237 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3240 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3241 SelectionDAG &DAG) const {
3242 if (Subtarget->isTargetDarwin())
3243 return LowerDarwinGlobalTLSAddress(Op, DAG);
3244 else if (Subtarget->isTargetELF())
3245 return LowerELFGlobalTLSAddress(Op, DAG);
3247 llvm_unreachable("Unexpected platform trying to use TLS");
3249 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3250 SDValue Chain = Op.getOperand(0);
3251 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3252 SDValue LHS = Op.getOperand(2);
3253 SDValue RHS = Op.getOperand(3);
3254 SDValue Dest = Op.getOperand(4);
3257 // Handle f128 first, since lowering it will result in comparing the return
3258 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3259 // is expecting to deal with.
3260 if (LHS.getValueType() == MVT::f128) {
3261 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3263 // If softenSetCCOperands returned a scalar, we need to compare the result
3264 // against zero to select between true and false values.
3265 if (!RHS.getNode()) {
3266 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3271 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3273 unsigned Opc = LHS.getOpcode();
3274 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3275 cast<ConstantSDNode>(RHS)->isOne() &&
3276 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3277 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3278 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3279 "Unexpected condition code.");
3280 // Only lower legal XALUO ops.
3281 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3284 // The actual operation with overflow check.
3285 AArch64CC::CondCode OFCC;
3286 SDValue Value, Overflow;
3287 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3289 if (CC == ISD::SETNE)
3290 OFCC = getInvertedCondCode(OFCC);
3291 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3293 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3297 if (LHS.getValueType().isInteger()) {
3298 assert((LHS.getValueType() == RHS.getValueType()) &&
3299 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3301 // If the RHS of the comparison is zero, we can potentially fold this
3302 // to a specialized branch.
3303 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3304 if (RHSC && RHSC->getZExtValue() == 0) {
3305 if (CC == ISD::SETEQ) {
3306 // See if we can use a TBZ to fold in an AND as well.
3307 // TBZ has a smaller branch displacement than CBZ. If the offset is
3308 // out of bounds, a late MI-layer pass rewrites branches.
3309 // 403.gcc is an example that hits this case.
3310 if (LHS.getOpcode() == ISD::AND &&
3311 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3312 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3313 SDValue Test = LHS.getOperand(0);
3314 uint64_t Mask = LHS.getConstantOperandVal(1);
3315 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3316 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3320 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3321 } else if (CC == ISD::SETNE) {
3322 // See if we can use a TBZ to fold in an AND as well.
3323 // TBZ has a smaller branch displacement than CBZ. If the offset is
3324 // out of bounds, a late MI-layer pass rewrites branches.
3325 // 403.gcc is an example that hits this case.
3326 if (LHS.getOpcode() == ISD::AND &&
3327 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3328 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3329 SDValue Test = LHS.getOperand(0);
3330 uint64_t Mask = LHS.getConstantOperandVal(1);
3331 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3332 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3336 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3337 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3338 // Don't combine AND since emitComparison converts the AND to an ANDS
3339 // (a.k.a. TST) and the test in the test bit and branch instruction
3340 // becomes redundant. This would also increase register pressure.
3341 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3342 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3343 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3346 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3347 LHS.getOpcode() != ISD::AND) {
3348 // Don't combine AND since emitComparison converts the AND to an ANDS
3349 // (a.k.a. TST) and the test in the test bit and branch instruction
3350 // becomes redundant. This would also increase register pressure.
3351 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3352 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3353 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3357 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3358 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3362 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3364 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3365 // clean. Some of them require two branches to implement.
3366 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3367 AArch64CC::CondCode CC1, CC2;
3368 changeFPCCToAArch64CC(CC, CC1, CC2);
3369 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3371 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3372 if (CC2 != AArch64CC::AL) {
3373 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3374 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3381 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3382 SelectionDAG &DAG) const {
3383 EVT VT = Op.getValueType();
3386 SDValue In1 = Op.getOperand(0);
3387 SDValue In2 = Op.getOperand(1);
3388 EVT SrcVT = In2.getValueType();
3390 if (SrcVT == MVT::f32 && VT == MVT::f64)
3391 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3392 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3393 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3394 DAG.getIntPtrConstant(0, DL));
3396 // FIXME: Src type is different, bail out for now. Can VT really be a
3404 SDValue VecVal1, VecVal2;
3405 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3408 EltMask = 0x80000000ULL;
3410 if (!VT.isVector()) {
3411 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3412 DAG.getUNDEF(VecVT), In1);
3413 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3414 DAG.getUNDEF(VecVT), In2);
3416 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3417 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3419 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3423 // We want to materialize a mask with the high bit set, but the AdvSIMD
3424 // immediate moves cannot materialize that in a single instruction for
3425 // 64-bit elements. Instead, materialize zero and then negate it.
3428 if (!VT.isVector()) {
3429 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3430 DAG.getUNDEF(VecVT), In1);
3431 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3432 DAG.getUNDEF(VecVT), In2);
3434 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3435 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3438 llvm_unreachable("Invalid type for copysign!");
3441 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3443 // If we couldn't materialize the mask above, then the mask vector will be
3444 // the zero vector, and we need to negate it here.
3445 if (VT == MVT::f64 || VT == MVT::v2f64) {
3446 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3447 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3448 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3452 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3455 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3456 else if (VT == MVT::f64)
3457 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3459 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3462 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3463 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3464 Attribute::NoImplicitFloat))
3467 if (!Subtarget->hasNEON())
3470 // While there is no integer popcount instruction, it can
3471 // be more efficiently lowered to the following sequence that uses
3472 // AdvSIMD registers/instructions as long as the copies to/from
3473 // the AdvSIMD registers are cheap.
3474 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3475 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3476 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3477 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3478 SDValue Val = Op.getOperand(0);
3480 EVT VT = Op.getValueType();
3483 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3484 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3486 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3487 SDValue UaddLV = DAG.getNode(
3488 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3489 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3492 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3496 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3498 if (Op.getValueType().isVector())
3499 return LowerVSETCC(Op, DAG);
3501 SDValue LHS = Op.getOperand(0);
3502 SDValue RHS = Op.getOperand(1);
3503 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3506 // We chose ZeroOrOneBooleanContents, so use zero and one.
3507 EVT VT = Op.getValueType();
3508 SDValue TVal = DAG.getConstant(1, dl, VT);
3509 SDValue FVal = DAG.getConstant(0, dl, VT);
3511 // Handle f128 first, since one possible outcome is a normal integer
3512 // comparison which gets picked up by the next if statement.
3513 if (LHS.getValueType() == MVT::f128) {
3514 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3516 // If softenSetCCOperands returned a scalar, use it.
3517 if (!RHS.getNode()) {
3518 assert(LHS.getValueType() == Op.getValueType() &&
3519 "Unexpected setcc expansion!");
3524 if (LHS.getValueType().isInteger()) {
3527 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3529 // Note that we inverted the condition above, so we reverse the order of
3530 // the true and false operands here. This will allow the setcc to be
3531 // matched to a single CSINC instruction.
3532 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3535 // Now we know we're dealing with FP values.
3536 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3538 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3539 // and do the comparison.
3540 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3542 AArch64CC::CondCode CC1, CC2;
3543 changeFPCCToAArch64CC(CC, CC1, CC2);
3544 if (CC2 == AArch64CC::AL) {
3545 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3546 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3548 // Note that we inverted the condition above, so we reverse the order of
3549 // the true and false operands here. This will allow the setcc to be
3550 // matched to a single CSINC instruction.
3551 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3553 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3554 // totally clean. Some of them require two CSELs to implement. As is in
3555 // this case, we emit the first CSEL and then emit a second using the output
3556 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3558 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3559 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3561 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3563 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3564 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3568 /// A SELECT_CC operation is really some kind of max or min if both values being
3569 /// compared are, in some sense, equal to the results in either case. However,
3570 /// it is permissible to compare f32 values and produce directly extended f64
3573 /// Extending the comparison operands would also be allowed, but is less likely
3574 /// to happen in practice since their use is right here. Note that truncate
3575 /// operations would *not* be semantically equivalent.
3576 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3578 return (Cmp.getValueType() == MVT::f32 ||
3579 Cmp.getValueType() == MVT::f64);
3581 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3582 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3583 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3584 Result.getValueType() == MVT::f64) {
3586 APFloat CmpVal = CCmp->getValueAPF();
3587 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3588 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3591 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3594 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3595 SDValue RHS, SDValue TVal,
3596 SDValue FVal, SDLoc dl,
3597 SelectionDAG &DAG) const {
3598 // Handle f128 first, because it will result in a comparison of some RTLIB
3599 // call result against zero.
3600 if (LHS.getValueType() == MVT::f128) {
3601 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3603 // If softenSetCCOperands returned a scalar, we need to compare the result
3604 // against zero to select between true and false values.
3605 if (!RHS.getNode()) {
3606 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3611 // Handle integers first.
3612 if (LHS.getValueType().isInteger()) {
3613 assert((LHS.getValueType() == RHS.getValueType()) &&
3614 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3616 unsigned Opcode = AArch64ISD::CSEL;
3618 // If both the TVal and the FVal are constants, see if we can swap them in
3619 // order to for a CSINV or CSINC out of them.
3620 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3621 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3623 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3624 std::swap(TVal, FVal);
3625 std::swap(CTVal, CFVal);
3626 CC = ISD::getSetCCInverse(CC, true);
3627 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3628 std::swap(TVal, FVal);
3629 std::swap(CTVal, CFVal);
3630 CC = ISD::getSetCCInverse(CC, true);
3631 } else if (TVal.getOpcode() == ISD::XOR) {
3632 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3633 // with a CSINV rather than a CSEL.
3634 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3636 if (CVal && CVal->isAllOnesValue()) {
3637 std::swap(TVal, FVal);
3638 std::swap(CTVal, CFVal);
3639 CC = ISD::getSetCCInverse(CC, true);
3641 } else if (TVal.getOpcode() == ISD::SUB) {
3642 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3643 // that we can match with a CSNEG rather than a CSEL.
3644 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3646 if (CVal && CVal->isNullValue()) {
3647 std::swap(TVal, FVal);
3648 std::swap(CTVal, CFVal);
3649 CC = ISD::getSetCCInverse(CC, true);
3651 } else if (CTVal && CFVal) {
3652 const int64_t TrueVal = CTVal->getSExtValue();
3653 const int64_t FalseVal = CFVal->getSExtValue();
3656 // If both TVal and FVal are constants, see if FVal is the
3657 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3658 // instead of a CSEL in that case.
3659 if (TrueVal == ~FalseVal) {
3660 Opcode = AArch64ISD::CSINV;
3661 } else if (TrueVal == -FalseVal) {
3662 Opcode = AArch64ISD::CSNEG;
3663 } else if (TVal.getValueType() == MVT::i32) {
3664 // If our operands are only 32-bit wide, make sure we use 32-bit
3665 // arithmetic for the check whether we can use CSINC. This ensures that
3666 // the addition in the check will wrap around properly in case there is
3667 // an overflow (which would not be the case if we do the check with
3668 // 64-bit arithmetic).
3669 const uint32_t TrueVal32 = CTVal->getZExtValue();
3670 const uint32_t FalseVal32 = CFVal->getZExtValue();
3672 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3673 Opcode = AArch64ISD::CSINC;
3675 if (TrueVal32 > FalseVal32) {
3679 // 64-bit check whether we can use CSINC.
3680 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3681 Opcode = AArch64ISD::CSINC;
3683 if (TrueVal > FalseVal) {
3688 // Swap TVal and FVal if necessary.
3690 std::swap(TVal, FVal);
3691 std::swap(CTVal, CFVal);
3692 CC = ISD::getSetCCInverse(CC, true);
3695 if (Opcode != AArch64ISD::CSEL) {
3696 // Drop FVal since we can get its value by simply inverting/negating
3703 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3705 EVT VT = TVal.getValueType();
3706 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3709 // Now we know we're dealing with FP values.
3710 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3711 assert(LHS.getValueType() == RHS.getValueType());
3712 EVT VT = TVal.getValueType();
3713 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3715 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3716 // clean. Some of them require two CSELs to implement.
3717 AArch64CC::CondCode CC1, CC2;
3718 changeFPCCToAArch64CC(CC, CC1, CC2);
3719 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3720 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3722 // If we need a second CSEL, emit it, using the output of the first as the
3723 // RHS. We're effectively OR'ing the two CC's together.
3724 if (CC2 != AArch64CC::AL) {
3725 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3726 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3729 // Otherwise, return the output of the first CSEL.
3733 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3734 SelectionDAG &DAG) const {
3735 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3736 SDValue LHS = Op.getOperand(0);
3737 SDValue RHS = Op.getOperand(1);
3738 SDValue TVal = Op.getOperand(2);
3739 SDValue FVal = Op.getOperand(3);
3741 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3744 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3745 SelectionDAG &DAG) const {
3746 SDValue CCVal = Op->getOperand(0);
3747 SDValue TVal = Op->getOperand(1);
3748 SDValue FVal = Op->getOperand(2);
3751 unsigned Opc = CCVal.getOpcode();
3752 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3754 if (CCVal.getResNo() == 1 &&
3755 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3756 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3757 // Only lower legal XALUO ops.
3758 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3761 AArch64CC::CondCode OFCC;
3762 SDValue Value, Overflow;
3763 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3764 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
3766 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3770 // Lower it the same way as we would lower a SELECT_CC node.
3773 if (CCVal.getOpcode() == ISD::SETCC) {
3774 LHS = CCVal.getOperand(0);
3775 RHS = CCVal.getOperand(1);
3776 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3779 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
3782 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3785 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3786 SelectionDAG &DAG) const {
3787 // Jump table entries as PC relative offsets. No additional tweaking
3788 // is necessary here. Just get the address of the jump table.
3789 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3790 EVT PtrVT = getPointerTy();
3793 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3794 !Subtarget->isTargetMachO()) {
3795 const unsigned char MO_NC = AArch64II::MO_NC;
3797 AArch64ISD::WrapperLarge, DL, PtrVT,
3798 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3799 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3800 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3801 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3802 AArch64II::MO_G0 | MO_NC));
3806 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3807 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3808 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3809 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3810 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3813 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3814 SelectionDAG &DAG) const {
3815 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3816 EVT PtrVT = getPointerTy();
3819 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3820 // Use the GOT for the large code model on iOS.
3821 if (Subtarget->isTargetMachO()) {
3822 SDValue GotAddr = DAG.getTargetConstantPool(
3823 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3825 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3828 const unsigned char MO_NC = AArch64II::MO_NC;
3830 AArch64ISD::WrapperLarge, DL, PtrVT,
3831 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3832 CP->getOffset(), AArch64II::MO_G3),
3833 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3834 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3835 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3836 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3837 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3838 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3840 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3841 // ELF, the only valid one on Darwin.
3843 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3844 CP->getOffset(), AArch64II::MO_PAGE);
3845 SDValue Lo = DAG.getTargetConstantPool(
3846 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3847 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3849 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3850 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3854 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3855 SelectionDAG &DAG) const {
3856 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3857 EVT PtrVT = getPointerTy();
3859 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3860 !Subtarget->isTargetMachO()) {
3861 const unsigned char MO_NC = AArch64II::MO_NC;
3863 AArch64ISD::WrapperLarge, DL, PtrVT,
3864 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3865 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3866 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3867 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3869 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3870 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3872 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3873 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3877 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3878 SelectionDAG &DAG) const {
3879 AArch64FunctionInfo *FuncInfo =
3880 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3884 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3885 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3886 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3887 MachinePointerInfo(SV), false, false, 0);
3890 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3891 SelectionDAG &DAG) const {
3892 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3893 // Standard, section B.3.
3894 MachineFunction &MF = DAG.getMachineFunction();
3895 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3898 SDValue Chain = Op.getOperand(0);
3899 SDValue VAList = Op.getOperand(1);
3900 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3901 SmallVector<SDValue, 4> MemOps;
3903 // void *__stack at offset 0
3905 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3906 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3907 MachinePointerInfo(SV), false, false, 8));
3909 // void *__gr_top at offset 8
3910 int GPRSize = FuncInfo->getVarArgsGPRSize();
3912 SDValue GRTop, GRTopAddr;
3914 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3915 DAG.getConstant(8, DL, getPointerTy()));
3917 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3918 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3919 DAG.getConstant(GPRSize, DL, getPointerTy()));
3921 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3922 MachinePointerInfo(SV, 8), false, false, 8));
3925 // void *__vr_top at offset 16
3926 int FPRSize = FuncInfo->getVarArgsFPRSize();
3928 SDValue VRTop, VRTopAddr;
3929 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3930 DAG.getConstant(16, DL, getPointerTy()));
3932 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3933 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3934 DAG.getConstant(FPRSize, DL, getPointerTy()));
3936 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3937 MachinePointerInfo(SV, 16), false, false, 8));
3940 // int __gr_offs at offset 24
3941 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3942 DAG.getConstant(24, DL, getPointerTy()));
3943 MemOps.push_back(DAG.getStore(Chain, DL,
3944 DAG.getConstant(-GPRSize, DL, MVT::i32),
3945 GROffsAddr, MachinePointerInfo(SV, 24), false,
3948 // int __vr_offs at offset 28
3949 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3950 DAG.getConstant(28, DL, getPointerTy()));
3951 MemOps.push_back(DAG.getStore(Chain, DL,
3952 DAG.getConstant(-FPRSize, DL, MVT::i32),
3953 VROffsAddr, MachinePointerInfo(SV, 28), false,
3956 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3959 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3960 SelectionDAG &DAG) const {
3961 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3962 : LowerAAPCS_VASTART(Op, DAG);
3965 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3966 SelectionDAG &DAG) const {
3967 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3970 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3971 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3972 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3974 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
3976 DAG.getConstant(VaListSize, DL, MVT::i32),
3977 8, false, false, false, MachinePointerInfo(DestSV),
3978 MachinePointerInfo(SrcSV));
3981 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3982 assert(Subtarget->isTargetDarwin() &&
3983 "automatic va_arg instruction only works on Darwin");
3985 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3986 EVT VT = Op.getValueType();
3988 SDValue Chain = Op.getOperand(0);
3989 SDValue Addr = Op.getOperand(1);
3990 unsigned Align = Op.getConstantOperandVal(3);
3992 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3993 MachinePointerInfo(V), false, false, false, 0);
3994 Chain = VAList.getValue(1);
3997 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3998 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3999 DAG.getConstant(Align - 1, DL, getPointerTy()));
4000 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
4001 DAG.getConstant(-(int64_t)Align, DL, getPointerTy()));
4004 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4005 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4007 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4008 // up to 64 bits. At the very least, we have to increase the striding of the
4009 // vaargs list to match this, and for FP values we need to introduce
4010 // FP_ROUND nodes as well.
4011 if (VT.isInteger() && !VT.isVector())
4013 bool NeedFPTrunc = false;
4014 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4019 // Increment the pointer, VAList, to the next vaarg
4020 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4021 DAG.getConstant(ArgSize, DL, getPointerTy()));
4022 // Store the incremented VAList to the legalized pointer
4023 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4026 // Load the actual argument out of the pointer VAList
4028 // Load the value as an f64.
4029 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4030 MachinePointerInfo(), false, false, false, 0);
4031 // Round the value down to an f32.
4032 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4033 DAG.getIntPtrConstant(1, DL));
4034 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4035 // Merge the rounded value with the chain output of the load.
4036 return DAG.getMergeValues(Ops, DL);
4039 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4043 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4044 SelectionDAG &DAG) const {
4045 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4046 MFI->setFrameAddressIsTaken(true);
4048 EVT VT = Op.getValueType();
4050 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4052 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4054 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4055 MachinePointerInfo(), false, false, false, 0);
4059 // FIXME? Maybe this could be a TableGen attribute on some registers and
4060 // this table could be generated automatically from RegInfo.
4061 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4063 unsigned Reg = StringSwitch<unsigned>(RegName)
4064 .Case("sp", AArch64::SP)
4068 report_fatal_error(Twine("Invalid register name \""
4069 + StringRef(RegName) + "\"."));
4072 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4073 SelectionDAG &DAG) const {
4074 MachineFunction &MF = DAG.getMachineFunction();
4075 MachineFrameInfo *MFI = MF.getFrameInfo();
4076 MFI->setReturnAddressIsTaken(true);
4078 EVT VT = Op.getValueType();
4080 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4082 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4083 SDValue Offset = DAG.getConstant(8, DL, getPointerTy());
4084 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4085 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4086 MachinePointerInfo(), false, false, false, 0);
4089 // Return LR, which contains the return address. Mark it an implicit live-in.
4090 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4091 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4094 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4095 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4096 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4097 SelectionDAG &DAG) const {
4098 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4099 EVT VT = Op.getValueType();
4100 unsigned VTBits = VT.getSizeInBits();
4102 SDValue ShOpLo = Op.getOperand(0);
4103 SDValue ShOpHi = Op.getOperand(1);
4104 SDValue ShAmt = Op.getOperand(2);
4106 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4108 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4110 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4111 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4112 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4113 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4114 DAG.getConstant(VTBits, dl, MVT::i64));
4115 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4117 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4118 ISD::SETGE, dl, DAG);
4119 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4121 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4122 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4124 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4126 // AArch64 shifts larger than the register width are wrapped rather than
4127 // clamped, so we can't just emit "hi >> x".
4128 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4129 SDValue TrueValHi = Opc == ISD::SRA
4130 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4131 DAG.getConstant(VTBits - 1, dl,
4133 : DAG.getConstant(0, dl, VT);
4135 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4137 SDValue Ops[2] = { Lo, Hi };
4138 return DAG.getMergeValues(Ops, dl);
4141 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4142 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4143 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4144 SelectionDAG &DAG) const {
4145 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4146 EVT VT = Op.getValueType();
4147 unsigned VTBits = VT.getSizeInBits();
4149 SDValue ShOpLo = Op.getOperand(0);
4150 SDValue ShOpHi = Op.getOperand(1);
4151 SDValue ShAmt = Op.getOperand(2);
4154 assert(Op.getOpcode() == ISD::SHL_PARTS);
4155 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4156 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4157 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4158 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4159 DAG.getConstant(VTBits, dl, MVT::i64));
4160 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4161 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4163 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4165 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4166 ISD::SETGE, dl, DAG);
4167 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4169 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4171 // AArch64 shifts of larger than register sizes are wrapped rather than
4172 // clamped, so we can't just emit "lo << a" if a is too big.
4173 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4174 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4176 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4178 SDValue Ops[2] = { Lo, Hi };
4179 return DAG.getMergeValues(Ops, dl);
4182 bool AArch64TargetLowering::isOffsetFoldingLegal(
4183 const GlobalAddressSDNode *GA) const {
4184 // The AArch64 target doesn't support folding offsets into global addresses.
4188 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4189 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4190 // FIXME: We should be able to handle f128 as well with a clever lowering.
4191 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4195 return AArch64_AM::getFP64Imm(Imm) != -1;
4196 else if (VT == MVT::f32)
4197 return AArch64_AM::getFP32Imm(Imm) != -1;
4201 //===----------------------------------------------------------------------===//
4202 // AArch64 Optimization Hooks
4203 //===----------------------------------------------------------------------===//
4205 //===----------------------------------------------------------------------===//
4206 // AArch64 Inline Assembly Support
4207 //===----------------------------------------------------------------------===//
4209 // Table of Constraints
4210 // TODO: This is the current set of constraints supported by ARM for the
4211 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4213 // r - A general register
4214 // w - An FP/SIMD register of some size in the range v0-v31
4215 // x - An FP/SIMD register of some size in the range v0-v15
4216 // I - Constant that can be used with an ADD instruction
4217 // J - Constant that can be used with a SUB instruction
4218 // K - Constant that can be used with a 32-bit logical instruction
4219 // L - Constant that can be used with a 64-bit logical instruction
4220 // M - Constant that can be used as a 32-bit MOV immediate
4221 // N - Constant that can be used as a 64-bit MOV immediate
4222 // Q - A memory reference with base register and no offset
4223 // S - A symbolic address
4224 // Y - Floating point constant zero
4225 // Z - Integer constant zero
4227 // Note that general register operands will be output using their 64-bit x
4228 // register name, whatever the size of the variable, unless the asm operand
4229 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4230 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4233 /// getConstraintType - Given a constraint letter, return the type of
4234 /// constraint it is for this target.
4235 AArch64TargetLowering::ConstraintType
4236 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4237 if (Constraint.size() == 1) {
4238 switch (Constraint[0]) {
4245 return C_RegisterClass;
4246 // An address with a single base register. Due to the way we
4247 // currently handle addresses it is the same as 'r'.
4252 return TargetLowering::getConstraintType(Constraint);
4255 /// Examine constraint type and operand type and determine a weight value.
4256 /// This object must already have been set up with the operand type
4257 /// and the current alternative constraint selected.
4258 TargetLowering::ConstraintWeight
4259 AArch64TargetLowering::getSingleConstraintMatchWeight(
4260 AsmOperandInfo &info, const char *constraint) const {
4261 ConstraintWeight weight = CW_Invalid;
4262 Value *CallOperandVal = info.CallOperandVal;
4263 // If we don't have a value, we can't do a match,
4264 // but allow it at the lowest weight.
4265 if (!CallOperandVal)
4267 Type *type = CallOperandVal->getType();
4268 // Look at the constraint type.
4269 switch (*constraint) {
4271 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4275 if (type->isFloatingPointTy() || type->isVectorTy())
4276 weight = CW_Register;
4279 weight = CW_Constant;
4285 std::pair<unsigned, const TargetRegisterClass *>
4286 AArch64TargetLowering::getRegForInlineAsmConstraint(
4287 const TargetRegisterInfo *TRI, const std::string &Constraint,
4289 if (Constraint.size() == 1) {
4290 switch (Constraint[0]) {
4292 if (VT.getSizeInBits() == 64)
4293 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4294 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4297 return std::make_pair(0U, &AArch64::FPR32RegClass);
4298 if (VT.getSizeInBits() == 64)
4299 return std::make_pair(0U, &AArch64::FPR64RegClass);
4300 if (VT.getSizeInBits() == 128)
4301 return std::make_pair(0U, &AArch64::FPR128RegClass);
4303 // The instructions that this constraint is designed for can
4304 // only take 128-bit registers so just use that regclass.
4306 if (VT.getSizeInBits() == 128)
4307 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4311 if (StringRef("{cc}").equals_lower(Constraint))
4312 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4314 // Use the default implementation in TargetLowering to convert the register
4315 // constraint into a member of a register class.
4316 std::pair<unsigned, const TargetRegisterClass *> Res;
4317 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4319 // Not found as a standard register?
4321 unsigned Size = Constraint.size();
4322 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4323 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4324 const std::string Reg =
4325 std::string(&Constraint[2], &Constraint[Size - 1]);
4326 int RegNo = atoi(Reg.c_str());
4327 if (RegNo >= 0 && RegNo <= 31) {
4328 // v0 - v31 are aliases of q0 - q31.
4329 // By default we'll emit v0-v31 for this unless there's a modifier where
4330 // we'll emit the correct register as well.
4331 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4332 Res.second = &AArch64::FPR128RegClass;
4340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4341 /// vector. If it is invalid, don't add anything to Ops.
4342 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4343 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4344 SelectionDAG &DAG) const {
4347 // Currently only support length 1 constraints.
4348 if (Constraint.length() != 1)
4351 char ConstraintLetter = Constraint[0];
4352 switch (ConstraintLetter) {
4356 // This set of constraints deal with valid constants for various instructions.
4357 // Validate and return a target constant for them if we can.
4359 // 'z' maps to xzr or wzr so it needs an input of 0.
4360 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4361 if (!C || C->getZExtValue() != 0)
4364 if (Op.getValueType() == MVT::i64)
4365 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4367 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4377 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4381 // Grab the value and do some validation.
4382 uint64_t CVal = C->getZExtValue();
4383 switch (ConstraintLetter) {
4384 // The I constraint applies only to simple ADD or SUB immediate operands:
4385 // i.e. 0 to 4095 with optional shift by 12
4386 // The J constraint applies only to ADD or SUB immediates that would be
4387 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4388 // instruction [or vice versa], in other words -1 to -4095 with optional
4389 // left shift by 12.
4391 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4395 uint64_t NVal = -C->getSExtValue();
4396 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4397 CVal = C->getSExtValue();
4402 // The K and L constraints apply *only* to logical immediates, including
4403 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4404 // been removed and MOV should be used). So these constraints have to
4405 // distinguish between bit patterns that are valid 32-bit or 64-bit
4406 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4407 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4410 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4414 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4417 // The M and N constraints are a superset of K and L respectively, for use
4418 // with the MOV (immediate) alias. As well as the logical immediates they
4419 // also match 32 or 64-bit immediates that can be loaded either using a
4420 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4421 // (M) or 64-bit 0x1234000000000000 (N) etc.
4422 // As a note some of this code is liberally stolen from the asm parser.
4424 if (!isUInt<32>(CVal))
4426 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4428 if ((CVal & 0xFFFF) == CVal)
4430 if ((CVal & 0xFFFF0000ULL) == CVal)
4432 uint64_t NCVal = ~(uint32_t)CVal;
4433 if ((NCVal & 0xFFFFULL) == NCVal)
4435 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4440 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4442 if ((CVal & 0xFFFFULL) == CVal)
4444 if ((CVal & 0xFFFF0000ULL) == CVal)
4446 if ((CVal & 0xFFFF00000000ULL) == CVal)
4448 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4450 uint64_t NCVal = ~CVal;
4451 if ((NCVal & 0xFFFFULL) == NCVal)
4453 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4455 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4457 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4465 // All assembler immediates are 64-bit integers.
4466 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4470 if (Result.getNode()) {
4471 Ops.push_back(Result);
4475 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4478 //===----------------------------------------------------------------------===//
4479 // AArch64 Advanced SIMD Support
4480 //===----------------------------------------------------------------------===//
4482 /// WidenVector - Given a value in the V64 register class, produce the
4483 /// equivalent value in the V128 register class.
4484 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4485 EVT VT = V64Reg.getValueType();
4486 unsigned NarrowSize = VT.getVectorNumElements();
4487 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4488 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4491 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4492 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4495 /// getExtFactor - Determine the adjustment factor for the position when
4496 /// generating an "extract from vector registers" instruction.
4497 static unsigned getExtFactor(SDValue &V) {
4498 EVT EltType = V.getValueType().getVectorElementType();
4499 return EltType.getSizeInBits() / 8;
4502 /// NarrowVector - Given a value in the V128 register class, produce the
4503 /// equivalent value in the V64 register class.
4504 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4505 EVT VT = V128Reg.getValueType();
4506 unsigned WideSize = VT.getVectorNumElements();
4507 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4508 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4511 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4514 // Gather data to see if the operation can be modelled as a
4515 // shuffle in combination with VEXTs.
4516 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4517 SelectionDAG &DAG) const {
4518 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4520 EVT VT = Op.getValueType();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 struct ShuffleSourceInfo {
4528 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4529 // be compatible with the shuffle we intend to construct. As a result
4530 // ShuffleVec will be some sliding window into the original Vec.
4533 // Code should guarantee that element i in Vec starts at element "WindowBase
4534 // + i * WindowScale in ShuffleVec".
4538 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4539 ShuffleSourceInfo(SDValue Vec)
4540 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4544 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4546 SmallVector<ShuffleSourceInfo, 2> Sources;
4547 for (unsigned i = 0; i < NumElts; ++i) {
4548 SDValue V = Op.getOperand(i);
4549 if (V.getOpcode() == ISD::UNDEF)
4551 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4552 // A shuffle can only come from building a vector from various
4553 // elements of other vectors.
4557 // Add this element source to the list if it's not already there.
4558 SDValue SourceVec = V.getOperand(0);
4559 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4560 if (Source == Sources.end())
4561 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4563 // Update the minimum and maximum lane number seen.
4564 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4565 Source->MinElt = std::min(Source->MinElt, EltNo);
4566 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4569 // Currently only do something sane when at most two source vectors
4571 if (Sources.size() > 2)
4574 // Find out the smallest element size among result and two sources, and use
4575 // it as element size to build the shuffle_vector.
4576 EVT SmallestEltTy = VT.getVectorElementType();
4577 for (auto &Source : Sources) {
4578 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4579 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4580 SmallestEltTy = SrcEltTy;
4583 unsigned ResMultiplier =
4584 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4585 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4586 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4588 // If the source vector is too wide or too narrow, we may nevertheless be able
4589 // to construct a compatible shuffle either by concatenating it with UNDEF or
4590 // extracting a suitable range of elements.
4591 for (auto &Src : Sources) {
4592 EVT SrcVT = Src.ShuffleVec.getValueType();
4594 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4597 // This stage of the search produces a source with the same element type as
4598 // the original, but with a total width matching the BUILD_VECTOR output.
4599 EVT EltVT = SrcVT.getVectorElementType();
4600 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4601 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4603 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4604 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4605 // We can pad out the smaller vector for free, so if it's part of a
4608 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4609 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4613 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4615 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4616 // Span too large for a VEXT to cope
4620 if (Src.MinElt >= NumSrcElts) {
4621 // The extraction can just take the second half
4623 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4624 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4625 Src.WindowBase = -NumSrcElts;
4626 } else if (Src.MaxElt < NumSrcElts) {
4627 // The extraction can just take the first half
4629 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4630 DAG.getConstant(0, dl, MVT::i64));
4632 // An actual VEXT is needed
4634 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4635 DAG.getConstant(0, dl, MVT::i64));
4637 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4638 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4639 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4641 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4643 DAG.getConstant(Imm, dl, MVT::i32));
4644 Src.WindowBase = -Src.MinElt;
4648 // Another possible incompatibility occurs from the vector element types. We
4649 // can fix this by bitcasting the source vectors to the same type we intend
4651 for (auto &Src : Sources) {
4652 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4653 if (SrcEltTy == SmallestEltTy)
4655 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4656 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4657 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4658 Src.WindowBase *= Src.WindowScale;
4661 // Final sanity check before we try to actually produce a shuffle.
4663 for (auto Src : Sources)
4664 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4667 // The stars all align, our next step is to produce the mask for the shuffle.
4668 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4669 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4670 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4671 SDValue Entry = Op.getOperand(i);
4672 if (Entry.getOpcode() == ISD::UNDEF)
4675 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4676 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4678 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4679 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4681 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4682 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4683 VT.getVectorElementType().getSizeInBits());
4684 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4686 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4687 // starting at the appropriate offset.
4688 int *LaneMask = &Mask[i * ResMultiplier];
4690 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4691 ExtractBase += NumElts * (Src - Sources.begin());
4692 for (int j = 0; j < LanesDefined; ++j)
4693 LaneMask[j] = ExtractBase + j;
4696 // Final check before we try to produce nonsense...
4697 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4700 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4701 for (unsigned i = 0; i < Sources.size(); ++i)
4702 ShuffleOps[i] = Sources[i].ShuffleVec;
4704 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4705 ShuffleOps[1], &Mask[0]);
4706 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4709 // check if an EXT instruction can handle the shuffle mask when the
4710 // vector sources of the shuffle are the same.
4711 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4712 unsigned NumElts = VT.getVectorNumElements();
4714 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4720 // If this is a VEXT shuffle, the immediate value is the index of the first
4721 // element. The other shuffle indices must be the successive elements after
4723 unsigned ExpectedElt = Imm;
4724 for (unsigned i = 1; i < NumElts; ++i) {
4725 // Increment the expected index. If it wraps around, just follow it
4726 // back to index zero and keep going.
4728 if (ExpectedElt == NumElts)
4732 continue; // ignore UNDEF indices
4733 if (ExpectedElt != static_cast<unsigned>(M[i]))
4740 // check if an EXT instruction can handle the shuffle mask when the
4741 // vector sources of the shuffle are different.
4742 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4744 // Look for the first non-undef element.
4745 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4746 [](int Elt) {return Elt >= 0;});
4748 // Benefit form APInt to handle overflow when calculating expected element.
4749 unsigned NumElts = VT.getVectorNumElements();
4750 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4751 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4752 // The following shuffle indices must be the successive elements after the
4753 // first real element.
4754 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4755 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4756 if (FirstWrongElt != M.end())
4759 // The index of an EXT is the first element if it is not UNDEF.
4760 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4761 // value of the first element. E.g.
4762 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4763 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4764 // ExpectedElt is the last mask index plus 1.
4765 Imm = ExpectedElt.getZExtValue();
4767 // There are two difference cases requiring to reverse input vectors.
4768 // For example, for vector <4 x i32> we have the following cases,
4769 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4770 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4771 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4772 // to reverse two input vectors.
4781 /// isREVMask - Check if a vector shuffle corresponds to a REV
4782 /// instruction with the specified blocksize. (The order of the elements
4783 /// within each block of the vector is reversed.)
4784 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4785 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4786 "Only possible block sizes for REV are: 16, 32, 64");
4788 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4792 unsigned NumElts = VT.getVectorNumElements();
4793 unsigned BlockElts = M[0] + 1;
4794 // If the first shuffle index is UNDEF, be optimistic.
4796 BlockElts = BlockSize / EltSz;
4798 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4801 for (unsigned i = 0; i < NumElts; ++i) {
4803 continue; // ignore UNDEF indices
4804 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4811 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4812 unsigned NumElts = VT.getVectorNumElements();
4813 WhichResult = (M[0] == 0 ? 0 : 1);
4814 unsigned Idx = WhichResult * NumElts / 2;
4815 for (unsigned i = 0; i != NumElts; i += 2) {
4816 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4817 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4825 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4826 unsigned NumElts = VT.getVectorNumElements();
4827 WhichResult = (M[0] == 0 ? 0 : 1);
4828 for (unsigned i = 0; i != NumElts; ++i) {
4830 continue; // ignore UNDEF indices
4831 if ((unsigned)M[i] != 2 * i + WhichResult)
4838 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4839 unsigned NumElts = VT.getVectorNumElements();
4840 WhichResult = (M[0] == 0 ? 0 : 1);
4841 for (unsigned i = 0; i < NumElts; i += 2) {
4842 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4843 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4849 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4850 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4851 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4852 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4853 unsigned NumElts = VT.getVectorNumElements();
4854 WhichResult = (M[0] == 0 ? 0 : 1);
4855 unsigned Idx = WhichResult * NumElts / 2;
4856 for (unsigned i = 0; i != NumElts; i += 2) {
4857 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4858 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4866 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4867 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4868 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4869 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4870 unsigned Half = VT.getVectorNumElements() / 2;
4871 WhichResult = (M[0] == 0 ? 0 : 1);
4872 for (unsigned j = 0; j != 2; ++j) {
4873 unsigned Idx = WhichResult;
4874 for (unsigned i = 0; i != Half; ++i) {
4875 int MIdx = M[i + j * Half];
4876 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4885 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4886 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4887 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4888 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4889 unsigned NumElts = VT.getVectorNumElements();
4890 WhichResult = (M[0] == 0 ? 0 : 1);
4891 for (unsigned i = 0; i < NumElts; i += 2) {
4892 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4893 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4899 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4900 bool &DstIsLeft, int &Anomaly) {
4901 if (M.size() != static_cast<size_t>(NumInputElements))
4904 int NumLHSMatch = 0, NumRHSMatch = 0;
4905 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4907 for (int i = 0; i < NumInputElements; ++i) {
4917 LastLHSMismatch = i;
4919 if (M[i] == i + NumInputElements)
4922 LastRHSMismatch = i;
4925 if (NumLHSMatch == NumInputElements - 1) {
4927 Anomaly = LastLHSMismatch;
4929 } else if (NumRHSMatch == NumInputElements - 1) {
4931 Anomaly = LastRHSMismatch;
4938 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4939 if (VT.getSizeInBits() != 128)
4942 unsigned NumElts = VT.getVectorNumElements();
4944 for (int I = 0, E = NumElts / 2; I != E; I++) {
4949 int Offset = NumElts / 2;
4950 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4951 if (Mask[I] != I + SplitLHS * Offset)
4958 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4960 EVT VT = Op.getValueType();
4961 SDValue V0 = Op.getOperand(0);
4962 SDValue V1 = Op.getOperand(1);
4963 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4965 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4966 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4969 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4971 if (!isConcatMask(Mask, VT, SplitV0))
4974 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4975 VT.getVectorNumElements() / 2);
4977 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4978 DAG.getConstant(0, DL, MVT::i64));
4980 if (V1.getValueType().getSizeInBits() == 128) {
4981 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4982 DAG.getConstant(0, DL, MVT::i64));
4984 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4987 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4988 /// the specified operations to build the shuffle.
4989 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4990 SDValue RHS, SelectionDAG &DAG,
4992 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4993 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4994 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4997 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5006 OP_VUZPL, // VUZP, left result
5007 OP_VUZPR, // VUZP, right result
5008 OP_VZIPL, // VZIP, left result
5009 OP_VZIPR, // VZIP, right result
5010 OP_VTRNL, // VTRN, left result
5011 OP_VTRNR // VTRN, right result
5014 if (OpNum == OP_COPY) {
5015 if (LHSID == (1 * 9 + 2) * 9 + 3)
5017 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5021 SDValue OpLHS, OpRHS;
5022 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5023 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5024 EVT VT = OpLHS.getValueType();
5028 llvm_unreachable("Unknown shuffle opcode!");
5030 // VREV divides the vector in half and swaps within the half.
5031 if (VT.getVectorElementType() == MVT::i32 ||
5032 VT.getVectorElementType() == MVT::f32)
5033 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5034 // vrev <4 x i16> -> REV32
5035 if (VT.getVectorElementType() == MVT::i16 ||
5036 VT.getVectorElementType() == MVT::f16)
5037 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5038 // vrev <4 x i8> -> REV16
5039 assert(VT.getVectorElementType() == MVT::i8);
5040 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5045 EVT EltTy = VT.getVectorElementType();
5047 if (EltTy == MVT::i8)
5048 Opcode = AArch64ISD::DUPLANE8;
5049 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5050 Opcode = AArch64ISD::DUPLANE16;
5051 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5052 Opcode = AArch64ISD::DUPLANE32;
5053 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5054 Opcode = AArch64ISD::DUPLANE64;
5056 llvm_unreachable("Invalid vector element type?");
5058 if (VT.getSizeInBits() == 64)
5059 OpLHS = WidenVector(OpLHS, DAG);
5060 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5061 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5066 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5067 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5068 DAG.getConstant(Imm, dl, MVT::i32));
5071 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5074 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5077 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5080 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5083 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5086 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5091 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5092 SelectionDAG &DAG) {
5093 // Check to see if we can use the TBL instruction.
5094 SDValue V1 = Op.getOperand(0);
5095 SDValue V2 = Op.getOperand(1);
5098 EVT EltVT = Op.getValueType().getVectorElementType();
5099 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5101 SmallVector<SDValue, 8> TBLMask;
5102 for (int Val : ShuffleMask) {
5103 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5104 unsigned Offset = Byte + Val * BytesPerElt;
5105 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5109 MVT IndexVT = MVT::v8i8;
5110 unsigned IndexLen = 8;
5111 if (Op.getValueType().getSizeInBits() == 128) {
5112 IndexVT = MVT::v16i8;
5116 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5117 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5120 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5122 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5123 Shuffle = DAG.getNode(
5124 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5125 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5126 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5127 makeArrayRef(TBLMask.data(), IndexLen)));
5129 if (IndexLen == 8) {
5130 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5131 Shuffle = DAG.getNode(
5132 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5133 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5134 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5135 makeArrayRef(TBLMask.data(), IndexLen)));
5137 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5138 // cannot currently represent the register constraints on the input
5140 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5141 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5142 // &TBLMask[0], IndexLen));
5143 Shuffle = DAG.getNode(
5144 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5145 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5147 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5148 makeArrayRef(TBLMask.data(), IndexLen)));
5151 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5154 static unsigned getDUPLANEOp(EVT EltType) {
5155 if (EltType == MVT::i8)
5156 return AArch64ISD::DUPLANE8;
5157 if (EltType == MVT::i16 || EltType == MVT::f16)
5158 return AArch64ISD::DUPLANE16;
5159 if (EltType == MVT::i32 || EltType == MVT::f32)
5160 return AArch64ISD::DUPLANE32;
5161 if (EltType == MVT::i64 || EltType == MVT::f64)
5162 return AArch64ISD::DUPLANE64;
5164 llvm_unreachable("Invalid vector element type?");
5167 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5168 SelectionDAG &DAG) const {
5170 EVT VT = Op.getValueType();
5172 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5174 // Convert shuffles that are directly supported on NEON to target-specific
5175 // DAG nodes, instead of keeping them as shuffles and matching them again
5176 // during code selection. This is more efficient and avoids the possibility
5177 // of inconsistencies between legalization and selection.
5178 ArrayRef<int> ShuffleMask = SVN->getMask();
5180 SDValue V1 = Op.getOperand(0);
5181 SDValue V2 = Op.getOperand(1);
5183 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5184 V1.getValueType().getSimpleVT())) {
5185 int Lane = SVN->getSplatIndex();
5186 // If this is undef splat, generate it via "just" vdup, if possible.
5190 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5191 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5193 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5194 // constant. If so, we can just reference the lane's definition directly.
5195 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5196 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5197 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5199 // Otherwise, duplicate from the lane of the input vector.
5200 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5202 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5203 // to make a vector of the same size as this SHUFFLE. We can ignore the
5204 // extract entirely, and canonicalise the concat using WidenVector.
5205 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5206 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5207 V1 = V1.getOperand(0);
5208 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5209 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5210 Lane -= Idx * VT.getVectorNumElements() / 2;
5211 V1 = WidenVector(V1.getOperand(Idx), DAG);
5212 } else if (VT.getSizeInBits() == 64)
5213 V1 = WidenVector(V1, DAG);
5215 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5218 if (isREVMask(ShuffleMask, VT, 64))
5219 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5220 if (isREVMask(ShuffleMask, VT, 32))
5221 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5222 if (isREVMask(ShuffleMask, VT, 16))
5223 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5225 bool ReverseEXT = false;
5227 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5230 Imm *= getExtFactor(V1);
5231 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5232 DAG.getConstant(Imm, dl, MVT::i32));
5233 } else if (V2->getOpcode() == ISD::UNDEF &&
5234 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5235 Imm *= getExtFactor(V1);
5236 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5237 DAG.getConstant(Imm, dl, MVT::i32));
5240 unsigned WhichResult;
5241 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5242 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5243 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5245 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5246 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5247 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5249 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5250 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5251 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5254 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5255 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5256 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5258 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5259 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5260 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5262 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5263 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5264 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5267 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5268 if (Concat.getNode())
5273 int NumInputElements = V1.getValueType().getVectorNumElements();
5274 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5275 SDValue DstVec = DstIsLeft ? V1 : V2;
5276 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5278 SDValue SrcVec = V1;
5279 int SrcLane = ShuffleMask[Anomaly];
5280 if (SrcLane >= NumInputElements) {
5282 SrcLane -= VT.getVectorNumElements();
5284 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5286 EVT ScalarVT = VT.getVectorElementType();
5288 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5289 ScalarVT = MVT::i32;
5292 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5293 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5297 // If the shuffle is not directly supported and it has 4 elements, use
5298 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5299 unsigned NumElts = VT.getVectorNumElements();
5301 unsigned PFIndexes[4];
5302 for (unsigned i = 0; i != 4; ++i) {
5303 if (ShuffleMask[i] < 0)
5306 PFIndexes[i] = ShuffleMask[i];
5309 // Compute the index in the perfect shuffle table.
5310 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5311 PFIndexes[2] * 9 + PFIndexes[3];
5312 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5313 unsigned Cost = (PFEntry >> 30);
5316 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5319 return GenerateTBL(Op, ShuffleMask, DAG);
5322 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5324 EVT VT = BVN->getValueType(0);
5325 APInt SplatBits, SplatUndef;
5326 unsigned SplatBitSize;
5328 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5329 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5331 for (unsigned i = 0; i < NumSplats; ++i) {
5332 CnstBits <<= SplatBitSize;
5333 UndefBits <<= SplatBitSize;
5334 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5335 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5344 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5345 SelectionDAG &DAG) const {
5346 BuildVectorSDNode *BVN =
5347 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5348 SDValue LHS = Op.getOperand(0);
5350 EVT VT = Op.getValueType();
5355 APInt CnstBits(VT.getSizeInBits(), 0);
5356 APInt UndefBits(VT.getSizeInBits(), 0);
5357 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5358 // We only have BIC vector immediate instruction, which is and-not.
5359 CnstBits = ~CnstBits;
5361 // We make use of a little bit of goto ickiness in order to avoid having to
5362 // duplicate the immediate matching logic for the undef toggled case.
5363 bool SecondTry = false;
5366 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5367 CnstBits = CnstBits.zextOrTrunc(64);
5368 uint64_t CnstVal = CnstBits.getZExtValue();
5370 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5371 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5372 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5373 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5374 DAG.getConstant(CnstVal, dl, MVT::i32),
5375 DAG.getConstant(0, dl, MVT::i32));
5376 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5379 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5380 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5381 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5382 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5383 DAG.getConstant(CnstVal, dl, MVT::i32),
5384 DAG.getConstant(8, dl, MVT::i32));
5385 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5388 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5389 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5391 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5392 DAG.getConstant(CnstVal, dl, MVT::i32),
5393 DAG.getConstant(16, dl, MVT::i32));
5394 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5397 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5400 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5401 DAG.getConstant(CnstVal, dl, MVT::i32),
5402 DAG.getConstant(24, dl, MVT::i32));
5403 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5406 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5409 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5410 DAG.getConstant(CnstVal, dl, MVT::i32),
5411 DAG.getConstant(0, dl, MVT::i32));
5412 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5415 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5416 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5417 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5418 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5419 DAG.getConstant(CnstVal, dl, MVT::i32),
5420 DAG.getConstant(8, dl, MVT::i32));
5421 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5428 CnstBits = ~UndefBits;
5432 // We can always fall back to a non-immediate AND.
5437 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5438 // consists of only the same constant int value, returned in reference arg
5440 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5441 uint64_t &ConstVal) {
5442 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5445 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5448 EVT VT = Bvec->getValueType(0);
5449 unsigned NumElts = VT.getVectorNumElements();
5450 for (unsigned i = 1; i < NumElts; ++i)
5451 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5453 ConstVal = FirstElt->getZExtValue();
5457 static unsigned getIntrinsicID(const SDNode *N) {
5458 unsigned Opcode = N->getOpcode();
5461 return Intrinsic::not_intrinsic;
5462 case ISD::INTRINSIC_WO_CHAIN: {
5463 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5464 if (IID < Intrinsic::num_intrinsics)
5466 return Intrinsic::not_intrinsic;
5471 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5472 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5473 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5474 // Also, logical shift right -> sri, with the same structure.
5475 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5476 EVT VT = N->getValueType(0);
5483 // Is the first op an AND?
5484 const SDValue And = N->getOperand(0);
5485 if (And.getOpcode() != ISD::AND)
5488 // Is the second op an shl or lshr?
5489 SDValue Shift = N->getOperand(1);
5490 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5491 // or AArch64ISD::VLSHR vector, #shift
5492 unsigned ShiftOpc = Shift.getOpcode();
5493 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5495 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5497 // Is the shift amount constant?
5498 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5502 // Is the and mask vector all constant?
5504 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5507 // Is C1 == ~C2, taking into account how much one can shift elements of a
5509 uint64_t C2 = C2node->getZExtValue();
5510 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5511 if (C2 > ElemSizeInBits)
5513 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5514 if ((C1 & ElemMask) != (~C2 & ElemMask))
5517 SDValue X = And.getOperand(0);
5518 SDValue Y = Shift.getOperand(0);
5521 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5523 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5524 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5525 Shift.getOperand(1));
5527 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5528 DEBUG(N->dump(&DAG));
5529 DEBUG(dbgs() << "into: \n");
5530 DEBUG(ResultSLI->dump(&DAG));
5536 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5537 SelectionDAG &DAG) const {
5538 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5539 if (EnableAArch64SlrGeneration) {
5540 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5545 BuildVectorSDNode *BVN =
5546 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5547 SDValue LHS = Op.getOperand(1);
5549 EVT VT = Op.getValueType();
5551 // OR commutes, so try swapping the operands.
5553 LHS = Op.getOperand(0);
5554 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5559 APInt CnstBits(VT.getSizeInBits(), 0);
5560 APInt UndefBits(VT.getSizeInBits(), 0);
5561 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5562 // We make use of a little bit of goto ickiness in order to avoid having to
5563 // duplicate the immediate matching logic for the undef toggled case.
5564 bool SecondTry = false;
5567 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5568 CnstBits = CnstBits.zextOrTrunc(64);
5569 uint64_t CnstVal = CnstBits.getZExtValue();
5571 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5572 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5573 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5574 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5575 DAG.getConstant(CnstVal, dl, MVT::i32),
5576 DAG.getConstant(0, dl, MVT::i32));
5577 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5580 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5581 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5582 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5583 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5584 DAG.getConstant(CnstVal, dl, MVT::i32),
5585 DAG.getConstant(8, dl, MVT::i32));
5586 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5589 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5590 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5591 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5592 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5593 DAG.getConstant(CnstVal, dl, MVT::i32),
5594 DAG.getConstant(16, dl, MVT::i32));
5595 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5598 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5599 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5600 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5601 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5602 DAG.getConstant(CnstVal, dl, MVT::i32),
5603 DAG.getConstant(24, dl, MVT::i32));
5604 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5607 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5608 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5609 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5610 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5611 DAG.getConstant(CnstVal, dl, MVT::i32),
5612 DAG.getConstant(0, dl, MVT::i32));
5613 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5616 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5617 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5618 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5619 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5620 DAG.getConstant(CnstVal, dl, MVT::i32),
5621 DAG.getConstant(8, dl, MVT::i32));
5622 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5629 CnstBits = UndefBits;
5633 // We can always fall back to a non-immediate OR.
5638 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5639 // be truncated to fit element width.
5640 static SDValue NormalizeBuildVector(SDValue Op,
5641 SelectionDAG &DAG) {
5642 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5644 EVT VT = Op.getValueType();
5645 EVT EltTy= VT.getVectorElementType();
5647 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5650 SmallVector<SDValue, 16> Ops;
5651 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5652 SDValue Lane = Op.getOperand(I);
5653 if (Lane.getOpcode() == ISD::Constant) {
5654 APInt LowBits(EltTy.getSizeInBits(),
5655 cast<ConstantSDNode>(Lane)->getZExtValue());
5656 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5658 Ops.push_back(Lane);
5660 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5663 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5664 SelectionDAG &DAG) const {
5666 EVT VT = Op.getValueType();
5667 Op = NormalizeBuildVector(Op, DAG);
5668 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5670 APInt CnstBits(VT.getSizeInBits(), 0);
5671 APInt UndefBits(VT.getSizeInBits(), 0);
5672 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5673 // We make use of a little bit of goto ickiness in order to avoid having to
5674 // duplicate the immediate matching logic for the undef toggled case.
5675 bool SecondTry = false;
5678 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5679 CnstBits = CnstBits.zextOrTrunc(64);
5680 uint64_t CnstVal = CnstBits.getZExtValue();
5682 // Certain magic vector constants (used to express things like NOT
5683 // and NEG) are passed through unmodified. This allows codegen patterns
5684 // for these operations to match. Special-purpose patterns will lower
5685 // these immediates to MOVIs if it proves necessary.
5686 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5689 // The many faces of MOVI...
5690 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5691 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5692 if (VT.getSizeInBits() == 128) {
5693 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5694 DAG.getConstant(CnstVal, dl, MVT::i32));
5695 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5698 // Support the V64 version via subregister insertion.
5699 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5700 DAG.getConstant(CnstVal, dl, MVT::i32));
5701 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5704 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5705 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5706 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5707 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5708 DAG.getConstant(CnstVal, dl, MVT::i32),
5709 DAG.getConstant(0, dl, MVT::i32));
5710 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5713 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5714 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5715 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5716 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5717 DAG.getConstant(CnstVal, dl, MVT::i32),
5718 DAG.getConstant(8, dl, MVT::i32));
5719 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5722 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5723 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5724 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5725 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5726 DAG.getConstant(CnstVal, dl, MVT::i32),
5727 DAG.getConstant(16, dl, MVT::i32));
5728 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5731 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5732 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5733 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5734 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5735 DAG.getConstant(CnstVal, dl, MVT::i32),
5736 DAG.getConstant(24, dl, MVT::i32));
5737 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5740 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5741 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5742 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5743 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5744 DAG.getConstant(CnstVal, dl, MVT::i32),
5745 DAG.getConstant(0, dl, MVT::i32));
5746 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5749 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5750 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5751 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5752 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5753 DAG.getConstant(CnstVal, dl, MVT::i32),
5754 DAG.getConstant(8, dl, MVT::i32));
5755 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5758 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5759 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5760 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5761 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5762 DAG.getConstant(CnstVal, dl, MVT::i32),
5763 DAG.getConstant(264, dl, MVT::i32));
5764 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5767 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5768 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5769 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5770 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5771 DAG.getConstant(CnstVal, dl, MVT::i32),
5772 DAG.getConstant(272, dl, MVT::i32));
5773 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5776 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5777 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5778 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5779 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5780 DAG.getConstant(CnstVal, dl, MVT::i32));
5781 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5784 // The few faces of FMOV...
5785 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5786 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5787 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5788 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5789 DAG.getConstant(CnstVal, dl, MVT::i32));
5790 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5793 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5794 VT.getSizeInBits() == 128) {
5795 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5796 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5797 DAG.getConstant(CnstVal, dl, MVT::i32));
5798 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5801 // The many faces of MVNI...
5803 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5804 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5805 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5806 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5807 DAG.getConstant(CnstVal, dl, MVT::i32),
5808 DAG.getConstant(0, dl, MVT::i32));
5809 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5812 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5813 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5814 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5815 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5816 DAG.getConstant(CnstVal, dl, MVT::i32),
5817 DAG.getConstant(8, dl, MVT::i32));
5818 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5821 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5822 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5823 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5824 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5825 DAG.getConstant(CnstVal, dl, MVT::i32),
5826 DAG.getConstant(16, dl, MVT::i32));
5827 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5830 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5831 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5832 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5833 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5834 DAG.getConstant(CnstVal, dl, MVT::i32),
5835 DAG.getConstant(24, dl, MVT::i32));
5836 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5839 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5840 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5841 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5842 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5843 DAG.getConstant(CnstVal, dl, MVT::i32),
5844 DAG.getConstant(0, dl, MVT::i32));
5845 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5848 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5849 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5850 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5851 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5852 DAG.getConstant(CnstVal, dl, MVT::i32),
5853 DAG.getConstant(8, dl, MVT::i32));
5854 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5857 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5858 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5859 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5860 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5861 DAG.getConstant(CnstVal, dl, MVT::i32),
5862 DAG.getConstant(264, dl, MVT::i32));
5863 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5866 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5867 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5868 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5869 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5870 DAG.getConstant(CnstVal, dl, MVT::i32),
5871 DAG.getConstant(272, dl, MVT::i32));
5872 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5879 CnstBits = UndefBits;
5884 // Scan through the operands to find some interesting properties we can
5886 // 1) If only one value is used, we can use a DUP, or
5887 // 2) if only the low element is not undef, we can just insert that, or
5888 // 3) if only one constant value is used (w/ some non-constant lanes),
5889 // we can splat the constant value into the whole vector then fill
5890 // in the non-constant lanes.
5891 // 4) FIXME: If different constant values are used, but we can intelligently
5892 // select the values we'll be overwriting for the non-constant
5893 // lanes such that we can directly materialize the vector
5894 // some other way (MOVI, e.g.), we can be sneaky.
5895 unsigned NumElts = VT.getVectorNumElements();
5896 bool isOnlyLowElement = true;
5897 bool usesOnlyOneValue = true;
5898 bool usesOnlyOneConstantValue = true;
5899 bool isConstant = true;
5900 unsigned NumConstantLanes = 0;
5902 SDValue ConstantValue;
5903 for (unsigned i = 0; i < NumElts; ++i) {
5904 SDValue V = Op.getOperand(i);
5905 if (V.getOpcode() == ISD::UNDEF)
5908 isOnlyLowElement = false;
5909 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5912 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5914 if (!ConstantValue.getNode())
5916 else if (ConstantValue != V)
5917 usesOnlyOneConstantValue = false;
5920 if (!Value.getNode())
5922 else if (V != Value)
5923 usesOnlyOneValue = false;
5926 if (!Value.getNode())
5927 return DAG.getUNDEF(VT);
5929 if (isOnlyLowElement)
5930 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5932 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5933 // i32 and try again.
5934 if (usesOnlyOneValue) {
5936 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5937 Value.getValueType() != VT)
5938 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5940 // This is actually a DUPLANExx operation, which keeps everything vectory.
5942 // DUPLANE works on 128-bit vectors, widen it if necessary.
5943 SDValue Lane = Value.getOperand(1);
5944 Value = Value.getOperand(0);
5945 if (Value.getValueType().getSizeInBits() == 64)
5946 Value = WidenVector(Value, DAG);
5948 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5949 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5952 if (VT.getVectorElementType().isFloatingPoint()) {
5953 SmallVector<SDValue, 8> Ops;
5954 EVT EltTy = VT.getVectorElementType();
5955 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5956 "Unsupported floating-point vector type");
5957 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5958 for (unsigned i = 0; i < NumElts; ++i)
5959 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5960 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5961 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5962 Val = LowerBUILD_VECTOR(Val, DAG);
5964 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5968 // If there was only one constant value used and for more than one lane,
5969 // start by splatting that value, then replace the non-constant lanes. This
5970 // is better than the default, which will perform a separate initialization
5972 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5973 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5974 // Now insert the non-constant lanes.
5975 for (unsigned i = 0; i < NumElts; ++i) {
5976 SDValue V = Op.getOperand(i);
5977 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
5978 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5979 // Note that type legalization likely mucked about with the VT of the
5980 // source operand, so we may have to convert it here before inserting.
5981 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5987 // If all elements are constants and the case above didn't get hit, fall back
5988 // to the default expansion, which will generate a load from the constant
5993 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5995 SDValue shuffle = ReconstructShuffle(Op, DAG);
5996 if (shuffle != SDValue())
6000 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6001 // know the default expansion would otherwise fall back on something even
6002 // worse. For a vector with one or two non-undef values, that's
6003 // scalar_to_vector for the elements followed by a shuffle (provided the
6004 // shuffle is valid for the target) and materialization element by element
6005 // on the stack followed by a load for everything else.
6006 if (!isConstant && !usesOnlyOneValue) {
6007 SDValue Vec = DAG.getUNDEF(VT);
6008 SDValue Op0 = Op.getOperand(0);
6009 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6011 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6012 // a) Avoid a RMW dependency on the full vector register, and
6013 // b) Allow the register coalescer to fold away the copy if the
6014 // value is already in an S or D register.
6015 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6016 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6018 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6019 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6020 Vec = SDValue(N, 0);
6023 for (; i < NumElts; ++i) {
6024 SDValue V = Op.getOperand(i);
6025 if (V.getOpcode() == ISD::UNDEF)
6027 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6028 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6033 // Just use the default expansion. We failed to find a better alternative.
6037 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6038 SelectionDAG &DAG) const {
6039 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6041 // Check for non-constant or out of range lane.
6042 EVT VT = Op.getOperand(0).getValueType();
6043 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6044 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6048 // Insertion/extraction are legal for V128 types.
6049 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6050 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6054 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6055 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6058 // For V64 types, we perform insertion by expanding the value
6059 // to a V128 type and perform the insertion on that.
6061 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6062 EVT WideTy = WideVec.getValueType();
6064 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6065 Op.getOperand(1), Op.getOperand(2));
6066 // Re-narrow the resultant vector.
6067 return NarrowVector(Node, DAG);
6071 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6072 SelectionDAG &DAG) const {
6073 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6075 // Check for non-constant or out of range lane.
6076 EVT VT = Op.getOperand(0).getValueType();
6077 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6078 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6082 // Insertion/extraction are legal for V128 types.
6083 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6084 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6088 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6089 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6092 // For V64 types, we perform extraction by expanding the value
6093 // to a V128 type and perform the extraction on that.
6095 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6096 EVT WideTy = WideVec.getValueType();
6098 EVT ExtrTy = WideTy.getVectorElementType();
6099 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6102 // For extractions, we just return the result directly.
6103 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6107 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6108 SelectionDAG &DAG) const {
6109 EVT VT = Op.getOperand(0).getValueType();
6115 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6118 unsigned Val = Cst->getZExtValue();
6120 unsigned Size = Op.getValueType().getSizeInBits();
6124 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6127 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6130 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6133 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6136 llvm_unreachable("Unexpected vector type in extract_subvector!");
6139 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6141 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6147 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6149 if (VT.getVectorNumElements() == 4 &&
6150 (VT.is128BitVector() || VT.is64BitVector())) {
6151 unsigned PFIndexes[4];
6152 for (unsigned i = 0; i != 4; ++i) {
6156 PFIndexes[i] = M[i];
6159 // Compute the index in the perfect shuffle table.
6160 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6161 PFIndexes[2] * 9 + PFIndexes[3];
6162 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6163 unsigned Cost = (PFEntry >> 30);
6171 unsigned DummyUnsigned;
6173 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6174 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6175 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6176 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6177 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6178 isZIPMask(M, VT, DummyUnsigned) ||
6179 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6180 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6181 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6182 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6183 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6186 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6187 /// operand of a vector shift operation, where all the elements of the
6188 /// build_vector must have the same constant integer value.
6189 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6190 // Ignore bit_converts.
6191 while (Op.getOpcode() == ISD::BITCAST)
6192 Op = Op.getOperand(0);
6193 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6194 APInt SplatBits, SplatUndef;
6195 unsigned SplatBitSize;
6197 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6198 HasAnyUndefs, ElementBits) ||
6199 SplatBitSize > ElementBits)
6201 Cnt = SplatBits.getSExtValue();
6205 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6206 /// operand of a vector shift left operation. That value must be in the range:
6207 /// 0 <= Value < ElementBits for a left shift; or
6208 /// 0 <= Value <= ElementBits for a long left shift.
6209 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6210 assert(VT.isVector() && "vector shift count is not a vector type");
6211 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6212 if (!getVShiftImm(Op, ElementBits, Cnt))
6214 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6217 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6218 /// operand of a vector shift right operation. For a shift opcode, the value
6219 /// is positive, but for an intrinsic the value count must be negative. The
6220 /// absolute value must be in the range:
6221 /// 1 <= |Value| <= ElementBits for a right shift; or
6222 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6223 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6225 assert(VT.isVector() && "vector shift count is not a vector type");
6226 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6227 if (!getVShiftImm(Op, ElementBits, Cnt))
6231 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6234 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6235 SelectionDAG &DAG) const {
6236 EVT VT = Op.getValueType();
6240 if (!Op.getOperand(1).getValueType().isVector())
6242 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6244 switch (Op.getOpcode()) {
6246 llvm_unreachable("unexpected shift opcode");
6249 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6250 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6251 DAG.getConstant(Cnt, DL, MVT::i32));
6252 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6253 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6255 Op.getOperand(0), Op.getOperand(1));
6258 // Right shift immediate
6259 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6262 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6263 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6264 DAG.getConstant(Cnt, DL, MVT::i32));
6267 // Right shift register. Note, there is not a shift right register
6268 // instruction, but the shift left register instruction takes a signed
6269 // value, where negative numbers specify a right shift.
6270 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6271 : Intrinsic::aarch64_neon_ushl;
6272 // negate the shift amount
6273 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6274 SDValue NegShiftLeft =
6275 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6276 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6278 return NegShiftLeft;
6284 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6285 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6286 SDLoc dl, SelectionDAG &DAG) {
6287 EVT SrcVT = LHS.getValueType();
6288 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6289 "function only supposed to emit natural comparisons");
6291 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6292 APInt CnstBits(VT.getSizeInBits(), 0);
6293 APInt UndefBits(VT.getSizeInBits(), 0);
6294 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6295 bool IsZero = IsCnst && (CnstBits == 0);
6297 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6301 case AArch64CC::NE: {
6304 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6306 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6307 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6311 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6312 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6315 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6316 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6319 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6320 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6323 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6324 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6328 // If we ignore NaNs then we can use to the MI implementation.
6332 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6333 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6340 case AArch64CC::NE: {
6343 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6345 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6346 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6350 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6351 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6354 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6355 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6358 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6359 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6362 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6363 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6365 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6367 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6370 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6371 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6373 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6375 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6379 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6380 SelectionDAG &DAG) const {
6381 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6382 SDValue LHS = Op.getOperand(0);
6383 SDValue RHS = Op.getOperand(1);
6384 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6387 if (LHS.getValueType().getVectorElementType().isInteger()) {
6388 assert(LHS.getValueType() == RHS.getValueType());
6389 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6391 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6392 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6395 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6396 LHS.getValueType().getVectorElementType() == MVT::f64);
6398 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6399 // clean. Some of them require two branches to implement.
6400 AArch64CC::CondCode CC1, CC2;
6402 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6404 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6406 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6410 if (CC2 != AArch64CC::AL) {
6412 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6413 if (!Cmp2.getNode())
6416 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6419 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6422 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6427 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6428 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6429 /// specified in the intrinsic calls.
6430 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6432 unsigned Intrinsic) const {
6433 switch (Intrinsic) {
6434 case Intrinsic::aarch64_neon_ld2:
6435 case Intrinsic::aarch64_neon_ld3:
6436 case Intrinsic::aarch64_neon_ld4:
6437 case Intrinsic::aarch64_neon_ld1x2:
6438 case Intrinsic::aarch64_neon_ld1x3:
6439 case Intrinsic::aarch64_neon_ld1x4:
6440 case Intrinsic::aarch64_neon_ld2lane:
6441 case Intrinsic::aarch64_neon_ld3lane:
6442 case Intrinsic::aarch64_neon_ld4lane:
6443 case Intrinsic::aarch64_neon_ld2r:
6444 case Intrinsic::aarch64_neon_ld3r:
6445 case Intrinsic::aarch64_neon_ld4r: {
6446 Info.opc = ISD::INTRINSIC_W_CHAIN;
6447 // Conservatively set memVT to the entire set of vectors loaded.
6448 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6449 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6450 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6453 Info.vol = false; // volatile loads with NEON intrinsics not supported
6454 Info.readMem = true;
6455 Info.writeMem = false;
6458 case Intrinsic::aarch64_neon_st2:
6459 case Intrinsic::aarch64_neon_st3:
6460 case Intrinsic::aarch64_neon_st4:
6461 case Intrinsic::aarch64_neon_st1x2:
6462 case Intrinsic::aarch64_neon_st1x3:
6463 case Intrinsic::aarch64_neon_st1x4:
6464 case Intrinsic::aarch64_neon_st2lane:
6465 case Intrinsic::aarch64_neon_st3lane:
6466 case Intrinsic::aarch64_neon_st4lane: {
6467 Info.opc = ISD::INTRINSIC_VOID;
6468 // Conservatively set memVT to the entire set of vectors stored.
6469 unsigned NumElts = 0;
6470 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6471 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6472 if (!ArgTy->isVectorTy())
6474 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6476 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6477 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6480 Info.vol = false; // volatile stores with NEON intrinsics not supported
6481 Info.readMem = false;
6482 Info.writeMem = true;
6485 case Intrinsic::aarch64_ldaxr:
6486 case Intrinsic::aarch64_ldxr: {
6487 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6488 Info.opc = ISD::INTRINSIC_W_CHAIN;
6489 Info.memVT = MVT::getVT(PtrTy->getElementType());
6490 Info.ptrVal = I.getArgOperand(0);
6492 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6494 Info.readMem = true;
6495 Info.writeMem = false;
6498 case Intrinsic::aarch64_stlxr:
6499 case Intrinsic::aarch64_stxr: {
6500 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6501 Info.opc = ISD::INTRINSIC_W_CHAIN;
6502 Info.memVT = MVT::getVT(PtrTy->getElementType());
6503 Info.ptrVal = I.getArgOperand(1);
6505 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6507 Info.readMem = false;
6508 Info.writeMem = true;
6511 case Intrinsic::aarch64_ldaxp:
6512 case Intrinsic::aarch64_ldxp: {
6513 Info.opc = ISD::INTRINSIC_W_CHAIN;
6514 Info.memVT = MVT::i128;
6515 Info.ptrVal = I.getArgOperand(0);
6519 Info.readMem = true;
6520 Info.writeMem = false;
6523 case Intrinsic::aarch64_stlxp:
6524 case Intrinsic::aarch64_stxp: {
6525 Info.opc = ISD::INTRINSIC_W_CHAIN;
6526 Info.memVT = MVT::i128;
6527 Info.ptrVal = I.getArgOperand(2);
6531 Info.readMem = false;
6532 Info.writeMem = true;
6542 // Truncations from 64-bit GPR to 32-bit GPR is free.
6543 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6544 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6546 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6547 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6548 return NumBits1 > NumBits2;
6550 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6551 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6553 unsigned NumBits1 = VT1.getSizeInBits();
6554 unsigned NumBits2 = VT2.getSizeInBits();
6555 return NumBits1 > NumBits2;
6558 /// Check if it is profitable to hoist instruction in then/else to if.
6559 /// Not profitable if I and it's user can form a FMA instruction
6560 /// because we prefer FMSUB/FMADD.
6561 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6562 if (I->getOpcode() != Instruction::FMul)
6565 if (I->getNumUses() != 1)
6568 Instruction *User = I->user_back();
6571 !(User->getOpcode() == Instruction::FSub ||
6572 User->getOpcode() == Instruction::FAdd))
6575 const TargetOptions &Options = getTargetMachine().Options;
6576 EVT VT = getValueType(User->getOperand(0)->getType());
6578 if (isFMAFasterThanFMulAndFAdd(VT) &&
6579 isOperationLegalOrCustom(ISD::FMA, VT) &&
6580 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6586 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6588 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6589 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6591 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6592 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6593 return NumBits1 == 32 && NumBits2 == 64;
6595 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6596 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6598 unsigned NumBits1 = VT1.getSizeInBits();
6599 unsigned NumBits2 = VT2.getSizeInBits();
6600 return NumBits1 == 32 && NumBits2 == 64;
6603 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6604 EVT VT1 = Val.getValueType();
6605 if (isZExtFree(VT1, VT2)) {
6609 if (Val.getOpcode() != ISD::LOAD)
6612 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6613 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6614 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6615 VT1.getSizeInBits() <= 32);
6618 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6619 if (isa<FPExtInst>(Ext))
6622 // Vector types are next free.
6623 if (Ext->getType()->isVectorTy())
6626 for (const Use &U : Ext->uses()) {
6627 // The extension is free if we can fold it with a left shift in an
6628 // addressing mode or an arithmetic operation: add, sub, and cmp.
6630 // Is there a shift?
6631 const Instruction *Instr = cast<Instruction>(U.getUser());
6633 // Is this a constant shift?
6634 switch (Instr->getOpcode()) {
6635 case Instruction::Shl:
6636 if (!isa<ConstantInt>(Instr->getOperand(1)))
6639 case Instruction::GetElementPtr: {
6640 gep_type_iterator GTI = gep_type_begin(Instr);
6641 std::advance(GTI, U.getOperandNo());
6643 // This extension will end up with a shift because of the scaling factor.
6644 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6645 // Get the shift amount based on the scaling factor:
6646 // log2(sizeof(IdxTy)) - log2(8).
6648 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6649 // Is the constant foldable in the shift of the addressing mode?
6650 // I.e., shift amount is between 1 and 4 inclusive.
6651 if (ShiftAmt == 0 || ShiftAmt > 4)
6655 case Instruction::Trunc:
6656 // Check if this is a noop.
6657 // trunc(sext ty1 to ty2) to ty1.
6658 if (Instr->getType() == Ext->getOperand(0)->getType())
6665 // At this point we can use the bfm family, so this extension is free
6671 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6672 unsigned &RequiredAligment) const {
6673 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6675 // Cyclone supports unaligned accesses.
6676 RequiredAligment = 0;
6677 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6678 return NumBits == 32 || NumBits == 64;
6681 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6682 unsigned &RequiredAligment) const {
6683 if (!LoadedType.isSimple() ||
6684 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6686 // Cyclone supports unaligned accesses.
6687 RequiredAligment = 0;
6688 unsigned NumBits = LoadedType.getSizeInBits();
6689 return NumBits == 32 || NumBits == 64;
6692 /// \brief Lower an interleaved load into a ldN intrinsic.
6694 /// E.g. Lower an interleaved load (Factor = 2):
6695 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6696 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6697 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6700 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6701 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6702 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6703 bool AArch64TargetLowering::lowerInterleavedLoad(
6704 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6705 ArrayRef<unsigned> Indices, unsigned Factor) const {
6706 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6707 "Invalid interleave factor");
6708 assert(!Shuffles.empty() && "Empty shufflevector input");
6709 assert(Shuffles.size() == Indices.size() &&
6710 "Unmatched number of shufflevectors and indices");
6712 const DataLayout *DL = getDataLayout();
6714 VectorType *VecTy = Shuffles[0]->getType();
6715 unsigned VecSize = DL->getTypeAllocSizeInBits(VecTy);
6717 // Skip illegal vector types.
6718 if (VecSize != 64 && VecSize != 128)
6721 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6722 // load integer vectors first and then convert to pointer vectors.
6723 Type *EltTy = VecTy->getVectorElementType();
6724 if (EltTy->isPointerTy())
6725 VecTy = VectorType::get(DL->getIntPtrType(EltTy),
6726 VecTy->getVectorNumElements());
6728 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
6729 Type *Tys[2] = {VecTy, PtrTy};
6730 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
6731 Intrinsic::aarch64_neon_ld3,
6732 Intrinsic::aarch64_neon_ld4};
6734 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
6736 IRBuilder<> Builder(LI);
6737 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
6739 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
6741 // Replace uses of each shufflevector with the corresponding vector loaded
6743 for (unsigned i = 0; i < Shuffles.size(); i++) {
6744 ShuffleVectorInst *SVI = Shuffles[i];
6745 unsigned Index = Indices[i];
6747 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
6749 // Convert the integer vector to pointer vector if the element is pointer.
6750 if (EltTy->isPointerTy())
6751 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
6753 SVI->replaceAllUsesWith(SubVec);
6759 /// \brief Get a mask consisting of sequential integers starting from \p Start.
6761 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
6762 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
6764 SmallVector<Constant *, 16> Mask;
6765 for (unsigned i = 0; i < NumElts; i++)
6766 Mask.push_back(Builder.getInt32(Start + i));
6768 return ConstantVector::get(Mask);
6771 /// \brief Lower an interleaved store into a stN intrinsic.
6773 /// E.g. Lower an interleaved store (Factor = 3):
6774 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
6775 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
6776 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
6779 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
6780 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
6781 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
6782 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
6784 /// Note that the new shufflevectors will be removed and we'll only generate one
6785 /// st3 instruction in CodeGen.
6786 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
6787 ShuffleVectorInst *SVI,
6788 unsigned Factor) const {
6789 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6790 "Invalid interleave factor");
6792 VectorType *VecTy = SVI->getType();
6793 assert(VecTy->getVectorNumElements() % Factor == 0 &&
6794 "Invalid interleaved store");
6796 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
6797 Type *EltTy = VecTy->getVectorElementType();
6798 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
6800 const DataLayout *DL = getDataLayout();
6801 unsigned SubVecSize = DL->getTypeAllocSizeInBits(SubVecTy);
6803 // Skip illegal vector types.
6804 if (SubVecSize != 64 && SubVecSize != 128)
6807 Value *Op0 = SVI->getOperand(0);
6808 Value *Op1 = SVI->getOperand(1);
6809 IRBuilder<> Builder(SI);
6811 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
6812 // vectors to integer vectors.
6813 if (EltTy->isPointerTy()) {
6814 Type *IntTy = DL->getIntPtrType(EltTy);
6815 unsigned NumOpElts =
6816 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
6818 // Convert to the corresponding integer vector.
6819 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
6820 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
6821 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
6823 SubVecTy = VectorType::get(IntTy, NumSubElts);
6826 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
6827 Type *Tys[2] = {SubVecTy, PtrTy};
6828 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
6829 Intrinsic::aarch64_neon_st3,
6830 Intrinsic::aarch64_neon_st4};
6832 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
6834 SmallVector<Value *, 5> Ops;
6836 // Split the shufflevector operands into sub vectors for the new stN call.
6837 for (unsigned i = 0; i < Factor; i++)
6838 Ops.push_back(Builder.CreateShuffleVector(
6839 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
6841 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
6842 Builder.CreateCall(StNFunc, Ops);
6846 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6847 unsigned AlignCheck) {
6848 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6849 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6852 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6853 unsigned SrcAlign, bool IsMemset,
6856 MachineFunction &MF) const {
6857 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6858 // instruction to materialize the v2i64 zero and one store (with restrictive
6859 // addressing mode). Just do two i64 store of zero-registers.
6861 const Function *F = MF.getFunction();
6862 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6863 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6864 (memOpAlign(SrcAlign, DstAlign, 16) ||
6865 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6869 (memOpAlign(SrcAlign, DstAlign, 8) ||
6870 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
6874 (memOpAlign(SrcAlign, DstAlign, 4) ||
6875 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
6881 // 12-bit optionally shifted immediates are legal for adds.
6882 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6883 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6888 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6889 // immediates is the same as for an add or a sub.
6890 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6893 return isLegalAddImmediate(Immed);
6896 /// isLegalAddressingMode - Return true if the addressing mode represented
6897 /// by AM is legal for this target, for a load/store of the specified type.
6898 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6900 unsigned AS) const {
6901 // AArch64 has five basic addressing modes:
6903 // reg + 9-bit signed offset
6904 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6906 // reg + SIZE_IN_BYTES * reg
6908 // No global is ever allowed as a base.
6912 // No reg+reg+imm addressing.
6913 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6916 // check reg + imm case:
6917 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6918 uint64_t NumBytes = 0;
6919 if (Ty->isSized()) {
6920 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6921 NumBytes = NumBits / 8;
6922 if (!isPowerOf2_64(NumBits))
6927 int64_t Offset = AM.BaseOffs;
6929 // 9-bit signed offset
6930 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6933 // 12-bit unsigned offset
6934 unsigned shift = Log2_64(NumBytes);
6935 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6936 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6937 (Offset >> shift) << shift == Offset)
6942 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6944 if (!AM.Scale || AM.Scale == 1 ||
6945 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6950 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6952 unsigned AS) const {
6953 // Scaling factors are not free at all.
6954 // Operands | Rt Latency
6955 // -------------------------------------------
6957 // -------------------------------------------
6958 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6959 // Rt, [Xn, Wm, <extend> #imm] |
6960 if (isLegalAddressingMode(AM, Ty, AS))
6961 // Scale represents reg2 * scale, thus account for 1 if
6962 // it is not equal to 0 or 1.
6963 return AM.Scale != 0 && AM.Scale != 1;
6967 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6968 VT = VT.getScalarType();
6973 switch (VT.getSimpleVT().SimpleTy) {
6985 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6986 // LR is a callee-save register, but we must treat it as clobbered by any call
6987 // site. Hence we include LR in the scratch registers, which are in turn added
6988 // as implicit-defs for stackmaps and patchpoints.
6989 static const MCPhysReg ScratchRegs[] = {
6990 AArch64::X16, AArch64::X17, AArch64::LR, 0
6996 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6997 EVT VT = N->getValueType(0);
6998 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6999 // it with shift to let it be lowered to UBFX.
7000 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7001 isa<ConstantSDNode>(N->getOperand(1))) {
7002 uint64_t TruncMask = N->getConstantOperandVal(1);
7003 if (isMask_64(TruncMask) &&
7004 N->getOperand(0).getOpcode() == ISD::SRL &&
7005 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7011 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7013 assert(Ty->isIntegerTy());
7015 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7019 int64_t Val = Imm.getSExtValue();
7020 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7023 if ((int64_t)Val < 0)
7026 Val &= (1LL << 32) - 1;
7028 unsigned LZ = countLeadingZeros((uint64_t)Val);
7029 unsigned Shift = (63 - LZ) / 16;
7030 // MOVZ is free so return true for one or fewer MOVK.
7034 // Generate SUBS and CSEL for integer abs.
7035 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7036 EVT VT = N->getValueType(0);
7038 SDValue N0 = N->getOperand(0);
7039 SDValue N1 = N->getOperand(1);
7042 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7043 // and change it to SUB and CSEL.
7044 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7045 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7046 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7047 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7048 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7049 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7051 // Generate SUBS & CSEL.
7053 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7054 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7055 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7056 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7057 SDValue(Cmp.getNode(), 1));
7062 // performXorCombine - Attempts to handle integer ABS.
7063 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7064 TargetLowering::DAGCombinerInfo &DCI,
7065 const AArch64Subtarget *Subtarget) {
7066 if (DCI.isBeforeLegalizeOps())
7069 return performIntegerAbsCombine(N, DAG);
7073 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7075 std::vector<SDNode *> *Created) const {
7076 // fold (sdiv X, pow2)
7077 EVT VT = N->getValueType(0);
7078 if ((VT != MVT::i32 && VT != MVT::i64) ||
7079 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7083 SDValue N0 = N->getOperand(0);
7084 unsigned Lg2 = Divisor.countTrailingZeros();
7085 SDValue Zero = DAG.getConstant(0, DL, VT);
7086 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7088 // Add (N0 < 0) ? Pow2 - 1 : 0;
7090 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7091 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7092 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7095 Created->push_back(Cmp.getNode());
7096 Created->push_back(Add.getNode());
7097 Created->push_back(CSel.getNode());
7102 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7104 // If we're dividing by a positive value, we're done. Otherwise, we must
7105 // negate the result.
7106 if (Divisor.isNonNegative())
7110 Created->push_back(SRA.getNode());
7111 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7114 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7115 TargetLowering::DAGCombinerInfo &DCI,
7116 const AArch64Subtarget *Subtarget) {
7117 if (DCI.isBeforeLegalizeOps())
7120 // Multiplication of a power of two plus/minus one can be done more
7121 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7122 // future CPUs have a cheaper MADD instruction, this may need to be
7123 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7124 // 64-bit is 5 cycles, so this is always a win.
7125 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7126 APInt Value = C->getAPIntValue();
7127 EVT VT = N->getValueType(0);
7129 if (Value.isNonNegative()) {
7130 // (mul x, 2^N + 1) => (add (shl x, N), x)
7131 APInt VM1 = Value - 1;
7132 if (VM1.isPowerOf2()) {
7133 SDValue ShiftedVal =
7134 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7135 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7136 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7139 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7140 APInt VP1 = Value + 1;
7141 if (VP1.isPowerOf2()) {
7142 SDValue ShiftedVal =
7143 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7144 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7145 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7149 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7150 APInt VNP1 = -Value + 1;
7151 if (VNP1.isPowerOf2()) {
7152 SDValue ShiftedVal =
7153 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7154 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7155 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7158 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7159 APInt VNM1 = -Value - 1;
7160 if (VNM1.isPowerOf2()) {
7161 SDValue ShiftedVal =
7162 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7163 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7165 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7166 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7173 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7174 SelectionDAG &DAG) {
7175 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7176 // optimize away operation when it's from a constant.
7178 // The general transformation is:
7179 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7180 // AND(VECTOR_CMP(x,y), constant2)
7181 // constant2 = UNARYOP(constant)
7183 // Early exit if this isn't a vector operation, the operand of the
7184 // unary operation isn't a bitwise AND, or if the sizes of the operations
7186 EVT VT = N->getValueType(0);
7187 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7188 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7189 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7192 // Now check that the other operand of the AND is a constant. We could
7193 // make the transformation for non-constant splats as well, but it's unclear
7194 // that would be a benefit as it would not eliminate any operations, just
7195 // perform one more step in scalar code before moving to the vector unit.
7196 if (BuildVectorSDNode *BV =
7197 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7198 // Bail out if the vector isn't a constant.
7199 if (!BV->isConstant())
7202 // Everything checks out. Build up the new and improved node.
7204 EVT IntVT = BV->getValueType(0);
7205 // Create a new constant of the appropriate type for the transformed
7207 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7208 // The AND node needs bitcasts to/from an integer vector type around it.
7209 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7210 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7211 N->getOperand(0)->getOperand(0), MaskConst);
7212 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7219 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7220 const AArch64Subtarget *Subtarget) {
7221 // First try to optimize away the conversion when it's conditionally from
7222 // a constant. Vectors only.
7223 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7224 if (Res != SDValue())
7227 EVT VT = N->getValueType(0);
7228 if (VT != MVT::f32 && VT != MVT::f64)
7231 // Only optimize when the source and destination types have the same width.
7232 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7235 // If the result of an integer load is only used by an integer-to-float
7236 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7237 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7238 SDValue N0 = N->getOperand(0);
7239 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7240 // Do not change the width of a volatile load.
7241 !cast<LoadSDNode>(N0)->isVolatile()) {
7242 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7243 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7244 LN0->getPointerInfo(), LN0->isVolatile(),
7245 LN0->isNonTemporal(), LN0->isInvariant(),
7246 LN0->getAlignment());
7248 // Make sure successors of the original load stay after it by updating them
7249 // to use the new Chain.
7250 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7253 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7254 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7260 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7261 /// searches for and classifies those shifts.
7262 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7264 if (N.getOpcode() == ISD::SHL)
7266 else if (N.getOpcode() == ISD::SRL)
7271 if (!isa<ConstantSDNode>(N.getOperand(1)))
7274 ShiftAmount = N->getConstantOperandVal(1);
7275 Src = N->getOperand(0);
7279 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7280 /// registers viewed as a high/low pair. This function looks for the pattern:
7281 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7282 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7284 static SDValue tryCombineToEXTR(SDNode *N,
7285 TargetLowering::DAGCombinerInfo &DCI) {
7286 SelectionDAG &DAG = DCI.DAG;
7288 EVT VT = N->getValueType(0);
7290 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7292 if (VT != MVT::i32 && VT != MVT::i64)
7296 uint32_t ShiftLHS = 0;
7298 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7302 uint32_t ShiftRHS = 0;
7304 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7307 // If they're both trying to come from the high part of the register, they're
7308 // not really an EXTR.
7309 if (LHSFromHi == RHSFromHi)
7312 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7316 std::swap(LHS, RHS);
7317 std::swap(ShiftLHS, ShiftRHS);
7320 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7321 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7324 static SDValue tryCombineToBSL(SDNode *N,
7325 TargetLowering::DAGCombinerInfo &DCI) {
7326 EVT VT = N->getValueType(0);
7327 SelectionDAG &DAG = DCI.DAG;
7333 SDValue N0 = N->getOperand(0);
7334 if (N0.getOpcode() != ISD::AND)
7337 SDValue N1 = N->getOperand(1);
7338 if (N1.getOpcode() != ISD::AND)
7341 // We only have to look for constant vectors here since the general, variable
7342 // case can be handled in TableGen.
7343 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7344 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7345 for (int i = 1; i >= 0; --i)
7346 for (int j = 1; j >= 0; --j) {
7347 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7348 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7352 bool FoundMatch = true;
7353 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7354 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7355 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7357 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7364 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7365 N0->getOperand(1 - i), N1->getOperand(1 - j));
7371 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7372 const AArch64Subtarget *Subtarget) {
7373 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7374 if (!EnableAArch64ExtrGeneration)
7376 SelectionDAG &DAG = DCI.DAG;
7377 EVT VT = N->getValueType(0);
7379 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7382 SDValue Res = tryCombineToEXTR(N, DCI);
7386 Res = tryCombineToBSL(N, DCI);
7393 static SDValue performBitcastCombine(SDNode *N,
7394 TargetLowering::DAGCombinerInfo &DCI,
7395 SelectionDAG &DAG) {
7396 // Wait 'til after everything is legalized to try this. That way we have
7397 // legal vector types and such.
7398 if (DCI.isBeforeLegalizeOps())
7401 // Remove extraneous bitcasts around an extract_subvector.
7403 // (v4i16 (bitconvert
7404 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7406 // (extract_subvector ((v8i16 ...), (i64 4)))
7408 // Only interested in 64-bit vectors as the ultimate result.
7409 EVT VT = N->getValueType(0);
7412 if (VT.getSimpleVT().getSizeInBits() != 64)
7414 // Is the operand an extract_subvector starting at the beginning or halfway
7415 // point of the vector? A low half may also come through as an
7416 // EXTRACT_SUBREG, so look for that, too.
7417 SDValue Op0 = N->getOperand(0);
7418 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7419 !(Op0->isMachineOpcode() &&
7420 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7422 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7423 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7424 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7426 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7427 if (idx != AArch64::dsub)
7429 // The dsub reference is equivalent to a lane zero subvector reference.
7432 // Look through the bitcast of the input to the extract.
7433 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7435 SDValue Source = Op0->getOperand(0)->getOperand(0);
7436 // If the source type has twice the number of elements as our destination
7437 // type, we know this is an extract of the high or low half of the vector.
7438 EVT SVT = Source->getValueType(0);
7439 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7442 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7444 // Create the simplified form to just extract the low or high half of the
7445 // vector directly rather than bothering with the bitcasts.
7447 unsigned NumElements = VT.getVectorNumElements();
7449 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7450 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7452 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7453 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7459 static SDValue performConcatVectorsCombine(SDNode *N,
7460 TargetLowering::DAGCombinerInfo &DCI,
7461 SelectionDAG &DAG) {
7463 EVT VT = N->getValueType(0);
7464 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7466 // Optimize concat_vectors of truncated vectors, where the intermediate
7467 // type is illegal, to avoid said illegality, e.g.,
7468 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7469 // (v2i16 (truncate (v2i64)))))
7471 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7472 // (v4i32 (bitcast (v2i64))),
7474 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7475 // on both input and result type, so we might generate worse code.
7476 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7477 if (N->getNumOperands() == 2 &&
7478 N0->getOpcode() == ISD::TRUNCATE &&
7479 N1->getOpcode() == ISD::TRUNCATE) {
7480 SDValue N00 = N0->getOperand(0);
7481 SDValue N10 = N1->getOperand(0);
7482 EVT N00VT = N00.getValueType();
7484 if (N00VT == N10.getValueType() &&
7485 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7486 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7487 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7488 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7489 for (size_t i = 0; i < Mask.size(); ++i)
7491 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7492 DAG.getVectorShuffle(
7494 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7495 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7499 // Wait 'til after everything is legalized to try this. That way we have
7500 // legal vector types and such.
7501 if (DCI.isBeforeLegalizeOps())
7504 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7505 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7506 // canonicalise to that.
7507 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7508 assert(VT.getVectorElementType().getSizeInBits() == 64);
7509 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7510 DAG.getConstant(0, dl, MVT::i64));
7513 // Canonicalise concat_vectors so that the right-hand vector has as few
7514 // bit-casts as possible before its real operation. The primary matching
7515 // destination for these operations will be the narrowing "2" instructions,
7516 // which depend on the operation being performed on this right-hand vector.
7518 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7520 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7522 if (N1->getOpcode() != ISD::BITCAST)
7524 SDValue RHS = N1->getOperand(0);
7525 MVT RHSTy = RHS.getValueType().getSimpleVT();
7526 // If the RHS is not a vector, this is not the pattern we're looking for.
7527 if (!RHSTy.isVector())
7530 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7532 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7533 RHSTy.getVectorNumElements() * 2);
7534 return DAG.getNode(ISD::BITCAST, dl, VT,
7535 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7536 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7540 static SDValue tryCombineFixedPointConvert(SDNode *N,
7541 TargetLowering::DAGCombinerInfo &DCI,
7542 SelectionDAG &DAG) {
7543 // Wait 'til after everything is legalized to try this. That way we have
7544 // legal vector types and such.
7545 if (DCI.isBeforeLegalizeOps())
7547 // Transform a scalar conversion of a value from a lane extract into a
7548 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7549 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7550 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7552 // The second form interacts better with instruction selection and the
7553 // register allocator to avoid cross-class register copies that aren't
7554 // coalescable due to a lane reference.
7556 // Check the operand and see if it originates from a lane extract.
7557 SDValue Op1 = N->getOperand(1);
7558 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7559 // Yep, no additional predication needed. Perform the transform.
7560 SDValue IID = N->getOperand(0);
7561 SDValue Shift = N->getOperand(2);
7562 SDValue Vec = Op1.getOperand(0);
7563 SDValue Lane = Op1.getOperand(1);
7564 EVT ResTy = N->getValueType(0);
7568 // The vector width should be 128 bits by the time we get here, even
7569 // if it started as 64 bits (the extract_vector handling will have
7571 assert(Vec.getValueType().getSizeInBits() == 128 &&
7572 "unexpected vector size on extract_vector_elt!");
7573 if (Vec.getValueType() == MVT::v4i32)
7574 VecResTy = MVT::v4f32;
7575 else if (Vec.getValueType() == MVT::v2i64)
7576 VecResTy = MVT::v2f64;
7578 llvm_unreachable("unexpected vector type!");
7581 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7587 // AArch64 high-vector "long" operations are formed by performing the non-high
7588 // version on an extract_subvector of each operand which gets the high half:
7590 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7592 // However, there are cases which don't have an extract_high explicitly, but
7593 // have another operation that can be made compatible with one for free. For
7596 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7598 // This routine does the actual conversion of such DUPs, once outer routines
7599 // have determined that everything else is in order.
7600 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7602 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7603 switch (N.getOpcode()) {
7604 case AArch64ISD::DUP:
7605 case AArch64ISD::DUPLANE8:
7606 case AArch64ISD::DUPLANE16:
7607 case AArch64ISD::DUPLANE32:
7608 case AArch64ISD::DUPLANE64:
7609 case AArch64ISD::MOVI:
7610 case AArch64ISD::MOVIshift:
7611 case AArch64ISD::MOVIedit:
7612 case AArch64ISD::MOVImsl:
7613 case AArch64ISD::MVNIshift:
7614 case AArch64ISD::MVNImsl:
7617 // FMOV could be supported, but isn't very useful, as it would only occur
7618 // if you passed a bitcast' floating point immediate to an eligible long
7619 // integer op (addl, smull, ...).
7623 MVT NarrowTy = N.getSimpleValueType();
7624 if (!NarrowTy.is64BitVector())
7627 MVT ElementTy = NarrowTy.getVectorElementType();
7628 unsigned NumElems = NarrowTy.getVectorNumElements();
7629 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7632 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7633 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7634 DAG.getConstant(NumElems, dl, MVT::i64));
7637 static bool isEssentiallyExtractSubvector(SDValue N) {
7638 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7641 return N.getOpcode() == ISD::BITCAST &&
7642 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7645 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7646 struct GenericSetCCInfo {
7647 const SDValue *Opnd0;
7648 const SDValue *Opnd1;
7652 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7653 struct AArch64SetCCInfo {
7655 AArch64CC::CondCode CC;
7658 /// \brief Helper structure to keep track of SetCC information.
7660 GenericSetCCInfo Generic;
7661 AArch64SetCCInfo AArch64;
7664 /// \brief Helper structure to be able to read SetCC information. If set to
7665 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7666 /// GenericSetCCInfo.
7667 struct SetCCInfoAndKind {
7672 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7674 /// AArch64 lowered one.
7675 /// \p SetCCInfo is filled accordingly.
7676 /// \post SetCCInfo is meanginfull only when this function returns true.
7677 /// \return True when Op is a kind of SET_CC operation.
7678 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7679 // If this is a setcc, this is straight forward.
7680 if (Op.getOpcode() == ISD::SETCC) {
7681 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7682 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7683 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7684 SetCCInfo.IsAArch64 = false;
7687 // Otherwise, check if this is a matching csel instruction.
7691 if (Op.getOpcode() != AArch64ISD::CSEL)
7693 // Set the information about the operands.
7694 // TODO: we want the operands of the Cmp not the csel
7695 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7696 SetCCInfo.IsAArch64 = true;
7697 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7698 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7700 // Check that the operands matches the constraints:
7701 // (1) Both operands must be constants.
7702 // (2) One must be 1 and the other must be 0.
7703 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7704 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7707 if (!TValue || !FValue)
7711 if (!TValue->isOne()) {
7712 // Update the comparison when we are interested in !cc.
7713 std::swap(TValue, FValue);
7714 SetCCInfo.Info.AArch64.CC =
7715 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7717 return TValue->isOne() && FValue->isNullValue();
7720 // Returns true if Op is setcc or zext of setcc.
7721 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7722 if (isSetCC(Op, Info))
7724 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7725 isSetCC(Op->getOperand(0), Info));
7728 // The folding we want to perform is:
7729 // (add x, [zext] (setcc cc ...) )
7731 // (csel x, (add x, 1), !cc ...)
7733 // The latter will get matched to a CSINC instruction.
7734 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7735 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7736 SDValue LHS = Op->getOperand(0);
7737 SDValue RHS = Op->getOperand(1);
7738 SetCCInfoAndKind InfoAndKind;
7740 // If neither operand is a SET_CC, give up.
7741 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7742 std::swap(LHS, RHS);
7743 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7747 // FIXME: This could be generatized to work for FP comparisons.
7748 EVT CmpVT = InfoAndKind.IsAArch64
7749 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7750 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7751 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7757 if (InfoAndKind.IsAArch64) {
7758 CCVal = DAG.getConstant(
7759 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
7761 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7763 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7764 *InfoAndKind.Info.Generic.Opnd1,
7765 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7768 EVT VT = Op->getValueType(0);
7769 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
7770 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7773 // The basic add/sub long vector instructions have variants with "2" on the end
7774 // which act on the high-half of their inputs. They are normally matched by
7777 // (add (zeroext (extract_high LHS)),
7778 // (zeroext (extract_high RHS)))
7779 // -> uaddl2 vD, vN, vM
7781 // However, if one of the extracts is something like a duplicate, this
7782 // instruction can still be used profitably. This function puts the DAG into a
7783 // more appropriate form for those patterns to trigger.
7784 static SDValue performAddSubLongCombine(SDNode *N,
7785 TargetLowering::DAGCombinerInfo &DCI,
7786 SelectionDAG &DAG) {
7787 if (DCI.isBeforeLegalizeOps())
7790 MVT VT = N->getSimpleValueType(0);
7791 if (!VT.is128BitVector()) {
7792 if (N->getOpcode() == ISD::ADD)
7793 return performSetccAddFolding(N, DAG);
7797 // Make sure both branches are extended in the same way.
7798 SDValue LHS = N->getOperand(0);
7799 SDValue RHS = N->getOperand(1);
7800 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7801 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7802 LHS.getOpcode() != RHS.getOpcode())
7805 unsigned ExtType = LHS.getOpcode();
7807 // It's not worth doing if at least one of the inputs isn't already an
7808 // extract, but we don't know which it'll be so we have to try both.
7809 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7810 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7814 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7815 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7816 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7820 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7823 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7826 // Massage DAGs which we can use the high-half "long" operations on into
7827 // something isel will recognize better. E.g.
7829 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7830 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7831 // (extract_high (v2i64 (dup128 scalar)))))
7833 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7834 TargetLowering::DAGCombinerInfo &DCI,
7835 SelectionDAG &DAG) {
7836 if (DCI.isBeforeLegalizeOps())
7839 SDValue LHS = N->getOperand(1);
7840 SDValue RHS = N->getOperand(2);
7841 assert(LHS.getValueType().is64BitVector() &&
7842 RHS.getValueType().is64BitVector() &&
7843 "unexpected shape for long operation");
7845 // Either node could be a DUP, but it's not worth doing both of them (you'd
7846 // just as well use the non-high version) so look for a corresponding extract
7847 // operation on the other "wing".
7848 if (isEssentiallyExtractSubvector(LHS)) {
7849 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7852 } else if (isEssentiallyExtractSubvector(RHS)) {
7853 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7858 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7859 N->getOperand(0), LHS, RHS);
7862 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7863 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7864 unsigned ElemBits = ElemTy.getSizeInBits();
7866 int64_t ShiftAmount;
7867 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7868 APInt SplatValue, SplatUndef;
7869 unsigned SplatBitSize;
7871 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7872 HasAnyUndefs, ElemBits) ||
7873 SplatBitSize != ElemBits)
7876 ShiftAmount = SplatValue.getSExtValue();
7877 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7878 ShiftAmount = CVN->getSExtValue();
7886 llvm_unreachable("Unknown shift intrinsic");
7887 case Intrinsic::aarch64_neon_sqshl:
7888 Opcode = AArch64ISD::SQSHL_I;
7889 IsRightShift = false;
7891 case Intrinsic::aarch64_neon_uqshl:
7892 Opcode = AArch64ISD::UQSHL_I;
7893 IsRightShift = false;
7895 case Intrinsic::aarch64_neon_srshl:
7896 Opcode = AArch64ISD::SRSHR_I;
7897 IsRightShift = true;
7899 case Intrinsic::aarch64_neon_urshl:
7900 Opcode = AArch64ISD::URSHR_I;
7901 IsRightShift = true;
7903 case Intrinsic::aarch64_neon_sqshlu:
7904 Opcode = AArch64ISD::SQSHLU_I;
7905 IsRightShift = false;
7909 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
7911 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7912 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
7913 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
7915 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7916 DAG.getConstant(ShiftAmount, dl, MVT::i32));
7922 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7923 // the intrinsics must be legal and take an i32, this means there's almost
7924 // certainly going to be a zext in the DAG which we can eliminate.
7925 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7926 SDValue AndN = N->getOperand(2);
7927 if (AndN.getOpcode() != ISD::AND)
7930 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7931 if (!CMask || CMask->getZExtValue() != Mask)
7934 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7935 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7938 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7939 SelectionDAG &DAG) {
7941 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
7942 DAG.getNode(Opc, dl,
7943 N->getOperand(1).getSimpleValueType(),
7945 DAG.getConstant(0, dl, MVT::i64));
7948 static SDValue performIntrinsicCombine(SDNode *N,
7949 TargetLowering::DAGCombinerInfo &DCI,
7950 const AArch64Subtarget *Subtarget) {
7951 SelectionDAG &DAG = DCI.DAG;
7952 unsigned IID = getIntrinsicID(N);
7956 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7957 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7958 return tryCombineFixedPointConvert(N, DCI, DAG);
7960 case Intrinsic::aarch64_neon_saddv:
7961 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7962 case Intrinsic::aarch64_neon_uaddv:
7963 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7964 case Intrinsic::aarch64_neon_sminv:
7965 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7966 case Intrinsic::aarch64_neon_uminv:
7967 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7968 case Intrinsic::aarch64_neon_smaxv:
7969 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7970 case Intrinsic::aarch64_neon_umaxv:
7971 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7972 case Intrinsic::aarch64_neon_fmax:
7973 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7974 N->getOperand(1), N->getOperand(2));
7975 case Intrinsic::aarch64_neon_fmin:
7976 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7977 N->getOperand(1), N->getOperand(2));
7978 case Intrinsic::aarch64_neon_smull:
7979 case Intrinsic::aarch64_neon_umull:
7980 case Intrinsic::aarch64_neon_pmull:
7981 case Intrinsic::aarch64_neon_sqdmull:
7982 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7983 case Intrinsic::aarch64_neon_sqshl:
7984 case Intrinsic::aarch64_neon_uqshl:
7985 case Intrinsic::aarch64_neon_sqshlu:
7986 case Intrinsic::aarch64_neon_srshl:
7987 case Intrinsic::aarch64_neon_urshl:
7988 return tryCombineShiftImm(IID, N, DAG);
7989 case Intrinsic::aarch64_crc32b:
7990 case Intrinsic::aarch64_crc32cb:
7991 return tryCombineCRC32(0xff, N, DAG);
7992 case Intrinsic::aarch64_crc32h:
7993 case Intrinsic::aarch64_crc32ch:
7994 return tryCombineCRC32(0xffff, N, DAG);
7999 static SDValue performExtendCombine(SDNode *N,
8000 TargetLowering::DAGCombinerInfo &DCI,
8001 SelectionDAG &DAG) {
8002 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8003 // we can convert that DUP into another extract_high (of a bigger DUP), which
8004 // helps the backend to decide that an sabdl2 would be useful, saving a real
8005 // extract_high operation.
8006 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8007 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
8008 SDNode *ABDNode = N->getOperand(0).getNode();
8009 unsigned IID = getIntrinsicID(ABDNode);
8010 if (IID == Intrinsic::aarch64_neon_sabd ||
8011 IID == Intrinsic::aarch64_neon_uabd) {
8012 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
8013 if (!NewABD.getNode())
8016 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8021 // This is effectively a custom type legalization for AArch64.
8023 // Type legalization will split an extend of a small, legal, type to a larger
8024 // illegal type by first splitting the destination type, often creating
8025 // illegal source types, which then get legalized in isel-confusing ways,
8026 // leading to really terrible codegen. E.g.,
8027 // %result = v8i32 sext v8i8 %value
8029 // %losrc = extract_subreg %value, ...
8030 // %hisrc = extract_subreg %value, ...
8031 // %lo = v4i32 sext v4i8 %losrc
8032 // %hi = v4i32 sext v4i8 %hisrc
8033 // Things go rapidly downhill from there.
8035 // For AArch64, the [sz]ext vector instructions can only go up one element
8036 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8037 // take two instructions.
8039 // This implies that the most efficient way to do the extend from v8i8
8040 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8041 // the normal splitting to happen for the v8i16->v8i32.
8043 // This is pre-legalization to catch some cases where the default
8044 // type legalization will create ill-tempered code.
8045 if (!DCI.isBeforeLegalizeOps())
8048 // We're only interested in cleaning things up for non-legal vector types
8049 // here. If both the source and destination are legal, things will just
8050 // work naturally without any fiddling.
8051 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8052 EVT ResVT = N->getValueType(0);
8053 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8055 // If the vector type isn't a simple VT, it's beyond the scope of what
8056 // we're worried about here. Let legalization do its thing and hope for
8058 SDValue Src = N->getOperand(0);
8059 EVT SrcVT = Src->getValueType(0);
8060 if (!ResVT.isSimple() || !SrcVT.isSimple())
8063 // If the source VT is a 64-bit vector, we can play games and get the
8064 // better results we want.
8065 if (SrcVT.getSizeInBits() != 64)
8068 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8069 unsigned ElementCount = SrcVT.getVectorNumElements();
8070 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8072 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8074 // Now split the rest of the operation into two halves, each with a 64
8078 unsigned NumElements = ResVT.getVectorNumElements();
8079 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8080 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8081 ResVT.getVectorElementType(), NumElements / 2);
8083 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8084 LoVT.getVectorNumElements());
8085 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8086 DAG.getConstant(0, DL, MVT::i64));
8087 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8088 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8089 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8090 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8092 // Now combine the parts back together so we still have a single result
8093 // like the combiner expects.
8094 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8097 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8098 /// value. The load store optimizer pass will merge them to store pair stores.
8099 /// This has better performance than a splat of the scalar followed by a split
8100 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8101 /// followed by an ext.b and two stores.
8102 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8103 SDValue StVal = St->getValue();
8104 EVT VT = StVal.getValueType();
8106 // Don't replace floating point stores, they possibly won't be transformed to
8107 // stp because of the store pair suppress pass.
8108 if (VT.isFloatingPoint())
8111 // Check for insert vector elements.
8112 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8115 // We can express a splat as store pair(s) for 2 or 4 elements.
8116 unsigned NumVecElts = VT.getVectorNumElements();
8117 if (NumVecElts != 4 && NumVecElts != 2)
8119 SDValue SplatVal = StVal.getOperand(1);
8120 unsigned RemainInsertElts = NumVecElts - 1;
8122 // Check that this is a splat.
8123 while (--RemainInsertElts) {
8124 SDValue NextInsertElt = StVal.getOperand(0);
8125 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8127 if (NextInsertElt.getOperand(1) != SplatVal)
8129 StVal = NextInsertElt;
8131 unsigned OrigAlignment = St->getAlignment();
8132 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8133 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8135 // Create scalar stores. This is at least as good as the code sequence for a
8136 // split unaligned store wich is a dup.s, ext.b, and two stores.
8137 // Most of the time the three stores should be replaced by store pair
8138 // instructions (stp).
8140 SDValue BasePtr = St->getBasePtr();
8142 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8143 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8145 unsigned Offset = EltOffset;
8146 while (--NumVecElts) {
8147 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8148 DAG.getConstant(Offset, DL, MVT::i64));
8149 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8150 St->getPointerInfo(), St->isVolatile(),
8151 St->isNonTemporal(), Alignment);
8152 Offset += EltOffset;
8157 static SDValue performSTORECombine(SDNode *N,
8158 TargetLowering::DAGCombinerInfo &DCI,
8160 const AArch64Subtarget *Subtarget) {
8161 if (!DCI.isBeforeLegalize())
8164 StoreSDNode *S = cast<StoreSDNode>(N);
8165 if (S->isVolatile())
8168 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8169 // page boundaries. We want to split such stores.
8170 if (!Subtarget->isCyclone())
8173 // Don't split at Oz.
8174 MachineFunction &MF = DAG.getMachineFunction();
8175 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8179 SDValue StVal = S->getValue();
8180 EVT VT = StVal.getValueType();
8182 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8183 // those up regresses performance on micro-benchmarks and olden/bh.
8184 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8187 // Split unaligned 16B stores. They are terrible for performance.
8188 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8189 // extensions can use this to mark that it does not want splitting to happen
8190 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8191 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8192 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8193 S->getAlignment() <= 2)
8196 // If we get a splat of a scalar convert this vector store to a store of
8197 // scalars. They will be merged into store pairs thereby removing two
8199 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8200 if (ReplacedSplat != SDValue())
8201 return ReplacedSplat;
8204 unsigned NumElts = VT.getVectorNumElements() / 2;
8205 // Split VT into two.
8207 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8208 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8209 DAG.getConstant(0, DL, MVT::i64));
8210 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8211 DAG.getConstant(NumElts, DL, MVT::i64));
8212 SDValue BasePtr = S->getBasePtr();
8214 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8215 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8216 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8217 DAG.getConstant(8, DL, MVT::i64));
8218 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8219 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8223 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8224 /// post-increment LD1R.
8225 static SDValue performPostLD1Combine(SDNode *N,
8226 TargetLowering::DAGCombinerInfo &DCI,
8228 if (DCI.isBeforeLegalizeOps())
8231 SelectionDAG &DAG = DCI.DAG;
8232 EVT VT = N->getValueType(0);
8234 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8235 SDNode *LD = N->getOperand(LoadIdx).getNode();
8236 // If it is not LOAD, can not do such combine.
8237 if (LD->getOpcode() != ISD::LOAD)
8240 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8241 EVT MemVT = LoadSDN->getMemoryVT();
8242 // Check if memory operand is the same type as the vector element.
8243 if (MemVT != VT.getVectorElementType())
8246 // Check if there are other uses. If so, do not combine as it will introduce
8248 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8250 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8256 SDValue Addr = LD->getOperand(1);
8257 SDValue Vector = N->getOperand(0);
8258 // Search for a use of the address operand that is an increment.
8259 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8260 Addr.getNode()->use_end(); UI != UE; ++UI) {
8262 if (User->getOpcode() != ISD::ADD
8263 || UI.getUse().getResNo() != Addr.getResNo())
8266 // Check that the add is independent of the load. Otherwise, folding it
8267 // would create a cycle.
8268 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8270 // Also check that add is not used in the vector operand. This would also
8272 if (User->isPredecessorOf(Vector.getNode()))
8275 // If the increment is a constant, it must match the memory ref size.
8276 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8277 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8278 uint32_t IncVal = CInc->getZExtValue();
8279 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8280 if (IncVal != NumBytes)
8282 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8285 // Finally, check that the vector doesn't depend on the load.
8286 // Again, this would create a cycle.
8287 // The load depending on the vector is fine, as that's the case for the
8288 // LD1*post we'll eventually generate anyway.
8289 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8292 SmallVector<SDValue, 8> Ops;
8293 Ops.push_back(LD->getOperand(0)); // Chain
8295 Ops.push_back(Vector); // The vector to be inserted
8296 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8298 Ops.push_back(Addr);
8301 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8302 SDVTList SDTys = DAG.getVTList(Tys);
8303 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8304 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8306 LoadSDN->getMemOperand());
8309 SmallVector<SDValue, 2> NewResults;
8310 NewResults.push_back(SDValue(LD, 0)); // The result of load
8311 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8312 DCI.CombineTo(LD, NewResults);
8313 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8314 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8321 /// Target-specific DAG combine function for NEON load/store intrinsics
8322 /// to merge base address updates.
8323 static SDValue performNEONPostLDSTCombine(SDNode *N,
8324 TargetLowering::DAGCombinerInfo &DCI,
8325 SelectionDAG &DAG) {
8326 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8329 unsigned AddrOpIdx = N->getNumOperands() - 1;
8330 SDValue Addr = N->getOperand(AddrOpIdx);
8332 // Search for a use of the address operand that is an increment.
8333 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8334 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8336 if (User->getOpcode() != ISD::ADD ||
8337 UI.getUse().getResNo() != Addr.getResNo())
8340 // Check that the add is independent of the load/store. Otherwise, folding
8341 // it would create a cycle.
8342 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8345 // Find the new opcode for the updating load/store.
8346 bool IsStore = false;
8347 bool IsLaneOp = false;
8348 bool IsDupOp = false;
8349 unsigned NewOpc = 0;
8350 unsigned NumVecs = 0;
8351 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8353 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8354 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8356 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8358 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8360 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8361 NumVecs = 2; IsStore = true; break;
8362 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8363 NumVecs = 3; IsStore = true; break;
8364 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8365 NumVecs = 4; IsStore = true; break;
8366 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8368 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8370 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8372 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8373 NumVecs = 2; IsStore = true; break;
8374 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8375 NumVecs = 3; IsStore = true; break;
8376 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8377 NumVecs = 4; IsStore = true; break;
8378 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8379 NumVecs = 2; IsDupOp = true; break;
8380 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8381 NumVecs = 3; IsDupOp = true; break;
8382 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8383 NumVecs = 4; IsDupOp = true; break;
8384 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8385 NumVecs = 2; IsLaneOp = true; break;
8386 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8387 NumVecs = 3; IsLaneOp = true; break;
8388 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8389 NumVecs = 4; IsLaneOp = true; break;
8390 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8391 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8392 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8393 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8394 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8395 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8400 VecTy = N->getOperand(2).getValueType();
8402 VecTy = N->getValueType(0);
8404 // If the increment is a constant, it must match the memory ref size.
8405 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8406 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8407 uint32_t IncVal = CInc->getZExtValue();
8408 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8409 if (IsLaneOp || IsDupOp)
8410 NumBytes /= VecTy.getVectorNumElements();
8411 if (IncVal != NumBytes)
8413 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8415 SmallVector<SDValue, 8> Ops;
8416 Ops.push_back(N->getOperand(0)); // Incoming chain
8417 // Load lane and store have vector list as input.
8418 if (IsLaneOp || IsStore)
8419 for (unsigned i = 2; i < AddrOpIdx; ++i)
8420 Ops.push_back(N->getOperand(i));
8421 Ops.push_back(Addr); // Base register
8426 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8428 for (n = 0; n < NumResultVecs; ++n)
8430 Tys[n++] = MVT::i64; // Type of write back register
8431 Tys[n] = MVT::Other; // Type of the chain
8432 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8434 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8435 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8436 MemInt->getMemoryVT(),
8437 MemInt->getMemOperand());
8440 std::vector<SDValue> NewResults;
8441 for (unsigned i = 0; i < NumResultVecs; ++i) {
8442 NewResults.push_back(SDValue(UpdN.getNode(), i));
8444 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8445 DCI.CombineTo(N, NewResults);
8446 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8453 // Checks to see if the value is the prescribed width and returns information
8454 // about its extension mode.
8456 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8457 ExtType = ISD::NON_EXTLOAD;
8458 switch(V.getNode()->getOpcode()) {
8462 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8463 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8464 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8465 ExtType = LoadNode->getExtensionType();
8470 case ISD::AssertSext: {
8471 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8472 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8473 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8474 ExtType = ISD::SEXTLOAD;
8479 case ISD::AssertZext: {
8480 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8481 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8482 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8483 ExtType = ISD::ZEXTLOAD;
8489 case ISD::TargetConstant: {
8490 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8500 // This function does a whole lot of voodoo to determine if the tests are
8501 // equivalent without and with a mask. Essentially what happens is that given a
8504 // +-------------+ +-------------+ +-------------+ +-------------+
8505 // | Input | | AddConstant | | CompConstant| | CC |
8506 // +-------------+ +-------------+ +-------------+ +-------------+
8508 // V V | +----------+
8509 // +-------------+ +----+ | |
8510 // | ADD | |0xff| | |
8511 // +-------------+ +----+ | |
8514 // +-------------+ | |
8516 // +-------------+ | |
8525 // The AND node may be safely removed for some combinations of inputs. In
8526 // particular we need to take into account the extension type of the Input,
8527 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8528 // width of the input (this can work for any width inputs, the above graph is
8529 // specific to 8 bits.
8531 // The specific equations were worked out by generating output tables for each
8532 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8533 // problem was simplified by working with 4 bit inputs, which means we only
8534 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8535 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8536 // patterns present in both extensions (0,7). For every distinct set of
8537 // AddConstant and CompConstants bit patterns we can consider the masked and
8538 // unmasked versions to be equivalent if the result of this function is true for
8539 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8542 // and w10, w8, #0x0f
8544 // cset w9, AArch64CC
8546 // cset w11, AArch64CC
8551 // Since the above function shows when the outputs are equivalent it defines
8552 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8553 // would be expensive to run during compiles. The equations below were written
8554 // in a test harness that confirmed they gave equivalent outputs to the above
8555 // for all inputs function, so they can be used determine if the removal is
8558 // isEquivalentMaskless() is the code for testing if the AND can be removed
8559 // factored out of the DAG recognition as the DAG can take several forms.
8562 bool isEquivalentMaskless(unsigned CC, unsigned width,
8563 ISD::LoadExtType ExtType, signed AddConstant,
8564 signed CompConstant) {
8565 // By being careful about our equations and only writing the in term
8566 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8567 // make them generally applicable to all bit widths.
8568 signed MaxUInt = (1 << width);
8570 // For the purposes of these comparisons sign extending the type is
8571 // equivalent to zero extending the add and displacing it by half the integer
8572 // width. Provided we are careful and make sure our equations are valid over
8573 // the whole range we can just adjust the input and avoid writing equations
8574 // for sign extended inputs.
8575 if (ExtType == ISD::SEXTLOAD)
8576 AddConstant -= (1 << (width-1));
8580 case AArch64CC::GT: {
8581 if ((AddConstant == 0) ||
8582 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8583 (AddConstant >= 0 && CompConstant < 0) ||
8584 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8588 case AArch64CC::GE: {
8589 if ((AddConstant == 0) ||
8590 (AddConstant >= 0 && CompConstant <= 0) ||
8591 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8595 case AArch64CC::LS: {
8596 if ((AddConstant >= 0 && CompConstant < 0) ||
8597 (AddConstant <= 0 && CompConstant >= -1 &&
8598 CompConstant < AddConstant + MaxUInt))
8602 case AArch64CC::MI: {
8603 if ((AddConstant == 0) ||
8604 (AddConstant > 0 && CompConstant <= 0) ||
8605 (AddConstant < 0 && CompConstant <= AddConstant))
8609 case AArch64CC::HS: {
8610 if ((AddConstant >= 0 && CompConstant <= 0) ||
8611 (AddConstant <= 0 && CompConstant >= 0 &&
8612 CompConstant <= AddConstant + MaxUInt))
8616 case AArch64CC::NE: {
8617 if ((AddConstant > 0 && CompConstant < 0) ||
8618 (AddConstant < 0 && CompConstant >= 0 &&
8619 CompConstant < AddConstant + MaxUInt) ||
8620 (AddConstant >= 0 && CompConstant >= 0 &&
8621 CompConstant >= AddConstant) ||
8622 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8631 case AArch64CC::Invalid:
8639 SDValue performCONDCombine(SDNode *N,
8640 TargetLowering::DAGCombinerInfo &DCI,
8641 SelectionDAG &DAG, unsigned CCIndex,
8642 unsigned CmpIndex) {
8643 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8644 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8645 unsigned CondOpcode = SubsNode->getOpcode();
8647 if (CondOpcode != AArch64ISD::SUBS)
8650 // There is a SUBS feeding this condition. Is it fed by a mask we can
8653 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8654 unsigned MaskBits = 0;
8656 if (AndNode->getOpcode() != ISD::AND)
8659 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8660 uint32_t CNV = CN->getZExtValue();
8663 else if (CNV == 65535)
8670 SDValue AddValue = AndNode->getOperand(0);
8672 if (AddValue.getOpcode() != ISD::ADD)
8675 // The basic dag structure is correct, grab the inputs and validate them.
8677 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8678 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8679 SDValue SubsInputValue = SubsNode->getOperand(1);
8681 // The mask is present and the provenance of all the values is a smaller type,
8682 // lets see if the mask is superfluous.
8684 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8685 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8688 ISD::LoadExtType ExtType;
8690 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8691 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8692 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8695 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8696 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8697 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8700 // The AND is not necessary, remove it.
8702 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8703 SubsNode->getValueType(1));
8704 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8706 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8707 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8709 return SDValue(N, 0);
8712 // Optimize compare with zero and branch.
8713 static SDValue performBRCONDCombine(SDNode *N,
8714 TargetLowering::DAGCombinerInfo &DCI,
8715 SelectionDAG &DAG) {
8716 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8719 SDValue Chain = N->getOperand(0);
8720 SDValue Dest = N->getOperand(1);
8721 SDValue CCVal = N->getOperand(2);
8722 SDValue Cmp = N->getOperand(3);
8724 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8725 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8726 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8729 unsigned CmpOpc = Cmp.getOpcode();
8730 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8733 // Only attempt folding if there is only one use of the flag and no use of the
8735 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8738 SDValue LHS = Cmp.getOperand(0);
8739 SDValue RHS = Cmp.getOperand(1);
8741 assert(LHS.getValueType() == RHS.getValueType() &&
8742 "Expected the value type to be the same for both operands!");
8743 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8746 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8747 std::swap(LHS, RHS);
8749 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8752 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8753 LHS.getOpcode() == ISD::SRL)
8756 // Fold the compare into the branch instruction.
8758 if (CC == AArch64CC::EQ)
8759 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8761 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8763 // Do not add new nodes to DAG combiner worklist.
8764 DCI.CombineTo(N, BR, false);
8769 // vselect (v1i1 setcc) ->
8770 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8771 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8772 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8774 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8775 SDValue N0 = N->getOperand(0);
8776 EVT CCVT = N0.getValueType();
8778 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8779 CCVT.getVectorElementType() != MVT::i1)
8782 EVT ResVT = N->getValueType(0);
8783 EVT CmpVT = N0.getOperand(0).getValueType();
8784 // Only combine when the result type is of the same size as the compared
8786 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8789 SDValue IfTrue = N->getOperand(1);
8790 SDValue IfFalse = N->getOperand(2);
8792 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8793 N0.getOperand(0), N0.getOperand(1),
8794 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8795 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8799 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8800 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8801 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8802 /// with a vector one followed by a DUP shuffle on the result.
8803 static SDValue performSelectCombine(SDNode *N,
8804 TargetLowering::DAGCombinerInfo &DCI) {
8805 SelectionDAG &DAG = DCI.DAG;
8806 SDValue N0 = N->getOperand(0);
8807 EVT ResVT = N->getValueType(0);
8809 if (N0.getOpcode() != ISD::SETCC)
8812 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
8813 // scalar SetCCResultType. We also don't expect vectors, because we assume
8814 // that selects fed by vector SETCCs are canonicalized to VSELECT.
8815 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
8816 "Scalar-SETCC feeding SELECT has unexpected result type!");
8818 // If NumMaskElts == 0, the comparison is larger than select result. The
8819 // largest real NEON comparison is 64-bits per lane, which means the result is
8820 // at most 32-bits and an illegal vector. Just bail out for now.
8821 EVT SrcVT = N0.getOperand(0).getValueType();
8823 // Don't try to do this optimization when the setcc itself has i1 operands.
8824 // There are no legal vectors of i1, so this would be pointless.
8825 if (SrcVT == MVT::i1)
8828 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8829 if (!ResVT.isVector() || NumMaskElts == 0)
8832 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8833 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8835 // Also bail out if the vector CCVT isn't the same size as ResVT.
8836 // This can happen if the SETCC operand size doesn't divide the ResVT size
8837 // (e.g., f64 vs v3f32).
8838 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
8841 // Make sure we didn't create illegal types, if we're not supposed to.
8842 assert(DCI.isBeforeLegalize() ||
8843 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
8845 // First perform a vector comparison, where lane 0 is the one we're interested
8849 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8851 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8852 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8854 // Now duplicate the comparison mask we want across all other lanes.
8855 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8856 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8857 Mask = DAG.getNode(ISD::BITCAST, DL,
8858 ResVT.changeVectorElementTypeToInteger(), Mask);
8860 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8863 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
8864 /// to match FMIN/FMAX patterns.
8865 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
8866 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
8867 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
8868 // vmax/vmin return NaN if either operand is a NaN;
8869 // only do the transformation when it matches that behavior.
8871 SDValue CondLHS = N->getOperand(0);
8872 SDValue CondRHS = N->getOperand(1);
8873 SDValue LHS = N->getOperand(2);
8874 SDValue RHS = N->getOperand(3);
8875 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
8879 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
8880 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
8881 IsReversed = false; // x CC y ? x : y
8882 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
8883 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
8884 IsReversed = true ; // x CC y ? y : x
8889 bool IsUnordered = false, IsOrEqual;
8900 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
8901 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
8911 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
8912 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
8916 // If LHS is NaN, an ordered comparison will be false and the result will be
8917 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
8918 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
8919 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8922 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
8923 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
8924 // used for unsafe math or if one of the operands is known to be nonzero.
8925 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
8926 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8929 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
8932 /// Get rid of unnecessary NVCASTs (that don't change the type).
8933 static SDValue performNVCASTCombine(SDNode *N) {
8934 if (N->getValueType(0) == N->getOperand(0).getValueType())
8935 return N->getOperand(0);
8940 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8941 DAGCombinerInfo &DCI) const {
8942 SelectionDAG &DAG = DCI.DAG;
8943 switch (N->getOpcode()) {
8948 return performAddSubLongCombine(N, DCI, DAG);
8950 return performXorCombine(N, DAG, DCI, Subtarget);
8952 return performMulCombine(N, DAG, DCI, Subtarget);
8953 case ISD::SINT_TO_FP:
8954 case ISD::UINT_TO_FP:
8955 return performIntToFpCombine(N, DAG, Subtarget);
8957 return performORCombine(N, DCI, Subtarget);
8958 case ISD::INTRINSIC_WO_CHAIN:
8959 return performIntrinsicCombine(N, DCI, Subtarget);
8960 case ISD::ANY_EXTEND:
8961 case ISD::ZERO_EXTEND:
8962 case ISD::SIGN_EXTEND:
8963 return performExtendCombine(N, DCI, DAG);
8965 return performBitcastCombine(N, DCI, DAG);
8966 case ISD::CONCAT_VECTORS:
8967 return performConcatVectorsCombine(N, DCI, DAG);
8969 return performSelectCombine(N, DCI);
8971 return performVSelectCombine(N, DCI.DAG);
8972 case ISD::SELECT_CC:
8973 return performSelectCCCombine(N, DCI.DAG);
8975 return performSTORECombine(N, DCI, DAG, Subtarget);
8976 case AArch64ISD::BRCOND:
8977 return performBRCONDCombine(N, DCI, DAG);
8978 case AArch64ISD::CSEL:
8979 return performCONDCombine(N, DCI, DAG, 2, 3);
8980 case AArch64ISD::DUP:
8981 return performPostLD1Combine(N, DCI, false);
8982 case AArch64ISD::NVCAST:
8983 return performNVCASTCombine(N);
8984 case ISD::INSERT_VECTOR_ELT:
8985 return performPostLD1Combine(N, DCI, true);
8986 case ISD::INTRINSIC_VOID:
8987 case ISD::INTRINSIC_W_CHAIN:
8988 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8989 case Intrinsic::aarch64_neon_ld2:
8990 case Intrinsic::aarch64_neon_ld3:
8991 case Intrinsic::aarch64_neon_ld4:
8992 case Intrinsic::aarch64_neon_ld1x2:
8993 case Intrinsic::aarch64_neon_ld1x3:
8994 case Intrinsic::aarch64_neon_ld1x4:
8995 case Intrinsic::aarch64_neon_ld2lane:
8996 case Intrinsic::aarch64_neon_ld3lane:
8997 case Intrinsic::aarch64_neon_ld4lane:
8998 case Intrinsic::aarch64_neon_ld2r:
8999 case Intrinsic::aarch64_neon_ld3r:
9000 case Intrinsic::aarch64_neon_ld4r:
9001 case Intrinsic::aarch64_neon_st2:
9002 case Intrinsic::aarch64_neon_st3:
9003 case Intrinsic::aarch64_neon_st4:
9004 case Intrinsic::aarch64_neon_st1x2:
9005 case Intrinsic::aarch64_neon_st1x3:
9006 case Intrinsic::aarch64_neon_st1x4:
9007 case Intrinsic::aarch64_neon_st2lane:
9008 case Intrinsic::aarch64_neon_st3lane:
9009 case Intrinsic::aarch64_neon_st4lane:
9010 return performNEONPostLDSTCombine(N, DCI, DAG);
9018 // Check if the return value is used as only a return value, as otherwise
9019 // we can't perform a tail-call. In particular, we need to check for
9020 // target ISD nodes that are returns and any other "odd" constructs
9021 // that the generic analysis code won't necessarily catch.
9022 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9023 SDValue &Chain) const {
9024 if (N->getNumValues() != 1)
9026 if (!N->hasNUsesOfValue(1, 0))
9029 SDValue TCChain = Chain;
9030 SDNode *Copy = *N->use_begin();
9031 if (Copy->getOpcode() == ISD::CopyToReg) {
9032 // If the copy has a glue operand, we conservatively assume it isn't safe to
9033 // perform a tail call.
9034 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9037 TCChain = Copy->getOperand(0);
9038 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9041 bool HasRet = false;
9042 for (SDNode *Node : Copy->uses()) {
9043 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9055 // Return whether the an instruction can potentially be optimized to a tail
9056 // call. This will cause the optimizers to attempt to move, or duplicate,
9057 // return instructions to help enable tail call optimizations for this
9059 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9060 if (!CI->isTailCall())
9066 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9068 ISD::MemIndexedMode &AM,
9070 SelectionDAG &DAG) const {
9071 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9074 Base = Op->getOperand(0);
9075 // All of the indexed addressing mode instructions take a signed
9076 // 9 bit immediate offset.
9077 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9078 int64_t RHSC = (int64_t)RHS->getZExtValue();
9079 if (RHSC >= 256 || RHSC <= -256)
9081 IsInc = (Op->getOpcode() == ISD::ADD);
9082 Offset = Op->getOperand(1);
9088 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9090 ISD::MemIndexedMode &AM,
9091 SelectionDAG &DAG) const {
9094 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9095 VT = LD->getMemoryVT();
9096 Ptr = LD->getBasePtr();
9097 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9098 VT = ST->getMemoryVT();
9099 Ptr = ST->getBasePtr();
9104 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9106 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9110 bool AArch64TargetLowering::getPostIndexedAddressParts(
9111 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9112 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9115 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9116 VT = LD->getMemoryVT();
9117 Ptr = LD->getBasePtr();
9118 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9119 VT = ST->getMemoryVT();
9120 Ptr = ST->getBasePtr();
9125 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9127 // Post-indexing updates the base, so it's not a valid transform
9128 // if that's not the same as the load's pointer.
9131 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9135 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9136 SelectionDAG &DAG) {
9138 SDValue Op = N->getOperand(0);
9140 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9144 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9145 DAG.getUNDEF(MVT::i32), Op,
9146 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9148 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9149 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9152 void AArch64TargetLowering::ReplaceNodeResults(
9153 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9154 switch (N->getOpcode()) {
9156 llvm_unreachable("Don't know how to custom expand this");
9158 ReplaceBITCASTResults(N, Results, DAG);
9160 case ISD::FP_TO_UINT:
9161 case ISD::FP_TO_SINT:
9162 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9163 // Let normal code take care of it by not adding anything to Results.
9168 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9172 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9173 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9174 // reciprocal if there are three or more FDIVs.
9175 return NumUsers > 2;
9178 TargetLoweringBase::LegalizeTypeAction
9179 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9180 MVT SVT = VT.getSimpleVT();
9181 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9182 // v4i16, v2i32 instead of to promote.
9183 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9184 || SVT == MVT::v1f32)
9185 return TypeWidenVector;
9187 return TargetLoweringBase::getPreferredVectorAction(VT);
9190 // Loads and stores less than 128-bits are already atomic; ones above that
9191 // are doomed anyway, so defer to the default libcall and blame the OS when
9193 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9194 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9198 // Loads and stores less than 128-bits are already atomic; ones above that
9199 // are doomed anyway, so defer to the default libcall and blame the OS when
9201 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9202 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9206 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9207 TargetLoweringBase::AtomicRMWExpansionKind
9208 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9209 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9210 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9211 : AtomicRMWExpansionKind::None;
9214 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9218 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9219 AtomicOrdering Ord) const {
9220 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9221 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9222 bool IsAcquire = isAtLeastAcquire(Ord);
9224 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9225 // intrinsic must return {i64, i64} and we have to recombine them into a
9226 // single i128 here.
9227 if (ValTy->getPrimitiveSizeInBits() == 128) {
9229 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9230 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9232 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9233 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9235 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9236 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9237 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9238 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9239 return Builder.CreateOr(
9240 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9243 Type *Tys[] = { Addr->getType() };
9245 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9246 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9248 return Builder.CreateTruncOrBitCast(
9249 Builder.CreateCall(Ldxr, Addr),
9250 cast<PointerType>(Addr->getType())->getElementType());
9253 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9254 Value *Val, Value *Addr,
9255 AtomicOrdering Ord) const {
9256 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9257 bool IsRelease = isAtLeastRelease(Ord);
9259 // Since the intrinsics must have legal type, the i128 intrinsics take two
9260 // parameters: "i64, i64". We must marshal Val into the appropriate form
9262 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9264 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9265 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9266 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9268 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9269 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9270 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9271 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9275 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9276 Type *Tys[] = { Addr->getType() };
9277 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9279 return Builder.CreateCall(Stxr,
9280 {Builder.CreateZExtOrBitCast(
9281 Val, Stxr->getFunctionType()->getParamType(0)),
9285 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9286 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9287 return Ty->isArrayTy();