1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
43 // Place holder until extr generation is tested fully.
45 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
46 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
50 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
51 cl::desc("Allow AArch64 SLI/SRI formation"),
54 // FIXME: The necessary dtprel relocations don't seem to be supported
55 // well in the GNU bfd and gold linkers at the moment. Therefore, by
56 // default, for now, fall back to GeneralDynamic code generation.
57 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
58 "aarch64-elf-ldtls-generation", cl::Hidden,
59 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
62 /// Value type used for condition codes.
63 static const MVT MVT_CC = MVT::i32;
65 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
66 const AArch64Subtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
70 // we have to make something up. Arbitrarily, choose ZeroOrOne.
71 setBooleanContents(ZeroOrOneBooleanContent);
72 // When comparing vectors the result sets the different elements in the
73 // vector to all-one or all-zero.
74 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
78 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
80 if (Subtarget->hasFPARMv8()) {
81 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
82 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
83 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
84 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
87 if (Subtarget->hasNEON()) {
88 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
89 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
90 // Someone set us up the NEON.
91 addDRTypeForNEON(MVT::v2f32);
92 addDRTypeForNEON(MVT::v8i8);
93 addDRTypeForNEON(MVT::v4i16);
94 addDRTypeForNEON(MVT::v2i32);
95 addDRTypeForNEON(MVT::v1i64);
96 addDRTypeForNEON(MVT::v1f64);
97 addDRTypeForNEON(MVT::v4f16);
99 addQRTypeForNEON(MVT::v4f32);
100 addQRTypeForNEON(MVT::v2f64);
101 addQRTypeForNEON(MVT::v16i8);
102 addQRTypeForNEON(MVT::v8i16);
103 addQRTypeForNEON(MVT::v4i32);
104 addQRTypeForNEON(MVT::v2i64);
105 addQRTypeForNEON(MVT::v8f16);
108 // Compute derived properties from the register classes
109 computeRegisterProperties(Subtarget->getRegisterInfo());
111 // Provide all sorts of operation actions
112 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
120 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
121 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
122 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
123 setOperationAction(ISD::SELECT, MVT::i32, Custom);
124 setOperationAction(ISD::SELECT, MVT::i64, Custom);
125 setOperationAction(ISD::SELECT, MVT::f32, Custom);
126 setOperationAction(ISD::SELECT, MVT::f64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
131 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
135 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
136 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Expand);
139 setOperationAction(ISD::FREM, MVT::f64, Expand);
140 setOperationAction(ISD::FREM, MVT::f80, Expand);
142 // Custom lowering hooks are needed for XOR
143 // to fold it into CSINC/CSINV.
144 setOperationAction(ISD::XOR, MVT::i32, Custom);
145 setOperationAction(ISD::XOR, MVT::i64, Custom);
147 // Virtually no operation on f128 is legal, but LLVM can't expand them when
148 // there's a valid register class, so we need custom operations in most cases.
149 setOperationAction(ISD::FABS, MVT::f128, Expand);
150 setOperationAction(ISD::FADD, MVT::f128, Custom);
151 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
152 setOperationAction(ISD::FCOS, MVT::f128, Expand);
153 setOperationAction(ISD::FDIV, MVT::f128, Custom);
154 setOperationAction(ISD::FMA, MVT::f128, Expand);
155 setOperationAction(ISD::FMUL, MVT::f128, Custom);
156 setOperationAction(ISD::FNEG, MVT::f128, Expand);
157 setOperationAction(ISD::FPOW, MVT::f128, Expand);
158 setOperationAction(ISD::FREM, MVT::f128, Expand);
159 setOperationAction(ISD::FRINT, MVT::f128, Expand);
160 setOperationAction(ISD::FSIN, MVT::f128, Expand);
161 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
162 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
163 setOperationAction(ISD::FSUB, MVT::f128, Custom);
164 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
166 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
167 setOperationAction(ISD::SELECT, MVT::f128, Custom);
168 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
169 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
171 // Lowering for many of the conversions is actually specified by the non-f128
172 // type. The LowerXXX function will be trivial when f128 isn't involved.
173 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
177 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
178 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
182 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
183 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
184 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
186 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
188 // Variable arguments.
189 setOperationAction(ISD::VASTART, MVT::Other, Custom);
190 setOperationAction(ISD::VAARG, MVT::Other, Custom);
191 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
192 setOperationAction(ISD::VAEND, MVT::Other, Expand);
194 // Variable-sized objects.
195 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
196 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
197 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
199 // Exception handling.
200 // FIXME: These are guesses. Has this been defined yet?
201 setExceptionPointerRegister(AArch64::X0);
202 setExceptionSelectorRegister(AArch64::X1);
204 // Constant pool entries
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
208 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
210 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
211 setOperationAction(ISD::ADDC, MVT::i32, Custom);
212 setOperationAction(ISD::ADDE, MVT::i32, Custom);
213 setOperationAction(ISD::SUBC, MVT::i32, Custom);
214 setOperationAction(ISD::SUBE, MVT::i32, Custom);
215 setOperationAction(ISD::ADDC, MVT::i64, Custom);
216 setOperationAction(ISD::ADDE, MVT::i64, Custom);
217 setOperationAction(ISD::SUBC, MVT::i64, Custom);
218 setOperationAction(ISD::SUBE, MVT::i64, Custom);
220 // AArch64 lacks both left-rotate and popcount instructions.
221 setOperationAction(ISD::ROTL, MVT::i32, Expand);
222 setOperationAction(ISD::ROTL, MVT::i64, Expand);
224 // AArch64 doesn't have {U|S}MUL_LOHI.
225 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
226 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
229 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
230 // counterparts, which AArch64 supports directly.
231 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
232 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
233 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
234 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
236 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
237 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
239 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
240 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
241 setOperationAction(ISD::SREM, MVT::i32, Expand);
242 setOperationAction(ISD::SREM, MVT::i64, Expand);
243 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
244 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
245 setOperationAction(ISD::UREM, MVT::i32, Expand);
246 setOperationAction(ISD::UREM, MVT::i64, Expand);
248 // Custom lower Add/Sub/Mul with overflow.
249 setOperationAction(ISD::SADDO, MVT::i32, Custom);
250 setOperationAction(ISD::SADDO, MVT::i64, Custom);
251 setOperationAction(ISD::UADDO, MVT::i32, Custom);
252 setOperationAction(ISD::UADDO, MVT::i64, Custom);
253 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
254 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
255 setOperationAction(ISD::USUBO, MVT::i32, Custom);
256 setOperationAction(ISD::USUBO, MVT::i64, Custom);
257 setOperationAction(ISD::SMULO, MVT::i32, Custom);
258 setOperationAction(ISD::SMULO, MVT::i64, Custom);
259 setOperationAction(ISD::UMULO, MVT::i32, Custom);
260 setOperationAction(ISD::UMULO, MVT::i64, Custom);
262 setOperationAction(ISD::FSIN, MVT::f32, Expand);
263 setOperationAction(ISD::FSIN, MVT::f64, Expand);
264 setOperationAction(ISD::FCOS, MVT::f32, Expand);
265 setOperationAction(ISD::FCOS, MVT::f64, Expand);
266 setOperationAction(ISD::FPOW, MVT::f32, Expand);
267 setOperationAction(ISD::FPOW, MVT::f64, Expand);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
269 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
271 // f16 is a storage-only type, always promote it to f32.
272 setOperationAction(ISD::SETCC, MVT::f16, Promote);
273 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
274 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
275 setOperationAction(ISD::SELECT, MVT::f16, Promote);
276 setOperationAction(ISD::FADD, MVT::f16, Promote);
277 setOperationAction(ISD::FSUB, MVT::f16, Promote);
278 setOperationAction(ISD::FMUL, MVT::f16, Promote);
279 setOperationAction(ISD::FDIV, MVT::f16, Promote);
280 setOperationAction(ISD::FREM, MVT::f16, Promote);
281 setOperationAction(ISD::FMA, MVT::f16, Promote);
282 setOperationAction(ISD::FNEG, MVT::f16, Promote);
283 setOperationAction(ISD::FABS, MVT::f16, Promote);
284 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
285 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
286 setOperationAction(ISD::FCOS, MVT::f16, Promote);
287 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
288 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
289 setOperationAction(ISD::FPOW, MVT::f16, Promote);
290 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
291 setOperationAction(ISD::FRINT, MVT::f16, Promote);
292 setOperationAction(ISD::FSIN, MVT::f16, Promote);
293 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
294 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
295 setOperationAction(ISD::FEXP, MVT::f16, Promote);
296 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
297 setOperationAction(ISD::FLOG, MVT::f16, Promote);
298 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
299 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
300 setOperationAction(ISD::FROUND, MVT::f16, Promote);
301 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
302 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
303 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
305 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
307 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
308 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
309 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
310 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
311 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
312 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
313 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
314 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
315 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
316 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
317 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
318 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
320 // Expand all other v4f16 operations.
321 // FIXME: We could generate better code by promoting some operations to
323 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
324 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
325 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
328 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
329 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
330 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
331 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
332 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
333 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
334 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
335 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
336 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
337 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
338 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
339 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
340 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
341 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
342 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
343 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
344 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
345 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
346 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
347 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
348 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
351 // v8f16 is also a storage-only type, so expand it.
352 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
353 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
354 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
355 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
356 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
357 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
358 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
359 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
360 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
361 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
362 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
363 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
364 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
365 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
366 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
368 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
371 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
372 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
373 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
374 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
375 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
376 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
377 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
378 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
379 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
380 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
381 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
382 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
384 // AArch64 has implementations of a lot of rounding-like FP operations.
385 for (MVT Ty : {MVT::f32, MVT::f64}) {
386 setOperationAction(ISD::FFLOOR, Ty, Legal);
387 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
388 setOperationAction(ISD::FCEIL, Ty, Legal);
389 setOperationAction(ISD::FRINT, Ty, Legal);
390 setOperationAction(ISD::FTRUNC, Ty, Legal);
391 setOperationAction(ISD::FROUND, Ty, Legal);
394 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
396 if (Subtarget->isTargetMachO()) {
397 // For iOS, we don't want to the normal expansion of a libcall to
398 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
400 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
401 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
403 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
404 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
407 // Make floating-point constants legal for the large code model, so they don't
408 // become loads from the constant pool.
409 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
410 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
411 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
414 // AArch64 does not have floating-point extending loads, i1 sign-extending
415 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
416 for (MVT VT : MVT::fp_valuetypes()) {
417 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
418 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
419 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
420 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
422 for (MVT VT : MVT::integer_valuetypes())
423 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
425 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
426 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
427 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
428 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
429 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
430 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
431 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
433 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
434 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
436 // Indexed loads and stores are supported.
437 for (unsigned im = (unsigned)ISD::PRE_INC;
438 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
439 setIndexedLoadAction(im, MVT::i8, Legal);
440 setIndexedLoadAction(im, MVT::i16, Legal);
441 setIndexedLoadAction(im, MVT::i32, Legal);
442 setIndexedLoadAction(im, MVT::i64, Legal);
443 setIndexedLoadAction(im, MVT::f64, Legal);
444 setIndexedLoadAction(im, MVT::f32, Legal);
445 setIndexedLoadAction(im, MVT::f16, Legal);
446 setIndexedStoreAction(im, MVT::i8, Legal);
447 setIndexedStoreAction(im, MVT::i16, Legal);
448 setIndexedStoreAction(im, MVT::i32, Legal);
449 setIndexedStoreAction(im, MVT::i64, Legal);
450 setIndexedStoreAction(im, MVT::f64, Legal);
451 setIndexedStoreAction(im, MVT::f32, Legal);
452 setIndexedStoreAction(im, MVT::f16, Legal);
456 setOperationAction(ISD::TRAP, MVT::Other, Legal);
458 // We combine OR nodes for bitfield operations.
459 setTargetDAGCombine(ISD::OR);
461 // Vector add and sub nodes may conceal a high-half opportunity.
462 // Also, try to fold ADD into CSINC/CSINV..
463 setTargetDAGCombine(ISD::ADD);
464 setTargetDAGCombine(ISD::SUB);
466 setTargetDAGCombine(ISD::XOR);
467 setTargetDAGCombine(ISD::SINT_TO_FP);
468 setTargetDAGCombine(ISD::UINT_TO_FP);
470 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
472 setTargetDAGCombine(ISD::ANY_EXTEND);
473 setTargetDAGCombine(ISD::ZERO_EXTEND);
474 setTargetDAGCombine(ISD::SIGN_EXTEND);
475 setTargetDAGCombine(ISD::BITCAST);
476 setTargetDAGCombine(ISD::CONCAT_VECTORS);
477 setTargetDAGCombine(ISD::STORE);
479 setTargetDAGCombine(ISD::MUL);
481 setTargetDAGCombine(ISD::SELECT);
482 setTargetDAGCombine(ISD::VSELECT);
483 setTargetDAGCombine(ISD::SELECT_CC);
485 setTargetDAGCombine(ISD::INTRINSIC_VOID);
486 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
487 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
489 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
490 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
491 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
493 setStackPointerRegisterToSaveRestore(AArch64::SP);
495 setSchedulingPreference(Sched::Hybrid);
498 MaskAndBranchFoldingIsLegal = true;
499 EnableExtLdPromotion = true;
501 setMinFunctionAlignment(2);
503 setHasExtractBitsInsn(true);
505 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
507 if (Subtarget->hasNEON()) {
508 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
509 // silliness like this:
510 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
511 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
512 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
513 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
514 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
515 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
516 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
517 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
518 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
519 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
520 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
521 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
522 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
523 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
524 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
525 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
526 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
527 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
528 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
529 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
530 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
531 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
532 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
533 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
534 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
536 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
537 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
538 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
539 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
540 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
542 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
544 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
545 // elements smaller than i32, so promote the input to i32 first.
546 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
547 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
548 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
549 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
550 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
551 // -> v8f16 conversions.
552 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
553 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
554 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
555 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
556 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
557 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
560 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
561 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
562 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
563 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
564 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
566 // AArch64 doesn't have MUL.2d:
567 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
568 // Custom handling for some quad-vector types to detect MULL.
569 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
570 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
571 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
573 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
574 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
575 // Likewise, narrowing and extending vector loads/stores aren't handled
577 for (MVT VT : MVT::vector_valuetypes()) {
578 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
580 setOperationAction(ISD::MULHS, VT, Expand);
581 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
582 setOperationAction(ISD::MULHU, VT, Expand);
583 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
585 setOperationAction(ISD::BSWAP, VT, Expand);
587 for (MVT InnerVT : MVT::vector_valuetypes()) {
588 setTruncStoreAction(VT, InnerVT, Expand);
589 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
590 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
591 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
595 // AArch64 has implementations of a lot of rounding-like FP operations.
596 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
597 setOperationAction(ISD::FFLOOR, Ty, Legal);
598 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
599 setOperationAction(ISD::FCEIL, Ty, Legal);
600 setOperationAction(ISD::FRINT, Ty, Legal);
601 setOperationAction(ISD::FTRUNC, Ty, Legal);
602 setOperationAction(ISD::FROUND, Ty, Legal);
606 // Prefer likely predicted branches to selects on out-of-order cores.
607 if (Subtarget->isCortexA57())
608 PredictableSelectIsExpensive = true;
611 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
612 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
613 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
614 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
616 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
617 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
618 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
619 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
620 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
622 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
623 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
626 // Mark vector float intrinsics as expand.
627 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
628 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
633 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
635 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
636 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
638 // But we do support custom-lowering for FCOPYSIGN.
639 setOperationAction(ISD::FCOPYSIGN, VT.getSimpleVT(), Custom);
642 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
643 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
644 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
646 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
647 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
648 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
649 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
650 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
651 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
652 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
653 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
655 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
656 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
657 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
658 for (MVT InnerVT : MVT::all_valuetypes())
659 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
661 // CNT supports only B element sizes.
662 if (VT != MVT::v8i8 && VT != MVT::v16i8)
663 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
665 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
666 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
667 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
668 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
669 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
671 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
672 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
674 // [SU][MIN|MAX] and [SU]ABSDIFF are available for all NEON types apart from
676 if (!VT.isFloatingPoint() &&
677 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
678 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
679 ISD::SABSDIFF, ISD::UABSDIFF})
680 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
682 if (Subtarget->isLittleEndian()) {
683 for (unsigned im = (unsigned)ISD::PRE_INC;
684 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
685 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
686 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
691 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
692 addRegisterClass(VT, &AArch64::FPR64RegClass);
693 addTypeForNEON(VT, MVT::v2i32);
696 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
697 addRegisterClass(VT, &AArch64::FPR128RegClass);
698 addTypeForNEON(VT, MVT::v4i32);
701 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
705 return VT.changeVectorElementTypeToInteger();
708 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
709 /// Mask are known to be either zero or one and return them in the
710 /// KnownZero/KnownOne bitsets.
711 void AArch64TargetLowering::computeKnownBitsForTargetNode(
712 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
713 const SelectionDAG &DAG, unsigned Depth) const {
714 switch (Op.getOpcode()) {
717 case AArch64ISD::CSEL: {
718 APInt KnownZero2, KnownOne2;
719 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
720 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
721 KnownZero &= KnownZero2;
722 KnownOne &= KnownOne2;
725 case ISD::INTRINSIC_W_CHAIN: {
726 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
727 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
730 case Intrinsic::aarch64_ldaxr:
731 case Intrinsic::aarch64_ldxr: {
732 unsigned BitWidth = KnownOne.getBitWidth();
733 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
734 unsigned MemBits = VT.getScalarType().getSizeInBits();
735 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
741 case ISD::INTRINSIC_WO_CHAIN:
742 case ISD::INTRINSIC_VOID: {
743 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
747 case Intrinsic::aarch64_neon_umaxv:
748 case Intrinsic::aarch64_neon_uminv: {
749 // Figure out the datatype of the vector operand. The UMINV instruction
750 // will zero extend the result, so we can mark as known zero all the
751 // bits larger than the element datatype. 32-bit or larget doesn't need
752 // this as those are legal types and will be handled by isel directly.
753 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
754 unsigned BitWidth = KnownZero.getBitWidth();
755 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
756 assert(BitWidth >= 8 && "Unexpected width!");
757 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
759 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
760 assert(BitWidth >= 16 && "Unexpected width!");
761 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
771 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
776 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
780 if (Subtarget->requiresStrictAlign())
782 // FIXME: True for Cyclone, but not necessary others.
789 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
790 const TargetLibraryInfo *libInfo) const {
791 return AArch64::createFastISel(funcInfo, libInfo);
794 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
795 switch ((AArch64ISD::NodeType)Opcode) {
796 case AArch64ISD::FIRST_NUMBER: break;
797 case AArch64ISD::CALL: return "AArch64ISD::CALL";
798 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
799 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
800 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
801 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
802 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
803 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
804 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
805 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
806 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
807 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
808 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
809 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
810 case AArch64ISD::ADC: return "AArch64ISD::ADC";
811 case AArch64ISD::SBC: return "AArch64ISD::SBC";
812 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
813 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
814 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
815 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
816 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
817 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
818 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
819 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
820 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
821 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
822 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
823 case AArch64ISD::DUP: return "AArch64ISD::DUP";
824 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
825 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
826 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
827 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
828 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
829 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
830 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
831 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
832 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
833 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
834 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
835 case AArch64ISD::BICi: return "AArch64ISD::BICi";
836 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
837 case AArch64ISD::BSL: return "AArch64ISD::BSL";
838 case AArch64ISD::NEG: return "AArch64ISD::NEG";
839 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
840 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
841 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
842 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
843 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
844 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
845 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
846 case AArch64ISD::REV16: return "AArch64ISD::REV16";
847 case AArch64ISD::REV32: return "AArch64ISD::REV32";
848 case AArch64ISD::REV64: return "AArch64ISD::REV64";
849 case AArch64ISD::EXT: return "AArch64ISD::EXT";
850 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
851 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
852 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
853 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
854 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
855 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
856 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
857 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
858 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
859 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
860 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
861 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
862 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
863 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
864 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
865 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
866 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
867 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
868 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
869 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
870 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
871 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
872 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
873 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
874 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
875 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
876 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
877 case AArch64ISD::NOT: return "AArch64ISD::NOT";
878 case AArch64ISD::BIT: return "AArch64ISD::BIT";
879 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
880 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
881 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
882 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
883 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
884 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
885 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
886 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
887 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
888 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
889 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
890 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
891 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
892 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
893 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
894 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
895 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
896 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
897 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
898 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
899 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
900 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
901 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
902 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
903 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
904 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
905 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
906 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
907 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
908 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
909 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
910 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
911 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
912 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
913 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
914 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
915 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
916 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
917 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
918 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
924 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
925 MachineBasicBlock *MBB) const {
926 // We materialise the F128CSEL pseudo-instruction as some control flow and a
930 // [... previous instrs leading to comparison ...]
936 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
938 MachineFunction *MF = MBB->getParent();
939 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
940 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
941 DebugLoc DL = MI->getDebugLoc();
942 MachineFunction::iterator It = MBB;
945 unsigned DestReg = MI->getOperand(0).getReg();
946 unsigned IfTrueReg = MI->getOperand(1).getReg();
947 unsigned IfFalseReg = MI->getOperand(2).getReg();
948 unsigned CondCode = MI->getOperand(3).getImm();
949 bool NZCVKilled = MI->getOperand(4).isKill();
951 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
952 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
953 MF->insert(It, TrueBB);
954 MF->insert(It, EndBB);
956 // Transfer rest of current basic-block to EndBB
957 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
959 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
961 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
962 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
963 MBB->addSuccessor(TrueBB);
964 MBB->addSuccessor(EndBB);
966 // TrueBB falls through to the end.
967 TrueBB->addSuccessor(EndBB);
970 TrueBB->addLiveIn(AArch64::NZCV);
971 EndBB->addLiveIn(AArch64::NZCV);
974 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
980 MI->eraseFromParent();
985 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
986 MachineBasicBlock *BB) const {
987 switch (MI->getOpcode()) {
992 llvm_unreachable("Unexpected instruction for custom inserter!");
994 case AArch64::F128CSEL:
995 return EmitF128CSEL(MI, BB);
997 case TargetOpcode::STACKMAP:
998 case TargetOpcode::PATCHPOINT:
999 return emitPatchPoint(MI, BB);
1003 //===----------------------------------------------------------------------===//
1004 // AArch64 Lowering private implementation.
1005 //===----------------------------------------------------------------------===//
1007 //===----------------------------------------------------------------------===//
1009 //===----------------------------------------------------------------------===//
1011 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1013 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1016 llvm_unreachable("Unknown condition code!");
1018 return AArch64CC::NE;
1020 return AArch64CC::EQ;
1022 return AArch64CC::GT;
1024 return AArch64CC::GE;
1026 return AArch64CC::LT;
1028 return AArch64CC::LE;
1030 return AArch64CC::HI;
1032 return AArch64CC::HS;
1034 return AArch64CC::LO;
1036 return AArch64CC::LS;
1040 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1041 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1042 AArch64CC::CondCode &CondCode,
1043 AArch64CC::CondCode &CondCode2) {
1044 CondCode2 = AArch64CC::AL;
1047 llvm_unreachable("Unknown FP condition!");
1050 CondCode = AArch64CC::EQ;
1054 CondCode = AArch64CC::GT;
1058 CondCode = AArch64CC::GE;
1061 CondCode = AArch64CC::MI;
1064 CondCode = AArch64CC::LS;
1067 CondCode = AArch64CC::MI;
1068 CondCode2 = AArch64CC::GT;
1071 CondCode = AArch64CC::VC;
1074 CondCode = AArch64CC::VS;
1077 CondCode = AArch64CC::EQ;
1078 CondCode2 = AArch64CC::VS;
1081 CondCode = AArch64CC::HI;
1084 CondCode = AArch64CC::PL;
1088 CondCode = AArch64CC::LT;
1092 CondCode = AArch64CC::LE;
1096 CondCode = AArch64CC::NE;
1101 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1102 /// CC usable with the vector instructions. Fewer operations are available
1103 /// without a real NZCV register, so we have to use less efficient combinations
1104 /// to get the same effect.
1105 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1106 AArch64CC::CondCode &CondCode,
1107 AArch64CC::CondCode &CondCode2,
1112 // Mostly the scalar mappings work fine.
1113 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1116 Invert = true; // Fallthrough
1118 CondCode = AArch64CC::MI;
1119 CondCode2 = AArch64CC::GE;
1126 // All of the compare-mask comparisons are ordered, but we can switch
1127 // between the two by a double inversion. E.g. ULE == !OGT.
1129 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1134 static bool isLegalArithImmed(uint64_t C) {
1135 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1136 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1139 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1140 SDLoc dl, SelectionDAG &DAG) {
1141 EVT VT = LHS.getValueType();
1143 if (VT.isFloatingPoint())
1144 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1146 // The CMP instruction is just an alias for SUBS, and representing it as
1147 // SUBS means that it's possible to get CSE with subtract operations.
1148 // A later phase can perform the optimization of setting the destination
1149 // register to WZR/XZR if it ends up being unused.
1150 unsigned Opcode = AArch64ISD::SUBS;
1152 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1153 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1154 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1155 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1156 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1157 // can be set differently by this operation. It comes down to whether
1158 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1159 // everything is fine. If not then the optimization is wrong. Thus general
1160 // comparisons are only valid if op2 != 0.
1162 // So, finally, the only LLVM-native comparisons that don't mention C and V
1163 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1164 // the absence of information about op2.
1165 Opcode = AArch64ISD::ADDS;
1166 RHS = RHS.getOperand(1);
1167 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1168 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1169 !isUnsignedIntSetCC(CC)) {
1170 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1171 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1172 // of the signed comparisons.
1173 Opcode = AArch64ISD::ANDS;
1174 RHS = LHS.getOperand(1);
1175 LHS = LHS.getOperand(0);
1178 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1182 /// \defgroup AArch64CCMP CMP;CCMP matching
1184 /// These functions deal with the formation of CMP;CCMP;... sequences.
1185 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1186 /// a comparison. They set the NZCV flags to a predefined value if their
1187 /// predicate is false. This allows to express arbitrary conjunctions, for
1188 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1191 /// ccmp B, inv(CB), CA
1192 /// check for CB flags
1194 /// In general we can create code for arbitrary "... (and (and A B) C)"
1195 /// sequences. We can also implement some "or" expressions, because "(or A B)"
1196 /// is equivalent to "not (and (not A) (not B))" and we can implement some
1197 /// negation operations:
1198 /// We can negate the results of a single comparison by inverting the flags
1199 /// used when the predicate fails and inverting the flags tested in the next
1200 /// instruction; We can also negate the results of the whole previous
1201 /// conditional compare sequence by inverting the flags tested in the next
1202 /// instruction. However there is no way to negate the result of a partial
1205 /// Therefore on encountering an "or" expression we can negate the subtree on
1206 /// one side and have to be able to push the negate to the leafs of the subtree
1207 /// on the other side (see also the comments in code). As complete example:
1208 /// "or (or (setCA (cmp A)) (setCB (cmp B)))
1209 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1210 /// is transformed to
1211 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1212 /// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1213 /// and implemented as:
1215 /// ccmp D, inv(CD), CC
1216 /// ccmp A, CA, inv(CD)
1217 /// ccmp B, CB, inv(CA)
1218 /// check for CB flags
1219 /// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1220 /// by conditional compare sequences.
1223 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1224 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1225 ISD::CondCode CC, SDValue CCOp,
1226 SDValue Condition, unsigned NZCV,
1227 SDLoc DL, SelectionDAG &DAG) {
1228 unsigned Opcode = 0;
1229 if (LHS.getValueType().isFloatingPoint())
1230 Opcode = AArch64ISD::FCCMP;
1231 else if (RHS.getOpcode() == ISD::SUB) {
1232 SDValue SubOp0 = RHS.getOperand(0);
1233 if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
1234 if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1235 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1236 Opcode = AArch64ISD::CCMN;
1237 RHS = RHS.getOperand(1);
1241 Opcode = AArch64ISD::CCMP;
1243 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1244 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1247 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1248 /// CanPushNegate is set to true if we can push a negate operation through
1249 /// the tree in a was that we are left with AND operations and negate operations
1250 /// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1251 /// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1252 /// brought into such a form.
1253 static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
1254 unsigned Depth = 0) {
1255 if (!Val.hasOneUse())
1257 unsigned Opcode = Val->getOpcode();
1258 if (Opcode == ISD::SETCC) {
1259 CanPushNegate = true;
1262 // Protect against stack overflow.
1265 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1266 SDValue O0 = Val->getOperand(0);
1267 SDValue O1 = Val->getOperand(1);
1268 bool CanPushNegateL;
1269 if (!isConjunctionDisjunctionTree(O0, CanPushNegateL, Depth+1))
1271 bool CanPushNegateR;
1272 if (!isConjunctionDisjunctionTree(O1, CanPushNegateR, Depth+1))
1274 // We cannot push a negate through an AND operation (it would become an OR),
1275 // we can however change a (not (or x y)) to (and (not x) (not y)) if we can
1276 // push the negate through the x/y subtrees.
1277 CanPushNegate = (Opcode == ISD::OR) && CanPushNegateL && CanPushNegateR;
1283 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1284 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1285 /// Tries to transform the given i1 producing node @p Val to a series compare
1286 /// and conditional compare operations. @returns an NZCV flags producing node
1287 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1288 /// transformation was not possible.
1289 /// On recursive invocations @p PushNegate may be set to true to have negation
1290 /// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1291 /// for the comparisons in the current subtree; @p Depth limits the search
1292 /// depth to avoid stack overflow.
1293 static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1294 AArch64CC::CondCode &OutCC, bool PushNegate = false,
1295 SDValue CCOp = SDValue(), AArch64CC::CondCode Predicate = AArch64CC::AL,
1296 unsigned Depth = 0) {
1297 // We're at a tree leaf, produce a conditional comparison operation.
1298 unsigned Opcode = Val->getOpcode();
1299 if (Opcode == ISD::SETCC) {
1300 SDValue LHS = Val->getOperand(0);
1301 SDValue RHS = Val->getOperand(1);
1302 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1303 bool isInteger = LHS.getValueType().isInteger();
1305 CC = getSetCCInverse(CC, isInteger);
1307 // Determine OutCC and handle FP special case.
1309 OutCC = changeIntCCToAArch64CC(CC);
1311 assert(LHS.getValueType().isFloatingPoint());
1312 AArch64CC::CondCode ExtraCC;
1313 changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
1314 // Surpisingly some floating point conditions can't be tested with a
1315 // single condition code. Construct an additional comparison in this case.
1316 // See comment below on how we deal with OR conditions.
1317 if (ExtraCC != AArch64CC::AL) {
1319 if (!CCOp.getNode())
1320 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1322 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1323 // Note that we want the inverse of ExtraCC, so NZCV is not inversed.
1324 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
1325 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
1329 Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
1330 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1334 // Produce a normal comparison if we are first in the chain
1335 if (!CCOp.getNode())
1336 return emitComparison(LHS, RHS, CC, DL, DAG);
1337 // Otherwise produce a ccmp.
1338 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1339 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1340 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1341 return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
1343 } else if (Opcode != ISD::AND && Opcode != ISD::OR)
1346 assert((Opcode == ISD::OR || !PushNegate)
1347 && "Can only push negate through OR operation");
1349 // Check if both sides can be transformed.
1350 SDValue LHS = Val->getOperand(0);
1351 SDValue RHS = Val->getOperand(1);
1352 bool CanPushNegateL;
1353 if (!isConjunctionDisjunctionTree(LHS, CanPushNegateL, Depth+1))
1355 bool CanPushNegateR;
1356 if (!isConjunctionDisjunctionTree(RHS, CanPushNegateR, Depth+1))
1359 // Do we need to negate our operands?
1360 bool NegateOperands = Opcode == ISD::OR;
1361 // We can negate the results of all previous operations by inverting the
1362 // predicate flags giving us a free negation for one side. For the other side
1363 // we need to be able to push the negation to the leafs of the tree.
1364 if (NegateOperands) {
1365 if (!CanPushNegateL && !CanPushNegateR)
1367 // Order the side where we can push the negate through to LHS.
1368 if (!CanPushNegateL && CanPushNegateR) {
1369 std::swap(LHS, RHS);
1370 CanPushNegateL = true;
1374 // Emit RHS. If we want to negate the tree we only need to push a negate
1375 // through if we are already in a PushNegate case, otherwise we can negate
1376 // the "flags to test" afterwards.
1377 AArch64CC::CondCode RHSCC;
1378 SDValue CmpR = emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, PushNegate,
1379 CCOp, Predicate, Depth+1);
1380 if (NegateOperands && !PushNegate)
1381 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1382 // Emit LHS. We must push the negate through if we need to negate it.
1383 SDValue CmpL = emitConjunctionDisjunctionTree(DAG, LHS, OutCC, NegateOperands,
1384 CmpR, RHSCC, Depth+1);
1385 // If we transformed an OR to and AND then we have to negate the result
1386 // (or absorb a PushNegate resulting in a double negation).
1387 if (Opcode == ISD::OR && !PushNegate)
1388 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1394 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1395 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1396 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1397 EVT VT = RHS.getValueType();
1398 uint64_t C = RHSC->getZExtValue();
1399 if (!isLegalArithImmed(C)) {
1400 // Constant does not fit, try adjusting it by one?
1406 if ((VT == MVT::i32 && C != 0x80000000 &&
1407 isLegalArithImmed((uint32_t)(C - 1))) ||
1408 (VT == MVT::i64 && C != 0x80000000ULL &&
1409 isLegalArithImmed(C - 1ULL))) {
1410 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1411 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1412 RHS = DAG.getConstant(C, dl, VT);
1417 if ((VT == MVT::i32 && C != 0 &&
1418 isLegalArithImmed((uint32_t)(C - 1))) ||
1419 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1420 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1421 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1422 RHS = DAG.getConstant(C, dl, VT);
1427 if ((VT == MVT::i32 && C != INT32_MAX &&
1428 isLegalArithImmed((uint32_t)(C + 1))) ||
1429 (VT == MVT::i64 && C != INT64_MAX &&
1430 isLegalArithImmed(C + 1ULL))) {
1431 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1432 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1433 RHS = DAG.getConstant(C, dl, VT);
1438 if ((VT == MVT::i32 && C != UINT32_MAX &&
1439 isLegalArithImmed((uint32_t)(C + 1))) ||
1440 (VT == MVT::i64 && C != UINT64_MAX &&
1441 isLegalArithImmed(C + 1ULL))) {
1442 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1443 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1444 RHS = DAG.getConstant(C, dl, VT);
1451 AArch64CC::CondCode AArch64CC;
1452 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1453 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1455 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1456 // For the i8 operand, the largest immediate is 255, so this can be easily
1457 // encoded in the compare instruction. For the i16 operand, however, the
1458 // largest immediate cannot be encoded in the compare.
1459 // Therefore, use a sign extending load and cmn to avoid materializing the
1460 // -1 constant. For example,
1462 // ldrh w0, [x0, #0]
1465 // ldrsh w0, [x0, #0]
1467 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1468 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1469 // ensure both the LHS and RHS are truly zero extended and to make sure the
1470 // transformation is profitable.
1471 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1472 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1473 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1474 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1475 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1476 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1478 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1479 DAG.getValueType(MVT::i16));
1480 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1481 RHS.getValueType()),
1483 AArch64CC = changeIntCCToAArch64CC(CC);
1487 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1488 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1489 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1490 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1496 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1497 AArch64CC = changeIntCCToAArch64CC(CC);
1499 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1503 static std::pair<SDValue, SDValue>
1504 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1505 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1506 "Unsupported value type");
1507 SDValue Value, Overflow;
1509 SDValue LHS = Op.getOperand(0);
1510 SDValue RHS = Op.getOperand(1);
1512 switch (Op.getOpcode()) {
1514 llvm_unreachable("Unknown overflow instruction!");
1516 Opc = AArch64ISD::ADDS;
1520 Opc = AArch64ISD::ADDS;
1524 Opc = AArch64ISD::SUBS;
1528 Opc = AArch64ISD::SUBS;
1531 // Multiply needs a little bit extra work.
1535 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1536 if (Op.getValueType() == MVT::i32) {
1537 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1538 // For a 32 bit multiply with overflow check we want the instruction
1539 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1540 // need to generate the following pattern:
1541 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1542 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1543 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1544 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1545 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1546 DAG.getConstant(0, DL, MVT::i64));
1547 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1548 // operation. We need to clear out the upper 32 bits, because we used a
1549 // widening multiply that wrote all 64 bits. In the end this should be a
1551 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1553 // The signed overflow check requires more than just a simple check for
1554 // any bit set in the upper 32 bits of the result. These bits could be
1555 // just the sign bits of a negative number. To perform the overflow
1556 // check we have to arithmetic shift right the 32nd bit of the result by
1557 // 31 bits. Then we compare the result to the upper 32 bits.
1558 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1559 DAG.getConstant(32, DL, MVT::i64));
1560 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1561 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1562 DAG.getConstant(31, DL, MVT::i64));
1563 // It is important that LowerBits is last, otherwise the arithmetic
1564 // shift will not be folded into the compare (SUBS).
1565 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1566 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1569 // The overflow check for unsigned multiply is easy. We only need to
1570 // check if any of the upper 32 bits are set. This can be done with a
1571 // CMP (shifted register). For that we need to generate the following
1573 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1574 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1575 DAG.getConstant(32, DL, MVT::i64));
1576 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1578 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1579 DAG.getConstant(0, DL, MVT::i64),
1580 UpperBits).getValue(1);
1584 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1585 // For the 64 bit multiply
1586 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1588 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1589 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1590 DAG.getConstant(63, DL, MVT::i64));
1591 // It is important that LowerBits is last, otherwise the arithmetic
1592 // shift will not be folded into the compare (SUBS).
1593 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1594 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1597 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1598 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1600 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1601 DAG.getConstant(0, DL, MVT::i64),
1602 UpperBits).getValue(1);
1609 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1611 // Emit the AArch64 operation with overflow check.
1612 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1613 Overflow = Value.getValue(1);
1615 return std::make_pair(Value, Overflow);
1618 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1619 RTLIB::Libcall Call) const {
1620 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1621 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1625 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1626 SDValue Sel = Op.getOperand(0);
1627 SDValue Other = Op.getOperand(1);
1629 // If neither operand is a SELECT_CC, give up.
1630 if (Sel.getOpcode() != ISD::SELECT_CC)
1631 std::swap(Sel, Other);
1632 if (Sel.getOpcode() != ISD::SELECT_CC)
1635 // The folding we want to perform is:
1636 // (xor x, (select_cc a, b, cc, 0, -1) )
1638 // (csel x, (xor x, -1), cc ...)
1640 // The latter will get matched to a CSINV instruction.
1642 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1643 SDValue LHS = Sel.getOperand(0);
1644 SDValue RHS = Sel.getOperand(1);
1645 SDValue TVal = Sel.getOperand(2);
1646 SDValue FVal = Sel.getOperand(3);
1649 // FIXME: This could be generalized to non-integer comparisons.
1650 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1653 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1654 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1656 // The values aren't constants, this isn't the pattern we're looking for.
1657 if (!CFVal || !CTVal)
1660 // We can commute the SELECT_CC by inverting the condition. This
1661 // might be needed to make this fit into a CSINV pattern.
1662 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1663 std::swap(TVal, FVal);
1664 std::swap(CTVal, CFVal);
1665 CC = ISD::getSetCCInverse(CC, true);
1668 // If the constants line up, perform the transform!
1669 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1671 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1674 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1675 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1677 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1684 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1685 EVT VT = Op.getValueType();
1687 // Let legalize expand this if it isn't a legal type yet.
1688 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1691 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1694 bool ExtraOp = false;
1695 switch (Op.getOpcode()) {
1697 llvm_unreachable("Invalid code");
1699 Opc = AArch64ISD::ADDS;
1702 Opc = AArch64ISD::SUBS;
1705 Opc = AArch64ISD::ADCS;
1709 Opc = AArch64ISD::SBCS;
1715 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1716 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1720 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1721 // Let legalize expand this if it isn't a legal type yet.
1722 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1726 AArch64CC::CondCode CC;
1727 // The actual operation that sets the overflow or carry flag.
1728 SDValue Value, Overflow;
1729 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1731 // We use 0 and 1 as false and true values.
1732 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1733 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1735 // We use an inverted condition, because the conditional select is inverted
1736 // too. This will allow it to be selected to a single instruction:
1737 // CSINC Wd, WZR, WZR, invert(cond).
1738 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1739 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1742 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1743 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1746 // Prefetch operands are:
1747 // 1: Address to prefetch
1749 // 3: int locality (0 = no locality ... 3 = extreme locality)
1750 // 4: bool isDataCache
1751 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1753 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1754 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1755 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1757 bool IsStream = !Locality;
1758 // When the locality number is set
1760 // The front-end should have filtered out the out-of-range values
1761 assert(Locality <= 3 && "Prefetch locality out-of-range");
1762 // The locality degree is the opposite of the cache speed.
1763 // Put the number the other way around.
1764 // The encoding starts at 0 for level 1
1765 Locality = 3 - Locality;
1768 // built the mask value encoding the expected behavior.
1769 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1770 (!IsData << 3) | // IsDataCache bit
1771 (Locality << 1) | // Cache level bits
1772 (unsigned)IsStream; // Stream bit
1773 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1774 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1777 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1778 SelectionDAG &DAG) const {
1779 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1782 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1784 return LowerF128Call(Op, DAG, LC);
1787 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1788 SelectionDAG &DAG) const {
1789 if (Op.getOperand(0).getValueType() != MVT::f128) {
1790 // It's legal except when f128 is involved
1795 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1797 // FP_ROUND node has a second operand indicating whether it is known to be
1798 // precise. That doesn't take part in the LibCall so we can't directly use
1800 SDValue SrcVal = Op.getOperand(0);
1801 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1802 /*isSigned*/ false, SDLoc(Op)).first;
1805 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1806 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1807 // Any additional optimization in this function should be recorded
1808 // in the cost tables.
1809 EVT InVT = Op.getOperand(0).getValueType();
1810 EVT VT = Op.getValueType();
1812 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1815 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1817 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1820 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1823 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1824 VT.getVectorNumElements());
1825 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1826 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1829 // Type changing conversions are illegal.
1833 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1834 SelectionDAG &DAG) const {
1835 if (Op.getOperand(0).getValueType().isVector())
1836 return LowerVectorFP_TO_INT(Op, DAG);
1838 // f16 conversions are promoted to f32.
1839 if (Op.getOperand(0).getValueType() == MVT::f16) {
1842 Op.getOpcode(), dl, Op.getValueType(),
1843 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1846 if (Op.getOperand(0).getValueType() != MVT::f128) {
1847 // It's legal except when f128 is involved
1852 if (Op.getOpcode() == ISD::FP_TO_SINT)
1853 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1855 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1857 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1858 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1862 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1863 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1864 // Any additional optimization in this function should be recorded
1865 // in the cost tables.
1866 EVT VT = Op.getValueType();
1868 SDValue In = Op.getOperand(0);
1869 EVT InVT = In.getValueType();
1871 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1873 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1874 InVT.getVectorNumElements());
1875 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1876 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1879 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1881 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1882 EVT CastVT = VT.changeVectorElementTypeToInteger();
1883 In = DAG.getNode(CastOpc, dl, CastVT, In);
1884 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1890 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1891 SelectionDAG &DAG) const {
1892 if (Op.getValueType().isVector())
1893 return LowerVectorINT_TO_FP(Op, DAG);
1895 // f16 conversions are promoted to f32.
1896 if (Op.getValueType() == MVT::f16) {
1899 ISD::FP_ROUND, dl, MVT::f16,
1900 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1901 DAG.getIntPtrConstant(0, dl));
1904 // i128 conversions are libcalls.
1905 if (Op.getOperand(0).getValueType() == MVT::i128)
1908 // Other conversions are legal, unless it's to the completely software-based
1910 if (Op.getValueType() != MVT::f128)
1914 if (Op.getOpcode() == ISD::SINT_TO_FP)
1915 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1917 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1919 return LowerF128Call(Op, DAG, LC);
1922 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1923 SelectionDAG &DAG) const {
1924 // For iOS, we want to call an alternative entry point: __sincos_stret,
1925 // which returns the values in two S / D registers.
1927 SDValue Arg = Op.getOperand(0);
1928 EVT ArgVT = Arg.getValueType();
1929 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1936 Entry.isSExt = false;
1937 Entry.isZExt = false;
1938 Args.push_back(Entry);
1940 const char *LibcallName =
1941 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1943 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
1945 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1946 TargetLowering::CallLoweringInfo CLI(DAG);
1947 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1948 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1950 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1951 return CallResult.first;
1954 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1955 if (Op.getValueType() != MVT::f16)
1958 assert(Op.getOperand(0).getValueType() == MVT::i16);
1961 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1962 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1964 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1965 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1969 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1970 if (OrigVT.getSizeInBits() >= 64)
1973 assert(OrigVT.isSimple() && "Expecting a simple value type");
1975 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1976 switch (OrigSimpleTy) {
1977 default: llvm_unreachable("Unexpected Vector Type");
1986 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1989 unsigned ExtOpcode) {
1990 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1991 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1992 // 64-bits we need to insert a new extension so that it will be 64-bits.
1993 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1994 if (OrigTy.getSizeInBits() >= 64)
1997 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1998 EVT NewVT = getExtensionTo64Bits(OrigTy);
2000 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
2003 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2005 EVT VT = N->getValueType(0);
2007 if (N->getOpcode() != ISD::BUILD_VECTOR)
2010 for (const SDValue &Elt : N->op_values()) {
2011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2012 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2013 unsigned HalfSize = EltSize / 2;
2015 if (!isIntN(HalfSize, C->getSExtValue()))
2018 if (!isUIntN(HalfSize, C->getZExtValue()))
2029 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2030 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2031 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2032 N->getOperand(0)->getValueType(0),
2036 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2037 EVT VT = N->getValueType(0);
2039 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
2040 unsigned NumElts = VT.getVectorNumElements();
2041 MVT TruncVT = MVT::getIntegerVT(EltSize);
2042 SmallVector<SDValue, 8> Ops;
2043 for (unsigned i = 0; i != NumElts; ++i) {
2044 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2045 const APInt &CInt = C->getAPIntValue();
2046 // Element types smaller than 32 bits are not legal, so use i32 elements.
2047 // The values are implicitly truncated so sext vs. zext doesn't matter.
2048 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2050 return DAG.getNode(ISD::BUILD_VECTOR, dl,
2051 MVT::getVectorVT(TruncVT, NumElts), Ops);
2054 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2055 if (N->getOpcode() == ISD::SIGN_EXTEND)
2057 if (isExtendedBUILD_VECTOR(N, DAG, true))
2062 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2063 if (N->getOpcode() == ISD::ZERO_EXTEND)
2065 if (isExtendedBUILD_VECTOR(N, DAG, false))
2070 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2071 unsigned Opcode = N->getOpcode();
2072 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2073 SDNode *N0 = N->getOperand(0).getNode();
2074 SDNode *N1 = N->getOperand(1).getNode();
2075 return N0->hasOneUse() && N1->hasOneUse() &&
2076 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2081 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2082 unsigned Opcode = N->getOpcode();
2083 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2084 SDNode *N0 = N->getOperand(0).getNode();
2085 SDNode *N1 = N->getOperand(1).getNode();
2086 return N0->hasOneUse() && N1->hasOneUse() &&
2087 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2092 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2093 // Multiplications are only custom-lowered for 128-bit vectors so that
2094 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2095 EVT VT = Op.getValueType();
2096 assert(VT.is128BitVector() && VT.isInteger() &&
2097 "unexpected type for custom-lowering ISD::MUL");
2098 SDNode *N0 = Op.getOperand(0).getNode();
2099 SDNode *N1 = Op.getOperand(1).getNode();
2100 unsigned NewOpc = 0;
2102 bool isN0SExt = isSignExtended(N0, DAG);
2103 bool isN1SExt = isSignExtended(N1, DAG);
2104 if (isN0SExt && isN1SExt)
2105 NewOpc = AArch64ISD::SMULL;
2107 bool isN0ZExt = isZeroExtended(N0, DAG);
2108 bool isN1ZExt = isZeroExtended(N1, DAG);
2109 if (isN0ZExt && isN1ZExt)
2110 NewOpc = AArch64ISD::UMULL;
2111 else if (isN1SExt || isN1ZExt) {
2112 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2113 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2114 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2115 NewOpc = AArch64ISD::SMULL;
2117 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2118 NewOpc = AArch64ISD::UMULL;
2120 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2122 NewOpc = AArch64ISD::UMULL;
2128 if (VT == MVT::v2i64)
2129 // Fall through to expand this. It is not legal.
2132 // Other vector multiplications are legal.
2137 // Legalize to a S/UMULL instruction
2140 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2142 Op0 = skipExtensionForVectorMULL(N0, DAG);
2143 assert(Op0.getValueType().is64BitVector() &&
2144 Op1.getValueType().is64BitVector() &&
2145 "unexpected types for extended operands to VMULL");
2146 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2148 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2149 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2150 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2151 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2152 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2153 EVT Op1VT = Op1.getValueType();
2154 return DAG.getNode(N0->getOpcode(), DL, VT,
2155 DAG.getNode(NewOpc, DL, VT,
2156 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2157 DAG.getNode(NewOpc, DL, VT,
2158 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2161 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2162 SelectionDAG &DAG) const {
2163 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2166 default: return SDValue(); // Don't custom lower most intrinsics.
2167 case Intrinsic::aarch64_thread_pointer: {
2168 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2169 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2174 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2175 SelectionDAG &DAG) const {
2176 switch (Op.getOpcode()) {
2178 llvm_unreachable("unimplemented operand");
2181 return LowerBITCAST(Op, DAG);
2182 case ISD::GlobalAddress:
2183 return LowerGlobalAddress(Op, DAG);
2184 case ISD::GlobalTLSAddress:
2185 return LowerGlobalTLSAddress(Op, DAG);
2187 return LowerSETCC(Op, DAG);
2189 return LowerBR_CC(Op, DAG);
2191 return LowerSELECT(Op, DAG);
2192 case ISD::SELECT_CC:
2193 return LowerSELECT_CC(Op, DAG);
2194 case ISD::JumpTable:
2195 return LowerJumpTable(Op, DAG);
2196 case ISD::ConstantPool:
2197 return LowerConstantPool(Op, DAG);
2198 case ISD::BlockAddress:
2199 return LowerBlockAddress(Op, DAG);
2201 return LowerVASTART(Op, DAG);
2203 return LowerVACOPY(Op, DAG);
2205 return LowerVAARG(Op, DAG);
2210 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2217 return LowerXALUO(Op, DAG);
2219 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2221 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2223 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2225 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2227 return LowerFP_ROUND(Op, DAG);
2228 case ISD::FP_EXTEND:
2229 return LowerFP_EXTEND(Op, DAG);
2230 case ISD::FRAMEADDR:
2231 return LowerFRAMEADDR(Op, DAG);
2232 case ISD::RETURNADDR:
2233 return LowerRETURNADDR(Op, DAG);
2234 case ISD::INSERT_VECTOR_ELT:
2235 return LowerINSERT_VECTOR_ELT(Op, DAG);
2236 case ISD::EXTRACT_VECTOR_ELT:
2237 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2238 case ISD::BUILD_VECTOR:
2239 return LowerBUILD_VECTOR(Op, DAG);
2240 case ISD::VECTOR_SHUFFLE:
2241 return LowerVECTOR_SHUFFLE(Op, DAG);
2242 case ISD::EXTRACT_SUBVECTOR:
2243 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2247 return LowerVectorSRA_SRL_SHL(Op, DAG);
2248 case ISD::SHL_PARTS:
2249 return LowerShiftLeftParts(Op, DAG);
2250 case ISD::SRL_PARTS:
2251 case ISD::SRA_PARTS:
2252 return LowerShiftRightParts(Op, DAG);
2254 return LowerCTPOP(Op, DAG);
2255 case ISD::FCOPYSIGN:
2256 return LowerFCOPYSIGN(Op, DAG);
2258 return LowerVectorAND(Op, DAG);
2260 return LowerVectorOR(Op, DAG);
2262 return LowerXOR(Op, DAG);
2264 return LowerPREFETCH(Op, DAG);
2265 case ISD::SINT_TO_FP:
2266 case ISD::UINT_TO_FP:
2267 return LowerINT_TO_FP(Op, DAG);
2268 case ISD::FP_TO_SINT:
2269 case ISD::FP_TO_UINT:
2270 return LowerFP_TO_INT(Op, DAG);
2272 return LowerFSINCOS(Op, DAG);
2274 return LowerMUL(Op, DAG);
2275 case ISD::INTRINSIC_WO_CHAIN:
2276 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2280 /// getFunctionAlignment - Return the Log2 alignment of this function.
2281 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2285 //===----------------------------------------------------------------------===//
2286 // Calling Convention Implementation
2287 //===----------------------------------------------------------------------===//
2289 #include "AArch64GenCallingConv.inc"
2291 /// Selects the correct CCAssignFn for a given CallingConvention value.
2292 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2293 bool IsVarArg) const {
2296 llvm_unreachable("Unsupported calling convention.");
2297 case CallingConv::WebKit_JS:
2298 return CC_AArch64_WebKit_JS;
2299 case CallingConv::GHC:
2300 return CC_AArch64_GHC;
2301 case CallingConv::C:
2302 case CallingConv::Fast:
2303 if (!Subtarget->isTargetDarwin())
2304 return CC_AArch64_AAPCS;
2305 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2309 SDValue AArch64TargetLowering::LowerFormalArguments(
2310 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2311 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2312 SmallVectorImpl<SDValue> &InVals) const {
2313 MachineFunction &MF = DAG.getMachineFunction();
2314 MachineFrameInfo *MFI = MF.getFrameInfo();
2316 // Assign locations to all of the incoming arguments.
2317 SmallVector<CCValAssign, 16> ArgLocs;
2318 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2321 // At this point, Ins[].VT may already be promoted to i32. To correctly
2322 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2323 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2324 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2325 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2327 unsigned NumArgs = Ins.size();
2328 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2329 unsigned CurArgIdx = 0;
2330 for (unsigned i = 0; i != NumArgs; ++i) {
2331 MVT ValVT = Ins[i].VT;
2332 if (Ins[i].isOrigArg()) {
2333 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2334 CurArgIdx = Ins[i].getOrigArgIndex();
2336 // Get type of the original argument.
2337 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2338 /*AllowUnknown*/ true);
2339 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2340 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2341 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2343 else if (ActualMVT == MVT::i16)
2346 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2348 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2349 assert(!Res && "Call operand has unhandled type");
2352 assert(ArgLocs.size() == Ins.size());
2353 SmallVector<SDValue, 16> ArgValues;
2354 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2355 CCValAssign &VA = ArgLocs[i];
2357 if (Ins[i].Flags.isByVal()) {
2358 // Byval is used for HFAs in the PCS, but the system should work in a
2359 // non-compliant manner for larger structs.
2360 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2361 int Size = Ins[i].Flags.getByValSize();
2362 unsigned NumRegs = (Size + 7) / 8;
2364 // FIXME: This works on big-endian for composite byvals, which are the common
2365 // case. It should also work for fundamental types too.
2367 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2368 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2369 InVals.push_back(FrameIdxN);
2374 if (VA.isRegLoc()) {
2375 // Arguments stored in registers.
2376 EVT RegVT = VA.getLocVT();
2379 const TargetRegisterClass *RC;
2381 if (RegVT == MVT::i32)
2382 RC = &AArch64::GPR32RegClass;
2383 else if (RegVT == MVT::i64)
2384 RC = &AArch64::GPR64RegClass;
2385 else if (RegVT == MVT::f16)
2386 RC = &AArch64::FPR16RegClass;
2387 else if (RegVT == MVT::f32)
2388 RC = &AArch64::FPR32RegClass;
2389 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2390 RC = &AArch64::FPR64RegClass;
2391 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2392 RC = &AArch64::FPR128RegClass;
2394 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2396 // Transform the arguments in physical registers into virtual ones.
2397 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2398 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2400 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2401 // to 64 bits. Insert an assert[sz]ext to capture this, then
2402 // truncate to the right size.
2403 switch (VA.getLocInfo()) {
2405 llvm_unreachable("Unknown loc info!");
2406 case CCValAssign::Full:
2408 case CCValAssign::BCvt:
2409 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2411 case CCValAssign::AExt:
2412 case CCValAssign::SExt:
2413 case CCValAssign::ZExt:
2414 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2415 // nodes after our lowering.
2416 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2420 InVals.push_back(ArgValue);
2422 } else { // VA.isRegLoc()
2423 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2424 unsigned ArgOffset = VA.getLocMemOffset();
2425 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2427 uint32_t BEAlign = 0;
2428 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2429 !Ins[i].Flags.isInConsecutiveRegs())
2430 BEAlign = 8 - ArgSize;
2432 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2434 // Create load nodes to retrieve arguments from the stack.
2435 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2438 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2439 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2440 MVT MemVT = VA.getValVT();
2442 switch (VA.getLocInfo()) {
2445 case CCValAssign::BCvt:
2446 MemVT = VA.getLocVT();
2448 case CCValAssign::SExt:
2449 ExtType = ISD::SEXTLOAD;
2451 case CCValAssign::ZExt:
2452 ExtType = ISD::ZEXTLOAD;
2454 case CCValAssign::AExt:
2455 ExtType = ISD::EXTLOAD;
2459 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2460 MachinePointerInfo::getFixedStack(FI),
2461 MemVT, false, false, false, 0);
2463 InVals.push_back(ArgValue);
2469 if (!Subtarget->isTargetDarwin()) {
2470 // The AAPCS variadic function ABI is identical to the non-variadic
2471 // one. As a result there may be more arguments in registers and we should
2472 // save them for future reference.
2473 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2476 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2477 // This will point to the next argument passed via stack.
2478 unsigned StackOffset = CCInfo.getNextStackOffset();
2479 // We currently pass all varargs at 8-byte alignment.
2480 StackOffset = ((StackOffset + 7) & ~7);
2481 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2484 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2485 unsigned StackArgSize = CCInfo.getNextStackOffset();
2486 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2487 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2488 // This is a non-standard ABI so by fiat I say we're allowed to make full
2489 // use of the stack area to be popped, which must be aligned to 16 bytes in
2491 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2493 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2494 // a multiple of 16.
2495 FuncInfo->setArgumentStackToRestore(StackArgSize);
2497 // This realignment carries over to the available bytes below. Our own
2498 // callers will guarantee the space is free by giving an aligned value to
2501 // Even if we're not expected to free up the space, it's useful to know how
2502 // much is there while considering tail calls (because we can reuse it).
2503 FuncInfo->setBytesInStackArgArea(StackArgSize);
2508 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2509 SelectionDAG &DAG, SDLoc DL,
2510 SDValue &Chain) const {
2511 MachineFunction &MF = DAG.getMachineFunction();
2512 MachineFrameInfo *MFI = MF.getFrameInfo();
2513 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2514 auto PtrVT = getPointerTy(DAG.getDataLayout());
2516 SmallVector<SDValue, 8> MemOps;
2518 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2519 AArch64::X3, AArch64::X4, AArch64::X5,
2520 AArch64::X6, AArch64::X7 };
2521 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2522 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2524 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2526 if (GPRSaveSize != 0) {
2527 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2529 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2531 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2532 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2533 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2535 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2536 MachinePointerInfo::getStack(i * 8), false, false, 0);
2537 MemOps.push_back(Store);
2539 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2542 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2543 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2545 if (Subtarget->hasFPARMv8()) {
2546 static const MCPhysReg FPRArgRegs[] = {
2547 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2548 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2549 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2550 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2552 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2554 if (FPRSaveSize != 0) {
2555 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2557 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2559 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2560 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2561 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2564 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2565 MachinePointerInfo::getStack(i * 16), false, false, 0);
2566 MemOps.push_back(Store);
2567 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2568 DAG.getConstant(16, DL, PtrVT));
2571 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2572 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2575 if (!MemOps.empty()) {
2576 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2580 /// LowerCallResult - Lower the result values of a call into the
2581 /// appropriate copies out of appropriate physical registers.
2582 SDValue AArch64TargetLowering::LowerCallResult(
2583 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2584 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2585 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2586 SDValue ThisVal) const {
2587 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2588 ? RetCC_AArch64_WebKit_JS
2589 : RetCC_AArch64_AAPCS;
2590 // Assign locations to each value returned by this call.
2591 SmallVector<CCValAssign, 16> RVLocs;
2592 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2594 CCInfo.AnalyzeCallResult(Ins, RetCC);
2596 // Copy all of the result registers out of their specified physreg.
2597 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2598 CCValAssign VA = RVLocs[i];
2600 // Pass 'this' value directly from the argument to return value, to avoid
2601 // reg unit interference
2602 if (i == 0 && isThisReturn) {
2603 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2604 "unexpected return calling convention register assignment");
2605 InVals.push_back(ThisVal);
2610 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2611 Chain = Val.getValue(1);
2612 InFlag = Val.getValue(2);
2614 switch (VA.getLocInfo()) {
2616 llvm_unreachable("Unknown loc info!");
2617 case CCValAssign::Full:
2619 case CCValAssign::BCvt:
2620 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2624 InVals.push_back(Val);
2630 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2631 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2632 bool isCalleeStructRet, bool isCallerStructRet,
2633 const SmallVectorImpl<ISD::OutputArg> &Outs,
2634 const SmallVectorImpl<SDValue> &OutVals,
2635 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2636 // For CallingConv::C this function knows whether the ABI needs
2637 // changing. That's not true for other conventions so they will have to opt in
2639 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2642 const MachineFunction &MF = DAG.getMachineFunction();
2643 const Function *CallerF = MF.getFunction();
2644 CallingConv::ID CallerCC = CallerF->getCallingConv();
2645 bool CCMatch = CallerCC == CalleeCC;
2647 // Byval parameters hand the function a pointer directly into the stack area
2648 // we want to reuse during a tail call. Working around this *is* possible (see
2649 // X86) but less efficient and uglier in LowerCall.
2650 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2651 e = CallerF->arg_end();
2653 if (i->hasByValAttr())
2656 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2657 if (IsTailCallConvention(CalleeCC) && CCMatch)
2662 // Externally-defined functions with weak linkage should not be
2663 // tail-called on AArch64 when the OS does not support dynamic
2664 // pre-emption of symbols, as the AAELF spec requires normal calls
2665 // to undefined weak functions to be replaced with a NOP or jump to the
2666 // next instruction. The behaviour of branch instructions in this
2667 // situation (as used for tail calls) is implementation-defined, so we
2668 // cannot rely on the linker replacing the tail call with a return.
2669 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2670 const GlobalValue *GV = G->getGlobal();
2671 const Triple &TT = getTargetMachine().getTargetTriple();
2672 if (GV->hasExternalWeakLinkage() &&
2673 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2677 // Now we search for cases where we can use a tail call without changing the
2678 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2681 // I want anyone implementing a new calling convention to think long and hard
2682 // about this assert.
2683 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2684 "Unexpected variadic calling convention");
2686 if (isVarArg && !Outs.empty()) {
2687 // At least two cases here: if caller is fastcc then we can't have any
2688 // memory arguments (we'd be expected to clean up the stack afterwards). If
2689 // caller is C then we could potentially use its argument area.
2691 // FIXME: for now we take the most conservative of these in both cases:
2692 // disallow all variadic memory operands.
2693 SmallVector<CCValAssign, 16> ArgLocs;
2694 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2697 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2698 for (const CCValAssign &ArgLoc : ArgLocs)
2699 if (!ArgLoc.isRegLoc())
2703 // If the calling conventions do not match, then we'd better make sure the
2704 // results are returned in the same way as what the caller expects.
2706 SmallVector<CCValAssign, 16> RVLocs1;
2707 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2709 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2711 SmallVector<CCValAssign, 16> RVLocs2;
2712 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2714 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2716 if (RVLocs1.size() != RVLocs2.size())
2718 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2719 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2721 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2723 if (RVLocs1[i].isRegLoc()) {
2724 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2727 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2733 // Nothing more to check if the callee is taking no arguments
2737 SmallVector<CCValAssign, 16> ArgLocs;
2738 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2741 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2743 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2745 // If the stack arguments for this call would fit into our own save area then
2746 // the call can be made tail.
2747 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2750 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2752 MachineFrameInfo *MFI,
2753 int ClobberedFI) const {
2754 SmallVector<SDValue, 8> ArgChains;
2755 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2756 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2758 // Include the original chain at the beginning of the list. When this is
2759 // used by target LowerCall hooks, this helps legalize find the
2760 // CALLSEQ_BEGIN node.
2761 ArgChains.push_back(Chain);
2763 // Add a chain value for each stack argument corresponding
2764 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2765 UE = DAG.getEntryNode().getNode()->use_end();
2767 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2768 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2769 if (FI->getIndex() < 0) {
2770 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2771 int64_t InLastByte = InFirstByte;
2772 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2774 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2775 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2776 ArgChains.push_back(SDValue(L, 1));
2779 // Build a tokenfactor for all the chains.
2780 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2783 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2784 bool TailCallOpt) const {
2785 return CallCC == CallingConv::Fast && TailCallOpt;
2788 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2789 return CallCC == CallingConv::Fast;
2792 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2793 /// and add input and output parameter nodes.
2795 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2796 SmallVectorImpl<SDValue> &InVals) const {
2797 SelectionDAG &DAG = CLI.DAG;
2799 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2800 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2801 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2802 SDValue Chain = CLI.Chain;
2803 SDValue Callee = CLI.Callee;
2804 bool &IsTailCall = CLI.IsTailCall;
2805 CallingConv::ID CallConv = CLI.CallConv;
2806 bool IsVarArg = CLI.IsVarArg;
2808 MachineFunction &MF = DAG.getMachineFunction();
2809 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2810 bool IsThisReturn = false;
2812 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2813 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2814 bool IsSibCall = false;
2817 // Check if it's really possible to do a tail call.
2818 IsTailCall = isEligibleForTailCallOptimization(
2819 Callee, CallConv, IsVarArg, IsStructRet,
2820 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2821 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2822 report_fatal_error("failed to perform tail call elimination on a call "
2823 "site marked musttail");
2825 // A sibling call is one where we're under the usual C ABI and not planning
2826 // to change that but can still do a tail call:
2827 if (!TailCallOpt && IsTailCall)
2834 // Analyze operands of the call, assigning locations to each operand.
2835 SmallVector<CCValAssign, 16> ArgLocs;
2836 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2840 // Handle fixed and variable vector arguments differently.
2841 // Variable vector arguments always go into memory.
2842 unsigned NumArgs = Outs.size();
2844 for (unsigned i = 0; i != NumArgs; ++i) {
2845 MVT ArgVT = Outs[i].VT;
2846 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2847 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2848 /*IsVarArg=*/ !Outs[i].IsFixed);
2849 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2850 assert(!Res && "Call operand has unhandled type");
2854 // At this point, Outs[].VT may already be promoted to i32. To correctly
2855 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2856 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2857 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2858 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2860 unsigned NumArgs = Outs.size();
2861 for (unsigned i = 0; i != NumArgs; ++i) {
2862 MVT ValVT = Outs[i].VT;
2863 // Get type of the original argument.
2864 EVT ActualVT = getValueType(DAG.getDataLayout(),
2865 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2866 /*AllowUnknown*/ true);
2867 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2868 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2869 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2870 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2872 else if (ActualMVT == MVT::i16)
2875 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2876 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2877 assert(!Res && "Call operand has unhandled type");
2882 // Get a count of how many bytes are to be pushed on the stack.
2883 unsigned NumBytes = CCInfo.getNextStackOffset();
2886 // Since we're not changing the ABI to make this a tail call, the memory
2887 // operands are already available in the caller's incoming argument space.
2891 // FPDiff is the byte offset of the call's argument area from the callee's.
2892 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2893 // by this amount for a tail call. In a sibling call it must be 0 because the
2894 // caller will deallocate the entire stack and the callee still expects its
2895 // arguments to begin at SP+0. Completely unused for non-tail calls.
2898 if (IsTailCall && !IsSibCall) {
2899 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2901 // Since callee will pop argument stack as a tail call, we must keep the
2902 // popped size 16-byte aligned.
2903 NumBytes = RoundUpToAlignment(NumBytes, 16);
2905 // FPDiff will be negative if this tail call requires more space than we
2906 // would automatically have in our incoming argument space. Positive if we
2907 // can actually shrink the stack.
2908 FPDiff = NumReusableBytes - NumBytes;
2910 // The stack pointer must be 16-byte aligned at all times it's used for a
2911 // memory operation, which in practice means at *all* times and in
2912 // particular across call boundaries. Therefore our own arguments started at
2913 // a 16-byte aligned SP and the delta applied for the tail call should
2914 // satisfy the same constraint.
2915 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2918 // Adjust the stack pointer for the new arguments...
2919 // These operations are automatically eliminated by the prolog/epilog pass
2921 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2925 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
2926 getPointerTy(DAG.getDataLayout()));
2928 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2929 SmallVector<SDValue, 8> MemOpChains;
2930 auto PtrVT = getPointerTy(DAG.getDataLayout());
2932 // Walk the register/memloc assignments, inserting copies/loads.
2933 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2934 ++i, ++realArgIdx) {
2935 CCValAssign &VA = ArgLocs[i];
2936 SDValue Arg = OutVals[realArgIdx];
2937 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2939 // Promote the value if needed.
2940 switch (VA.getLocInfo()) {
2942 llvm_unreachable("Unknown loc info!");
2943 case CCValAssign::Full:
2945 case CCValAssign::SExt:
2946 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2948 case CCValAssign::ZExt:
2949 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2951 case CCValAssign::AExt:
2952 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2953 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2954 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2955 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2957 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2959 case CCValAssign::BCvt:
2960 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2962 case CCValAssign::FPExt:
2963 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2967 if (VA.isRegLoc()) {
2968 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2969 assert(VA.getLocVT() == MVT::i64 &&
2970 "unexpected calling convention register assignment");
2971 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2972 "unexpected use of 'returned'");
2973 IsThisReturn = true;
2975 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2977 assert(VA.isMemLoc());
2980 MachinePointerInfo DstInfo;
2982 // FIXME: This works on big-endian for composite byvals, which are the
2983 // common case. It should also work for fundamental types too.
2984 uint32_t BEAlign = 0;
2985 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2986 : VA.getValVT().getSizeInBits();
2987 OpSize = (OpSize + 7) / 8;
2988 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2989 !Flags.isInConsecutiveRegs()) {
2991 BEAlign = 8 - OpSize;
2993 unsigned LocMemOffset = VA.getLocMemOffset();
2994 int32_t Offset = LocMemOffset + BEAlign;
2995 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2996 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
2999 Offset = Offset + FPDiff;
3000 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3002 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3003 DstInfo = MachinePointerInfo::getFixedStack(FI);
3005 // Make sure any stack arguments overlapping with where we're storing
3006 // are loaded before this eventual operation. Otherwise they'll be
3008 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3010 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3012 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3013 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
3016 if (Outs[i].Flags.isByVal()) {
3018 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3019 SDValue Cpy = DAG.getMemcpy(
3020 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3021 /*isVol = */ false, /*AlwaysInline = */ false,
3022 /*isTailCall = */ false,
3023 DstInfo, MachinePointerInfo());
3025 MemOpChains.push_back(Cpy);
3027 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3028 // promoted to a legal register type i32, we should truncate Arg back to
3030 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3031 VA.getValVT() == MVT::i16)
3032 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3035 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
3036 MemOpChains.push_back(Store);
3041 if (!MemOpChains.empty())
3042 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3044 // Build a sequence of copy-to-reg nodes chained together with token chain
3045 // and flag operands which copy the outgoing args into the appropriate regs.
3047 for (auto &RegToPass : RegsToPass) {
3048 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3049 RegToPass.second, InFlag);
3050 InFlag = Chain.getValue(1);
3053 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3054 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3055 // node so that legalize doesn't hack it.
3056 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3057 Subtarget->isTargetMachO()) {
3058 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3059 const GlobalValue *GV = G->getGlobal();
3060 bool InternalLinkage = GV->hasInternalLinkage();
3061 if (InternalLinkage)
3062 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3065 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3066 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3068 } else if (ExternalSymbolSDNode *S =
3069 dyn_cast<ExternalSymbolSDNode>(Callee)) {
3070 const char *Sym = S->getSymbol();
3071 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3072 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3074 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3075 const GlobalValue *GV = G->getGlobal();
3076 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3077 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3078 const char *Sym = S->getSymbol();
3079 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3082 // We don't usually want to end the call-sequence here because we would tidy
3083 // the frame up *after* the call, however in the ABI-changing tail-call case
3084 // we've carefully laid out the parameters so that when sp is reset they'll be
3085 // in the correct location.
3086 if (IsTailCall && !IsSibCall) {
3087 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3088 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3089 InFlag = Chain.getValue(1);
3092 std::vector<SDValue> Ops;
3093 Ops.push_back(Chain);
3094 Ops.push_back(Callee);
3097 // Each tail call may have to adjust the stack by a different amount, so
3098 // this information must travel along with the operation for eventual
3099 // consumption by emitEpilogue.
3100 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3103 // Add argument registers to the end of the list so that they are known live
3105 for (auto &RegToPass : RegsToPass)
3106 Ops.push_back(DAG.getRegister(RegToPass.first,
3107 RegToPass.second.getValueType()));
3109 // Add a register mask operand representing the call-preserved registers.
3110 const uint32_t *Mask;
3111 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3113 // For 'this' returns, use the X0-preserving mask if applicable
3114 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3116 IsThisReturn = false;
3117 Mask = TRI->getCallPreservedMask(MF, CallConv);
3120 Mask = TRI->getCallPreservedMask(MF, CallConv);
3122 assert(Mask && "Missing call preserved mask for calling convention");
3123 Ops.push_back(DAG.getRegisterMask(Mask));
3125 if (InFlag.getNode())
3126 Ops.push_back(InFlag);
3128 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 // If we're doing a tall call, use a TC_RETURN here rather than an
3131 // actual call instruction.
3133 MF.getFrameInfo()->setHasTailCall();
3134 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3137 // Returns a chain and a flag for retval copy to use.
3138 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3139 InFlag = Chain.getValue(1);
3141 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
3142 ? RoundUpToAlignment(NumBytes, 16)
3145 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3146 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3149 InFlag = Chain.getValue(1);
3151 // Handle result values, copying them out of physregs into vregs that we
3153 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3154 InVals, IsThisReturn,
3155 IsThisReturn ? OutVals[0] : SDValue());
3158 bool AArch64TargetLowering::CanLowerReturn(
3159 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3160 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3161 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3162 ? RetCC_AArch64_WebKit_JS
3163 : RetCC_AArch64_AAPCS;
3164 SmallVector<CCValAssign, 16> RVLocs;
3165 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3166 return CCInfo.CheckReturn(Outs, RetCC);
3170 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3172 const SmallVectorImpl<ISD::OutputArg> &Outs,
3173 const SmallVectorImpl<SDValue> &OutVals,
3174 SDLoc DL, SelectionDAG &DAG) const {
3175 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3176 ? RetCC_AArch64_WebKit_JS
3177 : RetCC_AArch64_AAPCS;
3178 SmallVector<CCValAssign, 16> RVLocs;
3179 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3181 CCInfo.AnalyzeReturn(Outs, RetCC);
3183 // Copy the result values into the output registers.
3185 SmallVector<SDValue, 4> RetOps(1, Chain);
3186 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3187 ++i, ++realRVLocIdx) {
3188 CCValAssign &VA = RVLocs[i];
3189 assert(VA.isRegLoc() && "Can only return in registers!");
3190 SDValue Arg = OutVals[realRVLocIdx];
3192 switch (VA.getLocInfo()) {
3194 llvm_unreachable("Unknown loc info!");
3195 case CCValAssign::Full:
3196 if (Outs[i].ArgVT == MVT::i1) {
3197 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3198 // value. This is strictly redundant on Darwin (which uses "zeroext
3199 // i1"), but will be optimised out before ISel.
3200 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3201 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3204 case CCValAssign::BCvt:
3205 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3210 Flag = Chain.getValue(1);
3211 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3214 RetOps[0] = Chain; // Update chain.
3216 // Add the flag if we have it.
3218 RetOps.push_back(Flag);
3220 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3223 //===----------------------------------------------------------------------===//
3224 // Other Lowering Code
3225 //===----------------------------------------------------------------------===//
3227 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3228 SelectionDAG &DAG) const {
3229 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3231 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3232 const GlobalValue *GV = GN->getGlobal();
3233 unsigned char OpFlags =
3234 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3236 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
3237 "unexpected offset in global node");
3239 // This also catched the large code model case for Darwin.
3240 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3241 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
3242 // FIXME: Once remat is capable of dealing with instructions with register
3243 // operands, expand this into two nodes instead of using a wrapper node.
3244 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3247 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
3248 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3249 "use of MO_CONSTPOOL only supported on small model");
3250 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3251 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3252 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3253 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3254 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3255 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3256 MachinePointerInfo::getConstantPool(),
3257 /*isVolatile=*/ false,
3258 /*isNonTemporal=*/ true,
3259 /*isInvariant=*/ true, 8);
3260 if (GN->getOffset() != 0)
3261 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3262 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3266 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3267 const unsigned char MO_NC = AArch64II::MO_NC;
3269 AArch64ISD::WrapperLarge, DL, PtrVT,
3270 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3271 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3272 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3273 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3275 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3276 // the only correct model on Darwin.
3277 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3278 OpFlags | AArch64II::MO_PAGE);
3279 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3280 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3282 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3283 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3287 /// \brief Convert a TLS address reference into the correct sequence of loads
3288 /// and calls to compute the variable's address (for Darwin, currently) and
3289 /// return an SDValue containing the final node.
3291 /// Darwin only has one TLS scheme which must be capable of dealing with the
3292 /// fully general situation, in the worst case. This means:
3293 /// + "extern __thread" declaration.
3294 /// + Defined in a possibly unknown dynamic library.
3296 /// The general system is that each __thread variable has a [3 x i64] descriptor
3297 /// which contains information used by the runtime to calculate the address. The
3298 /// only part of this the compiler needs to know about is the first xword, which
3299 /// contains a function pointer that must be called with the address of the
3300 /// entire descriptor in "x0".
3302 /// Since this descriptor may be in a different unit, in general even the
3303 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3305 /// adrp x0, _var@TLVPPAGE
3306 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3307 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3308 /// ; the function pointer
3309 /// blr x1 ; Uses descriptor address in x0
3310 /// ; Address of _var is now in x0.
3312 /// If the address of _var's descriptor *is* known to the linker, then it can
3313 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3314 /// a slight efficiency gain.
3316 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3317 SelectionDAG &DAG) const {
3318 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3321 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3322 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3325 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3326 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3328 // The first entry in the descriptor is a function pointer that we must call
3329 // to obtain the address of the variable.
3330 SDValue Chain = DAG.getEntryNode();
3331 SDValue FuncTLVGet =
3332 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3333 false, true, true, 8);
3334 Chain = FuncTLVGet.getValue(1);
3336 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3337 MFI->setAdjustsStack(true);
3339 // TLS calls preserve all registers except those that absolutely must be
3340 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3342 const uint32_t *Mask =
3343 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3345 // Finally, we can make the call. This is just a degenerate version of a
3346 // normal AArch64 call node: x0 takes the address of the descriptor, and
3347 // returns the address of the variable in this thread.
3348 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3350 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3351 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3352 DAG.getRegisterMask(Mask), Chain.getValue(1));
3353 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3356 /// When accessing thread-local variables under either the general-dynamic or
3357 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3358 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3359 /// is a function pointer to carry out the resolution.
3361 /// The sequence is:
3362 /// adrp x0, :tlsdesc:var
3363 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3364 /// add x0, x0, #:tlsdesc_lo12:var
3365 /// .tlsdesccall var
3367 /// (TPIDR_EL0 offset now in x0)
3369 /// The above sequence must be produced unscheduled, to enable the linker to
3370 /// optimize/relax this sequence.
3371 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3372 /// above sequence, and expanded really late in the compilation flow, to ensure
3373 /// the sequence is produced as per above.
3374 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3375 SelectionDAG &DAG) const {
3376 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3378 SDValue Chain = DAG.getEntryNode();
3379 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3381 SmallVector<SDValue, 2> Ops;
3382 Ops.push_back(Chain);
3383 Ops.push_back(SymAddr);
3385 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3386 SDValue Glue = Chain.getValue(1);
3388 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3392 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3393 SelectionDAG &DAG) const {
3394 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3395 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3396 "ELF TLS only supported in small memory model");
3397 // Different choices can be made for the maximum size of the TLS area for a
3398 // module. For the small address model, the default TLS size is 16MiB and the
3399 // maximum TLS size is 4GiB.
3400 // FIXME: add -mtls-size command line option and make it control the 16MiB
3401 // vs. 4GiB code sequence generation.
3402 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3404 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3406 if (DAG.getTarget().Options.EmulatedTLS)
3407 return LowerToTLSEmulatedModel(GA, DAG);
3409 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3410 if (Model == TLSModel::LocalDynamic)
3411 Model = TLSModel::GeneralDynamic;
3415 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3417 const GlobalValue *GV = GA->getGlobal();
3419 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3421 if (Model == TLSModel::LocalExec) {
3422 SDValue HiVar = DAG.getTargetGlobalAddress(
3423 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3424 SDValue LoVar = DAG.getTargetGlobalAddress(
3426 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3428 SDValue TPWithOff_lo =
3429 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3431 DAG.getTargetConstant(0, DL, MVT::i32)),
3434 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3436 DAG.getTargetConstant(0, DL, MVT::i32)),
3439 } else if (Model == TLSModel::InitialExec) {
3440 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3441 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3442 } else if (Model == TLSModel::LocalDynamic) {
3443 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3444 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3445 // the beginning of the module's TLS region, followed by a DTPREL offset
3448 // These accesses will need deduplicating if there's more than one.
3449 AArch64FunctionInfo *MFI =
3450 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3451 MFI->incNumLocalDynamicTLSAccesses();
3453 // The call needs a relocation too for linker relaxation. It doesn't make
3454 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3456 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3459 // Now we can calculate the offset from TPIDR_EL0 to this module's
3460 // thread-local area.
3461 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3463 // Now use :dtprel_whatever: operations to calculate this variable's offset
3464 // in its thread-storage area.
3465 SDValue HiVar = DAG.getTargetGlobalAddress(
3466 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3467 SDValue LoVar = DAG.getTargetGlobalAddress(
3468 GV, DL, MVT::i64, 0,
3469 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3471 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3472 DAG.getTargetConstant(0, DL, MVT::i32)),
3474 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3475 DAG.getTargetConstant(0, DL, MVT::i32)),
3477 } else if (Model == TLSModel::GeneralDynamic) {
3478 // The call needs a relocation too for linker relaxation. It doesn't make
3479 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3482 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3484 // Finally we can make a call to calculate the offset from tpidr_el0.
3485 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3487 llvm_unreachable("Unsupported ELF TLS access model");
3489 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3492 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3493 SelectionDAG &DAG) const {
3494 if (Subtarget->isTargetDarwin())
3495 return LowerDarwinGlobalTLSAddress(Op, DAG);
3496 else if (Subtarget->isTargetELF())
3497 return LowerELFGlobalTLSAddress(Op, DAG);
3499 llvm_unreachable("Unexpected platform trying to use TLS");
3501 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3502 SDValue Chain = Op.getOperand(0);
3503 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3504 SDValue LHS = Op.getOperand(2);
3505 SDValue RHS = Op.getOperand(3);
3506 SDValue Dest = Op.getOperand(4);
3509 // Handle f128 first, since lowering it will result in comparing the return
3510 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3511 // is expecting to deal with.
3512 if (LHS.getValueType() == MVT::f128) {
3513 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3515 // If softenSetCCOperands returned a scalar, we need to compare the result
3516 // against zero to select between true and false values.
3517 if (!RHS.getNode()) {
3518 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3523 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3525 unsigned Opc = LHS.getOpcode();
3526 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3527 cast<ConstantSDNode>(RHS)->isOne() &&
3528 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3529 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3530 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3531 "Unexpected condition code.");
3532 // Only lower legal XALUO ops.
3533 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3536 // The actual operation with overflow check.
3537 AArch64CC::CondCode OFCC;
3538 SDValue Value, Overflow;
3539 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3541 if (CC == ISD::SETNE)
3542 OFCC = getInvertedCondCode(OFCC);
3543 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3545 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3549 if (LHS.getValueType().isInteger()) {
3550 assert((LHS.getValueType() == RHS.getValueType()) &&
3551 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3553 // If the RHS of the comparison is zero, we can potentially fold this
3554 // to a specialized branch.
3555 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3556 if (RHSC && RHSC->getZExtValue() == 0) {
3557 if (CC == ISD::SETEQ) {
3558 // See if we can use a TBZ to fold in an AND as well.
3559 // TBZ has a smaller branch displacement than CBZ. If the offset is
3560 // out of bounds, a late MI-layer pass rewrites branches.
3561 // 403.gcc is an example that hits this case.
3562 if (LHS.getOpcode() == ISD::AND &&
3563 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3564 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3565 SDValue Test = LHS.getOperand(0);
3566 uint64_t Mask = LHS.getConstantOperandVal(1);
3567 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3568 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3572 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3573 } else if (CC == ISD::SETNE) {
3574 // See if we can use a TBZ to fold in an AND as well.
3575 // TBZ has a smaller branch displacement than CBZ. If the offset is
3576 // out of bounds, a late MI-layer pass rewrites branches.
3577 // 403.gcc is an example that hits this case.
3578 if (LHS.getOpcode() == ISD::AND &&
3579 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3580 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3581 SDValue Test = LHS.getOperand(0);
3582 uint64_t Mask = LHS.getConstantOperandVal(1);
3583 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3584 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3588 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3589 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3590 // Don't combine AND since emitComparison converts the AND to an ANDS
3591 // (a.k.a. TST) and the test in the test bit and branch instruction
3592 // becomes redundant. This would also increase register pressure.
3593 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3594 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3595 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3598 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3599 LHS.getOpcode() != ISD::AND) {
3600 // Don't combine AND since emitComparison converts the AND to an ANDS
3601 // (a.k.a. TST) and the test in the test bit and branch instruction
3602 // becomes redundant. This would also increase register pressure.
3603 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3604 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3605 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3609 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3610 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3614 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3616 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3617 // clean. Some of them require two branches to implement.
3618 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3619 AArch64CC::CondCode CC1, CC2;
3620 changeFPCCToAArch64CC(CC, CC1, CC2);
3621 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3623 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3624 if (CC2 != AArch64CC::AL) {
3625 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3626 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3633 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3634 SelectionDAG &DAG) const {
3635 EVT VT = Op.getValueType();
3638 SDValue In1 = Op.getOperand(0);
3639 SDValue In2 = Op.getOperand(1);
3640 EVT SrcVT = In2.getValueType();
3642 if (SrcVT == MVT::f32 && VT == MVT::f64)
3643 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3644 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3645 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3646 DAG.getIntPtrConstant(0, DL));
3648 // FIXME: Src type is different, bail out for now. Can VT really be a
3656 SDValue VecVal1, VecVal2;
3657 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3659 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
3660 EltMask = 0x80000000ULL;
3662 if (!VT.isVector()) {
3663 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3664 DAG.getUNDEF(VecVT), In1);
3665 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3666 DAG.getUNDEF(VecVT), In2);
3668 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3669 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3671 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3675 // We want to materialize a mask with the high bit set, but the AdvSIMD
3676 // immediate moves cannot materialize that in a single instruction for
3677 // 64-bit elements. Instead, materialize zero and then negate it.
3680 if (!VT.isVector()) {
3681 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3682 DAG.getUNDEF(VecVT), In1);
3683 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3684 DAG.getUNDEF(VecVT), In2);
3686 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3687 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3690 llvm_unreachable("Invalid type for copysign!");
3693 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3695 // If we couldn't materialize the mask above, then the mask vector will be
3696 // the zero vector, and we need to negate it here.
3697 if (VT == MVT::f64 || VT == MVT::v2f64) {
3698 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3699 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3700 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3704 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3707 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3708 else if (VT == MVT::f64)
3709 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3711 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3714 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3715 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3716 Attribute::NoImplicitFloat))
3719 if (!Subtarget->hasNEON())
3722 // While there is no integer popcount instruction, it can
3723 // be more efficiently lowered to the following sequence that uses
3724 // AdvSIMD registers/instructions as long as the copies to/from
3725 // the AdvSIMD registers are cheap.
3726 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3727 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3728 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3729 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3730 SDValue Val = Op.getOperand(0);
3732 EVT VT = Op.getValueType();
3735 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3736 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3738 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3739 SDValue UaddLV = DAG.getNode(
3740 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3741 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3744 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3748 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3750 if (Op.getValueType().isVector())
3751 return LowerVSETCC(Op, DAG);
3753 SDValue LHS = Op.getOperand(0);
3754 SDValue RHS = Op.getOperand(1);
3755 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3758 // We chose ZeroOrOneBooleanContents, so use zero and one.
3759 EVT VT = Op.getValueType();
3760 SDValue TVal = DAG.getConstant(1, dl, VT);
3761 SDValue FVal = DAG.getConstant(0, dl, VT);
3763 // Handle f128 first, since one possible outcome is a normal integer
3764 // comparison which gets picked up by the next if statement.
3765 if (LHS.getValueType() == MVT::f128) {
3766 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3768 // If softenSetCCOperands returned a scalar, use it.
3769 if (!RHS.getNode()) {
3770 assert(LHS.getValueType() == Op.getValueType() &&
3771 "Unexpected setcc expansion!");
3776 if (LHS.getValueType().isInteger()) {
3779 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3781 // Note that we inverted the condition above, so we reverse the order of
3782 // the true and false operands here. This will allow the setcc to be
3783 // matched to a single CSINC instruction.
3784 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3787 // Now we know we're dealing with FP values.
3788 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3790 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3791 // and do the comparison.
3792 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3794 AArch64CC::CondCode CC1, CC2;
3795 changeFPCCToAArch64CC(CC, CC1, CC2);
3796 if (CC2 == AArch64CC::AL) {
3797 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3798 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3800 // Note that we inverted the condition above, so we reverse the order of
3801 // the true and false operands here. This will allow the setcc to be
3802 // matched to a single CSINC instruction.
3803 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3805 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3806 // totally clean. Some of them require two CSELs to implement. As is in
3807 // this case, we emit the first CSEL and then emit a second using the output
3808 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3810 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3811 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3813 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3815 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3816 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3820 /// A SELECT_CC operation is really some kind of max or min if both values being
3821 /// compared are, in some sense, equal to the results in either case. However,
3822 /// it is permissible to compare f32 values and produce directly extended f64
3825 /// Extending the comparison operands would also be allowed, but is less likely
3826 /// to happen in practice since their use is right here. Note that truncate
3827 /// operations would *not* be semantically equivalent.
3828 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3830 return (Cmp.getValueType() == MVT::f32 ||
3831 Cmp.getValueType() == MVT::f64);
3833 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3834 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3835 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3836 Result.getValueType() == MVT::f64) {
3838 APFloat CmpVal = CCmp->getValueAPF();
3839 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3840 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3843 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3846 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3847 SDValue RHS, SDValue TVal,
3848 SDValue FVal, SDLoc dl,
3849 SelectionDAG &DAG) const {
3850 // Handle f128 first, because it will result in a comparison of some RTLIB
3851 // call result against zero.
3852 if (LHS.getValueType() == MVT::f128) {
3853 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3855 // If softenSetCCOperands returned a scalar, we need to compare the result
3856 // against zero to select between true and false values.
3857 if (!RHS.getNode()) {
3858 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3863 // Handle integers first.
3864 if (LHS.getValueType().isInteger()) {
3865 assert((LHS.getValueType() == RHS.getValueType()) &&
3866 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3868 unsigned Opcode = AArch64ISD::CSEL;
3870 // If both the TVal and the FVal are constants, see if we can swap them in
3871 // order to for a CSINV or CSINC out of them.
3872 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3873 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3875 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3876 std::swap(TVal, FVal);
3877 std::swap(CTVal, CFVal);
3878 CC = ISD::getSetCCInverse(CC, true);
3879 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3880 std::swap(TVal, FVal);
3881 std::swap(CTVal, CFVal);
3882 CC = ISD::getSetCCInverse(CC, true);
3883 } else if (TVal.getOpcode() == ISD::XOR) {
3884 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3885 // with a CSINV rather than a CSEL.
3886 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3888 if (CVal && CVal->isAllOnesValue()) {
3889 std::swap(TVal, FVal);
3890 std::swap(CTVal, CFVal);
3891 CC = ISD::getSetCCInverse(CC, true);
3893 } else if (TVal.getOpcode() == ISD::SUB) {
3894 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3895 // that we can match with a CSNEG rather than a CSEL.
3896 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3898 if (CVal && CVal->isNullValue()) {
3899 std::swap(TVal, FVal);
3900 std::swap(CTVal, CFVal);
3901 CC = ISD::getSetCCInverse(CC, true);
3903 } else if (CTVal && CFVal) {
3904 const int64_t TrueVal = CTVal->getSExtValue();
3905 const int64_t FalseVal = CFVal->getSExtValue();
3908 // If both TVal and FVal are constants, see if FVal is the
3909 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3910 // instead of a CSEL in that case.
3911 if (TrueVal == ~FalseVal) {
3912 Opcode = AArch64ISD::CSINV;
3913 } else if (TrueVal == -FalseVal) {
3914 Opcode = AArch64ISD::CSNEG;
3915 } else if (TVal.getValueType() == MVT::i32) {
3916 // If our operands are only 32-bit wide, make sure we use 32-bit
3917 // arithmetic for the check whether we can use CSINC. This ensures that
3918 // the addition in the check will wrap around properly in case there is
3919 // an overflow (which would not be the case if we do the check with
3920 // 64-bit arithmetic).
3921 const uint32_t TrueVal32 = CTVal->getZExtValue();
3922 const uint32_t FalseVal32 = CFVal->getZExtValue();
3924 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3925 Opcode = AArch64ISD::CSINC;
3927 if (TrueVal32 > FalseVal32) {
3931 // 64-bit check whether we can use CSINC.
3932 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3933 Opcode = AArch64ISD::CSINC;
3935 if (TrueVal > FalseVal) {
3940 // Swap TVal and FVal if necessary.
3942 std::swap(TVal, FVal);
3943 std::swap(CTVal, CFVal);
3944 CC = ISD::getSetCCInverse(CC, true);
3947 if (Opcode != AArch64ISD::CSEL) {
3948 // Drop FVal since we can get its value by simply inverting/negating
3955 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3957 EVT VT = TVal.getValueType();
3958 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3961 // Now we know we're dealing with FP values.
3962 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3963 assert(LHS.getValueType() == RHS.getValueType());
3964 EVT VT = TVal.getValueType();
3965 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3967 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3968 // clean. Some of them require two CSELs to implement.
3969 AArch64CC::CondCode CC1, CC2;
3970 changeFPCCToAArch64CC(CC, CC1, CC2);
3971 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3972 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3974 // If we need a second CSEL, emit it, using the output of the first as the
3975 // RHS. We're effectively OR'ing the two CC's together.
3976 if (CC2 != AArch64CC::AL) {
3977 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3978 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3981 // Otherwise, return the output of the first CSEL.
3985 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3986 SelectionDAG &DAG) const {
3987 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3988 SDValue LHS = Op.getOperand(0);
3989 SDValue RHS = Op.getOperand(1);
3990 SDValue TVal = Op.getOperand(2);
3991 SDValue FVal = Op.getOperand(3);
3993 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3996 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3997 SelectionDAG &DAG) const {
3998 SDValue CCVal = Op->getOperand(0);
3999 SDValue TVal = Op->getOperand(1);
4000 SDValue FVal = Op->getOperand(2);
4003 unsigned Opc = CCVal.getOpcode();
4004 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4006 if (CCVal.getResNo() == 1 &&
4007 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4008 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4009 // Only lower legal XALUO ops.
4010 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4013 AArch64CC::CondCode OFCC;
4014 SDValue Value, Overflow;
4015 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4016 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4018 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4022 // Lower it the same way as we would lower a SELECT_CC node.
4025 if (CCVal.getOpcode() == ISD::SETCC) {
4026 LHS = CCVal.getOperand(0);
4027 RHS = CCVal.getOperand(1);
4028 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4031 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4034 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4037 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4038 SelectionDAG &DAG) const {
4039 // Jump table entries as PC relative offsets. No additional tweaking
4040 // is necessary here. Just get the address of the jump table.
4041 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4042 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4045 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4046 !Subtarget->isTargetMachO()) {
4047 const unsigned char MO_NC = AArch64II::MO_NC;
4049 AArch64ISD::WrapperLarge, DL, PtrVT,
4050 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
4051 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
4052 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
4053 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4054 AArch64II::MO_G0 | MO_NC));
4058 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
4059 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4060 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4061 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4062 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4065 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4066 SelectionDAG &DAG) const {
4067 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4068 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4071 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4072 // Use the GOT for the large code model on iOS.
4073 if (Subtarget->isTargetMachO()) {
4074 SDValue GotAddr = DAG.getTargetConstantPool(
4075 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4077 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
4080 const unsigned char MO_NC = AArch64II::MO_NC;
4082 AArch64ISD::WrapperLarge, DL, PtrVT,
4083 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4084 CP->getOffset(), AArch64II::MO_G3),
4085 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4086 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
4087 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4088 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
4089 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4090 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
4092 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4093 // ELF, the only valid one on Darwin.
4095 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4096 CP->getOffset(), AArch64II::MO_PAGE);
4097 SDValue Lo = DAG.getTargetConstantPool(
4098 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4099 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4101 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4102 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4106 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4107 SelectionDAG &DAG) const {
4108 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4109 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4111 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4112 !Subtarget->isTargetMachO()) {
4113 const unsigned char MO_NC = AArch64II::MO_NC;
4115 AArch64ISD::WrapperLarge, DL, PtrVT,
4116 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
4117 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
4118 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
4119 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
4121 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
4122 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
4124 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4125 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4129 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4130 SelectionDAG &DAG) const {
4131 AArch64FunctionInfo *FuncInfo =
4132 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4135 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4136 getPointerTy(DAG.getDataLayout()));
4137 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4138 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4139 MachinePointerInfo(SV), false, false, 0);
4142 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4143 SelectionDAG &DAG) const {
4144 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4145 // Standard, section B.3.
4146 MachineFunction &MF = DAG.getMachineFunction();
4147 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4148 auto PtrVT = getPointerTy(DAG.getDataLayout());
4151 SDValue Chain = Op.getOperand(0);
4152 SDValue VAList = Op.getOperand(1);
4153 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4154 SmallVector<SDValue, 4> MemOps;
4156 // void *__stack at offset 0
4157 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4158 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4159 MachinePointerInfo(SV), false, false, 8));
4161 // void *__gr_top at offset 8
4162 int GPRSize = FuncInfo->getVarArgsGPRSize();
4164 SDValue GRTop, GRTopAddr;
4167 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4169 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4170 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4171 DAG.getConstant(GPRSize, DL, PtrVT));
4173 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4174 MachinePointerInfo(SV, 8), false, false, 8));
4177 // void *__vr_top at offset 16
4178 int FPRSize = FuncInfo->getVarArgsFPRSize();
4180 SDValue VRTop, VRTopAddr;
4181 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4182 DAG.getConstant(16, DL, PtrVT));
4184 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4185 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4186 DAG.getConstant(FPRSize, DL, PtrVT));
4188 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4189 MachinePointerInfo(SV, 16), false, false, 8));
4192 // int __gr_offs at offset 24
4193 SDValue GROffsAddr =
4194 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4195 MemOps.push_back(DAG.getStore(Chain, DL,
4196 DAG.getConstant(-GPRSize, DL, MVT::i32),
4197 GROffsAddr, MachinePointerInfo(SV, 24), false,
4200 // int __vr_offs at offset 28
4201 SDValue VROffsAddr =
4202 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4203 MemOps.push_back(DAG.getStore(Chain, DL,
4204 DAG.getConstant(-FPRSize, DL, MVT::i32),
4205 VROffsAddr, MachinePointerInfo(SV, 28), false,
4208 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4211 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4212 SelectionDAG &DAG) const {
4213 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
4214 : LowerAAPCS_VASTART(Op, DAG);
4217 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4218 SelectionDAG &DAG) const {
4219 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4222 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
4223 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4224 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4226 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4228 DAG.getConstant(VaListSize, DL, MVT::i32),
4229 8, false, false, false, MachinePointerInfo(DestSV),
4230 MachinePointerInfo(SrcSV));
4233 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4234 assert(Subtarget->isTargetDarwin() &&
4235 "automatic va_arg instruction only works on Darwin");
4237 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4238 EVT VT = Op.getValueType();
4240 SDValue Chain = Op.getOperand(0);
4241 SDValue Addr = Op.getOperand(1);
4242 unsigned Align = Op.getConstantOperandVal(3);
4243 auto PtrVT = getPointerTy(DAG.getDataLayout());
4245 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V),
4246 false, false, false, 0);
4247 Chain = VAList.getValue(1);
4250 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4251 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4252 DAG.getConstant(Align - 1, DL, PtrVT));
4253 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4254 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4257 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4258 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4260 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4261 // up to 64 bits. At the very least, we have to increase the striding of the
4262 // vaargs list to match this, and for FP values we need to introduce
4263 // FP_ROUND nodes as well.
4264 if (VT.isInteger() && !VT.isVector())
4266 bool NeedFPTrunc = false;
4267 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4272 // Increment the pointer, VAList, to the next vaarg
4273 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4274 DAG.getConstant(ArgSize, DL, PtrVT));
4275 // Store the incremented VAList to the legalized pointer
4276 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4279 // Load the actual argument out of the pointer VAList
4281 // Load the value as an f64.
4282 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4283 MachinePointerInfo(), false, false, false, 0);
4284 // Round the value down to an f32.
4285 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4286 DAG.getIntPtrConstant(1, DL));
4287 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4288 // Merge the rounded value with the chain output of the load.
4289 return DAG.getMergeValues(Ops, DL);
4292 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4296 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4297 SelectionDAG &DAG) const {
4298 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4299 MFI->setFrameAddressIsTaken(true);
4301 EVT VT = Op.getValueType();
4303 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4305 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4307 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4308 MachinePointerInfo(), false, false, false, 0);
4312 // FIXME? Maybe this could be a TableGen attribute on some registers and
4313 // this table could be generated automatically from RegInfo.
4314 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4315 SelectionDAG &DAG) const {
4316 unsigned Reg = StringSwitch<unsigned>(RegName)
4317 .Case("sp", AArch64::SP)
4321 report_fatal_error(Twine("Invalid register name \""
4322 + StringRef(RegName) + "\"."));
4325 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4326 SelectionDAG &DAG) const {
4327 MachineFunction &MF = DAG.getMachineFunction();
4328 MachineFrameInfo *MFI = MF.getFrameInfo();
4329 MFI->setReturnAddressIsTaken(true);
4331 EVT VT = Op.getValueType();
4333 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4335 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4336 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4337 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4338 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4339 MachinePointerInfo(), false, false, false, 0);
4342 // Return LR, which contains the return address. Mark it an implicit live-in.
4343 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4344 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4347 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4348 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4349 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4350 SelectionDAG &DAG) const {
4351 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4352 EVT VT = Op.getValueType();
4353 unsigned VTBits = VT.getSizeInBits();
4355 SDValue ShOpLo = Op.getOperand(0);
4356 SDValue ShOpHi = Op.getOperand(1);
4357 SDValue ShAmt = Op.getOperand(2);
4359 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4361 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4363 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4364 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4365 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4366 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4367 DAG.getConstant(VTBits, dl, MVT::i64));
4368 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4370 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4371 ISD::SETGE, dl, DAG);
4372 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4374 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4375 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4377 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4379 // AArch64 shifts larger than the register width are wrapped rather than
4380 // clamped, so we can't just emit "hi >> x".
4381 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4382 SDValue TrueValHi = Opc == ISD::SRA
4383 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4384 DAG.getConstant(VTBits - 1, dl,
4386 : DAG.getConstant(0, dl, VT);
4388 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4390 SDValue Ops[2] = { Lo, Hi };
4391 return DAG.getMergeValues(Ops, dl);
4394 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4395 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4396 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4397 SelectionDAG &DAG) const {
4398 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4399 EVT VT = Op.getValueType();
4400 unsigned VTBits = VT.getSizeInBits();
4402 SDValue ShOpLo = Op.getOperand(0);
4403 SDValue ShOpHi = Op.getOperand(1);
4404 SDValue ShAmt = Op.getOperand(2);
4407 assert(Op.getOpcode() == ISD::SHL_PARTS);
4408 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4409 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4410 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4411 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4412 DAG.getConstant(VTBits, dl, MVT::i64));
4413 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4414 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4416 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4418 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4419 ISD::SETGE, dl, DAG);
4420 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4422 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4424 // AArch64 shifts of larger than register sizes are wrapped rather than
4425 // clamped, so we can't just emit "lo << a" if a is too big.
4426 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4427 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4429 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4431 SDValue Ops[2] = { Lo, Hi };
4432 return DAG.getMergeValues(Ops, dl);
4435 bool AArch64TargetLowering::isOffsetFoldingLegal(
4436 const GlobalAddressSDNode *GA) const {
4437 // The AArch64 target doesn't support folding offsets into global addresses.
4441 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4442 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4443 // FIXME: We should be able to handle f128 as well with a clever lowering.
4444 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4448 return AArch64_AM::getFP64Imm(Imm) != -1;
4449 else if (VT == MVT::f32)
4450 return AArch64_AM::getFP32Imm(Imm) != -1;
4454 //===----------------------------------------------------------------------===//
4455 // AArch64 Optimization Hooks
4456 //===----------------------------------------------------------------------===//
4458 //===----------------------------------------------------------------------===//
4459 // AArch64 Inline Assembly Support
4460 //===----------------------------------------------------------------------===//
4462 // Table of Constraints
4463 // TODO: This is the current set of constraints supported by ARM for the
4464 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4466 // r - A general register
4467 // w - An FP/SIMD register of some size in the range v0-v31
4468 // x - An FP/SIMD register of some size in the range v0-v15
4469 // I - Constant that can be used with an ADD instruction
4470 // J - Constant that can be used with a SUB instruction
4471 // K - Constant that can be used with a 32-bit logical instruction
4472 // L - Constant that can be used with a 64-bit logical instruction
4473 // M - Constant that can be used as a 32-bit MOV immediate
4474 // N - Constant that can be used as a 64-bit MOV immediate
4475 // Q - A memory reference with base register and no offset
4476 // S - A symbolic address
4477 // Y - Floating point constant zero
4478 // Z - Integer constant zero
4480 // Note that general register operands will be output using their 64-bit x
4481 // register name, whatever the size of the variable, unless the asm operand
4482 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4483 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4486 /// getConstraintType - Given a constraint letter, return the type of
4487 /// constraint it is for this target.
4488 AArch64TargetLowering::ConstraintType
4489 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4490 if (Constraint.size() == 1) {
4491 switch (Constraint[0]) {
4498 return C_RegisterClass;
4499 // An address with a single base register. Due to the way we
4500 // currently handle addresses it is the same as 'r'.
4505 return TargetLowering::getConstraintType(Constraint);
4508 /// Examine constraint type and operand type and determine a weight value.
4509 /// This object must already have been set up with the operand type
4510 /// and the current alternative constraint selected.
4511 TargetLowering::ConstraintWeight
4512 AArch64TargetLowering::getSingleConstraintMatchWeight(
4513 AsmOperandInfo &info, const char *constraint) const {
4514 ConstraintWeight weight = CW_Invalid;
4515 Value *CallOperandVal = info.CallOperandVal;
4516 // If we don't have a value, we can't do a match,
4517 // but allow it at the lowest weight.
4518 if (!CallOperandVal)
4520 Type *type = CallOperandVal->getType();
4521 // Look at the constraint type.
4522 switch (*constraint) {
4524 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4528 if (type->isFloatingPointTy() || type->isVectorTy())
4529 weight = CW_Register;
4532 weight = CW_Constant;
4538 std::pair<unsigned, const TargetRegisterClass *>
4539 AArch64TargetLowering::getRegForInlineAsmConstraint(
4540 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4541 if (Constraint.size() == 1) {
4542 switch (Constraint[0]) {
4544 if (VT.getSizeInBits() == 64)
4545 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4546 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4549 return std::make_pair(0U, &AArch64::FPR32RegClass);
4550 if (VT.getSizeInBits() == 64)
4551 return std::make_pair(0U, &AArch64::FPR64RegClass);
4552 if (VT.getSizeInBits() == 128)
4553 return std::make_pair(0U, &AArch64::FPR128RegClass);
4555 // The instructions that this constraint is designed for can
4556 // only take 128-bit registers so just use that regclass.
4558 if (VT.getSizeInBits() == 128)
4559 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4563 if (StringRef("{cc}").equals_lower(Constraint))
4564 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4566 // Use the default implementation in TargetLowering to convert the register
4567 // constraint into a member of a register class.
4568 std::pair<unsigned, const TargetRegisterClass *> Res;
4569 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4571 // Not found as a standard register?
4573 unsigned Size = Constraint.size();
4574 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4575 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4577 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4578 if (!Failed && RegNo >= 0 && RegNo <= 31) {
4579 // v0 - v31 are aliases of q0 - q31.
4580 // By default we'll emit v0-v31 for this unless there's a modifier where
4581 // we'll emit the correct register as well.
4582 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4583 Res.second = &AArch64::FPR128RegClass;
4591 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4592 /// vector. If it is invalid, don't add anything to Ops.
4593 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4594 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4595 SelectionDAG &DAG) const {
4598 // Currently only support length 1 constraints.
4599 if (Constraint.length() != 1)
4602 char ConstraintLetter = Constraint[0];
4603 switch (ConstraintLetter) {
4607 // This set of constraints deal with valid constants for various instructions.
4608 // Validate and return a target constant for them if we can.
4610 // 'z' maps to xzr or wzr so it needs an input of 0.
4611 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4612 if (!C || C->getZExtValue() != 0)
4615 if (Op.getValueType() == MVT::i64)
4616 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4618 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4628 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4632 // Grab the value and do some validation.
4633 uint64_t CVal = C->getZExtValue();
4634 switch (ConstraintLetter) {
4635 // The I constraint applies only to simple ADD or SUB immediate operands:
4636 // i.e. 0 to 4095 with optional shift by 12
4637 // The J constraint applies only to ADD or SUB immediates that would be
4638 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4639 // instruction [or vice versa], in other words -1 to -4095 with optional
4640 // left shift by 12.
4642 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4646 uint64_t NVal = -C->getSExtValue();
4647 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4648 CVal = C->getSExtValue();
4653 // The K and L constraints apply *only* to logical immediates, including
4654 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4655 // been removed and MOV should be used). So these constraints have to
4656 // distinguish between bit patterns that are valid 32-bit or 64-bit
4657 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4658 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4661 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4665 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4668 // The M and N constraints are a superset of K and L respectively, for use
4669 // with the MOV (immediate) alias. As well as the logical immediates they
4670 // also match 32 or 64-bit immediates that can be loaded either using a
4671 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4672 // (M) or 64-bit 0x1234000000000000 (N) etc.
4673 // As a note some of this code is liberally stolen from the asm parser.
4675 if (!isUInt<32>(CVal))
4677 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4679 if ((CVal & 0xFFFF) == CVal)
4681 if ((CVal & 0xFFFF0000ULL) == CVal)
4683 uint64_t NCVal = ~(uint32_t)CVal;
4684 if ((NCVal & 0xFFFFULL) == NCVal)
4686 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4691 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4693 if ((CVal & 0xFFFFULL) == CVal)
4695 if ((CVal & 0xFFFF0000ULL) == CVal)
4697 if ((CVal & 0xFFFF00000000ULL) == CVal)
4699 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4701 uint64_t NCVal = ~CVal;
4702 if ((NCVal & 0xFFFFULL) == NCVal)
4704 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4706 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4708 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4716 // All assembler immediates are 64-bit integers.
4717 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4721 if (Result.getNode()) {
4722 Ops.push_back(Result);
4726 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4729 //===----------------------------------------------------------------------===//
4730 // AArch64 Advanced SIMD Support
4731 //===----------------------------------------------------------------------===//
4733 /// WidenVector - Given a value in the V64 register class, produce the
4734 /// equivalent value in the V128 register class.
4735 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4736 EVT VT = V64Reg.getValueType();
4737 unsigned NarrowSize = VT.getVectorNumElements();
4738 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4739 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4742 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4743 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4746 /// getExtFactor - Determine the adjustment factor for the position when
4747 /// generating an "extract from vector registers" instruction.
4748 static unsigned getExtFactor(SDValue &V) {
4749 EVT EltType = V.getValueType().getVectorElementType();
4750 return EltType.getSizeInBits() / 8;
4753 /// NarrowVector - Given a value in the V128 register class, produce the
4754 /// equivalent value in the V64 register class.
4755 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4756 EVT VT = V128Reg.getValueType();
4757 unsigned WideSize = VT.getVectorNumElements();
4758 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4759 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4762 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4765 // Gather data to see if the operation can be modelled as a
4766 // shuffle in combination with VEXTs.
4767 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4768 SelectionDAG &DAG) const {
4769 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4771 EVT VT = Op.getValueType();
4772 unsigned NumElts = VT.getVectorNumElements();
4774 struct ShuffleSourceInfo {
4779 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4780 // be compatible with the shuffle we intend to construct. As a result
4781 // ShuffleVec will be some sliding window into the original Vec.
4784 // Code should guarantee that element i in Vec starts at element "WindowBase
4785 // + i * WindowScale in ShuffleVec".
4789 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4790 ShuffleSourceInfo(SDValue Vec)
4791 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4795 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4797 SmallVector<ShuffleSourceInfo, 2> Sources;
4798 for (unsigned i = 0; i < NumElts; ++i) {
4799 SDValue V = Op.getOperand(i);
4800 if (V.getOpcode() == ISD::UNDEF)
4802 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4803 // A shuffle can only come from building a vector from various
4804 // elements of other vectors.
4808 // Add this element source to the list if it's not already there.
4809 SDValue SourceVec = V.getOperand(0);
4810 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4811 if (Source == Sources.end())
4812 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4814 // Update the minimum and maximum lane number seen.
4815 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4816 Source->MinElt = std::min(Source->MinElt, EltNo);
4817 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4820 // Currently only do something sane when at most two source vectors
4822 if (Sources.size() > 2)
4825 // Find out the smallest element size among result and two sources, and use
4826 // it as element size to build the shuffle_vector.
4827 EVT SmallestEltTy = VT.getVectorElementType();
4828 for (auto &Source : Sources) {
4829 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4830 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4831 SmallestEltTy = SrcEltTy;
4834 unsigned ResMultiplier =
4835 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4836 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4837 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4839 // If the source vector is too wide or too narrow, we may nevertheless be able
4840 // to construct a compatible shuffle either by concatenating it with UNDEF or
4841 // extracting a suitable range of elements.
4842 for (auto &Src : Sources) {
4843 EVT SrcVT = Src.ShuffleVec.getValueType();
4845 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4848 // This stage of the search produces a source with the same element type as
4849 // the original, but with a total width matching the BUILD_VECTOR output.
4850 EVT EltVT = SrcVT.getVectorElementType();
4851 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4852 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4854 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4855 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4856 // We can pad out the smaller vector for free, so if it's part of a
4859 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4860 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4864 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4866 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4867 // Span too large for a VEXT to cope
4871 if (Src.MinElt >= NumSrcElts) {
4872 // The extraction can just take the second half
4874 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4875 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4876 Src.WindowBase = -NumSrcElts;
4877 } else if (Src.MaxElt < NumSrcElts) {
4878 // The extraction can just take the first half
4880 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4881 DAG.getConstant(0, dl, MVT::i64));
4883 // An actual VEXT is needed
4885 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4886 DAG.getConstant(0, dl, MVT::i64));
4888 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4889 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4890 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4892 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4894 DAG.getConstant(Imm, dl, MVT::i32));
4895 Src.WindowBase = -Src.MinElt;
4899 // Another possible incompatibility occurs from the vector element types. We
4900 // can fix this by bitcasting the source vectors to the same type we intend
4902 for (auto &Src : Sources) {
4903 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4904 if (SrcEltTy == SmallestEltTy)
4906 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4907 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4908 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4909 Src.WindowBase *= Src.WindowScale;
4912 // Final sanity check before we try to actually produce a shuffle.
4914 for (auto Src : Sources)
4915 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4918 // The stars all align, our next step is to produce the mask for the shuffle.
4919 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4920 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4921 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4922 SDValue Entry = Op.getOperand(i);
4923 if (Entry.getOpcode() == ISD::UNDEF)
4926 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4927 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4929 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4930 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4932 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4933 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4934 VT.getVectorElementType().getSizeInBits());
4935 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4937 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4938 // starting at the appropriate offset.
4939 int *LaneMask = &Mask[i * ResMultiplier];
4941 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4942 ExtractBase += NumElts * (Src - Sources.begin());
4943 for (int j = 0; j < LanesDefined; ++j)
4944 LaneMask[j] = ExtractBase + j;
4947 // Final check before we try to produce nonsense...
4948 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4951 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4952 for (unsigned i = 0; i < Sources.size(); ++i)
4953 ShuffleOps[i] = Sources[i].ShuffleVec;
4955 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4956 ShuffleOps[1], &Mask[0]);
4957 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4960 // check if an EXT instruction can handle the shuffle mask when the
4961 // vector sources of the shuffle are the same.
4962 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4963 unsigned NumElts = VT.getVectorNumElements();
4965 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4971 // If this is a VEXT shuffle, the immediate value is the index of the first
4972 // element. The other shuffle indices must be the successive elements after
4974 unsigned ExpectedElt = Imm;
4975 for (unsigned i = 1; i < NumElts; ++i) {
4976 // Increment the expected index. If it wraps around, just follow it
4977 // back to index zero and keep going.
4979 if (ExpectedElt == NumElts)
4983 continue; // ignore UNDEF indices
4984 if (ExpectedElt != static_cast<unsigned>(M[i]))
4991 // check if an EXT instruction can handle the shuffle mask when the
4992 // vector sources of the shuffle are different.
4993 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4995 // Look for the first non-undef element.
4996 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4997 [](int Elt) {return Elt >= 0;});
4999 // Benefit form APInt to handle overflow when calculating expected element.
5000 unsigned NumElts = VT.getVectorNumElements();
5001 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
5002 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
5003 // The following shuffle indices must be the successive elements after the
5004 // first real element.
5005 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5006 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5007 if (FirstWrongElt != M.end())
5010 // The index of an EXT is the first element if it is not UNDEF.
5011 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5012 // value of the first element. E.g.
5013 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5014 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5015 // ExpectedElt is the last mask index plus 1.
5016 Imm = ExpectedElt.getZExtValue();
5018 // There are two difference cases requiring to reverse input vectors.
5019 // For example, for vector <4 x i32> we have the following cases,
5020 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5021 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5022 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5023 // to reverse two input vectors.
5032 /// isREVMask - Check if a vector shuffle corresponds to a REV
5033 /// instruction with the specified blocksize. (The order of the elements
5034 /// within each block of the vector is reversed.)
5035 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5036 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
5037 "Only possible block sizes for REV are: 16, 32, 64");
5039 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5043 unsigned NumElts = VT.getVectorNumElements();
5044 unsigned BlockElts = M[0] + 1;
5045 // If the first shuffle index is UNDEF, be optimistic.
5047 BlockElts = BlockSize / EltSz;
5049 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5052 for (unsigned i = 0; i < NumElts; ++i) {
5054 continue; // ignore UNDEF indices
5055 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5062 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5063 unsigned NumElts = VT.getVectorNumElements();
5064 WhichResult = (M[0] == 0 ? 0 : 1);
5065 unsigned Idx = WhichResult * NumElts / 2;
5066 for (unsigned i = 0; i != NumElts; i += 2) {
5067 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5068 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5076 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5077 unsigned NumElts = VT.getVectorNumElements();
5078 WhichResult = (M[0] == 0 ? 0 : 1);
5079 for (unsigned i = 0; i != NumElts; ++i) {
5081 continue; // ignore UNDEF indices
5082 if ((unsigned)M[i] != 2 * i + WhichResult)
5089 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5090 unsigned NumElts = VT.getVectorNumElements();
5091 WhichResult = (M[0] == 0 ? 0 : 1);
5092 for (unsigned i = 0; i < NumElts; i += 2) {
5093 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5094 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5100 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5101 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5102 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5103 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5104 unsigned NumElts = VT.getVectorNumElements();
5105 WhichResult = (M[0] == 0 ? 0 : 1);
5106 unsigned Idx = WhichResult * NumElts / 2;
5107 for (unsigned i = 0; i != NumElts; i += 2) {
5108 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5109 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5117 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5118 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5119 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5120 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5121 unsigned Half = VT.getVectorNumElements() / 2;
5122 WhichResult = (M[0] == 0 ? 0 : 1);
5123 for (unsigned j = 0; j != 2; ++j) {
5124 unsigned Idx = WhichResult;
5125 for (unsigned i = 0; i != Half; ++i) {
5126 int MIdx = M[i + j * Half];
5127 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5136 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5137 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5138 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5139 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5140 unsigned NumElts = VT.getVectorNumElements();
5141 WhichResult = (M[0] == 0 ? 0 : 1);
5142 for (unsigned i = 0; i < NumElts; i += 2) {
5143 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5144 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5150 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5151 bool &DstIsLeft, int &Anomaly) {
5152 if (M.size() != static_cast<size_t>(NumInputElements))
5155 int NumLHSMatch = 0, NumRHSMatch = 0;
5156 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5158 for (int i = 0; i < NumInputElements; ++i) {
5168 LastLHSMismatch = i;
5170 if (M[i] == i + NumInputElements)
5173 LastRHSMismatch = i;
5176 if (NumLHSMatch == NumInputElements - 1) {
5178 Anomaly = LastLHSMismatch;
5180 } else if (NumRHSMatch == NumInputElements - 1) {
5182 Anomaly = LastRHSMismatch;
5189 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5190 if (VT.getSizeInBits() != 128)
5193 unsigned NumElts = VT.getVectorNumElements();
5195 for (int I = 0, E = NumElts / 2; I != E; I++) {
5200 int Offset = NumElts / 2;
5201 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5202 if (Mask[I] != I + SplitLHS * Offset)
5209 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5211 EVT VT = Op.getValueType();
5212 SDValue V0 = Op.getOperand(0);
5213 SDValue V1 = Op.getOperand(1);
5214 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5216 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5217 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5220 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
5222 if (!isConcatMask(Mask, VT, SplitV0))
5225 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5226 VT.getVectorNumElements() / 2);
5228 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5229 DAG.getConstant(0, DL, MVT::i64));
5231 if (V1.getValueType().getSizeInBits() == 128) {
5232 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5233 DAG.getConstant(0, DL, MVT::i64));
5235 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5238 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5239 /// the specified operations to build the shuffle.
5240 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5241 SDValue RHS, SelectionDAG &DAG,
5243 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5244 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5245 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5248 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5257 OP_VUZPL, // VUZP, left result
5258 OP_VUZPR, // VUZP, right result
5259 OP_VZIPL, // VZIP, left result
5260 OP_VZIPR, // VZIP, right result
5261 OP_VTRNL, // VTRN, left result
5262 OP_VTRNR // VTRN, right result
5265 if (OpNum == OP_COPY) {
5266 if (LHSID == (1 * 9 + 2) * 9 + 3)
5268 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5272 SDValue OpLHS, OpRHS;
5273 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5274 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5275 EVT VT = OpLHS.getValueType();
5279 llvm_unreachable("Unknown shuffle opcode!");
5281 // VREV divides the vector in half and swaps within the half.
5282 if (VT.getVectorElementType() == MVT::i32 ||
5283 VT.getVectorElementType() == MVT::f32)
5284 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5285 // vrev <4 x i16> -> REV32
5286 if (VT.getVectorElementType() == MVT::i16 ||
5287 VT.getVectorElementType() == MVT::f16)
5288 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5289 // vrev <4 x i8> -> REV16
5290 assert(VT.getVectorElementType() == MVT::i8);
5291 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5296 EVT EltTy = VT.getVectorElementType();
5298 if (EltTy == MVT::i8)
5299 Opcode = AArch64ISD::DUPLANE8;
5300 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5301 Opcode = AArch64ISD::DUPLANE16;
5302 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5303 Opcode = AArch64ISD::DUPLANE32;
5304 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5305 Opcode = AArch64ISD::DUPLANE64;
5307 llvm_unreachable("Invalid vector element type?");
5309 if (VT.getSizeInBits() == 64)
5310 OpLHS = WidenVector(OpLHS, DAG);
5311 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5312 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5317 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5318 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5319 DAG.getConstant(Imm, dl, MVT::i32));
5322 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5325 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5328 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5331 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5334 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5337 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5342 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5343 SelectionDAG &DAG) {
5344 // Check to see if we can use the TBL instruction.
5345 SDValue V1 = Op.getOperand(0);
5346 SDValue V2 = Op.getOperand(1);
5349 EVT EltVT = Op.getValueType().getVectorElementType();
5350 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5352 SmallVector<SDValue, 8> TBLMask;
5353 for (int Val : ShuffleMask) {
5354 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5355 unsigned Offset = Byte + Val * BytesPerElt;
5356 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5360 MVT IndexVT = MVT::v8i8;
5361 unsigned IndexLen = 8;
5362 if (Op.getValueType().getSizeInBits() == 128) {
5363 IndexVT = MVT::v16i8;
5367 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5368 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5371 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5373 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5374 Shuffle = DAG.getNode(
5375 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5376 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5377 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5378 makeArrayRef(TBLMask.data(), IndexLen)));
5380 if (IndexLen == 8) {
5381 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5382 Shuffle = DAG.getNode(
5383 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5384 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5385 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5386 makeArrayRef(TBLMask.data(), IndexLen)));
5388 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5389 // cannot currently represent the register constraints on the input
5391 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5392 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5393 // &TBLMask[0], IndexLen));
5394 Shuffle = DAG.getNode(
5395 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5396 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5398 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5399 makeArrayRef(TBLMask.data(), IndexLen)));
5402 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5405 static unsigned getDUPLANEOp(EVT EltType) {
5406 if (EltType == MVT::i8)
5407 return AArch64ISD::DUPLANE8;
5408 if (EltType == MVT::i16 || EltType == MVT::f16)
5409 return AArch64ISD::DUPLANE16;
5410 if (EltType == MVT::i32 || EltType == MVT::f32)
5411 return AArch64ISD::DUPLANE32;
5412 if (EltType == MVT::i64 || EltType == MVT::f64)
5413 return AArch64ISD::DUPLANE64;
5415 llvm_unreachable("Invalid vector element type?");
5418 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5419 SelectionDAG &DAG) const {
5421 EVT VT = Op.getValueType();
5423 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5425 // Convert shuffles that are directly supported on NEON to target-specific
5426 // DAG nodes, instead of keeping them as shuffles and matching them again
5427 // during code selection. This is more efficient and avoids the possibility
5428 // of inconsistencies between legalization and selection.
5429 ArrayRef<int> ShuffleMask = SVN->getMask();
5431 SDValue V1 = Op.getOperand(0);
5432 SDValue V2 = Op.getOperand(1);
5434 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5435 V1.getValueType().getSimpleVT())) {
5436 int Lane = SVN->getSplatIndex();
5437 // If this is undef splat, generate it via "just" vdup, if possible.
5441 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5442 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5444 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5445 // constant. If so, we can just reference the lane's definition directly.
5446 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5447 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5448 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5450 // Otherwise, duplicate from the lane of the input vector.
5451 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5453 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5454 // to make a vector of the same size as this SHUFFLE. We can ignore the
5455 // extract entirely, and canonicalise the concat using WidenVector.
5456 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5457 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5458 V1 = V1.getOperand(0);
5459 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5460 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5461 Lane -= Idx * VT.getVectorNumElements() / 2;
5462 V1 = WidenVector(V1.getOperand(Idx), DAG);
5463 } else if (VT.getSizeInBits() == 64)
5464 V1 = WidenVector(V1, DAG);
5466 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5469 if (isREVMask(ShuffleMask, VT, 64))
5470 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5471 if (isREVMask(ShuffleMask, VT, 32))
5472 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5473 if (isREVMask(ShuffleMask, VT, 16))
5474 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5476 bool ReverseEXT = false;
5478 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5481 Imm *= getExtFactor(V1);
5482 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5483 DAG.getConstant(Imm, dl, MVT::i32));
5484 } else if (V2->getOpcode() == ISD::UNDEF &&
5485 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5486 Imm *= getExtFactor(V1);
5487 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5488 DAG.getConstant(Imm, dl, MVT::i32));
5491 unsigned WhichResult;
5492 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5493 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5494 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5496 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5497 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5498 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5500 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5501 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5502 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5505 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5506 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5507 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5509 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5510 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5511 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5513 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5514 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5515 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5518 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5519 if (Concat.getNode())
5524 int NumInputElements = V1.getValueType().getVectorNumElements();
5525 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5526 SDValue DstVec = DstIsLeft ? V1 : V2;
5527 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5529 SDValue SrcVec = V1;
5530 int SrcLane = ShuffleMask[Anomaly];
5531 if (SrcLane >= NumInputElements) {
5533 SrcLane -= VT.getVectorNumElements();
5535 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5537 EVT ScalarVT = VT.getVectorElementType();
5539 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5540 ScalarVT = MVT::i32;
5543 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5544 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5548 // If the shuffle is not directly supported and it has 4 elements, use
5549 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5550 unsigned NumElts = VT.getVectorNumElements();
5552 unsigned PFIndexes[4];
5553 for (unsigned i = 0; i != 4; ++i) {
5554 if (ShuffleMask[i] < 0)
5557 PFIndexes[i] = ShuffleMask[i];
5560 // Compute the index in the perfect shuffle table.
5561 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5562 PFIndexes[2] * 9 + PFIndexes[3];
5563 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5564 unsigned Cost = (PFEntry >> 30);
5567 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5570 return GenerateTBL(Op, ShuffleMask, DAG);
5573 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5575 EVT VT = BVN->getValueType(0);
5576 APInt SplatBits, SplatUndef;
5577 unsigned SplatBitSize;
5579 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5580 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5582 for (unsigned i = 0; i < NumSplats; ++i) {
5583 CnstBits <<= SplatBitSize;
5584 UndefBits <<= SplatBitSize;
5585 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5586 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5595 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5596 SelectionDAG &DAG) const {
5597 BuildVectorSDNode *BVN =
5598 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5599 SDValue LHS = Op.getOperand(0);
5601 EVT VT = Op.getValueType();
5606 APInt CnstBits(VT.getSizeInBits(), 0);
5607 APInt UndefBits(VT.getSizeInBits(), 0);
5608 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5609 // We only have BIC vector immediate instruction, which is and-not.
5610 CnstBits = ~CnstBits;
5612 // We make use of a little bit of goto ickiness in order to avoid having to
5613 // duplicate the immediate matching logic for the undef toggled case.
5614 bool SecondTry = false;
5617 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5618 CnstBits = CnstBits.zextOrTrunc(64);
5619 uint64_t CnstVal = CnstBits.getZExtValue();
5621 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5622 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5623 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5624 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5625 DAG.getConstant(CnstVal, dl, MVT::i32),
5626 DAG.getConstant(0, dl, MVT::i32));
5627 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5630 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5631 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5632 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5633 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5634 DAG.getConstant(CnstVal, dl, MVT::i32),
5635 DAG.getConstant(8, dl, MVT::i32));
5636 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5639 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5640 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5641 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5642 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5643 DAG.getConstant(CnstVal, dl, MVT::i32),
5644 DAG.getConstant(16, dl, MVT::i32));
5645 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5648 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5649 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5650 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5651 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5652 DAG.getConstant(CnstVal, dl, MVT::i32),
5653 DAG.getConstant(24, dl, MVT::i32));
5654 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5657 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5658 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5659 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5660 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5661 DAG.getConstant(CnstVal, dl, MVT::i32),
5662 DAG.getConstant(0, dl, MVT::i32));
5663 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5666 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5667 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5668 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5669 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5670 DAG.getConstant(CnstVal, dl, MVT::i32),
5671 DAG.getConstant(8, dl, MVT::i32));
5672 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5679 CnstBits = ~UndefBits;
5683 // We can always fall back to a non-immediate AND.
5688 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5689 // consists of only the same constant int value, returned in reference arg
5691 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5692 uint64_t &ConstVal) {
5693 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5696 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5699 EVT VT = Bvec->getValueType(0);
5700 unsigned NumElts = VT.getVectorNumElements();
5701 for (unsigned i = 1; i < NumElts; ++i)
5702 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5704 ConstVal = FirstElt->getZExtValue();
5708 static unsigned getIntrinsicID(const SDNode *N) {
5709 unsigned Opcode = N->getOpcode();
5712 return Intrinsic::not_intrinsic;
5713 case ISD::INTRINSIC_WO_CHAIN: {
5714 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5715 if (IID < Intrinsic::num_intrinsics)
5717 return Intrinsic::not_intrinsic;
5722 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5723 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5724 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5725 // Also, logical shift right -> sri, with the same structure.
5726 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5727 EVT VT = N->getValueType(0);
5734 // Is the first op an AND?
5735 const SDValue And = N->getOperand(0);
5736 if (And.getOpcode() != ISD::AND)
5739 // Is the second op an shl or lshr?
5740 SDValue Shift = N->getOperand(1);
5741 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5742 // or AArch64ISD::VLSHR vector, #shift
5743 unsigned ShiftOpc = Shift.getOpcode();
5744 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5746 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5748 // Is the shift amount constant?
5749 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5753 // Is the and mask vector all constant?
5755 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5758 // Is C1 == ~C2, taking into account how much one can shift elements of a
5760 uint64_t C2 = C2node->getZExtValue();
5761 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5762 if (C2 > ElemSizeInBits)
5764 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5765 if ((C1 & ElemMask) != (~C2 & ElemMask))
5768 SDValue X = And.getOperand(0);
5769 SDValue Y = Shift.getOperand(0);
5772 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5774 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5775 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5776 Shift.getOperand(1));
5778 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5779 DEBUG(N->dump(&DAG));
5780 DEBUG(dbgs() << "into: \n");
5781 DEBUG(ResultSLI->dump(&DAG));
5787 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5788 SelectionDAG &DAG) const {
5789 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5790 if (EnableAArch64SlrGeneration) {
5791 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5796 BuildVectorSDNode *BVN =
5797 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5798 SDValue LHS = Op.getOperand(1);
5800 EVT VT = Op.getValueType();
5802 // OR commutes, so try swapping the operands.
5804 LHS = Op.getOperand(0);
5805 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5810 APInt CnstBits(VT.getSizeInBits(), 0);
5811 APInt UndefBits(VT.getSizeInBits(), 0);
5812 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5813 // We make use of a little bit of goto ickiness in order to avoid having to
5814 // duplicate the immediate matching logic for the undef toggled case.
5815 bool SecondTry = false;
5818 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5819 CnstBits = CnstBits.zextOrTrunc(64);
5820 uint64_t CnstVal = CnstBits.getZExtValue();
5822 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5823 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5824 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5825 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5826 DAG.getConstant(CnstVal, dl, MVT::i32),
5827 DAG.getConstant(0, dl, MVT::i32));
5828 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5831 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5832 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5833 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5834 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5835 DAG.getConstant(CnstVal, dl, MVT::i32),
5836 DAG.getConstant(8, dl, MVT::i32));
5837 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5840 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5841 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5842 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5843 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5844 DAG.getConstant(CnstVal, dl, MVT::i32),
5845 DAG.getConstant(16, dl, MVT::i32));
5846 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5849 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5850 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5851 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5852 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5853 DAG.getConstant(CnstVal, dl, MVT::i32),
5854 DAG.getConstant(24, dl, MVT::i32));
5855 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5858 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5859 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5860 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5861 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5862 DAG.getConstant(CnstVal, dl, MVT::i32),
5863 DAG.getConstant(0, dl, MVT::i32));
5864 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5867 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5868 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5869 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5870 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5871 DAG.getConstant(CnstVal, dl, MVT::i32),
5872 DAG.getConstant(8, dl, MVT::i32));
5873 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5880 CnstBits = UndefBits;
5884 // We can always fall back to a non-immediate OR.
5889 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5890 // be truncated to fit element width.
5891 static SDValue NormalizeBuildVector(SDValue Op,
5892 SelectionDAG &DAG) {
5893 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5895 EVT VT = Op.getValueType();
5896 EVT EltTy= VT.getVectorElementType();
5898 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5901 SmallVector<SDValue, 16> Ops;
5902 for (SDValue Lane : Op->ops()) {
5903 if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
5904 APInt LowBits(EltTy.getSizeInBits(),
5905 CstLane->getZExtValue());
5906 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5908 Ops.push_back(Lane);
5910 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5913 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5914 SelectionDAG &DAG) const {
5916 EVT VT = Op.getValueType();
5917 Op = NormalizeBuildVector(Op, DAG);
5918 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5920 APInt CnstBits(VT.getSizeInBits(), 0);
5921 APInt UndefBits(VT.getSizeInBits(), 0);
5922 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5923 // We make use of a little bit of goto ickiness in order to avoid having to
5924 // duplicate the immediate matching logic for the undef toggled case.
5925 bool SecondTry = false;
5928 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5929 CnstBits = CnstBits.zextOrTrunc(64);
5930 uint64_t CnstVal = CnstBits.getZExtValue();
5932 // Certain magic vector constants (used to express things like NOT
5933 // and NEG) are passed through unmodified. This allows codegen patterns
5934 // for these operations to match. Special-purpose patterns will lower
5935 // these immediates to MOVIs if it proves necessary.
5936 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5939 // The many faces of MOVI...
5940 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5941 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5942 if (VT.getSizeInBits() == 128) {
5943 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5944 DAG.getConstant(CnstVal, dl, MVT::i32));
5945 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5948 // Support the V64 version via subregister insertion.
5949 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5950 DAG.getConstant(CnstVal, dl, MVT::i32));
5951 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5954 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5955 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5956 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5957 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5958 DAG.getConstant(CnstVal, dl, MVT::i32),
5959 DAG.getConstant(0, dl, MVT::i32));
5960 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5963 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5964 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5965 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5966 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5967 DAG.getConstant(CnstVal, dl, MVT::i32),
5968 DAG.getConstant(8, dl, MVT::i32));
5969 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5972 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5973 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5974 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5975 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5976 DAG.getConstant(CnstVal, dl, MVT::i32),
5977 DAG.getConstant(16, dl, MVT::i32));
5978 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5981 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5982 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5983 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5984 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5985 DAG.getConstant(CnstVal, dl, MVT::i32),
5986 DAG.getConstant(24, dl, MVT::i32));
5987 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5990 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5991 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5992 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5993 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5994 DAG.getConstant(CnstVal, dl, MVT::i32),
5995 DAG.getConstant(0, dl, MVT::i32));
5996 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5999 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6000 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6001 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6002 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6003 DAG.getConstant(CnstVal, dl, MVT::i32),
6004 DAG.getConstant(8, dl, MVT::i32));
6005 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6008 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6009 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6010 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6011 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6012 DAG.getConstant(CnstVal, dl, MVT::i32),
6013 DAG.getConstant(264, dl, MVT::i32));
6014 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6017 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6018 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6019 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6020 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6021 DAG.getConstant(CnstVal, dl, MVT::i32),
6022 DAG.getConstant(272, dl, MVT::i32));
6023 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6026 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
6027 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
6028 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6029 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
6030 DAG.getConstant(CnstVal, dl, MVT::i32));
6031 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6034 // The few faces of FMOV...
6035 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
6036 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
6037 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6038 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
6039 DAG.getConstant(CnstVal, dl, MVT::i32));
6040 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6043 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
6044 VT.getSizeInBits() == 128) {
6045 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
6046 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
6047 DAG.getConstant(CnstVal, dl, MVT::i32));
6048 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6051 // The many faces of MVNI...
6053 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6054 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6055 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6056 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6057 DAG.getConstant(CnstVal, dl, MVT::i32),
6058 DAG.getConstant(0, dl, MVT::i32));
6059 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6062 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6063 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6064 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6065 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6066 DAG.getConstant(CnstVal, dl, MVT::i32),
6067 DAG.getConstant(8, dl, MVT::i32));
6068 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6071 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6072 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6073 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6074 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6075 DAG.getConstant(CnstVal, dl, MVT::i32),
6076 DAG.getConstant(16, dl, MVT::i32));
6077 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6080 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6081 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6082 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6083 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6084 DAG.getConstant(CnstVal, dl, MVT::i32),
6085 DAG.getConstant(24, dl, MVT::i32));
6086 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6089 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6090 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6091 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6092 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6093 DAG.getConstant(CnstVal, dl, MVT::i32),
6094 DAG.getConstant(0, dl, MVT::i32));
6095 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6098 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6099 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6100 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6101 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6102 DAG.getConstant(CnstVal, dl, MVT::i32),
6103 DAG.getConstant(8, dl, MVT::i32));
6104 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6107 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6108 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6109 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6110 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6111 DAG.getConstant(CnstVal, dl, MVT::i32),
6112 DAG.getConstant(264, dl, MVT::i32));
6113 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6116 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6117 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6118 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6119 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6120 DAG.getConstant(CnstVal, dl, MVT::i32),
6121 DAG.getConstant(272, dl, MVT::i32));
6122 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6129 CnstBits = UndefBits;
6134 // Scan through the operands to find some interesting properties we can
6136 // 1) If only one value is used, we can use a DUP, or
6137 // 2) if only the low element is not undef, we can just insert that, or
6138 // 3) if only one constant value is used (w/ some non-constant lanes),
6139 // we can splat the constant value into the whole vector then fill
6140 // in the non-constant lanes.
6141 // 4) FIXME: If different constant values are used, but we can intelligently
6142 // select the values we'll be overwriting for the non-constant
6143 // lanes such that we can directly materialize the vector
6144 // some other way (MOVI, e.g.), we can be sneaky.
6145 unsigned NumElts = VT.getVectorNumElements();
6146 bool isOnlyLowElement = true;
6147 bool usesOnlyOneValue = true;
6148 bool usesOnlyOneConstantValue = true;
6149 bool isConstant = true;
6150 unsigned NumConstantLanes = 0;
6152 SDValue ConstantValue;
6153 for (unsigned i = 0; i < NumElts; ++i) {
6154 SDValue V = Op.getOperand(i);
6155 if (V.getOpcode() == ISD::UNDEF)
6158 isOnlyLowElement = false;
6159 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6162 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
6164 if (!ConstantValue.getNode())
6166 else if (ConstantValue != V)
6167 usesOnlyOneConstantValue = false;
6170 if (!Value.getNode())
6172 else if (V != Value)
6173 usesOnlyOneValue = false;
6176 if (!Value.getNode())
6177 return DAG.getUNDEF(VT);
6179 if (isOnlyLowElement)
6180 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6182 // Use DUP for non-constant splats. For f32 constant splats, reduce to
6183 // i32 and try again.
6184 if (usesOnlyOneValue) {
6186 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6187 Value.getValueType() != VT)
6188 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6190 // This is actually a DUPLANExx operation, which keeps everything vectory.
6192 // DUPLANE works on 128-bit vectors, widen it if necessary.
6193 SDValue Lane = Value.getOperand(1);
6194 Value = Value.getOperand(0);
6195 if (Value.getValueType().getSizeInBits() == 64)
6196 Value = WidenVector(Value, DAG);
6198 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6199 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6202 if (VT.getVectorElementType().isFloatingPoint()) {
6203 SmallVector<SDValue, 8> Ops;
6204 EVT EltTy = VT.getVectorElementType();
6205 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
6206 "Unsupported floating-point vector type");
6207 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
6208 for (unsigned i = 0; i < NumElts; ++i)
6209 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
6210 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
6211 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
6212 Val = LowerBUILD_VECTOR(Val, DAG);
6214 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6218 // If there was only one constant value used and for more than one lane,
6219 // start by splatting that value, then replace the non-constant lanes. This
6220 // is better than the default, which will perform a separate initialization
6222 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6223 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6224 // Now insert the non-constant lanes.
6225 for (unsigned i = 0; i < NumElts; ++i) {
6226 SDValue V = Op.getOperand(i);
6227 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6228 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6229 // Note that type legalization likely mucked about with the VT of the
6230 // source operand, so we may have to convert it here before inserting.
6231 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6237 // If all elements are constants and the case above didn't get hit, fall back
6238 // to the default expansion, which will generate a load from the constant
6243 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6245 if (SDValue shuffle = ReconstructShuffle(Op, DAG))
6249 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6250 // know the default expansion would otherwise fall back on something even
6251 // worse. For a vector with one or two non-undef values, that's
6252 // scalar_to_vector for the elements followed by a shuffle (provided the
6253 // shuffle is valid for the target) and materialization element by element
6254 // on the stack followed by a load for everything else.
6255 if (!isConstant && !usesOnlyOneValue) {
6256 SDValue Vec = DAG.getUNDEF(VT);
6257 SDValue Op0 = Op.getOperand(0);
6258 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6260 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6261 // a) Avoid a RMW dependency on the full vector register, and
6262 // b) Allow the register coalescer to fold away the copy if the
6263 // value is already in an S or D register.
6264 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6265 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6267 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6268 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6269 Vec = SDValue(N, 0);
6272 for (; i < NumElts; ++i) {
6273 SDValue V = Op.getOperand(i);
6274 if (V.getOpcode() == ISD::UNDEF)
6276 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6277 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6282 // Just use the default expansion. We failed to find a better alternative.
6286 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6287 SelectionDAG &DAG) const {
6288 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6290 // Check for non-constant or out of range lane.
6291 EVT VT = Op.getOperand(0).getValueType();
6292 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6293 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6297 // Insertion/extraction are legal for V128 types.
6298 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6299 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6303 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6304 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6307 // For V64 types, we perform insertion by expanding the value
6308 // to a V128 type and perform the insertion on that.
6310 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6311 EVT WideTy = WideVec.getValueType();
6313 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6314 Op.getOperand(1), Op.getOperand(2));
6315 // Re-narrow the resultant vector.
6316 return NarrowVector(Node, DAG);
6320 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6321 SelectionDAG &DAG) const {
6322 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6324 // Check for non-constant or out of range lane.
6325 EVT VT = Op.getOperand(0).getValueType();
6326 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6327 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6331 // Insertion/extraction are legal for V128 types.
6332 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6333 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6337 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6338 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6341 // For V64 types, we perform extraction by expanding the value
6342 // to a V128 type and perform the extraction on that.
6344 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6345 EVT WideTy = WideVec.getValueType();
6347 EVT ExtrTy = WideTy.getVectorElementType();
6348 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6351 // For extractions, we just return the result directly.
6352 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6356 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6357 SelectionDAG &DAG) const {
6358 EVT VT = Op.getOperand(0).getValueType();
6364 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6367 unsigned Val = Cst->getZExtValue();
6369 unsigned Size = Op.getValueType().getSizeInBits();
6373 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6376 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6379 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6382 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6385 llvm_unreachable("Unexpected vector type in extract_subvector!");
6388 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6390 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6396 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6398 if (VT.getVectorNumElements() == 4 &&
6399 (VT.is128BitVector() || VT.is64BitVector())) {
6400 unsigned PFIndexes[4];
6401 for (unsigned i = 0; i != 4; ++i) {
6405 PFIndexes[i] = M[i];
6408 // Compute the index in the perfect shuffle table.
6409 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6410 PFIndexes[2] * 9 + PFIndexes[3];
6411 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6412 unsigned Cost = (PFEntry >> 30);
6420 unsigned DummyUnsigned;
6422 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6423 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6424 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6425 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6426 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6427 isZIPMask(M, VT, DummyUnsigned) ||
6428 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6429 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6430 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6431 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6432 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6435 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6436 /// operand of a vector shift operation, where all the elements of the
6437 /// build_vector must have the same constant integer value.
6438 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6439 // Ignore bit_converts.
6440 while (Op.getOpcode() == ISD::BITCAST)
6441 Op = Op.getOperand(0);
6442 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6443 APInt SplatBits, SplatUndef;
6444 unsigned SplatBitSize;
6446 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6447 HasAnyUndefs, ElementBits) ||
6448 SplatBitSize > ElementBits)
6450 Cnt = SplatBits.getSExtValue();
6454 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6455 /// operand of a vector shift left operation. That value must be in the range:
6456 /// 0 <= Value < ElementBits for a left shift; or
6457 /// 0 <= Value <= ElementBits for a long left shift.
6458 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6459 assert(VT.isVector() && "vector shift count is not a vector type");
6460 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6461 if (!getVShiftImm(Op, ElementBits, Cnt))
6463 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6466 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6467 /// operand of a vector shift right operation. The value must be in the range:
6468 /// 1 <= Value <= ElementBits for a right shift; or
6469 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6470 assert(VT.isVector() && "vector shift count is not a vector type");
6471 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6472 if (!getVShiftImm(Op, ElementBits, Cnt))
6474 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6477 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6478 SelectionDAG &DAG) const {
6479 EVT VT = Op.getValueType();
6483 if (!Op.getOperand(1).getValueType().isVector())
6485 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6487 switch (Op.getOpcode()) {
6489 llvm_unreachable("unexpected shift opcode");
6492 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6493 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6494 DAG.getConstant(Cnt, DL, MVT::i32));
6495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6496 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6498 Op.getOperand(0), Op.getOperand(1));
6501 // Right shift immediate
6502 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6504 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6505 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6506 DAG.getConstant(Cnt, DL, MVT::i32));
6509 // Right shift register. Note, there is not a shift right register
6510 // instruction, but the shift left register instruction takes a signed
6511 // value, where negative numbers specify a right shift.
6512 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6513 : Intrinsic::aarch64_neon_ushl;
6514 // negate the shift amount
6515 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6516 SDValue NegShiftLeft =
6517 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6518 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6520 return NegShiftLeft;
6526 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6527 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6528 SDLoc dl, SelectionDAG &DAG) {
6529 EVT SrcVT = LHS.getValueType();
6530 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6531 "function only supposed to emit natural comparisons");
6533 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6534 APInt CnstBits(VT.getSizeInBits(), 0);
6535 APInt UndefBits(VT.getSizeInBits(), 0);
6536 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6537 bool IsZero = IsCnst && (CnstBits == 0);
6539 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6543 case AArch64CC::NE: {
6546 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6548 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6549 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6553 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6554 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6557 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6558 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6561 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6562 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6565 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6566 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6570 // If we ignore NaNs then we can use to the MI implementation.
6574 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6575 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6582 case AArch64CC::NE: {
6585 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6587 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6588 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6592 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6593 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6596 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6597 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6600 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6601 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6604 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6605 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6607 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6609 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6612 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6613 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6615 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6617 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6621 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6622 SelectionDAG &DAG) const {
6623 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6624 SDValue LHS = Op.getOperand(0);
6625 SDValue RHS = Op.getOperand(1);
6626 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6629 if (LHS.getValueType().getVectorElementType().isInteger()) {
6630 assert(LHS.getValueType() == RHS.getValueType());
6631 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6633 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6634 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6637 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6638 LHS.getValueType().getVectorElementType() == MVT::f64);
6640 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6641 // clean. Some of them require two branches to implement.
6642 AArch64CC::CondCode CC1, CC2;
6644 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6646 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6648 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6652 if (CC2 != AArch64CC::AL) {
6654 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6655 if (!Cmp2.getNode())
6658 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6661 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6664 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6669 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6670 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6671 /// specified in the intrinsic calls.
6672 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6674 unsigned Intrinsic) const {
6675 auto &DL = I.getModule()->getDataLayout();
6676 switch (Intrinsic) {
6677 case Intrinsic::aarch64_neon_ld2:
6678 case Intrinsic::aarch64_neon_ld3:
6679 case Intrinsic::aarch64_neon_ld4:
6680 case Intrinsic::aarch64_neon_ld1x2:
6681 case Intrinsic::aarch64_neon_ld1x3:
6682 case Intrinsic::aarch64_neon_ld1x4:
6683 case Intrinsic::aarch64_neon_ld2lane:
6684 case Intrinsic::aarch64_neon_ld3lane:
6685 case Intrinsic::aarch64_neon_ld4lane:
6686 case Intrinsic::aarch64_neon_ld2r:
6687 case Intrinsic::aarch64_neon_ld3r:
6688 case Intrinsic::aarch64_neon_ld4r: {
6689 Info.opc = ISD::INTRINSIC_W_CHAIN;
6690 // Conservatively set memVT to the entire set of vectors loaded.
6691 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
6692 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6693 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6696 Info.vol = false; // volatile loads with NEON intrinsics not supported
6697 Info.readMem = true;
6698 Info.writeMem = false;
6701 case Intrinsic::aarch64_neon_st2:
6702 case Intrinsic::aarch64_neon_st3:
6703 case Intrinsic::aarch64_neon_st4:
6704 case Intrinsic::aarch64_neon_st1x2:
6705 case Intrinsic::aarch64_neon_st1x3:
6706 case Intrinsic::aarch64_neon_st1x4:
6707 case Intrinsic::aarch64_neon_st2lane:
6708 case Intrinsic::aarch64_neon_st3lane:
6709 case Intrinsic::aarch64_neon_st4lane: {
6710 Info.opc = ISD::INTRINSIC_VOID;
6711 // Conservatively set memVT to the entire set of vectors stored.
6712 unsigned NumElts = 0;
6713 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6714 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6715 if (!ArgTy->isVectorTy())
6717 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
6719 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6720 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6723 Info.vol = false; // volatile stores with NEON intrinsics not supported
6724 Info.readMem = false;
6725 Info.writeMem = true;
6728 case Intrinsic::aarch64_ldaxr:
6729 case Intrinsic::aarch64_ldxr: {
6730 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6731 Info.opc = ISD::INTRINSIC_W_CHAIN;
6732 Info.memVT = MVT::getVT(PtrTy->getElementType());
6733 Info.ptrVal = I.getArgOperand(0);
6735 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6737 Info.readMem = true;
6738 Info.writeMem = false;
6741 case Intrinsic::aarch64_stlxr:
6742 case Intrinsic::aarch64_stxr: {
6743 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6744 Info.opc = ISD::INTRINSIC_W_CHAIN;
6745 Info.memVT = MVT::getVT(PtrTy->getElementType());
6746 Info.ptrVal = I.getArgOperand(1);
6748 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6750 Info.readMem = false;
6751 Info.writeMem = true;
6754 case Intrinsic::aarch64_ldaxp:
6755 case Intrinsic::aarch64_ldxp: {
6756 Info.opc = ISD::INTRINSIC_W_CHAIN;
6757 Info.memVT = MVT::i128;
6758 Info.ptrVal = I.getArgOperand(0);
6762 Info.readMem = true;
6763 Info.writeMem = false;
6766 case Intrinsic::aarch64_stlxp:
6767 case Intrinsic::aarch64_stxp: {
6768 Info.opc = ISD::INTRINSIC_W_CHAIN;
6769 Info.memVT = MVT::i128;
6770 Info.ptrVal = I.getArgOperand(2);
6774 Info.readMem = false;
6775 Info.writeMem = true;
6785 // Truncations from 64-bit GPR to 32-bit GPR is free.
6786 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6787 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6789 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6790 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6791 return NumBits1 > NumBits2;
6793 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6794 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6796 unsigned NumBits1 = VT1.getSizeInBits();
6797 unsigned NumBits2 = VT2.getSizeInBits();
6798 return NumBits1 > NumBits2;
6801 /// Check if it is profitable to hoist instruction in then/else to if.
6802 /// Not profitable if I and it's user can form a FMA instruction
6803 /// because we prefer FMSUB/FMADD.
6804 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6805 if (I->getOpcode() != Instruction::FMul)
6808 if (I->getNumUses() != 1)
6811 Instruction *User = I->user_back();
6814 !(User->getOpcode() == Instruction::FSub ||
6815 User->getOpcode() == Instruction::FAdd))
6818 const TargetOptions &Options = getTargetMachine().Options;
6819 const DataLayout &DL = I->getModule()->getDataLayout();
6820 EVT VT = getValueType(DL, User->getOperand(0)->getType());
6822 if (isFMAFasterThanFMulAndFAdd(VT) &&
6823 isOperationLegalOrCustom(ISD::FMA, VT) &&
6824 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6830 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6832 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6833 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6835 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6836 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6837 return NumBits1 == 32 && NumBits2 == 64;
6839 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6840 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6842 unsigned NumBits1 = VT1.getSizeInBits();
6843 unsigned NumBits2 = VT2.getSizeInBits();
6844 return NumBits1 == 32 && NumBits2 == 64;
6847 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6848 EVT VT1 = Val.getValueType();
6849 if (isZExtFree(VT1, VT2)) {
6853 if (Val.getOpcode() != ISD::LOAD)
6856 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6857 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6858 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6859 VT1.getSizeInBits() <= 32);
6862 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6863 if (isa<FPExtInst>(Ext))
6866 // Vector types are next free.
6867 if (Ext->getType()->isVectorTy())
6870 for (const Use &U : Ext->uses()) {
6871 // The extension is free if we can fold it with a left shift in an
6872 // addressing mode or an arithmetic operation: add, sub, and cmp.
6874 // Is there a shift?
6875 const Instruction *Instr = cast<Instruction>(U.getUser());
6877 // Is this a constant shift?
6878 switch (Instr->getOpcode()) {
6879 case Instruction::Shl:
6880 if (!isa<ConstantInt>(Instr->getOperand(1)))
6883 case Instruction::GetElementPtr: {
6884 gep_type_iterator GTI = gep_type_begin(Instr);
6885 auto &DL = Ext->getModule()->getDataLayout();
6886 std::advance(GTI, U.getOperandNo());
6888 // This extension will end up with a shift because of the scaling factor.
6889 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6890 // Get the shift amount based on the scaling factor:
6891 // log2(sizeof(IdxTy)) - log2(8).
6893 countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy)) - 3;
6894 // Is the constant foldable in the shift of the addressing mode?
6895 // I.e., shift amount is between 1 and 4 inclusive.
6896 if (ShiftAmt == 0 || ShiftAmt > 4)
6900 case Instruction::Trunc:
6901 // Check if this is a noop.
6902 // trunc(sext ty1 to ty2) to ty1.
6903 if (Instr->getType() == Ext->getOperand(0)->getType())
6910 // At this point we can use the bfm family, so this extension is free
6916 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6917 unsigned &RequiredAligment) const {
6918 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6920 // Cyclone supports unaligned accesses.
6921 RequiredAligment = 0;
6922 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6923 return NumBits == 32 || NumBits == 64;
6926 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6927 unsigned &RequiredAligment) const {
6928 if (!LoadedType.isSimple() ||
6929 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6931 // Cyclone supports unaligned accesses.
6932 RequiredAligment = 0;
6933 unsigned NumBits = LoadedType.getSizeInBits();
6934 return NumBits == 32 || NumBits == 64;
6937 /// \brief Lower an interleaved load into a ldN intrinsic.
6939 /// E.g. Lower an interleaved load (Factor = 2):
6940 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6941 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6942 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6945 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6946 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6947 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6948 bool AArch64TargetLowering::lowerInterleavedLoad(
6949 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6950 ArrayRef<unsigned> Indices, unsigned Factor) const {
6951 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6952 "Invalid interleave factor");
6953 assert(!Shuffles.empty() && "Empty shufflevector input");
6954 assert(Shuffles.size() == Indices.size() &&
6955 "Unmatched number of shufflevectors and indices");
6957 const DataLayout &DL = LI->getModule()->getDataLayout();
6959 VectorType *VecTy = Shuffles[0]->getType();
6960 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
6962 // Skip illegal vector types.
6963 if (VecSize != 64 && VecSize != 128)
6966 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6967 // load integer vectors first and then convert to pointer vectors.
6968 Type *EltTy = VecTy->getVectorElementType();
6969 if (EltTy->isPointerTy())
6971 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
6973 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
6974 Type *Tys[2] = {VecTy, PtrTy};
6975 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
6976 Intrinsic::aarch64_neon_ld3,
6977 Intrinsic::aarch64_neon_ld4};
6979 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
6981 IRBuilder<> Builder(LI);
6982 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
6984 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
6986 // Replace uses of each shufflevector with the corresponding vector loaded
6988 for (unsigned i = 0; i < Shuffles.size(); i++) {
6989 ShuffleVectorInst *SVI = Shuffles[i];
6990 unsigned Index = Indices[i];
6992 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
6994 // Convert the integer vector to pointer vector if the element is pointer.
6995 if (EltTy->isPointerTy())
6996 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
6998 SVI->replaceAllUsesWith(SubVec);
7004 /// \brief Get a mask consisting of sequential integers starting from \p Start.
7006 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
7007 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
7009 SmallVector<Constant *, 16> Mask;
7010 for (unsigned i = 0; i < NumElts; i++)
7011 Mask.push_back(Builder.getInt32(Start + i));
7013 return ConstantVector::get(Mask);
7016 /// \brief Lower an interleaved store into a stN intrinsic.
7018 /// E.g. Lower an interleaved store (Factor = 3):
7019 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7020 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
7021 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7024 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7025 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7026 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7027 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7029 /// Note that the new shufflevectors will be removed and we'll only generate one
7030 /// st3 instruction in CodeGen.
7031 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7032 ShuffleVectorInst *SVI,
7033 unsigned Factor) const {
7034 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7035 "Invalid interleave factor");
7037 VectorType *VecTy = SVI->getType();
7038 assert(VecTy->getVectorNumElements() % Factor == 0 &&
7039 "Invalid interleaved store");
7041 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
7042 Type *EltTy = VecTy->getVectorElementType();
7043 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
7045 const DataLayout &DL = SI->getModule()->getDataLayout();
7046 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
7048 // Skip illegal vector types.
7049 if (SubVecSize != 64 && SubVecSize != 128)
7052 Value *Op0 = SVI->getOperand(0);
7053 Value *Op1 = SVI->getOperand(1);
7054 IRBuilder<> Builder(SI);
7056 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
7057 // vectors to integer vectors.
7058 if (EltTy->isPointerTy()) {
7059 Type *IntTy = DL.getIntPtrType(EltTy);
7060 unsigned NumOpElts =
7061 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
7063 // Convert to the corresponding integer vector.
7064 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
7065 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
7066 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
7068 SubVecTy = VectorType::get(IntTy, NumSubElts);
7071 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
7072 Type *Tys[2] = {SubVecTy, PtrTy};
7073 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
7074 Intrinsic::aarch64_neon_st3,
7075 Intrinsic::aarch64_neon_st4};
7077 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
7079 SmallVector<Value *, 5> Ops;
7081 // Split the shufflevector operands into sub vectors for the new stN call.
7082 for (unsigned i = 0; i < Factor; i++)
7083 Ops.push_back(Builder.CreateShuffleVector(
7084 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
7086 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
7087 Builder.CreateCall(StNFunc, Ops);
7091 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
7092 unsigned AlignCheck) {
7093 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
7094 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7097 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7098 unsigned SrcAlign, bool IsMemset,
7101 MachineFunction &MF) const {
7102 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
7103 // instruction to materialize the v2i64 zero and one store (with restrictive
7104 // addressing mode). Just do two i64 store of zero-registers.
7106 const Function *F = MF.getFunction();
7107 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
7108 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
7109 (memOpAlign(SrcAlign, DstAlign, 16) ||
7110 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
7114 (memOpAlign(SrcAlign, DstAlign, 8) ||
7115 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
7119 (memOpAlign(SrcAlign, DstAlign, 4) ||
7120 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
7126 // 12-bit optionally shifted immediates are legal for adds.
7127 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7128 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
7133 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
7134 // immediates is the same as for an add or a sub.
7135 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7138 return isLegalAddImmediate(Immed);
7141 /// isLegalAddressingMode - Return true if the addressing mode represented
7142 /// by AM is legal for this target, for a load/store of the specified type.
7143 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7144 const AddrMode &AM, Type *Ty,
7145 unsigned AS) const {
7146 // AArch64 has five basic addressing modes:
7148 // reg + 9-bit signed offset
7149 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
7151 // reg + SIZE_IN_BYTES * reg
7153 // No global is ever allowed as a base.
7157 // No reg+reg+imm addressing.
7158 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
7161 // check reg + imm case:
7162 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
7163 uint64_t NumBytes = 0;
7164 if (Ty->isSized()) {
7165 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
7166 NumBytes = NumBits / 8;
7167 if (!isPowerOf2_64(NumBits))
7172 int64_t Offset = AM.BaseOffs;
7174 // 9-bit signed offset
7175 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
7178 // 12-bit unsigned offset
7179 unsigned shift = Log2_64(NumBytes);
7180 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
7181 // Must be a multiple of NumBytes (NumBytes is a power of 2)
7182 (Offset >> shift) << shift == Offset)
7187 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
7189 if (!AM.Scale || AM.Scale == 1 ||
7190 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
7195 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7196 const AddrMode &AM, Type *Ty,
7197 unsigned AS) const {
7198 // Scaling factors are not free at all.
7199 // Operands | Rt Latency
7200 // -------------------------------------------
7202 // -------------------------------------------
7203 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
7204 // Rt, [Xn, Wm, <extend> #imm] |
7205 if (isLegalAddressingMode(DL, AM, Ty, AS))
7206 // Scale represents reg2 * scale, thus account for 1 if
7207 // it is not equal to 0 or 1.
7208 return AM.Scale != 0 && AM.Scale != 1;
7212 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7213 VT = VT.getScalarType();
7218 switch (VT.getSimpleVT().SimpleTy) {
7230 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7231 // LR is a callee-save register, but we must treat it as clobbered by any call
7232 // site. Hence we include LR in the scratch registers, which are in turn added
7233 // as implicit-defs for stackmaps and patchpoints.
7234 static const MCPhysReg ScratchRegs[] = {
7235 AArch64::X16, AArch64::X17, AArch64::LR, 0
7241 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7242 EVT VT = N->getValueType(0);
7243 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
7244 // it with shift to let it be lowered to UBFX.
7245 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7246 isa<ConstantSDNode>(N->getOperand(1))) {
7247 uint64_t TruncMask = N->getConstantOperandVal(1);
7248 if (isMask_64(TruncMask) &&
7249 N->getOperand(0).getOpcode() == ISD::SRL &&
7250 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7256 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7258 assert(Ty->isIntegerTy());
7260 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7264 int64_t Val = Imm.getSExtValue();
7265 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7268 if ((int64_t)Val < 0)
7271 Val &= (1LL << 32) - 1;
7273 unsigned LZ = countLeadingZeros((uint64_t)Val);
7274 unsigned Shift = (63 - LZ) / 16;
7275 // MOVZ is free so return true for one or fewer MOVK.
7279 // Generate SUBS and CSEL for integer abs.
7280 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7281 EVT VT = N->getValueType(0);
7283 SDValue N0 = N->getOperand(0);
7284 SDValue N1 = N->getOperand(1);
7287 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7288 // and change it to SUB and CSEL.
7289 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7290 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7291 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7292 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7293 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7294 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7296 // Generate SUBS & CSEL.
7298 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7299 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7300 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7301 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7302 SDValue(Cmp.getNode(), 1));
7307 // performXorCombine - Attempts to handle integer ABS.
7308 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7309 TargetLowering::DAGCombinerInfo &DCI,
7310 const AArch64Subtarget *Subtarget) {
7311 if (DCI.isBeforeLegalizeOps())
7314 return performIntegerAbsCombine(N, DAG);
7318 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7320 std::vector<SDNode *> *Created) const {
7321 // fold (sdiv X, pow2)
7322 EVT VT = N->getValueType(0);
7323 if ((VT != MVT::i32 && VT != MVT::i64) ||
7324 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7328 SDValue N0 = N->getOperand(0);
7329 unsigned Lg2 = Divisor.countTrailingZeros();
7330 SDValue Zero = DAG.getConstant(0, DL, VT);
7331 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7333 // Add (N0 < 0) ? Pow2 - 1 : 0;
7335 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7336 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7337 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7340 Created->push_back(Cmp.getNode());
7341 Created->push_back(Add.getNode());
7342 Created->push_back(CSel.getNode());
7347 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7349 // If we're dividing by a positive value, we're done. Otherwise, we must
7350 // negate the result.
7351 if (Divisor.isNonNegative())
7355 Created->push_back(SRA.getNode());
7356 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7359 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7360 TargetLowering::DAGCombinerInfo &DCI,
7361 const AArch64Subtarget *Subtarget) {
7362 if (DCI.isBeforeLegalizeOps())
7365 // Multiplication of a power of two plus/minus one can be done more
7366 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7367 // future CPUs have a cheaper MADD instruction, this may need to be
7368 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7369 // 64-bit is 5 cycles, so this is always a win.
7370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7371 APInt Value = C->getAPIntValue();
7372 EVT VT = N->getValueType(0);
7374 if (Value.isNonNegative()) {
7375 // (mul x, 2^N + 1) => (add (shl x, N), x)
7376 APInt VM1 = Value - 1;
7377 if (VM1.isPowerOf2()) {
7378 SDValue ShiftedVal =
7379 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7380 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7381 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7384 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7385 APInt VP1 = Value + 1;
7386 if (VP1.isPowerOf2()) {
7387 SDValue ShiftedVal =
7388 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7389 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7390 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7394 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7395 APInt VNP1 = -Value + 1;
7396 if (VNP1.isPowerOf2()) {
7397 SDValue ShiftedVal =
7398 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7399 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7400 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7403 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7404 APInt VNM1 = -Value - 1;
7405 if (VNM1.isPowerOf2()) {
7406 SDValue ShiftedVal =
7407 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7408 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7410 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7411 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7418 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7419 SelectionDAG &DAG) {
7420 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7421 // optimize away operation when it's from a constant.
7423 // The general transformation is:
7424 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7425 // AND(VECTOR_CMP(x,y), constant2)
7426 // constant2 = UNARYOP(constant)
7428 // Early exit if this isn't a vector operation, the operand of the
7429 // unary operation isn't a bitwise AND, or if the sizes of the operations
7431 EVT VT = N->getValueType(0);
7432 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7433 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7434 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7437 // Now check that the other operand of the AND is a constant. We could
7438 // make the transformation for non-constant splats as well, but it's unclear
7439 // that would be a benefit as it would not eliminate any operations, just
7440 // perform one more step in scalar code before moving to the vector unit.
7441 if (BuildVectorSDNode *BV =
7442 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7443 // Bail out if the vector isn't a constant.
7444 if (!BV->isConstant())
7447 // Everything checks out. Build up the new and improved node.
7449 EVT IntVT = BV->getValueType(0);
7450 // Create a new constant of the appropriate type for the transformed
7452 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7453 // The AND node needs bitcasts to/from an integer vector type around it.
7454 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7455 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7456 N->getOperand(0)->getOperand(0), MaskConst);
7457 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7464 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7465 const AArch64Subtarget *Subtarget) {
7466 // First try to optimize away the conversion when it's conditionally from
7467 // a constant. Vectors only.
7468 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
7471 EVT VT = N->getValueType(0);
7472 if (VT != MVT::f32 && VT != MVT::f64)
7475 // Only optimize when the source and destination types have the same width.
7476 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7479 // If the result of an integer load is only used by an integer-to-float
7480 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7481 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7482 SDValue N0 = N->getOperand(0);
7483 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7484 // Do not change the width of a volatile load.
7485 !cast<LoadSDNode>(N0)->isVolatile()) {
7486 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7487 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7488 LN0->getPointerInfo(), LN0->isVolatile(),
7489 LN0->isNonTemporal(), LN0->isInvariant(),
7490 LN0->getAlignment());
7492 // Make sure successors of the original load stay after it by updating them
7493 // to use the new Chain.
7494 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7497 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7498 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7504 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7505 /// searches for and classifies those shifts.
7506 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7508 if (N.getOpcode() == ISD::SHL)
7510 else if (N.getOpcode() == ISD::SRL)
7515 if (!isa<ConstantSDNode>(N.getOperand(1)))
7518 ShiftAmount = N->getConstantOperandVal(1);
7519 Src = N->getOperand(0);
7523 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7524 /// registers viewed as a high/low pair. This function looks for the pattern:
7525 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7526 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7528 static SDValue tryCombineToEXTR(SDNode *N,
7529 TargetLowering::DAGCombinerInfo &DCI) {
7530 SelectionDAG &DAG = DCI.DAG;
7532 EVT VT = N->getValueType(0);
7534 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7536 if (VT != MVT::i32 && VT != MVT::i64)
7540 uint32_t ShiftLHS = 0;
7542 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7546 uint32_t ShiftRHS = 0;
7548 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7551 // If they're both trying to come from the high part of the register, they're
7552 // not really an EXTR.
7553 if (LHSFromHi == RHSFromHi)
7556 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7560 std::swap(LHS, RHS);
7561 std::swap(ShiftLHS, ShiftRHS);
7564 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7565 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7568 static SDValue tryCombineToBSL(SDNode *N,
7569 TargetLowering::DAGCombinerInfo &DCI) {
7570 EVT VT = N->getValueType(0);
7571 SelectionDAG &DAG = DCI.DAG;
7577 SDValue N0 = N->getOperand(0);
7578 if (N0.getOpcode() != ISD::AND)
7581 SDValue N1 = N->getOperand(1);
7582 if (N1.getOpcode() != ISD::AND)
7585 // We only have to look for constant vectors here since the general, variable
7586 // case can be handled in TableGen.
7587 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7588 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7589 for (int i = 1; i >= 0; --i)
7590 for (int j = 1; j >= 0; --j) {
7591 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7592 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7596 bool FoundMatch = true;
7597 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7598 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7599 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7601 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7608 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7609 N0->getOperand(1 - i), N1->getOperand(1 - j));
7615 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7616 const AArch64Subtarget *Subtarget) {
7617 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7618 if (!EnableAArch64ExtrGeneration)
7620 SelectionDAG &DAG = DCI.DAG;
7621 EVT VT = N->getValueType(0);
7623 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7626 SDValue Res = tryCombineToEXTR(N, DCI);
7630 Res = tryCombineToBSL(N, DCI);
7637 static SDValue performBitcastCombine(SDNode *N,
7638 TargetLowering::DAGCombinerInfo &DCI,
7639 SelectionDAG &DAG) {
7640 // Wait 'til after everything is legalized to try this. That way we have
7641 // legal vector types and such.
7642 if (DCI.isBeforeLegalizeOps())
7645 // Remove extraneous bitcasts around an extract_subvector.
7647 // (v4i16 (bitconvert
7648 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7650 // (extract_subvector ((v8i16 ...), (i64 4)))
7652 // Only interested in 64-bit vectors as the ultimate result.
7653 EVT VT = N->getValueType(0);
7656 if (VT.getSimpleVT().getSizeInBits() != 64)
7658 // Is the operand an extract_subvector starting at the beginning or halfway
7659 // point of the vector? A low half may also come through as an
7660 // EXTRACT_SUBREG, so look for that, too.
7661 SDValue Op0 = N->getOperand(0);
7662 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7663 !(Op0->isMachineOpcode() &&
7664 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7666 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7667 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7668 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7670 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7671 if (idx != AArch64::dsub)
7673 // The dsub reference is equivalent to a lane zero subvector reference.
7676 // Look through the bitcast of the input to the extract.
7677 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7679 SDValue Source = Op0->getOperand(0)->getOperand(0);
7680 // If the source type has twice the number of elements as our destination
7681 // type, we know this is an extract of the high or low half of the vector.
7682 EVT SVT = Source->getValueType(0);
7683 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7686 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7688 // Create the simplified form to just extract the low or high half of the
7689 // vector directly rather than bothering with the bitcasts.
7691 unsigned NumElements = VT.getVectorNumElements();
7693 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7694 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7696 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7697 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7703 static SDValue performConcatVectorsCombine(SDNode *N,
7704 TargetLowering::DAGCombinerInfo &DCI,
7705 SelectionDAG &DAG) {
7707 EVT VT = N->getValueType(0);
7708 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7710 // Optimize concat_vectors of truncated vectors, where the intermediate
7711 // type is illegal, to avoid said illegality, e.g.,
7712 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7713 // (v2i16 (truncate (v2i64)))))
7715 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7716 // (v4i32 (bitcast (v2i64))),
7718 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7719 // on both input and result type, so we might generate worse code.
7720 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7721 if (N->getNumOperands() == 2 &&
7722 N0->getOpcode() == ISD::TRUNCATE &&
7723 N1->getOpcode() == ISD::TRUNCATE) {
7724 SDValue N00 = N0->getOperand(0);
7725 SDValue N10 = N1->getOperand(0);
7726 EVT N00VT = N00.getValueType();
7728 if (N00VT == N10.getValueType() &&
7729 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7730 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7731 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7732 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7733 for (size_t i = 0; i < Mask.size(); ++i)
7735 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7736 DAG.getVectorShuffle(
7738 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7739 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7743 // Wait 'til after everything is legalized to try this. That way we have
7744 // legal vector types and such.
7745 if (DCI.isBeforeLegalizeOps())
7748 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7749 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7750 // canonicalise to that.
7751 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7752 assert(VT.getVectorElementType().getSizeInBits() == 64);
7753 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7754 DAG.getConstant(0, dl, MVT::i64));
7757 // Canonicalise concat_vectors so that the right-hand vector has as few
7758 // bit-casts as possible before its real operation. The primary matching
7759 // destination for these operations will be the narrowing "2" instructions,
7760 // which depend on the operation being performed on this right-hand vector.
7762 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7764 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7766 if (N1->getOpcode() != ISD::BITCAST)
7768 SDValue RHS = N1->getOperand(0);
7769 MVT RHSTy = RHS.getValueType().getSimpleVT();
7770 // If the RHS is not a vector, this is not the pattern we're looking for.
7771 if (!RHSTy.isVector())
7774 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7776 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7777 RHSTy.getVectorNumElements() * 2);
7778 return DAG.getNode(ISD::BITCAST, dl, VT,
7779 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7780 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7784 static SDValue tryCombineFixedPointConvert(SDNode *N,
7785 TargetLowering::DAGCombinerInfo &DCI,
7786 SelectionDAG &DAG) {
7787 // Wait 'til after everything is legalized to try this. That way we have
7788 // legal vector types and such.
7789 if (DCI.isBeforeLegalizeOps())
7791 // Transform a scalar conversion of a value from a lane extract into a
7792 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7793 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7794 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7796 // The second form interacts better with instruction selection and the
7797 // register allocator to avoid cross-class register copies that aren't
7798 // coalescable due to a lane reference.
7800 // Check the operand and see if it originates from a lane extract.
7801 SDValue Op1 = N->getOperand(1);
7802 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7803 // Yep, no additional predication needed. Perform the transform.
7804 SDValue IID = N->getOperand(0);
7805 SDValue Shift = N->getOperand(2);
7806 SDValue Vec = Op1.getOperand(0);
7807 SDValue Lane = Op1.getOperand(1);
7808 EVT ResTy = N->getValueType(0);
7812 // The vector width should be 128 bits by the time we get here, even
7813 // if it started as 64 bits (the extract_vector handling will have
7815 assert(Vec.getValueType().getSizeInBits() == 128 &&
7816 "unexpected vector size on extract_vector_elt!");
7817 if (Vec.getValueType() == MVT::v4i32)
7818 VecResTy = MVT::v4f32;
7819 else if (Vec.getValueType() == MVT::v2i64)
7820 VecResTy = MVT::v2f64;
7822 llvm_unreachable("unexpected vector type!");
7825 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7826 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7831 // AArch64 high-vector "long" operations are formed by performing the non-high
7832 // version on an extract_subvector of each operand which gets the high half:
7834 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7836 // However, there are cases which don't have an extract_high explicitly, but
7837 // have another operation that can be made compatible with one for free. For
7840 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7842 // This routine does the actual conversion of such DUPs, once outer routines
7843 // have determined that everything else is in order.
7844 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7846 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7847 switch (N.getOpcode()) {
7848 case AArch64ISD::DUP:
7849 case AArch64ISD::DUPLANE8:
7850 case AArch64ISD::DUPLANE16:
7851 case AArch64ISD::DUPLANE32:
7852 case AArch64ISD::DUPLANE64:
7853 case AArch64ISD::MOVI:
7854 case AArch64ISD::MOVIshift:
7855 case AArch64ISD::MOVIedit:
7856 case AArch64ISD::MOVImsl:
7857 case AArch64ISD::MVNIshift:
7858 case AArch64ISD::MVNImsl:
7861 // FMOV could be supported, but isn't very useful, as it would only occur
7862 // if you passed a bitcast' floating point immediate to an eligible long
7863 // integer op (addl, smull, ...).
7867 MVT NarrowTy = N.getSimpleValueType();
7868 if (!NarrowTy.is64BitVector())
7871 MVT ElementTy = NarrowTy.getVectorElementType();
7872 unsigned NumElems = NarrowTy.getVectorNumElements();
7873 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7876 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7877 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7878 DAG.getConstant(NumElems, dl, MVT::i64));
7881 static bool isEssentiallyExtractSubvector(SDValue N) {
7882 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7885 return N.getOpcode() == ISD::BITCAST &&
7886 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7889 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7890 struct GenericSetCCInfo {
7891 const SDValue *Opnd0;
7892 const SDValue *Opnd1;
7896 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7897 struct AArch64SetCCInfo {
7899 AArch64CC::CondCode CC;
7902 /// \brief Helper structure to keep track of SetCC information.
7904 GenericSetCCInfo Generic;
7905 AArch64SetCCInfo AArch64;
7908 /// \brief Helper structure to be able to read SetCC information. If set to
7909 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7910 /// GenericSetCCInfo.
7911 struct SetCCInfoAndKind {
7916 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7918 /// AArch64 lowered one.
7919 /// \p SetCCInfo is filled accordingly.
7920 /// \post SetCCInfo is meanginfull only when this function returns true.
7921 /// \return True when Op is a kind of SET_CC operation.
7922 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7923 // If this is a setcc, this is straight forward.
7924 if (Op.getOpcode() == ISD::SETCC) {
7925 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7926 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7927 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7928 SetCCInfo.IsAArch64 = false;
7931 // Otherwise, check if this is a matching csel instruction.
7935 if (Op.getOpcode() != AArch64ISD::CSEL)
7937 // Set the information about the operands.
7938 // TODO: we want the operands of the Cmp not the csel
7939 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7940 SetCCInfo.IsAArch64 = true;
7941 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7942 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7944 // Check that the operands matches the constraints:
7945 // (1) Both operands must be constants.
7946 // (2) One must be 1 and the other must be 0.
7947 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7948 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7951 if (!TValue || !FValue)
7955 if (!TValue->isOne()) {
7956 // Update the comparison when we are interested in !cc.
7957 std::swap(TValue, FValue);
7958 SetCCInfo.Info.AArch64.CC =
7959 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7961 return TValue->isOne() && FValue->isNullValue();
7964 // Returns true if Op is setcc or zext of setcc.
7965 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7966 if (isSetCC(Op, Info))
7968 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7969 isSetCC(Op->getOperand(0), Info));
7972 // The folding we want to perform is:
7973 // (add x, [zext] (setcc cc ...) )
7975 // (csel x, (add x, 1), !cc ...)
7977 // The latter will get matched to a CSINC instruction.
7978 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7979 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7980 SDValue LHS = Op->getOperand(0);
7981 SDValue RHS = Op->getOperand(1);
7982 SetCCInfoAndKind InfoAndKind;
7984 // If neither operand is a SET_CC, give up.
7985 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7986 std::swap(LHS, RHS);
7987 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7991 // FIXME: This could be generatized to work for FP comparisons.
7992 EVT CmpVT = InfoAndKind.IsAArch64
7993 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7994 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7995 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
8001 if (InfoAndKind.IsAArch64) {
8002 CCVal = DAG.getConstant(
8003 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8005 Cmp = *InfoAndKind.Info.AArch64.Cmp;
8007 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
8008 *InfoAndKind.Info.Generic.Opnd1,
8009 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
8012 EVT VT = Op->getValueType(0);
8013 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8014 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8017 // The basic add/sub long vector instructions have variants with "2" on the end
8018 // which act on the high-half of their inputs. They are normally matched by
8021 // (add (zeroext (extract_high LHS)),
8022 // (zeroext (extract_high RHS)))
8023 // -> uaddl2 vD, vN, vM
8025 // However, if one of the extracts is something like a duplicate, this
8026 // instruction can still be used profitably. This function puts the DAG into a
8027 // more appropriate form for those patterns to trigger.
8028 static SDValue performAddSubLongCombine(SDNode *N,
8029 TargetLowering::DAGCombinerInfo &DCI,
8030 SelectionDAG &DAG) {
8031 if (DCI.isBeforeLegalizeOps())
8034 MVT VT = N->getSimpleValueType(0);
8035 if (!VT.is128BitVector()) {
8036 if (N->getOpcode() == ISD::ADD)
8037 return performSetccAddFolding(N, DAG);
8041 // Make sure both branches are extended in the same way.
8042 SDValue LHS = N->getOperand(0);
8043 SDValue RHS = N->getOperand(1);
8044 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8045 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8046 LHS.getOpcode() != RHS.getOpcode())
8049 unsigned ExtType = LHS.getOpcode();
8051 // It's not worth doing if at least one of the inputs isn't already an
8052 // extract, but we don't know which it'll be so we have to try both.
8053 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
8054 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
8058 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8059 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
8060 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
8064 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8067 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8070 // Massage DAGs which we can use the high-half "long" operations on into
8071 // something isel will recognize better. E.g.
8073 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
8074 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8075 // (extract_high (v2i64 (dup128 scalar)))))
8077 static SDValue tryCombineLongOpWithDup(SDNode *N,
8078 TargetLowering::DAGCombinerInfo &DCI,
8079 SelectionDAG &DAG) {
8080 if (DCI.isBeforeLegalizeOps())
8083 bool IsIntrinsic = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
8084 SDValue LHS = N->getOperand(IsIntrinsic ? 1 : 0);
8085 SDValue RHS = N->getOperand(IsIntrinsic ? 2 : 1);
8086 assert(LHS.getValueType().is64BitVector() &&
8087 RHS.getValueType().is64BitVector() &&
8088 "unexpected shape for long operation");
8090 // Either node could be a DUP, but it's not worth doing both of them (you'd
8091 // just as well use the non-high version) so look for a corresponding extract
8092 // operation on the other "wing".
8093 if (isEssentiallyExtractSubvector(LHS)) {
8094 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
8097 } else if (isEssentiallyExtractSubvector(RHS)) {
8098 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
8103 // N could either be an intrinsic or a sabsdiff/uabsdiff node.
8105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
8106 N->getOperand(0), LHS, RHS);
8108 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
8112 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
8113 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
8114 unsigned ElemBits = ElemTy.getSizeInBits();
8116 int64_t ShiftAmount;
8117 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
8118 APInt SplatValue, SplatUndef;
8119 unsigned SplatBitSize;
8121 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
8122 HasAnyUndefs, ElemBits) ||
8123 SplatBitSize != ElemBits)
8126 ShiftAmount = SplatValue.getSExtValue();
8127 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
8128 ShiftAmount = CVN->getSExtValue();
8136 llvm_unreachable("Unknown shift intrinsic");
8137 case Intrinsic::aarch64_neon_sqshl:
8138 Opcode = AArch64ISD::SQSHL_I;
8139 IsRightShift = false;
8141 case Intrinsic::aarch64_neon_uqshl:
8142 Opcode = AArch64ISD::UQSHL_I;
8143 IsRightShift = false;
8145 case Intrinsic::aarch64_neon_srshl:
8146 Opcode = AArch64ISD::SRSHR_I;
8147 IsRightShift = true;
8149 case Intrinsic::aarch64_neon_urshl:
8150 Opcode = AArch64ISD::URSHR_I;
8151 IsRightShift = true;
8153 case Intrinsic::aarch64_neon_sqshlu:
8154 Opcode = AArch64ISD::SQSHLU_I;
8155 IsRightShift = false;
8159 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8161 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8162 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8163 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
8165 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8166 DAG.getConstant(ShiftAmount, dl, MVT::i32));
8172 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
8173 // the intrinsics must be legal and take an i32, this means there's almost
8174 // certainly going to be a zext in the DAG which we can eliminate.
8175 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
8176 SDValue AndN = N->getOperand(2);
8177 if (AndN.getOpcode() != ISD::AND)
8180 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
8181 if (!CMask || CMask->getZExtValue() != Mask)
8184 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
8185 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
8188 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
8189 SelectionDAG &DAG) {
8191 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
8192 DAG.getNode(Opc, dl,
8193 N->getOperand(1).getSimpleValueType(),
8195 DAG.getConstant(0, dl, MVT::i64));
8198 static SDValue performIntrinsicCombine(SDNode *N,
8199 TargetLowering::DAGCombinerInfo &DCI,
8200 const AArch64Subtarget *Subtarget) {
8201 SelectionDAG &DAG = DCI.DAG;
8202 unsigned IID = getIntrinsicID(N);
8206 case Intrinsic::aarch64_neon_vcvtfxs2fp:
8207 case Intrinsic::aarch64_neon_vcvtfxu2fp:
8208 return tryCombineFixedPointConvert(N, DCI, DAG);
8209 case Intrinsic::aarch64_neon_saddv:
8210 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
8211 case Intrinsic::aarch64_neon_uaddv:
8212 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
8213 case Intrinsic::aarch64_neon_sminv:
8214 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
8215 case Intrinsic::aarch64_neon_uminv:
8216 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
8217 case Intrinsic::aarch64_neon_smaxv:
8218 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
8219 case Intrinsic::aarch64_neon_umaxv:
8220 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
8221 case Intrinsic::aarch64_neon_fmax:
8222 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
8223 N->getOperand(1), N->getOperand(2));
8224 case Intrinsic::aarch64_neon_fmin:
8225 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
8226 N->getOperand(1), N->getOperand(2));
8227 case Intrinsic::aarch64_neon_sabd:
8228 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
8229 N->getOperand(1), N->getOperand(2));
8230 case Intrinsic::aarch64_neon_uabd:
8231 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
8232 N->getOperand(1), N->getOperand(2));
8233 case Intrinsic::aarch64_neon_smull:
8234 case Intrinsic::aarch64_neon_umull:
8235 case Intrinsic::aarch64_neon_pmull:
8236 case Intrinsic::aarch64_neon_sqdmull:
8237 return tryCombineLongOpWithDup(N, DCI, DAG);
8238 case Intrinsic::aarch64_neon_sqshl:
8239 case Intrinsic::aarch64_neon_uqshl:
8240 case Intrinsic::aarch64_neon_sqshlu:
8241 case Intrinsic::aarch64_neon_srshl:
8242 case Intrinsic::aarch64_neon_urshl:
8243 return tryCombineShiftImm(IID, N, DAG);
8244 case Intrinsic::aarch64_crc32b:
8245 case Intrinsic::aarch64_crc32cb:
8246 return tryCombineCRC32(0xff, N, DAG);
8247 case Intrinsic::aarch64_crc32h:
8248 case Intrinsic::aarch64_crc32ch:
8249 return tryCombineCRC32(0xffff, N, DAG);
8254 static SDValue performExtendCombine(SDNode *N,
8255 TargetLowering::DAGCombinerInfo &DCI,
8256 SelectionDAG &DAG) {
8257 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8258 // we can convert that DUP into another extract_high (of a bigger DUP), which
8259 // helps the backend to decide that an sabdl2 would be useful, saving a real
8260 // extract_high operation.
8261 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8262 (N->getOperand(0).getOpcode() == ISD::SABSDIFF ||
8263 N->getOperand(0).getOpcode() == ISD::UABSDIFF)) {
8264 SDNode *ABDNode = N->getOperand(0).getNode();
8265 SDValue NewABD = tryCombineLongOpWithDup(ABDNode, DCI, DAG);
8266 if (!NewABD.getNode())
8269 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8273 // This is effectively a custom type legalization for AArch64.
8275 // Type legalization will split an extend of a small, legal, type to a larger
8276 // illegal type by first splitting the destination type, often creating
8277 // illegal source types, which then get legalized in isel-confusing ways,
8278 // leading to really terrible codegen. E.g.,
8279 // %result = v8i32 sext v8i8 %value
8281 // %losrc = extract_subreg %value, ...
8282 // %hisrc = extract_subreg %value, ...
8283 // %lo = v4i32 sext v4i8 %losrc
8284 // %hi = v4i32 sext v4i8 %hisrc
8285 // Things go rapidly downhill from there.
8287 // For AArch64, the [sz]ext vector instructions can only go up one element
8288 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8289 // take two instructions.
8291 // This implies that the most efficient way to do the extend from v8i8
8292 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8293 // the normal splitting to happen for the v8i16->v8i32.
8295 // This is pre-legalization to catch some cases where the default
8296 // type legalization will create ill-tempered code.
8297 if (!DCI.isBeforeLegalizeOps())
8300 // We're only interested in cleaning things up for non-legal vector types
8301 // here. If both the source and destination are legal, things will just
8302 // work naturally without any fiddling.
8303 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8304 EVT ResVT = N->getValueType(0);
8305 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8307 // If the vector type isn't a simple VT, it's beyond the scope of what
8308 // we're worried about here. Let legalization do its thing and hope for
8310 SDValue Src = N->getOperand(0);
8311 EVT SrcVT = Src->getValueType(0);
8312 if (!ResVT.isSimple() || !SrcVT.isSimple())
8315 // If the source VT is a 64-bit vector, we can play games and get the
8316 // better results we want.
8317 if (SrcVT.getSizeInBits() != 64)
8320 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8321 unsigned ElementCount = SrcVT.getVectorNumElements();
8322 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8324 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8326 // Now split the rest of the operation into two halves, each with a 64
8330 unsigned NumElements = ResVT.getVectorNumElements();
8331 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8332 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8333 ResVT.getVectorElementType(), NumElements / 2);
8335 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8336 LoVT.getVectorNumElements());
8337 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8338 DAG.getConstant(0, DL, MVT::i64));
8339 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8340 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8341 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8342 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8344 // Now combine the parts back together so we still have a single result
8345 // like the combiner expects.
8346 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8349 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8350 /// value. The load store optimizer pass will merge them to store pair stores.
8351 /// This has better performance than a splat of the scalar followed by a split
8352 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8353 /// followed by an ext.b and two stores.
8354 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8355 SDValue StVal = St->getValue();
8356 EVT VT = StVal.getValueType();
8358 // Don't replace floating point stores, they possibly won't be transformed to
8359 // stp because of the store pair suppress pass.
8360 if (VT.isFloatingPoint())
8363 // Check for insert vector elements.
8364 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8367 // We can express a splat as store pair(s) for 2 or 4 elements.
8368 unsigned NumVecElts = VT.getVectorNumElements();
8369 if (NumVecElts != 4 && NumVecElts != 2)
8371 SDValue SplatVal = StVal.getOperand(1);
8372 unsigned RemainInsertElts = NumVecElts - 1;
8374 // Check that this is a splat.
8375 while (--RemainInsertElts) {
8376 SDValue NextInsertElt = StVal.getOperand(0);
8377 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8379 if (NextInsertElt.getOperand(1) != SplatVal)
8381 StVal = NextInsertElt;
8383 unsigned OrigAlignment = St->getAlignment();
8384 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8385 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8387 // Create scalar stores. This is at least as good as the code sequence for a
8388 // split unaligned store which is a dup.s, ext.b, and two stores.
8389 // Most of the time the three stores should be replaced by store pair
8390 // instructions (stp).
8392 SDValue BasePtr = St->getBasePtr();
8394 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8395 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8397 unsigned Offset = EltOffset;
8398 while (--NumVecElts) {
8399 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8400 DAG.getConstant(Offset, DL, MVT::i64));
8401 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8402 St->getPointerInfo(), St->isVolatile(),
8403 St->isNonTemporal(), Alignment);
8404 Offset += EltOffset;
8409 static SDValue performSTORECombine(SDNode *N,
8410 TargetLowering::DAGCombinerInfo &DCI,
8412 const AArch64Subtarget *Subtarget) {
8413 if (!DCI.isBeforeLegalize())
8416 StoreSDNode *S = cast<StoreSDNode>(N);
8417 if (S->isVolatile())
8420 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8421 // page boundaries. We want to split such stores.
8422 if (!Subtarget->isCyclone())
8425 // Don't split at -Oz.
8426 if (DAG.getMachineFunction().getFunction()->optForMinSize())
8429 SDValue StVal = S->getValue();
8430 EVT VT = StVal.getValueType();
8432 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8433 // those up regresses performance on micro-benchmarks and olden/bh.
8434 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8437 // Split unaligned 16B stores. They are terrible for performance.
8438 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8439 // extensions can use this to mark that it does not want splitting to happen
8440 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8441 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8442 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8443 S->getAlignment() <= 2)
8446 // If we get a splat of a scalar convert this vector store to a store of
8447 // scalars. They will be merged into store pairs thereby removing two
8449 if (SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S))
8450 return ReplacedSplat;
8453 unsigned NumElts = VT.getVectorNumElements() / 2;
8454 // Split VT into two.
8456 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8457 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8458 DAG.getConstant(0, DL, MVT::i64));
8459 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8460 DAG.getConstant(NumElts, DL, MVT::i64));
8461 SDValue BasePtr = S->getBasePtr();
8463 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8464 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8465 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8466 DAG.getConstant(8, DL, MVT::i64));
8467 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8468 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8472 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8473 /// post-increment LD1R.
8474 static SDValue performPostLD1Combine(SDNode *N,
8475 TargetLowering::DAGCombinerInfo &DCI,
8477 if (DCI.isBeforeLegalizeOps())
8480 SelectionDAG &DAG = DCI.DAG;
8481 EVT VT = N->getValueType(0);
8483 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8484 SDNode *LD = N->getOperand(LoadIdx).getNode();
8485 // If it is not LOAD, can not do such combine.
8486 if (LD->getOpcode() != ISD::LOAD)
8489 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8490 EVT MemVT = LoadSDN->getMemoryVT();
8491 // Check if memory operand is the same type as the vector element.
8492 if (MemVT != VT.getVectorElementType())
8495 // Check if there are other uses. If so, do not combine as it will introduce
8497 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8499 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8505 SDValue Addr = LD->getOperand(1);
8506 SDValue Vector = N->getOperand(0);
8507 // Search for a use of the address operand that is an increment.
8508 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8509 Addr.getNode()->use_end(); UI != UE; ++UI) {
8511 if (User->getOpcode() != ISD::ADD
8512 || UI.getUse().getResNo() != Addr.getResNo())
8515 // Check that the add is independent of the load. Otherwise, folding it
8516 // would create a cycle.
8517 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8519 // Also check that add is not used in the vector operand. This would also
8521 if (User->isPredecessorOf(Vector.getNode()))
8524 // If the increment is a constant, it must match the memory ref size.
8525 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8526 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8527 uint32_t IncVal = CInc->getZExtValue();
8528 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8529 if (IncVal != NumBytes)
8531 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8534 // Finally, check that the vector doesn't depend on the load.
8535 // Again, this would create a cycle.
8536 // The load depending on the vector is fine, as that's the case for the
8537 // LD1*post we'll eventually generate anyway.
8538 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8541 SmallVector<SDValue, 8> Ops;
8542 Ops.push_back(LD->getOperand(0)); // Chain
8544 Ops.push_back(Vector); // The vector to be inserted
8545 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8547 Ops.push_back(Addr);
8550 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8551 SDVTList SDTys = DAG.getVTList(Tys);
8552 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8553 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8555 LoadSDN->getMemOperand());
8558 SmallVector<SDValue, 2> NewResults;
8559 NewResults.push_back(SDValue(LD, 0)); // The result of load
8560 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8561 DCI.CombineTo(LD, NewResults);
8562 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8563 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8570 /// Target-specific DAG combine function for NEON load/store intrinsics
8571 /// to merge base address updates.
8572 static SDValue performNEONPostLDSTCombine(SDNode *N,
8573 TargetLowering::DAGCombinerInfo &DCI,
8574 SelectionDAG &DAG) {
8575 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8578 unsigned AddrOpIdx = N->getNumOperands() - 1;
8579 SDValue Addr = N->getOperand(AddrOpIdx);
8581 // Search for a use of the address operand that is an increment.
8582 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8583 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8585 if (User->getOpcode() != ISD::ADD ||
8586 UI.getUse().getResNo() != Addr.getResNo())
8589 // Check that the add is independent of the load/store. Otherwise, folding
8590 // it would create a cycle.
8591 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8594 // Find the new opcode for the updating load/store.
8595 bool IsStore = false;
8596 bool IsLaneOp = false;
8597 bool IsDupOp = false;
8598 unsigned NewOpc = 0;
8599 unsigned NumVecs = 0;
8600 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8602 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8603 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8605 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8607 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8609 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8610 NumVecs = 2; IsStore = true; break;
8611 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8612 NumVecs = 3; IsStore = true; break;
8613 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8614 NumVecs = 4; IsStore = true; break;
8615 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8617 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8619 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8621 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8622 NumVecs = 2; IsStore = true; break;
8623 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8624 NumVecs = 3; IsStore = true; break;
8625 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8626 NumVecs = 4; IsStore = true; break;
8627 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8628 NumVecs = 2; IsDupOp = true; break;
8629 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8630 NumVecs = 3; IsDupOp = true; break;
8631 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8632 NumVecs = 4; IsDupOp = true; break;
8633 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8634 NumVecs = 2; IsLaneOp = true; break;
8635 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8636 NumVecs = 3; IsLaneOp = true; break;
8637 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8638 NumVecs = 4; IsLaneOp = true; break;
8639 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8640 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8641 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8642 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8643 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8644 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8649 VecTy = N->getOperand(2).getValueType();
8651 VecTy = N->getValueType(0);
8653 // If the increment is a constant, it must match the memory ref size.
8654 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8655 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8656 uint32_t IncVal = CInc->getZExtValue();
8657 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8658 if (IsLaneOp || IsDupOp)
8659 NumBytes /= VecTy.getVectorNumElements();
8660 if (IncVal != NumBytes)
8662 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8664 SmallVector<SDValue, 8> Ops;
8665 Ops.push_back(N->getOperand(0)); // Incoming chain
8666 // Load lane and store have vector list as input.
8667 if (IsLaneOp || IsStore)
8668 for (unsigned i = 2; i < AddrOpIdx; ++i)
8669 Ops.push_back(N->getOperand(i));
8670 Ops.push_back(Addr); // Base register
8675 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8677 for (n = 0; n < NumResultVecs; ++n)
8679 Tys[n++] = MVT::i64; // Type of write back register
8680 Tys[n] = MVT::Other; // Type of the chain
8681 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8683 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8684 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8685 MemInt->getMemoryVT(),
8686 MemInt->getMemOperand());
8689 std::vector<SDValue> NewResults;
8690 for (unsigned i = 0; i < NumResultVecs; ++i) {
8691 NewResults.push_back(SDValue(UpdN.getNode(), i));
8693 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8694 DCI.CombineTo(N, NewResults);
8695 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8702 // Checks to see if the value is the prescribed width and returns information
8703 // about its extension mode.
8705 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8706 ExtType = ISD::NON_EXTLOAD;
8707 switch(V.getNode()->getOpcode()) {
8711 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8712 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8713 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8714 ExtType = LoadNode->getExtensionType();
8719 case ISD::AssertSext: {
8720 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8721 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8722 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8723 ExtType = ISD::SEXTLOAD;
8728 case ISD::AssertZext: {
8729 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8730 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8731 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8732 ExtType = ISD::ZEXTLOAD;
8738 case ISD::TargetConstant: {
8739 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8749 // This function does a whole lot of voodoo to determine if the tests are
8750 // equivalent without and with a mask. Essentially what happens is that given a
8753 // +-------------+ +-------------+ +-------------+ +-------------+
8754 // | Input | | AddConstant | | CompConstant| | CC |
8755 // +-------------+ +-------------+ +-------------+ +-------------+
8757 // V V | +----------+
8758 // +-------------+ +----+ | |
8759 // | ADD | |0xff| | |
8760 // +-------------+ +----+ | |
8763 // +-------------+ | |
8765 // +-------------+ | |
8774 // The AND node may be safely removed for some combinations of inputs. In
8775 // particular we need to take into account the extension type of the Input,
8776 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8777 // width of the input (this can work for any width inputs, the above graph is
8778 // specific to 8 bits.
8780 // The specific equations were worked out by generating output tables for each
8781 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8782 // problem was simplified by working with 4 bit inputs, which means we only
8783 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8784 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8785 // patterns present in both extensions (0,7). For every distinct set of
8786 // AddConstant and CompConstants bit patterns we can consider the masked and
8787 // unmasked versions to be equivalent if the result of this function is true for
8788 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8791 // and w10, w8, #0x0f
8793 // cset w9, AArch64CC
8795 // cset w11, AArch64CC
8800 // Since the above function shows when the outputs are equivalent it defines
8801 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8802 // would be expensive to run during compiles. The equations below were written
8803 // in a test harness that confirmed they gave equivalent outputs to the above
8804 // for all inputs function, so they can be used determine if the removal is
8807 // isEquivalentMaskless() is the code for testing if the AND can be removed
8808 // factored out of the DAG recognition as the DAG can take several forms.
8811 bool isEquivalentMaskless(unsigned CC, unsigned width,
8812 ISD::LoadExtType ExtType, signed AddConstant,
8813 signed CompConstant) {
8814 // By being careful about our equations and only writing the in term
8815 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8816 // make them generally applicable to all bit widths.
8817 signed MaxUInt = (1 << width);
8819 // For the purposes of these comparisons sign extending the type is
8820 // equivalent to zero extending the add and displacing it by half the integer
8821 // width. Provided we are careful and make sure our equations are valid over
8822 // the whole range we can just adjust the input and avoid writing equations
8823 // for sign extended inputs.
8824 if (ExtType == ISD::SEXTLOAD)
8825 AddConstant -= (1 << (width-1));
8829 case AArch64CC::GT: {
8830 if ((AddConstant == 0) ||
8831 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8832 (AddConstant >= 0 && CompConstant < 0) ||
8833 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8837 case AArch64CC::GE: {
8838 if ((AddConstant == 0) ||
8839 (AddConstant >= 0 && CompConstant <= 0) ||
8840 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8844 case AArch64CC::LS: {
8845 if ((AddConstant >= 0 && CompConstant < 0) ||
8846 (AddConstant <= 0 && CompConstant >= -1 &&
8847 CompConstant < AddConstant + MaxUInt))
8851 case AArch64CC::MI: {
8852 if ((AddConstant == 0) ||
8853 (AddConstant > 0 && CompConstant <= 0) ||
8854 (AddConstant < 0 && CompConstant <= AddConstant))
8858 case AArch64CC::HS: {
8859 if ((AddConstant >= 0 && CompConstant <= 0) ||
8860 (AddConstant <= 0 && CompConstant >= 0 &&
8861 CompConstant <= AddConstant + MaxUInt))
8865 case AArch64CC::NE: {
8866 if ((AddConstant > 0 && CompConstant < 0) ||
8867 (AddConstant < 0 && CompConstant >= 0 &&
8868 CompConstant < AddConstant + MaxUInt) ||
8869 (AddConstant >= 0 && CompConstant >= 0 &&
8870 CompConstant >= AddConstant) ||
8871 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8880 case AArch64CC::Invalid:
8888 SDValue performCONDCombine(SDNode *N,
8889 TargetLowering::DAGCombinerInfo &DCI,
8890 SelectionDAG &DAG, unsigned CCIndex,
8891 unsigned CmpIndex) {
8892 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8893 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8894 unsigned CondOpcode = SubsNode->getOpcode();
8896 if (CondOpcode != AArch64ISD::SUBS)
8899 // There is a SUBS feeding this condition. Is it fed by a mask we can
8902 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8903 unsigned MaskBits = 0;
8905 if (AndNode->getOpcode() != ISD::AND)
8908 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8909 uint32_t CNV = CN->getZExtValue();
8912 else if (CNV == 65535)
8919 SDValue AddValue = AndNode->getOperand(0);
8921 if (AddValue.getOpcode() != ISD::ADD)
8924 // The basic dag structure is correct, grab the inputs and validate them.
8926 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8927 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8928 SDValue SubsInputValue = SubsNode->getOperand(1);
8930 // The mask is present and the provenance of all the values is a smaller type,
8931 // lets see if the mask is superfluous.
8933 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8934 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8937 ISD::LoadExtType ExtType;
8939 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8940 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8941 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8944 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8945 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8946 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8949 // The AND is not necessary, remove it.
8951 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8952 SubsNode->getValueType(1));
8953 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8955 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8956 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8958 return SDValue(N, 0);
8961 // Optimize compare with zero and branch.
8962 static SDValue performBRCONDCombine(SDNode *N,
8963 TargetLowering::DAGCombinerInfo &DCI,
8964 SelectionDAG &DAG) {
8965 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8968 SDValue Chain = N->getOperand(0);
8969 SDValue Dest = N->getOperand(1);
8970 SDValue CCVal = N->getOperand(2);
8971 SDValue Cmp = N->getOperand(3);
8973 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8974 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8975 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8978 unsigned CmpOpc = Cmp.getOpcode();
8979 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8982 // Only attempt folding if there is only one use of the flag and no use of the
8984 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8987 SDValue LHS = Cmp.getOperand(0);
8988 SDValue RHS = Cmp.getOperand(1);
8990 assert(LHS.getValueType() == RHS.getValueType() &&
8991 "Expected the value type to be the same for both operands!");
8992 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8995 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8996 std::swap(LHS, RHS);
8998 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
9001 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9002 LHS.getOpcode() == ISD::SRL)
9005 // Fold the compare into the branch instruction.
9007 if (CC == AArch64CC::EQ)
9008 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9010 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9012 // Do not add new nodes to DAG combiner worklist.
9013 DCI.CombineTo(N, BR, false);
9018 // vselect (v1i1 setcc) ->
9019 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
9020 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
9021 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
9023 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
9024 SDValue N0 = N->getOperand(0);
9025 EVT CCVT = N0.getValueType();
9027 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9028 CCVT.getVectorElementType() != MVT::i1)
9031 EVT ResVT = N->getValueType(0);
9032 EVT CmpVT = N0.getOperand(0).getValueType();
9033 // Only combine when the result type is of the same size as the compared
9035 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
9038 SDValue IfTrue = N->getOperand(1);
9039 SDValue IfFalse = N->getOperand(2);
9041 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
9042 N0.getOperand(0), N0.getOperand(1),
9043 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9044 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
9048 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
9049 /// the compare-mask instructions rather than going via NZCV, even if LHS and
9050 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
9051 /// with a vector one followed by a DUP shuffle on the result.
9052 static SDValue performSelectCombine(SDNode *N,
9053 TargetLowering::DAGCombinerInfo &DCI) {
9054 SelectionDAG &DAG = DCI.DAG;
9055 SDValue N0 = N->getOperand(0);
9056 EVT ResVT = N->getValueType(0);
9058 if (N0.getOpcode() != ISD::SETCC)
9061 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
9062 // scalar SetCCResultType. We also don't expect vectors, because we assume
9063 // that selects fed by vector SETCCs are canonicalized to VSELECT.
9064 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
9065 "Scalar-SETCC feeding SELECT has unexpected result type!");
9067 // If NumMaskElts == 0, the comparison is larger than select result. The
9068 // largest real NEON comparison is 64-bits per lane, which means the result is
9069 // at most 32-bits and an illegal vector. Just bail out for now.
9070 EVT SrcVT = N0.getOperand(0).getValueType();
9072 // Don't try to do this optimization when the setcc itself has i1 operands.
9073 // There are no legal vectors of i1, so this would be pointless.
9074 if (SrcVT == MVT::i1)
9077 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
9078 if (!ResVT.isVector() || NumMaskElts == 0)
9081 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
9082 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
9084 // Also bail out if the vector CCVT isn't the same size as ResVT.
9085 // This can happen if the SETCC operand size doesn't divide the ResVT size
9086 // (e.g., f64 vs v3f32).
9087 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
9090 // Make sure we didn't create illegal types, if we're not supposed to.
9091 assert(DCI.isBeforeLegalize() ||
9092 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
9094 // First perform a vector comparison, where lane 0 is the one we're interested
9098 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
9100 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
9101 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
9103 // Now duplicate the comparison mask we want across all other lanes.
9104 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
9105 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
9106 Mask = DAG.getNode(ISD::BITCAST, DL,
9107 ResVT.changeVectorElementTypeToInteger(), Mask);
9109 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
9112 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
9113 /// to match FMIN/FMAX patterns.
9114 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
9115 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
9116 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
9117 // vmax/vmin return NaN if either operand is a NaN;
9118 // only do the transformation when it matches that behavior.
9120 SDValue CondLHS = N->getOperand(0);
9121 SDValue CondRHS = N->getOperand(1);
9122 SDValue LHS = N->getOperand(2);
9123 SDValue RHS = N->getOperand(3);
9124 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9128 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
9129 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
9130 IsReversed = false; // x CC y ? x : y
9131 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
9132 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
9133 IsReversed = true ; // x CC y ? y : x
9138 bool IsUnordered = false, IsOrEqual;
9149 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
9150 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
9160 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
9161 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
9165 // If LHS is NaN, an ordered comparison will be false and the result will be
9166 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
9167 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9168 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9171 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
9172 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
9173 // used for unsafe math or if one of the operands is known to be nonzero.
9174 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
9175 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9178 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9181 /// Get rid of unnecessary NVCASTs (that don't change the type).
9182 static SDValue performNVCASTCombine(SDNode *N) {
9183 if (N->getValueType(0) == N->getOperand(0).getValueType())
9184 return N->getOperand(0);
9189 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
9190 DAGCombinerInfo &DCI) const {
9191 SelectionDAG &DAG = DCI.DAG;
9192 switch (N->getOpcode()) {
9197 return performAddSubLongCombine(N, DCI, DAG);
9199 return performXorCombine(N, DAG, DCI, Subtarget);
9201 return performMulCombine(N, DAG, DCI, Subtarget);
9202 case ISD::SINT_TO_FP:
9203 case ISD::UINT_TO_FP:
9204 return performIntToFpCombine(N, DAG, Subtarget);
9206 return performORCombine(N, DCI, Subtarget);
9207 case ISD::INTRINSIC_WO_CHAIN:
9208 return performIntrinsicCombine(N, DCI, Subtarget);
9209 case ISD::ANY_EXTEND:
9210 case ISD::ZERO_EXTEND:
9211 case ISD::SIGN_EXTEND:
9212 return performExtendCombine(N, DCI, DAG);
9214 return performBitcastCombine(N, DCI, DAG);
9215 case ISD::CONCAT_VECTORS:
9216 return performConcatVectorsCombine(N, DCI, DAG);
9218 return performSelectCombine(N, DCI);
9220 return performVSelectCombine(N, DCI.DAG);
9221 case ISD::SELECT_CC:
9222 return performSelectCCCombine(N, DCI.DAG);
9224 return performSTORECombine(N, DCI, DAG, Subtarget);
9225 case AArch64ISD::BRCOND:
9226 return performBRCONDCombine(N, DCI, DAG);
9227 case AArch64ISD::CSEL:
9228 return performCONDCombine(N, DCI, DAG, 2, 3);
9229 case AArch64ISD::DUP:
9230 return performPostLD1Combine(N, DCI, false);
9231 case AArch64ISD::NVCAST:
9232 return performNVCASTCombine(N);
9233 case ISD::INSERT_VECTOR_ELT:
9234 return performPostLD1Combine(N, DCI, true);
9235 case ISD::INTRINSIC_VOID:
9236 case ISD::INTRINSIC_W_CHAIN:
9237 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9238 case Intrinsic::aarch64_neon_ld2:
9239 case Intrinsic::aarch64_neon_ld3:
9240 case Intrinsic::aarch64_neon_ld4:
9241 case Intrinsic::aarch64_neon_ld1x2:
9242 case Intrinsic::aarch64_neon_ld1x3:
9243 case Intrinsic::aarch64_neon_ld1x4:
9244 case Intrinsic::aarch64_neon_ld2lane:
9245 case Intrinsic::aarch64_neon_ld3lane:
9246 case Intrinsic::aarch64_neon_ld4lane:
9247 case Intrinsic::aarch64_neon_ld2r:
9248 case Intrinsic::aarch64_neon_ld3r:
9249 case Intrinsic::aarch64_neon_ld4r:
9250 case Intrinsic::aarch64_neon_st2:
9251 case Intrinsic::aarch64_neon_st3:
9252 case Intrinsic::aarch64_neon_st4:
9253 case Intrinsic::aarch64_neon_st1x2:
9254 case Intrinsic::aarch64_neon_st1x3:
9255 case Intrinsic::aarch64_neon_st1x4:
9256 case Intrinsic::aarch64_neon_st2lane:
9257 case Intrinsic::aarch64_neon_st3lane:
9258 case Intrinsic::aarch64_neon_st4lane:
9259 return performNEONPostLDSTCombine(N, DCI, DAG);
9267 // Check if the return value is used as only a return value, as otherwise
9268 // we can't perform a tail-call. In particular, we need to check for
9269 // target ISD nodes that are returns and any other "odd" constructs
9270 // that the generic analysis code won't necessarily catch.
9271 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9272 SDValue &Chain) const {
9273 if (N->getNumValues() != 1)
9275 if (!N->hasNUsesOfValue(1, 0))
9278 SDValue TCChain = Chain;
9279 SDNode *Copy = *N->use_begin();
9280 if (Copy->getOpcode() == ISD::CopyToReg) {
9281 // If the copy has a glue operand, we conservatively assume it isn't safe to
9282 // perform a tail call.
9283 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9286 TCChain = Copy->getOperand(0);
9287 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9290 bool HasRet = false;
9291 for (SDNode *Node : Copy->uses()) {
9292 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9304 // Return whether the an instruction can potentially be optimized to a tail
9305 // call. This will cause the optimizers to attempt to move, or duplicate,
9306 // return instructions to help enable tail call optimizations for this
9308 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9309 if (!CI->isTailCall())
9315 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9317 ISD::MemIndexedMode &AM,
9319 SelectionDAG &DAG) const {
9320 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9323 Base = Op->getOperand(0);
9324 // All of the indexed addressing mode instructions take a signed
9325 // 9 bit immediate offset.
9326 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9327 int64_t RHSC = (int64_t)RHS->getZExtValue();
9328 if (RHSC >= 256 || RHSC <= -256)
9330 IsInc = (Op->getOpcode() == ISD::ADD);
9331 Offset = Op->getOperand(1);
9337 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9339 ISD::MemIndexedMode &AM,
9340 SelectionDAG &DAG) const {
9343 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9344 VT = LD->getMemoryVT();
9345 Ptr = LD->getBasePtr();
9346 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9347 VT = ST->getMemoryVT();
9348 Ptr = ST->getBasePtr();
9353 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9355 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9359 bool AArch64TargetLowering::getPostIndexedAddressParts(
9360 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9361 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9364 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9365 VT = LD->getMemoryVT();
9366 Ptr = LD->getBasePtr();
9367 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9368 VT = ST->getMemoryVT();
9369 Ptr = ST->getBasePtr();
9374 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9376 // Post-indexing updates the base, so it's not a valid transform
9377 // if that's not the same as the load's pointer.
9380 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9384 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9385 SelectionDAG &DAG) {
9387 SDValue Op = N->getOperand(0);
9389 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9393 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9394 DAG.getUNDEF(MVT::i32), Op,
9395 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9397 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9398 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9401 void AArch64TargetLowering::ReplaceNodeResults(
9402 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9403 switch (N->getOpcode()) {
9405 llvm_unreachable("Don't know how to custom expand this");
9407 ReplaceBITCASTResults(N, Results, DAG);
9409 case ISD::FP_TO_UINT:
9410 case ISD::FP_TO_SINT:
9411 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9412 // Let normal code take care of it by not adding anything to Results.
9417 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9421 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
9422 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9423 // reciprocal if there are three or more FDIVs.
9427 TargetLoweringBase::LegalizeTypeAction
9428 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9429 MVT SVT = VT.getSimpleVT();
9430 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9431 // v4i16, v2i32 instead of to promote.
9432 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9433 || SVT == MVT::v1f32)
9434 return TypeWidenVector;
9436 return TargetLoweringBase::getPreferredVectorAction(VT);
9439 // Loads and stores less than 128-bits are already atomic; ones above that
9440 // are doomed anyway, so defer to the default libcall and blame the OS when
9442 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9443 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9447 // Loads and stores less than 128-bits are already atomic; ones above that
9448 // are doomed anyway, so defer to the default libcall and blame the OS when
9450 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9451 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9455 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9456 TargetLoweringBase::AtomicRMWExpansionKind
9457 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9458 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9459 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9460 : AtomicRMWExpansionKind::None;
9463 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9467 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9468 AtomicOrdering Ord) const {
9469 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9470 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9471 bool IsAcquire = isAtLeastAcquire(Ord);
9473 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9474 // intrinsic must return {i64, i64} and we have to recombine them into a
9475 // single i128 here.
9476 if (ValTy->getPrimitiveSizeInBits() == 128) {
9478 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9479 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9481 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9482 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9484 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9485 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9486 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9487 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9488 return Builder.CreateOr(
9489 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9492 Type *Tys[] = { Addr->getType() };
9494 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9495 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9497 return Builder.CreateTruncOrBitCast(
9498 Builder.CreateCall(Ldxr, Addr),
9499 cast<PointerType>(Addr->getType())->getElementType());
9502 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9503 Value *Val, Value *Addr,
9504 AtomicOrdering Ord) const {
9505 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9506 bool IsRelease = isAtLeastRelease(Ord);
9508 // Since the intrinsics must have legal type, the i128 intrinsics take two
9509 // parameters: "i64, i64". We must marshal Val into the appropriate form
9511 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9513 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9514 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9515 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9517 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9518 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9519 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9520 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9524 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9525 Type *Tys[] = { Addr->getType() };
9526 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9528 return Builder.CreateCall(Stxr,
9529 {Builder.CreateZExtOrBitCast(
9530 Val, Stxr->getFunctionType()->getParamType(0)),
9534 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9535 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9536 return Ty->isArrayTy();
9539 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,