1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64PerfectShuffle.h"
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
48 static cl::opt<AlignMode>
49 Align(cl::desc("Load/store alignment support"),
50 cl::Hidden, cl::init(NoStrictAlign),
52 clEnumValN(StrictAlign, "aarch64-strict-align",
53 "Disallow all unaligned memory accesses"),
54 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
55 "Allow unaligned memory accesses"),
58 // Place holder until extr generation is tested fully.
60 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
61 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
65 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
66 cl::desc("Allow AArch64 SLI/SRI formation"),
69 //===----------------------------------------------------------------------===//
70 // AArch64 Lowering public interface.
71 //===----------------------------------------------------------------------===//
72 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
73 if (TT.isOSBinFormatMachO())
74 return new AArch64_MachoTargetObjectFile();
76 return new AArch64_ELFTargetObjectFile();
79 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
81 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
84 // we have to make something up. Arbitrarily, choose ZeroOrOne.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // When comparing vectors the result sets the different elements in the
87 // vector to all-one or all-zero.
88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
90 // Set up the register classes.
91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
94 if (Subtarget->hasFPARMv8()) {
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
101 if (Subtarget->hasNEON()) {
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
104 // Someone set us up the NEON.
105 addDRTypeForNEON(MVT::v2f32);
106 addDRTypeForNEON(MVT::v8i8);
107 addDRTypeForNEON(MVT::v4i16);
108 addDRTypeForNEON(MVT::v2i32);
109 addDRTypeForNEON(MVT::v1i64);
110 addDRTypeForNEON(MVT::v1f64);
111 addDRTypeForNEON(MVT::v4f16);
113 addQRTypeForNEON(MVT::v4f32);
114 addQRTypeForNEON(MVT::v2f64);
115 addQRTypeForNEON(MVT::v16i8);
116 addQRTypeForNEON(MVT::v8i16);
117 addQRTypeForNEON(MVT::v4i32);
118 addQRTypeForNEON(MVT::v2i64);
119 addQRTypeForNEON(MVT::v8f16);
122 // Compute derived properties from the register classes
123 computeRegisterProperties();
125 // Provide all sorts of operation actions
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
128 setOperationAction(ISD::SETCC, MVT::i32, Custom);
129 setOperationAction(ISD::SETCC, MVT::i64, Custom);
130 setOperationAction(ISD::SETCC, MVT::f32, Custom);
131 setOperationAction(ISD::SETCC, MVT::f64, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::FREM, MVT::f32, Expand);
153 setOperationAction(ISD::FREM, MVT::f64, Expand);
154 setOperationAction(ISD::FREM, MVT::f80, Expand);
156 // Custom lowering hooks are needed for XOR
157 // to fold it into CSINC/CSINV.
158 setOperationAction(ISD::XOR, MVT::i32, Custom);
159 setOperationAction(ISD::XOR, MVT::i64, Custom);
161 // Virtually no operation on f128 is legal, but LLVM can't expand them when
162 // there's a valid register class, so we need custom operations in most cases.
163 setOperationAction(ISD::FABS, MVT::f128, Expand);
164 setOperationAction(ISD::FADD, MVT::f128, Custom);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
166 setOperationAction(ISD::FCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FDIV, MVT::f128, Custom);
168 setOperationAction(ISD::FMA, MVT::f128, Expand);
169 setOperationAction(ISD::FMUL, MVT::f128, Custom);
170 setOperationAction(ISD::FNEG, MVT::f128, Expand);
171 setOperationAction(ISD::FPOW, MVT::f128, Expand);
172 setOperationAction(ISD::FREM, MVT::f128, Expand);
173 setOperationAction(ISD::FRINT, MVT::f128, Expand);
174 setOperationAction(ISD::FSIN, MVT::f128, Expand);
175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
176 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
177 setOperationAction(ISD::FSUB, MVT::f128, Custom);
178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
179 setOperationAction(ISD::SETCC, MVT::f128, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT, MVT::f128, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
185 // Lowering for many of the conversions is actually specified by the non-f128
186 // type. The LowerXXX function will be trivial when f128 isn't involved.
187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
202 // Variable arguments.
203 setOperationAction(ISD::VASTART, MVT::Other, Custom);
204 setOperationAction(ISD::VAARG, MVT::Other, Custom);
205 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
206 setOperationAction(ISD::VAEND, MVT::Other, Expand);
208 // Variable-sized objects.
209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
213 // Exception handling.
214 // FIXME: These are guesses. Has this been defined yet?
215 setExceptionPointerRegister(AArch64::X0);
216 setExceptionSelectorRegister(AArch64::X1);
218 // Constant pool entries
219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
225 setOperationAction(ISD::ADDC, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i32, Custom);
227 setOperationAction(ISD::SUBC, MVT::i32, Custom);
228 setOperationAction(ISD::SUBE, MVT::i32, Custom);
229 setOperationAction(ISD::ADDC, MVT::i64, Custom);
230 setOperationAction(ISD::ADDE, MVT::i64, Custom);
231 setOperationAction(ISD::SUBC, MVT::i64, Custom);
232 setOperationAction(ISD::SUBE, MVT::i64, Custom);
234 // AArch64 lacks both left-rotate and popcount instructions.
235 setOperationAction(ISD::ROTL, MVT::i32, Expand);
236 setOperationAction(ISD::ROTL, MVT::i64, Expand);
238 // AArch64 doesn't have {U|S}MUL_LOHI.
239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
244 // counterparts, which AArch64 supports directly.
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
251 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
256 setOperationAction(ISD::SREM, MVT::i64, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i32, Expand);
260 setOperationAction(ISD::UREM, MVT::i64, Expand);
262 // Custom lower Add/Sub/Mul with overflow.
263 setOperationAction(ISD::SADDO, MVT::i32, Custom);
264 setOperationAction(ISD::SADDO, MVT::i64, Custom);
265 setOperationAction(ISD::UADDO, MVT::i32, Custom);
266 setOperationAction(ISD::UADDO, MVT::i64, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
268 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
269 setOperationAction(ISD::USUBO, MVT::i32, Custom);
270 setOperationAction(ISD::USUBO, MVT::i64, Custom);
271 setOperationAction(ISD::SMULO, MVT::i32, Custom);
272 setOperationAction(ISD::SMULO, MVT::i64, Custom);
273 setOperationAction(ISD::UMULO, MVT::i32, Custom);
274 setOperationAction(ISD::UMULO, MVT::i64, Custom);
276 setOperationAction(ISD::FSIN, MVT::f32, Expand);
277 setOperationAction(ISD::FSIN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FCOS, MVT::f64, Expand);
280 setOperationAction(ISD::FPOW, MVT::f32, Expand);
281 setOperationAction(ISD::FPOW, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285 // f16 is storage-only, so we promote operations to f32 if we know this is
286 // valid, and ignore them otherwise. The operations not mentioned here will
287 // fail to select, but this is not a major problem as no source language
288 // should be emitting native f16 operations yet.
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FDIV, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FSUB, MVT::f16, Promote);
294 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
296 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
297 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
298 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
299 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
301 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
302 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
307 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
309 // Expand all other v4f16 operations.
310 // FIXME: We could generate better code by promoting some operations to
312 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
315 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
316 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
317 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
319 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
321 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
322 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
323 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
324 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
328 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
329 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
330 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
332 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
334 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
337 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
340 // v8f16 is also a storage-only type, so expand it.
341 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
342 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
345 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
346 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
347 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
349 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
351 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
353 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
354 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
355 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
356 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
360 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
361 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
362 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
363 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
365 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
366 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
368 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
371 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
373 // AArch64 has implementations of a lot of rounding-like FP operations.
374 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
375 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
376 MVT Ty = RoundingTypes[I];
377 setOperationAction(ISD::FFLOOR, Ty, Legal);
378 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
379 setOperationAction(ISD::FCEIL, Ty, Legal);
380 setOperationAction(ISD::FRINT, Ty, Legal);
381 setOperationAction(ISD::FTRUNC, Ty, Legal);
382 setOperationAction(ISD::FROUND, Ty, Legal);
385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
387 if (Subtarget->isTargetMachO()) {
388 // For iOS, we don't want to the normal expansion of a libcall to
389 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
391 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
392 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
394 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
395 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
398 // AArch64 does not have floating-point extending loads, i1 sign-extending
399 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
400 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
401 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
402 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
403 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
404 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
405 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
406 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
407 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
408 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
409 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
410 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
411 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
413 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
414 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
416 // Indexed loads and stores are supported.
417 for (unsigned im = (unsigned)ISD::PRE_INC;
418 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
419 setIndexedLoadAction(im, MVT::i8, Legal);
420 setIndexedLoadAction(im, MVT::i16, Legal);
421 setIndexedLoadAction(im, MVT::i32, Legal);
422 setIndexedLoadAction(im, MVT::i64, Legal);
423 setIndexedLoadAction(im, MVT::f64, Legal);
424 setIndexedLoadAction(im, MVT::f32, Legal);
425 setIndexedStoreAction(im, MVT::i8, Legal);
426 setIndexedStoreAction(im, MVT::i16, Legal);
427 setIndexedStoreAction(im, MVT::i32, Legal);
428 setIndexedStoreAction(im, MVT::i64, Legal);
429 setIndexedStoreAction(im, MVT::f64, Legal);
430 setIndexedStoreAction(im, MVT::f32, Legal);
434 setOperationAction(ISD::TRAP, MVT::Other, Legal);
436 // We combine OR nodes for bitfield operations.
437 setTargetDAGCombine(ISD::OR);
439 // Vector add and sub nodes may conceal a high-half opportunity.
440 // Also, try to fold ADD into CSINC/CSINV..
441 setTargetDAGCombine(ISD::ADD);
442 setTargetDAGCombine(ISD::SUB);
444 setTargetDAGCombine(ISD::XOR);
445 setTargetDAGCombine(ISD::SINT_TO_FP);
446 setTargetDAGCombine(ISD::UINT_TO_FP);
448 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
450 setTargetDAGCombine(ISD::ANY_EXTEND);
451 setTargetDAGCombine(ISD::ZERO_EXTEND);
452 setTargetDAGCombine(ISD::SIGN_EXTEND);
453 setTargetDAGCombine(ISD::BITCAST);
454 setTargetDAGCombine(ISD::CONCAT_VECTORS);
455 setTargetDAGCombine(ISD::STORE);
457 setTargetDAGCombine(ISD::MUL);
459 setTargetDAGCombine(ISD::SELECT);
460 setTargetDAGCombine(ISD::VSELECT);
462 setTargetDAGCombine(ISD::INTRINSIC_VOID);
463 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
464 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
466 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
467 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
468 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
470 setStackPointerRegisterToSaveRestore(AArch64::SP);
472 setSchedulingPreference(Sched::Hybrid);
475 MaskAndBranchFoldingIsLegal = true;
477 setMinFunctionAlignment(2);
479 RequireStrictAlign = (Align == StrictAlign);
481 setHasExtractBitsInsn(true);
483 if (Subtarget->hasNEON()) {
484 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
485 // silliness like this:
486 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
487 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
488 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
489 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
490 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
491 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
492 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
493 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
494 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
495 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
496 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
497 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
498 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
499 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
500 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
501 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
502 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
503 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
504 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
505 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
506 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
507 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
508 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
509 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
510 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
512 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
513 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
514 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
515 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
516 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
518 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
521 // elements smaller than i32, so promote the input to i32 first.
522 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
523 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
524 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
525 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
526 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
527 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
528 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
529 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
530 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
532 // AArch64 doesn't have MUL.2d:
533 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
534 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
535 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
536 // Likewise, narrowing and extending vector loads/stores aren't handled
538 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
539 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
541 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
544 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
551 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
552 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
553 setTruncStoreAction((MVT::SimpleValueType)VT,
554 (MVT::SimpleValueType)InnerVT, Expand);
555 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
556 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
557 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
560 // AArch64 has implementations of a lot of rounding-like FP operations.
561 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
562 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
563 MVT Ty = RoundingVecTypes[I];
564 setOperationAction(ISD::FFLOOR, Ty, Legal);
565 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
566 setOperationAction(ISD::FCEIL, Ty, Legal);
567 setOperationAction(ISD::FRINT, Ty, Legal);
568 setOperationAction(ISD::FTRUNC, Ty, Legal);
569 setOperationAction(ISD::FROUND, Ty, Legal);
573 // Prefer likely predicted branches to selects on out-of-order cores.
574 if (Subtarget->isCortexA57())
575 PredictableSelectIsExpensive = true;
578 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
579 if (VT == MVT::v2f32) {
580 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
581 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
583 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
584 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
585 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
586 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
587 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
589 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
590 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
593 // Mark vector float intrinsics as expand.
594 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
595 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
596 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
597 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
598 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
599 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
600 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
601 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
602 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
603 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
606 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
607 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
608 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
609 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
610 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
611 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
612 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
613 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
614 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
615 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
616 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
617 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
619 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
620 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
621 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
622 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
624 // CNT supports only B element sizes.
625 if (VT != MVT::v8i8 && VT != MVT::v16i8)
626 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
635 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
637 if (Subtarget->isLittleEndian()) {
638 for (unsigned im = (unsigned)ISD::PRE_INC;
639 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
640 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
641 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
646 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
647 addRegisterClass(VT, &AArch64::FPR64RegClass);
648 addTypeForNEON(VT, MVT::v2i32);
651 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
652 addRegisterClass(VT, &AArch64::FPR128RegClass);
653 addTypeForNEON(VT, MVT::v4i32);
656 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
659 return VT.changeVectorElementTypeToInteger();
662 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
663 /// Mask are known to be either zero or one and return them in the
664 /// KnownZero/KnownOne bitsets.
665 void AArch64TargetLowering::computeKnownBitsForTargetNode(
666 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
667 const SelectionDAG &DAG, unsigned Depth) const {
668 switch (Op.getOpcode()) {
671 case AArch64ISD::CSEL: {
672 APInt KnownZero2, KnownOne2;
673 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
674 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
675 KnownZero &= KnownZero2;
676 KnownOne &= KnownOne2;
679 case ISD::INTRINSIC_W_CHAIN: {
680 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
681 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
684 case Intrinsic::aarch64_ldaxr:
685 case Intrinsic::aarch64_ldxr: {
686 unsigned BitWidth = KnownOne.getBitWidth();
687 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
688 unsigned MemBits = VT.getScalarType().getSizeInBits();
689 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
695 case ISD::INTRINSIC_WO_CHAIN:
696 case ISD::INTRINSIC_VOID: {
697 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
701 case Intrinsic::aarch64_neon_umaxv:
702 case Intrinsic::aarch64_neon_uminv: {
703 // Figure out the datatype of the vector operand. The UMINV instruction
704 // will zero extend the result, so we can mark as known zero all the
705 // bits larger than the element datatype. 32-bit or larget doesn't need
706 // this as those are legal types and will be handled by isel directly.
707 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
708 unsigned BitWidth = KnownZero.getBitWidth();
709 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
710 assert(BitWidth >= 8 && "Unexpected width!");
711 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
713 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
714 assert(BitWidth >= 16 && "Unexpected width!");
715 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
725 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
729 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
730 // FIXME: On AArch64, this depends on the type.
731 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
732 // and the offset has to be a multiple of the related size in bytes.
737 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
738 const TargetLibraryInfo *libInfo) const {
739 return AArch64::createFastISel(funcInfo, libInfo);
742 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
746 case AArch64ISD::CALL: return "AArch64ISD::CALL";
747 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
748 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
749 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
750 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
751 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
752 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
753 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
754 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
755 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
756 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
757 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
758 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
759 case AArch64ISD::ADC: return "AArch64ISD::ADC";
760 case AArch64ISD::SBC: return "AArch64ISD::SBC";
761 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
762 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
763 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
764 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
765 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
766 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
767 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
768 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
769 case AArch64ISD::DUP: return "AArch64ISD::DUP";
770 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
771 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
772 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
773 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
774 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
775 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
776 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
777 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
778 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
779 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
780 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
781 case AArch64ISD::BICi: return "AArch64ISD::BICi";
782 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
783 case AArch64ISD::BSL: return "AArch64ISD::BSL";
784 case AArch64ISD::NEG: return "AArch64ISD::NEG";
785 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
786 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
787 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
788 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
789 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
790 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
791 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
792 case AArch64ISD::REV16: return "AArch64ISD::REV16";
793 case AArch64ISD::REV32: return "AArch64ISD::REV32";
794 case AArch64ISD::REV64: return "AArch64ISD::REV64";
795 case AArch64ISD::EXT: return "AArch64ISD::EXT";
796 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
797 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
798 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
799 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
800 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
801 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
802 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
803 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
804 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
805 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
806 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
807 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
808 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
809 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
810 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
811 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
812 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
813 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
814 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
815 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
816 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
817 case AArch64ISD::NOT: return "AArch64ISD::NOT";
818 case AArch64ISD::BIT: return "AArch64ISD::BIT";
819 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
820 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
821 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
822 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
823 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
824 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
825 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
826 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
827 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
828 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
829 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
830 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
831 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
832 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
833 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
834 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
835 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
836 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
837 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
838 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
839 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
840 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
841 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
842 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
843 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
844 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
845 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
846 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
847 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
848 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
849 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
850 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
851 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
852 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
853 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
854 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
859 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
860 MachineBasicBlock *MBB) const {
861 // We materialise the F128CSEL pseudo-instruction as some control flow and a
865 // [... previous instrs leading to comparison ...]
871 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
873 const TargetInstrInfo *TII =
874 getTargetMachine().getSubtargetImpl()->getInstrInfo();
875 MachineFunction *MF = MBB->getParent();
876 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
877 DebugLoc DL = MI->getDebugLoc();
878 MachineFunction::iterator It = MBB;
881 unsigned DestReg = MI->getOperand(0).getReg();
882 unsigned IfTrueReg = MI->getOperand(1).getReg();
883 unsigned IfFalseReg = MI->getOperand(2).getReg();
884 unsigned CondCode = MI->getOperand(3).getImm();
885 bool NZCVKilled = MI->getOperand(4).isKill();
887 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
888 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
889 MF->insert(It, TrueBB);
890 MF->insert(It, EndBB);
892 // Transfer rest of current basic-block to EndBB
893 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
895 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
897 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
898 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
899 MBB->addSuccessor(TrueBB);
900 MBB->addSuccessor(EndBB);
902 // TrueBB falls through to the end.
903 TrueBB->addSuccessor(EndBB);
906 TrueBB->addLiveIn(AArch64::NZCV);
907 EndBB->addLiveIn(AArch64::NZCV);
910 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
916 MI->eraseFromParent();
921 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
922 MachineBasicBlock *BB) const {
923 switch (MI->getOpcode()) {
928 llvm_unreachable("Unexpected instruction for custom inserter!");
930 case AArch64::F128CSEL:
931 return EmitF128CSEL(MI, BB);
933 case TargetOpcode::STACKMAP:
934 case TargetOpcode::PATCHPOINT:
935 return emitPatchPoint(MI, BB);
939 //===----------------------------------------------------------------------===//
940 // AArch64 Lowering private implementation.
941 //===----------------------------------------------------------------------===//
943 //===----------------------------------------------------------------------===//
945 //===----------------------------------------------------------------------===//
947 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
949 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
952 llvm_unreachable("Unknown condition code!");
954 return AArch64CC::NE;
956 return AArch64CC::EQ;
958 return AArch64CC::GT;
960 return AArch64CC::GE;
962 return AArch64CC::LT;
964 return AArch64CC::LE;
966 return AArch64CC::HI;
968 return AArch64CC::HS;
970 return AArch64CC::LO;
972 return AArch64CC::LS;
976 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
977 static void changeFPCCToAArch64CC(ISD::CondCode CC,
978 AArch64CC::CondCode &CondCode,
979 AArch64CC::CondCode &CondCode2) {
980 CondCode2 = AArch64CC::AL;
983 llvm_unreachable("Unknown FP condition!");
986 CondCode = AArch64CC::EQ;
990 CondCode = AArch64CC::GT;
994 CondCode = AArch64CC::GE;
997 CondCode = AArch64CC::MI;
1000 CondCode = AArch64CC::LS;
1003 CondCode = AArch64CC::MI;
1004 CondCode2 = AArch64CC::GT;
1007 CondCode = AArch64CC::VC;
1010 CondCode = AArch64CC::VS;
1013 CondCode = AArch64CC::EQ;
1014 CondCode2 = AArch64CC::VS;
1017 CondCode = AArch64CC::HI;
1020 CondCode = AArch64CC::PL;
1024 CondCode = AArch64CC::LT;
1028 CondCode = AArch64CC::LE;
1032 CondCode = AArch64CC::NE;
1037 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1038 /// CC usable with the vector instructions. Fewer operations are available
1039 /// without a real NZCV register, so we have to use less efficient combinations
1040 /// to get the same effect.
1041 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1042 AArch64CC::CondCode &CondCode,
1043 AArch64CC::CondCode &CondCode2,
1048 // Mostly the scalar mappings work fine.
1049 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1052 Invert = true; // Fallthrough
1054 CondCode = AArch64CC::MI;
1055 CondCode2 = AArch64CC::GE;
1062 // All of the compare-mask comparisons are ordered, but we can switch
1063 // between the two by a double inversion. E.g. ULE == !OGT.
1065 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1070 static bool isLegalArithImmed(uint64_t C) {
1071 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1072 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1075 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1076 SDLoc dl, SelectionDAG &DAG) {
1077 EVT VT = LHS.getValueType();
1079 if (VT.isFloatingPoint())
1080 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1082 // The CMP instruction is just an alias for SUBS, and representing it as
1083 // SUBS means that it's possible to get CSE with subtract operations.
1084 // A later phase can perform the optimization of setting the destination
1085 // register to WZR/XZR if it ends up being unused.
1086 unsigned Opcode = AArch64ISD::SUBS;
1088 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1089 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1090 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1091 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1092 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1093 // can be set differently by this operation. It comes down to whether
1094 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1095 // everything is fine. If not then the optimization is wrong. Thus general
1096 // comparisons are only valid if op2 != 0.
1098 // So, finally, the only LLVM-native comparisons that don't mention C and V
1099 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1100 // the absence of information about op2.
1101 Opcode = AArch64ISD::ADDS;
1102 RHS = RHS.getOperand(1);
1103 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1104 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1105 !isUnsignedIntSetCC(CC)) {
1106 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1107 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1108 // of the signed comparisons.
1109 Opcode = AArch64ISD::ANDS;
1110 RHS = LHS.getOperand(1);
1111 LHS = LHS.getOperand(0);
1114 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1118 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1119 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1120 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1121 EVT VT = RHS.getValueType();
1122 uint64_t C = RHSC->getZExtValue();
1123 if (!isLegalArithImmed(C)) {
1124 // Constant does not fit, try adjusting it by one?
1130 if ((VT == MVT::i32 && C != 0x80000000 &&
1131 isLegalArithImmed((uint32_t)(C - 1))) ||
1132 (VT == MVT::i64 && C != 0x80000000ULL &&
1133 isLegalArithImmed(C - 1ULL))) {
1134 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1135 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1136 RHS = DAG.getConstant(C, VT);
1141 if ((VT == MVT::i32 && C != 0 &&
1142 isLegalArithImmed((uint32_t)(C - 1))) ||
1143 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1144 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1145 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1146 RHS = DAG.getConstant(C, VT);
1151 if ((VT == MVT::i32 && C != 0x7fffffff &&
1152 isLegalArithImmed((uint32_t)(C + 1))) ||
1153 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1154 isLegalArithImmed(C + 1ULL))) {
1155 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1156 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1157 RHS = DAG.getConstant(C, VT);
1162 if ((VT == MVT::i32 && C != 0xffffffff &&
1163 isLegalArithImmed((uint32_t)(C + 1))) ||
1164 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1165 isLegalArithImmed(C + 1ULL))) {
1166 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1167 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1168 RHS = DAG.getConstant(C, VT);
1175 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1176 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1177 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1181 static std::pair<SDValue, SDValue>
1182 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1183 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1184 "Unsupported value type");
1185 SDValue Value, Overflow;
1187 SDValue LHS = Op.getOperand(0);
1188 SDValue RHS = Op.getOperand(1);
1190 switch (Op.getOpcode()) {
1192 llvm_unreachable("Unknown overflow instruction!");
1194 Opc = AArch64ISD::ADDS;
1198 Opc = AArch64ISD::ADDS;
1202 Opc = AArch64ISD::SUBS;
1206 Opc = AArch64ISD::SUBS;
1209 // Multiply needs a little bit extra work.
1213 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1214 if (Op.getValueType() == MVT::i32) {
1215 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1216 // For a 32 bit multiply with overflow check we want the instruction
1217 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1218 // need to generate the following pattern:
1219 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1220 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1221 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1222 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1223 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1224 DAG.getConstant(0, MVT::i64));
1225 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1226 // operation. We need to clear out the upper 32 bits, because we used a
1227 // widening multiply that wrote all 64 bits. In the end this should be a
1229 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1231 // The signed overflow check requires more than just a simple check for
1232 // any bit set in the upper 32 bits of the result. These bits could be
1233 // just the sign bits of a negative number. To perform the overflow
1234 // check we have to arithmetic shift right the 32nd bit of the result by
1235 // 31 bits. Then we compare the result to the upper 32 bits.
1236 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1237 DAG.getConstant(32, MVT::i64));
1238 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1239 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1240 DAG.getConstant(31, MVT::i64));
1241 // It is important that LowerBits is last, otherwise the arithmetic
1242 // shift will not be folded into the compare (SUBS).
1243 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1244 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1247 // The overflow check for unsigned multiply is easy. We only need to
1248 // check if any of the upper 32 bits are set. This can be done with a
1249 // CMP (shifted register). For that we need to generate the following
1251 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1252 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1253 DAG.getConstant(32, MVT::i64));
1254 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1256 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1257 UpperBits).getValue(1);
1261 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1262 // For the 64 bit multiply
1263 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1265 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1266 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1267 DAG.getConstant(63, MVT::i64));
1268 // It is important that LowerBits is last, otherwise the arithmetic
1269 // shift will not be folded into the compare (SUBS).
1270 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1271 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1274 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1275 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1277 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1278 UpperBits).getValue(1);
1285 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1287 // Emit the AArch64 operation with overflow check.
1288 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1289 Overflow = Value.getValue(1);
1291 return std::make_pair(Value, Overflow);
1294 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1295 RTLIB::Libcall Call) const {
1296 SmallVector<SDValue, 2> Ops;
1297 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1298 Ops.push_back(Op.getOperand(i));
1300 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1304 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1305 SDValue Sel = Op.getOperand(0);
1306 SDValue Other = Op.getOperand(1);
1308 // If neither operand is a SELECT_CC, give up.
1309 if (Sel.getOpcode() != ISD::SELECT_CC)
1310 std::swap(Sel, Other);
1311 if (Sel.getOpcode() != ISD::SELECT_CC)
1314 // The folding we want to perform is:
1315 // (xor x, (select_cc a, b, cc, 0, -1) )
1317 // (csel x, (xor x, -1), cc ...)
1319 // The latter will get matched to a CSINV instruction.
1321 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1322 SDValue LHS = Sel.getOperand(0);
1323 SDValue RHS = Sel.getOperand(1);
1324 SDValue TVal = Sel.getOperand(2);
1325 SDValue FVal = Sel.getOperand(3);
1328 // FIXME: This could be generalized to non-integer comparisons.
1329 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1332 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1333 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1335 // The the values aren't constants, this isn't the pattern we're looking for.
1336 if (!CFVal || !CTVal)
1339 // We can commute the SELECT_CC by inverting the condition. This
1340 // might be needed to make this fit into a CSINV pattern.
1341 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1342 std::swap(TVal, FVal);
1343 std::swap(CTVal, CFVal);
1344 CC = ISD::getSetCCInverse(CC, true);
1347 // If the constants line up, perform the transform!
1348 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1350 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1353 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1354 DAG.getConstant(-1ULL, Other.getValueType()));
1356 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1363 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1364 EVT VT = Op.getValueType();
1366 // Let legalize expand this if it isn't a legal type yet.
1367 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1370 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1373 bool ExtraOp = false;
1374 switch (Op.getOpcode()) {
1376 llvm_unreachable("Invalid code");
1378 Opc = AArch64ISD::ADDS;
1381 Opc = AArch64ISD::SUBS;
1384 Opc = AArch64ISD::ADCS;
1388 Opc = AArch64ISD::SBCS;
1394 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1395 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1399 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1400 // Let legalize expand this if it isn't a legal type yet.
1401 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1404 AArch64CC::CondCode CC;
1405 // The actual operation that sets the overflow or carry flag.
1406 SDValue Value, Overflow;
1407 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1409 // We use 0 and 1 as false and true values.
1410 SDValue TVal = DAG.getConstant(1, MVT::i32);
1411 SDValue FVal = DAG.getConstant(0, MVT::i32);
1413 // We use an inverted condition, because the conditional select is inverted
1414 // too. This will allow it to be selected to a single instruction:
1415 // CSINC Wd, WZR, WZR, invert(cond).
1416 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1417 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1420 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1421 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1424 // Prefetch operands are:
1425 // 1: Address to prefetch
1427 // 3: int locality (0 = no locality ... 3 = extreme locality)
1428 // 4: bool isDataCache
1429 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1431 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1432 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1433 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1435 bool IsStream = !Locality;
1436 // When the locality number is set
1438 // The front-end should have filtered out the out-of-range values
1439 assert(Locality <= 3 && "Prefetch locality out-of-range");
1440 // The locality degree is the opposite of the cache speed.
1441 // Put the number the other way around.
1442 // The encoding starts at 0 for level 1
1443 Locality = 3 - Locality;
1446 // built the mask value encoding the expected behavior.
1447 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1448 (!IsData << 3) | // IsDataCache bit
1449 (Locality << 1) | // Cache level bits
1450 (unsigned)IsStream; // Stream bit
1451 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1452 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1455 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1456 SelectionDAG &DAG) const {
1457 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1460 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1462 return LowerF128Call(Op, DAG, LC);
1465 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1466 SelectionDAG &DAG) const {
1467 if (Op.getOperand(0).getValueType() != MVT::f128) {
1468 // It's legal except when f128 is involved
1473 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1475 // FP_ROUND node has a second operand indicating whether it is known to be
1476 // precise. That doesn't take part in the LibCall so we can't directly use
1478 SDValue SrcVal = Op.getOperand(0);
1479 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1480 /*isSigned*/ false, SDLoc(Op)).first;
1483 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1484 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1485 // Any additional optimization in this function should be recorded
1486 // in the cost tables.
1487 EVT InVT = Op.getOperand(0).getValueType();
1488 EVT VT = Op.getValueType();
1490 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1493 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1495 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1498 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1501 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1502 VT.getVectorNumElements());
1503 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1504 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1507 // Type changing conversions are illegal.
1511 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1512 SelectionDAG &DAG) const {
1513 if (Op.getOperand(0).getValueType().isVector())
1514 return LowerVectorFP_TO_INT(Op, DAG);
1516 if (Op.getOperand(0).getValueType() != MVT::f128) {
1517 // It's legal except when f128 is involved
1522 if (Op.getOpcode() == ISD::FP_TO_SINT)
1523 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1525 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1527 SmallVector<SDValue, 2> Ops;
1528 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1529 Ops.push_back(Op.getOperand(i));
1531 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1535 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1536 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1537 // Any additional optimization in this function should be recorded
1538 // in the cost tables.
1539 EVT VT = Op.getValueType();
1541 SDValue In = Op.getOperand(0);
1542 EVT InVT = In.getValueType();
1544 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1546 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1547 InVT.getVectorNumElements());
1548 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1549 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1552 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1554 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1555 EVT CastVT = VT.changeVectorElementTypeToInteger();
1556 In = DAG.getNode(CastOpc, dl, CastVT, In);
1557 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1563 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1564 SelectionDAG &DAG) const {
1565 if (Op.getValueType().isVector())
1566 return LowerVectorINT_TO_FP(Op, DAG);
1568 // i128 conversions are libcalls.
1569 if (Op.getOperand(0).getValueType() == MVT::i128)
1572 // Other conversions are legal, unless it's to the completely software-based
1574 if (Op.getValueType() != MVT::f128)
1578 if (Op.getOpcode() == ISD::SINT_TO_FP)
1579 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1581 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1583 return LowerF128Call(Op, DAG, LC);
1586 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1587 SelectionDAG &DAG) const {
1588 // For iOS, we want to call an alternative entry point: __sincos_stret,
1589 // which returns the values in two S / D registers.
1591 SDValue Arg = Op.getOperand(0);
1592 EVT ArgVT = Arg.getValueType();
1593 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1600 Entry.isSExt = false;
1601 Entry.isZExt = false;
1602 Args.push_back(Entry);
1604 const char *LibcallName =
1605 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1606 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1608 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1609 TargetLowering::CallLoweringInfo CLI(DAG);
1610 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1611 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1613 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1614 return CallResult.first;
1617 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1618 if (Op.getValueType() != MVT::f16)
1621 assert(Op.getOperand(0).getValueType() == MVT::i16);
1624 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1625 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1627 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1628 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1633 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1634 SelectionDAG &DAG) const {
1635 switch (Op.getOpcode()) {
1637 llvm_unreachable("unimplemented operand");
1640 return LowerBITCAST(Op, DAG);
1641 case ISD::GlobalAddress:
1642 return LowerGlobalAddress(Op, DAG);
1643 case ISD::GlobalTLSAddress:
1644 return LowerGlobalTLSAddress(Op, DAG);
1646 return LowerSETCC(Op, DAG);
1648 return LowerBR_CC(Op, DAG);
1650 return LowerSELECT(Op, DAG);
1651 case ISD::SELECT_CC:
1652 return LowerSELECT_CC(Op, DAG);
1653 case ISD::JumpTable:
1654 return LowerJumpTable(Op, DAG);
1655 case ISD::ConstantPool:
1656 return LowerConstantPool(Op, DAG);
1657 case ISD::BlockAddress:
1658 return LowerBlockAddress(Op, DAG);
1660 return LowerVASTART(Op, DAG);
1662 return LowerVACOPY(Op, DAG);
1664 return LowerVAARG(Op, DAG);
1669 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1676 return LowerXALUO(Op, DAG);
1678 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1680 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1682 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1684 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1686 return LowerFP_ROUND(Op, DAG);
1687 case ISD::FP_EXTEND:
1688 return LowerFP_EXTEND(Op, DAG);
1689 case ISD::FRAMEADDR:
1690 return LowerFRAMEADDR(Op, DAG);
1691 case ISD::RETURNADDR:
1692 return LowerRETURNADDR(Op, DAG);
1693 case ISD::INSERT_VECTOR_ELT:
1694 return LowerINSERT_VECTOR_ELT(Op, DAG);
1695 case ISD::EXTRACT_VECTOR_ELT:
1696 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1697 case ISD::BUILD_VECTOR:
1698 return LowerBUILD_VECTOR(Op, DAG);
1699 case ISD::VECTOR_SHUFFLE:
1700 return LowerVECTOR_SHUFFLE(Op, DAG);
1701 case ISD::EXTRACT_SUBVECTOR:
1702 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1706 return LowerVectorSRA_SRL_SHL(Op, DAG);
1707 case ISD::SHL_PARTS:
1708 return LowerShiftLeftParts(Op, DAG);
1709 case ISD::SRL_PARTS:
1710 case ISD::SRA_PARTS:
1711 return LowerShiftRightParts(Op, DAG);
1713 return LowerCTPOP(Op, DAG);
1714 case ISD::FCOPYSIGN:
1715 return LowerFCOPYSIGN(Op, DAG);
1717 return LowerVectorAND(Op, DAG);
1719 return LowerVectorOR(Op, DAG);
1721 return LowerXOR(Op, DAG);
1723 return LowerPREFETCH(Op, DAG);
1724 case ISD::SINT_TO_FP:
1725 case ISD::UINT_TO_FP:
1726 return LowerINT_TO_FP(Op, DAG);
1727 case ISD::FP_TO_SINT:
1728 case ISD::FP_TO_UINT:
1729 return LowerFP_TO_INT(Op, DAG);
1731 return LowerFSINCOS(Op, DAG);
1735 /// getFunctionAlignment - Return the Log2 alignment of this function.
1736 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1740 //===----------------------------------------------------------------------===//
1741 // Calling Convention Implementation
1742 //===----------------------------------------------------------------------===//
1744 #include "AArch64GenCallingConv.inc"
1746 /// Selects the correct CCAssignFn for a the given CallingConvention
1748 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1749 bool IsVarArg) const {
1752 llvm_unreachable("Unsupported calling convention.");
1753 case CallingConv::WebKit_JS:
1754 return CC_AArch64_WebKit_JS;
1755 case CallingConv::C:
1756 case CallingConv::Fast:
1757 if (!Subtarget->isTargetDarwin())
1758 return CC_AArch64_AAPCS;
1759 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1763 SDValue AArch64TargetLowering::LowerFormalArguments(
1764 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1765 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1766 SmallVectorImpl<SDValue> &InVals) const {
1767 MachineFunction &MF = DAG.getMachineFunction();
1768 MachineFrameInfo *MFI = MF.getFrameInfo();
1770 // Assign locations to all of the incoming arguments.
1771 SmallVector<CCValAssign, 16> ArgLocs;
1772 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1775 // At this point, Ins[].VT may already be promoted to i32. To correctly
1776 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1777 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1778 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1779 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1781 unsigned NumArgs = Ins.size();
1782 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1783 unsigned CurArgIdx = 0;
1784 for (unsigned i = 0; i != NumArgs; ++i) {
1785 MVT ValVT = Ins[i].VT;
1786 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1787 CurArgIdx = Ins[i].OrigArgIndex;
1789 // Get type of the original argument.
1790 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1791 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1792 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1793 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1795 else if (ActualMVT == MVT::i16)
1798 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1800 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1801 assert(!Res && "Call operand has unhandled type");
1804 assert(ArgLocs.size() == Ins.size());
1805 SmallVector<SDValue, 16> ArgValues;
1806 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1807 CCValAssign &VA = ArgLocs[i];
1809 if (Ins[i].Flags.isByVal()) {
1810 // Byval is used for HFAs in the PCS, but the system should work in a
1811 // non-compliant manner for larger structs.
1812 EVT PtrTy = getPointerTy();
1813 int Size = Ins[i].Flags.getByValSize();
1814 unsigned NumRegs = (Size + 7) / 8;
1816 // FIXME: This works on big-endian for composite byvals, which are the common
1817 // case. It should also work for fundamental types too.
1819 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1820 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1821 InVals.push_back(FrameIdxN);
1826 if (VA.isRegLoc()) {
1827 // Arguments stored in registers.
1828 EVT RegVT = VA.getLocVT();
1831 const TargetRegisterClass *RC;
1833 if (RegVT == MVT::i32)
1834 RC = &AArch64::GPR32RegClass;
1835 else if (RegVT == MVT::i64)
1836 RC = &AArch64::GPR64RegClass;
1837 else if (RegVT == MVT::f16)
1838 RC = &AArch64::FPR16RegClass;
1839 else if (RegVT == MVT::f32)
1840 RC = &AArch64::FPR32RegClass;
1841 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1842 RC = &AArch64::FPR64RegClass;
1843 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1844 RC = &AArch64::FPR128RegClass;
1846 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1848 // Transform the arguments in physical registers into virtual ones.
1849 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1850 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1852 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1853 // to 64 bits. Insert an assert[sz]ext to capture this, then
1854 // truncate to the right size.
1855 switch (VA.getLocInfo()) {
1857 llvm_unreachable("Unknown loc info!");
1858 case CCValAssign::Full:
1860 case CCValAssign::BCvt:
1861 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1863 case CCValAssign::AExt:
1864 case CCValAssign::SExt:
1865 case CCValAssign::ZExt:
1866 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1867 // nodes after our lowering.
1868 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1872 InVals.push_back(ArgValue);
1874 } else { // VA.isRegLoc()
1875 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1876 unsigned ArgOffset = VA.getLocMemOffset();
1877 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
1879 uint32_t BEAlign = 0;
1880 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1881 BEAlign = 8 - ArgSize;
1883 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1885 // Create load nodes to retrieve arguments from the stack.
1886 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1889 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1890 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1891 MVT MemVT = VA.getValVT();
1893 switch (VA.getLocInfo()) {
1896 case CCValAssign::BCvt:
1897 MemVT = VA.getLocVT();
1899 case CCValAssign::SExt:
1900 ExtType = ISD::SEXTLOAD;
1902 case CCValAssign::ZExt:
1903 ExtType = ISD::ZEXTLOAD;
1905 case CCValAssign::AExt:
1906 ExtType = ISD::EXTLOAD;
1910 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1911 MachinePointerInfo::getFixedStack(FI),
1912 MemVT, false, false, false, 0, nullptr);
1914 InVals.push_back(ArgValue);
1920 if (!Subtarget->isTargetDarwin()) {
1921 // The AAPCS variadic function ABI is identical to the non-variadic
1922 // one. As a result there may be more arguments in registers and we should
1923 // save them for future reference.
1924 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1927 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1928 // This will point to the next argument passed via stack.
1929 unsigned StackOffset = CCInfo.getNextStackOffset();
1930 // We currently pass all varargs at 8-byte alignment.
1931 StackOffset = ((StackOffset + 7) & ~7);
1932 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1935 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1936 unsigned StackArgSize = CCInfo.getNextStackOffset();
1937 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1938 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1939 // This is a non-standard ABI so by fiat I say we're allowed to make full
1940 // use of the stack area to be popped, which must be aligned to 16 bytes in
1942 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1944 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1945 // a multiple of 16.
1946 FuncInfo->setArgumentStackToRestore(StackArgSize);
1948 // This realignment carries over to the available bytes below. Our own
1949 // callers will guarantee the space is free by giving an aligned value to
1952 // Even if we're not expected to free up the space, it's useful to know how
1953 // much is there while considering tail calls (because we can reuse it).
1954 FuncInfo->setBytesInStackArgArea(StackArgSize);
1959 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1960 SelectionDAG &DAG, SDLoc DL,
1961 SDValue &Chain) const {
1962 MachineFunction &MF = DAG.getMachineFunction();
1963 MachineFrameInfo *MFI = MF.getFrameInfo();
1964 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1966 SmallVector<SDValue, 8> MemOps;
1968 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1969 AArch64::X3, AArch64::X4, AArch64::X5,
1970 AArch64::X6, AArch64::X7 };
1971 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1972 unsigned FirstVariadicGPR =
1973 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1975 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1977 if (GPRSaveSize != 0) {
1978 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1980 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1982 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1983 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1984 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1986 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1987 MachinePointerInfo::getStack(i * 8), false, false, 0);
1988 MemOps.push_back(Store);
1989 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1990 DAG.getConstant(8, getPointerTy()));
1993 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1994 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1996 if (Subtarget->hasFPARMv8()) {
1997 static const MCPhysReg FPRArgRegs[] = {
1998 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1999 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2000 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2001 unsigned FirstVariadicFPR =
2002 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
2004 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2006 if (FPRSaveSize != 0) {
2007 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2009 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2011 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2012 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2013 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2016 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2017 MachinePointerInfo::getStack(i * 16), false, false, 0);
2018 MemOps.push_back(Store);
2019 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2020 DAG.getConstant(16, getPointerTy()));
2023 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2024 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2027 if (!MemOps.empty()) {
2028 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2032 /// LowerCallResult - Lower the result values of a call into the
2033 /// appropriate copies out of appropriate physical registers.
2034 SDValue AArch64TargetLowering::LowerCallResult(
2035 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2036 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2037 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2038 SDValue ThisVal) const {
2039 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2040 ? RetCC_AArch64_WebKit_JS
2041 : RetCC_AArch64_AAPCS;
2042 // Assign locations to each value returned by this call.
2043 SmallVector<CCValAssign, 16> RVLocs;
2044 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2046 CCInfo.AnalyzeCallResult(Ins, RetCC);
2048 // Copy all of the result registers out of their specified physreg.
2049 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2050 CCValAssign VA = RVLocs[i];
2052 // Pass 'this' value directly from the argument to return value, to avoid
2053 // reg unit interference
2054 if (i == 0 && isThisReturn) {
2055 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2056 "unexpected return calling convention register assignment");
2057 InVals.push_back(ThisVal);
2062 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2063 Chain = Val.getValue(1);
2064 InFlag = Val.getValue(2);
2066 switch (VA.getLocInfo()) {
2068 llvm_unreachable("Unknown loc info!");
2069 case CCValAssign::Full:
2071 case CCValAssign::BCvt:
2072 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2076 InVals.push_back(Val);
2082 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2083 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2084 bool isCalleeStructRet, bool isCallerStructRet,
2085 const SmallVectorImpl<ISD::OutputArg> &Outs,
2086 const SmallVectorImpl<SDValue> &OutVals,
2087 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2088 // For CallingConv::C this function knows whether the ABI needs
2089 // changing. That's not true for other conventions so they will have to opt in
2091 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2094 const MachineFunction &MF = DAG.getMachineFunction();
2095 const Function *CallerF = MF.getFunction();
2096 CallingConv::ID CallerCC = CallerF->getCallingConv();
2097 bool CCMatch = CallerCC == CalleeCC;
2099 // Byval parameters hand the function a pointer directly into the stack area
2100 // we want to reuse during a tail call. Working around this *is* possible (see
2101 // X86) but less efficient and uglier in LowerCall.
2102 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2103 e = CallerF->arg_end();
2105 if (i->hasByValAttr())
2108 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2109 if (IsTailCallConvention(CalleeCC) && CCMatch)
2114 // Externally-defined functions with weak linkage should not be
2115 // tail-called on AArch64 when the OS does not support dynamic
2116 // pre-emption of symbols, as the AAELF spec requires normal calls
2117 // to undefined weak functions to be replaced with a NOP or jump to the
2118 // next instruction. The behaviour of branch instructions in this
2119 // situation (as used for tail calls) is implementation-defined, so we
2120 // cannot rely on the linker replacing the tail call with a return.
2121 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2122 const GlobalValue *GV = G->getGlobal();
2123 if (GV->hasExternalWeakLinkage())
2127 // Now we search for cases where we can use a tail call without changing the
2128 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2131 // I want anyone implementing a new calling convention to think long and hard
2132 // about this assert.
2133 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2134 "Unexpected variadic calling convention");
2136 if (isVarArg && !Outs.empty()) {
2137 // At least two cases here: if caller is fastcc then we can't have any
2138 // memory arguments (we'd be expected to clean up the stack afterwards). If
2139 // caller is C then we could potentially use its argument area.
2141 // FIXME: for now we take the most conservative of these in both cases:
2142 // disallow all variadic memory operands.
2143 SmallVector<CCValAssign, 16> ArgLocs;
2144 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2147 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2148 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2149 if (!ArgLocs[i].isRegLoc())
2153 // If the calling conventions do not match, then we'd better make sure the
2154 // results are returned in the same way as what the caller expects.
2156 SmallVector<CCValAssign, 16> RVLocs1;
2157 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2159 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2161 SmallVector<CCValAssign, 16> RVLocs2;
2162 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2164 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2166 if (RVLocs1.size() != RVLocs2.size())
2168 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2169 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2171 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2173 if (RVLocs1[i].isRegLoc()) {
2174 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2177 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2183 // Nothing more to check if the callee is taking no arguments
2187 SmallVector<CCValAssign, 16> ArgLocs;
2188 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2191 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2193 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2195 // If the stack arguments for this call would fit into our own save area then
2196 // the call can be made tail.
2197 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2200 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2202 MachineFrameInfo *MFI,
2203 int ClobberedFI) const {
2204 SmallVector<SDValue, 8> ArgChains;
2205 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2206 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2208 // Include the original chain at the beginning of the list. When this is
2209 // used by target LowerCall hooks, this helps legalize find the
2210 // CALLSEQ_BEGIN node.
2211 ArgChains.push_back(Chain);
2213 // Add a chain value for each stack argument corresponding
2214 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2215 UE = DAG.getEntryNode().getNode()->use_end();
2217 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2218 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2219 if (FI->getIndex() < 0) {
2220 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2221 int64_t InLastByte = InFirstByte;
2222 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2224 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2225 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2226 ArgChains.push_back(SDValue(L, 1));
2229 // Build a tokenfactor for all the chains.
2230 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2233 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2234 bool TailCallOpt) const {
2235 return CallCC == CallingConv::Fast && TailCallOpt;
2238 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2239 return CallCC == CallingConv::Fast;
2242 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2243 /// and add input and output parameter nodes.
2245 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2246 SmallVectorImpl<SDValue> &InVals) const {
2247 SelectionDAG &DAG = CLI.DAG;
2249 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2250 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2251 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2252 SDValue Chain = CLI.Chain;
2253 SDValue Callee = CLI.Callee;
2254 bool &IsTailCall = CLI.IsTailCall;
2255 CallingConv::ID CallConv = CLI.CallConv;
2256 bool IsVarArg = CLI.IsVarArg;
2258 MachineFunction &MF = DAG.getMachineFunction();
2259 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2260 bool IsThisReturn = false;
2262 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2263 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2264 bool IsSibCall = false;
2267 // Check if it's really possible to do a tail call.
2268 IsTailCall = isEligibleForTailCallOptimization(
2269 Callee, CallConv, IsVarArg, IsStructRet,
2270 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2271 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2272 report_fatal_error("failed to perform tail call elimination on a call "
2273 "site marked musttail");
2275 // A sibling call is one where we're under the usual C ABI and not planning
2276 // to change that but can still do a tail call:
2277 if (!TailCallOpt && IsTailCall)
2284 // Analyze operands of the call, assigning locations to each operand.
2285 SmallVector<CCValAssign, 16> ArgLocs;
2286 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2290 // Handle fixed and variable vector arguments differently.
2291 // Variable vector arguments always go into memory.
2292 unsigned NumArgs = Outs.size();
2294 for (unsigned i = 0; i != NumArgs; ++i) {
2295 MVT ArgVT = Outs[i].VT;
2296 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2297 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2298 /*IsVarArg=*/ !Outs[i].IsFixed);
2299 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2300 assert(!Res && "Call operand has unhandled type");
2304 // At this point, Outs[].VT may already be promoted to i32. To correctly
2305 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2306 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2307 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2308 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2310 unsigned NumArgs = Outs.size();
2311 for (unsigned i = 0; i != NumArgs; ++i) {
2312 MVT ValVT = Outs[i].VT;
2313 // Get type of the original argument.
2314 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2315 /*AllowUnknown*/ true);
2316 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2317 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2318 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2319 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2321 else if (ActualMVT == MVT::i16)
2324 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2325 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2326 assert(!Res && "Call operand has unhandled type");
2331 // Get a count of how many bytes are to be pushed on the stack.
2332 unsigned NumBytes = CCInfo.getNextStackOffset();
2335 // Since we're not changing the ABI to make this a tail call, the memory
2336 // operands are already available in the caller's incoming argument space.
2340 // FPDiff is the byte offset of the call's argument area from the callee's.
2341 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2342 // by this amount for a tail call. In a sibling call it must be 0 because the
2343 // caller will deallocate the entire stack and the callee still expects its
2344 // arguments to begin at SP+0. Completely unused for non-tail calls.
2347 if (IsTailCall && !IsSibCall) {
2348 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2350 // Since callee will pop argument stack as a tail call, we must keep the
2351 // popped size 16-byte aligned.
2352 NumBytes = RoundUpToAlignment(NumBytes, 16);
2354 // FPDiff will be negative if this tail call requires more space than we
2355 // would automatically have in our incoming argument space. Positive if we
2356 // can actually shrink the stack.
2357 FPDiff = NumReusableBytes - NumBytes;
2359 // The stack pointer must be 16-byte aligned at all times it's used for a
2360 // memory operation, which in practice means at *all* times and in
2361 // particular across call boundaries. Therefore our own arguments started at
2362 // a 16-byte aligned SP and the delta applied for the tail call should
2363 // satisfy the same constraint.
2364 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2367 // Adjust the stack pointer for the new arguments...
2368 // These operations are automatically eliminated by the prolog/epilog pass
2371 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2373 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2375 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2376 SmallVector<SDValue, 8> MemOpChains;
2378 // Walk the register/memloc assignments, inserting copies/loads.
2379 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2380 ++i, ++realArgIdx) {
2381 CCValAssign &VA = ArgLocs[i];
2382 SDValue Arg = OutVals[realArgIdx];
2383 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2385 // Promote the value if needed.
2386 switch (VA.getLocInfo()) {
2388 llvm_unreachable("Unknown loc info!");
2389 case CCValAssign::Full:
2391 case CCValAssign::SExt:
2392 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2394 case CCValAssign::ZExt:
2395 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2397 case CCValAssign::AExt:
2398 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2399 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2400 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2401 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2403 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2405 case CCValAssign::BCvt:
2406 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2408 case CCValAssign::FPExt:
2409 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2413 if (VA.isRegLoc()) {
2414 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2415 assert(VA.getLocVT() == MVT::i64 &&
2416 "unexpected calling convention register assignment");
2417 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2418 "unexpected use of 'returned'");
2419 IsThisReturn = true;
2421 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2423 assert(VA.isMemLoc());
2426 MachinePointerInfo DstInfo;
2428 // FIXME: This works on big-endian for composite byvals, which are the
2429 // common case. It should also work for fundamental types too.
2430 uint32_t BEAlign = 0;
2431 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2432 : VA.getValVT().getSizeInBits();
2433 OpSize = (OpSize + 7) / 8;
2434 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2436 BEAlign = 8 - OpSize;
2438 unsigned LocMemOffset = VA.getLocMemOffset();
2439 int32_t Offset = LocMemOffset + BEAlign;
2440 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2441 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2444 Offset = Offset + FPDiff;
2445 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2447 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2448 DstInfo = MachinePointerInfo::getFixedStack(FI);
2450 // Make sure any stack arguments overlapping with where we're storing
2451 // are loaded before this eventual operation. Otherwise they'll be
2453 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2455 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2457 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2458 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2461 if (Outs[i].Flags.isByVal()) {
2463 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2464 SDValue Cpy = DAG.getMemcpy(
2465 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2467 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2469 MemOpChains.push_back(Cpy);
2471 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2472 // promoted to a legal register type i32, we should truncate Arg back to
2474 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2475 VA.getValVT() == MVT::i16)
2476 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2479 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2480 MemOpChains.push_back(Store);
2485 if (!MemOpChains.empty())
2486 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2488 // Build a sequence of copy-to-reg nodes chained together with token chain
2489 // and flag operands which copy the outgoing args into the appropriate regs.
2491 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2492 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2493 RegsToPass[i].second, InFlag);
2494 InFlag = Chain.getValue(1);
2497 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2498 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2499 // node so that legalize doesn't hack it.
2500 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2501 Subtarget->isTargetMachO()) {
2502 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2503 const GlobalValue *GV = G->getGlobal();
2504 bool InternalLinkage = GV->hasInternalLinkage();
2505 if (InternalLinkage)
2506 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2508 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2510 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2512 } else if (ExternalSymbolSDNode *S =
2513 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2514 const char *Sym = S->getSymbol();
2516 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2517 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2519 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2520 const GlobalValue *GV = G->getGlobal();
2521 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2522 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2523 const char *Sym = S->getSymbol();
2524 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2527 // We don't usually want to end the call-sequence here because we would tidy
2528 // the frame up *after* the call, however in the ABI-changing tail-call case
2529 // we've carefully laid out the parameters so that when sp is reset they'll be
2530 // in the correct location.
2531 if (IsTailCall && !IsSibCall) {
2532 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2533 DAG.getIntPtrConstant(0, true), InFlag, DL);
2534 InFlag = Chain.getValue(1);
2537 std::vector<SDValue> Ops;
2538 Ops.push_back(Chain);
2539 Ops.push_back(Callee);
2542 // Each tail call may have to adjust the stack by a different amount, so
2543 // this information must travel along with the operation for eventual
2544 // consumption by emitEpilogue.
2545 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2548 // Add argument registers to the end of the list so that they are known live
2550 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2551 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2552 RegsToPass[i].second.getValueType()));
2554 // Add a register mask operand representing the call-preserved registers.
2555 const uint32_t *Mask;
2556 const TargetRegisterInfo *TRI =
2557 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2558 const AArch64RegisterInfo *ARI =
2559 static_cast<const AArch64RegisterInfo *>(TRI);
2561 // For 'this' returns, use the X0-preserving mask if applicable
2562 Mask = ARI->getThisReturnPreservedMask(CallConv);
2564 IsThisReturn = false;
2565 Mask = ARI->getCallPreservedMask(CallConv);
2568 Mask = ARI->getCallPreservedMask(CallConv);
2570 assert(Mask && "Missing call preserved mask for calling convention");
2571 Ops.push_back(DAG.getRegisterMask(Mask));
2573 if (InFlag.getNode())
2574 Ops.push_back(InFlag);
2576 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2578 // If we're doing a tall call, use a TC_RETURN here rather than an
2579 // actual call instruction.
2581 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2583 // Returns a chain and a flag for retval copy to use.
2584 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2585 InFlag = Chain.getValue(1);
2587 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2588 ? RoundUpToAlignment(NumBytes, 16)
2591 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2592 DAG.getIntPtrConstant(CalleePopBytes, true),
2595 InFlag = Chain.getValue(1);
2597 // Handle result values, copying them out of physregs into vregs that we
2599 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2600 InVals, IsThisReturn,
2601 IsThisReturn ? OutVals[0] : SDValue());
2604 bool AArch64TargetLowering::CanLowerReturn(
2605 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2606 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2607 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2608 ? RetCC_AArch64_WebKit_JS
2609 : RetCC_AArch64_AAPCS;
2610 SmallVector<CCValAssign, 16> RVLocs;
2611 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2612 return CCInfo.CheckReturn(Outs, RetCC);
2616 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2618 const SmallVectorImpl<ISD::OutputArg> &Outs,
2619 const SmallVectorImpl<SDValue> &OutVals,
2620 SDLoc DL, SelectionDAG &DAG) const {
2621 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2622 ? RetCC_AArch64_WebKit_JS
2623 : RetCC_AArch64_AAPCS;
2624 SmallVector<CCValAssign, 16> RVLocs;
2625 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2627 CCInfo.AnalyzeReturn(Outs, RetCC);
2629 // Copy the result values into the output registers.
2631 SmallVector<SDValue, 4> RetOps(1, Chain);
2632 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2633 ++i, ++realRVLocIdx) {
2634 CCValAssign &VA = RVLocs[i];
2635 assert(VA.isRegLoc() && "Can only return in registers!");
2636 SDValue Arg = OutVals[realRVLocIdx];
2638 switch (VA.getLocInfo()) {
2640 llvm_unreachable("Unknown loc info!");
2641 case CCValAssign::Full:
2642 if (Outs[i].ArgVT == MVT::i1) {
2643 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2644 // value. This is strictly redundant on Darwin (which uses "zeroext
2645 // i1"), but will be optimised out before ISel.
2646 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2647 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2650 case CCValAssign::BCvt:
2651 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2655 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2656 Flag = Chain.getValue(1);
2657 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2660 RetOps[0] = Chain; // Update chain.
2662 // Add the flag if we have it.
2664 RetOps.push_back(Flag);
2666 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2669 //===----------------------------------------------------------------------===//
2670 // Other Lowering Code
2671 //===----------------------------------------------------------------------===//
2673 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2674 SelectionDAG &DAG) const {
2675 EVT PtrVT = getPointerTy();
2677 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2678 unsigned char OpFlags =
2679 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2681 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2682 "unexpected offset in global node");
2684 // This also catched the large code model case for Darwin.
2685 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2686 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2687 // FIXME: Once remat is capable of dealing with instructions with register
2688 // operands, expand this into two nodes instead of using a wrapper node.
2689 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2692 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2693 const unsigned char MO_NC = AArch64II::MO_NC;
2695 AArch64ISD::WrapperLarge, DL, PtrVT,
2696 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2697 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2698 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2699 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2701 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2702 // the only correct model on Darwin.
2703 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2704 OpFlags | AArch64II::MO_PAGE);
2705 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2706 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2708 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2709 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2713 /// \brief Convert a TLS address reference into the correct sequence of loads
2714 /// and calls to compute the variable's address (for Darwin, currently) and
2715 /// return an SDValue containing the final node.
2717 /// Darwin only has one TLS scheme which must be capable of dealing with the
2718 /// fully general situation, in the worst case. This means:
2719 /// + "extern __thread" declaration.
2720 /// + Defined in a possibly unknown dynamic library.
2722 /// The general system is that each __thread variable has a [3 x i64] descriptor
2723 /// which contains information used by the runtime to calculate the address. The
2724 /// only part of this the compiler needs to know about is the first xword, which
2725 /// contains a function pointer that must be called with the address of the
2726 /// entire descriptor in "x0".
2728 /// Since this descriptor may be in a different unit, in general even the
2729 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2731 /// adrp x0, _var@TLVPPAGE
2732 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2733 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2734 /// ; the function pointer
2735 /// blr x1 ; Uses descriptor address in x0
2736 /// ; Address of _var is now in x0.
2738 /// If the address of _var's descriptor *is* known to the linker, then it can
2739 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2740 /// a slight efficiency gain.
2742 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2743 SelectionDAG &DAG) const {
2744 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2747 MVT PtrVT = getPointerTy();
2748 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2751 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2752 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2754 // The first entry in the descriptor is a function pointer that we must call
2755 // to obtain the address of the variable.
2756 SDValue Chain = DAG.getEntryNode();
2757 SDValue FuncTLVGet =
2758 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2759 false, true, true, 8);
2760 Chain = FuncTLVGet.getValue(1);
2762 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2763 MFI->setAdjustsStack(true);
2765 // TLS calls preserve all registers except those that absolutely must be
2766 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2768 const TargetRegisterInfo *TRI =
2769 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2770 const AArch64RegisterInfo *ARI =
2771 static_cast<const AArch64RegisterInfo *>(TRI);
2772 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2774 // Finally, we can make the call. This is just a degenerate version of a
2775 // normal AArch64 call node: x0 takes the address of the descriptor, and
2776 // returns the address of the variable in this thread.
2777 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2779 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2780 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2781 DAG.getRegisterMask(Mask), Chain.getValue(1));
2782 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2785 /// When accessing thread-local variables under either the general-dynamic or
2786 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2787 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2788 /// is a function pointer to carry out the resolution. This function takes the
2789 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2790 /// other registers (except LR, NZCV) are preserved.
2792 /// Thus, the ideal call sequence on AArch64 is:
2794 /// adrp x0, :tlsdesc:thread_var
2795 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2796 /// add x0, x0, :tlsdesc_lo12:thread_var
2797 /// .tlsdesccall thread_var
2799 /// (TPIDR_EL0 offset now in x0).
2801 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2802 /// relocation to help the linker relax this sequence if it turns out to be too
2805 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2807 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2808 SDValue DescAddr, SDLoc DL,
2809 SelectionDAG &DAG) const {
2810 EVT PtrVT = getPointerTy();
2812 // The function we need to call is simply the first entry in the GOT for this
2813 // descriptor, load it in preparation.
2814 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2816 // TLS calls preserve all registers except those that absolutely must be
2817 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2819 const TargetRegisterInfo *TRI =
2820 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2821 const AArch64RegisterInfo *ARI =
2822 static_cast<const AArch64RegisterInfo *>(TRI);
2823 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2825 // The function takes only one argument: the address of the descriptor itself
2827 SDValue Glue, Chain;
2828 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2829 Glue = Chain.getValue(1);
2831 // We're now ready to populate the argument list, as with a normal call:
2832 SmallVector<SDValue, 6> Ops;
2833 Ops.push_back(Chain);
2834 Ops.push_back(Func);
2835 Ops.push_back(SymAddr);
2836 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2837 Ops.push_back(DAG.getRegisterMask(Mask));
2838 Ops.push_back(Glue);
2840 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2841 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2842 Glue = Chain.getValue(1);
2844 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2848 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2849 SelectionDAG &DAG) const {
2850 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2851 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2852 "ELF TLS only supported in small memory model");
2853 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2855 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2858 EVT PtrVT = getPointerTy();
2860 const GlobalValue *GV = GA->getGlobal();
2862 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2864 if (Model == TLSModel::LocalExec) {
2865 SDValue HiVar = DAG.getTargetGlobalAddress(
2866 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2867 SDValue LoVar = DAG.getTargetGlobalAddress(
2869 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2871 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2872 DAG.getTargetConstant(16, MVT::i32)),
2874 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2875 DAG.getTargetConstant(0, MVT::i32)),
2877 } else if (Model == TLSModel::InitialExec) {
2878 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2879 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2880 } else if (Model == TLSModel::LocalDynamic) {
2881 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2882 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2883 // the beginning of the module's TLS region, followed by a DTPREL offset
2886 // These accesses will need deduplicating if there's more than one.
2887 AArch64FunctionInfo *MFI =
2888 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2889 MFI->incNumLocalDynamicTLSAccesses();
2891 // Accesses used in this sequence go via the TLS descriptor which lives in
2892 // the GOT. Prepare an address we can use to handle this.
2893 SDValue HiDesc = DAG.getTargetExternalSymbol(
2894 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2895 SDValue LoDesc = DAG.getTargetExternalSymbol(
2896 "_TLS_MODULE_BASE_", PtrVT,
2897 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2899 // First argument to the descriptor call is the address of the descriptor
2901 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2902 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2904 // The call needs a relocation too for linker relaxation. It doesn't make
2905 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2907 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2910 // Now we can calculate the offset from TPIDR_EL0 to this module's
2911 // thread-local area.
2912 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2914 // Now use :dtprel_whatever: operations to calculate this variable's offset
2915 // in its thread-storage area.
2916 SDValue HiVar = DAG.getTargetGlobalAddress(
2917 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2918 SDValue LoVar = DAG.getTargetGlobalAddress(
2919 GV, DL, MVT::i64, 0,
2920 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2923 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2924 DAG.getTargetConstant(16, MVT::i32)),
2927 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2928 DAG.getTargetConstant(0, MVT::i32)),
2931 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2932 } else if (Model == TLSModel::GeneralDynamic) {
2933 // Accesses used in this sequence go via the TLS descriptor which lives in
2934 // the GOT. Prepare an address we can use to handle this.
2935 SDValue HiDesc = DAG.getTargetGlobalAddress(
2936 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2937 SDValue LoDesc = DAG.getTargetGlobalAddress(
2939 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2941 // First argument to the descriptor call is the address of the descriptor
2943 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2944 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2946 // The call needs a relocation too for linker relaxation. It doesn't make
2947 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2950 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2952 // Finally we can make a call to calculate the offset from tpidr_el0.
2953 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2955 llvm_unreachable("Unsupported ELF TLS access model");
2957 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2960 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2961 SelectionDAG &DAG) const {
2962 if (Subtarget->isTargetDarwin())
2963 return LowerDarwinGlobalTLSAddress(Op, DAG);
2964 else if (Subtarget->isTargetELF())
2965 return LowerELFGlobalTLSAddress(Op, DAG);
2967 llvm_unreachable("Unexpected platform trying to use TLS");
2969 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2970 SDValue Chain = Op.getOperand(0);
2971 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2972 SDValue LHS = Op.getOperand(2);
2973 SDValue RHS = Op.getOperand(3);
2974 SDValue Dest = Op.getOperand(4);
2977 // Handle f128 first, since lowering it will result in comparing the return
2978 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2979 // is expecting to deal with.
2980 if (LHS.getValueType() == MVT::f128) {
2981 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2983 // If softenSetCCOperands returned a scalar, we need to compare the result
2984 // against zero to select between true and false values.
2985 if (!RHS.getNode()) {
2986 RHS = DAG.getConstant(0, LHS.getValueType());
2991 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2993 unsigned Opc = LHS.getOpcode();
2994 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2995 cast<ConstantSDNode>(RHS)->isOne() &&
2996 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2997 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2998 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2999 "Unexpected condition code.");
3000 // Only lower legal XALUO ops.
3001 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3004 // The actual operation with overflow check.
3005 AArch64CC::CondCode OFCC;
3006 SDValue Value, Overflow;
3007 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3009 if (CC == ISD::SETNE)
3010 OFCC = getInvertedCondCode(OFCC);
3011 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3013 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
3017 if (LHS.getValueType().isInteger()) {
3018 assert((LHS.getValueType() == RHS.getValueType()) &&
3019 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3021 // If the RHS of the comparison is zero, we can potentially fold this
3022 // to a specialized branch.
3023 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3024 if (RHSC && RHSC->getZExtValue() == 0) {
3025 if (CC == ISD::SETEQ) {
3026 // See if we can use a TBZ to fold in an AND as well.
3027 // TBZ has a smaller branch displacement than CBZ. If the offset is
3028 // out of bounds, a late MI-layer pass rewrites branches.
3029 // 403.gcc is an example that hits this case.
3030 if (LHS.getOpcode() == ISD::AND &&
3031 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3032 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3033 SDValue Test = LHS.getOperand(0);
3034 uint64_t Mask = LHS.getConstantOperandVal(1);
3035 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3036 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3039 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3040 } else if (CC == ISD::SETNE) {
3041 // See if we can use a TBZ to fold in an AND as well.
3042 // TBZ has a smaller branch displacement than CBZ. If the offset is
3043 // out of bounds, a late MI-layer pass rewrites branches.
3044 // 403.gcc is an example that hits this case.
3045 if (LHS.getOpcode() == ISD::AND &&
3046 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3047 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3048 SDValue Test = LHS.getOperand(0);
3049 uint64_t Mask = LHS.getConstantOperandVal(1);
3050 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3051 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3054 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3055 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3056 // Don't combine AND since emitComparison converts the AND to an ANDS
3057 // (a.k.a. TST) and the test in the test bit and branch instruction
3058 // becomes redundant. This would also increase register pressure.
3059 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3060 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3061 DAG.getConstant(Mask, MVT::i64), Dest);
3064 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3065 LHS.getOpcode() != ISD::AND) {
3066 // Don't combine AND since emitComparison converts the AND to an ANDS
3067 // (a.k.a. TST) and the test in the test bit and branch instruction
3068 // becomes redundant. This would also increase register pressure.
3069 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3070 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3071 DAG.getConstant(Mask, MVT::i64), Dest);
3075 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3076 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3080 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3082 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3083 // clean. Some of them require two branches to implement.
3084 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3085 AArch64CC::CondCode CC1, CC2;
3086 changeFPCCToAArch64CC(CC, CC1, CC2);
3087 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3089 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3090 if (CC2 != AArch64CC::AL) {
3091 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3092 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3099 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3100 SelectionDAG &DAG) const {
3101 EVT VT = Op.getValueType();
3104 SDValue In1 = Op.getOperand(0);
3105 SDValue In2 = Op.getOperand(1);
3106 EVT SrcVT = In2.getValueType();
3108 if (SrcVT == MVT::f32 && VT == MVT::f64)
3109 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3110 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3111 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3113 // FIXME: Src type is different, bail out for now. Can VT really be a
3120 SDValue EltMask, VecVal1, VecVal2;
3121 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3124 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3126 if (!VT.isVector()) {
3127 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3128 DAG.getUNDEF(VecVT), In1);
3129 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3130 DAG.getUNDEF(VecVT), In2);
3132 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3133 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3135 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3139 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3140 // immediate moves cannot materialize that in a single instruction for
3141 // 64-bit elements. Instead, materialize zero and then negate it.
3142 EltMask = DAG.getConstant(0, EltVT);
3144 if (!VT.isVector()) {
3145 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3146 DAG.getUNDEF(VecVT), In1);
3147 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3148 DAG.getUNDEF(VecVT), In2);
3150 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3151 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3154 llvm_unreachable("Invalid type for copysign!");
3157 std::vector<SDValue> BuildVectorOps;
3158 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3159 BuildVectorOps.push_back(EltMask);
3161 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3163 // If we couldn't materialize the mask above, then the mask vector will be
3164 // the zero vector, and we need to negate it here.
3165 if (VT == MVT::f64 || VT == MVT::v2f64) {
3166 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3167 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3168 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3172 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3175 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3176 else if (VT == MVT::f64)
3177 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3179 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3182 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3183 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3184 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3187 // While there is no integer popcount instruction, it can
3188 // be more efficiently lowered to the following sequence that uses
3189 // AdvSIMD registers/instructions as long as the copies to/from
3190 // the AdvSIMD registers are cheap.
3191 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3192 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3193 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3194 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3195 SDValue Val = Op.getOperand(0);
3197 EVT VT = Op.getValueType();
3198 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3201 if (VT == MVT::i32) {
3202 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3203 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3206 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3209 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3210 SDValue UaddLV = DAG.getNode(
3211 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3212 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3215 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3219 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3221 if (Op.getValueType().isVector())
3222 return LowerVSETCC(Op, DAG);
3224 SDValue LHS = Op.getOperand(0);
3225 SDValue RHS = Op.getOperand(1);
3226 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3229 // We chose ZeroOrOneBooleanContents, so use zero and one.
3230 EVT VT = Op.getValueType();
3231 SDValue TVal = DAG.getConstant(1, VT);
3232 SDValue FVal = DAG.getConstant(0, VT);
3234 // Handle f128 first, since one possible outcome is a normal integer
3235 // comparison which gets picked up by the next if statement.
3236 if (LHS.getValueType() == MVT::f128) {
3237 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3239 // If softenSetCCOperands returned a scalar, use it.
3240 if (!RHS.getNode()) {
3241 assert(LHS.getValueType() == Op.getValueType() &&
3242 "Unexpected setcc expansion!");
3247 if (LHS.getValueType().isInteger()) {
3250 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3252 // Note that we inverted the condition above, so we reverse the order of
3253 // the true and false operands here. This will allow the setcc to be
3254 // matched to a single CSINC instruction.
3255 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3258 // Now we know we're dealing with FP values.
3259 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3261 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3262 // and do the comparison.
3263 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3265 AArch64CC::CondCode CC1, CC2;
3266 changeFPCCToAArch64CC(CC, CC1, CC2);
3267 if (CC2 == AArch64CC::AL) {
3268 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3269 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3271 // Note that we inverted the condition above, so we reverse the order of
3272 // the true and false operands here. This will allow the setcc to be
3273 // matched to a single CSINC instruction.
3274 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3276 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3277 // totally clean. Some of them require two CSELs to implement. As is in
3278 // this case, we emit the first CSEL and then emit a second using the output
3279 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3281 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3282 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3284 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3286 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3287 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3291 /// A SELECT_CC operation is really some kind of max or min if both values being
3292 /// compared are, in some sense, equal to the results in either case. However,
3293 /// it is permissible to compare f32 values and produce directly extended f64
3296 /// Extending the comparison operands would also be allowed, but is less likely
3297 /// to happen in practice since their use is right here. Note that truncate
3298 /// operations would *not* be semantically equivalent.
3299 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3303 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3304 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3305 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3306 Result.getValueType() == MVT::f64) {
3308 APFloat CmpVal = CCmp->getValueAPF();
3309 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3310 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3313 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3316 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3317 SelectionDAG &DAG) const {
3318 SDValue CC = Op->getOperand(0);
3319 SDValue TVal = Op->getOperand(1);
3320 SDValue FVal = Op->getOperand(2);
3323 unsigned Opc = CC.getOpcode();
3324 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3326 if (CC.getResNo() == 1 &&
3327 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3328 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3329 // Only lower legal XALUO ops.
3330 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3333 AArch64CC::CondCode OFCC;
3334 SDValue Value, Overflow;
3335 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3336 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3338 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3342 if (CC.getOpcode() == ISD::SETCC)
3343 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3344 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3346 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3350 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3351 SelectionDAG &DAG) const {
3352 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3353 SDValue LHS = Op.getOperand(0);
3354 SDValue RHS = Op.getOperand(1);
3355 SDValue TVal = Op.getOperand(2);
3356 SDValue FVal = Op.getOperand(3);
3359 // Handle f128 first, because it will result in a comparison of some RTLIB
3360 // call result against zero.
3361 if (LHS.getValueType() == MVT::f128) {
3362 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3364 // If softenSetCCOperands returned a scalar, we need to compare the result
3365 // against zero to select between true and false values.
3366 if (!RHS.getNode()) {
3367 RHS = DAG.getConstant(0, LHS.getValueType());
3372 // Handle integers first.
3373 if (LHS.getValueType().isInteger()) {
3374 assert((LHS.getValueType() == RHS.getValueType()) &&
3375 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3377 unsigned Opcode = AArch64ISD::CSEL;
3379 // If both the TVal and the FVal are constants, see if we can swap them in
3380 // order to for a CSINV or CSINC out of them.
3381 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3382 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3384 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3385 std::swap(TVal, FVal);
3386 std::swap(CTVal, CFVal);
3387 CC = ISD::getSetCCInverse(CC, true);
3388 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3389 std::swap(TVal, FVal);
3390 std::swap(CTVal, CFVal);
3391 CC = ISD::getSetCCInverse(CC, true);
3392 } else if (TVal.getOpcode() == ISD::XOR) {
3393 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3394 // with a CSINV rather than a CSEL.
3395 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3397 if (CVal && CVal->isAllOnesValue()) {
3398 std::swap(TVal, FVal);
3399 std::swap(CTVal, CFVal);
3400 CC = ISD::getSetCCInverse(CC, true);
3402 } else if (TVal.getOpcode() == ISD::SUB) {
3403 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3404 // that we can match with a CSNEG rather than a CSEL.
3405 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3407 if (CVal && CVal->isNullValue()) {
3408 std::swap(TVal, FVal);
3409 std::swap(CTVal, CFVal);
3410 CC = ISD::getSetCCInverse(CC, true);
3412 } else if (CTVal && CFVal) {
3413 const int64_t TrueVal = CTVal->getSExtValue();
3414 const int64_t FalseVal = CFVal->getSExtValue();
3417 // If both TVal and FVal are constants, see if FVal is the
3418 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3419 // instead of a CSEL in that case.
3420 if (TrueVal == ~FalseVal) {
3421 Opcode = AArch64ISD::CSINV;
3422 } else if (TrueVal == -FalseVal) {
3423 Opcode = AArch64ISD::CSNEG;
3424 } else if (TVal.getValueType() == MVT::i32) {
3425 // If our operands are only 32-bit wide, make sure we use 32-bit
3426 // arithmetic for the check whether we can use CSINC. This ensures that
3427 // the addition in the check will wrap around properly in case there is
3428 // an overflow (which would not be the case if we do the check with
3429 // 64-bit arithmetic).
3430 const uint32_t TrueVal32 = CTVal->getZExtValue();
3431 const uint32_t FalseVal32 = CFVal->getZExtValue();
3433 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3434 Opcode = AArch64ISD::CSINC;
3436 if (TrueVal32 > FalseVal32) {
3440 // 64-bit check whether we can use CSINC.
3441 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3442 Opcode = AArch64ISD::CSINC;
3444 if (TrueVal > FalseVal) {
3449 // Swap TVal and FVal if necessary.
3451 std::swap(TVal, FVal);
3452 std::swap(CTVal, CFVal);
3453 CC = ISD::getSetCCInverse(CC, true);
3456 if (Opcode != AArch64ISD::CSEL) {
3457 // Drop FVal since we can get its value by simply inverting/negating
3464 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3466 EVT VT = Op.getValueType();
3467 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3470 // Now we know we're dealing with FP values.
3471 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3472 assert(LHS.getValueType() == RHS.getValueType());
3473 EVT VT = Op.getValueType();
3475 // Try to match this select into a max/min operation, which have dedicated
3476 // opcode in the instruction set.
3477 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3479 if (getTargetMachine().Options.NoNaNsFPMath) {
3480 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3481 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3482 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3483 CC = ISD::getSetCCSwappedOperands(CC);
3484 std::swap(MinMaxLHS, MinMaxRHS);
3487 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3488 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3498 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3506 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3512 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3513 // and do the comparison.
3514 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3516 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3517 // clean. Some of them require two CSELs to implement.
3518 AArch64CC::CondCode CC1, CC2;
3519 changeFPCCToAArch64CC(CC, CC1, CC2);
3520 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3521 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3523 // If we need a second CSEL, emit it, using the output of the first as the
3524 // RHS. We're effectively OR'ing the two CC's together.
3525 if (CC2 != AArch64CC::AL) {
3526 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3527 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3530 // Otherwise, return the output of the first CSEL.
3534 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3535 SelectionDAG &DAG) const {
3536 // Jump table entries as PC relative offsets. No additional tweaking
3537 // is necessary here. Just get the address of the jump table.
3538 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3539 EVT PtrVT = getPointerTy();
3542 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3543 !Subtarget->isTargetMachO()) {
3544 const unsigned char MO_NC = AArch64II::MO_NC;
3546 AArch64ISD::WrapperLarge, DL, PtrVT,
3547 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3548 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3549 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3550 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3551 AArch64II::MO_G0 | MO_NC));
3555 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3556 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3557 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3558 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3559 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3562 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3563 SelectionDAG &DAG) const {
3564 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3565 EVT PtrVT = getPointerTy();
3568 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3569 // Use the GOT for the large code model on iOS.
3570 if (Subtarget->isTargetMachO()) {
3571 SDValue GotAddr = DAG.getTargetConstantPool(
3572 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3574 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3577 const unsigned char MO_NC = AArch64II::MO_NC;
3579 AArch64ISD::WrapperLarge, DL, PtrVT,
3580 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3581 CP->getOffset(), AArch64II::MO_G3),
3582 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3583 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3584 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3585 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3586 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3587 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3589 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3590 // ELF, the only valid one on Darwin.
3592 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3593 CP->getOffset(), AArch64II::MO_PAGE);
3594 SDValue Lo = DAG.getTargetConstantPool(
3595 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3596 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3598 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3599 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3603 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3604 SelectionDAG &DAG) const {
3605 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3606 EVT PtrVT = getPointerTy();
3608 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3609 !Subtarget->isTargetMachO()) {
3610 const unsigned char MO_NC = AArch64II::MO_NC;
3612 AArch64ISD::WrapperLarge, DL, PtrVT,
3613 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3614 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3615 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3616 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3618 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3619 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3621 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3622 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3626 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3627 SelectionDAG &DAG) const {
3628 AArch64FunctionInfo *FuncInfo =
3629 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3633 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3634 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3635 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3636 MachinePointerInfo(SV), false, false, 0);
3639 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3640 SelectionDAG &DAG) const {
3641 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3642 // Standard, section B.3.
3643 MachineFunction &MF = DAG.getMachineFunction();
3644 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3647 SDValue Chain = Op.getOperand(0);
3648 SDValue VAList = Op.getOperand(1);
3649 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3650 SmallVector<SDValue, 4> MemOps;
3652 // void *__stack at offset 0
3654 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3655 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3656 MachinePointerInfo(SV), false, false, 8));
3658 // void *__gr_top at offset 8
3659 int GPRSize = FuncInfo->getVarArgsGPRSize();
3661 SDValue GRTop, GRTopAddr;
3663 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3664 DAG.getConstant(8, getPointerTy()));
3666 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3667 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3668 DAG.getConstant(GPRSize, getPointerTy()));
3670 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3671 MachinePointerInfo(SV, 8), false, false, 8));
3674 // void *__vr_top at offset 16
3675 int FPRSize = FuncInfo->getVarArgsFPRSize();
3677 SDValue VRTop, VRTopAddr;
3678 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3679 DAG.getConstant(16, getPointerTy()));
3681 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3682 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3683 DAG.getConstant(FPRSize, getPointerTy()));
3685 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3686 MachinePointerInfo(SV, 16), false, false, 8));
3689 // int __gr_offs at offset 24
3690 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3691 DAG.getConstant(24, getPointerTy()));
3692 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3693 GROffsAddr, MachinePointerInfo(SV, 24), false,
3696 // int __vr_offs at offset 28
3697 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3698 DAG.getConstant(28, getPointerTy()));
3699 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3700 VROffsAddr, MachinePointerInfo(SV, 28), false,
3703 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3706 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3707 SelectionDAG &DAG) const {
3708 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3709 : LowerAAPCS_VASTART(Op, DAG);
3712 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3713 SelectionDAG &DAG) const {
3714 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3716 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3717 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3718 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3720 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3721 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3722 8, false, false, MachinePointerInfo(DestSV),
3723 MachinePointerInfo(SrcSV));
3726 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3727 assert(Subtarget->isTargetDarwin() &&
3728 "automatic va_arg instruction only works on Darwin");
3730 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3731 EVT VT = Op.getValueType();
3733 SDValue Chain = Op.getOperand(0);
3734 SDValue Addr = Op.getOperand(1);
3735 unsigned Align = Op.getConstantOperandVal(3);
3737 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3738 MachinePointerInfo(V), false, false, false, 0);
3739 Chain = VAList.getValue(1);
3742 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3743 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3744 DAG.getConstant(Align - 1, getPointerTy()));
3745 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3746 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3749 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3750 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3752 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3753 // up to 64 bits. At the very least, we have to increase the striding of the
3754 // vaargs list to match this, and for FP values we need to introduce
3755 // FP_ROUND nodes as well.
3756 if (VT.isInteger() && !VT.isVector())
3758 bool NeedFPTrunc = false;
3759 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3764 // Increment the pointer, VAList, to the next vaarg
3765 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3766 DAG.getConstant(ArgSize, getPointerTy()));
3767 // Store the incremented VAList to the legalized pointer
3768 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3771 // Load the actual argument out of the pointer VAList
3773 // Load the value as an f64.
3774 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3775 MachinePointerInfo(), false, false, false, 0);
3776 // Round the value down to an f32.
3777 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3778 DAG.getIntPtrConstant(1));
3779 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3780 // Merge the rounded value with the chain output of the load.
3781 return DAG.getMergeValues(Ops, DL);
3784 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3788 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3789 SelectionDAG &DAG) const {
3790 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3791 MFI->setFrameAddressIsTaken(true);
3793 EVT VT = Op.getValueType();
3795 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3797 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3799 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3800 MachinePointerInfo(), false, false, false, 0);
3804 // FIXME? Maybe this could be a TableGen attribute on some registers and
3805 // this table could be generated automatically from RegInfo.
3806 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3808 unsigned Reg = StringSwitch<unsigned>(RegName)
3809 .Case("sp", AArch64::SP)
3813 report_fatal_error("Invalid register name global variable");
3816 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3817 SelectionDAG &DAG) const {
3818 MachineFunction &MF = DAG.getMachineFunction();
3819 MachineFrameInfo *MFI = MF.getFrameInfo();
3820 MFI->setReturnAddressIsTaken(true);
3822 EVT VT = Op.getValueType();
3824 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3826 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3827 SDValue Offset = DAG.getConstant(8, getPointerTy());
3828 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3829 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3830 MachinePointerInfo(), false, false, false, 0);
3833 // Return LR, which contains the return address. Mark it an implicit live-in.
3834 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3835 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3838 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3839 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3840 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3841 SelectionDAG &DAG) const {
3842 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3843 EVT VT = Op.getValueType();
3844 unsigned VTBits = VT.getSizeInBits();
3846 SDValue ShOpLo = Op.getOperand(0);
3847 SDValue ShOpHi = Op.getOperand(1);
3848 SDValue ShAmt = Op.getOperand(2);
3850 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3852 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3854 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3855 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3856 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3857 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3858 DAG.getConstant(VTBits, MVT::i64));
3859 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3861 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3862 ISD::SETGE, dl, DAG);
3863 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3865 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3866 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3868 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3870 // AArch64 shifts larger than the register width are wrapped rather than
3871 // clamped, so we can't just emit "hi >> x".
3872 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3873 SDValue TrueValHi = Opc == ISD::SRA
3874 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3875 DAG.getConstant(VTBits - 1, MVT::i64))
3876 : DAG.getConstant(0, VT);
3878 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3880 SDValue Ops[2] = { Lo, Hi };
3881 return DAG.getMergeValues(Ops, dl);
3884 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3885 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3886 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3887 SelectionDAG &DAG) const {
3888 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3889 EVT VT = Op.getValueType();
3890 unsigned VTBits = VT.getSizeInBits();
3892 SDValue ShOpLo = Op.getOperand(0);
3893 SDValue ShOpHi = Op.getOperand(1);
3894 SDValue ShAmt = Op.getOperand(2);
3897 assert(Op.getOpcode() == ISD::SHL_PARTS);
3898 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3899 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3900 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3901 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3902 DAG.getConstant(VTBits, MVT::i64));
3903 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3904 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3906 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3908 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3909 ISD::SETGE, dl, DAG);
3910 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3912 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3914 // AArch64 shifts of larger than register sizes are wrapped rather than
3915 // clamped, so we can't just emit "lo << a" if a is too big.
3916 SDValue TrueValLo = DAG.getConstant(0, VT);
3917 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3919 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3921 SDValue Ops[2] = { Lo, Hi };
3922 return DAG.getMergeValues(Ops, dl);
3925 bool AArch64TargetLowering::isOffsetFoldingLegal(
3926 const GlobalAddressSDNode *GA) const {
3927 // The AArch64 target doesn't support folding offsets into global addresses.
3931 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3932 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3933 // FIXME: We should be able to handle f128 as well with a clever lowering.
3934 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3938 return AArch64_AM::getFP64Imm(Imm) != -1;
3939 else if (VT == MVT::f32)
3940 return AArch64_AM::getFP32Imm(Imm) != -1;
3944 //===----------------------------------------------------------------------===//
3945 // AArch64 Optimization Hooks
3946 //===----------------------------------------------------------------------===//
3948 //===----------------------------------------------------------------------===//
3949 // AArch64 Inline Assembly Support
3950 //===----------------------------------------------------------------------===//
3952 // Table of Constraints
3953 // TODO: This is the current set of constraints supported by ARM for the
3954 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3956 // r - A general register
3957 // w - An FP/SIMD register of some size in the range v0-v31
3958 // x - An FP/SIMD register of some size in the range v0-v15
3959 // I - Constant that can be used with an ADD instruction
3960 // J - Constant that can be used with a SUB instruction
3961 // K - Constant that can be used with a 32-bit logical instruction
3962 // L - Constant that can be used with a 64-bit logical instruction
3963 // M - Constant that can be used as a 32-bit MOV immediate
3964 // N - Constant that can be used as a 64-bit MOV immediate
3965 // Q - A memory reference with base register and no offset
3966 // S - A symbolic address
3967 // Y - Floating point constant zero
3968 // Z - Integer constant zero
3970 // Note that general register operands will be output using their 64-bit x
3971 // register name, whatever the size of the variable, unless the asm operand
3972 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3973 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3976 /// getConstraintType - Given a constraint letter, return the type of
3977 /// constraint it is for this target.
3978 AArch64TargetLowering::ConstraintType
3979 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3980 if (Constraint.size() == 1) {
3981 switch (Constraint[0]) {
3988 return C_RegisterClass;
3989 // An address with a single base register. Due to the way we
3990 // currently handle addresses it is the same as 'r'.
3995 return TargetLowering::getConstraintType(Constraint);
3998 /// Examine constraint type and operand type and determine a weight value.
3999 /// This object must already have been set up with the operand type
4000 /// and the current alternative constraint selected.
4001 TargetLowering::ConstraintWeight
4002 AArch64TargetLowering::getSingleConstraintMatchWeight(
4003 AsmOperandInfo &info, const char *constraint) const {
4004 ConstraintWeight weight = CW_Invalid;
4005 Value *CallOperandVal = info.CallOperandVal;
4006 // If we don't have a value, we can't do a match,
4007 // but allow it at the lowest weight.
4008 if (!CallOperandVal)
4010 Type *type = CallOperandVal->getType();
4011 // Look at the constraint type.
4012 switch (*constraint) {
4014 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4018 if (type->isFloatingPointTy() || type->isVectorTy())
4019 weight = CW_Register;
4022 weight = CW_Constant;
4028 std::pair<unsigned, const TargetRegisterClass *>
4029 AArch64TargetLowering::getRegForInlineAsmConstraint(
4030 const std::string &Constraint, MVT VT) const {
4031 if (Constraint.size() == 1) {
4032 switch (Constraint[0]) {
4034 if (VT.getSizeInBits() == 64)
4035 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4036 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4039 return std::make_pair(0U, &AArch64::FPR32RegClass);
4040 if (VT.getSizeInBits() == 64)
4041 return std::make_pair(0U, &AArch64::FPR64RegClass);
4042 if (VT.getSizeInBits() == 128)
4043 return std::make_pair(0U, &AArch64::FPR128RegClass);
4045 // The instructions that this constraint is designed for can
4046 // only take 128-bit registers so just use that regclass.
4048 if (VT.getSizeInBits() == 128)
4049 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4053 if (StringRef("{cc}").equals_lower(Constraint))
4054 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4056 // Use the default implementation in TargetLowering to convert the register
4057 // constraint into a member of a register class.
4058 std::pair<unsigned, const TargetRegisterClass *> Res;
4059 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4061 // Not found as a standard register?
4063 unsigned Size = Constraint.size();
4064 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4065 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4066 const std::string Reg =
4067 std::string(&Constraint[2], &Constraint[Size - 1]);
4068 int RegNo = atoi(Reg.c_str());
4069 if (RegNo >= 0 && RegNo <= 31) {
4070 // v0 - v31 are aliases of q0 - q31.
4071 // By default we'll emit v0-v31 for this unless there's a modifier where
4072 // we'll emit the correct register as well.
4073 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4074 Res.second = &AArch64::FPR128RegClass;
4082 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4083 /// vector. If it is invalid, don't add anything to Ops.
4084 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4085 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4086 SelectionDAG &DAG) const {
4089 // Currently only support length 1 constraints.
4090 if (Constraint.length() != 1)
4093 char ConstraintLetter = Constraint[0];
4094 switch (ConstraintLetter) {
4098 // This set of constraints deal with valid constants for various instructions.
4099 // Validate and return a target constant for them if we can.
4101 // 'z' maps to xzr or wzr so it needs an input of 0.
4102 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4103 if (!C || C->getZExtValue() != 0)
4106 if (Op.getValueType() == MVT::i64)
4107 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4109 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4119 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4123 // Grab the value and do some validation.
4124 uint64_t CVal = C->getZExtValue();
4125 switch (ConstraintLetter) {
4126 // The I constraint applies only to simple ADD or SUB immediate operands:
4127 // i.e. 0 to 4095 with optional shift by 12
4128 // The J constraint applies only to ADD or SUB immediates that would be
4129 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4130 // instruction [or vice versa], in other words -1 to -4095 with optional
4131 // left shift by 12.
4133 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4137 uint64_t NVal = -C->getSExtValue();
4138 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4139 CVal = C->getSExtValue();
4144 // The K and L constraints apply *only* to logical immediates, including
4145 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4146 // been removed and MOV should be used). So these constraints have to
4147 // distinguish between bit patterns that are valid 32-bit or 64-bit
4148 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4149 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4152 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4156 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4159 // The M and N constraints are a superset of K and L respectively, for use
4160 // with the MOV (immediate) alias. As well as the logical immediates they
4161 // also match 32 or 64-bit immediates that can be loaded either using a
4162 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4163 // (M) or 64-bit 0x1234000000000000 (N) etc.
4164 // As a note some of this code is liberally stolen from the asm parser.
4166 if (!isUInt<32>(CVal))
4168 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4170 if ((CVal & 0xFFFF) == CVal)
4172 if ((CVal & 0xFFFF0000ULL) == CVal)
4174 uint64_t NCVal = ~(uint32_t)CVal;
4175 if ((NCVal & 0xFFFFULL) == NCVal)
4177 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4182 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4184 if ((CVal & 0xFFFFULL) == CVal)
4186 if ((CVal & 0xFFFF0000ULL) == CVal)
4188 if ((CVal & 0xFFFF00000000ULL) == CVal)
4190 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4192 uint64_t NCVal = ~CVal;
4193 if ((NCVal & 0xFFFFULL) == NCVal)
4195 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4197 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4199 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4207 // All assembler immediates are 64-bit integers.
4208 Result = DAG.getTargetConstant(CVal, MVT::i64);
4212 if (Result.getNode()) {
4213 Ops.push_back(Result);
4217 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4220 //===----------------------------------------------------------------------===//
4221 // AArch64 Advanced SIMD Support
4222 //===----------------------------------------------------------------------===//
4224 /// WidenVector - Given a value in the V64 register class, produce the
4225 /// equivalent value in the V128 register class.
4226 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4227 EVT VT = V64Reg.getValueType();
4228 unsigned NarrowSize = VT.getVectorNumElements();
4229 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4230 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4233 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4234 V64Reg, DAG.getConstant(0, MVT::i32));
4237 /// getExtFactor - Determine the adjustment factor for the position when
4238 /// generating an "extract from vector registers" instruction.
4239 static unsigned getExtFactor(SDValue &V) {
4240 EVT EltType = V.getValueType().getVectorElementType();
4241 return EltType.getSizeInBits() / 8;
4244 /// NarrowVector - Given a value in the V128 register class, produce the
4245 /// equivalent value in the V64 register class.
4246 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4247 EVT VT = V128Reg.getValueType();
4248 unsigned WideSize = VT.getVectorNumElements();
4249 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4250 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4253 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4256 // Gather data to see if the operation can be modelled as a
4257 // shuffle in combination with VEXTs.
4258 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4259 SelectionDAG &DAG) const {
4260 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4262 EVT VT = Op.getValueType();
4263 unsigned NumElts = VT.getVectorNumElements();
4265 struct ShuffleSourceInfo {
4270 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4271 // be compatible with the shuffle we intend to construct. As a result
4272 // ShuffleVec will be some sliding window into the original Vec.
4275 // Code should guarantee that element i in Vec starts at element "WindowBase
4276 // + i * WindowScale in ShuffleVec".
4280 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4281 ShuffleSourceInfo(SDValue Vec)
4282 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4286 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4288 SmallVector<ShuffleSourceInfo, 2> Sources;
4289 for (unsigned i = 0; i < NumElts; ++i) {
4290 SDValue V = Op.getOperand(i);
4291 if (V.getOpcode() == ISD::UNDEF)
4293 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4294 // A shuffle can only come from building a vector from various
4295 // elements of other vectors.
4299 // Add this element source to the list if it's not already there.
4300 SDValue SourceVec = V.getOperand(0);
4301 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4302 if (Source == Sources.end())
4303 Sources.push_back(ShuffleSourceInfo(SourceVec));
4305 // Update the minimum and maximum lane number seen.
4306 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4307 Source->MinElt = std::min(Source->MinElt, EltNo);
4308 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4311 // Currently only do something sane when at most two source vectors
4313 if (Sources.size() > 2)
4316 // Find out the smallest element size among result and two sources, and use
4317 // it as element size to build the shuffle_vector.
4318 EVT SmallestEltTy = VT.getVectorElementType();
4319 for (auto &Source : Sources) {
4320 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4321 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4322 SmallestEltTy = SrcEltTy;
4325 unsigned ResMultiplier =
4326 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4327 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4328 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4330 // If the source vector is too wide or too narrow, we may nevertheless be able
4331 // to construct a compatible shuffle either by concatenating it with UNDEF or
4332 // extracting a suitable range of elements.
4333 for (auto &Src : Sources) {
4334 EVT SrcVT = Src.ShuffleVec.getValueType();
4336 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4339 // This stage of the search produces a source with the same element type as
4340 // the original, but with a total width matching the BUILD_VECTOR output.
4341 EVT EltVT = SrcVT.getVectorElementType();
4342 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4343 VT.getSizeInBits() / EltVT.getSizeInBits());
4345 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4346 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4347 // We can pad out the smaller vector for free, so if it's part of a
4350 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4351 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4355 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4357 if (Src.MaxElt - Src.MinElt >= NumElts) {
4358 // Span too large for a VEXT to cope
4362 if (Src.MinElt >= NumElts) {
4363 // The extraction can just take the second half
4365 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4366 DAG.getIntPtrConstant(NumElts));
4367 Src.WindowBase = -NumElts;
4368 } else if (Src.MaxElt < NumElts) {
4369 // The extraction can just take the first half
4370 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4371 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4373 // An actual VEXT is needed
4374 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4375 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4377 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4378 DAG.getIntPtrConstant(NumElts));
4379 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4381 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4382 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4383 Src.WindowBase = -Src.MinElt;
4387 // Another possible incompatibility occurs from the vector element types. We
4388 // can fix this by bitcasting the source vectors to the same type we intend
4390 for (auto &Src : Sources) {
4391 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4392 if (SrcEltTy == SmallestEltTy)
4394 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4395 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4396 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4397 Src.WindowBase *= Src.WindowScale;
4400 // Final sanity check before we try to actually produce a shuffle.
4402 for (auto Src : Sources)
4403 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4406 // The stars all align, our next step is to produce the mask for the shuffle.
4407 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4408 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4409 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4410 SDValue Entry = Op.getOperand(i);
4411 if (Entry.getOpcode() == ISD::UNDEF)
4414 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4415 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4417 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4418 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4420 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4421 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4422 VT.getVectorElementType().getSizeInBits());
4423 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4425 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4426 // starting at the appropriate offset.
4427 int *LaneMask = &Mask[i * ResMultiplier];
4429 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4430 ExtractBase += NumElts * (Src - Sources.begin());
4431 for (int j = 0; j < LanesDefined; ++j)
4432 LaneMask[j] = ExtractBase + j;
4435 // Final check before we try to produce nonsense...
4436 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4439 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4440 for (unsigned i = 0; i < Sources.size(); ++i)
4441 ShuffleOps[i] = Sources[i].ShuffleVec;
4443 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4444 ShuffleOps[1], &Mask[0]);
4445 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4448 // check if an EXT instruction can handle the shuffle mask when the
4449 // vector sources of the shuffle are the same.
4450 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4451 unsigned NumElts = VT.getVectorNumElements();
4453 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4459 // If this is a VEXT shuffle, the immediate value is the index of the first
4460 // element. The other shuffle indices must be the successive elements after
4462 unsigned ExpectedElt = Imm;
4463 for (unsigned i = 1; i < NumElts; ++i) {
4464 // Increment the expected index. If it wraps around, just follow it
4465 // back to index zero and keep going.
4467 if (ExpectedElt == NumElts)
4471 continue; // ignore UNDEF indices
4472 if (ExpectedElt != static_cast<unsigned>(M[i]))
4479 // check if an EXT instruction can handle the shuffle mask when the
4480 // vector sources of the shuffle are different.
4481 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4483 // Look for the first non-undef element.
4484 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4485 [](int Elt) {return Elt >= 0;});
4487 // Benefit form APInt to handle overflow when calculating expected element.
4488 unsigned NumElts = VT.getVectorNumElements();
4489 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4490 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4491 // The following shuffle indices must be the successive elements after the
4492 // first real element.
4493 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4494 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4495 if (FirstWrongElt != M.end())
4498 // The index of an EXT is the first element if it is not UNDEF.
4499 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4500 // value of the first element. E.g.
4501 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4502 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4503 // ExpectedElt is the last mask index plus 1.
4504 Imm = ExpectedElt.getZExtValue();
4506 // There are two difference cases requiring to reverse input vectors.
4507 // For example, for vector <4 x i32> we have the following cases,
4508 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4509 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4510 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4511 // to reverse two input vectors.
4520 /// isREVMask - Check if a vector shuffle corresponds to a REV
4521 /// instruction with the specified blocksize. (The order of the elements
4522 /// within each block of the vector is reversed.)
4523 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4524 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4525 "Only possible block sizes for REV are: 16, 32, 64");
4527 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4531 unsigned NumElts = VT.getVectorNumElements();
4532 unsigned BlockElts = M[0] + 1;
4533 // If the first shuffle index is UNDEF, be optimistic.
4535 BlockElts = BlockSize / EltSz;
4537 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4540 for (unsigned i = 0; i < NumElts; ++i) {
4542 continue; // ignore UNDEF indices
4543 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4550 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4551 unsigned NumElts = VT.getVectorNumElements();
4552 WhichResult = (M[0] == 0 ? 0 : 1);
4553 unsigned Idx = WhichResult * NumElts / 2;
4554 for (unsigned i = 0; i != NumElts; i += 2) {
4555 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4556 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4564 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4565 unsigned NumElts = VT.getVectorNumElements();
4566 WhichResult = (M[0] == 0 ? 0 : 1);
4567 for (unsigned i = 0; i != NumElts; ++i) {
4569 continue; // ignore UNDEF indices
4570 if ((unsigned)M[i] != 2 * i + WhichResult)
4577 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4578 unsigned NumElts = VT.getVectorNumElements();
4579 WhichResult = (M[0] == 0 ? 0 : 1);
4580 for (unsigned i = 0; i < NumElts; i += 2) {
4581 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4582 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4588 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4589 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4590 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4591 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4592 unsigned NumElts = VT.getVectorNumElements();
4593 WhichResult = (M[0] == 0 ? 0 : 1);
4594 unsigned Idx = WhichResult * NumElts / 2;
4595 for (unsigned i = 0; i != NumElts; i += 2) {
4596 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4597 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4605 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4606 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4607 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4608 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4609 unsigned Half = VT.getVectorNumElements() / 2;
4610 WhichResult = (M[0] == 0 ? 0 : 1);
4611 for (unsigned j = 0; j != 2; ++j) {
4612 unsigned Idx = WhichResult;
4613 for (unsigned i = 0; i != Half; ++i) {
4614 int MIdx = M[i + j * Half];
4615 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4624 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4625 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4626 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4627 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4628 unsigned NumElts = VT.getVectorNumElements();
4629 WhichResult = (M[0] == 0 ? 0 : 1);
4630 for (unsigned i = 0; i < NumElts; i += 2) {
4631 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4632 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4638 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4639 bool &DstIsLeft, int &Anomaly) {
4640 if (M.size() != static_cast<size_t>(NumInputElements))
4643 int NumLHSMatch = 0, NumRHSMatch = 0;
4644 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4646 for (int i = 0; i < NumInputElements; ++i) {
4656 LastLHSMismatch = i;
4658 if (M[i] == i + NumInputElements)
4661 LastRHSMismatch = i;
4664 if (NumLHSMatch == NumInputElements - 1) {
4666 Anomaly = LastLHSMismatch;
4668 } else if (NumRHSMatch == NumInputElements - 1) {
4670 Anomaly = LastRHSMismatch;
4677 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4678 if (VT.getSizeInBits() != 128)
4681 unsigned NumElts = VT.getVectorNumElements();
4683 for (int I = 0, E = NumElts / 2; I != E; I++) {
4688 int Offset = NumElts / 2;
4689 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4690 if (Mask[I] != I + SplitLHS * Offset)
4697 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4699 EVT VT = Op.getValueType();
4700 SDValue V0 = Op.getOperand(0);
4701 SDValue V1 = Op.getOperand(1);
4702 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4704 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4705 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4708 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4710 if (!isConcatMask(Mask, VT, SplitV0))
4713 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4714 VT.getVectorNumElements() / 2);
4716 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4717 DAG.getConstant(0, MVT::i64));
4719 if (V1.getValueType().getSizeInBits() == 128) {
4720 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4721 DAG.getConstant(0, MVT::i64));
4723 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4726 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4727 /// the specified operations to build the shuffle.
4728 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4729 SDValue RHS, SelectionDAG &DAG,
4731 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4732 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4733 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4736 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4745 OP_VUZPL, // VUZP, left result
4746 OP_VUZPR, // VUZP, right result
4747 OP_VZIPL, // VZIP, left result
4748 OP_VZIPR, // VZIP, right result
4749 OP_VTRNL, // VTRN, left result
4750 OP_VTRNR // VTRN, right result
4753 if (OpNum == OP_COPY) {
4754 if (LHSID == (1 * 9 + 2) * 9 + 3)
4756 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4760 SDValue OpLHS, OpRHS;
4761 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4762 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4763 EVT VT = OpLHS.getValueType();
4767 llvm_unreachable("Unknown shuffle opcode!");
4769 // VREV divides the vector in half and swaps within the half.
4770 if (VT.getVectorElementType() == MVT::i32 ||
4771 VT.getVectorElementType() == MVT::f32)
4772 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4773 // vrev <4 x i16> -> REV32
4774 if (VT.getVectorElementType() == MVT::i16 ||
4775 VT.getVectorElementType() == MVT::f16)
4776 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4777 // vrev <4 x i8> -> REV16
4778 assert(VT.getVectorElementType() == MVT::i8);
4779 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4784 EVT EltTy = VT.getVectorElementType();
4786 if (EltTy == MVT::i8)
4787 Opcode = AArch64ISD::DUPLANE8;
4788 else if (EltTy == MVT::i16)
4789 Opcode = AArch64ISD::DUPLANE16;
4790 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4791 Opcode = AArch64ISD::DUPLANE32;
4792 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4793 Opcode = AArch64ISD::DUPLANE64;
4795 llvm_unreachable("Invalid vector element type?");
4797 if (VT.getSizeInBits() == 64)
4798 OpLHS = WidenVector(OpLHS, DAG);
4799 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4800 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4805 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4806 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4807 DAG.getConstant(Imm, MVT::i32));
4810 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4813 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4816 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4819 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4822 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4825 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4830 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4831 SelectionDAG &DAG) {
4832 // Check to see if we can use the TBL instruction.
4833 SDValue V1 = Op.getOperand(0);
4834 SDValue V2 = Op.getOperand(1);
4837 EVT EltVT = Op.getValueType().getVectorElementType();
4838 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4840 SmallVector<SDValue, 8> TBLMask;
4841 for (int Val : ShuffleMask) {
4842 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4843 unsigned Offset = Byte + Val * BytesPerElt;
4844 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4848 MVT IndexVT = MVT::v8i8;
4849 unsigned IndexLen = 8;
4850 if (Op.getValueType().getSizeInBits() == 128) {
4851 IndexVT = MVT::v16i8;
4855 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4856 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4859 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4861 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4862 Shuffle = DAG.getNode(
4863 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4864 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4865 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4866 makeArrayRef(TBLMask.data(), IndexLen)));
4868 if (IndexLen == 8) {
4869 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4870 Shuffle = DAG.getNode(
4871 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4872 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4873 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4874 makeArrayRef(TBLMask.data(), IndexLen)));
4876 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4877 // cannot currently represent the register constraints on the input
4879 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4880 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4881 // &TBLMask[0], IndexLen));
4882 Shuffle = DAG.getNode(
4883 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4884 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4885 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4886 makeArrayRef(TBLMask.data(), IndexLen)));
4889 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4892 static unsigned getDUPLANEOp(EVT EltType) {
4893 if (EltType == MVT::i8)
4894 return AArch64ISD::DUPLANE8;
4895 if (EltType == MVT::i16 || EltType == MVT::f16)
4896 return AArch64ISD::DUPLANE16;
4897 if (EltType == MVT::i32 || EltType == MVT::f32)
4898 return AArch64ISD::DUPLANE32;
4899 if (EltType == MVT::i64 || EltType == MVT::f64)
4900 return AArch64ISD::DUPLANE64;
4902 llvm_unreachable("Invalid vector element type?");
4905 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4906 SelectionDAG &DAG) const {
4908 EVT VT = Op.getValueType();
4910 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4912 // Convert shuffles that are directly supported on NEON to target-specific
4913 // DAG nodes, instead of keeping them as shuffles and matching them again
4914 // during code selection. This is more efficient and avoids the possibility
4915 // of inconsistencies between legalization and selection.
4916 ArrayRef<int> ShuffleMask = SVN->getMask();
4918 SDValue V1 = Op.getOperand(0);
4919 SDValue V2 = Op.getOperand(1);
4921 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4922 V1.getValueType().getSimpleVT())) {
4923 int Lane = SVN->getSplatIndex();
4924 // If this is undef splat, generate it via "just" vdup, if possible.
4928 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4929 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4931 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4932 // constant. If so, we can just reference the lane's definition directly.
4933 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4934 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4935 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4937 // Otherwise, duplicate from the lane of the input vector.
4938 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4940 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4941 // to make a vector of the same size as this SHUFFLE. We can ignore the
4942 // extract entirely, and canonicalise the concat using WidenVector.
4943 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4944 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4945 V1 = V1.getOperand(0);
4946 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4947 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4948 Lane -= Idx * VT.getVectorNumElements() / 2;
4949 V1 = WidenVector(V1.getOperand(Idx), DAG);
4950 } else if (VT.getSizeInBits() == 64)
4951 V1 = WidenVector(V1, DAG);
4953 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4956 if (isREVMask(ShuffleMask, VT, 64))
4957 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4958 if (isREVMask(ShuffleMask, VT, 32))
4959 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4960 if (isREVMask(ShuffleMask, VT, 16))
4961 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4963 bool ReverseEXT = false;
4965 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4968 Imm *= getExtFactor(V1);
4969 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4970 DAG.getConstant(Imm, MVT::i32));
4971 } else if (V2->getOpcode() == ISD::UNDEF &&
4972 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4973 Imm *= getExtFactor(V1);
4974 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4975 DAG.getConstant(Imm, MVT::i32));
4978 unsigned WhichResult;
4979 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4980 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4981 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4983 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4984 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4985 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4987 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4988 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4989 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4992 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4993 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4994 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4996 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4997 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4998 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5000 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5001 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5002 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5005 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5006 if (Concat.getNode())
5011 int NumInputElements = V1.getValueType().getVectorNumElements();
5012 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5013 SDValue DstVec = DstIsLeft ? V1 : V2;
5014 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5016 SDValue SrcVec = V1;
5017 int SrcLane = ShuffleMask[Anomaly];
5018 if (SrcLane >= NumInputElements) {
5020 SrcLane -= VT.getVectorNumElements();
5022 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5024 EVT ScalarVT = VT.getVectorElementType();
5026 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5027 ScalarVT = MVT::i32;
5030 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5031 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5035 // If the shuffle is not directly supported and it has 4 elements, use
5036 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5037 unsigned NumElts = VT.getVectorNumElements();
5039 unsigned PFIndexes[4];
5040 for (unsigned i = 0; i != 4; ++i) {
5041 if (ShuffleMask[i] < 0)
5044 PFIndexes[i] = ShuffleMask[i];
5047 // Compute the index in the perfect shuffle table.
5048 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5049 PFIndexes[2] * 9 + PFIndexes[3];
5050 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5051 unsigned Cost = (PFEntry >> 30);
5054 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5057 return GenerateTBL(Op, ShuffleMask, DAG);
5060 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5062 EVT VT = BVN->getValueType(0);
5063 APInt SplatBits, SplatUndef;
5064 unsigned SplatBitSize;
5066 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5067 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5069 for (unsigned i = 0; i < NumSplats; ++i) {
5070 CnstBits <<= SplatBitSize;
5071 UndefBits <<= SplatBitSize;
5072 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5073 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5082 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5083 SelectionDAG &DAG) const {
5084 BuildVectorSDNode *BVN =
5085 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5086 SDValue LHS = Op.getOperand(0);
5088 EVT VT = Op.getValueType();
5093 APInt CnstBits(VT.getSizeInBits(), 0);
5094 APInt UndefBits(VT.getSizeInBits(), 0);
5095 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5096 // We only have BIC vector immediate instruction, which is and-not.
5097 CnstBits = ~CnstBits;
5099 // We make use of a little bit of goto ickiness in order to avoid having to
5100 // duplicate the immediate matching logic for the undef toggled case.
5101 bool SecondTry = false;
5104 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5105 CnstBits = CnstBits.zextOrTrunc(64);
5106 uint64_t CnstVal = CnstBits.getZExtValue();
5108 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5109 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5110 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5111 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5112 DAG.getConstant(CnstVal, MVT::i32),
5113 DAG.getConstant(0, MVT::i32));
5114 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5117 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5118 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5119 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5120 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5121 DAG.getConstant(CnstVal, MVT::i32),
5122 DAG.getConstant(8, MVT::i32));
5123 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5126 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5127 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5128 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5129 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5130 DAG.getConstant(CnstVal, MVT::i32),
5131 DAG.getConstant(16, MVT::i32));
5132 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5135 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5136 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5137 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5138 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5139 DAG.getConstant(CnstVal, MVT::i32),
5140 DAG.getConstant(24, MVT::i32));
5141 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5144 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5145 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5146 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5147 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5148 DAG.getConstant(CnstVal, MVT::i32),
5149 DAG.getConstant(0, MVT::i32));
5150 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5153 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5154 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5155 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5156 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5157 DAG.getConstant(CnstVal, MVT::i32),
5158 DAG.getConstant(8, MVT::i32));
5159 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5166 CnstBits = ~UndefBits;
5170 // We can always fall back to a non-immediate AND.
5175 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5176 // consists of only the same constant int value, returned in reference arg
5178 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5179 uint64_t &ConstVal) {
5180 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5183 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5186 EVT VT = Bvec->getValueType(0);
5187 unsigned NumElts = VT.getVectorNumElements();
5188 for (unsigned i = 1; i < NumElts; ++i)
5189 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5191 ConstVal = FirstElt->getZExtValue();
5195 static unsigned getIntrinsicID(const SDNode *N) {
5196 unsigned Opcode = N->getOpcode();
5199 return Intrinsic::not_intrinsic;
5200 case ISD::INTRINSIC_WO_CHAIN: {
5201 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5202 if (IID < Intrinsic::num_intrinsics)
5204 return Intrinsic::not_intrinsic;
5209 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5210 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5211 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5212 // Also, logical shift right -> sri, with the same structure.
5213 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5214 EVT VT = N->getValueType(0);
5221 // Is the first op an AND?
5222 const SDValue And = N->getOperand(0);
5223 if (And.getOpcode() != ISD::AND)
5226 // Is the second op an shl or lshr?
5227 SDValue Shift = N->getOperand(1);
5228 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5229 // or AArch64ISD::VLSHR vector, #shift
5230 unsigned ShiftOpc = Shift.getOpcode();
5231 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5233 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5235 // Is the shift amount constant?
5236 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5240 // Is the and mask vector all constant?
5242 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5245 // Is C1 == ~C2, taking into account how much one can shift elements of a
5247 uint64_t C2 = C2node->getZExtValue();
5248 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5249 if (C2 > ElemSizeInBits)
5251 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5252 if ((C1 & ElemMask) != (~C2 & ElemMask))
5255 SDValue X = And.getOperand(0);
5256 SDValue Y = Shift.getOperand(0);
5259 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5261 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5262 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5264 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5265 DEBUG(N->dump(&DAG));
5266 DEBUG(dbgs() << "into: \n");
5267 DEBUG(ResultSLI->dump(&DAG));
5273 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5274 SelectionDAG &DAG) const {
5275 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5276 if (EnableAArch64SlrGeneration) {
5277 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5282 BuildVectorSDNode *BVN =
5283 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5284 SDValue LHS = Op.getOperand(1);
5286 EVT VT = Op.getValueType();
5288 // OR commutes, so try swapping the operands.
5290 LHS = Op.getOperand(0);
5291 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5296 APInt CnstBits(VT.getSizeInBits(), 0);
5297 APInt UndefBits(VT.getSizeInBits(), 0);
5298 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5299 // We make use of a little bit of goto ickiness in order to avoid having to
5300 // duplicate the immediate matching logic for the undef toggled case.
5301 bool SecondTry = false;
5304 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5305 CnstBits = CnstBits.zextOrTrunc(64);
5306 uint64_t CnstVal = CnstBits.getZExtValue();
5308 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5309 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5310 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5311 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5312 DAG.getConstant(CnstVal, MVT::i32),
5313 DAG.getConstant(0, MVT::i32));
5314 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5317 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5318 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5319 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5320 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5321 DAG.getConstant(CnstVal, MVT::i32),
5322 DAG.getConstant(8, MVT::i32));
5323 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5326 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5327 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5328 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5329 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5330 DAG.getConstant(CnstVal, MVT::i32),
5331 DAG.getConstant(16, MVT::i32));
5332 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5335 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5336 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5337 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5338 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5339 DAG.getConstant(CnstVal, MVT::i32),
5340 DAG.getConstant(24, MVT::i32));
5341 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5344 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5345 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5346 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5347 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5348 DAG.getConstant(CnstVal, MVT::i32),
5349 DAG.getConstant(0, MVT::i32));
5350 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5353 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5354 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5355 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5356 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5357 DAG.getConstant(CnstVal, MVT::i32),
5358 DAG.getConstant(8, MVT::i32));
5359 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5366 CnstBits = UndefBits;
5370 // We can always fall back to a non-immediate OR.
5375 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5376 // be truncated to fit element width.
5377 static SDValue NormalizeBuildVector(SDValue Op,
5378 SelectionDAG &DAG) {
5379 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5381 EVT VT = Op.getValueType();
5382 EVT EltTy= VT.getVectorElementType();
5384 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5387 SmallVector<SDValue, 16> Ops;
5388 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5389 SDValue Lane = Op.getOperand(I);
5390 if (Lane.getOpcode() == ISD::Constant) {
5391 APInt LowBits(EltTy.getSizeInBits(),
5392 cast<ConstantSDNode>(Lane)->getZExtValue());
5393 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5395 Ops.push_back(Lane);
5397 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5400 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5401 SelectionDAG &DAG) const {
5403 EVT VT = Op.getValueType();
5404 Op = NormalizeBuildVector(Op, DAG);
5405 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5407 APInt CnstBits(VT.getSizeInBits(), 0);
5408 APInt UndefBits(VT.getSizeInBits(), 0);
5409 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5410 // We make use of a little bit of goto ickiness in order to avoid having to
5411 // duplicate the immediate matching logic for the undef toggled case.
5412 bool SecondTry = false;
5415 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5416 CnstBits = CnstBits.zextOrTrunc(64);
5417 uint64_t CnstVal = CnstBits.getZExtValue();
5419 // Certain magic vector constants (used to express things like NOT
5420 // and NEG) are passed through unmodified. This allows codegen patterns
5421 // for these operations to match. Special-purpose patterns will lower
5422 // these immediates to MOVIs if it proves necessary.
5423 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5426 // The many faces of MOVI...
5427 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5428 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5429 if (VT.getSizeInBits() == 128) {
5430 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5431 DAG.getConstant(CnstVal, MVT::i32));
5432 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5435 // Support the V64 version via subregister insertion.
5436 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5437 DAG.getConstant(CnstVal, MVT::i32));
5438 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5441 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5442 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5443 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5444 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5445 DAG.getConstant(CnstVal, MVT::i32),
5446 DAG.getConstant(0, MVT::i32));
5447 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5450 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5451 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5452 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5453 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5454 DAG.getConstant(CnstVal, MVT::i32),
5455 DAG.getConstant(8, MVT::i32));
5456 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5459 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5460 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5461 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5462 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5463 DAG.getConstant(CnstVal, MVT::i32),
5464 DAG.getConstant(16, MVT::i32));
5465 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5468 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5469 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5470 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5471 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5472 DAG.getConstant(CnstVal, MVT::i32),
5473 DAG.getConstant(24, MVT::i32));
5474 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5477 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5478 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5479 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5480 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5481 DAG.getConstant(CnstVal, MVT::i32),
5482 DAG.getConstant(0, MVT::i32));
5483 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5486 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5487 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5488 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5489 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5490 DAG.getConstant(CnstVal, MVT::i32),
5491 DAG.getConstant(8, MVT::i32));
5492 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5495 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5496 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5497 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5498 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5499 DAG.getConstant(CnstVal, MVT::i32),
5500 DAG.getConstant(264, MVT::i32));
5501 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5504 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5505 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5506 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5507 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5508 DAG.getConstant(CnstVal, MVT::i32),
5509 DAG.getConstant(272, MVT::i32));
5510 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5513 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5514 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5515 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5516 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5517 DAG.getConstant(CnstVal, MVT::i32));
5518 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5521 // The few faces of FMOV...
5522 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5523 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5524 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5525 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5526 DAG.getConstant(CnstVal, MVT::i32));
5527 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5530 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5531 VT.getSizeInBits() == 128) {
5532 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5533 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5534 DAG.getConstant(CnstVal, MVT::i32));
5535 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5538 // The many faces of MVNI...
5540 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5541 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5542 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5543 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5544 DAG.getConstant(CnstVal, MVT::i32),
5545 DAG.getConstant(0, MVT::i32));
5546 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5549 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5550 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5551 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5552 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5553 DAG.getConstant(CnstVal, MVT::i32),
5554 DAG.getConstant(8, MVT::i32));
5555 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5558 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5559 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5560 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5561 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5562 DAG.getConstant(CnstVal, MVT::i32),
5563 DAG.getConstant(16, MVT::i32));
5564 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5567 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5568 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5569 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5570 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5571 DAG.getConstant(CnstVal, MVT::i32),
5572 DAG.getConstant(24, MVT::i32));
5573 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5576 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5577 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5578 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5579 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5580 DAG.getConstant(CnstVal, MVT::i32),
5581 DAG.getConstant(0, MVT::i32));
5582 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5585 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5586 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5587 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5588 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5589 DAG.getConstant(CnstVal, MVT::i32),
5590 DAG.getConstant(8, MVT::i32));
5591 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5594 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5595 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5596 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5597 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5598 DAG.getConstant(CnstVal, MVT::i32),
5599 DAG.getConstant(264, MVT::i32));
5600 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5603 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5604 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5605 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5606 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5607 DAG.getConstant(CnstVal, MVT::i32),
5608 DAG.getConstant(272, MVT::i32));
5609 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5616 CnstBits = UndefBits;
5621 // Scan through the operands to find some interesting properties we can
5623 // 1) If only one value is used, we can use a DUP, or
5624 // 2) if only the low element is not undef, we can just insert that, or
5625 // 3) if only one constant value is used (w/ some non-constant lanes),
5626 // we can splat the constant value into the whole vector then fill
5627 // in the non-constant lanes.
5628 // 4) FIXME: If different constant values are used, but we can intelligently
5629 // select the values we'll be overwriting for the non-constant
5630 // lanes such that we can directly materialize the vector
5631 // some other way (MOVI, e.g.), we can be sneaky.
5632 unsigned NumElts = VT.getVectorNumElements();
5633 bool isOnlyLowElement = true;
5634 bool usesOnlyOneValue = true;
5635 bool usesOnlyOneConstantValue = true;
5636 bool isConstant = true;
5637 unsigned NumConstantLanes = 0;
5639 SDValue ConstantValue;
5640 for (unsigned i = 0; i < NumElts; ++i) {
5641 SDValue V = Op.getOperand(i);
5642 if (V.getOpcode() == ISD::UNDEF)
5645 isOnlyLowElement = false;
5646 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5649 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5651 if (!ConstantValue.getNode())
5653 else if (ConstantValue != V)
5654 usesOnlyOneConstantValue = false;
5657 if (!Value.getNode())
5659 else if (V != Value)
5660 usesOnlyOneValue = false;
5663 if (!Value.getNode())
5664 return DAG.getUNDEF(VT);
5666 if (isOnlyLowElement)
5667 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5669 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5670 // i32 and try again.
5671 if (usesOnlyOneValue) {
5673 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5674 Value.getValueType() != VT)
5675 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5677 // This is actually a DUPLANExx operation, which keeps everything vectory.
5679 // DUPLANE works on 128-bit vectors, widen it if necessary.
5680 SDValue Lane = Value.getOperand(1);
5681 Value = Value.getOperand(0);
5682 if (Value.getValueType().getSizeInBits() == 64)
5683 Value = WidenVector(Value, DAG);
5685 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5686 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5689 if (VT.getVectorElementType().isFloatingPoint()) {
5690 SmallVector<SDValue, 8> Ops;
5692 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5693 for (unsigned i = 0; i < NumElts; ++i)
5694 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5695 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5696 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5697 Val = LowerBUILD_VECTOR(Val, DAG);
5699 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5703 // If there was only one constant value used and for more than one lane,
5704 // start by splatting that value, then replace the non-constant lanes. This
5705 // is better than the default, which will perform a separate initialization
5707 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5708 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5709 // Now insert the non-constant lanes.
5710 for (unsigned i = 0; i < NumElts; ++i) {
5711 SDValue V = Op.getOperand(i);
5712 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5713 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5714 // Note that type legalization likely mucked about with the VT of the
5715 // source operand, so we may have to convert it here before inserting.
5716 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5722 // If all elements are constants and the case above didn't get hit, fall back
5723 // to the default expansion, which will generate a load from the constant
5728 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5730 SDValue shuffle = ReconstructShuffle(Op, DAG);
5731 if (shuffle != SDValue())
5735 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5736 // know the default expansion would otherwise fall back on something even
5737 // worse. For a vector with one or two non-undef values, that's
5738 // scalar_to_vector for the elements followed by a shuffle (provided the
5739 // shuffle is valid for the target) and materialization element by element
5740 // on the stack followed by a load for everything else.
5741 if (!isConstant && !usesOnlyOneValue) {
5742 SDValue Vec = DAG.getUNDEF(VT);
5743 SDValue Op0 = Op.getOperand(0);
5744 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5746 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5747 // a) Avoid a RMW dependency on the full vector register, and
5748 // b) Allow the register coalescer to fold away the copy if the
5749 // value is already in an S or D register.
5750 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5751 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5753 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5754 DAG.getTargetConstant(SubIdx, MVT::i32));
5755 Vec = SDValue(N, 0);
5758 for (; i < NumElts; ++i) {
5759 SDValue V = Op.getOperand(i);
5760 if (V.getOpcode() == ISD::UNDEF)
5762 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5763 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5768 // Just use the default expansion. We failed to find a better alternative.
5772 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5773 SelectionDAG &DAG) const {
5774 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5776 // Check for non-constant or out of range lane.
5777 EVT VT = Op.getOperand(0).getValueType();
5778 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5779 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5783 // Insertion/extraction are legal for V128 types.
5784 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5785 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5789 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5790 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5793 // For V64 types, we perform insertion by expanding the value
5794 // to a V128 type and perform the insertion on that.
5796 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5797 EVT WideTy = WideVec.getValueType();
5799 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5800 Op.getOperand(1), Op.getOperand(2));
5801 // Re-narrow the resultant vector.
5802 return NarrowVector(Node, DAG);
5806 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5807 SelectionDAG &DAG) const {
5808 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5810 // Check for non-constant or out of range lane.
5811 EVT VT = Op.getOperand(0).getValueType();
5812 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5813 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5817 // Insertion/extraction are legal for V128 types.
5818 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5819 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5823 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5824 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5827 // For V64 types, we perform extraction by expanding the value
5828 // to a V128 type and perform the extraction on that.
5830 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5831 EVT WideTy = WideVec.getValueType();
5833 EVT ExtrTy = WideTy.getVectorElementType();
5834 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5837 // For extractions, we just return the result directly.
5838 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5842 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5843 SelectionDAG &DAG) const {
5844 EVT VT = Op.getOperand(0).getValueType();
5850 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5853 unsigned Val = Cst->getZExtValue();
5855 unsigned Size = Op.getValueType().getSizeInBits();
5859 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5862 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5865 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5868 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5871 llvm_unreachable("Unexpected vector type in extract_subvector!");
5874 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5876 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5882 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5884 if (VT.getVectorNumElements() == 4 &&
5885 (VT.is128BitVector() || VT.is64BitVector())) {
5886 unsigned PFIndexes[4];
5887 for (unsigned i = 0; i != 4; ++i) {
5891 PFIndexes[i] = M[i];
5894 // Compute the index in the perfect shuffle table.
5895 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5896 PFIndexes[2] * 9 + PFIndexes[3];
5897 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5898 unsigned Cost = (PFEntry >> 30);
5906 unsigned DummyUnsigned;
5908 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5909 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5910 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5911 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5912 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5913 isZIPMask(M, VT, DummyUnsigned) ||
5914 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5915 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5916 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5917 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5918 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5921 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5922 /// operand of a vector shift operation, where all the elements of the
5923 /// build_vector must have the same constant integer value.
5924 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5925 // Ignore bit_converts.
5926 while (Op.getOpcode() == ISD::BITCAST)
5927 Op = Op.getOperand(0);
5928 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5929 APInt SplatBits, SplatUndef;
5930 unsigned SplatBitSize;
5932 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5933 HasAnyUndefs, ElementBits) ||
5934 SplatBitSize > ElementBits)
5936 Cnt = SplatBits.getSExtValue();
5940 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5941 /// operand of a vector shift left operation. That value must be in the range:
5942 /// 0 <= Value < ElementBits for a left shift; or
5943 /// 0 <= Value <= ElementBits for a long left shift.
5944 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5945 assert(VT.isVector() && "vector shift count is not a vector type");
5946 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5947 if (!getVShiftImm(Op, ElementBits, Cnt))
5949 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5952 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5953 /// operand of a vector shift right operation. For a shift opcode, the value
5954 /// is positive, but for an intrinsic the value count must be negative. The
5955 /// absolute value must be in the range:
5956 /// 1 <= |Value| <= ElementBits for a right shift; or
5957 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5958 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5960 assert(VT.isVector() && "vector shift count is not a vector type");
5961 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5962 if (!getVShiftImm(Op, ElementBits, Cnt))
5966 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5969 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5970 SelectionDAG &DAG) const {
5971 EVT VT = Op.getValueType();
5975 if (!Op.getOperand(1).getValueType().isVector())
5977 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5979 switch (Op.getOpcode()) {
5981 llvm_unreachable("unexpected shift opcode");
5984 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5985 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5986 DAG.getConstant(Cnt, MVT::i32));
5987 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5988 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5989 Op.getOperand(0), Op.getOperand(1));
5992 // Right shift immediate
5993 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5996 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5997 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5998 DAG.getConstant(Cnt, MVT::i32));
6001 // Right shift register. Note, there is not a shift right register
6002 // instruction, but the shift left register instruction takes a signed
6003 // value, where negative numbers specify a right shift.
6004 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6005 : Intrinsic::aarch64_neon_ushl;
6006 // negate the shift amount
6007 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6008 SDValue NegShiftLeft =
6009 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6010 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6011 return NegShiftLeft;
6017 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6018 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6019 SDLoc dl, SelectionDAG &DAG) {
6020 EVT SrcVT = LHS.getValueType();
6022 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6023 APInt CnstBits(VT.getSizeInBits(), 0);
6024 APInt UndefBits(VT.getSizeInBits(), 0);
6025 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6026 bool IsZero = IsCnst && (CnstBits == 0);
6028 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6032 case AArch64CC::NE: {
6035 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6037 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6038 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6042 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6043 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6046 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6047 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6050 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6051 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6054 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6055 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6059 // If we ignore NaNs then we can use to the MI implementation.
6063 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6064 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6071 case AArch64CC::NE: {
6074 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6076 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6077 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6081 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6082 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6085 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6086 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6089 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6090 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6093 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6094 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6096 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6098 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6101 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6102 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6104 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6106 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6110 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6111 SelectionDAG &DAG) const {
6112 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6113 SDValue LHS = Op.getOperand(0);
6114 SDValue RHS = Op.getOperand(1);
6117 if (LHS.getValueType().getVectorElementType().isInteger()) {
6118 assert(LHS.getValueType() == RHS.getValueType());
6119 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6120 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
6124 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6125 LHS.getValueType().getVectorElementType() == MVT::f64);
6127 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6128 // clean. Some of them require two branches to implement.
6129 AArch64CC::CondCode CC1, CC2;
6131 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6133 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6135 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
6139 if (CC2 != AArch64CC::AL) {
6141 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
6142 if (!Cmp2.getNode())
6145 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
6149 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6154 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6155 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6156 /// specified in the intrinsic calls.
6157 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6159 unsigned Intrinsic) const {
6160 switch (Intrinsic) {
6161 case Intrinsic::aarch64_neon_ld2:
6162 case Intrinsic::aarch64_neon_ld3:
6163 case Intrinsic::aarch64_neon_ld4:
6164 case Intrinsic::aarch64_neon_ld1x2:
6165 case Intrinsic::aarch64_neon_ld1x3:
6166 case Intrinsic::aarch64_neon_ld1x4:
6167 case Intrinsic::aarch64_neon_ld2lane:
6168 case Intrinsic::aarch64_neon_ld3lane:
6169 case Intrinsic::aarch64_neon_ld4lane:
6170 case Intrinsic::aarch64_neon_ld2r:
6171 case Intrinsic::aarch64_neon_ld3r:
6172 case Intrinsic::aarch64_neon_ld4r: {
6173 Info.opc = ISD::INTRINSIC_W_CHAIN;
6174 // Conservatively set memVT to the entire set of vectors loaded.
6175 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6176 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6177 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6180 Info.vol = false; // volatile loads with NEON intrinsics not supported
6181 Info.readMem = true;
6182 Info.writeMem = false;
6185 case Intrinsic::aarch64_neon_st2:
6186 case Intrinsic::aarch64_neon_st3:
6187 case Intrinsic::aarch64_neon_st4:
6188 case Intrinsic::aarch64_neon_st1x2:
6189 case Intrinsic::aarch64_neon_st1x3:
6190 case Intrinsic::aarch64_neon_st1x4:
6191 case Intrinsic::aarch64_neon_st2lane:
6192 case Intrinsic::aarch64_neon_st3lane:
6193 case Intrinsic::aarch64_neon_st4lane: {
6194 Info.opc = ISD::INTRINSIC_VOID;
6195 // Conservatively set memVT to the entire set of vectors stored.
6196 unsigned NumElts = 0;
6197 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6198 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6199 if (!ArgTy->isVectorTy())
6201 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6203 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6204 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6207 Info.vol = false; // volatile stores with NEON intrinsics not supported
6208 Info.readMem = false;
6209 Info.writeMem = true;
6212 case Intrinsic::aarch64_ldaxr:
6213 case Intrinsic::aarch64_ldxr: {
6214 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6215 Info.opc = ISD::INTRINSIC_W_CHAIN;
6216 Info.memVT = MVT::getVT(PtrTy->getElementType());
6217 Info.ptrVal = I.getArgOperand(0);
6219 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6221 Info.readMem = true;
6222 Info.writeMem = false;
6225 case Intrinsic::aarch64_stlxr:
6226 case Intrinsic::aarch64_stxr: {
6227 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6228 Info.opc = ISD::INTRINSIC_W_CHAIN;
6229 Info.memVT = MVT::getVT(PtrTy->getElementType());
6230 Info.ptrVal = I.getArgOperand(1);
6232 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6234 Info.readMem = false;
6235 Info.writeMem = true;
6238 case Intrinsic::aarch64_ldaxp:
6239 case Intrinsic::aarch64_ldxp: {
6240 Info.opc = ISD::INTRINSIC_W_CHAIN;
6241 Info.memVT = MVT::i128;
6242 Info.ptrVal = I.getArgOperand(0);
6246 Info.readMem = true;
6247 Info.writeMem = false;
6250 case Intrinsic::aarch64_stlxp:
6251 case Intrinsic::aarch64_stxp: {
6252 Info.opc = ISD::INTRINSIC_W_CHAIN;
6253 Info.memVT = MVT::i128;
6254 Info.ptrVal = I.getArgOperand(2);
6258 Info.readMem = false;
6259 Info.writeMem = true;
6269 // Truncations from 64-bit GPR to 32-bit GPR is free.
6270 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6271 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6273 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6274 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6275 return NumBits1 > NumBits2;
6277 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6278 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6280 unsigned NumBits1 = VT1.getSizeInBits();
6281 unsigned NumBits2 = VT2.getSizeInBits();
6282 return NumBits1 > NumBits2;
6285 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6287 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6288 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6290 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6291 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6292 return NumBits1 == 32 && NumBits2 == 64;
6294 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6295 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6297 unsigned NumBits1 = VT1.getSizeInBits();
6298 unsigned NumBits2 = VT2.getSizeInBits();
6299 return NumBits1 == 32 && NumBits2 == 64;
6302 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6303 EVT VT1 = Val.getValueType();
6304 if (isZExtFree(VT1, VT2)) {
6308 if (Val.getOpcode() != ISD::LOAD)
6311 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6312 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6313 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6314 VT1.getSizeInBits() <= 32);
6317 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6318 unsigned &RequiredAligment) const {
6319 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6321 // Cyclone supports unaligned accesses.
6322 RequiredAligment = 0;
6323 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6324 return NumBits == 32 || NumBits == 64;
6327 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6328 unsigned &RequiredAligment) const {
6329 if (!LoadedType.isSimple() ||
6330 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6332 // Cyclone supports unaligned accesses.
6333 RequiredAligment = 0;
6334 unsigned NumBits = LoadedType.getSizeInBits();
6335 return NumBits == 32 || NumBits == 64;
6338 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6339 unsigned AlignCheck) {
6340 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6341 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6344 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6345 unsigned SrcAlign, bool IsMemset,
6348 MachineFunction &MF) const {
6349 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6350 // instruction to materialize the v2i64 zero and one store (with restrictive
6351 // addressing mode). Just do two i64 store of zero-registers.
6353 const Function *F = MF.getFunction();
6354 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6355 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6356 Attribute::NoImplicitFloat) &&
6357 (memOpAlign(SrcAlign, DstAlign, 16) ||
6358 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6361 return Size >= 8 ? MVT::i64 : MVT::i32;
6364 // 12-bit optionally shifted immediates are legal for adds.
6365 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6366 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6371 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6372 // immediates is the same as for an add or a sub.
6373 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6376 return isLegalAddImmediate(Immed);
6379 /// isLegalAddressingMode - Return true if the addressing mode represented
6380 /// by AM is legal for this target, for a load/store of the specified type.
6381 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6383 // AArch64 has five basic addressing modes:
6385 // reg + 9-bit signed offset
6386 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6388 // reg + SIZE_IN_BYTES * reg
6390 // No global is ever allowed as a base.
6394 // No reg+reg+imm addressing.
6395 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6398 // check reg + imm case:
6399 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6400 uint64_t NumBytes = 0;
6401 if (Ty->isSized()) {
6402 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6403 NumBytes = NumBits / 8;
6404 if (!isPowerOf2_64(NumBits))
6409 int64_t Offset = AM.BaseOffs;
6411 // 9-bit signed offset
6412 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6415 // 12-bit unsigned offset
6416 unsigned shift = Log2_64(NumBytes);
6417 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6418 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6419 (Offset >> shift) << shift == Offset)
6424 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6426 if (!AM.Scale || AM.Scale == 1 ||
6427 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6432 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6434 // Scaling factors are not free at all.
6435 // Operands | Rt Latency
6436 // -------------------------------------------
6438 // -------------------------------------------
6439 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6440 // Rt, [Xn, Wm, <extend> #imm] |
6441 if (isLegalAddressingMode(AM, Ty))
6442 // Scale represents reg2 * scale, thus account for 1 if
6443 // it is not equal to 0 or 1.
6444 return AM.Scale != 0 && AM.Scale != 1;
6448 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6449 VT = VT.getScalarType();
6454 switch (VT.getSimpleVT().SimpleTy) {
6466 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6467 // LR is a callee-save register, but we must treat it as clobbered by any call
6468 // site. Hence we include LR in the scratch registers, which are in turn added
6469 // as implicit-defs for stackmaps and patchpoints.
6470 static const MCPhysReg ScratchRegs[] = {
6471 AArch64::X16, AArch64::X17, AArch64::LR, 0
6477 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6478 EVT VT = N->getValueType(0);
6479 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6480 // it with shift to let it be lowered to UBFX.
6481 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6482 isa<ConstantSDNode>(N->getOperand(1))) {
6483 uint64_t TruncMask = N->getConstantOperandVal(1);
6484 if (isMask_64(TruncMask) &&
6485 N->getOperand(0).getOpcode() == ISD::SRL &&
6486 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6492 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6494 assert(Ty->isIntegerTy());
6496 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6500 int64_t Val = Imm.getSExtValue();
6501 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6504 if ((int64_t)Val < 0)
6507 Val &= (1LL << 32) - 1;
6509 unsigned LZ = countLeadingZeros((uint64_t)Val);
6510 unsigned Shift = (63 - LZ) / 16;
6511 // MOVZ is free so return true for one or fewer MOVK.
6512 return (Shift < 3) ? true : false;
6515 // Generate SUBS and CSEL for integer abs.
6516 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6517 EVT VT = N->getValueType(0);
6519 SDValue N0 = N->getOperand(0);
6520 SDValue N1 = N->getOperand(1);
6523 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6524 // and change it to SUB and CSEL.
6525 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6526 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6527 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6528 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6529 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6530 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6532 // Generate SUBS & CSEL.
6534 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6535 N0.getOperand(0), DAG.getConstant(0, VT));
6536 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6537 DAG.getConstant(AArch64CC::PL, MVT::i32),
6538 SDValue(Cmp.getNode(), 1));
6543 // performXorCombine - Attempts to handle integer ABS.
6544 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6545 TargetLowering::DAGCombinerInfo &DCI,
6546 const AArch64Subtarget *Subtarget) {
6547 if (DCI.isBeforeLegalizeOps())
6550 return performIntegerAbsCombine(N, DAG);
6554 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6556 std::vector<SDNode *> *Created) const {
6557 // fold (sdiv X, pow2)
6558 EVT VT = N->getValueType(0);
6559 if ((VT != MVT::i32 && VT != MVT::i64) ||
6560 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6564 SDValue N0 = N->getOperand(0);
6565 unsigned Lg2 = Divisor.countTrailingZeros();
6566 SDValue Zero = DAG.getConstant(0, VT);
6567 SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT);
6569 // Add (N0 < 0) ? Pow2 - 1 : 0;
6571 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6572 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6573 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6576 Created->push_back(Cmp.getNode());
6577 Created->push_back(Add.getNode());
6578 Created->push_back(CSel.getNode());
6583 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6585 // If we're dividing by a positive value, we're done. Otherwise, we must
6586 // negate the result.
6587 if (Divisor.isNonNegative())
6591 Created->push_back(SRA.getNode());
6592 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6595 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6596 TargetLowering::DAGCombinerInfo &DCI,
6597 const AArch64Subtarget *Subtarget) {
6598 if (DCI.isBeforeLegalizeOps())
6601 // Multiplication of a power of two plus/minus one can be done more
6602 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6603 // future CPUs have a cheaper MADD instruction, this may need to be
6604 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6605 // 64-bit is 5 cycles, so this is always a win.
6606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6607 APInt Value = C->getAPIntValue();
6608 EVT VT = N->getValueType(0);
6609 if (Value.isNonNegative()) {
6610 // (mul x, 2^N + 1) => (add (shl x, N), x)
6611 APInt VM1 = Value - 1;
6612 if (VM1.isPowerOf2()) {
6613 SDValue ShiftedVal =
6614 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6615 DAG.getConstant(VM1.logBase2(), MVT::i64));
6616 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6619 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6620 APInt VP1 = Value + 1;
6621 if (VP1.isPowerOf2()) {
6622 SDValue ShiftedVal =
6623 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6624 DAG.getConstant(VP1.logBase2(), MVT::i64));
6625 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6629 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6630 APInt VNM1 = -Value - 1;
6631 if (VNM1.isPowerOf2()) {
6632 SDValue ShiftedVal =
6633 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6634 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6636 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6637 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6639 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6640 APInt VNP1 = -Value + 1;
6641 if (VNP1.isPowerOf2()) {
6642 SDValue ShiftedVal =
6643 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6644 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6645 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6653 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6654 SelectionDAG &DAG) {
6655 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6656 // optimize away operation when it's from a constant.
6658 // The general transformation is:
6659 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6660 // AND(VECTOR_CMP(x,y), constant2)
6661 // constant2 = UNARYOP(constant)
6663 // Early exit if this isn't a vector operation, the operand of the
6664 // unary operation isn't a bitwise AND, or if the sizes of the operations
6666 EVT VT = N->getValueType(0);
6667 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6668 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6669 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6672 // Now check that the other operand of the AND is a constant. We could
6673 // make the transformation for non-constant splats as well, but it's unclear
6674 // that would be a benefit as it would not eliminate any operations, just
6675 // perform one more step in scalar code before moving to the vector unit.
6676 if (BuildVectorSDNode *BV =
6677 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6678 // Bail out if the vector isn't a constant.
6679 if (!BV->isConstant())
6682 // Everything checks out. Build up the new and improved node.
6684 EVT IntVT = BV->getValueType(0);
6685 // Create a new constant of the appropriate type for the transformed
6687 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6688 // The AND node needs bitcasts to/from an integer vector type around it.
6689 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6690 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6691 N->getOperand(0)->getOperand(0), MaskConst);
6692 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6699 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6700 // First try to optimize away the conversion when it's conditionally from
6701 // a constant. Vectors only.
6702 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6703 if (Res != SDValue())
6706 EVT VT = N->getValueType(0);
6707 if (VT != MVT::f32 && VT != MVT::f64)
6710 // Only optimize when the source and destination types have the same width.
6711 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6714 // If the result of an integer load is only used by an integer-to-float
6715 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6716 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6717 SDValue N0 = N->getOperand(0);
6718 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6719 // Do not change the width of a volatile load.
6720 !cast<LoadSDNode>(N0)->isVolatile()) {
6721 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6722 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6723 LN0->getPointerInfo(), LN0->isVolatile(),
6724 LN0->isNonTemporal(), LN0->isInvariant(),
6725 LN0->getAlignment());
6727 // Make sure successors of the original load stay after it by updating them
6728 // to use the new Chain.
6729 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6732 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6733 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6739 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6740 /// searches for and classifies those shifts.
6741 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6743 if (N.getOpcode() == ISD::SHL)
6745 else if (N.getOpcode() == ISD::SRL)
6750 if (!isa<ConstantSDNode>(N.getOperand(1)))
6753 ShiftAmount = N->getConstantOperandVal(1);
6754 Src = N->getOperand(0);
6758 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6759 /// registers viewed as a high/low pair. This function looks for the pattern:
6760 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6761 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6763 static SDValue tryCombineToEXTR(SDNode *N,
6764 TargetLowering::DAGCombinerInfo &DCI) {
6765 SelectionDAG &DAG = DCI.DAG;
6767 EVT VT = N->getValueType(0);
6769 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6771 if (VT != MVT::i32 && VT != MVT::i64)
6775 uint32_t ShiftLHS = 0;
6777 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6781 uint32_t ShiftRHS = 0;
6783 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6786 // If they're both trying to come from the high part of the register, they're
6787 // not really an EXTR.
6788 if (LHSFromHi == RHSFromHi)
6791 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6795 std::swap(LHS, RHS);
6796 std::swap(ShiftLHS, ShiftRHS);
6799 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6800 DAG.getConstant(ShiftRHS, MVT::i64));
6803 static SDValue tryCombineToBSL(SDNode *N,
6804 TargetLowering::DAGCombinerInfo &DCI) {
6805 EVT VT = N->getValueType(0);
6806 SelectionDAG &DAG = DCI.DAG;
6812 SDValue N0 = N->getOperand(0);
6813 if (N0.getOpcode() != ISD::AND)
6816 SDValue N1 = N->getOperand(1);
6817 if (N1.getOpcode() != ISD::AND)
6820 // We only have to look for constant vectors here since the general, variable
6821 // case can be handled in TableGen.
6822 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6823 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6824 for (int i = 1; i >= 0; --i)
6825 for (int j = 1; j >= 0; --j) {
6826 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6827 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6831 bool FoundMatch = true;
6832 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6833 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6834 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6836 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6843 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6844 N0->getOperand(1 - i), N1->getOperand(1 - j));
6850 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6851 const AArch64Subtarget *Subtarget) {
6852 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6853 if (!EnableAArch64ExtrGeneration)
6855 SelectionDAG &DAG = DCI.DAG;
6856 EVT VT = N->getValueType(0);
6858 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6861 SDValue Res = tryCombineToEXTR(N, DCI);
6865 Res = tryCombineToBSL(N, DCI);
6872 static SDValue performBitcastCombine(SDNode *N,
6873 TargetLowering::DAGCombinerInfo &DCI,
6874 SelectionDAG &DAG) {
6875 // Wait 'til after everything is legalized to try this. That way we have
6876 // legal vector types and such.
6877 if (DCI.isBeforeLegalizeOps())
6880 // Remove extraneous bitcasts around an extract_subvector.
6882 // (v4i16 (bitconvert
6883 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6885 // (extract_subvector ((v8i16 ...), (i64 4)))
6887 // Only interested in 64-bit vectors as the ultimate result.
6888 EVT VT = N->getValueType(0);
6891 if (VT.getSimpleVT().getSizeInBits() != 64)
6893 // Is the operand an extract_subvector starting at the beginning or halfway
6894 // point of the vector? A low half may also come through as an
6895 // EXTRACT_SUBREG, so look for that, too.
6896 SDValue Op0 = N->getOperand(0);
6897 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6898 !(Op0->isMachineOpcode() &&
6899 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6901 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6902 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6903 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6905 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6906 if (idx != AArch64::dsub)
6908 // The dsub reference is equivalent to a lane zero subvector reference.
6911 // Look through the bitcast of the input to the extract.
6912 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6914 SDValue Source = Op0->getOperand(0)->getOperand(0);
6915 // If the source type has twice the number of elements as our destination
6916 // type, we know this is an extract of the high or low half of the vector.
6917 EVT SVT = Source->getValueType(0);
6918 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6921 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6923 // Create the simplified form to just extract the low or high half of the
6924 // vector directly rather than bothering with the bitcasts.
6926 unsigned NumElements = VT.getVectorNumElements();
6928 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6929 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6931 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6932 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6938 static SDValue performConcatVectorsCombine(SDNode *N,
6939 TargetLowering::DAGCombinerInfo &DCI,
6940 SelectionDAG &DAG) {
6941 // Wait 'til after everything is legalized to try this. That way we have
6942 // legal vector types and such.
6943 if (DCI.isBeforeLegalizeOps())
6947 EVT VT = N->getValueType(0);
6949 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6950 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6951 // canonicalise to that.
6952 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6953 assert(VT.getVectorElementType().getSizeInBits() == 64);
6954 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6955 WidenVector(N->getOperand(0), DAG),
6956 DAG.getConstant(0, MVT::i64));
6959 // Canonicalise concat_vectors so that the right-hand vector has as few
6960 // bit-casts as possible before its real operation. The primary matching
6961 // destination for these operations will be the narrowing "2" instructions,
6962 // which depend on the operation being performed on this right-hand vector.
6964 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6966 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6968 SDValue Op1 = N->getOperand(1);
6969 if (Op1->getOpcode() != ISD::BITCAST)
6971 SDValue RHS = Op1->getOperand(0);
6972 MVT RHSTy = RHS.getValueType().getSimpleVT();
6973 // If the RHS is not a vector, this is not the pattern we're looking for.
6974 if (!RHSTy.isVector())
6977 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6979 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6980 RHSTy.getVectorNumElements() * 2);
6982 ISD::BITCAST, dl, VT,
6983 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6984 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6987 static SDValue tryCombineFixedPointConvert(SDNode *N,
6988 TargetLowering::DAGCombinerInfo &DCI,
6989 SelectionDAG &DAG) {
6990 // Wait 'til after everything is legalized to try this. That way we have
6991 // legal vector types and such.
6992 if (DCI.isBeforeLegalizeOps())
6994 // Transform a scalar conversion of a value from a lane extract into a
6995 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6996 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6997 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6999 // The second form interacts better with instruction selection and the
7000 // register allocator to avoid cross-class register copies that aren't
7001 // coalescable due to a lane reference.
7003 // Check the operand and see if it originates from a lane extract.
7004 SDValue Op1 = N->getOperand(1);
7005 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7006 // Yep, no additional predication needed. Perform the transform.
7007 SDValue IID = N->getOperand(0);
7008 SDValue Shift = N->getOperand(2);
7009 SDValue Vec = Op1.getOperand(0);
7010 SDValue Lane = Op1.getOperand(1);
7011 EVT ResTy = N->getValueType(0);
7015 // The vector width should be 128 bits by the time we get here, even
7016 // if it started as 64 bits (the extract_vector handling will have
7018 assert(Vec.getValueType().getSizeInBits() == 128 &&
7019 "unexpected vector size on extract_vector_elt!");
7020 if (Vec.getValueType() == MVT::v4i32)
7021 VecResTy = MVT::v4f32;
7022 else if (Vec.getValueType() == MVT::v2i64)
7023 VecResTy = MVT::v2f64;
7025 llvm_unreachable("unexpected vector type!");
7028 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7029 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7034 // AArch64 high-vector "long" operations are formed by performing the non-high
7035 // version on an extract_subvector of each operand which gets the high half:
7037 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7039 // However, there are cases which don't have an extract_high explicitly, but
7040 // have another operation that can be made compatible with one for free. For
7043 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7045 // This routine does the actual conversion of such DUPs, once outer routines
7046 // have determined that everything else is in order.
7047 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7048 // We can handle most types of duplicate, but the lane ones have an extra
7049 // operand saying *which* lane, so we need to know.
7051 switch (N.getOpcode()) {
7052 case AArch64ISD::DUP:
7055 case AArch64ISD::DUPLANE8:
7056 case AArch64ISD::DUPLANE16:
7057 case AArch64ISD::DUPLANE32:
7058 case AArch64ISD::DUPLANE64:
7065 MVT NarrowTy = N.getSimpleValueType();
7066 if (!NarrowTy.is64BitVector())
7069 MVT ElementTy = NarrowTy.getVectorElementType();
7070 unsigned NumElems = NarrowTy.getVectorNumElements();
7071 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7075 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7078 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7080 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7081 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7084 static bool isEssentiallyExtractSubvector(SDValue N) {
7085 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7088 return N.getOpcode() == ISD::BITCAST &&
7089 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7092 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7093 struct GenericSetCCInfo {
7094 const SDValue *Opnd0;
7095 const SDValue *Opnd1;
7099 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7100 struct AArch64SetCCInfo {
7102 AArch64CC::CondCode CC;
7105 /// \brief Helper structure to keep track of SetCC information.
7107 GenericSetCCInfo Generic;
7108 AArch64SetCCInfo AArch64;
7111 /// \brief Helper structure to be able to read SetCC information. If set to
7112 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7113 /// GenericSetCCInfo.
7114 struct SetCCInfoAndKind {
7119 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7121 /// AArch64 lowered one.
7122 /// \p SetCCInfo is filled accordingly.
7123 /// \post SetCCInfo is meanginfull only when this function returns true.
7124 /// \return True when Op is a kind of SET_CC operation.
7125 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7126 // If this is a setcc, this is straight forward.
7127 if (Op.getOpcode() == ISD::SETCC) {
7128 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7129 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7130 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7131 SetCCInfo.IsAArch64 = false;
7134 // Otherwise, check if this is a matching csel instruction.
7138 if (Op.getOpcode() != AArch64ISD::CSEL)
7140 // Set the information about the operands.
7141 // TODO: we want the operands of the Cmp not the csel
7142 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7143 SetCCInfo.IsAArch64 = true;
7144 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7145 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7147 // Check that the operands matches the constraints:
7148 // (1) Both operands must be constants.
7149 // (2) One must be 1 and the other must be 0.
7150 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7151 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7154 if (!TValue || !FValue)
7158 if (!TValue->isOne()) {
7159 // Update the comparison when we are interested in !cc.
7160 std::swap(TValue, FValue);
7161 SetCCInfo.Info.AArch64.CC =
7162 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7164 return TValue->isOne() && FValue->isNullValue();
7167 // Returns true if Op is setcc or zext of setcc.
7168 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7169 if (isSetCC(Op, Info))
7171 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7172 isSetCC(Op->getOperand(0), Info));
7175 // The folding we want to perform is:
7176 // (add x, [zext] (setcc cc ...) )
7178 // (csel x, (add x, 1), !cc ...)
7180 // The latter will get matched to a CSINC instruction.
7181 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7182 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7183 SDValue LHS = Op->getOperand(0);
7184 SDValue RHS = Op->getOperand(1);
7185 SetCCInfoAndKind InfoAndKind;
7187 // If neither operand is a SET_CC, give up.
7188 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7189 std::swap(LHS, RHS);
7190 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7194 // FIXME: This could be generatized to work for FP comparisons.
7195 EVT CmpVT = InfoAndKind.IsAArch64
7196 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7197 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7198 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7204 if (InfoAndKind.IsAArch64) {
7205 CCVal = DAG.getConstant(
7206 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7207 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7209 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7210 *InfoAndKind.Info.Generic.Opnd1,
7211 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7214 EVT VT = Op->getValueType(0);
7215 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7216 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7219 // The basic add/sub long vector instructions have variants with "2" on the end
7220 // which act on the high-half of their inputs. They are normally matched by
7223 // (add (zeroext (extract_high LHS)),
7224 // (zeroext (extract_high RHS)))
7225 // -> uaddl2 vD, vN, vM
7227 // However, if one of the extracts is something like a duplicate, this
7228 // instruction can still be used profitably. This function puts the DAG into a
7229 // more appropriate form for those patterns to trigger.
7230 static SDValue performAddSubLongCombine(SDNode *N,
7231 TargetLowering::DAGCombinerInfo &DCI,
7232 SelectionDAG &DAG) {
7233 if (DCI.isBeforeLegalizeOps())
7236 MVT VT = N->getSimpleValueType(0);
7237 if (!VT.is128BitVector()) {
7238 if (N->getOpcode() == ISD::ADD)
7239 return performSetccAddFolding(N, DAG);
7243 // Make sure both branches are extended in the same way.
7244 SDValue LHS = N->getOperand(0);
7245 SDValue RHS = N->getOperand(1);
7246 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7247 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7248 LHS.getOpcode() != RHS.getOpcode())
7251 unsigned ExtType = LHS.getOpcode();
7253 // It's not worth doing if at least one of the inputs isn't already an
7254 // extract, but we don't know which it'll be so we have to try both.
7255 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7256 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7260 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7261 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7262 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7266 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7269 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7272 // Massage DAGs which we can use the high-half "long" operations on into
7273 // something isel will recognize better. E.g.
7275 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7276 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7277 // (extract_high (v2i64 (dup128 scalar)))))
7279 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7280 TargetLowering::DAGCombinerInfo &DCI,
7281 SelectionDAG &DAG) {
7282 if (DCI.isBeforeLegalizeOps())
7285 SDValue LHS = N->getOperand(1);
7286 SDValue RHS = N->getOperand(2);
7287 assert(LHS.getValueType().is64BitVector() &&
7288 RHS.getValueType().is64BitVector() &&
7289 "unexpected shape for long operation");
7291 // Either node could be a DUP, but it's not worth doing both of them (you'd
7292 // just as well use the non-high version) so look for a corresponding extract
7293 // operation on the other "wing".
7294 if (isEssentiallyExtractSubvector(LHS)) {
7295 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7298 } else if (isEssentiallyExtractSubvector(RHS)) {
7299 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7304 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7305 N->getOperand(0), LHS, RHS);
7308 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7309 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7310 unsigned ElemBits = ElemTy.getSizeInBits();
7312 int64_t ShiftAmount;
7313 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7314 APInt SplatValue, SplatUndef;
7315 unsigned SplatBitSize;
7317 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7318 HasAnyUndefs, ElemBits) ||
7319 SplatBitSize != ElemBits)
7322 ShiftAmount = SplatValue.getSExtValue();
7323 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7324 ShiftAmount = CVN->getSExtValue();
7332 llvm_unreachable("Unknown shift intrinsic");
7333 case Intrinsic::aarch64_neon_sqshl:
7334 Opcode = AArch64ISD::SQSHL_I;
7335 IsRightShift = false;
7337 case Intrinsic::aarch64_neon_uqshl:
7338 Opcode = AArch64ISD::UQSHL_I;
7339 IsRightShift = false;
7341 case Intrinsic::aarch64_neon_srshl:
7342 Opcode = AArch64ISD::SRSHR_I;
7343 IsRightShift = true;
7345 case Intrinsic::aarch64_neon_urshl:
7346 Opcode = AArch64ISD::URSHR_I;
7347 IsRightShift = true;
7349 case Intrinsic::aarch64_neon_sqshlu:
7350 Opcode = AArch64ISD::SQSHLU_I;
7351 IsRightShift = false;
7355 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7356 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7357 DAG.getConstant(-ShiftAmount, MVT::i32));
7358 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7359 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7360 DAG.getConstant(ShiftAmount, MVT::i32));
7365 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7366 // the intrinsics must be legal and take an i32, this means there's almost
7367 // certainly going to be a zext in the DAG which we can eliminate.
7368 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7369 SDValue AndN = N->getOperand(2);
7370 if (AndN.getOpcode() != ISD::AND)
7373 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7374 if (!CMask || CMask->getZExtValue() != Mask)
7377 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7378 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7381 static SDValue performIntrinsicCombine(SDNode *N,
7382 TargetLowering::DAGCombinerInfo &DCI,
7383 const AArch64Subtarget *Subtarget) {
7384 SelectionDAG &DAG = DCI.DAG;
7385 unsigned IID = getIntrinsicID(N);
7389 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7390 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7391 return tryCombineFixedPointConvert(N, DCI, DAG);
7393 case Intrinsic::aarch64_neon_fmax:
7394 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7395 N->getOperand(1), N->getOperand(2));
7396 case Intrinsic::aarch64_neon_fmin:
7397 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7398 N->getOperand(1), N->getOperand(2));
7399 case Intrinsic::aarch64_neon_smull:
7400 case Intrinsic::aarch64_neon_umull:
7401 case Intrinsic::aarch64_neon_pmull:
7402 case Intrinsic::aarch64_neon_sqdmull:
7403 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7404 case Intrinsic::aarch64_neon_sqshl:
7405 case Intrinsic::aarch64_neon_uqshl:
7406 case Intrinsic::aarch64_neon_sqshlu:
7407 case Intrinsic::aarch64_neon_srshl:
7408 case Intrinsic::aarch64_neon_urshl:
7409 return tryCombineShiftImm(IID, N, DAG);
7410 case Intrinsic::aarch64_crc32b:
7411 case Intrinsic::aarch64_crc32cb:
7412 return tryCombineCRC32(0xff, N, DAG);
7413 case Intrinsic::aarch64_crc32h:
7414 case Intrinsic::aarch64_crc32ch:
7415 return tryCombineCRC32(0xffff, N, DAG);
7420 static SDValue performExtendCombine(SDNode *N,
7421 TargetLowering::DAGCombinerInfo &DCI,
7422 SelectionDAG &DAG) {
7423 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7424 // we can convert that DUP into another extract_high (of a bigger DUP), which
7425 // helps the backend to decide that an sabdl2 would be useful, saving a real
7426 // extract_high operation.
7427 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7428 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7429 SDNode *ABDNode = N->getOperand(0).getNode();
7430 unsigned IID = getIntrinsicID(ABDNode);
7431 if (IID == Intrinsic::aarch64_neon_sabd ||
7432 IID == Intrinsic::aarch64_neon_uabd) {
7433 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7434 if (!NewABD.getNode())
7437 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7442 // This is effectively a custom type legalization for AArch64.
7444 // Type legalization will split an extend of a small, legal, type to a larger
7445 // illegal type by first splitting the destination type, often creating
7446 // illegal source types, which then get legalized in isel-confusing ways,
7447 // leading to really terrible codegen. E.g.,
7448 // %result = v8i32 sext v8i8 %value
7450 // %losrc = extract_subreg %value, ...
7451 // %hisrc = extract_subreg %value, ...
7452 // %lo = v4i32 sext v4i8 %losrc
7453 // %hi = v4i32 sext v4i8 %hisrc
7454 // Things go rapidly downhill from there.
7456 // For AArch64, the [sz]ext vector instructions can only go up one element
7457 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7458 // take two instructions.
7460 // This implies that the most efficient way to do the extend from v8i8
7461 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7462 // the normal splitting to happen for the v8i16->v8i32.
7464 // This is pre-legalization to catch some cases where the default
7465 // type legalization will create ill-tempered code.
7466 if (!DCI.isBeforeLegalizeOps())
7469 // We're only interested in cleaning things up for non-legal vector types
7470 // here. If both the source and destination are legal, things will just
7471 // work naturally without any fiddling.
7472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7473 EVT ResVT = N->getValueType(0);
7474 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7476 // If the vector type isn't a simple VT, it's beyond the scope of what
7477 // we're worried about here. Let legalization do its thing and hope for
7479 if (!ResVT.isSimple())
7482 SDValue Src = N->getOperand(0);
7483 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7484 // If the source VT is a 64-bit vector, we can play games and get the
7485 // better results we want.
7486 if (SrcVT.getSizeInBits() != 64)
7489 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7490 unsigned ElementCount = SrcVT.getVectorNumElements();
7491 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7493 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7495 // Now split the rest of the operation into two halves, each with a 64
7499 unsigned NumElements = ResVT.getVectorNumElements();
7500 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7501 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7502 ResVT.getVectorElementType(), NumElements / 2);
7504 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7505 LoVT.getVectorNumElements());
7506 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7507 DAG.getIntPtrConstant(0));
7508 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7509 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7510 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7511 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7513 // Now combine the parts back together so we still have a single result
7514 // like the combiner expects.
7515 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7518 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7519 /// value. The load store optimizer pass will merge them to store pair stores.
7520 /// This has better performance than a splat of the scalar followed by a split
7521 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7522 /// followed by an ext.b and two stores.
7523 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7524 SDValue StVal = St->getValue();
7525 EVT VT = StVal.getValueType();
7527 // Don't replace floating point stores, they possibly won't be transformed to
7528 // stp because of the store pair suppress pass.
7529 if (VT.isFloatingPoint())
7532 // Check for insert vector elements.
7533 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7536 // We can express a splat as store pair(s) for 2 or 4 elements.
7537 unsigned NumVecElts = VT.getVectorNumElements();
7538 if (NumVecElts != 4 && NumVecElts != 2)
7540 SDValue SplatVal = StVal.getOperand(1);
7541 unsigned RemainInsertElts = NumVecElts - 1;
7543 // Check that this is a splat.
7544 while (--RemainInsertElts) {
7545 SDValue NextInsertElt = StVal.getOperand(0);
7546 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7548 if (NextInsertElt.getOperand(1) != SplatVal)
7550 StVal = NextInsertElt;
7552 unsigned OrigAlignment = St->getAlignment();
7553 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7554 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7556 // Create scalar stores. This is at least as good as the code sequence for a
7557 // split unaligned store wich is a dup.s, ext.b, and two stores.
7558 // Most of the time the three stores should be replaced by store pair
7559 // instructions (stp).
7561 SDValue BasePtr = St->getBasePtr();
7563 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7564 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7566 unsigned Offset = EltOffset;
7567 while (--NumVecElts) {
7568 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7569 DAG.getConstant(Offset, MVT::i64));
7570 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7571 St->getPointerInfo(), St->isVolatile(),
7572 St->isNonTemporal(), Alignment);
7573 Offset += EltOffset;
7578 static SDValue performSTORECombine(SDNode *N,
7579 TargetLowering::DAGCombinerInfo &DCI,
7581 const AArch64Subtarget *Subtarget) {
7582 if (!DCI.isBeforeLegalize())
7585 StoreSDNode *S = cast<StoreSDNode>(N);
7586 if (S->isVolatile())
7589 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7590 // page boundries. We want to split such stores.
7591 if (!Subtarget->isCyclone())
7594 // Don't split at Oz.
7595 MachineFunction &MF = DAG.getMachineFunction();
7596 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7597 AttributeSet::FunctionIndex, Attribute::MinSize);
7601 SDValue StVal = S->getValue();
7602 EVT VT = StVal.getValueType();
7604 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7605 // those up regresses performance on micro-benchmarks and olden/bh.
7606 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7609 // Split unaligned 16B stores. They are terrible for performance.
7610 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7611 // extensions can use this to mark that it does not want splitting to happen
7612 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7613 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7614 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7615 S->getAlignment() <= 2)
7618 // If we get a splat of a scalar convert this vector store to a store of
7619 // scalars. They will be merged into store pairs thereby removing two
7621 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7622 if (ReplacedSplat != SDValue())
7623 return ReplacedSplat;
7626 unsigned NumElts = VT.getVectorNumElements() / 2;
7627 // Split VT into two.
7629 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7630 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7631 DAG.getIntPtrConstant(0));
7632 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7633 DAG.getIntPtrConstant(NumElts));
7634 SDValue BasePtr = S->getBasePtr();
7636 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7637 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7638 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7639 DAG.getConstant(8, MVT::i64));
7640 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7641 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7645 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7646 /// post-increment LD1R.
7647 static SDValue performPostLD1Combine(SDNode *N,
7648 TargetLowering::DAGCombinerInfo &DCI,
7650 if (DCI.isBeforeLegalizeOps())
7653 SelectionDAG &DAG = DCI.DAG;
7654 EVT VT = N->getValueType(0);
7656 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7657 SDNode *LD = N->getOperand(LoadIdx).getNode();
7658 // If it is not LOAD, can not do such combine.
7659 if (LD->getOpcode() != ISD::LOAD)
7662 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7663 EVT MemVT = LoadSDN->getMemoryVT();
7664 // Check if memory operand is the same type as the vector element.
7665 if (MemVT != VT.getVectorElementType())
7668 // Check if there are other uses. If so, do not combine as it will introduce
7670 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7672 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7678 SDValue Addr = LD->getOperand(1);
7679 SDValue Vector = N->getOperand(0);
7680 // Search for a use of the address operand that is an increment.
7681 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7682 Addr.getNode()->use_end(); UI != UE; ++UI) {
7684 if (User->getOpcode() != ISD::ADD
7685 || UI.getUse().getResNo() != Addr.getResNo())
7688 // Check that the add is independent of the load. Otherwise, folding it
7689 // would create a cycle.
7690 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7692 // Also check that add is not used in the vector operand. This would also
7694 if (User->isPredecessorOf(Vector.getNode()))
7697 // If the increment is a constant, it must match the memory ref size.
7698 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7699 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7700 uint32_t IncVal = CInc->getZExtValue();
7701 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7702 if (IncVal != NumBytes)
7704 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7707 SmallVector<SDValue, 8> Ops;
7708 Ops.push_back(LD->getOperand(0)); // Chain
7710 Ops.push_back(Vector); // The vector to be inserted
7711 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7713 Ops.push_back(Addr);
7716 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7717 SDVTList SDTys = DAG.getVTList(Tys);
7718 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7719 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7721 LoadSDN->getMemOperand());
7724 std::vector<SDValue> NewResults;
7725 NewResults.push_back(SDValue(LD, 0)); // The result of load
7726 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7727 DCI.CombineTo(LD, NewResults);
7728 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7729 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7736 /// Target-specific DAG combine function for NEON load/store intrinsics
7737 /// to merge base address updates.
7738 static SDValue performNEONPostLDSTCombine(SDNode *N,
7739 TargetLowering::DAGCombinerInfo &DCI,
7740 SelectionDAG &DAG) {
7741 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7744 unsigned AddrOpIdx = N->getNumOperands() - 1;
7745 SDValue Addr = N->getOperand(AddrOpIdx);
7747 // Search for a use of the address operand that is an increment.
7748 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7749 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7751 if (User->getOpcode() != ISD::ADD ||
7752 UI.getUse().getResNo() != Addr.getResNo())
7755 // Check that the add is independent of the load/store. Otherwise, folding
7756 // it would create a cycle.
7757 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7760 // Find the new opcode for the updating load/store.
7761 bool IsStore = false;
7762 bool IsLaneOp = false;
7763 bool IsDupOp = false;
7764 unsigned NewOpc = 0;
7765 unsigned NumVecs = 0;
7766 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7768 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7769 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7771 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7773 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7775 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7776 NumVecs = 2; IsStore = true; break;
7777 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7778 NumVecs = 3; IsStore = true; break;
7779 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7780 NumVecs = 4; IsStore = true; break;
7781 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7783 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7785 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7787 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7788 NumVecs = 2; IsStore = true; break;
7789 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7790 NumVecs = 3; IsStore = true; break;
7791 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7792 NumVecs = 4; IsStore = true; break;
7793 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7794 NumVecs = 2; IsDupOp = true; break;
7795 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7796 NumVecs = 3; IsDupOp = true; break;
7797 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7798 NumVecs = 4; IsDupOp = true; break;
7799 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7800 NumVecs = 2; IsLaneOp = true; break;
7801 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7802 NumVecs = 3; IsLaneOp = true; break;
7803 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7804 NumVecs = 4; IsLaneOp = true; break;
7805 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7806 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7807 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7808 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7809 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7810 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7815 VecTy = N->getOperand(2).getValueType();
7817 VecTy = N->getValueType(0);
7819 // If the increment is a constant, it must match the memory ref size.
7820 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7821 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7822 uint32_t IncVal = CInc->getZExtValue();
7823 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7824 if (IsLaneOp || IsDupOp)
7825 NumBytes /= VecTy.getVectorNumElements();
7826 if (IncVal != NumBytes)
7828 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7830 SmallVector<SDValue, 8> Ops;
7831 Ops.push_back(N->getOperand(0)); // Incoming chain
7832 // Load lane and store have vector list as input.
7833 if (IsLaneOp || IsStore)
7834 for (unsigned i = 2; i < AddrOpIdx; ++i)
7835 Ops.push_back(N->getOperand(i));
7836 Ops.push_back(Addr); // Base register
7841 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7843 for (n = 0; n < NumResultVecs; ++n)
7845 Tys[n++] = MVT::i64; // Type of write back register
7846 Tys[n] = MVT::Other; // Type of the chain
7847 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
7849 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7850 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7851 MemInt->getMemoryVT(),
7852 MemInt->getMemOperand());
7855 std::vector<SDValue> NewResults;
7856 for (unsigned i = 0; i < NumResultVecs; ++i) {
7857 NewResults.push_back(SDValue(UpdN.getNode(), i));
7859 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7860 DCI.CombineTo(N, NewResults);
7861 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7868 // Optimize compare with zero and branch.
7869 static SDValue performBRCONDCombine(SDNode *N,
7870 TargetLowering::DAGCombinerInfo &DCI,
7871 SelectionDAG &DAG) {
7872 SDValue Chain = N->getOperand(0);
7873 SDValue Dest = N->getOperand(1);
7874 SDValue CCVal = N->getOperand(2);
7875 SDValue Cmp = N->getOperand(3);
7877 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7878 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7879 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7882 unsigned CmpOpc = Cmp.getOpcode();
7883 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7886 // Only attempt folding if there is only one use of the flag and no use of the
7888 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7891 SDValue LHS = Cmp.getOperand(0);
7892 SDValue RHS = Cmp.getOperand(1);
7894 assert(LHS.getValueType() == RHS.getValueType() &&
7895 "Expected the value type to be the same for both operands!");
7896 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7899 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7900 std::swap(LHS, RHS);
7902 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7905 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7906 LHS.getOpcode() == ISD::SRL)
7909 // Fold the compare into the branch instruction.
7911 if (CC == AArch64CC::EQ)
7912 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7914 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7916 // Do not add new nodes to DAG combiner worklist.
7917 DCI.CombineTo(N, BR, false);
7922 // vselect (v1i1 setcc) ->
7923 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7924 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7925 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7927 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7928 SDValue N0 = N->getOperand(0);
7929 EVT CCVT = N0.getValueType();
7931 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7932 CCVT.getVectorElementType() != MVT::i1)
7935 EVT ResVT = N->getValueType(0);
7936 EVT CmpVT = N0.getOperand(0).getValueType();
7937 // Only combine when the result type is of the same size as the compared
7939 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7942 SDValue IfTrue = N->getOperand(1);
7943 SDValue IfFalse = N->getOperand(2);
7945 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7946 N0.getOperand(0), N0.getOperand(1),
7947 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7948 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7952 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7953 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7954 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7955 /// with a vector one followed by a DUP shuffle on the result.
7956 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7957 SDValue N0 = N->getOperand(0);
7958 EVT ResVT = N->getValueType(0);
7960 if (!N->getOperand(1).getValueType().isVector())
7963 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7968 EVT SrcVT = N0.getOperand(0).getValueType();
7969 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7970 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7971 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7973 // First perform a vector comparison, where lane 0 is the one we're interested
7976 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7978 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7979 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7981 // Now duplicate the comparison mask we want across all other lanes.
7982 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7983 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7984 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7987 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7990 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7991 DAGCombinerInfo &DCI) const {
7992 SelectionDAG &DAG = DCI.DAG;
7993 switch (N->getOpcode()) {
7998 return performAddSubLongCombine(N, DCI, DAG);
8000 return performXorCombine(N, DAG, DCI, Subtarget);
8002 return performMulCombine(N, DAG, DCI, Subtarget);
8003 case ISD::SINT_TO_FP:
8004 case ISD::UINT_TO_FP:
8005 return performIntToFpCombine(N, DAG);
8007 return performORCombine(N, DCI, Subtarget);
8008 case ISD::INTRINSIC_WO_CHAIN:
8009 return performIntrinsicCombine(N, DCI, Subtarget);
8010 case ISD::ANY_EXTEND:
8011 case ISD::ZERO_EXTEND:
8012 case ISD::SIGN_EXTEND:
8013 return performExtendCombine(N, DCI, DAG);
8015 return performBitcastCombine(N, DCI, DAG);
8016 case ISD::CONCAT_VECTORS:
8017 return performConcatVectorsCombine(N, DCI, DAG);
8019 return performSelectCombine(N, DAG);
8021 return performVSelectCombine(N, DCI.DAG);
8023 return performSTORECombine(N, DCI, DAG, Subtarget);
8024 case AArch64ISD::BRCOND:
8025 return performBRCONDCombine(N, DCI, DAG);
8026 case AArch64ISD::DUP:
8027 return performPostLD1Combine(N, DCI, false);
8028 case ISD::INSERT_VECTOR_ELT:
8029 return performPostLD1Combine(N, DCI, true);
8030 case ISD::INTRINSIC_VOID:
8031 case ISD::INTRINSIC_W_CHAIN:
8032 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8033 case Intrinsic::aarch64_neon_ld2:
8034 case Intrinsic::aarch64_neon_ld3:
8035 case Intrinsic::aarch64_neon_ld4:
8036 case Intrinsic::aarch64_neon_ld1x2:
8037 case Intrinsic::aarch64_neon_ld1x3:
8038 case Intrinsic::aarch64_neon_ld1x4:
8039 case Intrinsic::aarch64_neon_ld2lane:
8040 case Intrinsic::aarch64_neon_ld3lane:
8041 case Intrinsic::aarch64_neon_ld4lane:
8042 case Intrinsic::aarch64_neon_ld2r:
8043 case Intrinsic::aarch64_neon_ld3r:
8044 case Intrinsic::aarch64_neon_ld4r:
8045 case Intrinsic::aarch64_neon_st2:
8046 case Intrinsic::aarch64_neon_st3:
8047 case Intrinsic::aarch64_neon_st4:
8048 case Intrinsic::aarch64_neon_st1x2:
8049 case Intrinsic::aarch64_neon_st1x3:
8050 case Intrinsic::aarch64_neon_st1x4:
8051 case Intrinsic::aarch64_neon_st2lane:
8052 case Intrinsic::aarch64_neon_st3lane:
8053 case Intrinsic::aarch64_neon_st4lane:
8054 return performNEONPostLDSTCombine(N, DCI, DAG);
8062 // Check if the return value is used as only a return value, as otherwise
8063 // we can't perform a tail-call. In particular, we need to check for
8064 // target ISD nodes that are returns and any other "odd" constructs
8065 // that the generic analysis code won't necessarily catch.
8066 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8067 SDValue &Chain) const {
8068 if (N->getNumValues() != 1)
8070 if (!N->hasNUsesOfValue(1, 0))
8073 SDValue TCChain = Chain;
8074 SDNode *Copy = *N->use_begin();
8075 if (Copy->getOpcode() == ISD::CopyToReg) {
8076 // If the copy has a glue operand, we conservatively assume it isn't safe to
8077 // perform a tail call.
8078 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8081 TCChain = Copy->getOperand(0);
8082 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8085 bool HasRet = false;
8086 for (SDNode *Node : Copy->uses()) {
8087 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8099 // Return whether the an instruction can potentially be optimized to a tail
8100 // call. This will cause the optimizers to attempt to move, or duplicate,
8101 // return instructions to help enable tail call optimizations for this
8103 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8104 if (!CI->isTailCall())
8110 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8112 ISD::MemIndexedMode &AM,
8114 SelectionDAG &DAG) const {
8115 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8118 Base = Op->getOperand(0);
8119 // All of the indexed addressing mode instructions take a signed
8120 // 9 bit immediate offset.
8121 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8122 int64_t RHSC = (int64_t)RHS->getZExtValue();
8123 if (RHSC >= 256 || RHSC <= -256)
8125 IsInc = (Op->getOpcode() == ISD::ADD);
8126 Offset = Op->getOperand(1);
8132 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8134 ISD::MemIndexedMode &AM,
8135 SelectionDAG &DAG) const {
8138 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8139 VT = LD->getMemoryVT();
8140 Ptr = LD->getBasePtr();
8141 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8142 VT = ST->getMemoryVT();
8143 Ptr = ST->getBasePtr();
8148 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8150 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8154 bool AArch64TargetLowering::getPostIndexedAddressParts(
8155 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8156 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8159 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8160 VT = LD->getMemoryVT();
8161 Ptr = LD->getBasePtr();
8162 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8163 VT = ST->getMemoryVT();
8164 Ptr = ST->getBasePtr();
8169 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8171 // Post-indexing updates the base, so it's not a valid transform
8172 // if that's not the same as the load's pointer.
8175 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8179 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8180 SelectionDAG &DAG) {
8181 if (N->getValueType(0) != MVT::i16)
8185 SDValue Op = N->getOperand(0);
8186 assert(Op.getValueType() == MVT::f16 &&
8187 "Inconsistent bitcast? Only 16-bit types should be i16 or f16");
8189 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8190 DAG.getUNDEF(MVT::i32), Op,
8191 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8193 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8194 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8197 void AArch64TargetLowering::ReplaceNodeResults(
8198 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8199 switch (N->getOpcode()) {
8201 llvm_unreachable("Don't know how to custom expand this");
8203 ReplaceBITCASTResults(N, Results, DAG);
8205 case ISD::FP_TO_UINT:
8206 case ISD::FP_TO_SINT:
8207 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8208 // Let normal code take care of it by not adding anything to Results.
8213 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
8214 // Loads and stores less than 128-bits are already atomic; ones above that
8215 // are doomed anyway, so defer to the default libcall and blame the OS when
8217 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
8218 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
8219 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
8220 return LI->getType()->getPrimitiveSizeInBits() == 128;
8222 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
8223 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
8226 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8230 TargetLoweringBase::LegalizeTypeAction
8231 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8232 MVT SVT = VT.getSimpleVT();
8233 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8234 // v4i16, v2i32 instead of to promote.
8235 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8236 || SVT == MVT::v1f32)
8237 return TypeWidenVector;
8239 return TargetLoweringBase::getPreferredVectorAction(VT);
8242 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8243 AtomicOrdering Ord) const {
8244 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8245 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8246 bool IsAcquire = isAtLeastAcquire(Ord);
8248 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8249 // intrinsic must return {i64, i64} and we have to recombine them into a
8250 // single i128 here.
8251 if (ValTy->getPrimitiveSizeInBits() == 128) {
8253 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8254 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8256 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8257 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8259 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8260 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8261 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8262 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8263 return Builder.CreateOr(
8264 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8267 Type *Tys[] = { Addr->getType() };
8269 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8270 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8272 return Builder.CreateTruncOrBitCast(
8273 Builder.CreateCall(Ldxr, Addr),
8274 cast<PointerType>(Addr->getType())->getElementType());
8277 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8278 Value *Val, Value *Addr,
8279 AtomicOrdering Ord) const {
8280 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8281 bool IsRelease = isAtLeastRelease(Ord);
8283 // Since the intrinsics must have legal type, the i128 intrinsics take two
8284 // parameters: "i64, i64". We must marshal Val into the appropriate form
8286 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8288 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8289 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8290 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8292 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8293 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8294 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8295 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8299 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8300 Type *Tys[] = { Addr->getType() };
8301 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8303 return Builder.CreateCall2(
8304 Stxr, Builder.CreateZExtOrBitCast(
8305 Val, Stxr->getFunctionType()->getParamType(0)),