1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64PerfectShuffle.h"
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
48 static cl::opt<AlignMode>
49 Align(cl::desc("Load/store alignment support"),
50 cl::Hidden, cl::init(NoStrictAlign),
52 clEnumValN(StrictAlign, "aarch64-strict-align",
53 "Disallow all unaligned memory accesses"),
54 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
55 "Allow unaligned memory accesses"),
58 // Place holder until extr generation is tested fully.
60 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
61 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
65 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
66 cl::desc("Allow AArch64 SLI/SRI formation"),
69 //===----------------------------------------------------------------------===//
70 // AArch64 Lowering public interface.
71 //===----------------------------------------------------------------------===//
72 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
73 if (TT.isOSBinFormatMachO())
74 return new AArch64_MachoTargetObjectFile();
76 return new AArch64_ELFTargetObjectFile();
79 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
81 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
84 // we have to make something up. Arbitrarily, choose ZeroOrOne.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // When comparing vectors the result sets the different elements in the
87 // vector to all-one or all-zero.
88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
90 // Set up the register classes.
91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
94 if (Subtarget->hasFPARMv8()) {
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
101 if (Subtarget->hasNEON()) {
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
104 // Someone set us up the NEON.
105 addDRTypeForNEON(MVT::v2f32);
106 addDRTypeForNEON(MVT::v8i8);
107 addDRTypeForNEON(MVT::v4i16);
108 addDRTypeForNEON(MVT::v2i32);
109 addDRTypeForNEON(MVT::v1i64);
110 addDRTypeForNEON(MVT::v1f64);
111 addDRTypeForNEON(MVT::v4f16);
113 addQRTypeForNEON(MVT::v4f32);
114 addQRTypeForNEON(MVT::v2f64);
115 addQRTypeForNEON(MVT::v16i8);
116 addQRTypeForNEON(MVT::v8i16);
117 addQRTypeForNEON(MVT::v4i32);
118 addQRTypeForNEON(MVT::v2i64);
119 addQRTypeForNEON(MVT::v8f16);
122 // Compute derived properties from the register classes
123 computeRegisterProperties();
125 // Provide all sorts of operation actions
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
128 setOperationAction(ISD::SETCC, MVT::i32, Custom);
129 setOperationAction(ISD::SETCC, MVT::i64, Custom);
130 setOperationAction(ISD::SETCC, MVT::f32, Custom);
131 setOperationAction(ISD::SETCC, MVT::f64, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::FREM, MVT::f32, Expand);
153 setOperationAction(ISD::FREM, MVT::f64, Expand);
154 setOperationAction(ISD::FREM, MVT::f80, Expand);
156 // Custom lowering hooks are needed for XOR
157 // to fold it into CSINC/CSINV.
158 setOperationAction(ISD::XOR, MVT::i32, Custom);
159 setOperationAction(ISD::XOR, MVT::i64, Custom);
161 // Virtually no operation on f128 is legal, but LLVM can't expand them when
162 // there's a valid register class, so we need custom operations in most cases.
163 setOperationAction(ISD::FABS, MVT::f128, Expand);
164 setOperationAction(ISD::FADD, MVT::f128, Custom);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
166 setOperationAction(ISD::FCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FDIV, MVT::f128, Custom);
168 setOperationAction(ISD::FMA, MVT::f128, Expand);
169 setOperationAction(ISD::FMUL, MVT::f128, Custom);
170 setOperationAction(ISD::FNEG, MVT::f128, Expand);
171 setOperationAction(ISD::FPOW, MVT::f128, Expand);
172 setOperationAction(ISD::FREM, MVT::f128, Expand);
173 setOperationAction(ISD::FRINT, MVT::f128, Expand);
174 setOperationAction(ISD::FSIN, MVT::f128, Expand);
175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
176 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
177 setOperationAction(ISD::FSUB, MVT::f128, Custom);
178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
179 setOperationAction(ISD::SETCC, MVT::f128, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT, MVT::f128, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
185 // Lowering for many of the conversions is actually specified by the non-f128
186 // type. The LowerXXX function will be trivial when f128 isn't involved.
187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
202 // Variable arguments.
203 setOperationAction(ISD::VASTART, MVT::Other, Custom);
204 setOperationAction(ISD::VAARG, MVT::Other, Custom);
205 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
206 setOperationAction(ISD::VAEND, MVT::Other, Expand);
208 // Variable-sized objects.
209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
213 // Exception handling.
214 // FIXME: These are guesses. Has this been defined yet?
215 setExceptionPointerRegister(AArch64::X0);
216 setExceptionSelectorRegister(AArch64::X1);
218 // Constant pool entries
219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
225 setOperationAction(ISD::ADDC, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i32, Custom);
227 setOperationAction(ISD::SUBC, MVT::i32, Custom);
228 setOperationAction(ISD::SUBE, MVT::i32, Custom);
229 setOperationAction(ISD::ADDC, MVT::i64, Custom);
230 setOperationAction(ISD::ADDE, MVT::i64, Custom);
231 setOperationAction(ISD::SUBC, MVT::i64, Custom);
232 setOperationAction(ISD::SUBE, MVT::i64, Custom);
234 // AArch64 lacks both left-rotate and popcount instructions.
235 setOperationAction(ISD::ROTL, MVT::i32, Expand);
236 setOperationAction(ISD::ROTL, MVT::i64, Expand);
238 // AArch64 doesn't have {U|S}MUL_LOHI.
239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
244 // counterparts, which AArch64 supports directly.
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
251 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
256 setOperationAction(ISD::SREM, MVT::i64, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i32, Expand);
260 setOperationAction(ISD::UREM, MVT::i64, Expand);
262 // Custom lower Add/Sub/Mul with overflow.
263 setOperationAction(ISD::SADDO, MVT::i32, Custom);
264 setOperationAction(ISD::SADDO, MVT::i64, Custom);
265 setOperationAction(ISD::UADDO, MVT::i32, Custom);
266 setOperationAction(ISD::UADDO, MVT::i64, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
268 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
269 setOperationAction(ISD::USUBO, MVT::i32, Custom);
270 setOperationAction(ISD::USUBO, MVT::i64, Custom);
271 setOperationAction(ISD::SMULO, MVT::i32, Custom);
272 setOperationAction(ISD::SMULO, MVT::i64, Custom);
273 setOperationAction(ISD::UMULO, MVT::i32, Custom);
274 setOperationAction(ISD::UMULO, MVT::i64, Custom);
276 setOperationAction(ISD::FSIN, MVT::f32, Expand);
277 setOperationAction(ISD::FSIN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FCOS, MVT::f64, Expand);
280 setOperationAction(ISD::FPOW, MVT::f32, Expand);
281 setOperationAction(ISD::FPOW, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285 // f16 is storage-only, so we promote operations to f32 if we know this is
286 // valid, and ignore them otherwise. The operations not mentioned here will
287 // fail to select, but this is not a major problem as no source language
288 // should be emitting native f16 operations yet.
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FDIV, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FSUB, MVT::f16, Promote);
294 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
296 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
297 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
298 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
299 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
301 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
302 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
307 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
309 // Expand all other v4f16 operations.
310 // FIXME: We could generate better code by promoting some operations to
312 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
315 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
316 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
317 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
319 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
321 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
322 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
323 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
324 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
328 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
329 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
330 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
332 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
334 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
337 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
340 // v8f16 is also a storage-only type, so expand it.
341 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
342 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
345 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
346 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
347 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
349 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
351 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
353 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
354 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
355 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
356 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
360 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
361 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
362 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
363 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
365 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
366 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
368 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
371 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
373 // AArch64 has implementations of a lot of rounding-like FP operations.
374 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
375 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
376 MVT Ty = RoundingTypes[I];
377 setOperationAction(ISD::FFLOOR, Ty, Legal);
378 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
379 setOperationAction(ISD::FCEIL, Ty, Legal);
380 setOperationAction(ISD::FRINT, Ty, Legal);
381 setOperationAction(ISD::FTRUNC, Ty, Legal);
382 setOperationAction(ISD::FROUND, Ty, Legal);
385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
387 if (Subtarget->isTargetMachO()) {
388 // For iOS, we don't want to the normal expansion of a libcall to
389 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
391 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
392 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
394 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
395 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
398 // AArch64 does not have floating-point extending loads, i1 sign-extending
399 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
400 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
401 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
402 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
403 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
404 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
405 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
406 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
407 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
408 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
409 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
410 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
411 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
413 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
414 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
416 // Indexed loads and stores are supported.
417 for (unsigned im = (unsigned)ISD::PRE_INC;
418 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
419 setIndexedLoadAction(im, MVT::i8, Legal);
420 setIndexedLoadAction(im, MVT::i16, Legal);
421 setIndexedLoadAction(im, MVT::i32, Legal);
422 setIndexedLoadAction(im, MVT::i64, Legal);
423 setIndexedLoadAction(im, MVT::f64, Legal);
424 setIndexedLoadAction(im, MVT::f32, Legal);
425 setIndexedStoreAction(im, MVT::i8, Legal);
426 setIndexedStoreAction(im, MVT::i16, Legal);
427 setIndexedStoreAction(im, MVT::i32, Legal);
428 setIndexedStoreAction(im, MVT::i64, Legal);
429 setIndexedStoreAction(im, MVT::f64, Legal);
430 setIndexedStoreAction(im, MVT::f32, Legal);
434 setOperationAction(ISD::TRAP, MVT::Other, Legal);
436 // We combine OR nodes for bitfield operations.
437 setTargetDAGCombine(ISD::OR);
439 // Vector add and sub nodes may conceal a high-half opportunity.
440 // Also, try to fold ADD into CSINC/CSINV..
441 setTargetDAGCombine(ISD::ADD);
442 setTargetDAGCombine(ISD::SUB);
444 setTargetDAGCombine(ISD::XOR);
445 setTargetDAGCombine(ISD::SINT_TO_FP);
446 setTargetDAGCombine(ISD::UINT_TO_FP);
448 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
450 setTargetDAGCombine(ISD::ANY_EXTEND);
451 setTargetDAGCombine(ISD::ZERO_EXTEND);
452 setTargetDAGCombine(ISD::SIGN_EXTEND);
453 setTargetDAGCombine(ISD::BITCAST);
454 setTargetDAGCombine(ISD::CONCAT_VECTORS);
455 setTargetDAGCombine(ISD::STORE);
457 setTargetDAGCombine(ISD::MUL);
459 setTargetDAGCombine(ISD::SELECT);
460 setTargetDAGCombine(ISD::VSELECT);
462 setTargetDAGCombine(ISD::INTRINSIC_VOID);
463 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
464 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
466 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
467 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
468 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
470 setStackPointerRegisterToSaveRestore(AArch64::SP);
472 setSchedulingPreference(Sched::Hybrid);
475 MaskAndBranchFoldingIsLegal = true;
477 setMinFunctionAlignment(2);
479 RequireStrictAlign = (Align == StrictAlign);
481 setHasExtractBitsInsn(true);
483 if (Subtarget->hasNEON()) {
484 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
485 // silliness like this:
486 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
487 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
488 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
489 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
490 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
491 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
492 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
493 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
494 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
495 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
496 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
497 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
498 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
499 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
500 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
501 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
502 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
503 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
504 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
505 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
506 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
507 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
508 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
509 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
510 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
512 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
513 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
514 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
515 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
516 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
518 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
521 // elements smaller than i32, so promote the input to i32 first.
522 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
523 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
524 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
525 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
526 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
527 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
528 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
529 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
530 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
532 // AArch64 doesn't have MUL.2d:
533 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
534 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
535 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
536 // Likewise, narrowing and extending vector loads/stores aren't handled
538 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
539 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
541 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
544 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
551 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
552 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
553 setTruncStoreAction((MVT::SimpleValueType)VT,
554 (MVT::SimpleValueType)InnerVT, Expand);
555 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
556 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
557 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
560 // AArch64 has implementations of a lot of rounding-like FP operations.
561 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
562 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
563 MVT Ty = RoundingVecTypes[I];
564 setOperationAction(ISD::FFLOOR, Ty, Legal);
565 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
566 setOperationAction(ISD::FCEIL, Ty, Legal);
567 setOperationAction(ISD::FRINT, Ty, Legal);
568 setOperationAction(ISD::FTRUNC, Ty, Legal);
569 setOperationAction(ISD::FROUND, Ty, Legal);
573 // Prefer likely predicted branches to selects on out-of-order cores.
574 if (Subtarget->isCortexA57())
575 PredictableSelectIsExpensive = true;
578 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
579 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
580 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
581 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
583 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
584 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
585 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
586 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
587 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
589 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
590 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
593 // Mark vector float intrinsics as expand.
594 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
595 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
596 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
597 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
598 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
599 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
600 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
601 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
602 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
603 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
606 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
607 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
608 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
609 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
610 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
611 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
612 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
613 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
614 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
615 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
616 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
617 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
619 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
620 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
621 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
622 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
624 // CNT supports only B element sizes.
625 if (VT != MVT::v8i8 && VT != MVT::v16i8)
626 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
635 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
637 if (Subtarget->isLittleEndian()) {
638 for (unsigned im = (unsigned)ISD::PRE_INC;
639 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
640 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
641 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
646 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
647 addRegisterClass(VT, &AArch64::FPR64RegClass);
648 addTypeForNEON(VT, MVT::v2i32);
651 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
652 addRegisterClass(VT, &AArch64::FPR128RegClass);
653 addTypeForNEON(VT, MVT::v4i32);
656 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
659 return VT.changeVectorElementTypeToInteger();
662 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
663 /// Mask are known to be either zero or one and return them in the
664 /// KnownZero/KnownOne bitsets.
665 void AArch64TargetLowering::computeKnownBitsForTargetNode(
666 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
667 const SelectionDAG &DAG, unsigned Depth) const {
668 switch (Op.getOpcode()) {
671 case AArch64ISD::CSEL: {
672 APInt KnownZero2, KnownOne2;
673 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
674 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
675 KnownZero &= KnownZero2;
676 KnownOne &= KnownOne2;
679 case ISD::INTRINSIC_W_CHAIN: {
680 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
681 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
684 case Intrinsic::aarch64_ldaxr:
685 case Intrinsic::aarch64_ldxr: {
686 unsigned BitWidth = KnownOne.getBitWidth();
687 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
688 unsigned MemBits = VT.getScalarType().getSizeInBits();
689 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
695 case ISD::INTRINSIC_WO_CHAIN:
696 case ISD::INTRINSIC_VOID: {
697 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
701 case Intrinsic::aarch64_neon_umaxv:
702 case Intrinsic::aarch64_neon_uminv: {
703 // Figure out the datatype of the vector operand. The UMINV instruction
704 // will zero extend the result, so we can mark as known zero all the
705 // bits larger than the element datatype. 32-bit or larget doesn't need
706 // this as those are legal types and will be handled by isel directly.
707 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
708 unsigned BitWidth = KnownZero.getBitWidth();
709 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
710 assert(BitWidth >= 8 && "Unexpected width!");
711 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
713 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
714 assert(BitWidth >= 16 && "Unexpected width!");
715 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
725 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
729 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
730 // FIXME: On AArch64, this depends on the type.
731 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
732 // and the offset has to be a multiple of the related size in bytes.
737 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
738 const TargetLibraryInfo *libInfo) const {
739 return AArch64::createFastISel(funcInfo, libInfo);
742 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
746 case AArch64ISD::CALL: return "AArch64ISD::CALL";
747 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
748 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
749 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
750 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
751 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
752 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
753 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
754 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
755 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
756 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
757 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
758 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
759 case AArch64ISD::ADC: return "AArch64ISD::ADC";
760 case AArch64ISD::SBC: return "AArch64ISD::SBC";
761 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
762 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
763 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
764 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
765 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
766 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
767 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
768 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
769 case AArch64ISD::DUP: return "AArch64ISD::DUP";
770 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
771 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
772 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
773 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
774 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
775 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
776 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
777 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
778 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
779 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
780 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
781 case AArch64ISD::BICi: return "AArch64ISD::BICi";
782 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
783 case AArch64ISD::BSL: return "AArch64ISD::BSL";
784 case AArch64ISD::NEG: return "AArch64ISD::NEG";
785 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
786 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
787 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
788 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
789 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
790 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
791 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
792 case AArch64ISD::REV16: return "AArch64ISD::REV16";
793 case AArch64ISD::REV32: return "AArch64ISD::REV32";
794 case AArch64ISD::REV64: return "AArch64ISD::REV64";
795 case AArch64ISD::EXT: return "AArch64ISD::EXT";
796 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
797 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
798 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
799 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
800 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
801 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
802 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
803 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
804 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
805 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
806 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
807 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
808 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
809 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
810 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
811 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
812 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
813 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
814 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
815 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
816 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
817 case AArch64ISD::NOT: return "AArch64ISD::NOT";
818 case AArch64ISD::BIT: return "AArch64ISD::BIT";
819 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
820 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
821 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
822 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
823 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
824 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
825 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
826 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
827 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
828 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
829 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
830 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
831 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
832 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
833 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
834 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
835 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
836 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
837 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
838 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
839 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
840 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
841 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
842 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
843 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
844 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
845 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
846 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
847 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
848 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
849 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
850 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
851 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
852 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
853 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
854 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
859 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
860 MachineBasicBlock *MBB) const {
861 // We materialise the F128CSEL pseudo-instruction as some control flow and a
865 // [... previous instrs leading to comparison ...]
871 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
873 const TargetInstrInfo *TII =
874 getTargetMachine().getSubtargetImpl()->getInstrInfo();
875 MachineFunction *MF = MBB->getParent();
876 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
877 DebugLoc DL = MI->getDebugLoc();
878 MachineFunction::iterator It = MBB;
881 unsigned DestReg = MI->getOperand(0).getReg();
882 unsigned IfTrueReg = MI->getOperand(1).getReg();
883 unsigned IfFalseReg = MI->getOperand(2).getReg();
884 unsigned CondCode = MI->getOperand(3).getImm();
885 bool NZCVKilled = MI->getOperand(4).isKill();
887 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
888 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
889 MF->insert(It, TrueBB);
890 MF->insert(It, EndBB);
892 // Transfer rest of current basic-block to EndBB
893 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
895 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
897 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
898 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
899 MBB->addSuccessor(TrueBB);
900 MBB->addSuccessor(EndBB);
902 // TrueBB falls through to the end.
903 TrueBB->addSuccessor(EndBB);
906 TrueBB->addLiveIn(AArch64::NZCV);
907 EndBB->addLiveIn(AArch64::NZCV);
910 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
916 MI->eraseFromParent();
921 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
922 MachineBasicBlock *BB) const {
923 switch (MI->getOpcode()) {
928 llvm_unreachable("Unexpected instruction for custom inserter!");
930 case AArch64::F128CSEL:
931 return EmitF128CSEL(MI, BB);
933 case TargetOpcode::STACKMAP:
934 case TargetOpcode::PATCHPOINT:
935 return emitPatchPoint(MI, BB);
939 //===----------------------------------------------------------------------===//
940 // AArch64 Lowering private implementation.
941 //===----------------------------------------------------------------------===//
943 //===----------------------------------------------------------------------===//
945 //===----------------------------------------------------------------------===//
947 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
949 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
952 llvm_unreachable("Unknown condition code!");
954 return AArch64CC::NE;
956 return AArch64CC::EQ;
958 return AArch64CC::GT;
960 return AArch64CC::GE;
962 return AArch64CC::LT;
964 return AArch64CC::LE;
966 return AArch64CC::HI;
968 return AArch64CC::HS;
970 return AArch64CC::LO;
972 return AArch64CC::LS;
976 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
977 static void changeFPCCToAArch64CC(ISD::CondCode CC,
978 AArch64CC::CondCode &CondCode,
979 AArch64CC::CondCode &CondCode2) {
980 CondCode2 = AArch64CC::AL;
983 llvm_unreachable("Unknown FP condition!");
986 CondCode = AArch64CC::EQ;
990 CondCode = AArch64CC::GT;
994 CondCode = AArch64CC::GE;
997 CondCode = AArch64CC::MI;
1000 CondCode = AArch64CC::LS;
1003 CondCode = AArch64CC::MI;
1004 CondCode2 = AArch64CC::GT;
1007 CondCode = AArch64CC::VC;
1010 CondCode = AArch64CC::VS;
1013 CondCode = AArch64CC::EQ;
1014 CondCode2 = AArch64CC::VS;
1017 CondCode = AArch64CC::HI;
1020 CondCode = AArch64CC::PL;
1024 CondCode = AArch64CC::LT;
1028 CondCode = AArch64CC::LE;
1032 CondCode = AArch64CC::NE;
1037 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1038 /// CC usable with the vector instructions. Fewer operations are available
1039 /// without a real NZCV register, so we have to use less efficient combinations
1040 /// to get the same effect.
1041 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1042 AArch64CC::CondCode &CondCode,
1043 AArch64CC::CondCode &CondCode2,
1048 // Mostly the scalar mappings work fine.
1049 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1052 Invert = true; // Fallthrough
1054 CondCode = AArch64CC::MI;
1055 CondCode2 = AArch64CC::GE;
1062 // All of the compare-mask comparisons are ordered, but we can switch
1063 // between the two by a double inversion. E.g. ULE == !OGT.
1065 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1070 static bool isLegalArithImmed(uint64_t C) {
1071 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1072 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1075 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1076 SDLoc dl, SelectionDAG &DAG) {
1077 EVT VT = LHS.getValueType();
1079 if (VT.isFloatingPoint())
1080 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1082 // The CMP instruction is just an alias for SUBS, and representing it as
1083 // SUBS means that it's possible to get CSE with subtract operations.
1084 // A later phase can perform the optimization of setting the destination
1085 // register to WZR/XZR if it ends up being unused.
1086 unsigned Opcode = AArch64ISD::SUBS;
1088 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1089 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1090 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1091 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1092 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1093 // can be set differently by this operation. It comes down to whether
1094 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1095 // everything is fine. If not then the optimization is wrong. Thus general
1096 // comparisons are only valid if op2 != 0.
1098 // So, finally, the only LLVM-native comparisons that don't mention C and V
1099 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1100 // the absence of information about op2.
1101 Opcode = AArch64ISD::ADDS;
1102 RHS = RHS.getOperand(1);
1103 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1104 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1105 !isUnsignedIntSetCC(CC)) {
1106 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1107 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1108 // of the signed comparisons.
1109 Opcode = AArch64ISD::ANDS;
1110 RHS = LHS.getOperand(1);
1111 LHS = LHS.getOperand(0);
1114 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1118 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1119 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1121 AArch64CC::CondCode AArch64CC;
1122 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1123 EVT VT = RHS.getValueType();
1124 uint64_t C = RHSC->getZExtValue();
1125 if (!isLegalArithImmed(C)) {
1126 // Constant does not fit, try adjusting it by one?
1132 if ((VT == MVT::i32 && C != 0x80000000 &&
1133 isLegalArithImmed((uint32_t)(C - 1))) ||
1134 (VT == MVT::i64 && C != 0x80000000ULL &&
1135 isLegalArithImmed(C - 1ULL))) {
1136 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1137 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1138 RHS = DAG.getConstant(C, VT);
1143 if ((VT == MVT::i32 && C != 0 &&
1144 isLegalArithImmed((uint32_t)(C - 1))) ||
1145 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1146 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1147 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1148 RHS = DAG.getConstant(C, VT);
1153 if ((VT == MVT::i32 && C != 0x7fffffff &&
1154 isLegalArithImmed((uint32_t)(C + 1))) ||
1155 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1156 isLegalArithImmed(C + 1ULL))) {
1157 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1158 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1159 RHS = DAG.getConstant(C, VT);
1164 if ((VT == MVT::i32 && C != 0xffffffff &&
1165 isLegalArithImmed((uint32_t)(C + 1))) ||
1166 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1167 isLegalArithImmed(C + 1ULL))) {
1168 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1169 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1170 RHS = DAG.getConstant(C, VT);
1176 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1177 // For the i8 operand, the largest immediate is 255, so this can be easily
1178 // encoded in the compare instruction. For the i16 operand, however, the
1179 // largest immediate cannot be encoded in the compare.
1180 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1181 // constant. For example,
1183 // ldrh w0, [x0, #0]
1186 // ldrsh w0, [x0, #0]
1188 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1189 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1190 // both the LHS and RHS are truely zero extended and to make sure the
1191 // transformation is profitable.
1192 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1193 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1194 isa<LoadSDNode>(LHS)) {
1195 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1196 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1197 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1198 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1199 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1201 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1202 DAG.getValueType(MVT::i16));
1203 Cmp = emitComparison(SExt,
1204 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1206 AArch64CC = changeIntCCToAArch64CC(CC);
1207 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1213 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1214 AArch64CC = changeIntCCToAArch64CC(CC);
1215 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1219 static std::pair<SDValue, SDValue>
1220 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1221 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1222 "Unsupported value type");
1223 SDValue Value, Overflow;
1225 SDValue LHS = Op.getOperand(0);
1226 SDValue RHS = Op.getOperand(1);
1228 switch (Op.getOpcode()) {
1230 llvm_unreachable("Unknown overflow instruction!");
1232 Opc = AArch64ISD::ADDS;
1236 Opc = AArch64ISD::ADDS;
1240 Opc = AArch64ISD::SUBS;
1244 Opc = AArch64ISD::SUBS;
1247 // Multiply needs a little bit extra work.
1251 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1252 if (Op.getValueType() == MVT::i32) {
1253 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1254 // For a 32 bit multiply with overflow check we want the instruction
1255 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1256 // need to generate the following pattern:
1257 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1258 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1259 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1260 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1261 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1262 DAG.getConstant(0, MVT::i64));
1263 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1264 // operation. We need to clear out the upper 32 bits, because we used a
1265 // widening multiply that wrote all 64 bits. In the end this should be a
1267 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1269 // The signed overflow check requires more than just a simple check for
1270 // any bit set in the upper 32 bits of the result. These bits could be
1271 // just the sign bits of a negative number. To perform the overflow
1272 // check we have to arithmetic shift right the 32nd bit of the result by
1273 // 31 bits. Then we compare the result to the upper 32 bits.
1274 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1275 DAG.getConstant(32, MVT::i64));
1276 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1277 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1278 DAG.getConstant(31, MVT::i64));
1279 // It is important that LowerBits is last, otherwise the arithmetic
1280 // shift will not be folded into the compare (SUBS).
1281 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1282 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1285 // The overflow check for unsigned multiply is easy. We only need to
1286 // check if any of the upper 32 bits are set. This can be done with a
1287 // CMP (shifted register). For that we need to generate the following
1289 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1290 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1291 DAG.getConstant(32, MVT::i64));
1292 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1294 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1295 UpperBits).getValue(1);
1299 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1300 // For the 64 bit multiply
1301 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1303 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1304 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1305 DAG.getConstant(63, MVT::i64));
1306 // It is important that LowerBits is last, otherwise the arithmetic
1307 // shift will not be folded into the compare (SUBS).
1308 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1309 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1312 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1313 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1315 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1316 UpperBits).getValue(1);
1323 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1325 // Emit the AArch64 operation with overflow check.
1326 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1327 Overflow = Value.getValue(1);
1329 return std::make_pair(Value, Overflow);
1332 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1333 RTLIB::Libcall Call) const {
1334 SmallVector<SDValue, 2> Ops;
1335 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1336 Ops.push_back(Op.getOperand(i));
1338 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1342 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1343 SDValue Sel = Op.getOperand(0);
1344 SDValue Other = Op.getOperand(1);
1346 // If neither operand is a SELECT_CC, give up.
1347 if (Sel.getOpcode() != ISD::SELECT_CC)
1348 std::swap(Sel, Other);
1349 if (Sel.getOpcode() != ISD::SELECT_CC)
1352 // The folding we want to perform is:
1353 // (xor x, (select_cc a, b, cc, 0, -1) )
1355 // (csel x, (xor x, -1), cc ...)
1357 // The latter will get matched to a CSINV instruction.
1359 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1360 SDValue LHS = Sel.getOperand(0);
1361 SDValue RHS = Sel.getOperand(1);
1362 SDValue TVal = Sel.getOperand(2);
1363 SDValue FVal = Sel.getOperand(3);
1366 // FIXME: This could be generalized to non-integer comparisons.
1367 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1370 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1371 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1373 // The the values aren't constants, this isn't the pattern we're looking for.
1374 if (!CFVal || !CTVal)
1377 // We can commute the SELECT_CC by inverting the condition. This
1378 // might be needed to make this fit into a CSINV pattern.
1379 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1380 std::swap(TVal, FVal);
1381 std::swap(CTVal, CFVal);
1382 CC = ISD::getSetCCInverse(CC, true);
1385 // If the constants line up, perform the transform!
1386 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1388 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1391 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1392 DAG.getConstant(-1ULL, Other.getValueType()));
1394 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1401 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1402 EVT VT = Op.getValueType();
1404 // Let legalize expand this if it isn't a legal type yet.
1405 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1408 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1411 bool ExtraOp = false;
1412 switch (Op.getOpcode()) {
1414 llvm_unreachable("Invalid code");
1416 Opc = AArch64ISD::ADDS;
1419 Opc = AArch64ISD::SUBS;
1422 Opc = AArch64ISD::ADCS;
1426 Opc = AArch64ISD::SBCS;
1432 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1433 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1437 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1438 // Let legalize expand this if it isn't a legal type yet.
1439 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1442 AArch64CC::CondCode CC;
1443 // The actual operation that sets the overflow or carry flag.
1444 SDValue Value, Overflow;
1445 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1447 // We use 0 and 1 as false and true values.
1448 SDValue TVal = DAG.getConstant(1, MVT::i32);
1449 SDValue FVal = DAG.getConstant(0, MVT::i32);
1451 // We use an inverted condition, because the conditional select is inverted
1452 // too. This will allow it to be selected to a single instruction:
1453 // CSINC Wd, WZR, WZR, invert(cond).
1454 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1455 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1458 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1459 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1462 // Prefetch operands are:
1463 // 1: Address to prefetch
1465 // 3: int locality (0 = no locality ... 3 = extreme locality)
1466 // 4: bool isDataCache
1467 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1469 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1470 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1471 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1473 bool IsStream = !Locality;
1474 // When the locality number is set
1476 // The front-end should have filtered out the out-of-range values
1477 assert(Locality <= 3 && "Prefetch locality out-of-range");
1478 // The locality degree is the opposite of the cache speed.
1479 // Put the number the other way around.
1480 // The encoding starts at 0 for level 1
1481 Locality = 3 - Locality;
1484 // built the mask value encoding the expected behavior.
1485 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1486 (!IsData << 3) | // IsDataCache bit
1487 (Locality << 1) | // Cache level bits
1488 (unsigned)IsStream; // Stream bit
1489 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1490 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1493 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1494 SelectionDAG &DAG) const {
1495 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1498 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1500 return LowerF128Call(Op, DAG, LC);
1503 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1504 SelectionDAG &DAG) const {
1505 if (Op.getOperand(0).getValueType() != MVT::f128) {
1506 // It's legal except when f128 is involved
1511 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1513 // FP_ROUND node has a second operand indicating whether it is known to be
1514 // precise. That doesn't take part in the LibCall so we can't directly use
1516 SDValue SrcVal = Op.getOperand(0);
1517 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1518 /*isSigned*/ false, SDLoc(Op)).first;
1521 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1522 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1523 // Any additional optimization in this function should be recorded
1524 // in the cost tables.
1525 EVT InVT = Op.getOperand(0).getValueType();
1526 EVT VT = Op.getValueType();
1528 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1531 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1533 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1536 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1539 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1540 VT.getVectorNumElements());
1541 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1542 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1545 // Type changing conversions are illegal.
1549 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1550 SelectionDAG &DAG) const {
1551 if (Op.getOperand(0).getValueType().isVector())
1552 return LowerVectorFP_TO_INT(Op, DAG);
1554 if (Op.getOperand(0).getValueType() != MVT::f128) {
1555 // It's legal except when f128 is involved
1560 if (Op.getOpcode() == ISD::FP_TO_SINT)
1561 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1563 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1565 SmallVector<SDValue, 2> Ops;
1566 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1567 Ops.push_back(Op.getOperand(i));
1569 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1573 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1574 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1575 // Any additional optimization in this function should be recorded
1576 // in the cost tables.
1577 EVT VT = Op.getValueType();
1579 SDValue In = Op.getOperand(0);
1580 EVT InVT = In.getValueType();
1582 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1584 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1585 InVT.getVectorNumElements());
1586 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1587 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1590 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1592 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1593 EVT CastVT = VT.changeVectorElementTypeToInteger();
1594 In = DAG.getNode(CastOpc, dl, CastVT, In);
1595 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1601 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1602 SelectionDAG &DAG) const {
1603 if (Op.getValueType().isVector())
1604 return LowerVectorINT_TO_FP(Op, DAG);
1606 // i128 conversions are libcalls.
1607 if (Op.getOperand(0).getValueType() == MVT::i128)
1610 // Other conversions are legal, unless it's to the completely software-based
1612 if (Op.getValueType() != MVT::f128)
1616 if (Op.getOpcode() == ISD::SINT_TO_FP)
1617 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1619 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1621 return LowerF128Call(Op, DAG, LC);
1624 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1625 SelectionDAG &DAG) const {
1626 // For iOS, we want to call an alternative entry point: __sincos_stret,
1627 // which returns the values in two S / D registers.
1629 SDValue Arg = Op.getOperand(0);
1630 EVT ArgVT = Arg.getValueType();
1631 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1638 Entry.isSExt = false;
1639 Entry.isZExt = false;
1640 Args.push_back(Entry);
1642 const char *LibcallName =
1643 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1644 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1646 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1647 TargetLowering::CallLoweringInfo CLI(DAG);
1648 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1649 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1651 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1652 return CallResult.first;
1655 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1656 if (Op.getValueType() != MVT::f16)
1659 assert(Op.getOperand(0).getValueType() == MVT::i16);
1662 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1663 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1665 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1666 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1671 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1672 SelectionDAG &DAG) const {
1673 switch (Op.getOpcode()) {
1675 llvm_unreachable("unimplemented operand");
1678 return LowerBITCAST(Op, DAG);
1679 case ISD::GlobalAddress:
1680 return LowerGlobalAddress(Op, DAG);
1681 case ISD::GlobalTLSAddress:
1682 return LowerGlobalTLSAddress(Op, DAG);
1684 return LowerSETCC(Op, DAG);
1686 return LowerBR_CC(Op, DAG);
1688 return LowerSELECT(Op, DAG);
1689 case ISD::SELECT_CC:
1690 return LowerSELECT_CC(Op, DAG);
1691 case ISD::JumpTable:
1692 return LowerJumpTable(Op, DAG);
1693 case ISD::ConstantPool:
1694 return LowerConstantPool(Op, DAG);
1695 case ISD::BlockAddress:
1696 return LowerBlockAddress(Op, DAG);
1698 return LowerVASTART(Op, DAG);
1700 return LowerVACOPY(Op, DAG);
1702 return LowerVAARG(Op, DAG);
1707 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1714 return LowerXALUO(Op, DAG);
1716 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1718 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1720 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1722 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1724 return LowerFP_ROUND(Op, DAG);
1725 case ISD::FP_EXTEND:
1726 return LowerFP_EXTEND(Op, DAG);
1727 case ISD::FRAMEADDR:
1728 return LowerFRAMEADDR(Op, DAG);
1729 case ISD::RETURNADDR:
1730 return LowerRETURNADDR(Op, DAG);
1731 case ISD::INSERT_VECTOR_ELT:
1732 return LowerINSERT_VECTOR_ELT(Op, DAG);
1733 case ISD::EXTRACT_VECTOR_ELT:
1734 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1735 case ISD::BUILD_VECTOR:
1736 return LowerBUILD_VECTOR(Op, DAG);
1737 case ISD::VECTOR_SHUFFLE:
1738 return LowerVECTOR_SHUFFLE(Op, DAG);
1739 case ISD::EXTRACT_SUBVECTOR:
1740 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1744 return LowerVectorSRA_SRL_SHL(Op, DAG);
1745 case ISD::SHL_PARTS:
1746 return LowerShiftLeftParts(Op, DAG);
1747 case ISD::SRL_PARTS:
1748 case ISD::SRA_PARTS:
1749 return LowerShiftRightParts(Op, DAG);
1751 return LowerCTPOP(Op, DAG);
1752 case ISD::FCOPYSIGN:
1753 return LowerFCOPYSIGN(Op, DAG);
1755 return LowerVectorAND(Op, DAG);
1757 return LowerVectorOR(Op, DAG);
1759 return LowerXOR(Op, DAG);
1761 return LowerPREFETCH(Op, DAG);
1762 case ISD::SINT_TO_FP:
1763 case ISD::UINT_TO_FP:
1764 return LowerINT_TO_FP(Op, DAG);
1765 case ISD::FP_TO_SINT:
1766 case ISD::FP_TO_UINT:
1767 return LowerFP_TO_INT(Op, DAG);
1769 return LowerFSINCOS(Op, DAG);
1773 /// getFunctionAlignment - Return the Log2 alignment of this function.
1774 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1778 //===----------------------------------------------------------------------===//
1779 // Calling Convention Implementation
1780 //===----------------------------------------------------------------------===//
1782 #include "AArch64GenCallingConv.inc"
1784 /// Selects the correct CCAssignFn for a given CallingConvention value.
1785 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1786 bool IsVarArg) const {
1789 llvm_unreachable("Unsupported calling convention.");
1790 case CallingConv::WebKit_JS:
1791 return CC_AArch64_WebKit_JS;
1792 case CallingConv::C:
1793 case CallingConv::Fast:
1794 if (!Subtarget->isTargetDarwin())
1795 return CC_AArch64_AAPCS;
1796 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1800 SDValue AArch64TargetLowering::LowerFormalArguments(
1801 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1802 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1803 SmallVectorImpl<SDValue> &InVals) const {
1804 MachineFunction &MF = DAG.getMachineFunction();
1805 MachineFrameInfo *MFI = MF.getFrameInfo();
1807 // Assign locations to all of the incoming arguments.
1808 SmallVector<CCValAssign, 16> ArgLocs;
1809 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1812 // At this point, Ins[].VT may already be promoted to i32. To correctly
1813 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1814 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1815 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1816 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1818 unsigned NumArgs = Ins.size();
1819 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1820 unsigned CurArgIdx = 0;
1821 for (unsigned i = 0; i != NumArgs; ++i) {
1822 MVT ValVT = Ins[i].VT;
1823 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1824 CurArgIdx = Ins[i].OrigArgIndex;
1826 // Get type of the original argument.
1827 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1828 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1829 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1830 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1832 else if (ActualMVT == MVT::i16)
1835 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1837 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1838 assert(!Res && "Call operand has unhandled type");
1841 assert(ArgLocs.size() == Ins.size());
1842 SmallVector<SDValue, 16> ArgValues;
1843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1844 CCValAssign &VA = ArgLocs[i];
1846 if (Ins[i].Flags.isByVal()) {
1847 // Byval is used for HFAs in the PCS, but the system should work in a
1848 // non-compliant manner for larger structs.
1849 EVT PtrTy = getPointerTy();
1850 int Size = Ins[i].Flags.getByValSize();
1851 unsigned NumRegs = (Size + 7) / 8;
1853 // FIXME: This works on big-endian for composite byvals, which are the common
1854 // case. It should also work for fundamental types too.
1856 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1857 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1858 InVals.push_back(FrameIdxN);
1863 if (VA.isRegLoc()) {
1864 // Arguments stored in registers.
1865 EVT RegVT = VA.getLocVT();
1868 const TargetRegisterClass *RC;
1870 if (RegVT == MVT::i32)
1871 RC = &AArch64::GPR32RegClass;
1872 else if (RegVT == MVT::i64)
1873 RC = &AArch64::GPR64RegClass;
1874 else if (RegVT == MVT::f16)
1875 RC = &AArch64::FPR16RegClass;
1876 else if (RegVT == MVT::f32)
1877 RC = &AArch64::FPR32RegClass;
1878 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1879 RC = &AArch64::FPR64RegClass;
1880 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1881 RC = &AArch64::FPR128RegClass;
1883 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1885 // Transform the arguments in physical registers into virtual ones.
1886 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1887 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1889 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1890 // to 64 bits. Insert an assert[sz]ext to capture this, then
1891 // truncate to the right size.
1892 switch (VA.getLocInfo()) {
1894 llvm_unreachable("Unknown loc info!");
1895 case CCValAssign::Full:
1897 case CCValAssign::BCvt:
1898 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1900 case CCValAssign::AExt:
1901 case CCValAssign::SExt:
1902 case CCValAssign::ZExt:
1903 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1904 // nodes after our lowering.
1905 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1909 InVals.push_back(ArgValue);
1911 } else { // VA.isRegLoc()
1912 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1913 unsigned ArgOffset = VA.getLocMemOffset();
1914 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
1916 uint32_t BEAlign = 0;
1917 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1918 BEAlign = 8 - ArgSize;
1920 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1922 // Create load nodes to retrieve arguments from the stack.
1923 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1926 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1927 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1928 MVT MemVT = VA.getValVT();
1930 switch (VA.getLocInfo()) {
1933 case CCValAssign::BCvt:
1934 MemVT = VA.getLocVT();
1936 case CCValAssign::SExt:
1937 ExtType = ISD::SEXTLOAD;
1939 case CCValAssign::ZExt:
1940 ExtType = ISD::ZEXTLOAD;
1942 case CCValAssign::AExt:
1943 ExtType = ISD::EXTLOAD;
1947 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1948 MachinePointerInfo::getFixedStack(FI),
1949 MemVT, false, false, false, 0, nullptr);
1951 InVals.push_back(ArgValue);
1957 if (!Subtarget->isTargetDarwin()) {
1958 // The AAPCS variadic function ABI is identical to the non-variadic
1959 // one. As a result there may be more arguments in registers and we should
1960 // save them for future reference.
1961 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1964 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1965 // This will point to the next argument passed via stack.
1966 unsigned StackOffset = CCInfo.getNextStackOffset();
1967 // We currently pass all varargs at 8-byte alignment.
1968 StackOffset = ((StackOffset + 7) & ~7);
1969 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1972 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1973 unsigned StackArgSize = CCInfo.getNextStackOffset();
1974 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1975 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1976 // This is a non-standard ABI so by fiat I say we're allowed to make full
1977 // use of the stack area to be popped, which must be aligned to 16 bytes in
1979 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1981 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1982 // a multiple of 16.
1983 FuncInfo->setArgumentStackToRestore(StackArgSize);
1985 // This realignment carries over to the available bytes below. Our own
1986 // callers will guarantee the space is free by giving an aligned value to
1989 // Even if we're not expected to free up the space, it's useful to know how
1990 // much is there while considering tail calls (because we can reuse it).
1991 FuncInfo->setBytesInStackArgArea(StackArgSize);
1996 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1997 SelectionDAG &DAG, SDLoc DL,
1998 SDValue &Chain) const {
1999 MachineFunction &MF = DAG.getMachineFunction();
2000 MachineFrameInfo *MFI = MF.getFrameInfo();
2001 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2003 SmallVector<SDValue, 8> MemOps;
2005 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2006 AArch64::X3, AArch64::X4, AArch64::X5,
2007 AArch64::X6, AArch64::X7 };
2008 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2009 unsigned FirstVariadicGPR =
2010 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
2012 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2014 if (GPRSaveSize != 0) {
2015 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2017 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2019 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2020 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2021 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2023 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2024 MachinePointerInfo::getStack(i * 8), false, false, 0);
2025 MemOps.push_back(Store);
2026 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2027 DAG.getConstant(8, getPointerTy()));
2030 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2031 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2033 if (Subtarget->hasFPARMv8()) {
2034 static const MCPhysReg FPRArgRegs[] = {
2035 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2036 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2037 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2038 unsigned FirstVariadicFPR =
2039 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
2041 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2043 if (FPRSaveSize != 0) {
2044 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2046 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2048 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2049 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2050 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2053 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2054 MachinePointerInfo::getStack(i * 16), false, false, 0);
2055 MemOps.push_back(Store);
2056 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2057 DAG.getConstant(16, getPointerTy()));
2060 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2061 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2064 if (!MemOps.empty()) {
2065 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2069 /// LowerCallResult - Lower the result values of a call into the
2070 /// appropriate copies out of appropriate physical registers.
2071 SDValue AArch64TargetLowering::LowerCallResult(
2072 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2073 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2074 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2075 SDValue ThisVal) const {
2076 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2077 ? RetCC_AArch64_WebKit_JS
2078 : RetCC_AArch64_AAPCS;
2079 // Assign locations to each value returned by this call.
2080 SmallVector<CCValAssign, 16> RVLocs;
2081 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2083 CCInfo.AnalyzeCallResult(Ins, RetCC);
2085 // Copy all of the result registers out of their specified physreg.
2086 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2087 CCValAssign VA = RVLocs[i];
2089 // Pass 'this' value directly from the argument to return value, to avoid
2090 // reg unit interference
2091 if (i == 0 && isThisReturn) {
2092 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2093 "unexpected return calling convention register assignment");
2094 InVals.push_back(ThisVal);
2099 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2100 Chain = Val.getValue(1);
2101 InFlag = Val.getValue(2);
2103 switch (VA.getLocInfo()) {
2105 llvm_unreachable("Unknown loc info!");
2106 case CCValAssign::Full:
2108 case CCValAssign::BCvt:
2109 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2113 InVals.push_back(Val);
2119 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2120 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2121 bool isCalleeStructRet, bool isCallerStructRet,
2122 const SmallVectorImpl<ISD::OutputArg> &Outs,
2123 const SmallVectorImpl<SDValue> &OutVals,
2124 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2125 // For CallingConv::C this function knows whether the ABI needs
2126 // changing. That's not true for other conventions so they will have to opt in
2128 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2131 const MachineFunction &MF = DAG.getMachineFunction();
2132 const Function *CallerF = MF.getFunction();
2133 CallingConv::ID CallerCC = CallerF->getCallingConv();
2134 bool CCMatch = CallerCC == CalleeCC;
2136 // Byval parameters hand the function a pointer directly into the stack area
2137 // we want to reuse during a tail call. Working around this *is* possible (see
2138 // X86) but less efficient and uglier in LowerCall.
2139 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2140 e = CallerF->arg_end();
2142 if (i->hasByValAttr())
2145 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2146 if (IsTailCallConvention(CalleeCC) && CCMatch)
2151 // Externally-defined functions with weak linkage should not be
2152 // tail-called on AArch64 when the OS does not support dynamic
2153 // pre-emption of symbols, as the AAELF spec requires normal calls
2154 // to undefined weak functions to be replaced with a NOP or jump to the
2155 // next instruction. The behaviour of branch instructions in this
2156 // situation (as used for tail calls) is implementation-defined, so we
2157 // cannot rely on the linker replacing the tail call with a return.
2158 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2159 const GlobalValue *GV = G->getGlobal();
2160 if (GV->hasExternalWeakLinkage())
2164 // Now we search for cases where we can use a tail call without changing the
2165 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2168 // I want anyone implementing a new calling convention to think long and hard
2169 // about this assert.
2170 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2171 "Unexpected variadic calling convention");
2173 if (isVarArg && !Outs.empty()) {
2174 // At least two cases here: if caller is fastcc then we can't have any
2175 // memory arguments (we'd be expected to clean up the stack afterwards). If
2176 // caller is C then we could potentially use its argument area.
2178 // FIXME: for now we take the most conservative of these in both cases:
2179 // disallow all variadic memory operands.
2180 SmallVector<CCValAssign, 16> ArgLocs;
2181 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2184 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2185 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2186 if (!ArgLocs[i].isRegLoc())
2190 // If the calling conventions do not match, then we'd better make sure the
2191 // results are returned in the same way as what the caller expects.
2193 SmallVector<CCValAssign, 16> RVLocs1;
2194 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2196 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2198 SmallVector<CCValAssign, 16> RVLocs2;
2199 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2201 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2203 if (RVLocs1.size() != RVLocs2.size())
2205 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2206 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2208 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2210 if (RVLocs1[i].isRegLoc()) {
2211 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2214 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2220 // Nothing more to check if the callee is taking no arguments
2224 SmallVector<CCValAssign, 16> ArgLocs;
2225 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2228 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2230 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2232 // If the stack arguments for this call would fit into our own save area then
2233 // the call can be made tail.
2234 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2237 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2239 MachineFrameInfo *MFI,
2240 int ClobberedFI) const {
2241 SmallVector<SDValue, 8> ArgChains;
2242 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2243 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2245 // Include the original chain at the beginning of the list. When this is
2246 // used by target LowerCall hooks, this helps legalize find the
2247 // CALLSEQ_BEGIN node.
2248 ArgChains.push_back(Chain);
2250 // Add a chain value for each stack argument corresponding
2251 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2252 UE = DAG.getEntryNode().getNode()->use_end();
2254 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2255 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2256 if (FI->getIndex() < 0) {
2257 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2258 int64_t InLastByte = InFirstByte;
2259 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2261 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2262 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2263 ArgChains.push_back(SDValue(L, 1));
2266 // Build a tokenfactor for all the chains.
2267 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2270 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2271 bool TailCallOpt) const {
2272 return CallCC == CallingConv::Fast && TailCallOpt;
2275 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2276 return CallCC == CallingConv::Fast;
2279 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2280 /// and add input and output parameter nodes.
2282 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2283 SmallVectorImpl<SDValue> &InVals) const {
2284 SelectionDAG &DAG = CLI.DAG;
2286 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2287 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2288 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2289 SDValue Chain = CLI.Chain;
2290 SDValue Callee = CLI.Callee;
2291 bool &IsTailCall = CLI.IsTailCall;
2292 CallingConv::ID CallConv = CLI.CallConv;
2293 bool IsVarArg = CLI.IsVarArg;
2295 MachineFunction &MF = DAG.getMachineFunction();
2296 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2297 bool IsThisReturn = false;
2299 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2300 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2301 bool IsSibCall = false;
2304 // Check if it's really possible to do a tail call.
2305 IsTailCall = isEligibleForTailCallOptimization(
2306 Callee, CallConv, IsVarArg, IsStructRet,
2307 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2308 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2309 report_fatal_error("failed to perform tail call elimination on a call "
2310 "site marked musttail");
2312 // A sibling call is one where we're under the usual C ABI and not planning
2313 // to change that but can still do a tail call:
2314 if (!TailCallOpt && IsTailCall)
2321 // Analyze operands of the call, assigning locations to each operand.
2322 SmallVector<CCValAssign, 16> ArgLocs;
2323 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2327 // Handle fixed and variable vector arguments differently.
2328 // Variable vector arguments always go into memory.
2329 unsigned NumArgs = Outs.size();
2331 for (unsigned i = 0; i != NumArgs; ++i) {
2332 MVT ArgVT = Outs[i].VT;
2333 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2334 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2335 /*IsVarArg=*/ !Outs[i].IsFixed);
2336 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2337 assert(!Res && "Call operand has unhandled type");
2341 // At this point, Outs[].VT may already be promoted to i32. To correctly
2342 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2343 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2344 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2345 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2347 unsigned NumArgs = Outs.size();
2348 for (unsigned i = 0; i != NumArgs; ++i) {
2349 MVT ValVT = Outs[i].VT;
2350 // Get type of the original argument.
2351 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2352 /*AllowUnknown*/ true);
2353 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2354 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2355 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2356 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2358 else if (ActualMVT == MVT::i16)
2361 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2362 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2363 assert(!Res && "Call operand has unhandled type");
2368 // Get a count of how many bytes are to be pushed on the stack.
2369 unsigned NumBytes = CCInfo.getNextStackOffset();
2372 // Since we're not changing the ABI to make this a tail call, the memory
2373 // operands are already available in the caller's incoming argument space.
2377 // FPDiff is the byte offset of the call's argument area from the callee's.
2378 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2379 // by this amount for a tail call. In a sibling call it must be 0 because the
2380 // caller will deallocate the entire stack and the callee still expects its
2381 // arguments to begin at SP+0. Completely unused for non-tail calls.
2384 if (IsTailCall && !IsSibCall) {
2385 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2387 // Since callee will pop argument stack as a tail call, we must keep the
2388 // popped size 16-byte aligned.
2389 NumBytes = RoundUpToAlignment(NumBytes, 16);
2391 // FPDiff will be negative if this tail call requires more space than we
2392 // would automatically have in our incoming argument space. Positive if we
2393 // can actually shrink the stack.
2394 FPDiff = NumReusableBytes - NumBytes;
2396 // The stack pointer must be 16-byte aligned at all times it's used for a
2397 // memory operation, which in practice means at *all* times and in
2398 // particular across call boundaries. Therefore our own arguments started at
2399 // a 16-byte aligned SP and the delta applied for the tail call should
2400 // satisfy the same constraint.
2401 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2404 // Adjust the stack pointer for the new arguments...
2405 // These operations are automatically eliminated by the prolog/epilog pass
2408 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2410 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2412 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2413 SmallVector<SDValue, 8> MemOpChains;
2415 // Walk the register/memloc assignments, inserting copies/loads.
2416 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2417 ++i, ++realArgIdx) {
2418 CCValAssign &VA = ArgLocs[i];
2419 SDValue Arg = OutVals[realArgIdx];
2420 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2422 // Promote the value if needed.
2423 switch (VA.getLocInfo()) {
2425 llvm_unreachable("Unknown loc info!");
2426 case CCValAssign::Full:
2428 case CCValAssign::SExt:
2429 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2431 case CCValAssign::ZExt:
2432 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2434 case CCValAssign::AExt:
2435 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2436 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2437 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2438 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2440 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2442 case CCValAssign::BCvt:
2443 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2445 case CCValAssign::FPExt:
2446 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2450 if (VA.isRegLoc()) {
2451 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2452 assert(VA.getLocVT() == MVT::i64 &&
2453 "unexpected calling convention register assignment");
2454 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2455 "unexpected use of 'returned'");
2456 IsThisReturn = true;
2458 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2460 assert(VA.isMemLoc());
2463 MachinePointerInfo DstInfo;
2465 // FIXME: This works on big-endian for composite byvals, which are the
2466 // common case. It should also work for fundamental types too.
2467 uint32_t BEAlign = 0;
2468 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2469 : VA.getValVT().getSizeInBits();
2470 OpSize = (OpSize + 7) / 8;
2471 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2473 BEAlign = 8 - OpSize;
2475 unsigned LocMemOffset = VA.getLocMemOffset();
2476 int32_t Offset = LocMemOffset + BEAlign;
2477 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2478 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2481 Offset = Offset + FPDiff;
2482 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2484 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2485 DstInfo = MachinePointerInfo::getFixedStack(FI);
2487 // Make sure any stack arguments overlapping with where we're storing
2488 // are loaded before this eventual operation. Otherwise they'll be
2490 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2492 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2494 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2495 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2498 if (Outs[i].Flags.isByVal()) {
2500 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2501 SDValue Cpy = DAG.getMemcpy(
2502 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2504 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2506 MemOpChains.push_back(Cpy);
2508 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2509 // promoted to a legal register type i32, we should truncate Arg back to
2511 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2512 VA.getValVT() == MVT::i16)
2513 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2516 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2517 MemOpChains.push_back(Store);
2522 if (!MemOpChains.empty())
2523 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2525 // Build a sequence of copy-to-reg nodes chained together with token chain
2526 // and flag operands which copy the outgoing args into the appropriate regs.
2528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2529 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2530 RegsToPass[i].second, InFlag);
2531 InFlag = Chain.getValue(1);
2534 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2535 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2536 // node so that legalize doesn't hack it.
2537 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2538 Subtarget->isTargetMachO()) {
2539 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2540 const GlobalValue *GV = G->getGlobal();
2541 bool InternalLinkage = GV->hasInternalLinkage();
2542 if (InternalLinkage)
2543 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2545 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2547 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2549 } else if (ExternalSymbolSDNode *S =
2550 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2551 const char *Sym = S->getSymbol();
2553 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2554 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2556 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2557 const GlobalValue *GV = G->getGlobal();
2558 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2559 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2560 const char *Sym = S->getSymbol();
2561 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2564 // We don't usually want to end the call-sequence here because we would tidy
2565 // the frame up *after* the call, however in the ABI-changing tail-call case
2566 // we've carefully laid out the parameters so that when sp is reset they'll be
2567 // in the correct location.
2568 if (IsTailCall && !IsSibCall) {
2569 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2570 DAG.getIntPtrConstant(0, true), InFlag, DL);
2571 InFlag = Chain.getValue(1);
2574 std::vector<SDValue> Ops;
2575 Ops.push_back(Chain);
2576 Ops.push_back(Callee);
2579 // Each tail call may have to adjust the stack by a different amount, so
2580 // this information must travel along with the operation for eventual
2581 // consumption by emitEpilogue.
2582 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2585 // Add argument registers to the end of the list so that they are known live
2587 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2588 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2589 RegsToPass[i].second.getValueType()));
2591 // Add a register mask operand representing the call-preserved registers.
2592 const uint32_t *Mask;
2593 const TargetRegisterInfo *TRI =
2594 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2595 const AArch64RegisterInfo *ARI =
2596 static_cast<const AArch64RegisterInfo *>(TRI);
2598 // For 'this' returns, use the X0-preserving mask if applicable
2599 Mask = ARI->getThisReturnPreservedMask(CallConv);
2601 IsThisReturn = false;
2602 Mask = ARI->getCallPreservedMask(CallConv);
2605 Mask = ARI->getCallPreservedMask(CallConv);
2607 assert(Mask && "Missing call preserved mask for calling convention");
2608 Ops.push_back(DAG.getRegisterMask(Mask));
2610 if (InFlag.getNode())
2611 Ops.push_back(InFlag);
2613 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2615 // If we're doing a tall call, use a TC_RETURN here rather than an
2616 // actual call instruction.
2618 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2620 // Returns a chain and a flag for retval copy to use.
2621 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2622 InFlag = Chain.getValue(1);
2624 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2625 ? RoundUpToAlignment(NumBytes, 16)
2628 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2629 DAG.getIntPtrConstant(CalleePopBytes, true),
2632 InFlag = Chain.getValue(1);
2634 // Handle result values, copying them out of physregs into vregs that we
2636 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2637 InVals, IsThisReturn,
2638 IsThisReturn ? OutVals[0] : SDValue());
2641 bool AArch64TargetLowering::CanLowerReturn(
2642 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2643 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2644 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2645 ? RetCC_AArch64_WebKit_JS
2646 : RetCC_AArch64_AAPCS;
2647 SmallVector<CCValAssign, 16> RVLocs;
2648 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2649 return CCInfo.CheckReturn(Outs, RetCC);
2653 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2655 const SmallVectorImpl<ISD::OutputArg> &Outs,
2656 const SmallVectorImpl<SDValue> &OutVals,
2657 SDLoc DL, SelectionDAG &DAG) const {
2658 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2659 ? RetCC_AArch64_WebKit_JS
2660 : RetCC_AArch64_AAPCS;
2661 SmallVector<CCValAssign, 16> RVLocs;
2662 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2664 CCInfo.AnalyzeReturn(Outs, RetCC);
2666 // Copy the result values into the output registers.
2668 SmallVector<SDValue, 4> RetOps(1, Chain);
2669 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2670 ++i, ++realRVLocIdx) {
2671 CCValAssign &VA = RVLocs[i];
2672 assert(VA.isRegLoc() && "Can only return in registers!");
2673 SDValue Arg = OutVals[realRVLocIdx];
2675 switch (VA.getLocInfo()) {
2677 llvm_unreachable("Unknown loc info!");
2678 case CCValAssign::Full:
2679 if (Outs[i].ArgVT == MVT::i1) {
2680 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2681 // value. This is strictly redundant on Darwin (which uses "zeroext
2682 // i1"), but will be optimised out before ISel.
2683 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2684 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2687 case CCValAssign::BCvt:
2688 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2692 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2693 Flag = Chain.getValue(1);
2694 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2697 RetOps[0] = Chain; // Update chain.
2699 // Add the flag if we have it.
2701 RetOps.push_back(Flag);
2703 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2706 //===----------------------------------------------------------------------===//
2707 // Other Lowering Code
2708 //===----------------------------------------------------------------------===//
2710 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2711 SelectionDAG &DAG) const {
2712 EVT PtrVT = getPointerTy();
2714 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2715 unsigned char OpFlags =
2716 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2718 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2719 "unexpected offset in global node");
2721 // This also catched the large code model case for Darwin.
2722 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2723 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2724 // FIXME: Once remat is capable of dealing with instructions with register
2725 // operands, expand this into two nodes instead of using a wrapper node.
2726 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2729 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2730 const unsigned char MO_NC = AArch64II::MO_NC;
2732 AArch64ISD::WrapperLarge, DL, PtrVT,
2733 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2734 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2735 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2736 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2738 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2739 // the only correct model on Darwin.
2740 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2741 OpFlags | AArch64II::MO_PAGE);
2742 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2743 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2745 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2746 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2750 /// \brief Convert a TLS address reference into the correct sequence of loads
2751 /// and calls to compute the variable's address (for Darwin, currently) and
2752 /// return an SDValue containing the final node.
2754 /// Darwin only has one TLS scheme which must be capable of dealing with the
2755 /// fully general situation, in the worst case. This means:
2756 /// + "extern __thread" declaration.
2757 /// + Defined in a possibly unknown dynamic library.
2759 /// The general system is that each __thread variable has a [3 x i64] descriptor
2760 /// which contains information used by the runtime to calculate the address. The
2761 /// only part of this the compiler needs to know about is the first xword, which
2762 /// contains a function pointer that must be called with the address of the
2763 /// entire descriptor in "x0".
2765 /// Since this descriptor may be in a different unit, in general even the
2766 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2768 /// adrp x0, _var@TLVPPAGE
2769 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2770 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2771 /// ; the function pointer
2772 /// blr x1 ; Uses descriptor address in x0
2773 /// ; Address of _var is now in x0.
2775 /// If the address of _var's descriptor *is* known to the linker, then it can
2776 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2777 /// a slight efficiency gain.
2779 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2780 SelectionDAG &DAG) const {
2781 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2784 MVT PtrVT = getPointerTy();
2785 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2788 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2789 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2791 // The first entry in the descriptor is a function pointer that we must call
2792 // to obtain the address of the variable.
2793 SDValue Chain = DAG.getEntryNode();
2794 SDValue FuncTLVGet =
2795 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2796 false, true, true, 8);
2797 Chain = FuncTLVGet.getValue(1);
2799 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2800 MFI->setAdjustsStack(true);
2802 // TLS calls preserve all registers except those that absolutely must be
2803 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2805 const TargetRegisterInfo *TRI =
2806 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2807 const AArch64RegisterInfo *ARI =
2808 static_cast<const AArch64RegisterInfo *>(TRI);
2809 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2811 // Finally, we can make the call. This is just a degenerate version of a
2812 // normal AArch64 call node: x0 takes the address of the descriptor, and
2813 // returns the address of the variable in this thread.
2814 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2816 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2817 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2818 DAG.getRegisterMask(Mask), Chain.getValue(1));
2819 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2822 /// When accessing thread-local variables under either the general-dynamic or
2823 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2824 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2825 /// is a function pointer to carry out the resolution. This function takes the
2826 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2827 /// other registers (except LR, NZCV) are preserved.
2829 /// Thus, the ideal call sequence on AArch64 is:
2831 /// adrp x0, :tlsdesc:thread_var
2832 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2833 /// add x0, x0, :tlsdesc_lo12:thread_var
2834 /// .tlsdesccall thread_var
2836 /// (TPIDR_EL0 offset now in x0).
2838 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2839 /// relocation to help the linker relax this sequence if it turns out to be too
2842 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2844 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2845 SDValue DescAddr, SDLoc DL,
2846 SelectionDAG &DAG) const {
2847 EVT PtrVT = getPointerTy();
2849 // The function we need to call is simply the first entry in the GOT for this
2850 // descriptor, load it in preparation.
2851 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2853 // TLS calls preserve all registers except those that absolutely must be
2854 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2856 const TargetRegisterInfo *TRI =
2857 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2858 const AArch64RegisterInfo *ARI =
2859 static_cast<const AArch64RegisterInfo *>(TRI);
2860 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2862 // The function takes only one argument: the address of the descriptor itself
2864 SDValue Glue, Chain;
2865 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2866 Glue = Chain.getValue(1);
2868 // We're now ready to populate the argument list, as with a normal call:
2869 SmallVector<SDValue, 6> Ops;
2870 Ops.push_back(Chain);
2871 Ops.push_back(Func);
2872 Ops.push_back(SymAddr);
2873 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2874 Ops.push_back(DAG.getRegisterMask(Mask));
2875 Ops.push_back(Glue);
2877 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2878 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2879 Glue = Chain.getValue(1);
2881 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2885 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2886 SelectionDAG &DAG) const {
2887 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2888 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2889 "ELF TLS only supported in small memory model");
2890 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2892 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2895 EVT PtrVT = getPointerTy();
2897 const GlobalValue *GV = GA->getGlobal();
2899 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2901 if (Model == TLSModel::LocalExec) {
2902 SDValue HiVar = DAG.getTargetGlobalAddress(
2903 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2904 SDValue LoVar = DAG.getTargetGlobalAddress(
2906 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2908 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2909 DAG.getTargetConstant(16, MVT::i32)),
2911 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2912 DAG.getTargetConstant(0, MVT::i32)),
2914 } else if (Model == TLSModel::InitialExec) {
2915 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2916 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2917 } else if (Model == TLSModel::LocalDynamic) {
2918 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2919 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2920 // the beginning of the module's TLS region, followed by a DTPREL offset
2923 // These accesses will need deduplicating if there's more than one.
2924 AArch64FunctionInfo *MFI =
2925 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2926 MFI->incNumLocalDynamicTLSAccesses();
2928 // Accesses used in this sequence go via the TLS descriptor which lives in
2929 // the GOT. Prepare an address we can use to handle this.
2930 SDValue HiDesc = DAG.getTargetExternalSymbol(
2931 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2932 SDValue LoDesc = DAG.getTargetExternalSymbol(
2933 "_TLS_MODULE_BASE_", PtrVT,
2934 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2936 // First argument to the descriptor call is the address of the descriptor
2938 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2939 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2941 // The call needs a relocation too for linker relaxation. It doesn't make
2942 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2944 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2947 // Now we can calculate the offset from TPIDR_EL0 to this module's
2948 // thread-local area.
2949 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2951 // Now use :dtprel_whatever: operations to calculate this variable's offset
2952 // in its thread-storage area.
2953 SDValue HiVar = DAG.getTargetGlobalAddress(
2954 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2955 SDValue LoVar = DAG.getTargetGlobalAddress(
2956 GV, DL, MVT::i64, 0,
2957 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2960 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2961 DAG.getTargetConstant(16, MVT::i32)),
2964 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2965 DAG.getTargetConstant(0, MVT::i32)),
2968 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2969 } else if (Model == TLSModel::GeneralDynamic) {
2970 // Accesses used in this sequence go via the TLS descriptor which lives in
2971 // the GOT. Prepare an address we can use to handle this.
2972 SDValue HiDesc = DAG.getTargetGlobalAddress(
2973 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2974 SDValue LoDesc = DAG.getTargetGlobalAddress(
2976 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2978 // First argument to the descriptor call is the address of the descriptor
2980 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2981 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2983 // The call needs a relocation too for linker relaxation. It doesn't make
2984 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2987 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2989 // Finally we can make a call to calculate the offset from tpidr_el0.
2990 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2992 llvm_unreachable("Unsupported ELF TLS access model");
2994 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2997 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2998 SelectionDAG &DAG) const {
2999 if (Subtarget->isTargetDarwin())
3000 return LowerDarwinGlobalTLSAddress(Op, DAG);
3001 else if (Subtarget->isTargetELF())
3002 return LowerELFGlobalTLSAddress(Op, DAG);
3004 llvm_unreachable("Unexpected platform trying to use TLS");
3006 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3007 SDValue Chain = Op.getOperand(0);
3008 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3009 SDValue LHS = Op.getOperand(2);
3010 SDValue RHS = Op.getOperand(3);
3011 SDValue Dest = Op.getOperand(4);
3014 // Handle f128 first, since lowering it will result in comparing the return
3015 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3016 // is expecting to deal with.
3017 if (LHS.getValueType() == MVT::f128) {
3018 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3020 // If softenSetCCOperands returned a scalar, we need to compare the result
3021 // against zero to select between true and false values.
3022 if (!RHS.getNode()) {
3023 RHS = DAG.getConstant(0, LHS.getValueType());
3028 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3030 unsigned Opc = LHS.getOpcode();
3031 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3032 cast<ConstantSDNode>(RHS)->isOne() &&
3033 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3034 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3035 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3036 "Unexpected condition code.");
3037 // Only lower legal XALUO ops.
3038 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3041 // The actual operation with overflow check.
3042 AArch64CC::CondCode OFCC;
3043 SDValue Value, Overflow;
3044 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3046 if (CC == ISD::SETNE)
3047 OFCC = getInvertedCondCode(OFCC);
3048 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3050 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
3054 if (LHS.getValueType().isInteger()) {
3055 assert((LHS.getValueType() == RHS.getValueType()) &&
3056 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3058 // If the RHS of the comparison is zero, we can potentially fold this
3059 // to a specialized branch.
3060 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3061 if (RHSC && RHSC->getZExtValue() == 0) {
3062 if (CC == ISD::SETEQ) {
3063 // See if we can use a TBZ to fold in an AND as well.
3064 // TBZ has a smaller branch displacement than CBZ. If the offset is
3065 // out of bounds, a late MI-layer pass rewrites branches.
3066 // 403.gcc is an example that hits this case.
3067 if (LHS.getOpcode() == ISD::AND &&
3068 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3069 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3070 SDValue Test = LHS.getOperand(0);
3071 uint64_t Mask = LHS.getConstantOperandVal(1);
3072 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3073 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3076 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3077 } else if (CC == ISD::SETNE) {
3078 // See if we can use a TBZ to fold in an AND as well.
3079 // TBZ has a smaller branch displacement than CBZ. If the offset is
3080 // out of bounds, a late MI-layer pass rewrites branches.
3081 // 403.gcc is an example that hits this case.
3082 if (LHS.getOpcode() == ISD::AND &&
3083 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3084 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3085 SDValue Test = LHS.getOperand(0);
3086 uint64_t Mask = LHS.getConstantOperandVal(1);
3087 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3088 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3091 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3092 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3093 // Don't combine AND since emitComparison converts the AND to an ANDS
3094 // (a.k.a. TST) and the test in the test bit and branch instruction
3095 // becomes redundant. This would also increase register pressure.
3096 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3097 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3098 DAG.getConstant(Mask, MVT::i64), Dest);
3101 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3102 LHS.getOpcode() != ISD::AND) {
3103 // Don't combine AND since emitComparison converts the AND to an ANDS
3104 // (a.k.a. TST) and the test in the test bit and branch instruction
3105 // becomes redundant. This would also increase register pressure.
3106 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3107 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3108 DAG.getConstant(Mask, MVT::i64), Dest);
3112 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3113 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3117 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3119 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3120 // clean. Some of them require two branches to implement.
3121 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3122 AArch64CC::CondCode CC1, CC2;
3123 changeFPCCToAArch64CC(CC, CC1, CC2);
3124 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3126 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3127 if (CC2 != AArch64CC::AL) {
3128 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3129 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3136 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3137 SelectionDAG &DAG) const {
3138 EVT VT = Op.getValueType();
3141 SDValue In1 = Op.getOperand(0);
3142 SDValue In2 = Op.getOperand(1);
3143 EVT SrcVT = In2.getValueType();
3145 if (SrcVT == MVT::f32 && VT == MVT::f64)
3146 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3147 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3148 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3150 // FIXME: Src type is different, bail out for now. Can VT really be a
3157 SDValue EltMask, VecVal1, VecVal2;
3158 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3161 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3163 if (!VT.isVector()) {
3164 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3165 DAG.getUNDEF(VecVT), In1);
3166 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3167 DAG.getUNDEF(VecVT), In2);
3169 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3170 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3172 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3176 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3177 // immediate moves cannot materialize that in a single instruction for
3178 // 64-bit elements. Instead, materialize zero and then negate it.
3179 EltMask = DAG.getConstant(0, EltVT);
3181 if (!VT.isVector()) {
3182 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3183 DAG.getUNDEF(VecVT), In1);
3184 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3185 DAG.getUNDEF(VecVT), In2);
3187 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3188 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3191 llvm_unreachable("Invalid type for copysign!");
3194 std::vector<SDValue> BuildVectorOps;
3195 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3196 BuildVectorOps.push_back(EltMask);
3198 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3200 // If we couldn't materialize the mask above, then the mask vector will be
3201 // the zero vector, and we need to negate it here.
3202 if (VT == MVT::f64 || VT == MVT::v2f64) {
3203 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3204 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3205 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3209 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3212 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3213 else if (VT == MVT::f64)
3214 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3216 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3219 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3220 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3221 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3224 // While there is no integer popcount instruction, it can
3225 // be more efficiently lowered to the following sequence that uses
3226 // AdvSIMD registers/instructions as long as the copies to/from
3227 // the AdvSIMD registers are cheap.
3228 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3229 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3230 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3231 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3232 SDValue Val = Op.getOperand(0);
3234 EVT VT = Op.getValueType();
3235 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3238 if (VT == MVT::i32) {
3239 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3240 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3243 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3246 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3247 SDValue UaddLV = DAG.getNode(
3248 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3249 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3252 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3256 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3258 if (Op.getValueType().isVector())
3259 return LowerVSETCC(Op, DAG);
3261 SDValue LHS = Op.getOperand(0);
3262 SDValue RHS = Op.getOperand(1);
3263 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3266 // We chose ZeroOrOneBooleanContents, so use zero and one.
3267 EVT VT = Op.getValueType();
3268 SDValue TVal = DAG.getConstant(1, VT);
3269 SDValue FVal = DAG.getConstant(0, VT);
3271 // Handle f128 first, since one possible outcome is a normal integer
3272 // comparison which gets picked up by the next if statement.
3273 if (LHS.getValueType() == MVT::f128) {
3274 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3276 // If softenSetCCOperands returned a scalar, use it.
3277 if (!RHS.getNode()) {
3278 assert(LHS.getValueType() == Op.getValueType() &&
3279 "Unexpected setcc expansion!");
3284 if (LHS.getValueType().isInteger()) {
3287 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3289 // Note that we inverted the condition above, so we reverse the order of
3290 // the true and false operands here. This will allow the setcc to be
3291 // matched to a single CSINC instruction.
3292 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3295 // Now we know we're dealing with FP values.
3296 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3298 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3299 // and do the comparison.
3300 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3302 AArch64CC::CondCode CC1, CC2;
3303 changeFPCCToAArch64CC(CC, CC1, CC2);
3304 if (CC2 == AArch64CC::AL) {
3305 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3306 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3308 // Note that we inverted the condition above, so we reverse the order of
3309 // the true and false operands here. This will allow the setcc to be
3310 // matched to a single CSINC instruction.
3311 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3313 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3314 // totally clean. Some of them require two CSELs to implement. As is in
3315 // this case, we emit the first CSEL and then emit a second using the output
3316 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3318 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3319 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3321 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3323 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3324 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3328 /// A SELECT_CC operation is really some kind of max or min if both values being
3329 /// compared are, in some sense, equal to the results in either case. However,
3330 /// it is permissible to compare f32 values and produce directly extended f64
3333 /// Extending the comparison operands would also be allowed, but is less likely
3334 /// to happen in practice since their use is right here. Note that truncate
3335 /// operations would *not* be semantically equivalent.
3336 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3340 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3341 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3342 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3343 Result.getValueType() == MVT::f64) {
3345 APFloat CmpVal = CCmp->getValueAPF();
3346 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3347 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3350 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3353 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3354 SelectionDAG &DAG) const {
3355 SDValue CC = Op->getOperand(0);
3356 SDValue TVal = Op->getOperand(1);
3357 SDValue FVal = Op->getOperand(2);
3360 unsigned Opc = CC.getOpcode();
3361 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3363 if (CC.getResNo() == 1 &&
3364 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3365 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3366 // Only lower legal XALUO ops.
3367 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3370 AArch64CC::CondCode OFCC;
3371 SDValue Value, Overflow;
3372 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3373 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3375 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3379 if (CC.getOpcode() == ISD::SETCC)
3380 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3381 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3383 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3387 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3388 SelectionDAG &DAG) const {
3389 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3390 SDValue LHS = Op.getOperand(0);
3391 SDValue RHS = Op.getOperand(1);
3392 SDValue TVal = Op.getOperand(2);
3393 SDValue FVal = Op.getOperand(3);
3396 // Handle f128 first, because it will result in a comparison of some RTLIB
3397 // call result against zero.
3398 if (LHS.getValueType() == MVT::f128) {
3399 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3401 // If softenSetCCOperands returned a scalar, we need to compare the result
3402 // against zero to select between true and false values.
3403 if (!RHS.getNode()) {
3404 RHS = DAG.getConstant(0, LHS.getValueType());
3409 // Handle integers first.
3410 if (LHS.getValueType().isInteger()) {
3411 assert((LHS.getValueType() == RHS.getValueType()) &&
3412 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3414 unsigned Opcode = AArch64ISD::CSEL;
3416 // If both the TVal and the FVal are constants, see if we can swap them in
3417 // order to for a CSINV or CSINC out of them.
3418 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3419 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3421 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3422 std::swap(TVal, FVal);
3423 std::swap(CTVal, CFVal);
3424 CC = ISD::getSetCCInverse(CC, true);
3425 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3426 std::swap(TVal, FVal);
3427 std::swap(CTVal, CFVal);
3428 CC = ISD::getSetCCInverse(CC, true);
3429 } else if (TVal.getOpcode() == ISD::XOR) {
3430 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3431 // with a CSINV rather than a CSEL.
3432 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3434 if (CVal && CVal->isAllOnesValue()) {
3435 std::swap(TVal, FVal);
3436 std::swap(CTVal, CFVal);
3437 CC = ISD::getSetCCInverse(CC, true);
3439 } else if (TVal.getOpcode() == ISD::SUB) {
3440 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3441 // that we can match with a CSNEG rather than a CSEL.
3442 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3444 if (CVal && CVal->isNullValue()) {
3445 std::swap(TVal, FVal);
3446 std::swap(CTVal, CFVal);
3447 CC = ISD::getSetCCInverse(CC, true);
3449 } else if (CTVal && CFVal) {
3450 const int64_t TrueVal = CTVal->getSExtValue();
3451 const int64_t FalseVal = CFVal->getSExtValue();
3454 // If both TVal and FVal are constants, see if FVal is the
3455 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3456 // instead of a CSEL in that case.
3457 if (TrueVal == ~FalseVal) {
3458 Opcode = AArch64ISD::CSINV;
3459 } else if (TrueVal == -FalseVal) {
3460 Opcode = AArch64ISD::CSNEG;
3461 } else if (TVal.getValueType() == MVT::i32) {
3462 // If our operands are only 32-bit wide, make sure we use 32-bit
3463 // arithmetic for the check whether we can use CSINC. This ensures that
3464 // the addition in the check will wrap around properly in case there is
3465 // an overflow (which would not be the case if we do the check with
3466 // 64-bit arithmetic).
3467 const uint32_t TrueVal32 = CTVal->getZExtValue();
3468 const uint32_t FalseVal32 = CFVal->getZExtValue();
3470 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3471 Opcode = AArch64ISD::CSINC;
3473 if (TrueVal32 > FalseVal32) {
3477 // 64-bit check whether we can use CSINC.
3478 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3479 Opcode = AArch64ISD::CSINC;
3481 if (TrueVal > FalseVal) {
3486 // Swap TVal and FVal if necessary.
3488 std::swap(TVal, FVal);
3489 std::swap(CTVal, CFVal);
3490 CC = ISD::getSetCCInverse(CC, true);
3493 if (Opcode != AArch64ISD::CSEL) {
3494 // Drop FVal since we can get its value by simply inverting/negating
3501 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3503 EVT VT = Op.getValueType();
3504 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3507 // Now we know we're dealing with FP values.
3508 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3509 assert(LHS.getValueType() == RHS.getValueType());
3510 EVT VT = Op.getValueType();
3512 // Try to match this select into a max/min operation, which have dedicated
3513 // opcode in the instruction set.
3514 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3516 if (getTargetMachine().Options.NoNaNsFPMath) {
3517 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3518 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3519 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3520 CC = ISD::getSetCCSwappedOperands(CC);
3521 std::swap(MinMaxLHS, MinMaxRHS);
3524 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3525 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3535 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3543 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3549 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3550 // and do the comparison.
3551 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3553 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3554 // clean. Some of them require two CSELs to implement.
3555 AArch64CC::CondCode CC1, CC2;
3556 changeFPCCToAArch64CC(CC, CC1, CC2);
3557 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3558 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3560 // If we need a second CSEL, emit it, using the output of the first as the
3561 // RHS. We're effectively OR'ing the two CC's together.
3562 if (CC2 != AArch64CC::AL) {
3563 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3564 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3567 // Otherwise, return the output of the first CSEL.
3571 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3572 SelectionDAG &DAG) const {
3573 // Jump table entries as PC relative offsets. No additional tweaking
3574 // is necessary here. Just get the address of the jump table.
3575 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3576 EVT PtrVT = getPointerTy();
3579 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3580 !Subtarget->isTargetMachO()) {
3581 const unsigned char MO_NC = AArch64II::MO_NC;
3583 AArch64ISD::WrapperLarge, DL, PtrVT,
3584 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3585 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3586 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3587 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3588 AArch64II::MO_G0 | MO_NC));
3592 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3593 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3594 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3595 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3596 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3599 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3600 SelectionDAG &DAG) const {
3601 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3602 EVT PtrVT = getPointerTy();
3605 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3606 // Use the GOT for the large code model on iOS.
3607 if (Subtarget->isTargetMachO()) {
3608 SDValue GotAddr = DAG.getTargetConstantPool(
3609 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3611 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3614 const unsigned char MO_NC = AArch64II::MO_NC;
3616 AArch64ISD::WrapperLarge, DL, PtrVT,
3617 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3618 CP->getOffset(), AArch64II::MO_G3),
3619 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3620 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3621 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3622 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3623 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3624 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3626 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3627 // ELF, the only valid one on Darwin.
3629 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3630 CP->getOffset(), AArch64II::MO_PAGE);
3631 SDValue Lo = DAG.getTargetConstantPool(
3632 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3633 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3635 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3636 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3640 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3641 SelectionDAG &DAG) const {
3642 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3643 EVT PtrVT = getPointerTy();
3645 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3646 !Subtarget->isTargetMachO()) {
3647 const unsigned char MO_NC = AArch64II::MO_NC;
3649 AArch64ISD::WrapperLarge, DL, PtrVT,
3650 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3651 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3652 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3653 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3655 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3656 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3658 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3659 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3663 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3664 SelectionDAG &DAG) const {
3665 AArch64FunctionInfo *FuncInfo =
3666 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3670 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3671 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3672 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3673 MachinePointerInfo(SV), false, false, 0);
3676 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3677 SelectionDAG &DAG) const {
3678 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3679 // Standard, section B.3.
3680 MachineFunction &MF = DAG.getMachineFunction();
3681 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3684 SDValue Chain = Op.getOperand(0);
3685 SDValue VAList = Op.getOperand(1);
3686 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3687 SmallVector<SDValue, 4> MemOps;
3689 // void *__stack at offset 0
3691 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3692 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3693 MachinePointerInfo(SV), false, false, 8));
3695 // void *__gr_top at offset 8
3696 int GPRSize = FuncInfo->getVarArgsGPRSize();
3698 SDValue GRTop, GRTopAddr;
3700 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3701 DAG.getConstant(8, getPointerTy()));
3703 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3704 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3705 DAG.getConstant(GPRSize, getPointerTy()));
3707 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3708 MachinePointerInfo(SV, 8), false, false, 8));
3711 // void *__vr_top at offset 16
3712 int FPRSize = FuncInfo->getVarArgsFPRSize();
3714 SDValue VRTop, VRTopAddr;
3715 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3716 DAG.getConstant(16, getPointerTy()));
3718 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3719 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3720 DAG.getConstant(FPRSize, getPointerTy()));
3722 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3723 MachinePointerInfo(SV, 16), false, false, 8));
3726 // int __gr_offs at offset 24
3727 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3728 DAG.getConstant(24, getPointerTy()));
3729 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3730 GROffsAddr, MachinePointerInfo(SV, 24), false,
3733 // int __vr_offs at offset 28
3734 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3735 DAG.getConstant(28, getPointerTy()));
3736 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3737 VROffsAddr, MachinePointerInfo(SV, 28), false,
3740 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3743 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3744 SelectionDAG &DAG) const {
3745 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3746 : LowerAAPCS_VASTART(Op, DAG);
3749 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3750 SelectionDAG &DAG) const {
3751 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3753 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3754 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3755 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3757 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3758 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3759 8, false, false, MachinePointerInfo(DestSV),
3760 MachinePointerInfo(SrcSV));
3763 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3764 assert(Subtarget->isTargetDarwin() &&
3765 "automatic va_arg instruction only works on Darwin");
3767 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3768 EVT VT = Op.getValueType();
3770 SDValue Chain = Op.getOperand(0);
3771 SDValue Addr = Op.getOperand(1);
3772 unsigned Align = Op.getConstantOperandVal(3);
3774 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3775 MachinePointerInfo(V), false, false, false, 0);
3776 Chain = VAList.getValue(1);
3779 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3780 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3781 DAG.getConstant(Align - 1, getPointerTy()));
3782 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3783 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3786 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3787 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3789 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3790 // up to 64 bits. At the very least, we have to increase the striding of the
3791 // vaargs list to match this, and for FP values we need to introduce
3792 // FP_ROUND nodes as well.
3793 if (VT.isInteger() && !VT.isVector())
3795 bool NeedFPTrunc = false;
3796 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3801 // Increment the pointer, VAList, to the next vaarg
3802 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3803 DAG.getConstant(ArgSize, getPointerTy()));
3804 // Store the incremented VAList to the legalized pointer
3805 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3808 // Load the actual argument out of the pointer VAList
3810 // Load the value as an f64.
3811 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3812 MachinePointerInfo(), false, false, false, 0);
3813 // Round the value down to an f32.
3814 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3815 DAG.getIntPtrConstant(1));
3816 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3817 // Merge the rounded value with the chain output of the load.
3818 return DAG.getMergeValues(Ops, DL);
3821 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3825 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3826 SelectionDAG &DAG) const {
3827 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3828 MFI->setFrameAddressIsTaken(true);
3830 EVT VT = Op.getValueType();
3832 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3834 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3836 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3837 MachinePointerInfo(), false, false, false, 0);
3841 // FIXME? Maybe this could be a TableGen attribute on some registers and
3842 // this table could be generated automatically from RegInfo.
3843 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3845 unsigned Reg = StringSwitch<unsigned>(RegName)
3846 .Case("sp", AArch64::SP)
3850 report_fatal_error("Invalid register name global variable");
3853 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3854 SelectionDAG &DAG) const {
3855 MachineFunction &MF = DAG.getMachineFunction();
3856 MachineFrameInfo *MFI = MF.getFrameInfo();
3857 MFI->setReturnAddressIsTaken(true);
3859 EVT VT = Op.getValueType();
3861 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3863 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3864 SDValue Offset = DAG.getConstant(8, getPointerTy());
3865 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3866 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3867 MachinePointerInfo(), false, false, false, 0);
3870 // Return LR, which contains the return address. Mark it an implicit live-in.
3871 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3872 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3875 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3876 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3877 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3878 SelectionDAG &DAG) const {
3879 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3880 EVT VT = Op.getValueType();
3881 unsigned VTBits = VT.getSizeInBits();
3883 SDValue ShOpLo = Op.getOperand(0);
3884 SDValue ShOpHi = Op.getOperand(1);
3885 SDValue ShAmt = Op.getOperand(2);
3887 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3889 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3891 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3892 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3893 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3894 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3895 DAG.getConstant(VTBits, MVT::i64));
3896 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3898 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3899 ISD::SETGE, dl, DAG);
3900 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3902 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3903 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3905 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3907 // AArch64 shifts larger than the register width are wrapped rather than
3908 // clamped, so we can't just emit "hi >> x".
3909 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3910 SDValue TrueValHi = Opc == ISD::SRA
3911 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3912 DAG.getConstant(VTBits - 1, MVT::i64))
3913 : DAG.getConstant(0, VT);
3915 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3917 SDValue Ops[2] = { Lo, Hi };
3918 return DAG.getMergeValues(Ops, dl);
3921 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3922 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3923 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3924 SelectionDAG &DAG) const {
3925 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3926 EVT VT = Op.getValueType();
3927 unsigned VTBits = VT.getSizeInBits();
3929 SDValue ShOpLo = Op.getOperand(0);
3930 SDValue ShOpHi = Op.getOperand(1);
3931 SDValue ShAmt = Op.getOperand(2);
3934 assert(Op.getOpcode() == ISD::SHL_PARTS);
3935 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3936 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3937 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3938 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3939 DAG.getConstant(VTBits, MVT::i64));
3940 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3941 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3943 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3945 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3946 ISD::SETGE, dl, DAG);
3947 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3949 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3951 // AArch64 shifts of larger than register sizes are wrapped rather than
3952 // clamped, so we can't just emit "lo << a" if a is too big.
3953 SDValue TrueValLo = DAG.getConstant(0, VT);
3954 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3956 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3958 SDValue Ops[2] = { Lo, Hi };
3959 return DAG.getMergeValues(Ops, dl);
3962 bool AArch64TargetLowering::isOffsetFoldingLegal(
3963 const GlobalAddressSDNode *GA) const {
3964 // The AArch64 target doesn't support folding offsets into global addresses.
3968 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3969 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3970 // FIXME: We should be able to handle f128 as well with a clever lowering.
3971 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3975 return AArch64_AM::getFP64Imm(Imm) != -1;
3976 else if (VT == MVT::f32)
3977 return AArch64_AM::getFP32Imm(Imm) != -1;
3981 //===----------------------------------------------------------------------===//
3982 // AArch64 Optimization Hooks
3983 //===----------------------------------------------------------------------===//
3985 //===----------------------------------------------------------------------===//
3986 // AArch64 Inline Assembly Support
3987 //===----------------------------------------------------------------------===//
3989 // Table of Constraints
3990 // TODO: This is the current set of constraints supported by ARM for the
3991 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3993 // r - A general register
3994 // w - An FP/SIMD register of some size in the range v0-v31
3995 // x - An FP/SIMD register of some size in the range v0-v15
3996 // I - Constant that can be used with an ADD instruction
3997 // J - Constant that can be used with a SUB instruction
3998 // K - Constant that can be used with a 32-bit logical instruction
3999 // L - Constant that can be used with a 64-bit logical instruction
4000 // M - Constant that can be used as a 32-bit MOV immediate
4001 // N - Constant that can be used as a 64-bit MOV immediate
4002 // Q - A memory reference with base register and no offset
4003 // S - A symbolic address
4004 // Y - Floating point constant zero
4005 // Z - Integer constant zero
4007 // Note that general register operands will be output using their 64-bit x
4008 // register name, whatever the size of the variable, unless the asm operand
4009 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4010 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4013 /// getConstraintType - Given a constraint letter, return the type of
4014 /// constraint it is for this target.
4015 AArch64TargetLowering::ConstraintType
4016 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4017 if (Constraint.size() == 1) {
4018 switch (Constraint[0]) {
4025 return C_RegisterClass;
4026 // An address with a single base register. Due to the way we
4027 // currently handle addresses it is the same as 'r'.
4032 return TargetLowering::getConstraintType(Constraint);
4035 /// Examine constraint type and operand type and determine a weight value.
4036 /// This object must already have been set up with the operand type
4037 /// and the current alternative constraint selected.
4038 TargetLowering::ConstraintWeight
4039 AArch64TargetLowering::getSingleConstraintMatchWeight(
4040 AsmOperandInfo &info, const char *constraint) const {
4041 ConstraintWeight weight = CW_Invalid;
4042 Value *CallOperandVal = info.CallOperandVal;
4043 // If we don't have a value, we can't do a match,
4044 // but allow it at the lowest weight.
4045 if (!CallOperandVal)
4047 Type *type = CallOperandVal->getType();
4048 // Look at the constraint type.
4049 switch (*constraint) {
4051 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4055 if (type->isFloatingPointTy() || type->isVectorTy())
4056 weight = CW_Register;
4059 weight = CW_Constant;
4065 std::pair<unsigned, const TargetRegisterClass *>
4066 AArch64TargetLowering::getRegForInlineAsmConstraint(
4067 const std::string &Constraint, MVT VT) const {
4068 if (Constraint.size() == 1) {
4069 switch (Constraint[0]) {
4071 if (VT.getSizeInBits() == 64)
4072 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4073 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4076 return std::make_pair(0U, &AArch64::FPR32RegClass);
4077 if (VT.getSizeInBits() == 64)
4078 return std::make_pair(0U, &AArch64::FPR64RegClass);
4079 if (VT.getSizeInBits() == 128)
4080 return std::make_pair(0U, &AArch64::FPR128RegClass);
4082 // The instructions that this constraint is designed for can
4083 // only take 128-bit registers so just use that regclass.
4085 if (VT.getSizeInBits() == 128)
4086 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4090 if (StringRef("{cc}").equals_lower(Constraint))
4091 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4093 // Use the default implementation in TargetLowering to convert the register
4094 // constraint into a member of a register class.
4095 std::pair<unsigned, const TargetRegisterClass *> Res;
4096 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4098 // Not found as a standard register?
4100 unsigned Size = Constraint.size();
4101 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4102 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4103 const std::string Reg =
4104 std::string(&Constraint[2], &Constraint[Size - 1]);
4105 int RegNo = atoi(Reg.c_str());
4106 if (RegNo >= 0 && RegNo <= 31) {
4107 // v0 - v31 are aliases of q0 - q31.
4108 // By default we'll emit v0-v31 for this unless there's a modifier where
4109 // we'll emit the correct register as well.
4110 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4111 Res.second = &AArch64::FPR128RegClass;
4119 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4120 /// vector. If it is invalid, don't add anything to Ops.
4121 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4122 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4123 SelectionDAG &DAG) const {
4126 // Currently only support length 1 constraints.
4127 if (Constraint.length() != 1)
4130 char ConstraintLetter = Constraint[0];
4131 switch (ConstraintLetter) {
4135 // This set of constraints deal with valid constants for various instructions.
4136 // Validate and return a target constant for them if we can.
4138 // 'z' maps to xzr or wzr so it needs an input of 0.
4139 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4140 if (!C || C->getZExtValue() != 0)
4143 if (Op.getValueType() == MVT::i64)
4144 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4146 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4156 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4160 // Grab the value and do some validation.
4161 uint64_t CVal = C->getZExtValue();
4162 switch (ConstraintLetter) {
4163 // The I constraint applies only to simple ADD or SUB immediate operands:
4164 // i.e. 0 to 4095 with optional shift by 12
4165 // The J constraint applies only to ADD or SUB immediates that would be
4166 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4167 // instruction [or vice versa], in other words -1 to -4095 with optional
4168 // left shift by 12.
4170 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4174 uint64_t NVal = -C->getSExtValue();
4175 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4176 CVal = C->getSExtValue();
4181 // The K and L constraints apply *only* to logical immediates, including
4182 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4183 // been removed and MOV should be used). So these constraints have to
4184 // distinguish between bit patterns that are valid 32-bit or 64-bit
4185 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4186 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4189 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4193 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4196 // The M and N constraints are a superset of K and L respectively, for use
4197 // with the MOV (immediate) alias. As well as the logical immediates they
4198 // also match 32 or 64-bit immediates that can be loaded either using a
4199 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4200 // (M) or 64-bit 0x1234000000000000 (N) etc.
4201 // As a note some of this code is liberally stolen from the asm parser.
4203 if (!isUInt<32>(CVal))
4205 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4207 if ((CVal & 0xFFFF) == CVal)
4209 if ((CVal & 0xFFFF0000ULL) == CVal)
4211 uint64_t NCVal = ~(uint32_t)CVal;
4212 if ((NCVal & 0xFFFFULL) == NCVal)
4214 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4219 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4221 if ((CVal & 0xFFFFULL) == CVal)
4223 if ((CVal & 0xFFFF0000ULL) == CVal)
4225 if ((CVal & 0xFFFF00000000ULL) == CVal)
4227 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4229 uint64_t NCVal = ~CVal;
4230 if ((NCVal & 0xFFFFULL) == NCVal)
4232 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4234 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4236 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4244 // All assembler immediates are 64-bit integers.
4245 Result = DAG.getTargetConstant(CVal, MVT::i64);
4249 if (Result.getNode()) {
4250 Ops.push_back(Result);
4254 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4257 //===----------------------------------------------------------------------===//
4258 // AArch64 Advanced SIMD Support
4259 //===----------------------------------------------------------------------===//
4261 /// WidenVector - Given a value in the V64 register class, produce the
4262 /// equivalent value in the V128 register class.
4263 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4264 EVT VT = V64Reg.getValueType();
4265 unsigned NarrowSize = VT.getVectorNumElements();
4266 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4267 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4270 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4271 V64Reg, DAG.getConstant(0, MVT::i32));
4274 /// getExtFactor - Determine the adjustment factor for the position when
4275 /// generating an "extract from vector registers" instruction.
4276 static unsigned getExtFactor(SDValue &V) {
4277 EVT EltType = V.getValueType().getVectorElementType();
4278 return EltType.getSizeInBits() / 8;
4281 /// NarrowVector - Given a value in the V128 register class, produce the
4282 /// equivalent value in the V64 register class.
4283 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4284 EVT VT = V128Reg.getValueType();
4285 unsigned WideSize = VT.getVectorNumElements();
4286 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4287 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4290 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4293 // Gather data to see if the operation can be modelled as a
4294 // shuffle in combination with VEXTs.
4295 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4296 SelectionDAG &DAG) const {
4297 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4299 EVT VT = Op.getValueType();
4300 unsigned NumElts = VT.getVectorNumElements();
4302 struct ShuffleSourceInfo {
4307 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4308 // be compatible with the shuffle we intend to construct. As a result
4309 // ShuffleVec will be some sliding window into the original Vec.
4312 // Code should guarantee that element i in Vec starts at element "WindowBase
4313 // + i * WindowScale in ShuffleVec".
4317 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4318 ShuffleSourceInfo(SDValue Vec)
4319 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4323 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4325 SmallVector<ShuffleSourceInfo, 2> Sources;
4326 for (unsigned i = 0; i < NumElts; ++i) {
4327 SDValue V = Op.getOperand(i);
4328 if (V.getOpcode() == ISD::UNDEF)
4330 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4331 // A shuffle can only come from building a vector from various
4332 // elements of other vectors.
4336 // Add this element source to the list if it's not already there.
4337 SDValue SourceVec = V.getOperand(0);
4338 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4339 if (Source == Sources.end())
4340 Sources.push_back(ShuffleSourceInfo(SourceVec));
4342 // Update the minimum and maximum lane number seen.
4343 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4344 Source->MinElt = std::min(Source->MinElt, EltNo);
4345 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4348 // Currently only do something sane when at most two source vectors
4350 if (Sources.size() > 2)
4353 // Find out the smallest element size among result and two sources, and use
4354 // it as element size to build the shuffle_vector.
4355 EVT SmallestEltTy = VT.getVectorElementType();
4356 for (auto &Source : Sources) {
4357 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4358 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4359 SmallestEltTy = SrcEltTy;
4362 unsigned ResMultiplier =
4363 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4364 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4365 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4367 // If the source vector is too wide or too narrow, we may nevertheless be able
4368 // to construct a compatible shuffle either by concatenating it with UNDEF or
4369 // extracting a suitable range of elements.
4370 for (auto &Src : Sources) {
4371 EVT SrcVT = Src.ShuffleVec.getValueType();
4373 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4376 // This stage of the search produces a source with the same element type as
4377 // the original, but with a total width matching the BUILD_VECTOR output.
4378 EVT EltVT = SrcVT.getVectorElementType();
4379 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4380 VT.getSizeInBits() / EltVT.getSizeInBits());
4382 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4383 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4384 // We can pad out the smaller vector for free, so if it's part of a
4387 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4388 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4392 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4394 if (Src.MaxElt - Src.MinElt >= NumElts) {
4395 // Span too large for a VEXT to cope
4399 if (Src.MinElt >= NumElts) {
4400 // The extraction can just take the second half
4402 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4403 DAG.getIntPtrConstant(NumElts));
4404 Src.WindowBase = -NumElts;
4405 } else if (Src.MaxElt < NumElts) {
4406 // The extraction can just take the first half
4407 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4408 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4410 // An actual VEXT is needed
4411 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4412 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4414 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4415 DAG.getIntPtrConstant(NumElts));
4416 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4418 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4419 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4420 Src.WindowBase = -Src.MinElt;
4424 // Another possible incompatibility occurs from the vector element types. We
4425 // can fix this by bitcasting the source vectors to the same type we intend
4427 for (auto &Src : Sources) {
4428 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4429 if (SrcEltTy == SmallestEltTy)
4431 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4432 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4433 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4434 Src.WindowBase *= Src.WindowScale;
4437 // Final sanity check before we try to actually produce a shuffle.
4439 for (auto Src : Sources)
4440 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4443 // The stars all align, our next step is to produce the mask for the shuffle.
4444 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4445 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4446 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4447 SDValue Entry = Op.getOperand(i);
4448 if (Entry.getOpcode() == ISD::UNDEF)
4451 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4452 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4454 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4455 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4457 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4458 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4459 VT.getVectorElementType().getSizeInBits());
4460 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4462 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4463 // starting at the appropriate offset.
4464 int *LaneMask = &Mask[i * ResMultiplier];
4466 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4467 ExtractBase += NumElts * (Src - Sources.begin());
4468 for (int j = 0; j < LanesDefined; ++j)
4469 LaneMask[j] = ExtractBase + j;
4472 // Final check before we try to produce nonsense...
4473 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4476 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4477 for (unsigned i = 0; i < Sources.size(); ++i)
4478 ShuffleOps[i] = Sources[i].ShuffleVec;
4480 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4481 ShuffleOps[1], &Mask[0]);
4482 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4485 // check if an EXT instruction can handle the shuffle mask when the
4486 // vector sources of the shuffle are the same.
4487 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4488 unsigned NumElts = VT.getVectorNumElements();
4490 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4496 // If this is a VEXT shuffle, the immediate value is the index of the first
4497 // element. The other shuffle indices must be the successive elements after
4499 unsigned ExpectedElt = Imm;
4500 for (unsigned i = 1; i < NumElts; ++i) {
4501 // Increment the expected index. If it wraps around, just follow it
4502 // back to index zero and keep going.
4504 if (ExpectedElt == NumElts)
4508 continue; // ignore UNDEF indices
4509 if (ExpectedElt != static_cast<unsigned>(M[i]))
4516 // check if an EXT instruction can handle the shuffle mask when the
4517 // vector sources of the shuffle are different.
4518 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4520 // Look for the first non-undef element.
4521 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4522 [](int Elt) {return Elt >= 0;});
4524 // Benefit form APInt to handle overflow when calculating expected element.
4525 unsigned NumElts = VT.getVectorNumElements();
4526 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4527 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4528 // The following shuffle indices must be the successive elements after the
4529 // first real element.
4530 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4531 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4532 if (FirstWrongElt != M.end())
4535 // The index of an EXT is the first element if it is not UNDEF.
4536 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4537 // value of the first element. E.g.
4538 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4539 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4540 // ExpectedElt is the last mask index plus 1.
4541 Imm = ExpectedElt.getZExtValue();
4543 // There are two difference cases requiring to reverse input vectors.
4544 // For example, for vector <4 x i32> we have the following cases,
4545 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4546 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4547 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4548 // to reverse two input vectors.
4557 /// isREVMask - Check if a vector shuffle corresponds to a REV
4558 /// instruction with the specified blocksize. (The order of the elements
4559 /// within each block of the vector is reversed.)
4560 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4561 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4562 "Only possible block sizes for REV are: 16, 32, 64");
4564 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4568 unsigned NumElts = VT.getVectorNumElements();
4569 unsigned BlockElts = M[0] + 1;
4570 // If the first shuffle index is UNDEF, be optimistic.
4572 BlockElts = BlockSize / EltSz;
4574 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4577 for (unsigned i = 0; i < NumElts; ++i) {
4579 continue; // ignore UNDEF indices
4580 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4587 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4588 unsigned NumElts = VT.getVectorNumElements();
4589 WhichResult = (M[0] == 0 ? 0 : 1);
4590 unsigned Idx = WhichResult * NumElts / 2;
4591 for (unsigned i = 0; i != NumElts; i += 2) {
4592 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4593 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4601 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4602 unsigned NumElts = VT.getVectorNumElements();
4603 WhichResult = (M[0] == 0 ? 0 : 1);
4604 for (unsigned i = 0; i != NumElts; ++i) {
4606 continue; // ignore UNDEF indices
4607 if ((unsigned)M[i] != 2 * i + WhichResult)
4614 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4615 unsigned NumElts = VT.getVectorNumElements();
4616 WhichResult = (M[0] == 0 ? 0 : 1);
4617 for (unsigned i = 0; i < NumElts; i += 2) {
4618 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4619 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4625 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4626 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4627 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4628 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4629 unsigned NumElts = VT.getVectorNumElements();
4630 WhichResult = (M[0] == 0 ? 0 : 1);
4631 unsigned Idx = WhichResult * NumElts / 2;
4632 for (unsigned i = 0; i != NumElts; i += 2) {
4633 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4634 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4642 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4643 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4644 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4645 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4646 unsigned Half = VT.getVectorNumElements() / 2;
4647 WhichResult = (M[0] == 0 ? 0 : 1);
4648 for (unsigned j = 0; j != 2; ++j) {
4649 unsigned Idx = WhichResult;
4650 for (unsigned i = 0; i != Half; ++i) {
4651 int MIdx = M[i + j * Half];
4652 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4661 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4662 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4663 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4664 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4665 unsigned NumElts = VT.getVectorNumElements();
4666 WhichResult = (M[0] == 0 ? 0 : 1);
4667 for (unsigned i = 0; i < NumElts; i += 2) {
4668 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4669 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4675 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4676 bool &DstIsLeft, int &Anomaly) {
4677 if (M.size() != static_cast<size_t>(NumInputElements))
4680 int NumLHSMatch = 0, NumRHSMatch = 0;
4681 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4683 for (int i = 0; i < NumInputElements; ++i) {
4693 LastLHSMismatch = i;
4695 if (M[i] == i + NumInputElements)
4698 LastRHSMismatch = i;
4701 if (NumLHSMatch == NumInputElements - 1) {
4703 Anomaly = LastLHSMismatch;
4705 } else if (NumRHSMatch == NumInputElements - 1) {
4707 Anomaly = LastRHSMismatch;
4714 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4715 if (VT.getSizeInBits() != 128)
4718 unsigned NumElts = VT.getVectorNumElements();
4720 for (int I = 0, E = NumElts / 2; I != E; I++) {
4725 int Offset = NumElts / 2;
4726 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4727 if (Mask[I] != I + SplitLHS * Offset)
4734 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4736 EVT VT = Op.getValueType();
4737 SDValue V0 = Op.getOperand(0);
4738 SDValue V1 = Op.getOperand(1);
4739 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4741 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4742 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4745 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4747 if (!isConcatMask(Mask, VT, SplitV0))
4750 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4751 VT.getVectorNumElements() / 2);
4753 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4754 DAG.getConstant(0, MVT::i64));
4756 if (V1.getValueType().getSizeInBits() == 128) {
4757 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4758 DAG.getConstant(0, MVT::i64));
4760 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4763 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4764 /// the specified operations to build the shuffle.
4765 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4766 SDValue RHS, SelectionDAG &DAG,
4768 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4769 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4770 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4773 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4782 OP_VUZPL, // VUZP, left result
4783 OP_VUZPR, // VUZP, right result
4784 OP_VZIPL, // VZIP, left result
4785 OP_VZIPR, // VZIP, right result
4786 OP_VTRNL, // VTRN, left result
4787 OP_VTRNR // VTRN, right result
4790 if (OpNum == OP_COPY) {
4791 if (LHSID == (1 * 9 + 2) * 9 + 3)
4793 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4797 SDValue OpLHS, OpRHS;
4798 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4799 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4800 EVT VT = OpLHS.getValueType();
4804 llvm_unreachable("Unknown shuffle opcode!");
4806 // VREV divides the vector in half and swaps within the half.
4807 if (VT.getVectorElementType() == MVT::i32 ||
4808 VT.getVectorElementType() == MVT::f32)
4809 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4810 // vrev <4 x i16> -> REV32
4811 if (VT.getVectorElementType() == MVT::i16 ||
4812 VT.getVectorElementType() == MVT::f16)
4813 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4814 // vrev <4 x i8> -> REV16
4815 assert(VT.getVectorElementType() == MVT::i8);
4816 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4821 EVT EltTy = VT.getVectorElementType();
4823 if (EltTy == MVT::i8)
4824 Opcode = AArch64ISD::DUPLANE8;
4825 else if (EltTy == MVT::i16)
4826 Opcode = AArch64ISD::DUPLANE16;
4827 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4828 Opcode = AArch64ISD::DUPLANE32;
4829 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4830 Opcode = AArch64ISD::DUPLANE64;
4832 llvm_unreachable("Invalid vector element type?");
4834 if (VT.getSizeInBits() == 64)
4835 OpLHS = WidenVector(OpLHS, DAG);
4836 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4837 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4842 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4843 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4844 DAG.getConstant(Imm, MVT::i32));
4847 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4850 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4853 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4856 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4859 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4862 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4867 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4868 SelectionDAG &DAG) {
4869 // Check to see if we can use the TBL instruction.
4870 SDValue V1 = Op.getOperand(0);
4871 SDValue V2 = Op.getOperand(1);
4874 EVT EltVT = Op.getValueType().getVectorElementType();
4875 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4877 SmallVector<SDValue, 8> TBLMask;
4878 for (int Val : ShuffleMask) {
4879 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4880 unsigned Offset = Byte + Val * BytesPerElt;
4881 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4885 MVT IndexVT = MVT::v8i8;
4886 unsigned IndexLen = 8;
4887 if (Op.getValueType().getSizeInBits() == 128) {
4888 IndexVT = MVT::v16i8;
4892 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4893 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4896 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4898 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4899 Shuffle = DAG.getNode(
4900 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4901 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4902 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4903 makeArrayRef(TBLMask.data(), IndexLen)));
4905 if (IndexLen == 8) {
4906 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4907 Shuffle = DAG.getNode(
4908 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4909 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4910 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4911 makeArrayRef(TBLMask.data(), IndexLen)));
4913 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4914 // cannot currently represent the register constraints on the input
4916 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4917 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4918 // &TBLMask[0], IndexLen));
4919 Shuffle = DAG.getNode(
4920 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4921 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4922 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4923 makeArrayRef(TBLMask.data(), IndexLen)));
4926 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4929 static unsigned getDUPLANEOp(EVT EltType) {
4930 if (EltType == MVT::i8)
4931 return AArch64ISD::DUPLANE8;
4932 if (EltType == MVT::i16 || EltType == MVT::f16)
4933 return AArch64ISD::DUPLANE16;
4934 if (EltType == MVT::i32 || EltType == MVT::f32)
4935 return AArch64ISD::DUPLANE32;
4936 if (EltType == MVT::i64 || EltType == MVT::f64)
4937 return AArch64ISD::DUPLANE64;
4939 llvm_unreachable("Invalid vector element type?");
4942 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4943 SelectionDAG &DAG) const {
4945 EVT VT = Op.getValueType();
4947 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4949 // Convert shuffles that are directly supported on NEON to target-specific
4950 // DAG nodes, instead of keeping them as shuffles and matching them again
4951 // during code selection. This is more efficient and avoids the possibility
4952 // of inconsistencies between legalization and selection.
4953 ArrayRef<int> ShuffleMask = SVN->getMask();
4955 SDValue V1 = Op.getOperand(0);
4956 SDValue V2 = Op.getOperand(1);
4958 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4959 V1.getValueType().getSimpleVT())) {
4960 int Lane = SVN->getSplatIndex();
4961 // If this is undef splat, generate it via "just" vdup, if possible.
4965 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4966 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4968 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4969 // constant. If so, we can just reference the lane's definition directly.
4970 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4971 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4972 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4974 // Otherwise, duplicate from the lane of the input vector.
4975 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4977 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4978 // to make a vector of the same size as this SHUFFLE. We can ignore the
4979 // extract entirely, and canonicalise the concat using WidenVector.
4980 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4981 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4982 V1 = V1.getOperand(0);
4983 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4984 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4985 Lane -= Idx * VT.getVectorNumElements() / 2;
4986 V1 = WidenVector(V1.getOperand(Idx), DAG);
4987 } else if (VT.getSizeInBits() == 64)
4988 V1 = WidenVector(V1, DAG);
4990 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4993 if (isREVMask(ShuffleMask, VT, 64))
4994 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4995 if (isREVMask(ShuffleMask, VT, 32))
4996 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4997 if (isREVMask(ShuffleMask, VT, 16))
4998 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5000 bool ReverseEXT = false;
5002 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5005 Imm *= getExtFactor(V1);
5006 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5007 DAG.getConstant(Imm, MVT::i32));
5008 } else if (V2->getOpcode() == ISD::UNDEF &&
5009 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5010 Imm *= getExtFactor(V1);
5011 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5012 DAG.getConstant(Imm, MVT::i32));
5015 unsigned WhichResult;
5016 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5017 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5018 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5020 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5021 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5022 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5024 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5025 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5026 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5029 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5030 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5031 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5033 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5034 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5035 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5037 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5038 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5039 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5042 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5043 if (Concat.getNode())
5048 int NumInputElements = V1.getValueType().getVectorNumElements();
5049 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5050 SDValue DstVec = DstIsLeft ? V1 : V2;
5051 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5053 SDValue SrcVec = V1;
5054 int SrcLane = ShuffleMask[Anomaly];
5055 if (SrcLane >= NumInputElements) {
5057 SrcLane -= VT.getVectorNumElements();
5059 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5061 EVT ScalarVT = VT.getVectorElementType();
5063 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5064 ScalarVT = MVT::i32;
5067 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5068 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5072 // If the shuffle is not directly supported and it has 4 elements, use
5073 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5074 unsigned NumElts = VT.getVectorNumElements();
5076 unsigned PFIndexes[4];
5077 for (unsigned i = 0; i != 4; ++i) {
5078 if (ShuffleMask[i] < 0)
5081 PFIndexes[i] = ShuffleMask[i];
5084 // Compute the index in the perfect shuffle table.
5085 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5086 PFIndexes[2] * 9 + PFIndexes[3];
5087 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5088 unsigned Cost = (PFEntry >> 30);
5091 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5094 return GenerateTBL(Op, ShuffleMask, DAG);
5097 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5099 EVT VT = BVN->getValueType(0);
5100 APInt SplatBits, SplatUndef;
5101 unsigned SplatBitSize;
5103 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5104 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5106 for (unsigned i = 0; i < NumSplats; ++i) {
5107 CnstBits <<= SplatBitSize;
5108 UndefBits <<= SplatBitSize;
5109 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5110 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5119 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5120 SelectionDAG &DAG) const {
5121 BuildVectorSDNode *BVN =
5122 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5123 SDValue LHS = Op.getOperand(0);
5125 EVT VT = Op.getValueType();
5130 APInt CnstBits(VT.getSizeInBits(), 0);
5131 APInt UndefBits(VT.getSizeInBits(), 0);
5132 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5133 // We only have BIC vector immediate instruction, which is and-not.
5134 CnstBits = ~CnstBits;
5136 // We make use of a little bit of goto ickiness in order to avoid having to
5137 // duplicate the immediate matching logic for the undef toggled case.
5138 bool SecondTry = false;
5141 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5142 CnstBits = CnstBits.zextOrTrunc(64);
5143 uint64_t CnstVal = CnstBits.getZExtValue();
5145 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5146 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5147 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5148 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5149 DAG.getConstant(CnstVal, MVT::i32),
5150 DAG.getConstant(0, MVT::i32));
5151 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5154 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5155 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5156 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5157 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5158 DAG.getConstant(CnstVal, MVT::i32),
5159 DAG.getConstant(8, MVT::i32));
5160 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5163 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5164 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5165 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5166 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5167 DAG.getConstant(CnstVal, MVT::i32),
5168 DAG.getConstant(16, MVT::i32));
5169 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5172 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5173 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5174 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5175 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5176 DAG.getConstant(CnstVal, MVT::i32),
5177 DAG.getConstant(24, MVT::i32));
5178 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5181 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5182 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5183 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5184 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5185 DAG.getConstant(CnstVal, MVT::i32),
5186 DAG.getConstant(0, MVT::i32));
5187 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5190 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5191 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5192 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5193 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5194 DAG.getConstant(CnstVal, MVT::i32),
5195 DAG.getConstant(8, MVT::i32));
5196 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5203 CnstBits = ~UndefBits;
5207 // We can always fall back to a non-immediate AND.
5212 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5213 // consists of only the same constant int value, returned in reference arg
5215 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5216 uint64_t &ConstVal) {
5217 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5220 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5223 EVT VT = Bvec->getValueType(0);
5224 unsigned NumElts = VT.getVectorNumElements();
5225 for (unsigned i = 1; i < NumElts; ++i)
5226 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5228 ConstVal = FirstElt->getZExtValue();
5232 static unsigned getIntrinsicID(const SDNode *N) {
5233 unsigned Opcode = N->getOpcode();
5236 return Intrinsic::not_intrinsic;
5237 case ISD::INTRINSIC_WO_CHAIN: {
5238 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5239 if (IID < Intrinsic::num_intrinsics)
5241 return Intrinsic::not_intrinsic;
5246 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5247 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5248 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5249 // Also, logical shift right -> sri, with the same structure.
5250 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5251 EVT VT = N->getValueType(0);
5258 // Is the first op an AND?
5259 const SDValue And = N->getOperand(0);
5260 if (And.getOpcode() != ISD::AND)
5263 // Is the second op an shl or lshr?
5264 SDValue Shift = N->getOperand(1);
5265 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5266 // or AArch64ISD::VLSHR vector, #shift
5267 unsigned ShiftOpc = Shift.getOpcode();
5268 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5270 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5272 // Is the shift amount constant?
5273 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5277 // Is the and mask vector all constant?
5279 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5282 // Is C1 == ~C2, taking into account how much one can shift elements of a
5284 uint64_t C2 = C2node->getZExtValue();
5285 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5286 if (C2 > ElemSizeInBits)
5288 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5289 if ((C1 & ElemMask) != (~C2 & ElemMask))
5292 SDValue X = And.getOperand(0);
5293 SDValue Y = Shift.getOperand(0);
5296 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5298 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5299 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5301 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5302 DEBUG(N->dump(&DAG));
5303 DEBUG(dbgs() << "into: \n");
5304 DEBUG(ResultSLI->dump(&DAG));
5310 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5311 SelectionDAG &DAG) const {
5312 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5313 if (EnableAArch64SlrGeneration) {
5314 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5319 BuildVectorSDNode *BVN =
5320 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5321 SDValue LHS = Op.getOperand(1);
5323 EVT VT = Op.getValueType();
5325 // OR commutes, so try swapping the operands.
5327 LHS = Op.getOperand(0);
5328 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5333 APInt CnstBits(VT.getSizeInBits(), 0);
5334 APInt UndefBits(VT.getSizeInBits(), 0);
5335 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5336 // We make use of a little bit of goto ickiness in order to avoid having to
5337 // duplicate the immediate matching logic for the undef toggled case.
5338 bool SecondTry = false;
5341 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5342 CnstBits = CnstBits.zextOrTrunc(64);
5343 uint64_t CnstVal = CnstBits.getZExtValue();
5345 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5346 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5347 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5348 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5349 DAG.getConstant(CnstVal, MVT::i32),
5350 DAG.getConstant(0, MVT::i32));
5351 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5354 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5355 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5356 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5357 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5358 DAG.getConstant(CnstVal, MVT::i32),
5359 DAG.getConstant(8, MVT::i32));
5360 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5363 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5364 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5365 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5366 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5367 DAG.getConstant(CnstVal, MVT::i32),
5368 DAG.getConstant(16, MVT::i32));
5369 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5372 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5373 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5374 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5375 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5376 DAG.getConstant(CnstVal, MVT::i32),
5377 DAG.getConstant(24, MVT::i32));
5378 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5381 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5382 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5383 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5384 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5385 DAG.getConstant(CnstVal, MVT::i32),
5386 DAG.getConstant(0, MVT::i32));
5387 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5390 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5391 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5392 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5393 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5394 DAG.getConstant(CnstVal, MVT::i32),
5395 DAG.getConstant(8, MVT::i32));
5396 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5403 CnstBits = UndefBits;
5407 // We can always fall back to a non-immediate OR.
5412 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5413 // be truncated to fit element width.
5414 static SDValue NormalizeBuildVector(SDValue Op,
5415 SelectionDAG &DAG) {
5416 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5418 EVT VT = Op.getValueType();
5419 EVT EltTy= VT.getVectorElementType();
5421 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5424 SmallVector<SDValue, 16> Ops;
5425 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5426 SDValue Lane = Op.getOperand(I);
5427 if (Lane.getOpcode() == ISD::Constant) {
5428 APInt LowBits(EltTy.getSizeInBits(),
5429 cast<ConstantSDNode>(Lane)->getZExtValue());
5430 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5432 Ops.push_back(Lane);
5434 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5437 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5438 SelectionDAG &DAG) const {
5440 EVT VT = Op.getValueType();
5441 Op = NormalizeBuildVector(Op, DAG);
5442 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5444 APInt CnstBits(VT.getSizeInBits(), 0);
5445 APInt UndefBits(VT.getSizeInBits(), 0);
5446 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5447 // We make use of a little bit of goto ickiness in order to avoid having to
5448 // duplicate the immediate matching logic for the undef toggled case.
5449 bool SecondTry = false;
5452 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5453 CnstBits = CnstBits.zextOrTrunc(64);
5454 uint64_t CnstVal = CnstBits.getZExtValue();
5456 // Certain magic vector constants (used to express things like NOT
5457 // and NEG) are passed through unmodified. This allows codegen patterns
5458 // for these operations to match. Special-purpose patterns will lower
5459 // these immediates to MOVIs if it proves necessary.
5460 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5463 // The many faces of MOVI...
5464 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5465 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5466 if (VT.getSizeInBits() == 128) {
5467 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5468 DAG.getConstant(CnstVal, MVT::i32));
5469 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5472 // Support the V64 version via subregister insertion.
5473 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5474 DAG.getConstant(CnstVal, MVT::i32));
5475 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5478 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5479 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5480 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5481 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5482 DAG.getConstant(CnstVal, MVT::i32),
5483 DAG.getConstant(0, MVT::i32));
5484 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5487 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5488 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5489 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5490 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5491 DAG.getConstant(CnstVal, MVT::i32),
5492 DAG.getConstant(8, MVT::i32));
5493 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5496 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5497 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5498 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5499 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5500 DAG.getConstant(CnstVal, MVT::i32),
5501 DAG.getConstant(16, MVT::i32));
5502 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5505 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5506 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5507 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5508 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5509 DAG.getConstant(CnstVal, MVT::i32),
5510 DAG.getConstant(24, MVT::i32));
5511 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5514 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5515 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5516 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5517 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5518 DAG.getConstant(CnstVal, MVT::i32),
5519 DAG.getConstant(0, MVT::i32));
5520 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5523 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5524 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5525 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5526 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5527 DAG.getConstant(CnstVal, MVT::i32),
5528 DAG.getConstant(8, MVT::i32));
5529 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5532 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5533 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5534 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5535 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5536 DAG.getConstant(CnstVal, MVT::i32),
5537 DAG.getConstant(264, MVT::i32));
5538 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5541 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5542 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5543 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5544 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5545 DAG.getConstant(CnstVal, MVT::i32),
5546 DAG.getConstant(272, MVT::i32));
5547 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5550 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5551 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5552 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5553 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5554 DAG.getConstant(CnstVal, MVT::i32));
5555 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5558 // The few faces of FMOV...
5559 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5560 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5561 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5562 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5563 DAG.getConstant(CnstVal, MVT::i32));
5564 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5567 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5568 VT.getSizeInBits() == 128) {
5569 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5570 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5571 DAG.getConstant(CnstVal, MVT::i32));
5572 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5575 // The many faces of MVNI...
5577 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5578 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5579 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5580 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5581 DAG.getConstant(CnstVal, MVT::i32),
5582 DAG.getConstant(0, MVT::i32));
5583 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5586 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5587 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5588 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5589 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5590 DAG.getConstant(CnstVal, MVT::i32),
5591 DAG.getConstant(8, MVT::i32));
5592 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5595 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5596 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5597 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5598 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5599 DAG.getConstant(CnstVal, MVT::i32),
5600 DAG.getConstant(16, MVT::i32));
5601 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5604 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5605 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5606 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5607 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5608 DAG.getConstant(CnstVal, MVT::i32),
5609 DAG.getConstant(24, MVT::i32));
5610 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5613 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5614 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5615 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5616 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5617 DAG.getConstant(CnstVal, MVT::i32),
5618 DAG.getConstant(0, MVT::i32));
5619 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5622 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5623 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5624 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5625 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5626 DAG.getConstant(CnstVal, MVT::i32),
5627 DAG.getConstant(8, MVT::i32));
5628 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5631 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5632 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5633 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5634 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5635 DAG.getConstant(CnstVal, MVT::i32),
5636 DAG.getConstant(264, MVT::i32));
5637 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5640 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5641 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5642 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5643 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5644 DAG.getConstant(CnstVal, MVT::i32),
5645 DAG.getConstant(272, MVT::i32));
5646 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5653 CnstBits = UndefBits;
5658 // Scan through the operands to find some interesting properties we can
5660 // 1) If only one value is used, we can use a DUP, or
5661 // 2) if only the low element is not undef, we can just insert that, or
5662 // 3) if only one constant value is used (w/ some non-constant lanes),
5663 // we can splat the constant value into the whole vector then fill
5664 // in the non-constant lanes.
5665 // 4) FIXME: If different constant values are used, but we can intelligently
5666 // select the values we'll be overwriting for the non-constant
5667 // lanes such that we can directly materialize the vector
5668 // some other way (MOVI, e.g.), we can be sneaky.
5669 unsigned NumElts = VT.getVectorNumElements();
5670 bool isOnlyLowElement = true;
5671 bool usesOnlyOneValue = true;
5672 bool usesOnlyOneConstantValue = true;
5673 bool isConstant = true;
5674 unsigned NumConstantLanes = 0;
5676 SDValue ConstantValue;
5677 for (unsigned i = 0; i < NumElts; ++i) {
5678 SDValue V = Op.getOperand(i);
5679 if (V.getOpcode() == ISD::UNDEF)
5682 isOnlyLowElement = false;
5683 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5686 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5688 if (!ConstantValue.getNode())
5690 else if (ConstantValue != V)
5691 usesOnlyOneConstantValue = false;
5694 if (!Value.getNode())
5696 else if (V != Value)
5697 usesOnlyOneValue = false;
5700 if (!Value.getNode())
5701 return DAG.getUNDEF(VT);
5703 if (isOnlyLowElement)
5704 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5706 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5707 // i32 and try again.
5708 if (usesOnlyOneValue) {
5710 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5711 Value.getValueType() != VT)
5712 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5714 // This is actually a DUPLANExx operation, which keeps everything vectory.
5716 // DUPLANE works on 128-bit vectors, widen it if necessary.
5717 SDValue Lane = Value.getOperand(1);
5718 Value = Value.getOperand(0);
5719 if (Value.getValueType().getSizeInBits() == 64)
5720 Value = WidenVector(Value, DAG);
5722 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5723 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5726 if (VT.getVectorElementType().isFloatingPoint()) {
5727 SmallVector<SDValue, 8> Ops;
5729 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5730 for (unsigned i = 0; i < NumElts; ++i)
5731 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5732 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5733 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5734 Val = LowerBUILD_VECTOR(Val, DAG);
5736 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5740 // If there was only one constant value used and for more than one lane,
5741 // start by splatting that value, then replace the non-constant lanes. This
5742 // is better than the default, which will perform a separate initialization
5744 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5745 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5746 // Now insert the non-constant lanes.
5747 for (unsigned i = 0; i < NumElts; ++i) {
5748 SDValue V = Op.getOperand(i);
5749 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5750 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5751 // Note that type legalization likely mucked about with the VT of the
5752 // source operand, so we may have to convert it here before inserting.
5753 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5759 // If all elements are constants and the case above didn't get hit, fall back
5760 // to the default expansion, which will generate a load from the constant
5765 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5767 SDValue shuffle = ReconstructShuffle(Op, DAG);
5768 if (shuffle != SDValue())
5772 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5773 // know the default expansion would otherwise fall back on something even
5774 // worse. For a vector with one or two non-undef values, that's
5775 // scalar_to_vector for the elements followed by a shuffle (provided the
5776 // shuffle is valid for the target) and materialization element by element
5777 // on the stack followed by a load for everything else.
5778 if (!isConstant && !usesOnlyOneValue) {
5779 SDValue Vec = DAG.getUNDEF(VT);
5780 SDValue Op0 = Op.getOperand(0);
5781 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5783 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5784 // a) Avoid a RMW dependency on the full vector register, and
5785 // b) Allow the register coalescer to fold away the copy if the
5786 // value is already in an S or D register.
5787 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5788 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5790 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5791 DAG.getTargetConstant(SubIdx, MVT::i32));
5792 Vec = SDValue(N, 0);
5795 for (; i < NumElts; ++i) {
5796 SDValue V = Op.getOperand(i);
5797 if (V.getOpcode() == ISD::UNDEF)
5799 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5800 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5805 // Just use the default expansion. We failed to find a better alternative.
5809 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5810 SelectionDAG &DAG) const {
5811 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5813 // Check for non-constant or out of range lane.
5814 EVT VT = Op.getOperand(0).getValueType();
5815 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5816 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5820 // Insertion/extraction are legal for V128 types.
5821 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5822 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5826 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5827 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5830 // For V64 types, we perform insertion by expanding the value
5831 // to a V128 type and perform the insertion on that.
5833 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5834 EVT WideTy = WideVec.getValueType();
5836 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5837 Op.getOperand(1), Op.getOperand(2));
5838 // Re-narrow the resultant vector.
5839 return NarrowVector(Node, DAG);
5843 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5844 SelectionDAG &DAG) const {
5845 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5847 // Check for non-constant or out of range lane.
5848 EVT VT = Op.getOperand(0).getValueType();
5849 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5850 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5854 // Insertion/extraction are legal for V128 types.
5855 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5856 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5860 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5861 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5864 // For V64 types, we perform extraction by expanding the value
5865 // to a V128 type and perform the extraction on that.
5867 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5868 EVT WideTy = WideVec.getValueType();
5870 EVT ExtrTy = WideTy.getVectorElementType();
5871 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5874 // For extractions, we just return the result directly.
5875 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5879 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5880 SelectionDAG &DAG) const {
5881 EVT VT = Op.getOperand(0).getValueType();
5887 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5890 unsigned Val = Cst->getZExtValue();
5892 unsigned Size = Op.getValueType().getSizeInBits();
5896 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5899 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5902 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5905 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5908 llvm_unreachable("Unexpected vector type in extract_subvector!");
5911 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5913 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5919 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5921 if (VT.getVectorNumElements() == 4 &&
5922 (VT.is128BitVector() || VT.is64BitVector())) {
5923 unsigned PFIndexes[4];
5924 for (unsigned i = 0; i != 4; ++i) {
5928 PFIndexes[i] = M[i];
5931 // Compute the index in the perfect shuffle table.
5932 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5933 PFIndexes[2] * 9 + PFIndexes[3];
5934 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5935 unsigned Cost = (PFEntry >> 30);
5943 unsigned DummyUnsigned;
5945 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5946 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5947 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5948 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5949 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5950 isZIPMask(M, VT, DummyUnsigned) ||
5951 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5952 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5953 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5954 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5955 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5958 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5959 /// operand of a vector shift operation, where all the elements of the
5960 /// build_vector must have the same constant integer value.
5961 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5962 // Ignore bit_converts.
5963 while (Op.getOpcode() == ISD::BITCAST)
5964 Op = Op.getOperand(0);
5965 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5966 APInt SplatBits, SplatUndef;
5967 unsigned SplatBitSize;
5969 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5970 HasAnyUndefs, ElementBits) ||
5971 SplatBitSize > ElementBits)
5973 Cnt = SplatBits.getSExtValue();
5977 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5978 /// operand of a vector shift left operation. That value must be in the range:
5979 /// 0 <= Value < ElementBits for a left shift; or
5980 /// 0 <= Value <= ElementBits for a long left shift.
5981 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5982 assert(VT.isVector() && "vector shift count is not a vector type");
5983 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5984 if (!getVShiftImm(Op, ElementBits, Cnt))
5986 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5989 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5990 /// operand of a vector shift right operation. For a shift opcode, the value
5991 /// is positive, but for an intrinsic the value count must be negative. The
5992 /// absolute value must be in the range:
5993 /// 1 <= |Value| <= ElementBits for a right shift; or
5994 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5995 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5997 assert(VT.isVector() && "vector shift count is not a vector type");
5998 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5999 if (!getVShiftImm(Op, ElementBits, Cnt))
6003 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6006 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6007 SelectionDAG &DAG) const {
6008 EVT VT = Op.getValueType();
6012 if (!Op.getOperand(1).getValueType().isVector())
6014 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6016 switch (Op.getOpcode()) {
6018 llvm_unreachable("unexpected shift opcode");
6021 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6022 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6023 DAG.getConstant(Cnt, MVT::i32));
6024 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6025 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6026 Op.getOperand(0), Op.getOperand(1));
6029 // Right shift immediate
6030 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6033 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6034 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6035 DAG.getConstant(Cnt, MVT::i32));
6038 // Right shift register. Note, there is not a shift right register
6039 // instruction, but the shift left register instruction takes a signed
6040 // value, where negative numbers specify a right shift.
6041 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6042 : Intrinsic::aarch64_neon_ushl;
6043 // negate the shift amount
6044 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6045 SDValue NegShiftLeft =
6046 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6047 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6048 return NegShiftLeft;
6054 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6055 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6056 SDLoc dl, SelectionDAG &DAG) {
6057 EVT SrcVT = LHS.getValueType();
6059 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6060 APInt CnstBits(VT.getSizeInBits(), 0);
6061 APInt UndefBits(VT.getSizeInBits(), 0);
6062 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6063 bool IsZero = IsCnst && (CnstBits == 0);
6065 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6069 case AArch64CC::NE: {
6072 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6074 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6075 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6079 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6080 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6083 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6084 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6087 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6088 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6091 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6092 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6096 // If we ignore NaNs then we can use to the MI implementation.
6100 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6101 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6108 case AArch64CC::NE: {
6111 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6113 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6114 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6118 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6119 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6122 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6123 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6126 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6127 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6130 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6131 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6133 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6135 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6138 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6139 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6141 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6143 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6147 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6148 SelectionDAG &DAG) const {
6149 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6150 SDValue LHS = Op.getOperand(0);
6151 SDValue RHS = Op.getOperand(1);
6154 if (LHS.getValueType().getVectorElementType().isInteger()) {
6155 assert(LHS.getValueType() == RHS.getValueType());
6156 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6157 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
6161 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6162 LHS.getValueType().getVectorElementType() == MVT::f64);
6164 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6165 // clean. Some of them require two branches to implement.
6166 AArch64CC::CondCode CC1, CC2;
6168 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6170 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6172 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
6176 if (CC2 != AArch64CC::AL) {
6178 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
6179 if (!Cmp2.getNode())
6182 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
6186 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6191 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6192 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6193 /// specified in the intrinsic calls.
6194 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6196 unsigned Intrinsic) const {
6197 switch (Intrinsic) {
6198 case Intrinsic::aarch64_neon_ld2:
6199 case Intrinsic::aarch64_neon_ld3:
6200 case Intrinsic::aarch64_neon_ld4:
6201 case Intrinsic::aarch64_neon_ld1x2:
6202 case Intrinsic::aarch64_neon_ld1x3:
6203 case Intrinsic::aarch64_neon_ld1x4:
6204 case Intrinsic::aarch64_neon_ld2lane:
6205 case Intrinsic::aarch64_neon_ld3lane:
6206 case Intrinsic::aarch64_neon_ld4lane:
6207 case Intrinsic::aarch64_neon_ld2r:
6208 case Intrinsic::aarch64_neon_ld3r:
6209 case Intrinsic::aarch64_neon_ld4r: {
6210 Info.opc = ISD::INTRINSIC_W_CHAIN;
6211 // Conservatively set memVT to the entire set of vectors loaded.
6212 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6213 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6214 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6217 Info.vol = false; // volatile loads with NEON intrinsics not supported
6218 Info.readMem = true;
6219 Info.writeMem = false;
6222 case Intrinsic::aarch64_neon_st2:
6223 case Intrinsic::aarch64_neon_st3:
6224 case Intrinsic::aarch64_neon_st4:
6225 case Intrinsic::aarch64_neon_st1x2:
6226 case Intrinsic::aarch64_neon_st1x3:
6227 case Intrinsic::aarch64_neon_st1x4:
6228 case Intrinsic::aarch64_neon_st2lane:
6229 case Intrinsic::aarch64_neon_st3lane:
6230 case Intrinsic::aarch64_neon_st4lane: {
6231 Info.opc = ISD::INTRINSIC_VOID;
6232 // Conservatively set memVT to the entire set of vectors stored.
6233 unsigned NumElts = 0;
6234 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6235 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6236 if (!ArgTy->isVectorTy())
6238 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6240 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6241 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6244 Info.vol = false; // volatile stores with NEON intrinsics not supported
6245 Info.readMem = false;
6246 Info.writeMem = true;
6249 case Intrinsic::aarch64_ldaxr:
6250 case Intrinsic::aarch64_ldxr: {
6251 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6252 Info.opc = ISD::INTRINSIC_W_CHAIN;
6253 Info.memVT = MVT::getVT(PtrTy->getElementType());
6254 Info.ptrVal = I.getArgOperand(0);
6256 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6258 Info.readMem = true;
6259 Info.writeMem = false;
6262 case Intrinsic::aarch64_stlxr:
6263 case Intrinsic::aarch64_stxr: {
6264 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6265 Info.opc = ISD::INTRINSIC_W_CHAIN;
6266 Info.memVT = MVT::getVT(PtrTy->getElementType());
6267 Info.ptrVal = I.getArgOperand(1);
6269 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6271 Info.readMem = false;
6272 Info.writeMem = true;
6275 case Intrinsic::aarch64_ldaxp:
6276 case Intrinsic::aarch64_ldxp: {
6277 Info.opc = ISD::INTRINSIC_W_CHAIN;
6278 Info.memVT = MVT::i128;
6279 Info.ptrVal = I.getArgOperand(0);
6283 Info.readMem = true;
6284 Info.writeMem = false;
6287 case Intrinsic::aarch64_stlxp:
6288 case Intrinsic::aarch64_stxp: {
6289 Info.opc = ISD::INTRINSIC_W_CHAIN;
6290 Info.memVT = MVT::i128;
6291 Info.ptrVal = I.getArgOperand(2);
6295 Info.readMem = false;
6296 Info.writeMem = true;
6306 // Truncations from 64-bit GPR to 32-bit GPR is free.
6307 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6308 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6310 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6311 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6312 return NumBits1 > NumBits2;
6314 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6315 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6317 unsigned NumBits1 = VT1.getSizeInBits();
6318 unsigned NumBits2 = VT2.getSizeInBits();
6319 return NumBits1 > NumBits2;
6322 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6324 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6325 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6327 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6328 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6329 return NumBits1 == 32 && NumBits2 == 64;
6331 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6332 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6334 unsigned NumBits1 = VT1.getSizeInBits();
6335 unsigned NumBits2 = VT2.getSizeInBits();
6336 return NumBits1 == 32 && NumBits2 == 64;
6339 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6340 EVT VT1 = Val.getValueType();
6341 if (isZExtFree(VT1, VT2)) {
6345 if (Val.getOpcode() != ISD::LOAD)
6348 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6349 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6350 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6351 VT1.getSizeInBits() <= 32);
6354 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6355 unsigned &RequiredAligment) const {
6356 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6358 // Cyclone supports unaligned accesses.
6359 RequiredAligment = 0;
6360 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6361 return NumBits == 32 || NumBits == 64;
6364 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6365 unsigned &RequiredAligment) const {
6366 if (!LoadedType.isSimple() ||
6367 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6369 // Cyclone supports unaligned accesses.
6370 RequiredAligment = 0;
6371 unsigned NumBits = LoadedType.getSizeInBits();
6372 return NumBits == 32 || NumBits == 64;
6375 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6376 unsigned AlignCheck) {
6377 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6378 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6381 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6382 unsigned SrcAlign, bool IsMemset,
6385 MachineFunction &MF) const {
6386 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6387 // instruction to materialize the v2i64 zero and one store (with restrictive
6388 // addressing mode). Just do two i64 store of zero-registers.
6390 const Function *F = MF.getFunction();
6391 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6392 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6393 Attribute::NoImplicitFloat) &&
6394 (memOpAlign(SrcAlign, DstAlign, 16) ||
6395 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6398 return Size >= 8 ? MVT::i64 : MVT::i32;
6401 // 12-bit optionally shifted immediates are legal for adds.
6402 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6403 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6408 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6409 // immediates is the same as for an add or a sub.
6410 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6413 return isLegalAddImmediate(Immed);
6416 /// isLegalAddressingMode - Return true if the addressing mode represented
6417 /// by AM is legal for this target, for a load/store of the specified type.
6418 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6420 // AArch64 has five basic addressing modes:
6422 // reg + 9-bit signed offset
6423 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6425 // reg + SIZE_IN_BYTES * reg
6427 // No global is ever allowed as a base.
6431 // No reg+reg+imm addressing.
6432 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6435 // check reg + imm case:
6436 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6437 uint64_t NumBytes = 0;
6438 if (Ty->isSized()) {
6439 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6440 NumBytes = NumBits / 8;
6441 if (!isPowerOf2_64(NumBits))
6446 int64_t Offset = AM.BaseOffs;
6448 // 9-bit signed offset
6449 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6452 // 12-bit unsigned offset
6453 unsigned shift = Log2_64(NumBytes);
6454 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6455 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6456 (Offset >> shift) << shift == Offset)
6461 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6463 if (!AM.Scale || AM.Scale == 1 ||
6464 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6469 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6471 // Scaling factors are not free at all.
6472 // Operands | Rt Latency
6473 // -------------------------------------------
6475 // -------------------------------------------
6476 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6477 // Rt, [Xn, Wm, <extend> #imm] |
6478 if (isLegalAddressingMode(AM, Ty))
6479 // Scale represents reg2 * scale, thus account for 1 if
6480 // it is not equal to 0 or 1.
6481 return AM.Scale != 0 && AM.Scale != 1;
6485 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6486 VT = VT.getScalarType();
6491 switch (VT.getSimpleVT().SimpleTy) {
6503 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6504 // LR is a callee-save register, but we must treat it as clobbered by any call
6505 // site. Hence we include LR in the scratch registers, which are in turn added
6506 // as implicit-defs for stackmaps and patchpoints.
6507 static const MCPhysReg ScratchRegs[] = {
6508 AArch64::X16, AArch64::X17, AArch64::LR, 0
6514 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6515 EVT VT = N->getValueType(0);
6516 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6517 // it with shift to let it be lowered to UBFX.
6518 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6519 isa<ConstantSDNode>(N->getOperand(1))) {
6520 uint64_t TruncMask = N->getConstantOperandVal(1);
6521 if (isMask_64(TruncMask) &&
6522 N->getOperand(0).getOpcode() == ISD::SRL &&
6523 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6529 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6531 assert(Ty->isIntegerTy());
6533 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6537 int64_t Val = Imm.getSExtValue();
6538 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6541 if ((int64_t)Val < 0)
6544 Val &= (1LL << 32) - 1;
6546 unsigned LZ = countLeadingZeros((uint64_t)Val);
6547 unsigned Shift = (63 - LZ) / 16;
6548 // MOVZ is free so return true for one or fewer MOVK.
6549 return (Shift < 3) ? true : false;
6552 // Generate SUBS and CSEL for integer abs.
6553 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6554 EVT VT = N->getValueType(0);
6556 SDValue N0 = N->getOperand(0);
6557 SDValue N1 = N->getOperand(1);
6560 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6561 // and change it to SUB and CSEL.
6562 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6563 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6564 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6565 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6566 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6567 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6569 // Generate SUBS & CSEL.
6571 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6572 N0.getOperand(0), DAG.getConstant(0, VT));
6573 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6574 DAG.getConstant(AArch64CC::PL, MVT::i32),
6575 SDValue(Cmp.getNode(), 1));
6580 // performXorCombine - Attempts to handle integer ABS.
6581 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6582 TargetLowering::DAGCombinerInfo &DCI,
6583 const AArch64Subtarget *Subtarget) {
6584 if (DCI.isBeforeLegalizeOps())
6587 return performIntegerAbsCombine(N, DAG);
6591 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6593 std::vector<SDNode *> *Created) const {
6594 // fold (sdiv X, pow2)
6595 EVT VT = N->getValueType(0);
6596 if ((VT != MVT::i32 && VT != MVT::i64) ||
6597 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6601 SDValue N0 = N->getOperand(0);
6602 unsigned Lg2 = Divisor.countTrailingZeros();
6603 SDValue Zero = DAG.getConstant(0, VT);
6604 SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT);
6606 // Add (N0 < 0) ? Pow2 - 1 : 0;
6608 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6609 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6610 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6613 Created->push_back(Cmp.getNode());
6614 Created->push_back(Add.getNode());
6615 Created->push_back(CSel.getNode());
6620 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6622 // If we're dividing by a positive value, we're done. Otherwise, we must
6623 // negate the result.
6624 if (Divisor.isNonNegative())
6628 Created->push_back(SRA.getNode());
6629 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6632 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6633 TargetLowering::DAGCombinerInfo &DCI,
6634 const AArch64Subtarget *Subtarget) {
6635 if (DCI.isBeforeLegalizeOps())
6638 // Multiplication of a power of two plus/minus one can be done more
6639 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6640 // future CPUs have a cheaper MADD instruction, this may need to be
6641 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6642 // 64-bit is 5 cycles, so this is always a win.
6643 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6644 APInt Value = C->getAPIntValue();
6645 EVT VT = N->getValueType(0);
6646 if (Value.isNonNegative()) {
6647 // (mul x, 2^N + 1) => (add (shl x, N), x)
6648 APInt VM1 = Value - 1;
6649 if (VM1.isPowerOf2()) {
6650 SDValue ShiftedVal =
6651 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6652 DAG.getConstant(VM1.logBase2(), MVT::i64));
6653 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6656 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6657 APInt VP1 = Value + 1;
6658 if (VP1.isPowerOf2()) {
6659 SDValue ShiftedVal =
6660 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6661 DAG.getConstant(VP1.logBase2(), MVT::i64));
6662 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6666 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6667 APInt VNM1 = -Value - 1;
6668 if (VNM1.isPowerOf2()) {
6669 SDValue ShiftedVal =
6670 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6671 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6673 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6674 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6676 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6677 APInt VNP1 = -Value + 1;
6678 if (VNP1.isPowerOf2()) {
6679 SDValue ShiftedVal =
6680 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6681 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6682 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6690 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6691 SelectionDAG &DAG) {
6692 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6693 // optimize away operation when it's from a constant.
6695 // The general transformation is:
6696 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6697 // AND(VECTOR_CMP(x,y), constant2)
6698 // constant2 = UNARYOP(constant)
6700 // Early exit if this isn't a vector operation, the operand of the
6701 // unary operation isn't a bitwise AND, or if the sizes of the operations
6703 EVT VT = N->getValueType(0);
6704 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6705 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6706 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6709 // Now check that the other operand of the AND is a constant. We could
6710 // make the transformation for non-constant splats as well, but it's unclear
6711 // that would be a benefit as it would not eliminate any operations, just
6712 // perform one more step in scalar code before moving to the vector unit.
6713 if (BuildVectorSDNode *BV =
6714 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6715 // Bail out if the vector isn't a constant.
6716 if (!BV->isConstant())
6719 // Everything checks out. Build up the new and improved node.
6721 EVT IntVT = BV->getValueType(0);
6722 // Create a new constant of the appropriate type for the transformed
6724 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6725 // The AND node needs bitcasts to/from an integer vector type around it.
6726 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6727 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6728 N->getOperand(0)->getOperand(0), MaskConst);
6729 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6736 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6737 // First try to optimize away the conversion when it's conditionally from
6738 // a constant. Vectors only.
6739 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6740 if (Res != SDValue())
6743 EVT VT = N->getValueType(0);
6744 if (VT != MVT::f32 && VT != MVT::f64)
6747 // Only optimize when the source and destination types have the same width.
6748 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6751 // If the result of an integer load is only used by an integer-to-float
6752 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6753 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6754 SDValue N0 = N->getOperand(0);
6755 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6756 // Do not change the width of a volatile load.
6757 !cast<LoadSDNode>(N0)->isVolatile()) {
6758 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6759 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6760 LN0->getPointerInfo(), LN0->isVolatile(),
6761 LN0->isNonTemporal(), LN0->isInvariant(),
6762 LN0->getAlignment());
6764 // Make sure successors of the original load stay after it by updating them
6765 // to use the new Chain.
6766 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6769 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6770 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6776 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6777 /// searches for and classifies those shifts.
6778 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6780 if (N.getOpcode() == ISD::SHL)
6782 else if (N.getOpcode() == ISD::SRL)
6787 if (!isa<ConstantSDNode>(N.getOperand(1)))
6790 ShiftAmount = N->getConstantOperandVal(1);
6791 Src = N->getOperand(0);
6795 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6796 /// registers viewed as a high/low pair. This function looks for the pattern:
6797 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6798 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6800 static SDValue tryCombineToEXTR(SDNode *N,
6801 TargetLowering::DAGCombinerInfo &DCI) {
6802 SelectionDAG &DAG = DCI.DAG;
6804 EVT VT = N->getValueType(0);
6806 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6808 if (VT != MVT::i32 && VT != MVT::i64)
6812 uint32_t ShiftLHS = 0;
6814 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6818 uint32_t ShiftRHS = 0;
6820 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6823 // If they're both trying to come from the high part of the register, they're
6824 // not really an EXTR.
6825 if (LHSFromHi == RHSFromHi)
6828 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6832 std::swap(LHS, RHS);
6833 std::swap(ShiftLHS, ShiftRHS);
6836 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6837 DAG.getConstant(ShiftRHS, MVT::i64));
6840 static SDValue tryCombineToBSL(SDNode *N,
6841 TargetLowering::DAGCombinerInfo &DCI) {
6842 EVT VT = N->getValueType(0);
6843 SelectionDAG &DAG = DCI.DAG;
6849 SDValue N0 = N->getOperand(0);
6850 if (N0.getOpcode() != ISD::AND)
6853 SDValue N1 = N->getOperand(1);
6854 if (N1.getOpcode() != ISD::AND)
6857 // We only have to look for constant vectors here since the general, variable
6858 // case can be handled in TableGen.
6859 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6860 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6861 for (int i = 1; i >= 0; --i)
6862 for (int j = 1; j >= 0; --j) {
6863 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6864 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6868 bool FoundMatch = true;
6869 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6870 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6871 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6873 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6880 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6881 N0->getOperand(1 - i), N1->getOperand(1 - j));
6887 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6888 const AArch64Subtarget *Subtarget) {
6889 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6890 if (!EnableAArch64ExtrGeneration)
6892 SelectionDAG &DAG = DCI.DAG;
6893 EVT VT = N->getValueType(0);
6895 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6898 SDValue Res = tryCombineToEXTR(N, DCI);
6902 Res = tryCombineToBSL(N, DCI);
6909 static SDValue performBitcastCombine(SDNode *N,
6910 TargetLowering::DAGCombinerInfo &DCI,
6911 SelectionDAG &DAG) {
6912 // Wait 'til after everything is legalized to try this. That way we have
6913 // legal vector types and such.
6914 if (DCI.isBeforeLegalizeOps())
6917 // Remove extraneous bitcasts around an extract_subvector.
6919 // (v4i16 (bitconvert
6920 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6922 // (extract_subvector ((v8i16 ...), (i64 4)))
6924 // Only interested in 64-bit vectors as the ultimate result.
6925 EVT VT = N->getValueType(0);
6928 if (VT.getSimpleVT().getSizeInBits() != 64)
6930 // Is the operand an extract_subvector starting at the beginning or halfway
6931 // point of the vector? A low half may also come through as an
6932 // EXTRACT_SUBREG, so look for that, too.
6933 SDValue Op0 = N->getOperand(0);
6934 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6935 !(Op0->isMachineOpcode() &&
6936 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6938 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6939 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6940 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6942 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6943 if (idx != AArch64::dsub)
6945 // The dsub reference is equivalent to a lane zero subvector reference.
6948 // Look through the bitcast of the input to the extract.
6949 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6951 SDValue Source = Op0->getOperand(0)->getOperand(0);
6952 // If the source type has twice the number of elements as our destination
6953 // type, we know this is an extract of the high or low half of the vector.
6954 EVT SVT = Source->getValueType(0);
6955 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6958 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6960 // Create the simplified form to just extract the low or high half of the
6961 // vector directly rather than bothering with the bitcasts.
6963 unsigned NumElements = VT.getVectorNumElements();
6965 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6966 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6968 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6969 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6975 static SDValue performConcatVectorsCombine(SDNode *N,
6976 TargetLowering::DAGCombinerInfo &DCI,
6977 SelectionDAG &DAG) {
6978 // Wait 'til after everything is legalized to try this. That way we have
6979 // legal vector types and such.
6980 if (DCI.isBeforeLegalizeOps())
6984 EVT VT = N->getValueType(0);
6986 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6987 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6988 // canonicalise to that.
6989 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6990 assert(VT.getVectorElementType().getSizeInBits() == 64);
6991 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6992 WidenVector(N->getOperand(0), DAG),
6993 DAG.getConstant(0, MVT::i64));
6996 // Canonicalise concat_vectors so that the right-hand vector has as few
6997 // bit-casts as possible before its real operation. The primary matching
6998 // destination for these operations will be the narrowing "2" instructions,
6999 // which depend on the operation being performed on this right-hand vector.
7001 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7003 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7005 SDValue Op1 = N->getOperand(1);
7006 if (Op1->getOpcode() != ISD::BITCAST)
7008 SDValue RHS = Op1->getOperand(0);
7009 MVT RHSTy = RHS.getValueType().getSimpleVT();
7010 // If the RHS is not a vector, this is not the pattern we're looking for.
7011 if (!RHSTy.isVector())
7014 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7016 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7017 RHSTy.getVectorNumElements() * 2);
7019 ISD::BITCAST, dl, VT,
7020 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7021 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
7024 static SDValue tryCombineFixedPointConvert(SDNode *N,
7025 TargetLowering::DAGCombinerInfo &DCI,
7026 SelectionDAG &DAG) {
7027 // Wait 'til after everything is legalized to try this. That way we have
7028 // legal vector types and such.
7029 if (DCI.isBeforeLegalizeOps())
7031 // Transform a scalar conversion of a value from a lane extract into a
7032 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7033 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7034 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7036 // The second form interacts better with instruction selection and the
7037 // register allocator to avoid cross-class register copies that aren't
7038 // coalescable due to a lane reference.
7040 // Check the operand and see if it originates from a lane extract.
7041 SDValue Op1 = N->getOperand(1);
7042 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7043 // Yep, no additional predication needed. Perform the transform.
7044 SDValue IID = N->getOperand(0);
7045 SDValue Shift = N->getOperand(2);
7046 SDValue Vec = Op1.getOperand(0);
7047 SDValue Lane = Op1.getOperand(1);
7048 EVT ResTy = N->getValueType(0);
7052 // The vector width should be 128 bits by the time we get here, even
7053 // if it started as 64 bits (the extract_vector handling will have
7055 assert(Vec.getValueType().getSizeInBits() == 128 &&
7056 "unexpected vector size on extract_vector_elt!");
7057 if (Vec.getValueType() == MVT::v4i32)
7058 VecResTy = MVT::v4f32;
7059 else if (Vec.getValueType() == MVT::v2i64)
7060 VecResTy = MVT::v2f64;
7062 llvm_unreachable("unexpected vector type!");
7065 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7066 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7071 // AArch64 high-vector "long" operations are formed by performing the non-high
7072 // version on an extract_subvector of each operand which gets the high half:
7074 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7076 // However, there are cases which don't have an extract_high explicitly, but
7077 // have another operation that can be made compatible with one for free. For
7080 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7082 // This routine does the actual conversion of such DUPs, once outer routines
7083 // have determined that everything else is in order.
7084 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7085 // We can handle most types of duplicate, but the lane ones have an extra
7086 // operand saying *which* lane, so we need to know.
7088 switch (N.getOpcode()) {
7089 case AArch64ISD::DUP:
7092 case AArch64ISD::DUPLANE8:
7093 case AArch64ISD::DUPLANE16:
7094 case AArch64ISD::DUPLANE32:
7095 case AArch64ISD::DUPLANE64:
7102 MVT NarrowTy = N.getSimpleValueType();
7103 if (!NarrowTy.is64BitVector())
7106 MVT ElementTy = NarrowTy.getVectorElementType();
7107 unsigned NumElems = NarrowTy.getVectorNumElements();
7108 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7112 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7115 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7117 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7118 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7121 static bool isEssentiallyExtractSubvector(SDValue N) {
7122 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7125 return N.getOpcode() == ISD::BITCAST &&
7126 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7129 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7130 struct GenericSetCCInfo {
7131 const SDValue *Opnd0;
7132 const SDValue *Opnd1;
7136 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7137 struct AArch64SetCCInfo {
7139 AArch64CC::CondCode CC;
7142 /// \brief Helper structure to keep track of SetCC information.
7144 GenericSetCCInfo Generic;
7145 AArch64SetCCInfo AArch64;
7148 /// \brief Helper structure to be able to read SetCC information. If set to
7149 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7150 /// GenericSetCCInfo.
7151 struct SetCCInfoAndKind {
7156 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7158 /// AArch64 lowered one.
7159 /// \p SetCCInfo is filled accordingly.
7160 /// \post SetCCInfo is meanginfull only when this function returns true.
7161 /// \return True when Op is a kind of SET_CC operation.
7162 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7163 // If this is a setcc, this is straight forward.
7164 if (Op.getOpcode() == ISD::SETCC) {
7165 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7166 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7167 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7168 SetCCInfo.IsAArch64 = false;
7171 // Otherwise, check if this is a matching csel instruction.
7175 if (Op.getOpcode() != AArch64ISD::CSEL)
7177 // Set the information about the operands.
7178 // TODO: we want the operands of the Cmp not the csel
7179 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7180 SetCCInfo.IsAArch64 = true;
7181 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7182 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7184 // Check that the operands matches the constraints:
7185 // (1) Both operands must be constants.
7186 // (2) One must be 1 and the other must be 0.
7187 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7188 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7191 if (!TValue || !FValue)
7195 if (!TValue->isOne()) {
7196 // Update the comparison when we are interested in !cc.
7197 std::swap(TValue, FValue);
7198 SetCCInfo.Info.AArch64.CC =
7199 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7201 return TValue->isOne() && FValue->isNullValue();
7204 // Returns true if Op is setcc or zext of setcc.
7205 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7206 if (isSetCC(Op, Info))
7208 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7209 isSetCC(Op->getOperand(0), Info));
7212 // The folding we want to perform is:
7213 // (add x, [zext] (setcc cc ...) )
7215 // (csel x, (add x, 1), !cc ...)
7217 // The latter will get matched to a CSINC instruction.
7218 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7219 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7220 SDValue LHS = Op->getOperand(0);
7221 SDValue RHS = Op->getOperand(1);
7222 SetCCInfoAndKind InfoAndKind;
7224 // If neither operand is a SET_CC, give up.
7225 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7226 std::swap(LHS, RHS);
7227 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7231 // FIXME: This could be generatized to work for FP comparisons.
7232 EVT CmpVT = InfoAndKind.IsAArch64
7233 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7234 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7235 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7241 if (InfoAndKind.IsAArch64) {
7242 CCVal = DAG.getConstant(
7243 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7244 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7246 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7247 *InfoAndKind.Info.Generic.Opnd1,
7248 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7251 EVT VT = Op->getValueType(0);
7252 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7253 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7256 // The basic add/sub long vector instructions have variants with "2" on the end
7257 // which act on the high-half of their inputs. They are normally matched by
7260 // (add (zeroext (extract_high LHS)),
7261 // (zeroext (extract_high RHS)))
7262 // -> uaddl2 vD, vN, vM
7264 // However, if one of the extracts is something like a duplicate, this
7265 // instruction can still be used profitably. This function puts the DAG into a
7266 // more appropriate form for those patterns to trigger.
7267 static SDValue performAddSubLongCombine(SDNode *N,
7268 TargetLowering::DAGCombinerInfo &DCI,
7269 SelectionDAG &DAG) {
7270 if (DCI.isBeforeLegalizeOps())
7273 MVT VT = N->getSimpleValueType(0);
7274 if (!VT.is128BitVector()) {
7275 if (N->getOpcode() == ISD::ADD)
7276 return performSetccAddFolding(N, DAG);
7280 // Make sure both branches are extended in the same way.
7281 SDValue LHS = N->getOperand(0);
7282 SDValue RHS = N->getOperand(1);
7283 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7284 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7285 LHS.getOpcode() != RHS.getOpcode())
7288 unsigned ExtType = LHS.getOpcode();
7290 // It's not worth doing if at least one of the inputs isn't already an
7291 // extract, but we don't know which it'll be so we have to try both.
7292 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7293 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7297 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7298 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7299 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7303 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7306 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7309 // Massage DAGs which we can use the high-half "long" operations on into
7310 // something isel will recognize better. E.g.
7312 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7313 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7314 // (extract_high (v2i64 (dup128 scalar)))))
7316 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7317 TargetLowering::DAGCombinerInfo &DCI,
7318 SelectionDAG &DAG) {
7319 if (DCI.isBeforeLegalizeOps())
7322 SDValue LHS = N->getOperand(1);
7323 SDValue RHS = N->getOperand(2);
7324 assert(LHS.getValueType().is64BitVector() &&
7325 RHS.getValueType().is64BitVector() &&
7326 "unexpected shape for long operation");
7328 // Either node could be a DUP, but it's not worth doing both of them (you'd
7329 // just as well use the non-high version) so look for a corresponding extract
7330 // operation on the other "wing".
7331 if (isEssentiallyExtractSubvector(LHS)) {
7332 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7335 } else if (isEssentiallyExtractSubvector(RHS)) {
7336 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7341 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7342 N->getOperand(0), LHS, RHS);
7345 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7346 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7347 unsigned ElemBits = ElemTy.getSizeInBits();
7349 int64_t ShiftAmount;
7350 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7351 APInt SplatValue, SplatUndef;
7352 unsigned SplatBitSize;
7354 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7355 HasAnyUndefs, ElemBits) ||
7356 SplatBitSize != ElemBits)
7359 ShiftAmount = SplatValue.getSExtValue();
7360 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7361 ShiftAmount = CVN->getSExtValue();
7369 llvm_unreachable("Unknown shift intrinsic");
7370 case Intrinsic::aarch64_neon_sqshl:
7371 Opcode = AArch64ISD::SQSHL_I;
7372 IsRightShift = false;
7374 case Intrinsic::aarch64_neon_uqshl:
7375 Opcode = AArch64ISD::UQSHL_I;
7376 IsRightShift = false;
7378 case Intrinsic::aarch64_neon_srshl:
7379 Opcode = AArch64ISD::SRSHR_I;
7380 IsRightShift = true;
7382 case Intrinsic::aarch64_neon_urshl:
7383 Opcode = AArch64ISD::URSHR_I;
7384 IsRightShift = true;
7386 case Intrinsic::aarch64_neon_sqshlu:
7387 Opcode = AArch64ISD::SQSHLU_I;
7388 IsRightShift = false;
7392 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7393 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7394 DAG.getConstant(-ShiftAmount, MVT::i32));
7395 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7396 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7397 DAG.getConstant(ShiftAmount, MVT::i32));
7402 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7403 // the intrinsics must be legal and take an i32, this means there's almost
7404 // certainly going to be a zext in the DAG which we can eliminate.
7405 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7406 SDValue AndN = N->getOperand(2);
7407 if (AndN.getOpcode() != ISD::AND)
7410 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7411 if (!CMask || CMask->getZExtValue() != Mask)
7414 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7415 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7418 static SDValue performIntrinsicCombine(SDNode *N,
7419 TargetLowering::DAGCombinerInfo &DCI,
7420 const AArch64Subtarget *Subtarget) {
7421 SelectionDAG &DAG = DCI.DAG;
7422 unsigned IID = getIntrinsicID(N);
7426 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7427 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7428 return tryCombineFixedPointConvert(N, DCI, DAG);
7430 case Intrinsic::aarch64_neon_fmax:
7431 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7432 N->getOperand(1), N->getOperand(2));
7433 case Intrinsic::aarch64_neon_fmin:
7434 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7435 N->getOperand(1), N->getOperand(2));
7436 case Intrinsic::aarch64_neon_smull:
7437 case Intrinsic::aarch64_neon_umull:
7438 case Intrinsic::aarch64_neon_pmull:
7439 case Intrinsic::aarch64_neon_sqdmull:
7440 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7441 case Intrinsic::aarch64_neon_sqshl:
7442 case Intrinsic::aarch64_neon_uqshl:
7443 case Intrinsic::aarch64_neon_sqshlu:
7444 case Intrinsic::aarch64_neon_srshl:
7445 case Intrinsic::aarch64_neon_urshl:
7446 return tryCombineShiftImm(IID, N, DAG);
7447 case Intrinsic::aarch64_crc32b:
7448 case Intrinsic::aarch64_crc32cb:
7449 return tryCombineCRC32(0xff, N, DAG);
7450 case Intrinsic::aarch64_crc32h:
7451 case Intrinsic::aarch64_crc32ch:
7452 return tryCombineCRC32(0xffff, N, DAG);
7457 static SDValue performExtendCombine(SDNode *N,
7458 TargetLowering::DAGCombinerInfo &DCI,
7459 SelectionDAG &DAG) {
7460 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7461 // we can convert that DUP into another extract_high (of a bigger DUP), which
7462 // helps the backend to decide that an sabdl2 would be useful, saving a real
7463 // extract_high operation.
7464 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7465 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7466 SDNode *ABDNode = N->getOperand(0).getNode();
7467 unsigned IID = getIntrinsicID(ABDNode);
7468 if (IID == Intrinsic::aarch64_neon_sabd ||
7469 IID == Intrinsic::aarch64_neon_uabd) {
7470 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7471 if (!NewABD.getNode())
7474 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7479 // This is effectively a custom type legalization for AArch64.
7481 // Type legalization will split an extend of a small, legal, type to a larger
7482 // illegal type by first splitting the destination type, often creating
7483 // illegal source types, which then get legalized in isel-confusing ways,
7484 // leading to really terrible codegen. E.g.,
7485 // %result = v8i32 sext v8i8 %value
7487 // %losrc = extract_subreg %value, ...
7488 // %hisrc = extract_subreg %value, ...
7489 // %lo = v4i32 sext v4i8 %losrc
7490 // %hi = v4i32 sext v4i8 %hisrc
7491 // Things go rapidly downhill from there.
7493 // For AArch64, the [sz]ext vector instructions can only go up one element
7494 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7495 // take two instructions.
7497 // This implies that the most efficient way to do the extend from v8i8
7498 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7499 // the normal splitting to happen for the v8i16->v8i32.
7501 // This is pre-legalization to catch some cases where the default
7502 // type legalization will create ill-tempered code.
7503 if (!DCI.isBeforeLegalizeOps())
7506 // We're only interested in cleaning things up for non-legal vector types
7507 // here. If both the source and destination are legal, things will just
7508 // work naturally without any fiddling.
7509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7510 EVT ResVT = N->getValueType(0);
7511 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7513 // If the vector type isn't a simple VT, it's beyond the scope of what
7514 // we're worried about here. Let legalization do its thing and hope for
7516 SDValue Src = N->getOperand(0);
7517 EVT SrcVT = Src->getValueType(0);
7518 if (!ResVT.isSimple() || !SrcVT.isSimple())
7521 // If the source VT is a 64-bit vector, we can play games and get the
7522 // better results we want.
7523 if (SrcVT.getSizeInBits() != 64)
7526 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7527 unsigned ElementCount = SrcVT.getVectorNumElements();
7528 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7530 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7532 // Now split the rest of the operation into two halves, each with a 64
7536 unsigned NumElements = ResVT.getVectorNumElements();
7537 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7538 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7539 ResVT.getVectorElementType(), NumElements / 2);
7541 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7542 LoVT.getVectorNumElements());
7543 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7544 DAG.getIntPtrConstant(0));
7545 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7546 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7547 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7548 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7550 // Now combine the parts back together so we still have a single result
7551 // like the combiner expects.
7552 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7555 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7556 /// value. The load store optimizer pass will merge them to store pair stores.
7557 /// This has better performance than a splat of the scalar followed by a split
7558 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7559 /// followed by an ext.b and two stores.
7560 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7561 SDValue StVal = St->getValue();
7562 EVT VT = StVal.getValueType();
7564 // Don't replace floating point stores, they possibly won't be transformed to
7565 // stp because of the store pair suppress pass.
7566 if (VT.isFloatingPoint())
7569 // Check for insert vector elements.
7570 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7573 // We can express a splat as store pair(s) for 2 or 4 elements.
7574 unsigned NumVecElts = VT.getVectorNumElements();
7575 if (NumVecElts != 4 && NumVecElts != 2)
7577 SDValue SplatVal = StVal.getOperand(1);
7578 unsigned RemainInsertElts = NumVecElts - 1;
7580 // Check that this is a splat.
7581 while (--RemainInsertElts) {
7582 SDValue NextInsertElt = StVal.getOperand(0);
7583 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7585 if (NextInsertElt.getOperand(1) != SplatVal)
7587 StVal = NextInsertElt;
7589 unsigned OrigAlignment = St->getAlignment();
7590 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7591 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7593 // Create scalar stores. This is at least as good as the code sequence for a
7594 // split unaligned store wich is a dup.s, ext.b, and two stores.
7595 // Most of the time the three stores should be replaced by store pair
7596 // instructions (stp).
7598 SDValue BasePtr = St->getBasePtr();
7600 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7601 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7603 unsigned Offset = EltOffset;
7604 while (--NumVecElts) {
7605 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7606 DAG.getConstant(Offset, MVT::i64));
7607 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7608 St->getPointerInfo(), St->isVolatile(),
7609 St->isNonTemporal(), Alignment);
7610 Offset += EltOffset;
7615 static SDValue performSTORECombine(SDNode *N,
7616 TargetLowering::DAGCombinerInfo &DCI,
7618 const AArch64Subtarget *Subtarget) {
7619 if (!DCI.isBeforeLegalize())
7622 StoreSDNode *S = cast<StoreSDNode>(N);
7623 if (S->isVolatile())
7626 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7627 // page boundries. We want to split such stores.
7628 if (!Subtarget->isCyclone())
7631 // Don't split at Oz.
7632 MachineFunction &MF = DAG.getMachineFunction();
7633 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7634 AttributeSet::FunctionIndex, Attribute::MinSize);
7638 SDValue StVal = S->getValue();
7639 EVT VT = StVal.getValueType();
7641 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7642 // those up regresses performance on micro-benchmarks and olden/bh.
7643 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7646 // Split unaligned 16B stores. They are terrible for performance.
7647 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7648 // extensions can use this to mark that it does not want splitting to happen
7649 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7650 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7651 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7652 S->getAlignment() <= 2)
7655 // If we get a splat of a scalar convert this vector store to a store of
7656 // scalars. They will be merged into store pairs thereby removing two
7658 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7659 if (ReplacedSplat != SDValue())
7660 return ReplacedSplat;
7663 unsigned NumElts = VT.getVectorNumElements() / 2;
7664 // Split VT into two.
7666 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7667 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7668 DAG.getIntPtrConstant(0));
7669 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7670 DAG.getIntPtrConstant(NumElts));
7671 SDValue BasePtr = S->getBasePtr();
7673 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7674 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7675 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7676 DAG.getConstant(8, MVT::i64));
7677 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7678 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7682 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7683 /// post-increment LD1R.
7684 static SDValue performPostLD1Combine(SDNode *N,
7685 TargetLowering::DAGCombinerInfo &DCI,
7687 if (DCI.isBeforeLegalizeOps())
7690 SelectionDAG &DAG = DCI.DAG;
7691 EVT VT = N->getValueType(0);
7693 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7694 SDNode *LD = N->getOperand(LoadIdx).getNode();
7695 // If it is not LOAD, can not do such combine.
7696 if (LD->getOpcode() != ISD::LOAD)
7699 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7700 EVT MemVT = LoadSDN->getMemoryVT();
7701 // Check if memory operand is the same type as the vector element.
7702 if (MemVT != VT.getVectorElementType())
7705 // Check if there are other uses. If so, do not combine as it will introduce
7707 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7709 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7715 SDValue Addr = LD->getOperand(1);
7716 SDValue Vector = N->getOperand(0);
7717 // Search for a use of the address operand that is an increment.
7718 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7719 Addr.getNode()->use_end(); UI != UE; ++UI) {
7721 if (User->getOpcode() != ISD::ADD
7722 || UI.getUse().getResNo() != Addr.getResNo())
7725 // Check that the add is independent of the load. Otherwise, folding it
7726 // would create a cycle.
7727 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7729 // Also check that add is not used in the vector operand. This would also
7731 if (User->isPredecessorOf(Vector.getNode()))
7734 // If the increment is a constant, it must match the memory ref size.
7735 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7736 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7737 uint32_t IncVal = CInc->getZExtValue();
7738 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7739 if (IncVal != NumBytes)
7741 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7744 SmallVector<SDValue, 8> Ops;
7745 Ops.push_back(LD->getOperand(0)); // Chain
7747 Ops.push_back(Vector); // The vector to be inserted
7748 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7750 Ops.push_back(Addr);
7753 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7754 SDVTList SDTys = DAG.getVTList(Tys);
7755 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7756 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7758 LoadSDN->getMemOperand());
7761 std::vector<SDValue> NewResults;
7762 NewResults.push_back(SDValue(LD, 0)); // The result of load
7763 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7764 DCI.CombineTo(LD, NewResults);
7765 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7766 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7773 /// Target-specific DAG combine function for NEON load/store intrinsics
7774 /// to merge base address updates.
7775 static SDValue performNEONPostLDSTCombine(SDNode *N,
7776 TargetLowering::DAGCombinerInfo &DCI,
7777 SelectionDAG &DAG) {
7778 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7781 unsigned AddrOpIdx = N->getNumOperands() - 1;
7782 SDValue Addr = N->getOperand(AddrOpIdx);
7784 // Search for a use of the address operand that is an increment.
7785 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7786 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7788 if (User->getOpcode() != ISD::ADD ||
7789 UI.getUse().getResNo() != Addr.getResNo())
7792 // Check that the add is independent of the load/store. Otherwise, folding
7793 // it would create a cycle.
7794 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7797 // Find the new opcode for the updating load/store.
7798 bool IsStore = false;
7799 bool IsLaneOp = false;
7800 bool IsDupOp = false;
7801 unsigned NewOpc = 0;
7802 unsigned NumVecs = 0;
7803 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7805 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7806 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7808 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7810 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7812 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7813 NumVecs = 2; IsStore = true; break;
7814 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7815 NumVecs = 3; IsStore = true; break;
7816 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7817 NumVecs = 4; IsStore = true; break;
7818 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7820 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7822 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7824 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7825 NumVecs = 2; IsStore = true; break;
7826 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7827 NumVecs = 3; IsStore = true; break;
7828 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7829 NumVecs = 4; IsStore = true; break;
7830 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7831 NumVecs = 2; IsDupOp = true; break;
7832 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7833 NumVecs = 3; IsDupOp = true; break;
7834 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7835 NumVecs = 4; IsDupOp = true; break;
7836 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7837 NumVecs = 2; IsLaneOp = true; break;
7838 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7839 NumVecs = 3; IsLaneOp = true; break;
7840 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7841 NumVecs = 4; IsLaneOp = true; break;
7842 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7843 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7844 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7845 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7846 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7847 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7852 VecTy = N->getOperand(2).getValueType();
7854 VecTy = N->getValueType(0);
7856 // If the increment is a constant, it must match the memory ref size.
7857 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7858 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7859 uint32_t IncVal = CInc->getZExtValue();
7860 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7861 if (IsLaneOp || IsDupOp)
7862 NumBytes /= VecTy.getVectorNumElements();
7863 if (IncVal != NumBytes)
7865 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7867 SmallVector<SDValue, 8> Ops;
7868 Ops.push_back(N->getOperand(0)); // Incoming chain
7869 // Load lane and store have vector list as input.
7870 if (IsLaneOp || IsStore)
7871 for (unsigned i = 2; i < AddrOpIdx; ++i)
7872 Ops.push_back(N->getOperand(i));
7873 Ops.push_back(Addr); // Base register
7878 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7880 for (n = 0; n < NumResultVecs; ++n)
7882 Tys[n++] = MVT::i64; // Type of write back register
7883 Tys[n] = MVT::Other; // Type of the chain
7884 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
7886 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7887 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7888 MemInt->getMemoryVT(),
7889 MemInt->getMemOperand());
7892 std::vector<SDValue> NewResults;
7893 for (unsigned i = 0; i < NumResultVecs; ++i) {
7894 NewResults.push_back(SDValue(UpdN.getNode(), i));
7896 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7897 DCI.CombineTo(N, NewResults);
7898 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7905 // Checks to see if the value is the prescribed width and returns information
7906 // about its extension mode.
7908 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
7909 ExtType = ISD::NON_EXTLOAD;
7910 switch(V.getNode()->getOpcode()) {
7914 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
7915 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
7916 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
7917 ExtType = LoadNode->getExtensionType();
7922 case ISD::AssertSext: {
7923 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
7924 if ((TypeNode->getVT() == MVT::i8 && width == 8)
7925 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
7926 ExtType = ISD::SEXTLOAD;
7931 case ISD::AssertZext: {
7932 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
7933 if ((TypeNode->getVT() == MVT::i8 && width == 8)
7934 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
7935 ExtType = ISD::ZEXTLOAD;
7941 case ISD::TargetConstant: {
7942 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
7952 // This function does a whole lot of voodoo to determine if the tests are
7953 // equivalent without and with a mask. Essentially what happens is that given a
7956 // +-------------+ +-------------+ +-------------+ +-------------+
7957 // | Input | | AddConstant | | CompConstant| | CC |
7958 // +-------------+ +-------------+ +-------------+ +-------------+
7960 // V V | +----------+
7961 // +-------------+ +----+ | |
7962 // | ADD | |0xff| | |
7963 // +-------------+ +----+ | |
7966 // +-------------+ | |
7968 // +-------------+ | |
7977 // The AND node may be safely removed for some combinations of inputs. In
7978 // particular we need to take into account the extension type of the Input,
7979 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
7980 // width of the input (this can work for any width inputs, the above graph is
7981 // specific to 8 bits.
7983 // The specific equations were worked out by generating output tables for each
7984 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
7985 // problem was simplified by working with 4 bit inputs, which means we only
7986 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
7987 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
7988 // patterns present in both extensions (0,7). For every distinct set of
7989 // AddConstant and CompConstants bit patterns we can consider the masked and
7990 // unmasked versions to be equivalent if the result of this function is true for
7991 // all 16 distinct bit patterns of for the current extension type of Input (w0).
7994 // and w10, w8, #0x0f
7996 // cset w9, AArch64CC
7998 // cset w11, AArch64CC
8003 // Since the above function shows when the outputs are equivalent it defines
8004 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8005 // would be expensive to run during compiles. The equations below were written
8006 // in a test harness that confirmed they gave equivalent outputs to the above
8007 // for all inputs function, so they can be used determine if the removal is
8010 // isEquivalentMaskless() is the code for testing if the AND can be removed
8011 // factored out of the DAG recognition as the DAG can take several forms.
8014 bool isEquivalentMaskless(unsigned CC, unsigned width,
8015 ISD::LoadExtType ExtType, signed AddConstant,
8016 signed CompConstant) {
8017 // By being careful about our equations and only writing the in term
8018 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8019 // make them generally applicable to all bit widths.
8020 signed MaxUInt = (1 << width);
8022 // For the purposes of these comparisons sign extending the type is
8023 // equivalent to zero extending the add and displacing it by half the integer
8024 // width. Provided we are careful and make sure our equations are valid over
8025 // the whole range we can just adjust the input and avoid writing equations
8026 // for sign extended inputs.
8027 if (ExtType == ISD::SEXTLOAD)
8028 AddConstant -= (1 << (width-1));
8032 case AArch64CC::GT: {
8033 if ((AddConstant == 0) ||
8034 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8035 (AddConstant >= 0 && CompConstant < 0) ||
8036 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8040 case AArch64CC::GE: {
8041 if ((AddConstant == 0) ||
8042 (AddConstant >= 0 && CompConstant <= 0) ||
8043 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8047 case AArch64CC::LS: {
8048 if ((AddConstant >= 0 && CompConstant < 0) ||
8049 (AddConstant <= 0 && CompConstant >= -1 &&
8050 CompConstant < AddConstant + MaxUInt))
8054 case AArch64CC::MI: {
8055 if ((AddConstant == 0) ||
8056 (AddConstant > 0 && CompConstant <= 0) ||
8057 (AddConstant < 0 && CompConstant <= AddConstant))
8061 case AArch64CC::HS: {
8062 if ((AddConstant >= 0 && CompConstant <= 0) ||
8063 (AddConstant <= 0 && CompConstant >= 0 &&
8064 CompConstant <= AddConstant + MaxUInt))
8068 case AArch64CC::NE: {
8069 if ((AddConstant > 0 && CompConstant < 0) ||
8070 (AddConstant < 0 && CompConstant >= 0 &&
8071 CompConstant < AddConstant + MaxUInt) ||
8072 (AddConstant >= 0 && CompConstant >= 0 &&
8073 CompConstant >= AddConstant) ||
8074 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8083 case AArch64CC::Invalid:
8091 SDValue performCONDCombine(SDNode *N,
8092 TargetLowering::DAGCombinerInfo &DCI,
8093 SelectionDAG &DAG, unsigned CCIndex,
8094 unsigned CmpIndex) {
8095 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8096 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8097 unsigned CondOpcode = SubsNode->getOpcode();
8099 if (CondOpcode != AArch64ISD::SUBS)
8102 // There is a SUBS feeding this condition. Is it fed by a mask we can
8105 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8106 unsigned MaskBits = 0;
8108 if (AndNode->getOpcode() != ISD::AND)
8111 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8112 uint32_t CNV = CN->getZExtValue();
8115 else if (CNV == 65535)
8122 SDValue AddValue = AndNode->getOperand(0);
8124 if (AddValue.getOpcode() != ISD::ADD)
8127 // The basic dag structure is correct, grab the inputs and validate them.
8129 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8130 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8131 SDValue SubsInputValue = SubsNode->getOperand(1);
8133 // The mask is present and the provenance of all the values is a smaller type,
8134 // lets see if the mask is superfluous.
8136 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8137 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8140 ISD::LoadExtType ExtType;
8142 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8143 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8144 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8147 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8148 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8149 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8152 // The AND is not necessary, remove it.
8154 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8155 SubsNode->getValueType(1));
8156 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8158 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8159 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8161 return SDValue(N, 0);
8164 // Optimize compare with zero and branch.
8165 static SDValue performBRCONDCombine(SDNode *N,
8166 TargetLowering::DAGCombinerInfo &DCI,
8167 SelectionDAG &DAG) {
8168 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8171 SDValue Chain = N->getOperand(0);
8172 SDValue Dest = N->getOperand(1);
8173 SDValue CCVal = N->getOperand(2);
8174 SDValue Cmp = N->getOperand(3);
8176 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8177 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8178 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8181 unsigned CmpOpc = Cmp.getOpcode();
8182 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8185 // Only attempt folding if there is only one use of the flag and no use of the
8187 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8190 SDValue LHS = Cmp.getOperand(0);
8191 SDValue RHS = Cmp.getOperand(1);
8193 assert(LHS.getValueType() == RHS.getValueType() &&
8194 "Expected the value type to be the same for both operands!");
8195 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8198 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8199 std::swap(LHS, RHS);
8201 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8204 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8205 LHS.getOpcode() == ISD::SRL)
8208 // Fold the compare into the branch instruction.
8210 if (CC == AArch64CC::EQ)
8211 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8213 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8215 // Do not add new nodes to DAG combiner worklist.
8216 DCI.CombineTo(N, BR, false);
8221 // vselect (v1i1 setcc) ->
8222 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8223 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8224 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8226 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8227 SDValue N0 = N->getOperand(0);
8228 EVT CCVT = N0.getValueType();
8230 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8231 CCVT.getVectorElementType() != MVT::i1)
8234 EVT ResVT = N->getValueType(0);
8235 EVT CmpVT = N0.getOperand(0).getValueType();
8236 // Only combine when the result type is of the same size as the compared
8238 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8241 SDValue IfTrue = N->getOperand(1);
8242 SDValue IfFalse = N->getOperand(2);
8244 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8245 N0.getOperand(0), N0.getOperand(1),
8246 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8247 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8251 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8252 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8253 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8254 /// with a vector one followed by a DUP shuffle on the result.
8255 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8256 SDValue N0 = N->getOperand(0);
8257 EVT ResVT = N->getValueType(0);
8259 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8262 // If NumMaskElts == 0, the comparison is larger than select result. The
8263 // largest real NEON comparison is 64-bits per lane, which means the result is
8264 // at most 32-bits and an illegal vector. Just bail out for now.
8265 EVT SrcVT = N0.getOperand(0).getValueType();
8266 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8267 if (!ResVT.isVector() || NumMaskElts == 0)
8270 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8271 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8273 // First perform a vector comparison, where lane 0 is the one we're interested
8277 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8279 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8280 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8282 // Now duplicate the comparison mask we want across all other lanes.
8283 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8284 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8285 Mask = DAG.getNode(ISD::BITCAST, DL,
8286 ResVT.changeVectorElementTypeToInteger(), Mask);
8288 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8291 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8292 DAGCombinerInfo &DCI) const {
8293 SelectionDAG &DAG = DCI.DAG;
8294 switch (N->getOpcode()) {
8299 return performAddSubLongCombine(N, DCI, DAG);
8301 return performXorCombine(N, DAG, DCI, Subtarget);
8303 return performMulCombine(N, DAG, DCI, Subtarget);
8304 case ISD::SINT_TO_FP:
8305 case ISD::UINT_TO_FP:
8306 return performIntToFpCombine(N, DAG);
8308 return performORCombine(N, DCI, Subtarget);
8309 case ISD::INTRINSIC_WO_CHAIN:
8310 return performIntrinsicCombine(N, DCI, Subtarget);
8311 case ISD::ANY_EXTEND:
8312 case ISD::ZERO_EXTEND:
8313 case ISD::SIGN_EXTEND:
8314 return performExtendCombine(N, DCI, DAG);
8316 return performBitcastCombine(N, DCI, DAG);
8317 case ISD::CONCAT_VECTORS:
8318 return performConcatVectorsCombine(N, DCI, DAG);
8320 return performSelectCombine(N, DAG);
8322 return performVSelectCombine(N, DCI.DAG);
8324 return performSTORECombine(N, DCI, DAG, Subtarget);
8325 case AArch64ISD::BRCOND:
8326 return performBRCONDCombine(N, DCI, DAG);
8327 case AArch64ISD::CSEL:
8328 return performCONDCombine(N, DCI, DAG, 2, 3);
8329 case AArch64ISD::DUP:
8330 return performPostLD1Combine(N, DCI, false);
8331 case ISD::INSERT_VECTOR_ELT:
8332 return performPostLD1Combine(N, DCI, true);
8333 case ISD::INTRINSIC_VOID:
8334 case ISD::INTRINSIC_W_CHAIN:
8335 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8336 case Intrinsic::aarch64_neon_ld2:
8337 case Intrinsic::aarch64_neon_ld3:
8338 case Intrinsic::aarch64_neon_ld4:
8339 case Intrinsic::aarch64_neon_ld1x2:
8340 case Intrinsic::aarch64_neon_ld1x3:
8341 case Intrinsic::aarch64_neon_ld1x4:
8342 case Intrinsic::aarch64_neon_ld2lane:
8343 case Intrinsic::aarch64_neon_ld3lane:
8344 case Intrinsic::aarch64_neon_ld4lane:
8345 case Intrinsic::aarch64_neon_ld2r:
8346 case Intrinsic::aarch64_neon_ld3r:
8347 case Intrinsic::aarch64_neon_ld4r:
8348 case Intrinsic::aarch64_neon_st2:
8349 case Intrinsic::aarch64_neon_st3:
8350 case Intrinsic::aarch64_neon_st4:
8351 case Intrinsic::aarch64_neon_st1x2:
8352 case Intrinsic::aarch64_neon_st1x3:
8353 case Intrinsic::aarch64_neon_st1x4:
8354 case Intrinsic::aarch64_neon_st2lane:
8355 case Intrinsic::aarch64_neon_st3lane:
8356 case Intrinsic::aarch64_neon_st4lane:
8357 return performNEONPostLDSTCombine(N, DCI, DAG);
8365 // Check if the return value is used as only a return value, as otherwise
8366 // we can't perform a tail-call. In particular, we need to check for
8367 // target ISD nodes that are returns and any other "odd" constructs
8368 // that the generic analysis code won't necessarily catch.
8369 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8370 SDValue &Chain) const {
8371 if (N->getNumValues() != 1)
8373 if (!N->hasNUsesOfValue(1, 0))
8376 SDValue TCChain = Chain;
8377 SDNode *Copy = *N->use_begin();
8378 if (Copy->getOpcode() == ISD::CopyToReg) {
8379 // If the copy has a glue operand, we conservatively assume it isn't safe to
8380 // perform a tail call.
8381 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8384 TCChain = Copy->getOperand(0);
8385 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8388 bool HasRet = false;
8389 for (SDNode *Node : Copy->uses()) {
8390 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8402 // Return whether the an instruction can potentially be optimized to a tail
8403 // call. This will cause the optimizers to attempt to move, or duplicate,
8404 // return instructions to help enable tail call optimizations for this
8406 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8407 if (!CI->isTailCall())
8413 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8415 ISD::MemIndexedMode &AM,
8417 SelectionDAG &DAG) const {
8418 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8421 Base = Op->getOperand(0);
8422 // All of the indexed addressing mode instructions take a signed
8423 // 9 bit immediate offset.
8424 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8425 int64_t RHSC = (int64_t)RHS->getZExtValue();
8426 if (RHSC >= 256 || RHSC <= -256)
8428 IsInc = (Op->getOpcode() == ISD::ADD);
8429 Offset = Op->getOperand(1);
8435 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8437 ISD::MemIndexedMode &AM,
8438 SelectionDAG &DAG) const {
8441 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8442 VT = LD->getMemoryVT();
8443 Ptr = LD->getBasePtr();
8444 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8445 VT = ST->getMemoryVT();
8446 Ptr = ST->getBasePtr();
8451 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8453 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8457 bool AArch64TargetLowering::getPostIndexedAddressParts(
8458 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8459 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8462 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8463 VT = LD->getMemoryVT();
8464 Ptr = LD->getBasePtr();
8465 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8466 VT = ST->getMemoryVT();
8467 Ptr = ST->getBasePtr();
8472 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8474 // Post-indexing updates the base, so it's not a valid transform
8475 // if that's not the same as the load's pointer.
8478 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8482 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8483 SelectionDAG &DAG) {
8484 if (N->getValueType(0) != MVT::i16)
8488 SDValue Op = N->getOperand(0);
8489 assert(Op.getValueType() == MVT::f16 &&
8490 "Inconsistent bitcast? Only 16-bit types should be i16 or f16");
8492 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8493 DAG.getUNDEF(MVT::i32), Op,
8494 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8496 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8497 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8500 void AArch64TargetLowering::ReplaceNodeResults(
8501 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8502 switch (N->getOpcode()) {
8504 llvm_unreachable("Don't know how to custom expand this");
8506 ReplaceBITCASTResults(N, Results, DAG);
8508 case ISD::FP_TO_UINT:
8509 case ISD::FP_TO_SINT:
8510 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8511 // Let normal code take care of it by not adding anything to Results.
8516 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
8517 // Loads and stores less than 128-bits are already atomic; ones above that
8518 // are doomed anyway, so defer to the default libcall and blame the OS when
8520 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
8521 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
8522 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
8523 return LI->getType()->getPrimitiveSizeInBits() == 128;
8525 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
8526 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
8529 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8533 TargetLoweringBase::LegalizeTypeAction
8534 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8535 MVT SVT = VT.getSimpleVT();
8536 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8537 // v4i16, v2i32 instead of to promote.
8538 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8539 || SVT == MVT::v1f32)
8540 return TypeWidenVector;
8542 return TargetLoweringBase::getPreferredVectorAction(VT);
8545 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8546 AtomicOrdering Ord) const {
8547 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8548 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8549 bool IsAcquire = isAtLeastAcquire(Ord);
8551 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8552 // intrinsic must return {i64, i64} and we have to recombine them into a
8553 // single i128 here.
8554 if (ValTy->getPrimitiveSizeInBits() == 128) {
8556 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8557 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8559 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8560 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8562 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8563 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8564 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8565 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8566 return Builder.CreateOr(
8567 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8570 Type *Tys[] = { Addr->getType() };
8572 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8573 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8575 return Builder.CreateTruncOrBitCast(
8576 Builder.CreateCall(Ldxr, Addr),
8577 cast<PointerType>(Addr->getType())->getElementType());
8580 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8581 Value *Val, Value *Addr,
8582 AtomicOrdering Ord) const {
8583 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8584 bool IsRelease = isAtLeastRelease(Ord);
8586 // Since the intrinsics must have legal type, the i128 intrinsics take two
8587 // parameters: "i64, i64". We must marshal Val into the appropriate form
8589 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8591 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8592 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8593 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8595 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8596 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8597 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8598 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8602 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8603 Type *Tys[] = { Addr->getType() };
8604 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8606 return Builder.CreateCall2(
8607 Stxr, Builder.CreateZExtOrBitCast(
8608 Val, Stxr->getFunctionType()->getParamType(0)),