1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64PerfectShuffle.h"
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
48 static cl::opt<AlignMode>
49 Align(cl::desc("Load/store alignment support"),
50 cl::Hidden, cl::init(NoStrictAlign),
52 clEnumValN(StrictAlign, "aarch64-strict-align",
53 "Disallow all unaligned memory accesses"),
54 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
55 "Allow unaligned memory accesses"),
58 // Place holder until extr generation is tested fully.
60 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
61 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
65 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
66 cl::desc("Allow AArch64 SLI/SRI formation"),
69 //===----------------------------------------------------------------------===//
70 // AArch64 Lowering public interface.
71 //===----------------------------------------------------------------------===//
72 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
73 if (TT.isOSBinFormatMachO())
74 return new AArch64_MachoTargetObjectFile();
76 return new AArch64_ELFTargetObjectFile();
79 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
81 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
84 // we have to make something up. Arbitrarily, choose ZeroOrOne.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // When comparing vectors the result sets the different elements in the
87 // vector to all-one or all-zero.
88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
90 // Set up the register classes.
91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
94 if (Subtarget->hasFPARMv8()) {
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
101 if (Subtarget->hasNEON()) {
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
104 // Someone set us up the NEON.
105 addDRTypeForNEON(MVT::v2f32);
106 addDRTypeForNEON(MVT::v8i8);
107 addDRTypeForNEON(MVT::v4i16);
108 addDRTypeForNEON(MVT::v2i32);
109 addDRTypeForNEON(MVT::v1i64);
110 addDRTypeForNEON(MVT::v1f64);
111 addDRTypeForNEON(MVT::v4f16);
113 addQRTypeForNEON(MVT::v4f32);
114 addQRTypeForNEON(MVT::v2f64);
115 addQRTypeForNEON(MVT::v16i8);
116 addQRTypeForNEON(MVT::v8i16);
117 addQRTypeForNEON(MVT::v4i32);
118 addQRTypeForNEON(MVT::v2i64);
119 addQRTypeForNEON(MVT::v8f16);
122 // Compute derived properties from the register classes
123 computeRegisterProperties();
125 // Provide all sorts of operation actions
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
128 setOperationAction(ISD::SETCC, MVT::i32, Custom);
129 setOperationAction(ISD::SETCC, MVT::i64, Custom);
130 setOperationAction(ISD::SETCC, MVT::f32, Custom);
131 setOperationAction(ISD::SETCC, MVT::f64, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::FREM, MVT::f32, Expand);
153 setOperationAction(ISD::FREM, MVT::f64, Expand);
154 setOperationAction(ISD::FREM, MVT::f80, Expand);
156 // Custom lowering hooks are needed for XOR
157 // to fold it into CSINC/CSINV.
158 setOperationAction(ISD::XOR, MVT::i32, Custom);
159 setOperationAction(ISD::XOR, MVT::i64, Custom);
161 // Virtually no operation on f128 is legal, but LLVM can't expand them when
162 // there's a valid register class, so we need custom operations in most cases.
163 setOperationAction(ISD::FABS, MVT::f128, Expand);
164 setOperationAction(ISD::FADD, MVT::f128, Custom);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
166 setOperationAction(ISD::FCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FDIV, MVT::f128, Custom);
168 setOperationAction(ISD::FMA, MVT::f128, Expand);
169 setOperationAction(ISD::FMUL, MVT::f128, Custom);
170 setOperationAction(ISD::FNEG, MVT::f128, Expand);
171 setOperationAction(ISD::FPOW, MVT::f128, Expand);
172 setOperationAction(ISD::FREM, MVT::f128, Expand);
173 setOperationAction(ISD::FRINT, MVT::f128, Expand);
174 setOperationAction(ISD::FSIN, MVT::f128, Expand);
175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
176 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
177 setOperationAction(ISD::FSUB, MVT::f128, Custom);
178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
179 setOperationAction(ISD::SETCC, MVT::f128, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT, MVT::f128, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
185 // Lowering for many of the conversions is actually specified by the non-f128
186 // type. The LowerXXX function will be trivial when f128 isn't involved.
187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
202 // Variable arguments.
203 setOperationAction(ISD::VASTART, MVT::Other, Custom);
204 setOperationAction(ISD::VAARG, MVT::Other, Custom);
205 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
206 setOperationAction(ISD::VAEND, MVT::Other, Expand);
208 // Variable-sized objects.
209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
213 // Exception handling.
214 // FIXME: These are guesses. Has this been defined yet?
215 setExceptionPointerRegister(AArch64::X0);
216 setExceptionSelectorRegister(AArch64::X1);
218 // Constant pool entries
219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
225 setOperationAction(ISD::ADDC, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i32, Custom);
227 setOperationAction(ISD::SUBC, MVT::i32, Custom);
228 setOperationAction(ISD::SUBE, MVT::i32, Custom);
229 setOperationAction(ISD::ADDC, MVT::i64, Custom);
230 setOperationAction(ISD::ADDE, MVT::i64, Custom);
231 setOperationAction(ISD::SUBC, MVT::i64, Custom);
232 setOperationAction(ISD::SUBE, MVT::i64, Custom);
234 // AArch64 lacks both left-rotate and popcount instructions.
235 setOperationAction(ISD::ROTL, MVT::i32, Expand);
236 setOperationAction(ISD::ROTL, MVT::i64, Expand);
238 // AArch64 doesn't have {U|S}MUL_LOHI.
239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
244 // counterparts, which AArch64 supports directly.
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
251 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
256 setOperationAction(ISD::SREM, MVT::i64, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i32, Expand);
260 setOperationAction(ISD::UREM, MVT::i64, Expand);
262 // Custom lower Add/Sub/Mul with overflow.
263 setOperationAction(ISD::SADDO, MVT::i32, Custom);
264 setOperationAction(ISD::SADDO, MVT::i64, Custom);
265 setOperationAction(ISD::UADDO, MVT::i32, Custom);
266 setOperationAction(ISD::UADDO, MVT::i64, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
268 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
269 setOperationAction(ISD::USUBO, MVT::i32, Custom);
270 setOperationAction(ISD::USUBO, MVT::i64, Custom);
271 setOperationAction(ISD::SMULO, MVT::i32, Custom);
272 setOperationAction(ISD::SMULO, MVT::i64, Custom);
273 setOperationAction(ISD::UMULO, MVT::i32, Custom);
274 setOperationAction(ISD::UMULO, MVT::i64, Custom);
276 setOperationAction(ISD::FSIN, MVT::f32, Expand);
277 setOperationAction(ISD::FSIN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FCOS, MVT::f64, Expand);
280 setOperationAction(ISD::FPOW, MVT::f32, Expand);
281 setOperationAction(ISD::FPOW, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285 // f16 is storage-only, so we promote operations to f32 if we know this is
286 // valid, and ignore them otherwise. The operations not mentioned here will
287 // fail to select, but this is not a major problem as no source language
288 // should be emitting native f16 operations yet.
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FDIV, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FSUB, MVT::f16, Promote);
294 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
296 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
297 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
298 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
299 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
301 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
302 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
307 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
309 // Expand all other v4f16 operations.
310 // FIXME: We could generate better code by promoting some operations to
312 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
315 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
316 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
317 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
319 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
321 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
322 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
323 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
324 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
328 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
329 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
330 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
332 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
334 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
337 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
340 // v8f16 is also a storage-only type, so expand it.
341 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
342 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
345 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
346 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
347 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
349 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
351 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
353 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
354 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
355 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
356 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
360 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
361 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
362 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
363 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
365 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
366 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
368 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
371 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
373 // AArch64 has implementations of a lot of rounding-like FP operations.
374 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
375 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
376 MVT Ty = RoundingTypes[I];
377 setOperationAction(ISD::FFLOOR, Ty, Legal);
378 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
379 setOperationAction(ISD::FCEIL, Ty, Legal);
380 setOperationAction(ISD::FRINT, Ty, Legal);
381 setOperationAction(ISD::FTRUNC, Ty, Legal);
382 setOperationAction(ISD::FROUND, Ty, Legal);
385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
387 if (Subtarget->isTargetMachO()) {
388 // For iOS, we don't want to the normal expansion of a libcall to
389 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
391 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
392 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
394 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
395 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
398 // AArch64 does not have floating-point extending loads, i1 sign-extending
399 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
400 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
401 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
402 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
403 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
404 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
405 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
406 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
407 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
408 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
409 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
410 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
411 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
413 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
414 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
416 // Indexed loads and stores are supported.
417 for (unsigned im = (unsigned)ISD::PRE_INC;
418 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
419 setIndexedLoadAction(im, MVT::i8, Legal);
420 setIndexedLoadAction(im, MVT::i16, Legal);
421 setIndexedLoadAction(im, MVT::i32, Legal);
422 setIndexedLoadAction(im, MVT::i64, Legal);
423 setIndexedLoadAction(im, MVT::f64, Legal);
424 setIndexedLoadAction(im, MVT::f32, Legal);
425 setIndexedStoreAction(im, MVT::i8, Legal);
426 setIndexedStoreAction(im, MVT::i16, Legal);
427 setIndexedStoreAction(im, MVT::i32, Legal);
428 setIndexedStoreAction(im, MVT::i64, Legal);
429 setIndexedStoreAction(im, MVT::f64, Legal);
430 setIndexedStoreAction(im, MVT::f32, Legal);
434 setOperationAction(ISD::TRAP, MVT::Other, Legal);
436 // We combine OR nodes for bitfield operations.
437 setTargetDAGCombine(ISD::OR);
439 // Vector add and sub nodes may conceal a high-half opportunity.
440 // Also, try to fold ADD into CSINC/CSINV..
441 setTargetDAGCombine(ISD::ADD);
442 setTargetDAGCombine(ISD::SUB);
444 setTargetDAGCombine(ISD::XOR);
445 setTargetDAGCombine(ISD::SINT_TO_FP);
446 setTargetDAGCombine(ISD::UINT_TO_FP);
448 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
450 setTargetDAGCombine(ISD::ANY_EXTEND);
451 setTargetDAGCombine(ISD::ZERO_EXTEND);
452 setTargetDAGCombine(ISD::SIGN_EXTEND);
453 setTargetDAGCombine(ISD::BITCAST);
454 setTargetDAGCombine(ISD::CONCAT_VECTORS);
455 setTargetDAGCombine(ISD::STORE);
457 setTargetDAGCombine(ISD::MUL);
459 setTargetDAGCombine(ISD::SELECT);
460 setTargetDAGCombine(ISD::VSELECT);
462 setTargetDAGCombine(ISD::INTRINSIC_VOID);
463 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
464 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
466 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
467 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
468 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
470 setStackPointerRegisterToSaveRestore(AArch64::SP);
472 setSchedulingPreference(Sched::Hybrid);
475 MaskAndBranchFoldingIsLegal = true;
477 setMinFunctionAlignment(2);
479 RequireStrictAlign = (Align == StrictAlign);
481 setHasExtractBitsInsn(true);
483 if (Subtarget->hasNEON()) {
484 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
485 // silliness like this:
486 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
487 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
488 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
489 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
490 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
491 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
492 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
493 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
494 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
495 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
496 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
497 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
498 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
499 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
500 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
501 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
502 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
503 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
504 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
505 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
506 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
507 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
508 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
509 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
510 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
512 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
513 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
514 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
515 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
516 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
518 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
521 // elements smaller than i32, so promote the input to i32 first.
522 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
523 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
524 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
525 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
526 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
527 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
528 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
529 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
530 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
532 // AArch64 doesn't have MUL.2d:
533 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
534 // Custom handling for some quad-vector types to detect MULL.
535 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
536 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
537 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
539 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
540 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
541 // Likewise, narrowing and extending vector loads/stores aren't handled
543 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
544 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
546 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
549 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
556 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
557 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
558 setTruncStoreAction((MVT::SimpleValueType)VT,
559 (MVT::SimpleValueType)InnerVT, Expand);
560 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
561 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
562 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
565 // AArch64 has implementations of a lot of rounding-like FP operations.
566 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
567 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
568 MVT Ty = RoundingVecTypes[I];
569 setOperationAction(ISD::FFLOOR, Ty, Legal);
570 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
571 setOperationAction(ISD::FCEIL, Ty, Legal);
572 setOperationAction(ISD::FRINT, Ty, Legal);
573 setOperationAction(ISD::FTRUNC, Ty, Legal);
574 setOperationAction(ISD::FROUND, Ty, Legal);
578 // Prefer likely predicted branches to selects on out-of-order cores.
579 if (Subtarget->isCortexA57())
580 PredictableSelectIsExpensive = true;
583 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
584 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
585 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
586 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
588 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
589 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
590 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
591 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
592 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
594 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
595 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
598 // Mark vector float intrinsics as expand.
599 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
600 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
601 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
602 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
603 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
604 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
605 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
606 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
607 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
608 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
611 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
612 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
613 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
614 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
615 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
616 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
617 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
618 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
619 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
620 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
621 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
622 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
624 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
625 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
626 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
627 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
629 // CNT supports only B element sizes.
630 if (VT != MVT::v8i8 && VT != MVT::v16i8)
631 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
633 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
635 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
636 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
637 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
639 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
640 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
642 if (Subtarget->isLittleEndian()) {
643 for (unsigned im = (unsigned)ISD::PRE_INC;
644 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
645 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
646 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
651 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
652 addRegisterClass(VT, &AArch64::FPR64RegClass);
653 addTypeForNEON(VT, MVT::v2i32);
656 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
657 addRegisterClass(VT, &AArch64::FPR128RegClass);
658 addTypeForNEON(VT, MVT::v4i32);
661 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
664 return VT.changeVectorElementTypeToInteger();
667 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
668 /// Mask are known to be either zero or one and return them in the
669 /// KnownZero/KnownOne bitsets.
670 void AArch64TargetLowering::computeKnownBitsForTargetNode(
671 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
672 const SelectionDAG &DAG, unsigned Depth) const {
673 switch (Op.getOpcode()) {
676 case AArch64ISD::CSEL: {
677 APInt KnownZero2, KnownOne2;
678 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
679 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
680 KnownZero &= KnownZero2;
681 KnownOne &= KnownOne2;
684 case ISD::INTRINSIC_W_CHAIN: {
685 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
686 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
689 case Intrinsic::aarch64_ldaxr:
690 case Intrinsic::aarch64_ldxr: {
691 unsigned BitWidth = KnownOne.getBitWidth();
692 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
693 unsigned MemBits = VT.getScalarType().getSizeInBits();
694 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
700 case ISD::INTRINSIC_WO_CHAIN:
701 case ISD::INTRINSIC_VOID: {
702 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
706 case Intrinsic::aarch64_neon_umaxv:
707 case Intrinsic::aarch64_neon_uminv: {
708 // Figure out the datatype of the vector operand. The UMINV instruction
709 // will zero extend the result, so we can mark as known zero all the
710 // bits larger than the element datatype. 32-bit or larget doesn't need
711 // this as those are legal types and will be handled by isel directly.
712 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
713 unsigned BitWidth = KnownZero.getBitWidth();
714 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
715 assert(BitWidth >= 8 && "Unexpected width!");
716 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
718 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
719 assert(BitWidth >= 16 && "Unexpected width!");
720 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
730 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
734 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
735 // FIXME: On AArch64, this depends on the type.
736 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
737 // and the offset has to be a multiple of the related size in bytes.
742 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
743 const TargetLibraryInfo *libInfo) const {
744 return AArch64::createFastISel(funcInfo, libInfo);
747 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
751 case AArch64ISD::CALL: return "AArch64ISD::CALL";
752 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
753 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
754 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
755 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
756 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
757 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
758 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
759 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
760 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
761 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
762 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
763 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
764 case AArch64ISD::ADC: return "AArch64ISD::ADC";
765 case AArch64ISD::SBC: return "AArch64ISD::SBC";
766 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
767 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
768 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
769 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
770 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
771 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
772 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
773 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
774 case AArch64ISD::DUP: return "AArch64ISD::DUP";
775 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
776 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
777 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
778 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
779 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
780 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
781 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
782 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
783 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
784 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
785 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
786 case AArch64ISD::BICi: return "AArch64ISD::BICi";
787 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
788 case AArch64ISD::BSL: return "AArch64ISD::BSL";
789 case AArch64ISD::NEG: return "AArch64ISD::NEG";
790 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
791 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
792 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
793 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
794 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
795 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
796 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
797 case AArch64ISD::REV16: return "AArch64ISD::REV16";
798 case AArch64ISD::REV32: return "AArch64ISD::REV32";
799 case AArch64ISD::REV64: return "AArch64ISD::REV64";
800 case AArch64ISD::EXT: return "AArch64ISD::EXT";
801 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
802 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
803 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
804 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
805 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
806 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
807 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
808 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
809 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
810 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
811 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
812 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
813 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
814 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
815 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
816 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
817 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
818 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
819 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
820 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
821 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
822 case AArch64ISD::NOT: return "AArch64ISD::NOT";
823 case AArch64ISD::BIT: return "AArch64ISD::BIT";
824 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
825 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
826 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
827 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
828 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
829 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
830 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
831 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
832 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
833 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
834 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
835 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
836 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
837 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
838 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
839 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
840 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
841 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
842 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
843 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
844 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
845 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
846 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
847 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
848 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
849 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
850 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
851 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
852 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
853 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
854 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
855 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
856 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
857 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
858 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
859 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
860 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
861 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
862 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
867 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
868 MachineBasicBlock *MBB) const {
869 // We materialise the F128CSEL pseudo-instruction as some control flow and a
873 // [... previous instrs leading to comparison ...]
879 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
881 const TargetInstrInfo *TII =
882 getTargetMachine().getSubtargetImpl()->getInstrInfo();
883 MachineFunction *MF = MBB->getParent();
884 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
885 DebugLoc DL = MI->getDebugLoc();
886 MachineFunction::iterator It = MBB;
889 unsigned DestReg = MI->getOperand(0).getReg();
890 unsigned IfTrueReg = MI->getOperand(1).getReg();
891 unsigned IfFalseReg = MI->getOperand(2).getReg();
892 unsigned CondCode = MI->getOperand(3).getImm();
893 bool NZCVKilled = MI->getOperand(4).isKill();
895 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
896 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
897 MF->insert(It, TrueBB);
898 MF->insert(It, EndBB);
900 // Transfer rest of current basic-block to EndBB
901 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
903 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
905 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
906 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
907 MBB->addSuccessor(TrueBB);
908 MBB->addSuccessor(EndBB);
910 // TrueBB falls through to the end.
911 TrueBB->addSuccessor(EndBB);
914 TrueBB->addLiveIn(AArch64::NZCV);
915 EndBB->addLiveIn(AArch64::NZCV);
918 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
924 MI->eraseFromParent();
929 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
930 MachineBasicBlock *BB) const {
931 switch (MI->getOpcode()) {
936 llvm_unreachable("Unexpected instruction for custom inserter!");
938 case AArch64::F128CSEL:
939 return EmitF128CSEL(MI, BB);
941 case TargetOpcode::STACKMAP:
942 case TargetOpcode::PATCHPOINT:
943 return emitPatchPoint(MI, BB);
947 //===----------------------------------------------------------------------===//
948 // AArch64 Lowering private implementation.
949 //===----------------------------------------------------------------------===//
951 //===----------------------------------------------------------------------===//
953 //===----------------------------------------------------------------------===//
955 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
957 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
960 llvm_unreachable("Unknown condition code!");
962 return AArch64CC::NE;
964 return AArch64CC::EQ;
966 return AArch64CC::GT;
968 return AArch64CC::GE;
970 return AArch64CC::LT;
972 return AArch64CC::LE;
974 return AArch64CC::HI;
976 return AArch64CC::HS;
978 return AArch64CC::LO;
980 return AArch64CC::LS;
984 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
985 static void changeFPCCToAArch64CC(ISD::CondCode CC,
986 AArch64CC::CondCode &CondCode,
987 AArch64CC::CondCode &CondCode2) {
988 CondCode2 = AArch64CC::AL;
991 llvm_unreachable("Unknown FP condition!");
994 CondCode = AArch64CC::EQ;
998 CondCode = AArch64CC::GT;
1002 CondCode = AArch64CC::GE;
1005 CondCode = AArch64CC::MI;
1008 CondCode = AArch64CC::LS;
1011 CondCode = AArch64CC::MI;
1012 CondCode2 = AArch64CC::GT;
1015 CondCode = AArch64CC::VC;
1018 CondCode = AArch64CC::VS;
1021 CondCode = AArch64CC::EQ;
1022 CondCode2 = AArch64CC::VS;
1025 CondCode = AArch64CC::HI;
1028 CondCode = AArch64CC::PL;
1032 CondCode = AArch64CC::LT;
1036 CondCode = AArch64CC::LE;
1040 CondCode = AArch64CC::NE;
1045 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1046 /// CC usable with the vector instructions. Fewer operations are available
1047 /// without a real NZCV register, so we have to use less efficient combinations
1048 /// to get the same effect.
1049 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1050 AArch64CC::CondCode &CondCode,
1051 AArch64CC::CondCode &CondCode2,
1056 // Mostly the scalar mappings work fine.
1057 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1060 Invert = true; // Fallthrough
1062 CondCode = AArch64CC::MI;
1063 CondCode2 = AArch64CC::GE;
1070 // All of the compare-mask comparisons are ordered, but we can switch
1071 // between the two by a double inversion. E.g. ULE == !OGT.
1073 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1078 static bool isLegalArithImmed(uint64_t C) {
1079 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1080 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1083 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1084 SDLoc dl, SelectionDAG &DAG) {
1085 EVT VT = LHS.getValueType();
1087 if (VT.isFloatingPoint())
1088 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1090 // The CMP instruction is just an alias for SUBS, and representing it as
1091 // SUBS means that it's possible to get CSE with subtract operations.
1092 // A later phase can perform the optimization of setting the destination
1093 // register to WZR/XZR if it ends up being unused.
1094 unsigned Opcode = AArch64ISD::SUBS;
1096 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1097 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1098 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1099 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1100 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1101 // can be set differently by this operation. It comes down to whether
1102 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1103 // everything is fine. If not then the optimization is wrong. Thus general
1104 // comparisons are only valid if op2 != 0.
1106 // So, finally, the only LLVM-native comparisons that don't mention C and V
1107 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1108 // the absence of information about op2.
1109 Opcode = AArch64ISD::ADDS;
1110 RHS = RHS.getOperand(1);
1111 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1112 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1113 !isUnsignedIntSetCC(CC)) {
1114 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1115 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1116 // of the signed comparisons.
1117 Opcode = AArch64ISD::ANDS;
1118 RHS = LHS.getOperand(1);
1119 LHS = LHS.getOperand(0);
1122 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1126 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1127 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1129 AArch64CC::CondCode AArch64CC;
1130 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1131 EVT VT = RHS.getValueType();
1132 uint64_t C = RHSC->getZExtValue();
1133 if (!isLegalArithImmed(C)) {
1134 // Constant does not fit, try adjusting it by one?
1140 if ((VT == MVT::i32 && C != 0x80000000 &&
1141 isLegalArithImmed((uint32_t)(C - 1))) ||
1142 (VT == MVT::i64 && C != 0x80000000ULL &&
1143 isLegalArithImmed(C - 1ULL))) {
1144 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1145 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1146 RHS = DAG.getConstant(C, VT);
1151 if ((VT == MVT::i32 && C != 0 &&
1152 isLegalArithImmed((uint32_t)(C - 1))) ||
1153 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1154 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1155 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1156 RHS = DAG.getConstant(C, VT);
1161 if ((VT == MVT::i32 && C != 0x7fffffff &&
1162 isLegalArithImmed((uint32_t)(C + 1))) ||
1163 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1164 isLegalArithImmed(C + 1ULL))) {
1165 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1166 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1167 RHS = DAG.getConstant(C, VT);
1172 if ((VT == MVT::i32 && C != 0xffffffff &&
1173 isLegalArithImmed((uint32_t)(C + 1))) ||
1174 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1175 isLegalArithImmed(C + 1ULL))) {
1176 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1177 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1178 RHS = DAG.getConstant(C, VT);
1184 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1185 // For the i8 operand, the largest immediate is 255, so this can be easily
1186 // encoded in the compare instruction. For the i16 operand, however, the
1187 // largest immediate cannot be encoded in the compare.
1188 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1189 // constant. For example,
1191 // ldrh w0, [x0, #0]
1194 // ldrsh w0, [x0, #0]
1196 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1197 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1198 // both the LHS and RHS are truely zero extended and to make sure the
1199 // transformation is profitable.
1200 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1201 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1202 isa<LoadSDNode>(LHS)) {
1203 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1204 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1205 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1206 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1207 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1209 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1210 DAG.getValueType(MVT::i16));
1211 Cmp = emitComparison(SExt,
1212 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1214 AArch64CC = changeIntCCToAArch64CC(CC);
1215 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1221 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1222 AArch64CC = changeIntCCToAArch64CC(CC);
1223 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1227 static std::pair<SDValue, SDValue>
1228 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1229 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1230 "Unsupported value type");
1231 SDValue Value, Overflow;
1233 SDValue LHS = Op.getOperand(0);
1234 SDValue RHS = Op.getOperand(1);
1236 switch (Op.getOpcode()) {
1238 llvm_unreachable("Unknown overflow instruction!");
1240 Opc = AArch64ISD::ADDS;
1244 Opc = AArch64ISD::ADDS;
1248 Opc = AArch64ISD::SUBS;
1252 Opc = AArch64ISD::SUBS;
1255 // Multiply needs a little bit extra work.
1259 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1260 if (Op.getValueType() == MVT::i32) {
1261 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1262 // For a 32 bit multiply with overflow check we want the instruction
1263 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1264 // need to generate the following pattern:
1265 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1266 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1267 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1268 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1269 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1270 DAG.getConstant(0, MVT::i64));
1271 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1272 // operation. We need to clear out the upper 32 bits, because we used a
1273 // widening multiply that wrote all 64 bits. In the end this should be a
1275 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1277 // The signed overflow check requires more than just a simple check for
1278 // any bit set in the upper 32 bits of the result. These bits could be
1279 // just the sign bits of a negative number. To perform the overflow
1280 // check we have to arithmetic shift right the 32nd bit of the result by
1281 // 31 bits. Then we compare the result to the upper 32 bits.
1282 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1283 DAG.getConstant(32, MVT::i64));
1284 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1285 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1286 DAG.getConstant(31, MVT::i64));
1287 // It is important that LowerBits is last, otherwise the arithmetic
1288 // shift will not be folded into the compare (SUBS).
1289 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1290 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1293 // The overflow check for unsigned multiply is easy. We only need to
1294 // check if any of the upper 32 bits are set. This can be done with a
1295 // CMP (shifted register). For that we need to generate the following
1297 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1298 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1299 DAG.getConstant(32, MVT::i64));
1300 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1302 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1303 UpperBits).getValue(1);
1307 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1308 // For the 64 bit multiply
1309 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1311 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1312 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1313 DAG.getConstant(63, MVT::i64));
1314 // It is important that LowerBits is last, otherwise the arithmetic
1315 // shift will not be folded into the compare (SUBS).
1316 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1317 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1320 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1321 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1323 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1324 UpperBits).getValue(1);
1331 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1333 // Emit the AArch64 operation with overflow check.
1334 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1335 Overflow = Value.getValue(1);
1337 return std::make_pair(Value, Overflow);
1340 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1341 RTLIB::Libcall Call) const {
1342 SmallVector<SDValue, 2> Ops;
1343 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1344 Ops.push_back(Op.getOperand(i));
1346 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1350 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1351 SDValue Sel = Op.getOperand(0);
1352 SDValue Other = Op.getOperand(1);
1354 // If neither operand is a SELECT_CC, give up.
1355 if (Sel.getOpcode() != ISD::SELECT_CC)
1356 std::swap(Sel, Other);
1357 if (Sel.getOpcode() != ISD::SELECT_CC)
1360 // The folding we want to perform is:
1361 // (xor x, (select_cc a, b, cc, 0, -1) )
1363 // (csel x, (xor x, -1), cc ...)
1365 // The latter will get matched to a CSINV instruction.
1367 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1368 SDValue LHS = Sel.getOperand(0);
1369 SDValue RHS = Sel.getOperand(1);
1370 SDValue TVal = Sel.getOperand(2);
1371 SDValue FVal = Sel.getOperand(3);
1374 // FIXME: This could be generalized to non-integer comparisons.
1375 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1378 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1379 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1381 // The the values aren't constants, this isn't the pattern we're looking for.
1382 if (!CFVal || !CTVal)
1385 // We can commute the SELECT_CC by inverting the condition. This
1386 // might be needed to make this fit into a CSINV pattern.
1387 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1388 std::swap(TVal, FVal);
1389 std::swap(CTVal, CFVal);
1390 CC = ISD::getSetCCInverse(CC, true);
1393 // If the constants line up, perform the transform!
1394 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1396 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1399 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1400 DAG.getConstant(-1ULL, Other.getValueType()));
1402 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1409 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1410 EVT VT = Op.getValueType();
1412 // Let legalize expand this if it isn't a legal type yet.
1413 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1416 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1419 bool ExtraOp = false;
1420 switch (Op.getOpcode()) {
1422 llvm_unreachable("Invalid code");
1424 Opc = AArch64ISD::ADDS;
1427 Opc = AArch64ISD::SUBS;
1430 Opc = AArch64ISD::ADCS;
1434 Opc = AArch64ISD::SBCS;
1440 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1441 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1445 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1446 // Let legalize expand this if it isn't a legal type yet.
1447 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1450 AArch64CC::CondCode CC;
1451 // The actual operation that sets the overflow or carry flag.
1452 SDValue Value, Overflow;
1453 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1455 // We use 0 and 1 as false and true values.
1456 SDValue TVal = DAG.getConstant(1, MVT::i32);
1457 SDValue FVal = DAG.getConstant(0, MVT::i32);
1459 // We use an inverted condition, because the conditional select is inverted
1460 // too. This will allow it to be selected to a single instruction:
1461 // CSINC Wd, WZR, WZR, invert(cond).
1462 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1463 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1466 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1467 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1470 // Prefetch operands are:
1471 // 1: Address to prefetch
1473 // 3: int locality (0 = no locality ... 3 = extreme locality)
1474 // 4: bool isDataCache
1475 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1477 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1478 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1479 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1481 bool IsStream = !Locality;
1482 // When the locality number is set
1484 // The front-end should have filtered out the out-of-range values
1485 assert(Locality <= 3 && "Prefetch locality out-of-range");
1486 // The locality degree is the opposite of the cache speed.
1487 // Put the number the other way around.
1488 // The encoding starts at 0 for level 1
1489 Locality = 3 - Locality;
1492 // built the mask value encoding the expected behavior.
1493 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1494 (!IsData << 3) | // IsDataCache bit
1495 (Locality << 1) | // Cache level bits
1496 (unsigned)IsStream; // Stream bit
1497 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1498 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1501 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1502 SelectionDAG &DAG) const {
1503 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1506 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1508 return LowerF128Call(Op, DAG, LC);
1511 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1512 SelectionDAG &DAG) const {
1513 if (Op.getOperand(0).getValueType() != MVT::f128) {
1514 // It's legal except when f128 is involved
1519 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1521 // FP_ROUND node has a second operand indicating whether it is known to be
1522 // precise. That doesn't take part in the LibCall so we can't directly use
1524 SDValue SrcVal = Op.getOperand(0);
1525 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1526 /*isSigned*/ false, SDLoc(Op)).first;
1529 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1530 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1531 // Any additional optimization in this function should be recorded
1532 // in the cost tables.
1533 EVT InVT = Op.getOperand(0).getValueType();
1534 EVT VT = Op.getValueType();
1536 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1539 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1541 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1544 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1547 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1548 VT.getVectorNumElements());
1549 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1550 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1553 // Type changing conversions are illegal.
1557 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1558 SelectionDAG &DAG) const {
1559 if (Op.getOperand(0).getValueType().isVector())
1560 return LowerVectorFP_TO_INT(Op, DAG);
1562 if (Op.getOperand(0).getValueType() != MVT::f128) {
1563 // It's legal except when f128 is involved
1568 if (Op.getOpcode() == ISD::FP_TO_SINT)
1569 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1571 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1573 SmallVector<SDValue, 2> Ops;
1574 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1575 Ops.push_back(Op.getOperand(i));
1577 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1581 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1582 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1583 // Any additional optimization in this function should be recorded
1584 // in the cost tables.
1585 EVT VT = Op.getValueType();
1587 SDValue In = Op.getOperand(0);
1588 EVT InVT = In.getValueType();
1590 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1592 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1593 InVT.getVectorNumElements());
1594 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1595 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1598 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1600 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1601 EVT CastVT = VT.changeVectorElementTypeToInteger();
1602 In = DAG.getNode(CastOpc, dl, CastVT, In);
1603 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1609 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1610 SelectionDAG &DAG) const {
1611 if (Op.getValueType().isVector())
1612 return LowerVectorINT_TO_FP(Op, DAG);
1614 // i128 conversions are libcalls.
1615 if (Op.getOperand(0).getValueType() == MVT::i128)
1618 // Other conversions are legal, unless it's to the completely software-based
1620 if (Op.getValueType() != MVT::f128)
1624 if (Op.getOpcode() == ISD::SINT_TO_FP)
1625 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1627 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1629 return LowerF128Call(Op, DAG, LC);
1632 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1633 SelectionDAG &DAG) const {
1634 // For iOS, we want to call an alternative entry point: __sincos_stret,
1635 // which returns the values in two S / D registers.
1637 SDValue Arg = Op.getOperand(0);
1638 EVT ArgVT = Arg.getValueType();
1639 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1646 Entry.isSExt = false;
1647 Entry.isZExt = false;
1648 Args.push_back(Entry);
1650 const char *LibcallName =
1651 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1652 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1654 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1655 TargetLowering::CallLoweringInfo CLI(DAG);
1656 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1657 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1659 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1660 return CallResult.first;
1663 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1664 if (Op.getValueType() != MVT::f16)
1667 assert(Op.getOperand(0).getValueType() == MVT::i16);
1670 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1671 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1673 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1674 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1678 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1679 if (OrigVT.getSizeInBits() >= 64)
1682 assert(OrigVT.isSimple() && "Expecting a simple value type");
1684 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1685 switch (OrigSimpleTy) {
1686 default: llvm_unreachable("Unexpected Vector Type");
1695 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1698 unsigned ExtOpcode) {
1699 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1700 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1701 // 64-bits we need to insert a new extension so that it will be 64-bits.
1702 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1703 if (OrigTy.getSizeInBits() >= 64)
1706 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1707 EVT NewVT = getExtensionTo64Bits(OrigTy);
1709 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1712 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1714 EVT VT = N->getValueType(0);
1716 if (N->getOpcode() != ISD::BUILD_VECTOR)
1719 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1720 SDNode *Elt = N->getOperand(i).getNode();
1721 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1722 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1723 unsigned HalfSize = EltSize / 2;
1725 if (!isIntN(HalfSize, C->getSExtValue()))
1728 if (!isUIntN(HalfSize, C->getZExtValue()))
1739 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1740 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1741 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1742 N->getOperand(0)->getValueType(0),
1746 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1747 EVT VT = N->getValueType(0);
1748 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1749 unsigned NumElts = VT.getVectorNumElements();
1750 MVT TruncVT = MVT::getIntegerVT(EltSize);
1751 SmallVector<SDValue, 8> Ops;
1752 for (unsigned i = 0; i != NumElts; ++i) {
1753 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1754 const APInt &CInt = C->getAPIntValue();
1755 // Element types smaller than 32 bits are not legal, so use i32 elements.
1756 // The values are implicitly truncated so sext vs. zext doesn't matter.
1757 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1759 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1760 MVT::getVectorVT(TruncVT, NumElts), Ops);
1763 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1764 if (N->getOpcode() == ISD::SIGN_EXTEND)
1766 if (isExtendedBUILD_VECTOR(N, DAG, true))
1771 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1772 if (N->getOpcode() == ISD::ZERO_EXTEND)
1774 if (isExtendedBUILD_VECTOR(N, DAG, false))
1779 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1780 unsigned Opcode = N->getOpcode();
1781 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1782 SDNode *N0 = N->getOperand(0).getNode();
1783 SDNode *N1 = N->getOperand(1).getNode();
1784 return N0->hasOneUse() && N1->hasOneUse() &&
1785 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1790 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1791 unsigned Opcode = N->getOpcode();
1792 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1793 SDNode *N0 = N->getOperand(0).getNode();
1794 SDNode *N1 = N->getOperand(1).getNode();
1795 return N0->hasOneUse() && N1->hasOneUse() &&
1796 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1801 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1802 // Multiplications are only custom-lowered for 128-bit vectors so that
1803 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1804 EVT VT = Op.getValueType();
1805 assert(VT.is128BitVector() && VT.isInteger() &&
1806 "unexpected type for custom-lowering ISD::MUL");
1807 SDNode *N0 = Op.getOperand(0).getNode();
1808 SDNode *N1 = Op.getOperand(1).getNode();
1809 unsigned NewOpc = 0;
1811 bool isN0SExt = isSignExtended(N0, DAG);
1812 bool isN1SExt = isSignExtended(N1, DAG);
1813 if (isN0SExt && isN1SExt)
1814 NewOpc = AArch64ISD::SMULL;
1816 bool isN0ZExt = isZeroExtended(N0, DAG);
1817 bool isN1ZExt = isZeroExtended(N1, DAG);
1818 if (isN0ZExt && isN1ZExt)
1819 NewOpc = AArch64ISD::UMULL;
1820 else if (isN1SExt || isN1ZExt) {
1821 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1822 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1823 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1824 NewOpc = AArch64ISD::SMULL;
1826 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1827 NewOpc = AArch64ISD::UMULL;
1829 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1831 NewOpc = AArch64ISD::UMULL;
1837 if (VT == MVT::v2i64)
1838 // Fall through to expand this. It is not legal.
1841 // Other vector multiplications are legal.
1846 // Legalize to a S/UMULL instruction
1849 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1851 Op0 = skipExtensionForVectorMULL(N0, DAG);
1852 assert(Op0.getValueType().is64BitVector() &&
1853 Op1.getValueType().is64BitVector() &&
1854 "unexpected types for extended operands to VMULL");
1855 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1857 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1858 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1859 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1860 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1861 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1862 EVT Op1VT = Op1.getValueType();
1863 return DAG.getNode(N0->getOpcode(), DL, VT,
1864 DAG.getNode(NewOpc, DL, VT,
1865 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1866 DAG.getNode(NewOpc, DL, VT,
1867 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1870 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1871 SelectionDAG &DAG) const {
1872 switch (Op.getOpcode()) {
1874 llvm_unreachable("unimplemented operand");
1877 return LowerBITCAST(Op, DAG);
1878 case ISD::GlobalAddress:
1879 return LowerGlobalAddress(Op, DAG);
1880 case ISD::GlobalTLSAddress:
1881 return LowerGlobalTLSAddress(Op, DAG);
1883 return LowerSETCC(Op, DAG);
1885 return LowerBR_CC(Op, DAG);
1887 return LowerSELECT(Op, DAG);
1888 case ISD::SELECT_CC:
1889 return LowerSELECT_CC(Op, DAG);
1890 case ISD::JumpTable:
1891 return LowerJumpTable(Op, DAG);
1892 case ISD::ConstantPool:
1893 return LowerConstantPool(Op, DAG);
1894 case ISD::BlockAddress:
1895 return LowerBlockAddress(Op, DAG);
1897 return LowerVASTART(Op, DAG);
1899 return LowerVACOPY(Op, DAG);
1901 return LowerVAARG(Op, DAG);
1906 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1913 return LowerXALUO(Op, DAG);
1915 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1917 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1919 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1921 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1923 return LowerFP_ROUND(Op, DAG);
1924 case ISD::FP_EXTEND:
1925 return LowerFP_EXTEND(Op, DAG);
1926 case ISD::FRAMEADDR:
1927 return LowerFRAMEADDR(Op, DAG);
1928 case ISD::RETURNADDR:
1929 return LowerRETURNADDR(Op, DAG);
1930 case ISD::INSERT_VECTOR_ELT:
1931 return LowerINSERT_VECTOR_ELT(Op, DAG);
1932 case ISD::EXTRACT_VECTOR_ELT:
1933 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1934 case ISD::BUILD_VECTOR:
1935 return LowerBUILD_VECTOR(Op, DAG);
1936 case ISD::VECTOR_SHUFFLE:
1937 return LowerVECTOR_SHUFFLE(Op, DAG);
1938 case ISD::EXTRACT_SUBVECTOR:
1939 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1943 return LowerVectorSRA_SRL_SHL(Op, DAG);
1944 case ISD::SHL_PARTS:
1945 return LowerShiftLeftParts(Op, DAG);
1946 case ISD::SRL_PARTS:
1947 case ISD::SRA_PARTS:
1948 return LowerShiftRightParts(Op, DAG);
1950 return LowerCTPOP(Op, DAG);
1951 case ISD::FCOPYSIGN:
1952 return LowerFCOPYSIGN(Op, DAG);
1954 return LowerVectorAND(Op, DAG);
1956 return LowerVectorOR(Op, DAG);
1958 return LowerXOR(Op, DAG);
1960 return LowerPREFETCH(Op, DAG);
1961 case ISD::SINT_TO_FP:
1962 case ISD::UINT_TO_FP:
1963 return LowerINT_TO_FP(Op, DAG);
1964 case ISD::FP_TO_SINT:
1965 case ISD::FP_TO_UINT:
1966 return LowerFP_TO_INT(Op, DAG);
1968 return LowerFSINCOS(Op, DAG);
1970 return LowerMUL(Op, DAG);
1974 /// getFunctionAlignment - Return the Log2 alignment of this function.
1975 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1979 //===----------------------------------------------------------------------===//
1980 // Calling Convention Implementation
1981 //===----------------------------------------------------------------------===//
1983 #include "AArch64GenCallingConv.inc"
1985 /// Selects the correct CCAssignFn for a given CallingConvention value.
1986 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1987 bool IsVarArg) const {
1990 llvm_unreachable("Unsupported calling convention.");
1991 case CallingConv::WebKit_JS:
1992 return CC_AArch64_WebKit_JS;
1993 case CallingConv::C:
1994 case CallingConv::Fast:
1995 if (!Subtarget->isTargetDarwin())
1996 return CC_AArch64_AAPCS;
1997 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2001 SDValue AArch64TargetLowering::LowerFormalArguments(
2002 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2003 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2004 SmallVectorImpl<SDValue> &InVals) const {
2005 MachineFunction &MF = DAG.getMachineFunction();
2006 MachineFrameInfo *MFI = MF.getFrameInfo();
2008 // Assign locations to all of the incoming arguments.
2009 SmallVector<CCValAssign, 16> ArgLocs;
2010 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2013 // At this point, Ins[].VT may already be promoted to i32. To correctly
2014 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2015 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2016 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2017 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2019 unsigned NumArgs = Ins.size();
2020 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2021 unsigned CurArgIdx = 0;
2022 for (unsigned i = 0; i != NumArgs; ++i) {
2023 MVT ValVT = Ins[i].VT;
2024 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
2025 CurArgIdx = Ins[i].OrigArgIndex;
2027 // Get type of the original argument.
2028 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2029 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2030 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2031 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2033 else if (ActualMVT == MVT::i16)
2036 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2038 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2039 assert(!Res && "Call operand has unhandled type");
2042 assert(ArgLocs.size() == Ins.size());
2043 SmallVector<SDValue, 16> ArgValues;
2044 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2045 CCValAssign &VA = ArgLocs[i];
2047 if (Ins[i].Flags.isByVal()) {
2048 // Byval is used for HFAs in the PCS, but the system should work in a
2049 // non-compliant manner for larger structs.
2050 EVT PtrTy = getPointerTy();
2051 int Size = Ins[i].Flags.getByValSize();
2052 unsigned NumRegs = (Size + 7) / 8;
2054 // FIXME: This works on big-endian for composite byvals, which are the common
2055 // case. It should also work for fundamental types too.
2057 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2058 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2059 InVals.push_back(FrameIdxN);
2064 if (VA.isRegLoc()) {
2065 // Arguments stored in registers.
2066 EVT RegVT = VA.getLocVT();
2069 const TargetRegisterClass *RC;
2071 if (RegVT == MVT::i32)
2072 RC = &AArch64::GPR32RegClass;
2073 else if (RegVT == MVT::i64)
2074 RC = &AArch64::GPR64RegClass;
2075 else if (RegVT == MVT::f16)
2076 RC = &AArch64::FPR16RegClass;
2077 else if (RegVT == MVT::f32)
2078 RC = &AArch64::FPR32RegClass;
2079 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2080 RC = &AArch64::FPR64RegClass;
2081 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2082 RC = &AArch64::FPR128RegClass;
2084 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2086 // Transform the arguments in physical registers into virtual ones.
2087 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2088 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2090 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2091 // to 64 bits. Insert an assert[sz]ext to capture this, then
2092 // truncate to the right size.
2093 switch (VA.getLocInfo()) {
2095 llvm_unreachable("Unknown loc info!");
2096 case CCValAssign::Full:
2098 case CCValAssign::BCvt:
2099 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2101 case CCValAssign::AExt:
2102 case CCValAssign::SExt:
2103 case CCValAssign::ZExt:
2104 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2105 // nodes after our lowering.
2106 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2110 InVals.push_back(ArgValue);
2112 } else { // VA.isRegLoc()
2113 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2114 unsigned ArgOffset = VA.getLocMemOffset();
2115 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2117 uint32_t BEAlign = 0;
2118 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2119 BEAlign = 8 - ArgSize;
2121 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2123 // Create load nodes to retrieve arguments from the stack.
2124 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2127 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2128 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2129 MVT MemVT = VA.getValVT();
2131 switch (VA.getLocInfo()) {
2134 case CCValAssign::BCvt:
2135 MemVT = VA.getLocVT();
2137 case CCValAssign::SExt:
2138 ExtType = ISD::SEXTLOAD;
2140 case CCValAssign::ZExt:
2141 ExtType = ISD::ZEXTLOAD;
2143 case CCValAssign::AExt:
2144 ExtType = ISD::EXTLOAD;
2148 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2149 MachinePointerInfo::getFixedStack(FI),
2150 MemVT, false, false, false, 0);
2152 InVals.push_back(ArgValue);
2158 if (!Subtarget->isTargetDarwin()) {
2159 // The AAPCS variadic function ABI is identical to the non-variadic
2160 // one. As a result there may be more arguments in registers and we should
2161 // save them for future reference.
2162 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2165 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2166 // This will point to the next argument passed via stack.
2167 unsigned StackOffset = CCInfo.getNextStackOffset();
2168 // We currently pass all varargs at 8-byte alignment.
2169 StackOffset = ((StackOffset + 7) & ~7);
2170 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2173 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2174 unsigned StackArgSize = CCInfo.getNextStackOffset();
2175 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2176 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2177 // This is a non-standard ABI so by fiat I say we're allowed to make full
2178 // use of the stack area to be popped, which must be aligned to 16 bytes in
2180 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2182 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2183 // a multiple of 16.
2184 FuncInfo->setArgumentStackToRestore(StackArgSize);
2186 // This realignment carries over to the available bytes below. Our own
2187 // callers will guarantee the space is free by giving an aligned value to
2190 // Even if we're not expected to free up the space, it's useful to know how
2191 // much is there while considering tail calls (because we can reuse it).
2192 FuncInfo->setBytesInStackArgArea(StackArgSize);
2197 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2198 SelectionDAG &DAG, SDLoc DL,
2199 SDValue &Chain) const {
2200 MachineFunction &MF = DAG.getMachineFunction();
2201 MachineFrameInfo *MFI = MF.getFrameInfo();
2202 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2204 SmallVector<SDValue, 8> MemOps;
2206 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2207 AArch64::X3, AArch64::X4, AArch64::X5,
2208 AArch64::X6, AArch64::X7 };
2209 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2210 unsigned FirstVariadicGPR =
2211 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
2213 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2215 if (GPRSaveSize != 0) {
2216 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2218 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2220 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2221 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2222 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2224 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2225 MachinePointerInfo::getStack(i * 8), false, false, 0);
2226 MemOps.push_back(Store);
2227 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2228 DAG.getConstant(8, getPointerTy()));
2231 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2232 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2234 if (Subtarget->hasFPARMv8()) {
2235 static const MCPhysReg FPRArgRegs[] = {
2236 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2237 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2238 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2239 unsigned FirstVariadicFPR =
2240 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
2242 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2244 if (FPRSaveSize != 0) {
2245 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2247 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2249 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2250 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2251 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2254 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2255 MachinePointerInfo::getStack(i * 16), false, false, 0);
2256 MemOps.push_back(Store);
2257 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2258 DAG.getConstant(16, getPointerTy()));
2261 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2262 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2265 if (!MemOps.empty()) {
2266 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2270 /// LowerCallResult - Lower the result values of a call into the
2271 /// appropriate copies out of appropriate physical registers.
2272 SDValue AArch64TargetLowering::LowerCallResult(
2273 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2274 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2275 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2276 SDValue ThisVal) const {
2277 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2278 ? RetCC_AArch64_WebKit_JS
2279 : RetCC_AArch64_AAPCS;
2280 // Assign locations to each value returned by this call.
2281 SmallVector<CCValAssign, 16> RVLocs;
2282 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2284 CCInfo.AnalyzeCallResult(Ins, RetCC);
2286 // Copy all of the result registers out of their specified physreg.
2287 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2288 CCValAssign VA = RVLocs[i];
2290 // Pass 'this' value directly from the argument to return value, to avoid
2291 // reg unit interference
2292 if (i == 0 && isThisReturn) {
2293 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2294 "unexpected return calling convention register assignment");
2295 InVals.push_back(ThisVal);
2300 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2301 Chain = Val.getValue(1);
2302 InFlag = Val.getValue(2);
2304 switch (VA.getLocInfo()) {
2306 llvm_unreachable("Unknown loc info!");
2307 case CCValAssign::Full:
2309 case CCValAssign::BCvt:
2310 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2314 InVals.push_back(Val);
2320 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2321 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2322 bool isCalleeStructRet, bool isCallerStructRet,
2323 const SmallVectorImpl<ISD::OutputArg> &Outs,
2324 const SmallVectorImpl<SDValue> &OutVals,
2325 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2326 // For CallingConv::C this function knows whether the ABI needs
2327 // changing. That's not true for other conventions so they will have to opt in
2329 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2332 const MachineFunction &MF = DAG.getMachineFunction();
2333 const Function *CallerF = MF.getFunction();
2334 CallingConv::ID CallerCC = CallerF->getCallingConv();
2335 bool CCMatch = CallerCC == CalleeCC;
2337 // Byval parameters hand the function a pointer directly into the stack area
2338 // we want to reuse during a tail call. Working around this *is* possible (see
2339 // X86) but less efficient and uglier in LowerCall.
2340 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2341 e = CallerF->arg_end();
2343 if (i->hasByValAttr())
2346 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2347 if (IsTailCallConvention(CalleeCC) && CCMatch)
2352 // Externally-defined functions with weak linkage should not be
2353 // tail-called on AArch64 when the OS does not support dynamic
2354 // pre-emption of symbols, as the AAELF spec requires normal calls
2355 // to undefined weak functions to be replaced with a NOP or jump to the
2356 // next instruction. The behaviour of branch instructions in this
2357 // situation (as used for tail calls) is implementation-defined, so we
2358 // cannot rely on the linker replacing the tail call with a return.
2359 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2360 const GlobalValue *GV = G->getGlobal();
2361 if (GV->hasExternalWeakLinkage())
2365 // Now we search for cases where we can use a tail call without changing the
2366 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2369 // I want anyone implementing a new calling convention to think long and hard
2370 // about this assert.
2371 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2372 "Unexpected variadic calling convention");
2374 if (isVarArg && !Outs.empty()) {
2375 // At least two cases here: if caller is fastcc then we can't have any
2376 // memory arguments (we'd be expected to clean up the stack afterwards). If
2377 // caller is C then we could potentially use its argument area.
2379 // FIXME: for now we take the most conservative of these in both cases:
2380 // disallow all variadic memory operands.
2381 SmallVector<CCValAssign, 16> ArgLocs;
2382 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2385 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2387 if (!ArgLocs[i].isRegLoc())
2391 // If the calling conventions do not match, then we'd better make sure the
2392 // results are returned in the same way as what the caller expects.
2394 SmallVector<CCValAssign, 16> RVLocs1;
2395 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2397 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2399 SmallVector<CCValAssign, 16> RVLocs2;
2400 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2402 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2404 if (RVLocs1.size() != RVLocs2.size())
2406 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2407 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2409 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2411 if (RVLocs1[i].isRegLoc()) {
2412 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2415 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2421 // Nothing more to check if the callee is taking no arguments
2425 SmallVector<CCValAssign, 16> ArgLocs;
2426 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2429 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2431 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2433 // If the stack arguments for this call would fit into our own save area then
2434 // the call can be made tail.
2435 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2438 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2440 MachineFrameInfo *MFI,
2441 int ClobberedFI) const {
2442 SmallVector<SDValue, 8> ArgChains;
2443 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2444 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2446 // Include the original chain at the beginning of the list. When this is
2447 // used by target LowerCall hooks, this helps legalize find the
2448 // CALLSEQ_BEGIN node.
2449 ArgChains.push_back(Chain);
2451 // Add a chain value for each stack argument corresponding
2452 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2453 UE = DAG.getEntryNode().getNode()->use_end();
2455 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2456 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2457 if (FI->getIndex() < 0) {
2458 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2459 int64_t InLastByte = InFirstByte;
2460 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2462 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2463 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2464 ArgChains.push_back(SDValue(L, 1));
2467 // Build a tokenfactor for all the chains.
2468 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2471 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2472 bool TailCallOpt) const {
2473 return CallCC == CallingConv::Fast && TailCallOpt;
2476 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2477 return CallCC == CallingConv::Fast;
2480 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2481 /// and add input and output parameter nodes.
2483 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2484 SmallVectorImpl<SDValue> &InVals) const {
2485 SelectionDAG &DAG = CLI.DAG;
2487 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2488 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2489 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2490 SDValue Chain = CLI.Chain;
2491 SDValue Callee = CLI.Callee;
2492 bool &IsTailCall = CLI.IsTailCall;
2493 CallingConv::ID CallConv = CLI.CallConv;
2494 bool IsVarArg = CLI.IsVarArg;
2496 MachineFunction &MF = DAG.getMachineFunction();
2497 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2498 bool IsThisReturn = false;
2500 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2501 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2502 bool IsSibCall = false;
2505 // Check if it's really possible to do a tail call.
2506 IsTailCall = isEligibleForTailCallOptimization(
2507 Callee, CallConv, IsVarArg, IsStructRet,
2508 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2509 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2510 report_fatal_error("failed to perform tail call elimination on a call "
2511 "site marked musttail");
2513 // A sibling call is one where we're under the usual C ABI and not planning
2514 // to change that but can still do a tail call:
2515 if (!TailCallOpt && IsTailCall)
2522 // Analyze operands of the call, assigning locations to each operand.
2523 SmallVector<CCValAssign, 16> ArgLocs;
2524 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2528 // Handle fixed and variable vector arguments differently.
2529 // Variable vector arguments always go into memory.
2530 unsigned NumArgs = Outs.size();
2532 for (unsigned i = 0; i != NumArgs; ++i) {
2533 MVT ArgVT = Outs[i].VT;
2534 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2535 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2536 /*IsVarArg=*/ !Outs[i].IsFixed);
2537 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2538 assert(!Res && "Call operand has unhandled type");
2542 // At this point, Outs[].VT may already be promoted to i32. To correctly
2543 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2544 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2545 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2546 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2548 unsigned NumArgs = Outs.size();
2549 for (unsigned i = 0; i != NumArgs; ++i) {
2550 MVT ValVT = Outs[i].VT;
2551 // Get type of the original argument.
2552 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2553 /*AllowUnknown*/ true);
2554 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2555 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2556 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2557 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2559 else if (ActualMVT == MVT::i16)
2562 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2563 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2564 assert(!Res && "Call operand has unhandled type");
2569 // Get a count of how many bytes are to be pushed on the stack.
2570 unsigned NumBytes = CCInfo.getNextStackOffset();
2573 // Since we're not changing the ABI to make this a tail call, the memory
2574 // operands are already available in the caller's incoming argument space.
2578 // FPDiff is the byte offset of the call's argument area from the callee's.
2579 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2580 // by this amount for a tail call. In a sibling call it must be 0 because the
2581 // caller will deallocate the entire stack and the callee still expects its
2582 // arguments to begin at SP+0. Completely unused for non-tail calls.
2585 if (IsTailCall && !IsSibCall) {
2586 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2588 // Since callee will pop argument stack as a tail call, we must keep the
2589 // popped size 16-byte aligned.
2590 NumBytes = RoundUpToAlignment(NumBytes, 16);
2592 // FPDiff will be negative if this tail call requires more space than we
2593 // would automatically have in our incoming argument space. Positive if we
2594 // can actually shrink the stack.
2595 FPDiff = NumReusableBytes - NumBytes;
2597 // The stack pointer must be 16-byte aligned at all times it's used for a
2598 // memory operation, which in practice means at *all* times and in
2599 // particular across call boundaries. Therefore our own arguments started at
2600 // a 16-byte aligned SP and the delta applied for the tail call should
2601 // satisfy the same constraint.
2602 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2605 // Adjust the stack pointer for the new arguments...
2606 // These operations are automatically eliminated by the prolog/epilog pass
2609 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2611 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2613 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2614 SmallVector<SDValue, 8> MemOpChains;
2616 // Walk the register/memloc assignments, inserting copies/loads.
2617 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2618 ++i, ++realArgIdx) {
2619 CCValAssign &VA = ArgLocs[i];
2620 SDValue Arg = OutVals[realArgIdx];
2621 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2623 // Promote the value if needed.
2624 switch (VA.getLocInfo()) {
2626 llvm_unreachable("Unknown loc info!");
2627 case CCValAssign::Full:
2629 case CCValAssign::SExt:
2630 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2632 case CCValAssign::ZExt:
2633 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2635 case CCValAssign::AExt:
2636 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2637 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2638 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2639 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2641 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2643 case CCValAssign::BCvt:
2644 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2646 case CCValAssign::FPExt:
2647 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2651 if (VA.isRegLoc()) {
2652 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2653 assert(VA.getLocVT() == MVT::i64 &&
2654 "unexpected calling convention register assignment");
2655 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2656 "unexpected use of 'returned'");
2657 IsThisReturn = true;
2659 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2661 assert(VA.isMemLoc());
2664 MachinePointerInfo DstInfo;
2666 // FIXME: This works on big-endian for composite byvals, which are the
2667 // common case. It should also work for fundamental types too.
2668 uint32_t BEAlign = 0;
2669 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2670 : VA.getValVT().getSizeInBits();
2671 OpSize = (OpSize + 7) / 8;
2672 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2674 BEAlign = 8 - OpSize;
2676 unsigned LocMemOffset = VA.getLocMemOffset();
2677 int32_t Offset = LocMemOffset + BEAlign;
2678 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2679 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2682 Offset = Offset + FPDiff;
2683 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2685 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2686 DstInfo = MachinePointerInfo::getFixedStack(FI);
2688 // Make sure any stack arguments overlapping with where we're storing
2689 // are loaded before this eventual operation. Otherwise they'll be
2691 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2693 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2695 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2696 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2699 if (Outs[i].Flags.isByVal()) {
2701 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2702 SDValue Cpy = DAG.getMemcpy(
2703 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2705 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2707 MemOpChains.push_back(Cpy);
2709 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2710 // promoted to a legal register type i32, we should truncate Arg back to
2712 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2713 VA.getValVT() == MVT::i16)
2714 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2717 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2718 MemOpChains.push_back(Store);
2723 if (!MemOpChains.empty())
2724 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2726 // Build a sequence of copy-to-reg nodes chained together with token chain
2727 // and flag operands which copy the outgoing args into the appropriate regs.
2729 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2730 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2731 RegsToPass[i].second, InFlag);
2732 InFlag = Chain.getValue(1);
2735 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2736 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2737 // node so that legalize doesn't hack it.
2738 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2739 Subtarget->isTargetMachO()) {
2740 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2741 const GlobalValue *GV = G->getGlobal();
2742 bool InternalLinkage = GV->hasInternalLinkage();
2743 if (InternalLinkage)
2744 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2746 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2748 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2750 } else if (ExternalSymbolSDNode *S =
2751 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2752 const char *Sym = S->getSymbol();
2754 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2755 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2757 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2758 const GlobalValue *GV = G->getGlobal();
2759 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2760 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2761 const char *Sym = S->getSymbol();
2762 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2765 // We don't usually want to end the call-sequence here because we would tidy
2766 // the frame up *after* the call, however in the ABI-changing tail-call case
2767 // we've carefully laid out the parameters so that when sp is reset they'll be
2768 // in the correct location.
2769 if (IsTailCall && !IsSibCall) {
2770 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2771 DAG.getIntPtrConstant(0, true), InFlag, DL);
2772 InFlag = Chain.getValue(1);
2775 std::vector<SDValue> Ops;
2776 Ops.push_back(Chain);
2777 Ops.push_back(Callee);
2780 // Each tail call may have to adjust the stack by a different amount, so
2781 // this information must travel along with the operation for eventual
2782 // consumption by emitEpilogue.
2783 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2786 // Add argument registers to the end of the list so that they are known live
2788 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2789 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2790 RegsToPass[i].second.getValueType()));
2792 // Add a register mask operand representing the call-preserved registers.
2793 const uint32_t *Mask;
2794 const TargetRegisterInfo *TRI =
2795 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2796 const AArch64RegisterInfo *ARI =
2797 static_cast<const AArch64RegisterInfo *>(TRI);
2799 // For 'this' returns, use the X0-preserving mask if applicable
2800 Mask = ARI->getThisReturnPreservedMask(CallConv);
2802 IsThisReturn = false;
2803 Mask = ARI->getCallPreservedMask(CallConv);
2806 Mask = ARI->getCallPreservedMask(CallConv);
2808 assert(Mask && "Missing call preserved mask for calling convention");
2809 Ops.push_back(DAG.getRegisterMask(Mask));
2811 if (InFlag.getNode())
2812 Ops.push_back(InFlag);
2814 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2816 // If we're doing a tall call, use a TC_RETURN here rather than an
2817 // actual call instruction.
2819 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2821 // Returns a chain and a flag for retval copy to use.
2822 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2823 InFlag = Chain.getValue(1);
2825 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2826 ? RoundUpToAlignment(NumBytes, 16)
2829 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2830 DAG.getIntPtrConstant(CalleePopBytes, true),
2833 InFlag = Chain.getValue(1);
2835 // Handle result values, copying them out of physregs into vregs that we
2837 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2838 InVals, IsThisReturn,
2839 IsThisReturn ? OutVals[0] : SDValue());
2842 bool AArch64TargetLowering::CanLowerReturn(
2843 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2844 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2845 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2846 ? RetCC_AArch64_WebKit_JS
2847 : RetCC_AArch64_AAPCS;
2848 SmallVector<CCValAssign, 16> RVLocs;
2849 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2850 return CCInfo.CheckReturn(Outs, RetCC);
2854 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2856 const SmallVectorImpl<ISD::OutputArg> &Outs,
2857 const SmallVectorImpl<SDValue> &OutVals,
2858 SDLoc DL, SelectionDAG &DAG) const {
2859 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2860 ? RetCC_AArch64_WebKit_JS
2861 : RetCC_AArch64_AAPCS;
2862 SmallVector<CCValAssign, 16> RVLocs;
2863 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2865 CCInfo.AnalyzeReturn(Outs, RetCC);
2867 // Copy the result values into the output registers.
2869 SmallVector<SDValue, 4> RetOps(1, Chain);
2870 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2871 ++i, ++realRVLocIdx) {
2872 CCValAssign &VA = RVLocs[i];
2873 assert(VA.isRegLoc() && "Can only return in registers!");
2874 SDValue Arg = OutVals[realRVLocIdx];
2876 switch (VA.getLocInfo()) {
2878 llvm_unreachable("Unknown loc info!");
2879 case CCValAssign::Full:
2880 if (Outs[i].ArgVT == MVT::i1) {
2881 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2882 // value. This is strictly redundant on Darwin (which uses "zeroext
2883 // i1"), but will be optimised out before ISel.
2884 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2885 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2888 case CCValAssign::BCvt:
2889 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2893 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2894 Flag = Chain.getValue(1);
2895 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2898 RetOps[0] = Chain; // Update chain.
2900 // Add the flag if we have it.
2902 RetOps.push_back(Flag);
2904 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2907 //===----------------------------------------------------------------------===//
2908 // Other Lowering Code
2909 //===----------------------------------------------------------------------===//
2911 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2912 SelectionDAG &DAG) const {
2913 EVT PtrVT = getPointerTy();
2915 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2916 const GlobalValue *GV = GN->getGlobal();
2917 unsigned char OpFlags =
2918 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2920 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2921 "unexpected offset in global node");
2923 // This also catched the large code model case for Darwin.
2924 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2925 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2926 // FIXME: Once remat is capable of dealing with instructions with register
2927 // operands, expand this into two nodes instead of using a wrapper node.
2928 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2931 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2932 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2933 "use of MO_CONSTPOOL only supported on small model");
2934 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2935 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2936 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2937 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2938 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2939 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2940 MachinePointerInfo::getConstantPool(),
2941 /*isVolatile=*/ false,
2942 /*isNonTemporal=*/ true,
2943 /*isInvariant=*/ true, 8);
2944 if (GN->getOffset() != 0)
2945 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2946 DAG.getConstant(GN->getOffset(), PtrVT));
2950 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2951 const unsigned char MO_NC = AArch64II::MO_NC;
2953 AArch64ISD::WrapperLarge, DL, PtrVT,
2954 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2955 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2956 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2957 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2959 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2960 // the only correct model on Darwin.
2961 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2962 OpFlags | AArch64II::MO_PAGE);
2963 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2964 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2966 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2967 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2971 /// \brief Convert a TLS address reference into the correct sequence of loads
2972 /// and calls to compute the variable's address (for Darwin, currently) and
2973 /// return an SDValue containing the final node.
2975 /// Darwin only has one TLS scheme which must be capable of dealing with the
2976 /// fully general situation, in the worst case. This means:
2977 /// + "extern __thread" declaration.
2978 /// + Defined in a possibly unknown dynamic library.
2980 /// The general system is that each __thread variable has a [3 x i64] descriptor
2981 /// which contains information used by the runtime to calculate the address. The
2982 /// only part of this the compiler needs to know about is the first xword, which
2983 /// contains a function pointer that must be called with the address of the
2984 /// entire descriptor in "x0".
2986 /// Since this descriptor may be in a different unit, in general even the
2987 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2989 /// adrp x0, _var@TLVPPAGE
2990 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2991 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2992 /// ; the function pointer
2993 /// blr x1 ; Uses descriptor address in x0
2994 /// ; Address of _var is now in x0.
2996 /// If the address of _var's descriptor *is* known to the linker, then it can
2997 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2998 /// a slight efficiency gain.
3000 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3001 SelectionDAG &DAG) const {
3002 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3005 MVT PtrVT = getPointerTy();
3006 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3009 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3010 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3012 // The first entry in the descriptor is a function pointer that we must call
3013 // to obtain the address of the variable.
3014 SDValue Chain = DAG.getEntryNode();
3015 SDValue FuncTLVGet =
3016 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3017 false, true, true, 8);
3018 Chain = FuncTLVGet.getValue(1);
3020 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3021 MFI->setAdjustsStack(true);
3023 // TLS calls preserve all registers except those that absolutely must be
3024 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3026 const TargetRegisterInfo *TRI =
3027 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3028 const AArch64RegisterInfo *ARI =
3029 static_cast<const AArch64RegisterInfo *>(TRI);
3030 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
3032 // Finally, we can make the call. This is just a degenerate version of a
3033 // normal AArch64 call node: x0 takes the address of the descriptor, and
3034 // returns the address of the variable in this thread.
3035 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3037 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3038 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3039 DAG.getRegisterMask(Mask), Chain.getValue(1));
3040 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3043 /// When accessing thread-local variables under either the general-dynamic or
3044 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3045 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3046 /// is a function pointer to carry out the resolution. This function takes the
3047 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
3048 /// other registers (except LR, NZCV) are preserved.
3050 /// Thus, the ideal call sequence on AArch64 is:
3052 /// adrp x0, :tlsdesc:thread_var
3053 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
3054 /// add x0, x0, :tlsdesc_lo12:thread_var
3055 /// .tlsdesccall thread_var
3057 /// (TPIDR_EL0 offset now in x0).
3059 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
3060 /// relocation to help the linker relax this sequence if it turns out to be too
3063 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
3065 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
3066 SDValue DescAddr, SDLoc DL,
3067 SelectionDAG &DAG) const {
3068 EVT PtrVT = getPointerTy();
3070 // The function we need to call is simply the first entry in the GOT for this
3071 // descriptor, load it in preparation.
3072 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
3074 // TLS calls preserve all registers except those that absolutely must be
3075 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3077 const TargetRegisterInfo *TRI =
3078 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3079 const AArch64RegisterInfo *ARI =
3080 static_cast<const AArch64RegisterInfo *>(TRI);
3081 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
3083 // The function takes only one argument: the address of the descriptor itself
3085 SDValue Glue, Chain;
3086 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
3087 Glue = Chain.getValue(1);
3089 // We're now ready to populate the argument list, as with a normal call:
3090 SmallVector<SDValue, 6> Ops;
3091 Ops.push_back(Chain);
3092 Ops.push_back(Func);
3093 Ops.push_back(SymAddr);
3094 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
3095 Ops.push_back(DAG.getRegisterMask(Mask));
3096 Ops.push_back(Glue);
3098 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3099 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
3100 Glue = Chain.getValue(1);
3102 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3106 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3107 SelectionDAG &DAG) const {
3108 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3109 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3110 "ELF TLS only supported in small memory model");
3111 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3113 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3116 EVT PtrVT = getPointerTy();
3118 const GlobalValue *GV = GA->getGlobal();
3120 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3122 if (Model == TLSModel::LocalExec) {
3123 SDValue HiVar = DAG.getTargetGlobalAddress(
3124 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
3125 SDValue LoVar = DAG.getTargetGlobalAddress(
3127 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
3129 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
3130 DAG.getTargetConstant(16, MVT::i32)),
3132 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
3133 DAG.getTargetConstant(0, MVT::i32)),
3135 } else if (Model == TLSModel::InitialExec) {
3136 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3137 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3138 } else if (Model == TLSModel::LocalDynamic) {
3139 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3140 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3141 // the beginning of the module's TLS region, followed by a DTPREL offset
3144 // These accesses will need deduplicating if there's more than one.
3145 AArch64FunctionInfo *MFI =
3146 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3147 MFI->incNumLocalDynamicTLSAccesses();
3149 // Accesses used in this sequence go via the TLS descriptor which lives in
3150 // the GOT. Prepare an address we can use to handle this.
3151 SDValue HiDesc = DAG.getTargetExternalSymbol(
3152 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
3153 SDValue LoDesc = DAG.getTargetExternalSymbol(
3154 "_TLS_MODULE_BASE_", PtrVT,
3155 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3157 // First argument to the descriptor call is the address of the descriptor
3159 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
3160 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
3162 // The call needs a relocation too for linker relaxation. It doesn't make
3163 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3165 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3168 // Now we can calculate the offset from TPIDR_EL0 to this module's
3169 // thread-local area.
3170 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
3172 // Now use :dtprel_whatever: operations to calculate this variable's offset
3173 // in its thread-storage area.
3174 SDValue HiVar = DAG.getTargetGlobalAddress(
3175 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
3176 SDValue LoVar = DAG.getTargetGlobalAddress(
3177 GV, DL, MVT::i64, 0,
3178 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
3181 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
3182 DAG.getTargetConstant(16, MVT::i32)),
3185 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
3186 DAG.getTargetConstant(0, MVT::i32)),
3189 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
3190 } else if (Model == TLSModel::GeneralDynamic) {
3191 // Accesses used in this sequence go via the TLS descriptor which lives in
3192 // the GOT. Prepare an address we can use to handle this.
3193 SDValue HiDesc = DAG.getTargetGlobalAddress(
3194 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
3195 SDValue LoDesc = DAG.getTargetGlobalAddress(
3197 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3199 // First argument to the descriptor call is the address of the descriptor
3201 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
3202 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
3204 // The call needs a relocation too for linker relaxation. It doesn't make
3205 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3208 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3210 // Finally we can make a call to calculate the offset from tpidr_el0.
3211 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
3213 llvm_unreachable("Unsupported ELF TLS access model");
3215 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3218 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3219 SelectionDAG &DAG) const {
3220 if (Subtarget->isTargetDarwin())
3221 return LowerDarwinGlobalTLSAddress(Op, DAG);
3222 else if (Subtarget->isTargetELF())
3223 return LowerELFGlobalTLSAddress(Op, DAG);
3225 llvm_unreachable("Unexpected platform trying to use TLS");
3227 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3228 SDValue Chain = Op.getOperand(0);
3229 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3230 SDValue LHS = Op.getOperand(2);
3231 SDValue RHS = Op.getOperand(3);
3232 SDValue Dest = Op.getOperand(4);
3235 // Handle f128 first, since lowering it will result in comparing the return
3236 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3237 // is expecting to deal with.
3238 if (LHS.getValueType() == MVT::f128) {
3239 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3241 // If softenSetCCOperands returned a scalar, we need to compare the result
3242 // against zero to select between true and false values.
3243 if (!RHS.getNode()) {
3244 RHS = DAG.getConstant(0, LHS.getValueType());
3249 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3251 unsigned Opc = LHS.getOpcode();
3252 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3253 cast<ConstantSDNode>(RHS)->isOne() &&
3254 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3255 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3256 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3257 "Unexpected condition code.");
3258 // Only lower legal XALUO ops.
3259 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3262 // The actual operation with overflow check.
3263 AArch64CC::CondCode OFCC;
3264 SDValue Value, Overflow;
3265 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3267 if (CC == ISD::SETNE)
3268 OFCC = getInvertedCondCode(OFCC);
3269 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3271 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
3275 if (LHS.getValueType().isInteger()) {
3276 assert((LHS.getValueType() == RHS.getValueType()) &&
3277 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3279 // If the RHS of the comparison is zero, we can potentially fold this
3280 // to a specialized branch.
3281 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3282 if (RHSC && RHSC->getZExtValue() == 0) {
3283 if (CC == ISD::SETEQ) {
3284 // See if we can use a TBZ to fold in an AND as well.
3285 // TBZ has a smaller branch displacement than CBZ. If the offset is
3286 // out of bounds, a late MI-layer pass rewrites branches.
3287 // 403.gcc is an example that hits this case.
3288 if (LHS.getOpcode() == ISD::AND &&
3289 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3290 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3291 SDValue Test = LHS.getOperand(0);
3292 uint64_t Mask = LHS.getConstantOperandVal(1);
3293 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3294 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3297 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3298 } else if (CC == ISD::SETNE) {
3299 // See if we can use a TBZ to fold in an AND as well.
3300 // TBZ has a smaller branch displacement than CBZ. If the offset is
3301 // out of bounds, a late MI-layer pass rewrites branches.
3302 // 403.gcc is an example that hits this case.
3303 if (LHS.getOpcode() == ISD::AND &&
3304 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3305 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3306 SDValue Test = LHS.getOperand(0);
3307 uint64_t Mask = LHS.getConstantOperandVal(1);
3308 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3309 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3312 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3313 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3314 // Don't combine AND since emitComparison converts the AND to an ANDS
3315 // (a.k.a. TST) and the test in the test bit and branch instruction
3316 // becomes redundant. This would also increase register pressure.
3317 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3318 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3319 DAG.getConstant(Mask, MVT::i64), Dest);
3322 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3323 LHS.getOpcode() != ISD::AND) {
3324 // Don't combine AND since emitComparison converts the AND to an ANDS
3325 // (a.k.a. TST) and the test in the test bit and branch instruction
3326 // becomes redundant. This would also increase register pressure.
3327 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3328 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3329 DAG.getConstant(Mask, MVT::i64), Dest);
3333 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3334 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3338 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3340 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3341 // clean. Some of them require two branches to implement.
3342 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3343 AArch64CC::CondCode CC1, CC2;
3344 changeFPCCToAArch64CC(CC, CC1, CC2);
3345 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3347 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3348 if (CC2 != AArch64CC::AL) {
3349 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3350 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3357 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3358 SelectionDAG &DAG) const {
3359 EVT VT = Op.getValueType();
3362 SDValue In1 = Op.getOperand(0);
3363 SDValue In2 = Op.getOperand(1);
3364 EVT SrcVT = In2.getValueType();
3366 if (SrcVT == MVT::f32 && VT == MVT::f64)
3367 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3368 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3369 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3371 // FIXME: Src type is different, bail out for now. Can VT really be a
3378 SDValue EltMask, VecVal1, VecVal2;
3379 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3382 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3384 if (!VT.isVector()) {
3385 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3386 DAG.getUNDEF(VecVT), In1);
3387 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3388 DAG.getUNDEF(VecVT), In2);
3390 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3391 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3393 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3397 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3398 // immediate moves cannot materialize that in a single instruction for
3399 // 64-bit elements. Instead, materialize zero and then negate it.
3400 EltMask = DAG.getConstant(0, EltVT);
3402 if (!VT.isVector()) {
3403 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3404 DAG.getUNDEF(VecVT), In1);
3405 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3406 DAG.getUNDEF(VecVT), In2);
3408 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3409 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3412 llvm_unreachable("Invalid type for copysign!");
3415 std::vector<SDValue> BuildVectorOps;
3416 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3417 BuildVectorOps.push_back(EltMask);
3419 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3421 // If we couldn't materialize the mask above, then the mask vector will be
3422 // the zero vector, and we need to negate it here.
3423 if (VT == MVT::f64 || VT == MVT::v2f64) {
3424 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3425 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3426 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3430 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3433 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3434 else if (VT == MVT::f64)
3435 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3437 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3440 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3441 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3442 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3445 // While there is no integer popcount instruction, it can
3446 // be more efficiently lowered to the following sequence that uses
3447 // AdvSIMD registers/instructions as long as the copies to/from
3448 // the AdvSIMD registers are cheap.
3449 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3450 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3451 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3452 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3453 SDValue Val = Op.getOperand(0);
3455 EVT VT = Op.getValueType();
3456 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3459 if (VT == MVT::i32) {
3460 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3461 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3464 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3467 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3468 SDValue UaddLV = DAG.getNode(
3469 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3470 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3473 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3477 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3479 if (Op.getValueType().isVector())
3480 return LowerVSETCC(Op, DAG);
3482 SDValue LHS = Op.getOperand(0);
3483 SDValue RHS = Op.getOperand(1);
3484 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3487 // We chose ZeroOrOneBooleanContents, so use zero and one.
3488 EVT VT = Op.getValueType();
3489 SDValue TVal = DAG.getConstant(1, VT);
3490 SDValue FVal = DAG.getConstant(0, VT);
3492 // Handle f128 first, since one possible outcome is a normal integer
3493 // comparison which gets picked up by the next if statement.
3494 if (LHS.getValueType() == MVT::f128) {
3495 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3497 // If softenSetCCOperands returned a scalar, use it.
3498 if (!RHS.getNode()) {
3499 assert(LHS.getValueType() == Op.getValueType() &&
3500 "Unexpected setcc expansion!");
3505 if (LHS.getValueType().isInteger()) {
3508 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3510 // Note that we inverted the condition above, so we reverse the order of
3511 // the true and false operands here. This will allow the setcc to be
3512 // matched to a single CSINC instruction.
3513 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3516 // Now we know we're dealing with FP values.
3517 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3519 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3520 // and do the comparison.
3521 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3523 AArch64CC::CondCode CC1, CC2;
3524 changeFPCCToAArch64CC(CC, CC1, CC2);
3525 if (CC2 == AArch64CC::AL) {
3526 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3527 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3529 // Note that we inverted the condition above, so we reverse the order of
3530 // the true and false operands here. This will allow the setcc to be
3531 // matched to a single CSINC instruction.
3532 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3534 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3535 // totally clean. Some of them require two CSELs to implement. As is in
3536 // this case, we emit the first CSEL and then emit a second using the output
3537 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3539 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3540 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3542 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3544 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3545 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3549 /// A SELECT_CC operation is really some kind of max or min if both values being
3550 /// compared are, in some sense, equal to the results in either case. However,
3551 /// it is permissible to compare f32 values and produce directly extended f64
3554 /// Extending the comparison operands would also be allowed, but is less likely
3555 /// to happen in practice since their use is right here. Note that truncate
3556 /// operations would *not* be semantically equivalent.
3557 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3561 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3562 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3563 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3564 Result.getValueType() == MVT::f64) {
3566 APFloat CmpVal = CCmp->getValueAPF();
3567 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3568 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3571 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3574 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3575 SelectionDAG &DAG) const {
3576 SDValue CC = Op->getOperand(0);
3577 SDValue TVal = Op->getOperand(1);
3578 SDValue FVal = Op->getOperand(2);
3581 unsigned Opc = CC.getOpcode();
3582 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3584 if (CC.getResNo() == 1 &&
3585 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3586 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3587 // Only lower legal XALUO ops.
3588 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3591 AArch64CC::CondCode OFCC;
3592 SDValue Value, Overflow;
3593 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3594 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3596 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3600 if (CC.getOpcode() == ISD::SETCC)
3601 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3602 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3604 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3608 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3609 SelectionDAG &DAG) const {
3610 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3611 SDValue LHS = Op.getOperand(0);
3612 SDValue RHS = Op.getOperand(1);
3613 SDValue TVal = Op.getOperand(2);
3614 SDValue FVal = Op.getOperand(3);
3617 // Handle f128 first, because it will result in a comparison of some RTLIB
3618 // call result against zero.
3619 if (LHS.getValueType() == MVT::f128) {
3620 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3622 // If softenSetCCOperands returned a scalar, we need to compare the result
3623 // against zero to select between true and false values.
3624 if (!RHS.getNode()) {
3625 RHS = DAG.getConstant(0, LHS.getValueType());
3630 // Handle integers first.
3631 if (LHS.getValueType().isInteger()) {
3632 assert((LHS.getValueType() == RHS.getValueType()) &&
3633 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3635 unsigned Opcode = AArch64ISD::CSEL;
3637 // If both the TVal and the FVal are constants, see if we can swap them in
3638 // order to for a CSINV or CSINC out of them.
3639 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3640 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3642 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3643 std::swap(TVal, FVal);
3644 std::swap(CTVal, CFVal);
3645 CC = ISD::getSetCCInverse(CC, true);
3646 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3647 std::swap(TVal, FVal);
3648 std::swap(CTVal, CFVal);
3649 CC = ISD::getSetCCInverse(CC, true);
3650 } else if (TVal.getOpcode() == ISD::XOR) {
3651 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3652 // with a CSINV rather than a CSEL.
3653 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3655 if (CVal && CVal->isAllOnesValue()) {
3656 std::swap(TVal, FVal);
3657 std::swap(CTVal, CFVal);
3658 CC = ISD::getSetCCInverse(CC, true);
3660 } else if (TVal.getOpcode() == ISD::SUB) {
3661 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3662 // that we can match with a CSNEG rather than a CSEL.
3663 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3665 if (CVal && CVal->isNullValue()) {
3666 std::swap(TVal, FVal);
3667 std::swap(CTVal, CFVal);
3668 CC = ISD::getSetCCInverse(CC, true);
3670 } else if (CTVal && CFVal) {
3671 const int64_t TrueVal = CTVal->getSExtValue();
3672 const int64_t FalseVal = CFVal->getSExtValue();
3675 // If both TVal and FVal are constants, see if FVal is the
3676 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3677 // instead of a CSEL in that case.
3678 if (TrueVal == ~FalseVal) {
3679 Opcode = AArch64ISD::CSINV;
3680 } else if (TrueVal == -FalseVal) {
3681 Opcode = AArch64ISD::CSNEG;
3682 } else if (TVal.getValueType() == MVT::i32) {
3683 // If our operands are only 32-bit wide, make sure we use 32-bit
3684 // arithmetic for the check whether we can use CSINC. This ensures that
3685 // the addition in the check will wrap around properly in case there is
3686 // an overflow (which would not be the case if we do the check with
3687 // 64-bit arithmetic).
3688 const uint32_t TrueVal32 = CTVal->getZExtValue();
3689 const uint32_t FalseVal32 = CFVal->getZExtValue();
3691 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3692 Opcode = AArch64ISD::CSINC;
3694 if (TrueVal32 > FalseVal32) {
3698 // 64-bit check whether we can use CSINC.
3699 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3700 Opcode = AArch64ISD::CSINC;
3702 if (TrueVal > FalseVal) {
3707 // Swap TVal and FVal if necessary.
3709 std::swap(TVal, FVal);
3710 std::swap(CTVal, CFVal);
3711 CC = ISD::getSetCCInverse(CC, true);
3714 if (Opcode != AArch64ISD::CSEL) {
3715 // Drop FVal since we can get its value by simply inverting/negating
3722 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3724 EVT VT = Op.getValueType();
3725 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3728 // Now we know we're dealing with FP values.
3729 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3730 assert(LHS.getValueType() == RHS.getValueType());
3731 EVT VT = Op.getValueType();
3733 // Try to match this select into a max/min operation, which have dedicated
3734 // opcode in the instruction set.
3735 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3737 if (getTargetMachine().Options.NoNaNsFPMath) {
3738 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3739 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3740 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3741 CC = ISD::getSetCCSwappedOperands(CC);
3742 std::swap(MinMaxLHS, MinMaxRHS);
3745 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3746 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3756 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3764 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3770 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3771 // and do the comparison.
3772 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3774 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3775 // clean. Some of them require two CSELs to implement.
3776 AArch64CC::CondCode CC1, CC2;
3777 changeFPCCToAArch64CC(CC, CC1, CC2);
3778 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3779 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3781 // If we need a second CSEL, emit it, using the output of the first as the
3782 // RHS. We're effectively OR'ing the two CC's together.
3783 if (CC2 != AArch64CC::AL) {
3784 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3785 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3788 // Otherwise, return the output of the first CSEL.
3792 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3793 SelectionDAG &DAG) const {
3794 // Jump table entries as PC relative offsets. No additional tweaking
3795 // is necessary here. Just get the address of the jump table.
3796 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3797 EVT PtrVT = getPointerTy();
3800 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3801 !Subtarget->isTargetMachO()) {
3802 const unsigned char MO_NC = AArch64II::MO_NC;
3804 AArch64ISD::WrapperLarge, DL, PtrVT,
3805 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3806 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3807 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3808 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3809 AArch64II::MO_G0 | MO_NC));
3813 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3814 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3815 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3816 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3817 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3820 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3821 SelectionDAG &DAG) const {
3822 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3823 EVT PtrVT = getPointerTy();
3826 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3827 // Use the GOT for the large code model on iOS.
3828 if (Subtarget->isTargetMachO()) {
3829 SDValue GotAddr = DAG.getTargetConstantPool(
3830 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3832 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3835 const unsigned char MO_NC = AArch64II::MO_NC;
3837 AArch64ISD::WrapperLarge, DL, PtrVT,
3838 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3839 CP->getOffset(), AArch64II::MO_G3),
3840 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3841 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3842 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3843 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3844 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3845 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3847 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3848 // ELF, the only valid one on Darwin.
3850 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3851 CP->getOffset(), AArch64II::MO_PAGE);
3852 SDValue Lo = DAG.getTargetConstantPool(
3853 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3854 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3856 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3857 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3861 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3862 SelectionDAG &DAG) const {
3863 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3864 EVT PtrVT = getPointerTy();
3866 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3867 !Subtarget->isTargetMachO()) {
3868 const unsigned char MO_NC = AArch64II::MO_NC;
3870 AArch64ISD::WrapperLarge, DL, PtrVT,
3871 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3872 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3873 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3874 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3876 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3877 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3879 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3880 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3884 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3885 SelectionDAG &DAG) const {
3886 AArch64FunctionInfo *FuncInfo =
3887 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3891 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3892 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3893 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3894 MachinePointerInfo(SV), false, false, 0);
3897 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3898 SelectionDAG &DAG) const {
3899 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3900 // Standard, section B.3.
3901 MachineFunction &MF = DAG.getMachineFunction();
3902 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3905 SDValue Chain = Op.getOperand(0);
3906 SDValue VAList = Op.getOperand(1);
3907 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3908 SmallVector<SDValue, 4> MemOps;
3910 // void *__stack at offset 0
3912 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3913 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3914 MachinePointerInfo(SV), false, false, 8));
3916 // void *__gr_top at offset 8
3917 int GPRSize = FuncInfo->getVarArgsGPRSize();
3919 SDValue GRTop, GRTopAddr;
3921 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3922 DAG.getConstant(8, getPointerTy()));
3924 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3925 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3926 DAG.getConstant(GPRSize, getPointerTy()));
3928 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3929 MachinePointerInfo(SV, 8), false, false, 8));
3932 // void *__vr_top at offset 16
3933 int FPRSize = FuncInfo->getVarArgsFPRSize();
3935 SDValue VRTop, VRTopAddr;
3936 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3937 DAG.getConstant(16, getPointerTy()));
3939 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3940 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3941 DAG.getConstant(FPRSize, getPointerTy()));
3943 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3944 MachinePointerInfo(SV, 16), false, false, 8));
3947 // int __gr_offs at offset 24
3948 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3949 DAG.getConstant(24, getPointerTy()));
3950 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3951 GROffsAddr, MachinePointerInfo(SV, 24), false,
3954 // int __vr_offs at offset 28
3955 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3956 DAG.getConstant(28, getPointerTy()));
3957 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3958 VROffsAddr, MachinePointerInfo(SV, 28), false,
3961 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3964 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3965 SelectionDAG &DAG) const {
3966 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3967 : LowerAAPCS_VASTART(Op, DAG);
3970 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3971 SelectionDAG &DAG) const {
3972 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3974 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3975 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3976 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3978 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3979 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3980 8, false, false, MachinePointerInfo(DestSV),
3981 MachinePointerInfo(SrcSV));
3984 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3985 assert(Subtarget->isTargetDarwin() &&
3986 "automatic va_arg instruction only works on Darwin");
3988 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3989 EVT VT = Op.getValueType();
3991 SDValue Chain = Op.getOperand(0);
3992 SDValue Addr = Op.getOperand(1);
3993 unsigned Align = Op.getConstantOperandVal(3);
3995 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3996 MachinePointerInfo(V), false, false, false, 0);
3997 Chain = VAList.getValue(1);
4000 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4001 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4002 DAG.getConstant(Align - 1, getPointerTy()));
4003 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
4004 DAG.getConstant(-(int64_t)Align, getPointerTy()));
4007 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4008 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4010 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4011 // up to 64 bits. At the very least, we have to increase the striding of the
4012 // vaargs list to match this, and for FP values we need to introduce
4013 // FP_ROUND nodes as well.
4014 if (VT.isInteger() && !VT.isVector())
4016 bool NeedFPTrunc = false;
4017 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4022 // Increment the pointer, VAList, to the next vaarg
4023 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4024 DAG.getConstant(ArgSize, getPointerTy()));
4025 // Store the incremented VAList to the legalized pointer
4026 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4029 // Load the actual argument out of the pointer VAList
4031 // Load the value as an f64.
4032 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4033 MachinePointerInfo(), false, false, false, 0);
4034 // Round the value down to an f32.
4035 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4036 DAG.getIntPtrConstant(1));
4037 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4038 // Merge the rounded value with the chain output of the load.
4039 return DAG.getMergeValues(Ops, DL);
4042 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4046 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4047 SelectionDAG &DAG) const {
4048 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4049 MFI->setFrameAddressIsTaken(true);
4051 EVT VT = Op.getValueType();
4053 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4055 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4057 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4058 MachinePointerInfo(), false, false, false, 0);
4062 // FIXME? Maybe this could be a TableGen attribute on some registers and
4063 // this table could be generated automatically from RegInfo.
4064 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4066 unsigned Reg = StringSwitch<unsigned>(RegName)
4067 .Case("sp", AArch64::SP)
4071 report_fatal_error("Invalid register name global variable");
4074 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4075 SelectionDAG &DAG) const {
4076 MachineFunction &MF = DAG.getMachineFunction();
4077 MachineFrameInfo *MFI = MF.getFrameInfo();
4078 MFI->setReturnAddressIsTaken(true);
4080 EVT VT = Op.getValueType();
4082 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4084 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4085 SDValue Offset = DAG.getConstant(8, getPointerTy());
4086 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4087 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4088 MachinePointerInfo(), false, false, false, 0);
4091 // Return LR, which contains the return address. Mark it an implicit live-in.
4092 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4093 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4096 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4097 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4098 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4099 SelectionDAG &DAG) const {
4100 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4101 EVT VT = Op.getValueType();
4102 unsigned VTBits = VT.getSizeInBits();
4104 SDValue ShOpLo = Op.getOperand(0);
4105 SDValue ShOpHi = Op.getOperand(1);
4106 SDValue ShAmt = Op.getOperand(2);
4108 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4110 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4112 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4113 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4114 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4115 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4116 DAG.getConstant(VTBits, MVT::i64));
4117 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4119 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4120 ISD::SETGE, dl, DAG);
4121 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4123 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4124 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4126 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4128 // AArch64 shifts larger than the register width are wrapped rather than
4129 // clamped, so we can't just emit "hi >> x".
4130 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4131 SDValue TrueValHi = Opc == ISD::SRA
4132 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4133 DAG.getConstant(VTBits - 1, MVT::i64))
4134 : DAG.getConstant(0, VT);
4136 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4138 SDValue Ops[2] = { Lo, Hi };
4139 return DAG.getMergeValues(Ops, dl);
4142 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4143 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4144 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4145 SelectionDAG &DAG) const {
4146 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4147 EVT VT = Op.getValueType();
4148 unsigned VTBits = VT.getSizeInBits();
4150 SDValue ShOpLo = Op.getOperand(0);
4151 SDValue ShOpHi = Op.getOperand(1);
4152 SDValue ShAmt = Op.getOperand(2);
4155 assert(Op.getOpcode() == ISD::SHL_PARTS);
4156 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4157 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4158 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4159 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4160 DAG.getConstant(VTBits, MVT::i64));
4161 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4162 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4164 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4166 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4167 ISD::SETGE, dl, DAG);
4168 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4170 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4172 // AArch64 shifts of larger than register sizes are wrapped rather than
4173 // clamped, so we can't just emit "lo << a" if a is too big.
4174 SDValue TrueValLo = DAG.getConstant(0, VT);
4175 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4177 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4179 SDValue Ops[2] = { Lo, Hi };
4180 return DAG.getMergeValues(Ops, dl);
4183 bool AArch64TargetLowering::isOffsetFoldingLegal(
4184 const GlobalAddressSDNode *GA) const {
4185 // The AArch64 target doesn't support folding offsets into global addresses.
4189 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4190 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4191 // FIXME: We should be able to handle f128 as well with a clever lowering.
4192 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4196 return AArch64_AM::getFP64Imm(Imm) != -1;
4197 else if (VT == MVT::f32)
4198 return AArch64_AM::getFP32Imm(Imm) != -1;
4202 //===----------------------------------------------------------------------===//
4203 // AArch64 Optimization Hooks
4204 //===----------------------------------------------------------------------===//
4206 //===----------------------------------------------------------------------===//
4207 // AArch64 Inline Assembly Support
4208 //===----------------------------------------------------------------------===//
4210 // Table of Constraints
4211 // TODO: This is the current set of constraints supported by ARM for the
4212 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4214 // r - A general register
4215 // w - An FP/SIMD register of some size in the range v0-v31
4216 // x - An FP/SIMD register of some size in the range v0-v15
4217 // I - Constant that can be used with an ADD instruction
4218 // J - Constant that can be used with a SUB instruction
4219 // K - Constant that can be used with a 32-bit logical instruction
4220 // L - Constant that can be used with a 64-bit logical instruction
4221 // M - Constant that can be used as a 32-bit MOV immediate
4222 // N - Constant that can be used as a 64-bit MOV immediate
4223 // Q - A memory reference with base register and no offset
4224 // S - A symbolic address
4225 // Y - Floating point constant zero
4226 // Z - Integer constant zero
4228 // Note that general register operands will be output using their 64-bit x
4229 // register name, whatever the size of the variable, unless the asm operand
4230 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4231 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4234 /// getConstraintType - Given a constraint letter, return the type of
4235 /// constraint it is for this target.
4236 AArch64TargetLowering::ConstraintType
4237 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4238 if (Constraint.size() == 1) {
4239 switch (Constraint[0]) {
4246 return C_RegisterClass;
4247 // An address with a single base register. Due to the way we
4248 // currently handle addresses it is the same as 'r'.
4253 return TargetLowering::getConstraintType(Constraint);
4256 /// Examine constraint type and operand type and determine a weight value.
4257 /// This object must already have been set up with the operand type
4258 /// and the current alternative constraint selected.
4259 TargetLowering::ConstraintWeight
4260 AArch64TargetLowering::getSingleConstraintMatchWeight(
4261 AsmOperandInfo &info, const char *constraint) const {
4262 ConstraintWeight weight = CW_Invalid;
4263 Value *CallOperandVal = info.CallOperandVal;
4264 // If we don't have a value, we can't do a match,
4265 // but allow it at the lowest weight.
4266 if (!CallOperandVal)
4268 Type *type = CallOperandVal->getType();
4269 // Look at the constraint type.
4270 switch (*constraint) {
4272 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4276 if (type->isFloatingPointTy() || type->isVectorTy())
4277 weight = CW_Register;
4280 weight = CW_Constant;
4286 std::pair<unsigned, const TargetRegisterClass *>
4287 AArch64TargetLowering::getRegForInlineAsmConstraint(
4288 const std::string &Constraint, MVT VT) const {
4289 if (Constraint.size() == 1) {
4290 switch (Constraint[0]) {
4292 if (VT.getSizeInBits() == 64)
4293 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4294 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4297 return std::make_pair(0U, &AArch64::FPR32RegClass);
4298 if (VT.getSizeInBits() == 64)
4299 return std::make_pair(0U, &AArch64::FPR64RegClass);
4300 if (VT.getSizeInBits() == 128)
4301 return std::make_pair(0U, &AArch64::FPR128RegClass);
4303 // The instructions that this constraint is designed for can
4304 // only take 128-bit registers so just use that regclass.
4306 if (VT.getSizeInBits() == 128)
4307 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4311 if (StringRef("{cc}").equals_lower(Constraint))
4312 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4314 // Use the default implementation in TargetLowering to convert the register
4315 // constraint into a member of a register class.
4316 std::pair<unsigned, const TargetRegisterClass *> Res;
4317 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4319 // Not found as a standard register?
4321 unsigned Size = Constraint.size();
4322 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4323 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4324 const std::string Reg =
4325 std::string(&Constraint[2], &Constraint[Size - 1]);
4326 int RegNo = atoi(Reg.c_str());
4327 if (RegNo >= 0 && RegNo <= 31) {
4328 // v0 - v31 are aliases of q0 - q31.
4329 // By default we'll emit v0-v31 for this unless there's a modifier where
4330 // we'll emit the correct register as well.
4331 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4332 Res.second = &AArch64::FPR128RegClass;
4340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4341 /// vector. If it is invalid, don't add anything to Ops.
4342 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4343 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4344 SelectionDAG &DAG) const {
4347 // Currently only support length 1 constraints.
4348 if (Constraint.length() != 1)
4351 char ConstraintLetter = Constraint[0];
4352 switch (ConstraintLetter) {
4356 // This set of constraints deal with valid constants for various instructions.
4357 // Validate and return a target constant for them if we can.
4359 // 'z' maps to xzr or wzr so it needs an input of 0.
4360 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4361 if (!C || C->getZExtValue() != 0)
4364 if (Op.getValueType() == MVT::i64)
4365 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4367 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4377 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4381 // Grab the value and do some validation.
4382 uint64_t CVal = C->getZExtValue();
4383 switch (ConstraintLetter) {
4384 // The I constraint applies only to simple ADD or SUB immediate operands:
4385 // i.e. 0 to 4095 with optional shift by 12
4386 // The J constraint applies only to ADD or SUB immediates that would be
4387 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4388 // instruction [or vice versa], in other words -1 to -4095 with optional
4389 // left shift by 12.
4391 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4395 uint64_t NVal = -C->getSExtValue();
4396 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4397 CVal = C->getSExtValue();
4402 // The K and L constraints apply *only* to logical immediates, including
4403 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4404 // been removed and MOV should be used). So these constraints have to
4405 // distinguish between bit patterns that are valid 32-bit or 64-bit
4406 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4407 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4410 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4414 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4417 // The M and N constraints are a superset of K and L respectively, for use
4418 // with the MOV (immediate) alias. As well as the logical immediates they
4419 // also match 32 or 64-bit immediates that can be loaded either using a
4420 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4421 // (M) or 64-bit 0x1234000000000000 (N) etc.
4422 // As a note some of this code is liberally stolen from the asm parser.
4424 if (!isUInt<32>(CVal))
4426 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4428 if ((CVal & 0xFFFF) == CVal)
4430 if ((CVal & 0xFFFF0000ULL) == CVal)
4432 uint64_t NCVal = ~(uint32_t)CVal;
4433 if ((NCVal & 0xFFFFULL) == NCVal)
4435 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4440 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4442 if ((CVal & 0xFFFFULL) == CVal)
4444 if ((CVal & 0xFFFF0000ULL) == CVal)
4446 if ((CVal & 0xFFFF00000000ULL) == CVal)
4448 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4450 uint64_t NCVal = ~CVal;
4451 if ((NCVal & 0xFFFFULL) == NCVal)
4453 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4455 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4457 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4465 // All assembler immediates are 64-bit integers.
4466 Result = DAG.getTargetConstant(CVal, MVT::i64);
4470 if (Result.getNode()) {
4471 Ops.push_back(Result);
4475 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4478 //===----------------------------------------------------------------------===//
4479 // AArch64 Advanced SIMD Support
4480 //===----------------------------------------------------------------------===//
4482 /// WidenVector - Given a value in the V64 register class, produce the
4483 /// equivalent value in the V128 register class.
4484 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4485 EVT VT = V64Reg.getValueType();
4486 unsigned NarrowSize = VT.getVectorNumElements();
4487 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4488 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4491 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4492 V64Reg, DAG.getConstant(0, MVT::i32));
4495 /// getExtFactor - Determine the adjustment factor for the position when
4496 /// generating an "extract from vector registers" instruction.
4497 static unsigned getExtFactor(SDValue &V) {
4498 EVT EltType = V.getValueType().getVectorElementType();
4499 return EltType.getSizeInBits() / 8;
4502 /// NarrowVector - Given a value in the V128 register class, produce the
4503 /// equivalent value in the V64 register class.
4504 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4505 EVT VT = V128Reg.getValueType();
4506 unsigned WideSize = VT.getVectorNumElements();
4507 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4508 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4511 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4514 // Gather data to see if the operation can be modelled as a
4515 // shuffle in combination with VEXTs.
4516 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4517 SelectionDAG &DAG) const {
4518 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4520 EVT VT = Op.getValueType();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 struct ShuffleSourceInfo {
4528 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4529 // be compatible with the shuffle we intend to construct. As a result
4530 // ShuffleVec will be some sliding window into the original Vec.
4533 // Code should guarantee that element i in Vec starts at element "WindowBase
4534 // + i * WindowScale in ShuffleVec".
4538 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4539 ShuffleSourceInfo(SDValue Vec)
4540 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4544 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4546 SmallVector<ShuffleSourceInfo, 2> Sources;
4547 for (unsigned i = 0; i < NumElts; ++i) {
4548 SDValue V = Op.getOperand(i);
4549 if (V.getOpcode() == ISD::UNDEF)
4551 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4552 // A shuffle can only come from building a vector from various
4553 // elements of other vectors.
4557 // Add this element source to the list if it's not already there.
4558 SDValue SourceVec = V.getOperand(0);
4559 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4560 if (Source == Sources.end())
4561 Sources.push_back(ShuffleSourceInfo(SourceVec));
4563 // Update the minimum and maximum lane number seen.
4564 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4565 Source->MinElt = std::min(Source->MinElt, EltNo);
4566 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4569 // Currently only do something sane when at most two source vectors
4571 if (Sources.size() > 2)
4574 // Find out the smallest element size among result and two sources, and use
4575 // it as element size to build the shuffle_vector.
4576 EVT SmallestEltTy = VT.getVectorElementType();
4577 for (auto &Source : Sources) {
4578 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4579 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4580 SmallestEltTy = SrcEltTy;
4583 unsigned ResMultiplier =
4584 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4585 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4586 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4588 // If the source vector is too wide or too narrow, we may nevertheless be able
4589 // to construct a compatible shuffle either by concatenating it with UNDEF or
4590 // extracting a suitable range of elements.
4591 for (auto &Src : Sources) {
4592 EVT SrcVT = Src.ShuffleVec.getValueType();
4594 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4597 // This stage of the search produces a source with the same element type as
4598 // the original, but with a total width matching the BUILD_VECTOR output.
4599 EVT EltVT = SrcVT.getVectorElementType();
4600 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4601 VT.getSizeInBits() / EltVT.getSizeInBits());
4603 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4604 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4605 // We can pad out the smaller vector for free, so if it's part of a
4608 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4609 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4613 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4615 if (Src.MaxElt - Src.MinElt >= NumElts) {
4616 // Span too large for a VEXT to cope
4620 if (Src.MinElt >= NumElts) {
4621 // The extraction can just take the second half
4623 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4624 DAG.getIntPtrConstant(NumElts));
4625 Src.WindowBase = -NumElts;
4626 } else if (Src.MaxElt < NumElts) {
4627 // The extraction can just take the first half
4628 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4629 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4631 // An actual VEXT is needed
4632 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4633 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4635 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4636 DAG.getIntPtrConstant(NumElts));
4637 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4639 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4640 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4641 Src.WindowBase = -Src.MinElt;
4645 // Another possible incompatibility occurs from the vector element types. We
4646 // can fix this by bitcasting the source vectors to the same type we intend
4648 for (auto &Src : Sources) {
4649 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4650 if (SrcEltTy == SmallestEltTy)
4652 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4653 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4654 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4655 Src.WindowBase *= Src.WindowScale;
4658 // Final sanity check before we try to actually produce a shuffle.
4660 for (auto Src : Sources)
4661 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4664 // The stars all align, our next step is to produce the mask for the shuffle.
4665 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4666 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4667 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4668 SDValue Entry = Op.getOperand(i);
4669 if (Entry.getOpcode() == ISD::UNDEF)
4672 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4673 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4675 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4676 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4678 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4679 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4680 VT.getVectorElementType().getSizeInBits());
4681 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4683 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4684 // starting at the appropriate offset.
4685 int *LaneMask = &Mask[i * ResMultiplier];
4687 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4688 ExtractBase += NumElts * (Src - Sources.begin());
4689 for (int j = 0; j < LanesDefined; ++j)
4690 LaneMask[j] = ExtractBase + j;
4693 // Final check before we try to produce nonsense...
4694 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4697 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4698 for (unsigned i = 0; i < Sources.size(); ++i)
4699 ShuffleOps[i] = Sources[i].ShuffleVec;
4701 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4702 ShuffleOps[1], &Mask[0]);
4703 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4706 // check if an EXT instruction can handle the shuffle mask when the
4707 // vector sources of the shuffle are the same.
4708 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4709 unsigned NumElts = VT.getVectorNumElements();
4711 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4717 // If this is a VEXT shuffle, the immediate value is the index of the first
4718 // element. The other shuffle indices must be the successive elements after
4720 unsigned ExpectedElt = Imm;
4721 for (unsigned i = 1; i < NumElts; ++i) {
4722 // Increment the expected index. If it wraps around, just follow it
4723 // back to index zero and keep going.
4725 if (ExpectedElt == NumElts)
4729 continue; // ignore UNDEF indices
4730 if (ExpectedElt != static_cast<unsigned>(M[i]))
4737 // check if an EXT instruction can handle the shuffle mask when the
4738 // vector sources of the shuffle are different.
4739 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4741 // Look for the first non-undef element.
4742 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4743 [](int Elt) {return Elt >= 0;});
4745 // Benefit form APInt to handle overflow when calculating expected element.
4746 unsigned NumElts = VT.getVectorNumElements();
4747 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4748 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4749 // The following shuffle indices must be the successive elements after the
4750 // first real element.
4751 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4752 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4753 if (FirstWrongElt != M.end())
4756 // The index of an EXT is the first element if it is not UNDEF.
4757 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4758 // value of the first element. E.g.
4759 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4760 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4761 // ExpectedElt is the last mask index plus 1.
4762 Imm = ExpectedElt.getZExtValue();
4764 // There are two difference cases requiring to reverse input vectors.
4765 // For example, for vector <4 x i32> we have the following cases,
4766 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4767 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4768 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4769 // to reverse two input vectors.
4778 /// isREVMask - Check if a vector shuffle corresponds to a REV
4779 /// instruction with the specified blocksize. (The order of the elements
4780 /// within each block of the vector is reversed.)
4781 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4782 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4783 "Only possible block sizes for REV are: 16, 32, 64");
4785 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4789 unsigned NumElts = VT.getVectorNumElements();
4790 unsigned BlockElts = M[0] + 1;
4791 // If the first shuffle index is UNDEF, be optimistic.
4793 BlockElts = BlockSize / EltSz;
4795 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4798 for (unsigned i = 0; i < NumElts; ++i) {
4800 continue; // ignore UNDEF indices
4801 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4808 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4809 unsigned NumElts = VT.getVectorNumElements();
4810 WhichResult = (M[0] == 0 ? 0 : 1);
4811 unsigned Idx = WhichResult * NumElts / 2;
4812 for (unsigned i = 0; i != NumElts; i += 2) {
4813 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4814 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4822 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4823 unsigned NumElts = VT.getVectorNumElements();
4824 WhichResult = (M[0] == 0 ? 0 : 1);
4825 for (unsigned i = 0; i != NumElts; ++i) {
4827 continue; // ignore UNDEF indices
4828 if ((unsigned)M[i] != 2 * i + WhichResult)
4835 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4836 unsigned NumElts = VT.getVectorNumElements();
4837 WhichResult = (M[0] == 0 ? 0 : 1);
4838 for (unsigned i = 0; i < NumElts; i += 2) {
4839 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4840 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4846 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4847 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4848 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4849 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4850 unsigned NumElts = VT.getVectorNumElements();
4851 WhichResult = (M[0] == 0 ? 0 : 1);
4852 unsigned Idx = WhichResult * NumElts / 2;
4853 for (unsigned i = 0; i != NumElts; i += 2) {
4854 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4855 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4863 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4864 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4865 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4866 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4867 unsigned Half = VT.getVectorNumElements() / 2;
4868 WhichResult = (M[0] == 0 ? 0 : 1);
4869 for (unsigned j = 0; j != 2; ++j) {
4870 unsigned Idx = WhichResult;
4871 for (unsigned i = 0; i != Half; ++i) {
4872 int MIdx = M[i + j * Half];
4873 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4882 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4883 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4884 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4885 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4886 unsigned NumElts = VT.getVectorNumElements();
4887 WhichResult = (M[0] == 0 ? 0 : 1);
4888 for (unsigned i = 0; i < NumElts; i += 2) {
4889 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4890 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4896 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4897 bool &DstIsLeft, int &Anomaly) {
4898 if (M.size() != static_cast<size_t>(NumInputElements))
4901 int NumLHSMatch = 0, NumRHSMatch = 0;
4902 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4904 for (int i = 0; i < NumInputElements; ++i) {
4914 LastLHSMismatch = i;
4916 if (M[i] == i + NumInputElements)
4919 LastRHSMismatch = i;
4922 if (NumLHSMatch == NumInputElements - 1) {
4924 Anomaly = LastLHSMismatch;
4926 } else if (NumRHSMatch == NumInputElements - 1) {
4928 Anomaly = LastRHSMismatch;
4935 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4936 if (VT.getSizeInBits() != 128)
4939 unsigned NumElts = VT.getVectorNumElements();
4941 for (int I = 0, E = NumElts / 2; I != E; I++) {
4946 int Offset = NumElts / 2;
4947 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4948 if (Mask[I] != I + SplitLHS * Offset)
4955 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4957 EVT VT = Op.getValueType();
4958 SDValue V0 = Op.getOperand(0);
4959 SDValue V1 = Op.getOperand(1);
4960 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4962 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4963 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4966 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4968 if (!isConcatMask(Mask, VT, SplitV0))
4971 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4972 VT.getVectorNumElements() / 2);
4974 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4975 DAG.getConstant(0, MVT::i64));
4977 if (V1.getValueType().getSizeInBits() == 128) {
4978 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4979 DAG.getConstant(0, MVT::i64));
4981 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4984 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4985 /// the specified operations to build the shuffle.
4986 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4987 SDValue RHS, SelectionDAG &DAG,
4989 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4990 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4991 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4994 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5003 OP_VUZPL, // VUZP, left result
5004 OP_VUZPR, // VUZP, right result
5005 OP_VZIPL, // VZIP, left result
5006 OP_VZIPR, // VZIP, right result
5007 OP_VTRNL, // VTRN, left result
5008 OP_VTRNR // VTRN, right result
5011 if (OpNum == OP_COPY) {
5012 if (LHSID == (1 * 9 + 2) * 9 + 3)
5014 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5018 SDValue OpLHS, OpRHS;
5019 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5020 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5021 EVT VT = OpLHS.getValueType();
5025 llvm_unreachable("Unknown shuffle opcode!");
5027 // VREV divides the vector in half and swaps within the half.
5028 if (VT.getVectorElementType() == MVT::i32 ||
5029 VT.getVectorElementType() == MVT::f32)
5030 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5031 // vrev <4 x i16> -> REV32
5032 if (VT.getVectorElementType() == MVT::i16 ||
5033 VT.getVectorElementType() == MVT::f16)
5034 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5035 // vrev <4 x i8> -> REV16
5036 assert(VT.getVectorElementType() == MVT::i8);
5037 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5042 EVT EltTy = VT.getVectorElementType();
5044 if (EltTy == MVT::i8)
5045 Opcode = AArch64ISD::DUPLANE8;
5046 else if (EltTy == MVT::i16)
5047 Opcode = AArch64ISD::DUPLANE16;
5048 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5049 Opcode = AArch64ISD::DUPLANE32;
5050 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5051 Opcode = AArch64ISD::DUPLANE64;
5053 llvm_unreachable("Invalid vector element type?");
5055 if (VT.getSizeInBits() == 64)
5056 OpLHS = WidenVector(OpLHS, DAG);
5057 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5058 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5063 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5064 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5065 DAG.getConstant(Imm, MVT::i32));
5068 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5071 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5074 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5077 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5080 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5083 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5088 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5089 SelectionDAG &DAG) {
5090 // Check to see if we can use the TBL instruction.
5091 SDValue V1 = Op.getOperand(0);
5092 SDValue V2 = Op.getOperand(1);
5095 EVT EltVT = Op.getValueType().getVectorElementType();
5096 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5098 SmallVector<SDValue, 8> TBLMask;
5099 for (int Val : ShuffleMask) {
5100 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5101 unsigned Offset = Byte + Val * BytesPerElt;
5102 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5106 MVT IndexVT = MVT::v8i8;
5107 unsigned IndexLen = 8;
5108 if (Op.getValueType().getSizeInBits() == 128) {
5109 IndexVT = MVT::v16i8;
5113 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5114 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5117 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5119 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5120 Shuffle = DAG.getNode(
5121 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5122 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5123 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5124 makeArrayRef(TBLMask.data(), IndexLen)));
5126 if (IndexLen == 8) {
5127 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5128 Shuffle = DAG.getNode(
5129 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5130 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5131 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5132 makeArrayRef(TBLMask.data(), IndexLen)));
5134 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5135 // cannot currently represent the register constraints on the input
5137 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5138 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5139 // &TBLMask[0], IndexLen));
5140 Shuffle = DAG.getNode(
5141 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5142 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5143 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5144 makeArrayRef(TBLMask.data(), IndexLen)));
5147 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5150 static unsigned getDUPLANEOp(EVT EltType) {
5151 if (EltType == MVT::i8)
5152 return AArch64ISD::DUPLANE8;
5153 if (EltType == MVT::i16 || EltType == MVT::f16)
5154 return AArch64ISD::DUPLANE16;
5155 if (EltType == MVT::i32 || EltType == MVT::f32)
5156 return AArch64ISD::DUPLANE32;
5157 if (EltType == MVT::i64 || EltType == MVT::f64)
5158 return AArch64ISD::DUPLANE64;
5160 llvm_unreachable("Invalid vector element type?");
5163 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5164 SelectionDAG &DAG) const {
5166 EVT VT = Op.getValueType();
5168 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5170 // Convert shuffles that are directly supported on NEON to target-specific
5171 // DAG nodes, instead of keeping them as shuffles and matching them again
5172 // during code selection. This is more efficient and avoids the possibility
5173 // of inconsistencies between legalization and selection.
5174 ArrayRef<int> ShuffleMask = SVN->getMask();
5176 SDValue V1 = Op.getOperand(0);
5177 SDValue V2 = Op.getOperand(1);
5179 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5180 V1.getValueType().getSimpleVT())) {
5181 int Lane = SVN->getSplatIndex();
5182 // If this is undef splat, generate it via "just" vdup, if possible.
5186 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5187 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5189 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5190 // constant. If so, we can just reference the lane's definition directly.
5191 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5192 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5193 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5195 // Otherwise, duplicate from the lane of the input vector.
5196 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5198 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5199 // to make a vector of the same size as this SHUFFLE. We can ignore the
5200 // extract entirely, and canonicalise the concat using WidenVector.
5201 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5202 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5203 V1 = V1.getOperand(0);
5204 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5205 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5206 Lane -= Idx * VT.getVectorNumElements() / 2;
5207 V1 = WidenVector(V1.getOperand(Idx), DAG);
5208 } else if (VT.getSizeInBits() == 64)
5209 V1 = WidenVector(V1, DAG);
5211 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5214 if (isREVMask(ShuffleMask, VT, 64))
5215 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5216 if (isREVMask(ShuffleMask, VT, 32))
5217 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5218 if (isREVMask(ShuffleMask, VT, 16))
5219 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5221 bool ReverseEXT = false;
5223 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5226 Imm *= getExtFactor(V1);
5227 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5228 DAG.getConstant(Imm, MVT::i32));
5229 } else if (V2->getOpcode() == ISD::UNDEF &&
5230 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5231 Imm *= getExtFactor(V1);
5232 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5233 DAG.getConstant(Imm, MVT::i32));
5236 unsigned WhichResult;
5237 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5238 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5239 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5241 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5242 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5243 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5245 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5246 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5247 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5250 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5251 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5252 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5254 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5255 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5256 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5258 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5259 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5260 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5263 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5264 if (Concat.getNode())
5269 int NumInputElements = V1.getValueType().getVectorNumElements();
5270 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5271 SDValue DstVec = DstIsLeft ? V1 : V2;
5272 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5274 SDValue SrcVec = V1;
5275 int SrcLane = ShuffleMask[Anomaly];
5276 if (SrcLane >= NumInputElements) {
5278 SrcLane -= VT.getVectorNumElements();
5280 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5282 EVT ScalarVT = VT.getVectorElementType();
5284 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5285 ScalarVT = MVT::i32;
5288 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5289 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5293 // If the shuffle is not directly supported and it has 4 elements, use
5294 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5295 unsigned NumElts = VT.getVectorNumElements();
5297 unsigned PFIndexes[4];
5298 for (unsigned i = 0; i != 4; ++i) {
5299 if (ShuffleMask[i] < 0)
5302 PFIndexes[i] = ShuffleMask[i];
5305 // Compute the index in the perfect shuffle table.
5306 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5307 PFIndexes[2] * 9 + PFIndexes[3];
5308 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5309 unsigned Cost = (PFEntry >> 30);
5312 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5315 return GenerateTBL(Op, ShuffleMask, DAG);
5318 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5320 EVT VT = BVN->getValueType(0);
5321 APInt SplatBits, SplatUndef;
5322 unsigned SplatBitSize;
5324 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5325 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5327 for (unsigned i = 0; i < NumSplats; ++i) {
5328 CnstBits <<= SplatBitSize;
5329 UndefBits <<= SplatBitSize;
5330 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5331 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5340 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5341 SelectionDAG &DAG) const {
5342 BuildVectorSDNode *BVN =
5343 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5344 SDValue LHS = Op.getOperand(0);
5346 EVT VT = Op.getValueType();
5351 APInt CnstBits(VT.getSizeInBits(), 0);
5352 APInt UndefBits(VT.getSizeInBits(), 0);
5353 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5354 // We only have BIC vector immediate instruction, which is and-not.
5355 CnstBits = ~CnstBits;
5357 // We make use of a little bit of goto ickiness in order to avoid having to
5358 // duplicate the immediate matching logic for the undef toggled case.
5359 bool SecondTry = false;
5362 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5363 CnstBits = CnstBits.zextOrTrunc(64);
5364 uint64_t CnstVal = CnstBits.getZExtValue();
5366 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5367 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5368 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5369 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5370 DAG.getConstant(CnstVal, MVT::i32),
5371 DAG.getConstant(0, MVT::i32));
5372 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5375 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5376 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5377 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5378 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5379 DAG.getConstant(CnstVal, MVT::i32),
5380 DAG.getConstant(8, MVT::i32));
5381 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5384 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5385 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5386 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5387 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5388 DAG.getConstant(CnstVal, MVT::i32),
5389 DAG.getConstant(16, MVT::i32));
5390 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5393 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5394 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5395 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5396 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5397 DAG.getConstant(CnstVal, MVT::i32),
5398 DAG.getConstant(24, MVT::i32));
5399 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5402 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5403 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5404 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5405 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5406 DAG.getConstant(CnstVal, MVT::i32),
5407 DAG.getConstant(0, MVT::i32));
5408 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5411 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5412 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5413 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5414 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5415 DAG.getConstant(CnstVal, MVT::i32),
5416 DAG.getConstant(8, MVT::i32));
5417 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5424 CnstBits = ~UndefBits;
5428 // We can always fall back to a non-immediate AND.
5433 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5434 // consists of only the same constant int value, returned in reference arg
5436 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5437 uint64_t &ConstVal) {
5438 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5441 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5444 EVT VT = Bvec->getValueType(0);
5445 unsigned NumElts = VT.getVectorNumElements();
5446 for (unsigned i = 1; i < NumElts; ++i)
5447 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5449 ConstVal = FirstElt->getZExtValue();
5453 static unsigned getIntrinsicID(const SDNode *N) {
5454 unsigned Opcode = N->getOpcode();
5457 return Intrinsic::not_intrinsic;
5458 case ISD::INTRINSIC_WO_CHAIN: {
5459 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5460 if (IID < Intrinsic::num_intrinsics)
5462 return Intrinsic::not_intrinsic;
5467 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5468 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5469 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5470 // Also, logical shift right -> sri, with the same structure.
5471 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5472 EVT VT = N->getValueType(0);
5479 // Is the first op an AND?
5480 const SDValue And = N->getOperand(0);
5481 if (And.getOpcode() != ISD::AND)
5484 // Is the second op an shl or lshr?
5485 SDValue Shift = N->getOperand(1);
5486 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5487 // or AArch64ISD::VLSHR vector, #shift
5488 unsigned ShiftOpc = Shift.getOpcode();
5489 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5491 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5493 // Is the shift amount constant?
5494 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5498 // Is the and mask vector all constant?
5500 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5503 // Is C1 == ~C2, taking into account how much one can shift elements of a
5505 uint64_t C2 = C2node->getZExtValue();
5506 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5507 if (C2 > ElemSizeInBits)
5509 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5510 if ((C1 & ElemMask) != (~C2 & ElemMask))
5513 SDValue X = And.getOperand(0);
5514 SDValue Y = Shift.getOperand(0);
5517 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5519 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5520 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5522 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5523 DEBUG(N->dump(&DAG));
5524 DEBUG(dbgs() << "into: \n");
5525 DEBUG(ResultSLI->dump(&DAG));
5531 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5532 SelectionDAG &DAG) const {
5533 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5534 if (EnableAArch64SlrGeneration) {
5535 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5540 BuildVectorSDNode *BVN =
5541 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5542 SDValue LHS = Op.getOperand(1);
5544 EVT VT = Op.getValueType();
5546 // OR commutes, so try swapping the operands.
5548 LHS = Op.getOperand(0);
5549 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5554 APInt CnstBits(VT.getSizeInBits(), 0);
5555 APInt UndefBits(VT.getSizeInBits(), 0);
5556 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5557 // We make use of a little bit of goto ickiness in order to avoid having to
5558 // duplicate the immediate matching logic for the undef toggled case.
5559 bool SecondTry = false;
5562 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5563 CnstBits = CnstBits.zextOrTrunc(64);
5564 uint64_t CnstVal = CnstBits.getZExtValue();
5566 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5567 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5568 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5569 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5570 DAG.getConstant(CnstVal, MVT::i32),
5571 DAG.getConstant(0, MVT::i32));
5572 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5575 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5576 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5577 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5578 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5579 DAG.getConstant(CnstVal, MVT::i32),
5580 DAG.getConstant(8, MVT::i32));
5581 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5584 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5585 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5586 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5587 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5588 DAG.getConstant(CnstVal, MVT::i32),
5589 DAG.getConstant(16, MVT::i32));
5590 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5593 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5594 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5595 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5596 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5597 DAG.getConstant(CnstVal, MVT::i32),
5598 DAG.getConstant(24, MVT::i32));
5599 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5602 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5603 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5604 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5605 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5606 DAG.getConstant(CnstVal, MVT::i32),
5607 DAG.getConstant(0, MVT::i32));
5608 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5611 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5612 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5613 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5614 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5615 DAG.getConstant(CnstVal, MVT::i32),
5616 DAG.getConstant(8, MVT::i32));
5617 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5624 CnstBits = UndefBits;
5628 // We can always fall back to a non-immediate OR.
5633 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5634 // be truncated to fit element width.
5635 static SDValue NormalizeBuildVector(SDValue Op,
5636 SelectionDAG &DAG) {
5637 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5639 EVT VT = Op.getValueType();
5640 EVT EltTy= VT.getVectorElementType();
5642 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5645 SmallVector<SDValue, 16> Ops;
5646 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5647 SDValue Lane = Op.getOperand(I);
5648 if (Lane.getOpcode() == ISD::Constant) {
5649 APInt LowBits(EltTy.getSizeInBits(),
5650 cast<ConstantSDNode>(Lane)->getZExtValue());
5651 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5653 Ops.push_back(Lane);
5655 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5658 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5659 SelectionDAG &DAG) const {
5661 EVT VT = Op.getValueType();
5662 Op = NormalizeBuildVector(Op, DAG);
5663 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5665 APInt CnstBits(VT.getSizeInBits(), 0);
5666 APInt UndefBits(VT.getSizeInBits(), 0);
5667 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5668 // We make use of a little bit of goto ickiness in order to avoid having to
5669 // duplicate the immediate matching logic for the undef toggled case.
5670 bool SecondTry = false;
5673 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5674 CnstBits = CnstBits.zextOrTrunc(64);
5675 uint64_t CnstVal = CnstBits.getZExtValue();
5677 // Certain magic vector constants (used to express things like NOT
5678 // and NEG) are passed through unmodified. This allows codegen patterns
5679 // for these operations to match. Special-purpose patterns will lower
5680 // these immediates to MOVIs if it proves necessary.
5681 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5684 // The many faces of MOVI...
5685 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5686 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5687 if (VT.getSizeInBits() == 128) {
5688 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5689 DAG.getConstant(CnstVal, MVT::i32));
5690 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5693 // Support the V64 version via subregister insertion.
5694 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5695 DAG.getConstant(CnstVal, MVT::i32));
5696 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5699 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5700 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5701 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5702 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5703 DAG.getConstant(CnstVal, MVT::i32),
5704 DAG.getConstant(0, MVT::i32));
5705 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5708 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5709 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5710 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5711 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5712 DAG.getConstant(CnstVal, MVT::i32),
5713 DAG.getConstant(8, MVT::i32));
5714 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5717 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5718 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5719 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5720 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5721 DAG.getConstant(CnstVal, MVT::i32),
5722 DAG.getConstant(16, MVT::i32));
5723 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5726 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5727 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5728 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5729 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5730 DAG.getConstant(CnstVal, MVT::i32),
5731 DAG.getConstant(24, MVT::i32));
5732 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5735 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5736 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5737 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5738 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5739 DAG.getConstant(CnstVal, MVT::i32),
5740 DAG.getConstant(0, MVT::i32));
5741 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5744 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5745 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5746 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5747 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5748 DAG.getConstant(CnstVal, MVT::i32),
5749 DAG.getConstant(8, MVT::i32));
5750 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5753 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5754 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5755 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5756 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5757 DAG.getConstant(CnstVal, MVT::i32),
5758 DAG.getConstant(264, MVT::i32));
5759 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5762 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5763 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5764 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5765 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5766 DAG.getConstant(CnstVal, MVT::i32),
5767 DAG.getConstant(272, MVT::i32));
5768 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5771 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5772 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5773 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5774 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5775 DAG.getConstant(CnstVal, MVT::i32));
5776 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5779 // The few faces of FMOV...
5780 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5781 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5782 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5783 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5784 DAG.getConstant(CnstVal, MVT::i32));
5785 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5788 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5789 VT.getSizeInBits() == 128) {
5790 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5791 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5792 DAG.getConstant(CnstVal, MVT::i32));
5793 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5796 // The many faces of MVNI...
5798 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5799 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5800 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5801 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5802 DAG.getConstant(CnstVal, MVT::i32),
5803 DAG.getConstant(0, MVT::i32));
5804 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5807 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5808 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5809 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5810 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5811 DAG.getConstant(CnstVal, MVT::i32),
5812 DAG.getConstant(8, MVT::i32));
5813 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5816 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5817 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5818 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5819 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5820 DAG.getConstant(CnstVal, MVT::i32),
5821 DAG.getConstant(16, MVT::i32));
5822 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5825 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5826 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5827 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5828 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5829 DAG.getConstant(CnstVal, MVT::i32),
5830 DAG.getConstant(24, MVT::i32));
5831 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5834 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5835 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5836 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5837 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5838 DAG.getConstant(CnstVal, MVT::i32),
5839 DAG.getConstant(0, MVT::i32));
5840 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5843 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5844 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5845 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5846 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5847 DAG.getConstant(CnstVal, MVT::i32),
5848 DAG.getConstant(8, MVT::i32));
5849 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5852 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5853 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5854 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5855 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5856 DAG.getConstant(CnstVal, MVT::i32),
5857 DAG.getConstant(264, MVT::i32));
5858 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5861 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5862 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5863 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5864 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5865 DAG.getConstant(CnstVal, MVT::i32),
5866 DAG.getConstant(272, MVT::i32));
5867 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5874 CnstBits = UndefBits;
5879 // Scan through the operands to find some interesting properties we can
5881 // 1) If only one value is used, we can use a DUP, or
5882 // 2) if only the low element is not undef, we can just insert that, or
5883 // 3) if only one constant value is used (w/ some non-constant lanes),
5884 // we can splat the constant value into the whole vector then fill
5885 // in the non-constant lanes.
5886 // 4) FIXME: If different constant values are used, but we can intelligently
5887 // select the values we'll be overwriting for the non-constant
5888 // lanes such that we can directly materialize the vector
5889 // some other way (MOVI, e.g.), we can be sneaky.
5890 unsigned NumElts = VT.getVectorNumElements();
5891 bool isOnlyLowElement = true;
5892 bool usesOnlyOneValue = true;
5893 bool usesOnlyOneConstantValue = true;
5894 bool isConstant = true;
5895 unsigned NumConstantLanes = 0;
5897 SDValue ConstantValue;
5898 for (unsigned i = 0; i < NumElts; ++i) {
5899 SDValue V = Op.getOperand(i);
5900 if (V.getOpcode() == ISD::UNDEF)
5903 isOnlyLowElement = false;
5904 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5907 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5909 if (!ConstantValue.getNode())
5911 else if (ConstantValue != V)
5912 usesOnlyOneConstantValue = false;
5915 if (!Value.getNode())
5917 else if (V != Value)
5918 usesOnlyOneValue = false;
5921 if (!Value.getNode())
5922 return DAG.getUNDEF(VT);
5924 if (isOnlyLowElement)
5925 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5927 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5928 // i32 and try again.
5929 if (usesOnlyOneValue) {
5931 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5932 Value.getValueType() != VT)
5933 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5935 // This is actually a DUPLANExx operation, which keeps everything vectory.
5937 // DUPLANE works on 128-bit vectors, widen it if necessary.
5938 SDValue Lane = Value.getOperand(1);
5939 Value = Value.getOperand(0);
5940 if (Value.getValueType().getSizeInBits() == 64)
5941 Value = WidenVector(Value, DAG);
5943 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5944 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5947 if (VT.getVectorElementType().isFloatingPoint()) {
5948 SmallVector<SDValue, 8> Ops;
5950 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5951 for (unsigned i = 0; i < NumElts; ++i)
5952 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5953 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5954 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5955 Val = LowerBUILD_VECTOR(Val, DAG);
5957 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5961 // If there was only one constant value used and for more than one lane,
5962 // start by splatting that value, then replace the non-constant lanes. This
5963 // is better than the default, which will perform a separate initialization
5965 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5966 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5967 // Now insert the non-constant lanes.
5968 for (unsigned i = 0; i < NumElts; ++i) {
5969 SDValue V = Op.getOperand(i);
5970 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5971 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5972 // Note that type legalization likely mucked about with the VT of the
5973 // source operand, so we may have to convert it here before inserting.
5974 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5980 // If all elements are constants and the case above didn't get hit, fall back
5981 // to the default expansion, which will generate a load from the constant
5986 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5988 SDValue shuffle = ReconstructShuffle(Op, DAG);
5989 if (shuffle != SDValue())
5993 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5994 // know the default expansion would otherwise fall back on something even
5995 // worse. For a vector with one or two non-undef values, that's
5996 // scalar_to_vector for the elements followed by a shuffle (provided the
5997 // shuffle is valid for the target) and materialization element by element
5998 // on the stack followed by a load for everything else.
5999 if (!isConstant && !usesOnlyOneValue) {
6000 SDValue Vec = DAG.getUNDEF(VT);
6001 SDValue Op0 = Op.getOperand(0);
6002 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6004 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6005 // a) Avoid a RMW dependency on the full vector register, and
6006 // b) Allow the register coalescer to fold away the copy if the
6007 // value is already in an S or D register.
6008 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6009 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6011 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6012 DAG.getTargetConstant(SubIdx, MVT::i32));
6013 Vec = SDValue(N, 0);
6016 for (; i < NumElts; ++i) {
6017 SDValue V = Op.getOperand(i);
6018 if (V.getOpcode() == ISD::UNDEF)
6020 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
6021 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6026 // Just use the default expansion. We failed to find a better alternative.
6030 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6031 SelectionDAG &DAG) const {
6032 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6034 // Check for non-constant or out of range lane.
6035 EVT VT = Op.getOperand(0).getValueType();
6036 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6037 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6041 // Insertion/extraction are legal for V128 types.
6042 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6043 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6047 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6048 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6051 // For V64 types, we perform insertion by expanding the value
6052 // to a V128 type and perform the insertion on that.
6054 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6055 EVT WideTy = WideVec.getValueType();
6057 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6058 Op.getOperand(1), Op.getOperand(2));
6059 // Re-narrow the resultant vector.
6060 return NarrowVector(Node, DAG);
6064 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6065 SelectionDAG &DAG) const {
6066 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6068 // Check for non-constant or out of range lane.
6069 EVT VT = Op.getOperand(0).getValueType();
6070 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6071 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6075 // Insertion/extraction are legal for V128 types.
6076 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6077 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6081 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6082 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6085 // For V64 types, we perform extraction by expanding the value
6086 // to a V128 type and perform the extraction on that.
6088 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6089 EVT WideTy = WideVec.getValueType();
6091 EVT ExtrTy = WideTy.getVectorElementType();
6092 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6095 // For extractions, we just return the result directly.
6096 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6100 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6101 SelectionDAG &DAG) const {
6102 EVT VT = Op.getOperand(0).getValueType();
6108 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6111 unsigned Val = Cst->getZExtValue();
6113 unsigned Size = Op.getValueType().getSizeInBits();
6117 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6120 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6123 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6126 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6129 llvm_unreachable("Unexpected vector type in extract_subvector!");
6132 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6134 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6140 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6142 if (VT.getVectorNumElements() == 4 &&
6143 (VT.is128BitVector() || VT.is64BitVector())) {
6144 unsigned PFIndexes[4];
6145 for (unsigned i = 0; i != 4; ++i) {
6149 PFIndexes[i] = M[i];
6152 // Compute the index in the perfect shuffle table.
6153 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6154 PFIndexes[2] * 9 + PFIndexes[3];
6155 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6156 unsigned Cost = (PFEntry >> 30);
6164 unsigned DummyUnsigned;
6166 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6167 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6168 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6169 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6170 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6171 isZIPMask(M, VT, DummyUnsigned) ||
6172 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6173 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6174 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6175 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6176 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6179 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6180 /// operand of a vector shift operation, where all the elements of the
6181 /// build_vector must have the same constant integer value.
6182 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6183 // Ignore bit_converts.
6184 while (Op.getOpcode() == ISD::BITCAST)
6185 Op = Op.getOperand(0);
6186 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6187 APInt SplatBits, SplatUndef;
6188 unsigned SplatBitSize;
6190 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6191 HasAnyUndefs, ElementBits) ||
6192 SplatBitSize > ElementBits)
6194 Cnt = SplatBits.getSExtValue();
6198 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6199 /// operand of a vector shift left operation. That value must be in the range:
6200 /// 0 <= Value < ElementBits for a left shift; or
6201 /// 0 <= Value <= ElementBits for a long left shift.
6202 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6203 assert(VT.isVector() && "vector shift count is not a vector type");
6204 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6205 if (!getVShiftImm(Op, ElementBits, Cnt))
6207 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6210 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6211 /// operand of a vector shift right operation. For a shift opcode, the value
6212 /// is positive, but for an intrinsic the value count must be negative. The
6213 /// absolute value must be in the range:
6214 /// 1 <= |Value| <= ElementBits for a right shift; or
6215 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6216 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6218 assert(VT.isVector() && "vector shift count is not a vector type");
6219 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6220 if (!getVShiftImm(Op, ElementBits, Cnt))
6224 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6227 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6228 SelectionDAG &DAG) const {
6229 EVT VT = Op.getValueType();
6233 if (!Op.getOperand(1).getValueType().isVector())
6235 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6237 switch (Op.getOpcode()) {
6239 llvm_unreachable("unexpected shift opcode");
6242 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6243 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6244 DAG.getConstant(Cnt, MVT::i32));
6245 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6246 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6247 Op.getOperand(0), Op.getOperand(1));
6250 // Right shift immediate
6251 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6254 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6255 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6256 DAG.getConstant(Cnt, MVT::i32));
6259 // Right shift register. Note, there is not a shift right register
6260 // instruction, but the shift left register instruction takes a signed
6261 // value, where negative numbers specify a right shift.
6262 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6263 : Intrinsic::aarch64_neon_ushl;
6264 // negate the shift amount
6265 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6266 SDValue NegShiftLeft =
6267 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6268 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6269 return NegShiftLeft;
6275 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6276 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6277 SDLoc dl, SelectionDAG &DAG) {
6278 EVT SrcVT = LHS.getValueType();
6280 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6281 APInt CnstBits(VT.getSizeInBits(), 0);
6282 APInt UndefBits(VT.getSizeInBits(), 0);
6283 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6284 bool IsZero = IsCnst && (CnstBits == 0);
6286 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6290 case AArch64CC::NE: {
6293 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6295 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6296 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6300 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6301 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6304 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6305 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6308 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6309 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6312 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6313 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6317 // If we ignore NaNs then we can use to the MI implementation.
6321 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6322 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6329 case AArch64CC::NE: {
6332 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6334 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6335 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6339 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6340 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6343 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6344 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6347 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6348 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6351 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6352 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6354 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6356 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6359 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6360 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6362 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6364 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6368 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6369 SelectionDAG &DAG) const {
6370 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6371 SDValue LHS = Op.getOperand(0);
6372 SDValue RHS = Op.getOperand(1);
6375 if (LHS.getValueType().getVectorElementType().isInteger()) {
6376 assert(LHS.getValueType() == RHS.getValueType());
6377 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6378 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
6382 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6383 LHS.getValueType().getVectorElementType() == MVT::f64);
6385 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6386 // clean. Some of them require two branches to implement.
6387 AArch64CC::CondCode CC1, CC2;
6389 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6391 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6393 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
6397 if (CC2 != AArch64CC::AL) {
6399 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
6400 if (!Cmp2.getNode())
6403 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
6407 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6412 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6413 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6414 /// specified in the intrinsic calls.
6415 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6417 unsigned Intrinsic) const {
6418 switch (Intrinsic) {
6419 case Intrinsic::aarch64_neon_ld2:
6420 case Intrinsic::aarch64_neon_ld3:
6421 case Intrinsic::aarch64_neon_ld4:
6422 case Intrinsic::aarch64_neon_ld1x2:
6423 case Intrinsic::aarch64_neon_ld1x3:
6424 case Intrinsic::aarch64_neon_ld1x4:
6425 case Intrinsic::aarch64_neon_ld2lane:
6426 case Intrinsic::aarch64_neon_ld3lane:
6427 case Intrinsic::aarch64_neon_ld4lane:
6428 case Intrinsic::aarch64_neon_ld2r:
6429 case Intrinsic::aarch64_neon_ld3r:
6430 case Intrinsic::aarch64_neon_ld4r: {
6431 Info.opc = ISD::INTRINSIC_W_CHAIN;
6432 // Conservatively set memVT to the entire set of vectors loaded.
6433 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6434 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6435 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6438 Info.vol = false; // volatile loads with NEON intrinsics not supported
6439 Info.readMem = true;
6440 Info.writeMem = false;
6443 case Intrinsic::aarch64_neon_st2:
6444 case Intrinsic::aarch64_neon_st3:
6445 case Intrinsic::aarch64_neon_st4:
6446 case Intrinsic::aarch64_neon_st1x2:
6447 case Intrinsic::aarch64_neon_st1x3:
6448 case Intrinsic::aarch64_neon_st1x4:
6449 case Intrinsic::aarch64_neon_st2lane:
6450 case Intrinsic::aarch64_neon_st3lane:
6451 case Intrinsic::aarch64_neon_st4lane: {
6452 Info.opc = ISD::INTRINSIC_VOID;
6453 // Conservatively set memVT to the entire set of vectors stored.
6454 unsigned NumElts = 0;
6455 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6456 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6457 if (!ArgTy->isVectorTy())
6459 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6461 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6462 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6465 Info.vol = false; // volatile stores with NEON intrinsics not supported
6466 Info.readMem = false;
6467 Info.writeMem = true;
6470 case Intrinsic::aarch64_ldaxr:
6471 case Intrinsic::aarch64_ldxr: {
6472 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6473 Info.opc = ISD::INTRINSIC_W_CHAIN;
6474 Info.memVT = MVT::getVT(PtrTy->getElementType());
6475 Info.ptrVal = I.getArgOperand(0);
6477 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6479 Info.readMem = true;
6480 Info.writeMem = false;
6483 case Intrinsic::aarch64_stlxr:
6484 case Intrinsic::aarch64_stxr: {
6485 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6486 Info.opc = ISD::INTRINSIC_W_CHAIN;
6487 Info.memVT = MVT::getVT(PtrTy->getElementType());
6488 Info.ptrVal = I.getArgOperand(1);
6490 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6492 Info.readMem = false;
6493 Info.writeMem = true;
6496 case Intrinsic::aarch64_ldaxp:
6497 case Intrinsic::aarch64_ldxp: {
6498 Info.opc = ISD::INTRINSIC_W_CHAIN;
6499 Info.memVT = MVT::i128;
6500 Info.ptrVal = I.getArgOperand(0);
6504 Info.readMem = true;
6505 Info.writeMem = false;
6508 case Intrinsic::aarch64_stlxp:
6509 case Intrinsic::aarch64_stxp: {
6510 Info.opc = ISD::INTRINSIC_W_CHAIN;
6511 Info.memVT = MVT::i128;
6512 Info.ptrVal = I.getArgOperand(2);
6516 Info.readMem = false;
6517 Info.writeMem = true;
6527 // Truncations from 64-bit GPR to 32-bit GPR is free.
6528 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6529 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6531 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6532 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6533 return NumBits1 > NumBits2;
6535 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6536 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6538 unsigned NumBits1 = VT1.getSizeInBits();
6539 unsigned NumBits2 = VT2.getSizeInBits();
6540 return NumBits1 > NumBits2;
6543 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6545 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6546 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6548 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6549 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6550 return NumBits1 == 32 && NumBits2 == 64;
6552 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6553 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6555 unsigned NumBits1 = VT1.getSizeInBits();
6556 unsigned NumBits2 = VT2.getSizeInBits();
6557 return NumBits1 == 32 && NumBits2 == 64;
6560 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6561 EVT VT1 = Val.getValueType();
6562 if (isZExtFree(VT1, VT2)) {
6566 if (Val.getOpcode() != ISD::LOAD)
6569 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6570 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6571 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6572 VT1.getSizeInBits() <= 32);
6575 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6576 unsigned &RequiredAligment) const {
6577 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6579 // Cyclone supports unaligned accesses.
6580 RequiredAligment = 0;
6581 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6582 return NumBits == 32 || NumBits == 64;
6585 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6586 unsigned &RequiredAligment) const {
6587 if (!LoadedType.isSimple() ||
6588 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6590 // Cyclone supports unaligned accesses.
6591 RequiredAligment = 0;
6592 unsigned NumBits = LoadedType.getSizeInBits();
6593 return NumBits == 32 || NumBits == 64;
6596 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6597 unsigned AlignCheck) {
6598 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6599 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6602 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6603 unsigned SrcAlign, bool IsMemset,
6606 MachineFunction &MF) const {
6607 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6608 // instruction to materialize the v2i64 zero and one store (with restrictive
6609 // addressing mode). Just do two i64 store of zero-registers.
6611 const Function *F = MF.getFunction();
6612 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6613 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6614 Attribute::NoImplicitFloat) &&
6615 (memOpAlign(SrcAlign, DstAlign, 16) ||
6616 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6619 return Size >= 8 ? MVT::i64 : MVT::i32;
6622 // 12-bit optionally shifted immediates are legal for adds.
6623 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6624 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6629 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6630 // immediates is the same as for an add or a sub.
6631 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6634 return isLegalAddImmediate(Immed);
6637 /// isLegalAddressingMode - Return true if the addressing mode represented
6638 /// by AM is legal for this target, for a load/store of the specified type.
6639 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6641 // AArch64 has five basic addressing modes:
6643 // reg + 9-bit signed offset
6644 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6646 // reg + SIZE_IN_BYTES * reg
6648 // No global is ever allowed as a base.
6652 // No reg+reg+imm addressing.
6653 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6656 // check reg + imm case:
6657 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6658 uint64_t NumBytes = 0;
6659 if (Ty->isSized()) {
6660 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6661 NumBytes = NumBits / 8;
6662 if (!isPowerOf2_64(NumBits))
6667 int64_t Offset = AM.BaseOffs;
6669 // 9-bit signed offset
6670 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6673 // 12-bit unsigned offset
6674 unsigned shift = Log2_64(NumBytes);
6675 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6676 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6677 (Offset >> shift) << shift == Offset)
6682 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6684 if (!AM.Scale || AM.Scale == 1 ||
6685 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6690 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6692 // Scaling factors are not free at all.
6693 // Operands | Rt Latency
6694 // -------------------------------------------
6696 // -------------------------------------------
6697 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6698 // Rt, [Xn, Wm, <extend> #imm] |
6699 if (isLegalAddressingMode(AM, Ty))
6700 // Scale represents reg2 * scale, thus account for 1 if
6701 // it is not equal to 0 or 1.
6702 return AM.Scale != 0 && AM.Scale != 1;
6706 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6707 VT = VT.getScalarType();
6712 switch (VT.getSimpleVT().SimpleTy) {
6724 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6725 // LR is a callee-save register, but we must treat it as clobbered by any call
6726 // site. Hence we include LR in the scratch registers, which are in turn added
6727 // as implicit-defs for stackmaps and patchpoints.
6728 static const MCPhysReg ScratchRegs[] = {
6729 AArch64::X16, AArch64::X17, AArch64::LR, 0
6735 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6736 EVT VT = N->getValueType(0);
6737 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6738 // it with shift to let it be lowered to UBFX.
6739 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6740 isa<ConstantSDNode>(N->getOperand(1))) {
6741 uint64_t TruncMask = N->getConstantOperandVal(1);
6742 if (isMask_64(TruncMask) &&
6743 N->getOperand(0).getOpcode() == ISD::SRL &&
6744 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6750 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6752 assert(Ty->isIntegerTy());
6754 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6758 int64_t Val = Imm.getSExtValue();
6759 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6762 if ((int64_t)Val < 0)
6765 Val &= (1LL << 32) - 1;
6767 unsigned LZ = countLeadingZeros((uint64_t)Val);
6768 unsigned Shift = (63 - LZ) / 16;
6769 // MOVZ is free so return true for one or fewer MOVK.
6770 return (Shift < 3) ? true : false;
6773 // Generate SUBS and CSEL for integer abs.
6774 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6775 EVT VT = N->getValueType(0);
6777 SDValue N0 = N->getOperand(0);
6778 SDValue N1 = N->getOperand(1);
6781 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6782 // and change it to SUB and CSEL.
6783 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6784 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6785 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6786 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6787 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6788 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6790 // Generate SUBS & CSEL.
6792 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6793 N0.getOperand(0), DAG.getConstant(0, VT));
6794 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6795 DAG.getConstant(AArch64CC::PL, MVT::i32),
6796 SDValue(Cmp.getNode(), 1));
6801 // performXorCombine - Attempts to handle integer ABS.
6802 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6803 TargetLowering::DAGCombinerInfo &DCI,
6804 const AArch64Subtarget *Subtarget) {
6805 if (DCI.isBeforeLegalizeOps())
6808 return performIntegerAbsCombine(N, DAG);
6812 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6814 std::vector<SDNode *> *Created) const {
6815 // fold (sdiv X, pow2)
6816 EVT VT = N->getValueType(0);
6817 if ((VT != MVT::i32 && VT != MVT::i64) ||
6818 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6822 SDValue N0 = N->getOperand(0);
6823 unsigned Lg2 = Divisor.countTrailingZeros();
6824 SDValue Zero = DAG.getConstant(0, VT);
6825 SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT);
6827 // Add (N0 < 0) ? Pow2 - 1 : 0;
6829 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6830 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6831 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6834 Created->push_back(Cmp.getNode());
6835 Created->push_back(Add.getNode());
6836 Created->push_back(CSel.getNode());
6841 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6843 // If we're dividing by a positive value, we're done. Otherwise, we must
6844 // negate the result.
6845 if (Divisor.isNonNegative())
6849 Created->push_back(SRA.getNode());
6850 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6853 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6854 TargetLowering::DAGCombinerInfo &DCI,
6855 const AArch64Subtarget *Subtarget) {
6856 if (DCI.isBeforeLegalizeOps())
6859 // Multiplication of a power of two plus/minus one can be done more
6860 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6861 // future CPUs have a cheaper MADD instruction, this may need to be
6862 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6863 // 64-bit is 5 cycles, so this is always a win.
6864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6865 APInt Value = C->getAPIntValue();
6866 EVT VT = N->getValueType(0);
6867 if (Value.isNonNegative()) {
6868 // (mul x, 2^N + 1) => (add (shl x, N), x)
6869 APInt VM1 = Value - 1;
6870 if (VM1.isPowerOf2()) {
6871 SDValue ShiftedVal =
6872 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6873 DAG.getConstant(VM1.logBase2(), MVT::i64));
6874 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6877 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6878 APInt VP1 = Value + 1;
6879 if (VP1.isPowerOf2()) {
6880 SDValue ShiftedVal =
6881 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6882 DAG.getConstant(VP1.logBase2(), MVT::i64));
6883 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6887 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6888 APInt VNM1 = -Value - 1;
6889 if (VNM1.isPowerOf2()) {
6890 SDValue ShiftedVal =
6891 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6892 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6894 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6895 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6897 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6898 APInt VNP1 = -Value + 1;
6899 if (VNP1.isPowerOf2()) {
6900 SDValue ShiftedVal =
6901 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6902 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6903 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6911 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6912 SelectionDAG &DAG) {
6913 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6914 // optimize away operation when it's from a constant.
6916 // The general transformation is:
6917 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6918 // AND(VECTOR_CMP(x,y), constant2)
6919 // constant2 = UNARYOP(constant)
6921 // Early exit if this isn't a vector operation, the operand of the
6922 // unary operation isn't a bitwise AND, or if the sizes of the operations
6924 EVT VT = N->getValueType(0);
6925 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6926 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6927 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6930 // Now check that the other operand of the AND is a constant. We could
6931 // make the transformation for non-constant splats as well, but it's unclear
6932 // that would be a benefit as it would not eliminate any operations, just
6933 // perform one more step in scalar code before moving to the vector unit.
6934 if (BuildVectorSDNode *BV =
6935 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6936 // Bail out if the vector isn't a constant.
6937 if (!BV->isConstant())
6940 // Everything checks out. Build up the new and improved node.
6942 EVT IntVT = BV->getValueType(0);
6943 // Create a new constant of the appropriate type for the transformed
6945 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6946 // The AND node needs bitcasts to/from an integer vector type around it.
6947 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6948 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6949 N->getOperand(0)->getOperand(0), MaskConst);
6950 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6957 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6958 // First try to optimize away the conversion when it's conditionally from
6959 // a constant. Vectors only.
6960 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6961 if (Res != SDValue())
6964 EVT VT = N->getValueType(0);
6965 if (VT != MVT::f32 && VT != MVT::f64)
6968 // Only optimize when the source and destination types have the same width.
6969 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6972 // If the result of an integer load is only used by an integer-to-float
6973 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6974 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6975 SDValue N0 = N->getOperand(0);
6976 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6977 // Do not change the width of a volatile load.
6978 !cast<LoadSDNode>(N0)->isVolatile()) {
6979 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6980 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6981 LN0->getPointerInfo(), LN0->isVolatile(),
6982 LN0->isNonTemporal(), LN0->isInvariant(),
6983 LN0->getAlignment());
6985 // Make sure successors of the original load stay after it by updating them
6986 // to use the new Chain.
6987 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6990 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6991 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6997 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6998 /// searches for and classifies those shifts.
6999 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7001 if (N.getOpcode() == ISD::SHL)
7003 else if (N.getOpcode() == ISD::SRL)
7008 if (!isa<ConstantSDNode>(N.getOperand(1)))
7011 ShiftAmount = N->getConstantOperandVal(1);
7012 Src = N->getOperand(0);
7016 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7017 /// registers viewed as a high/low pair. This function looks for the pattern:
7018 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7019 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7021 static SDValue tryCombineToEXTR(SDNode *N,
7022 TargetLowering::DAGCombinerInfo &DCI) {
7023 SelectionDAG &DAG = DCI.DAG;
7025 EVT VT = N->getValueType(0);
7027 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7029 if (VT != MVT::i32 && VT != MVT::i64)
7033 uint32_t ShiftLHS = 0;
7035 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7039 uint32_t ShiftRHS = 0;
7041 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7044 // If they're both trying to come from the high part of the register, they're
7045 // not really an EXTR.
7046 if (LHSFromHi == RHSFromHi)
7049 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7053 std::swap(LHS, RHS);
7054 std::swap(ShiftLHS, ShiftRHS);
7057 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7058 DAG.getConstant(ShiftRHS, MVT::i64));
7061 static SDValue tryCombineToBSL(SDNode *N,
7062 TargetLowering::DAGCombinerInfo &DCI) {
7063 EVT VT = N->getValueType(0);
7064 SelectionDAG &DAG = DCI.DAG;
7070 SDValue N0 = N->getOperand(0);
7071 if (N0.getOpcode() != ISD::AND)
7074 SDValue N1 = N->getOperand(1);
7075 if (N1.getOpcode() != ISD::AND)
7078 // We only have to look for constant vectors here since the general, variable
7079 // case can be handled in TableGen.
7080 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7081 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7082 for (int i = 1; i >= 0; --i)
7083 for (int j = 1; j >= 0; --j) {
7084 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7085 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7089 bool FoundMatch = true;
7090 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7091 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7092 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7094 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7101 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7102 N0->getOperand(1 - i), N1->getOperand(1 - j));
7108 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7109 const AArch64Subtarget *Subtarget) {
7110 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7111 if (!EnableAArch64ExtrGeneration)
7113 SelectionDAG &DAG = DCI.DAG;
7114 EVT VT = N->getValueType(0);
7116 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7119 SDValue Res = tryCombineToEXTR(N, DCI);
7123 Res = tryCombineToBSL(N, DCI);
7130 static SDValue performBitcastCombine(SDNode *N,
7131 TargetLowering::DAGCombinerInfo &DCI,
7132 SelectionDAG &DAG) {
7133 // Wait 'til after everything is legalized to try this. That way we have
7134 // legal vector types and such.
7135 if (DCI.isBeforeLegalizeOps())
7138 // Remove extraneous bitcasts around an extract_subvector.
7140 // (v4i16 (bitconvert
7141 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7143 // (extract_subvector ((v8i16 ...), (i64 4)))
7145 // Only interested in 64-bit vectors as the ultimate result.
7146 EVT VT = N->getValueType(0);
7149 if (VT.getSimpleVT().getSizeInBits() != 64)
7151 // Is the operand an extract_subvector starting at the beginning or halfway
7152 // point of the vector? A low half may also come through as an
7153 // EXTRACT_SUBREG, so look for that, too.
7154 SDValue Op0 = N->getOperand(0);
7155 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7156 !(Op0->isMachineOpcode() &&
7157 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7159 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7160 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7161 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7163 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7164 if (idx != AArch64::dsub)
7166 // The dsub reference is equivalent to a lane zero subvector reference.
7169 // Look through the bitcast of the input to the extract.
7170 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7172 SDValue Source = Op0->getOperand(0)->getOperand(0);
7173 // If the source type has twice the number of elements as our destination
7174 // type, we know this is an extract of the high or low half of the vector.
7175 EVT SVT = Source->getValueType(0);
7176 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7179 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7181 // Create the simplified form to just extract the low or high half of the
7182 // vector directly rather than bothering with the bitcasts.
7184 unsigned NumElements = VT.getVectorNumElements();
7186 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7187 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7189 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7190 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7196 static SDValue performConcatVectorsCombine(SDNode *N,
7197 TargetLowering::DAGCombinerInfo &DCI,
7198 SelectionDAG &DAG) {
7199 // Wait 'til after everything is legalized to try this. That way we have
7200 // legal vector types and such.
7201 if (DCI.isBeforeLegalizeOps())
7205 EVT VT = N->getValueType(0);
7207 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7208 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7209 // canonicalise to that.
7210 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
7211 assert(VT.getVectorElementType().getSizeInBits() == 64);
7212 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
7213 WidenVector(N->getOperand(0), DAG),
7214 DAG.getConstant(0, MVT::i64));
7217 // Canonicalise concat_vectors so that the right-hand vector has as few
7218 // bit-casts as possible before its real operation. The primary matching
7219 // destination for these operations will be the narrowing "2" instructions,
7220 // which depend on the operation being performed on this right-hand vector.
7222 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7224 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7226 SDValue Op1 = N->getOperand(1);
7227 if (Op1->getOpcode() != ISD::BITCAST)
7229 SDValue RHS = Op1->getOperand(0);
7230 MVT RHSTy = RHS.getValueType().getSimpleVT();
7231 // If the RHS is not a vector, this is not the pattern we're looking for.
7232 if (!RHSTy.isVector())
7235 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7237 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7238 RHSTy.getVectorNumElements() * 2);
7240 ISD::BITCAST, dl, VT,
7241 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7242 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
7245 static SDValue tryCombineFixedPointConvert(SDNode *N,
7246 TargetLowering::DAGCombinerInfo &DCI,
7247 SelectionDAG &DAG) {
7248 // Wait 'til after everything is legalized to try this. That way we have
7249 // legal vector types and such.
7250 if (DCI.isBeforeLegalizeOps())
7252 // Transform a scalar conversion of a value from a lane extract into a
7253 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7254 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7255 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7257 // The second form interacts better with instruction selection and the
7258 // register allocator to avoid cross-class register copies that aren't
7259 // coalescable due to a lane reference.
7261 // Check the operand and see if it originates from a lane extract.
7262 SDValue Op1 = N->getOperand(1);
7263 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7264 // Yep, no additional predication needed. Perform the transform.
7265 SDValue IID = N->getOperand(0);
7266 SDValue Shift = N->getOperand(2);
7267 SDValue Vec = Op1.getOperand(0);
7268 SDValue Lane = Op1.getOperand(1);
7269 EVT ResTy = N->getValueType(0);
7273 // The vector width should be 128 bits by the time we get here, even
7274 // if it started as 64 bits (the extract_vector handling will have
7276 assert(Vec.getValueType().getSizeInBits() == 128 &&
7277 "unexpected vector size on extract_vector_elt!");
7278 if (Vec.getValueType() == MVT::v4i32)
7279 VecResTy = MVT::v4f32;
7280 else if (Vec.getValueType() == MVT::v2i64)
7281 VecResTy = MVT::v2f64;
7283 llvm_unreachable("unexpected vector type!");
7286 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7287 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7292 // AArch64 high-vector "long" operations are formed by performing the non-high
7293 // version on an extract_subvector of each operand which gets the high half:
7295 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7297 // However, there are cases which don't have an extract_high explicitly, but
7298 // have another operation that can be made compatible with one for free. For
7301 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7303 // This routine does the actual conversion of such DUPs, once outer routines
7304 // have determined that everything else is in order.
7305 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7306 // We can handle most types of duplicate, but the lane ones have an extra
7307 // operand saying *which* lane, so we need to know.
7309 switch (N.getOpcode()) {
7310 case AArch64ISD::DUP:
7313 case AArch64ISD::DUPLANE8:
7314 case AArch64ISD::DUPLANE16:
7315 case AArch64ISD::DUPLANE32:
7316 case AArch64ISD::DUPLANE64:
7323 MVT NarrowTy = N.getSimpleValueType();
7324 if (!NarrowTy.is64BitVector())
7327 MVT ElementTy = NarrowTy.getVectorElementType();
7328 unsigned NumElems = NarrowTy.getVectorNumElements();
7329 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7333 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7336 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7338 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7339 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7342 static bool isEssentiallyExtractSubvector(SDValue N) {
7343 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7346 return N.getOpcode() == ISD::BITCAST &&
7347 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7350 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7351 struct GenericSetCCInfo {
7352 const SDValue *Opnd0;
7353 const SDValue *Opnd1;
7357 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7358 struct AArch64SetCCInfo {
7360 AArch64CC::CondCode CC;
7363 /// \brief Helper structure to keep track of SetCC information.
7365 GenericSetCCInfo Generic;
7366 AArch64SetCCInfo AArch64;
7369 /// \brief Helper structure to be able to read SetCC information. If set to
7370 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7371 /// GenericSetCCInfo.
7372 struct SetCCInfoAndKind {
7377 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7379 /// AArch64 lowered one.
7380 /// \p SetCCInfo is filled accordingly.
7381 /// \post SetCCInfo is meanginfull only when this function returns true.
7382 /// \return True when Op is a kind of SET_CC operation.
7383 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7384 // If this is a setcc, this is straight forward.
7385 if (Op.getOpcode() == ISD::SETCC) {
7386 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7387 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7388 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7389 SetCCInfo.IsAArch64 = false;
7392 // Otherwise, check if this is a matching csel instruction.
7396 if (Op.getOpcode() != AArch64ISD::CSEL)
7398 // Set the information about the operands.
7399 // TODO: we want the operands of the Cmp not the csel
7400 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7401 SetCCInfo.IsAArch64 = true;
7402 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7403 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7405 // Check that the operands matches the constraints:
7406 // (1) Both operands must be constants.
7407 // (2) One must be 1 and the other must be 0.
7408 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7409 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7412 if (!TValue || !FValue)
7416 if (!TValue->isOne()) {
7417 // Update the comparison when we are interested in !cc.
7418 std::swap(TValue, FValue);
7419 SetCCInfo.Info.AArch64.CC =
7420 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7422 return TValue->isOne() && FValue->isNullValue();
7425 // Returns true if Op is setcc or zext of setcc.
7426 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7427 if (isSetCC(Op, Info))
7429 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7430 isSetCC(Op->getOperand(0), Info));
7433 // The folding we want to perform is:
7434 // (add x, [zext] (setcc cc ...) )
7436 // (csel x, (add x, 1), !cc ...)
7438 // The latter will get matched to a CSINC instruction.
7439 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7440 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7441 SDValue LHS = Op->getOperand(0);
7442 SDValue RHS = Op->getOperand(1);
7443 SetCCInfoAndKind InfoAndKind;
7445 // If neither operand is a SET_CC, give up.
7446 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7447 std::swap(LHS, RHS);
7448 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7452 // FIXME: This could be generatized to work for FP comparisons.
7453 EVT CmpVT = InfoAndKind.IsAArch64
7454 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7455 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7456 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7462 if (InfoAndKind.IsAArch64) {
7463 CCVal = DAG.getConstant(
7464 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7465 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7467 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7468 *InfoAndKind.Info.Generic.Opnd1,
7469 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7472 EVT VT = Op->getValueType(0);
7473 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7474 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7477 // The basic add/sub long vector instructions have variants with "2" on the end
7478 // which act on the high-half of their inputs. They are normally matched by
7481 // (add (zeroext (extract_high LHS)),
7482 // (zeroext (extract_high RHS)))
7483 // -> uaddl2 vD, vN, vM
7485 // However, if one of the extracts is something like a duplicate, this
7486 // instruction can still be used profitably. This function puts the DAG into a
7487 // more appropriate form for those patterns to trigger.
7488 static SDValue performAddSubLongCombine(SDNode *N,
7489 TargetLowering::DAGCombinerInfo &DCI,
7490 SelectionDAG &DAG) {
7491 if (DCI.isBeforeLegalizeOps())
7494 MVT VT = N->getSimpleValueType(0);
7495 if (!VT.is128BitVector()) {
7496 if (N->getOpcode() == ISD::ADD)
7497 return performSetccAddFolding(N, DAG);
7501 // Make sure both branches are extended in the same way.
7502 SDValue LHS = N->getOperand(0);
7503 SDValue RHS = N->getOperand(1);
7504 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7505 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7506 LHS.getOpcode() != RHS.getOpcode())
7509 unsigned ExtType = LHS.getOpcode();
7511 // It's not worth doing if at least one of the inputs isn't already an
7512 // extract, but we don't know which it'll be so we have to try both.
7513 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7514 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7518 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7519 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7520 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7524 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7527 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7530 // Massage DAGs which we can use the high-half "long" operations on into
7531 // something isel will recognize better. E.g.
7533 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7534 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7535 // (extract_high (v2i64 (dup128 scalar)))))
7537 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7538 TargetLowering::DAGCombinerInfo &DCI,
7539 SelectionDAG &DAG) {
7540 if (DCI.isBeforeLegalizeOps())
7543 SDValue LHS = N->getOperand(1);
7544 SDValue RHS = N->getOperand(2);
7545 assert(LHS.getValueType().is64BitVector() &&
7546 RHS.getValueType().is64BitVector() &&
7547 "unexpected shape for long operation");
7549 // Either node could be a DUP, but it's not worth doing both of them (you'd
7550 // just as well use the non-high version) so look for a corresponding extract
7551 // operation on the other "wing".
7552 if (isEssentiallyExtractSubvector(LHS)) {
7553 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7556 } else if (isEssentiallyExtractSubvector(RHS)) {
7557 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7562 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7563 N->getOperand(0), LHS, RHS);
7566 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7567 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7568 unsigned ElemBits = ElemTy.getSizeInBits();
7570 int64_t ShiftAmount;
7571 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7572 APInt SplatValue, SplatUndef;
7573 unsigned SplatBitSize;
7575 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7576 HasAnyUndefs, ElemBits) ||
7577 SplatBitSize != ElemBits)
7580 ShiftAmount = SplatValue.getSExtValue();
7581 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7582 ShiftAmount = CVN->getSExtValue();
7590 llvm_unreachable("Unknown shift intrinsic");
7591 case Intrinsic::aarch64_neon_sqshl:
7592 Opcode = AArch64ISD::SQSHL_I;
7593 IsRightShift = false;
7595 case Intrinsic::aarch64_neon_uqshl:
7596 Opcode = AArch64ISD::UQSHL_I;
7597 IsRightShift = false;
7599 case Intrinsic::aarch64_neon_srshl:
7600 Opcode = AArch64ISD::SRSHR_I;
7601 IsRightShift = true;
7603 case Intrinsic::aarch64_neon_urshl:
7604 Opcode = AArch64ISD::URSHR_I;
7605 IsRightShift = true;
7607 case Intrinsic::aarch64_neon_sqshlu:
7608 Opcode = AArch64ISD::SQSHLU_I;
7609 IsRightShift = false;
7613 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7614 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7615 DAG.getConstant(-ShiftAmount, MVT::i32));
7616 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7617 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7618 DAG.getConstant(ShiftAmount, MVT::i32));
7623 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7624 // the intrinsics must be legal and take an i32, this means there's almost
7625 // certainly going to be a zext in the DAG which we can eliminate.
7626 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7627 SDValue AndN = N->getOperand(2);
7628 if (AndN.getOpcode() != ISD::AND)
7631 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7632 if (!CMask || CMask->getZExtValue() != Mask)
7635 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7636 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7639 static SDValue performIntrinsicCombine(SDNode *N,
7640 TargetLowering::DAGCombinerInfo &DCI,
7641 const AArch64Subtarget *Subtarget) {
7642 SelectionDAG &DAG = DCI.DAG;
7643 unsigned IID = getIntrinsicID(N);
7647 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7648 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7649 return tryCombineFixedPointConvert(N, DCI, DAG);
7651 case Intrinsic::aarch64_neon_fmax:
7652 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7653 N->getOperand(1), N->getOperand(2));
7654 case Intrinsic::aarch64_neon_fmin:
7655 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7656 N->getOperand(1), N->getOperand(2));
7657 case Intrinsic::aarch64_neon_smull:
7658 case Intrinsic::aarch64_neon_umull:
7659 case Intrinsic::aarch64_neon_pmull:
7660 case Intrinsic::aarch64_neon_sqdmull:
7661 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7662 case Intrinsic::aarch64_neon_sqshl:
7663 case Intrinsic::aarch64_neon_uqshl:
7664 case Intrinsic::aarch64_neon_sqshlu:
7665 case Intrinsic::aarch64_neon_srshl:
7666 case Intrinsic::aarch64_neon_urshl:
7667 return tryCombineShiftImm(IID, N, DAG);
7668 case Intrinsic::aarch64_crc32b:
7669 case Intrinsic::aarch64_crc32cb:
7670 return tryCombineCRC32(0xff, N, DAG);
7671 case Intrinsic::aarch64_crc32h:
7672 case Intrinsic::aarch64_crc32ch:
7673 return tryCombineCRC32(0xffff, N, DAG);
7678 static SDValue performExtendCombine(SDNode *N,
7679 TargetLowering::DAGCombinerInfo &DCI,
7680 SelectionDAG &DAG) {
7681 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7682 // we can convert that DUP into another extract_high (of a bigger DUP), which
7683 // helps the backend to decide that an sabdl2 would be useful, saving a real
7684 // extract_high operation.
7685 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7686 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7687 SDNode *ABDNode = N->getOperand(0).getNode();
7688 unsigned IID = getIntrinsicID(ABDNode);
7689 if (IID == Intrinsic::aarch64_neon_sabd ||
7690 IID == Intrinsic::aarch64_neon_uabd) {
7691 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7692 if (!NewABD.getNode())
7695 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7700 // This is effectively a custom type legalization for AArch64.
7702 // Type legalization will split an extend of a small, legal, type to a larger
7703 // illegal type by first splitting the destination type, often creating
7704 // illegal source types, which then get legalized in isel-confusing ways,
7705 // leading to really terrible codegen. E.g.,
7706 // %result = v8i32 sext v8i8 %value
7708 // %losrc = extract_subreg %value, ...
7709 // %hisrc = extract_subreg %value, ...
7710 // %lo = v4i32 sext v4i8 %losrc
7711 // %hi = v4i32 sext v4i8 %hisrc
7712 // Things go rapidly downhill from there.
7714 // For AArch64, the [sz]ext vector instructions can only go up one element
7715 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7716 // take two instructions.
7718 // This implies that the most efficient way to do the extend from v8i8
7719 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7720 // the normal splitting to happen for the v8i16->v8i32.
7722 // This is pre-legalization to catch some cases where the default
7723 // type legalization will create ill-tempered code.
7724 if (!DCI.isBeforeLegalizeOps())
7727 // We're only interested in cleaning things up for non-legal vector types
7728 // here. If both the source and destination are legal, things will just
7729 // work naturally without any fiddling.
7730 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7731 EVT ResVT = N->getValueType(0);
7732 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7734 // If the vector type isn't a simple VT, it's beyond the scope of what
7735 // we're worried about here. Let legalization do its thing and hope for
7737 SDValue Src = N->getOperand(0);
7738 EVT SrcVT = Src->getValueType(0);
7739 if (!ResVT.isSimple() || !SrcVT.isSimple())
7742 // If the source VT is a 64-bit vector, we can play games and get the
7743 // better results we want.
7744 if (SrcVT.getSizeInBits() != 64)
7747 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7748 unsigned ElementCount = SrcVT.getVectorNumElements();
7749 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7751 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7753 // Now split the rest of the operation into two halves, each with a 64
7757 unsigned NumElements = ResVT.getVectorNumElements();
7758 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7759 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7760 ResVT.getVectorElementType(), NumElements / 2);
7762 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7763 LoVT.getVectorNumElements());
7764 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7765 DAG.getIntPtrConstant(0));
7766 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7767 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7768 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7769 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7771 // Now combine the parts back together so we still have a single result
7772 // like the combiner expects.
7773 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7776 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7777 /// value. The load store optimizer pass will merge them to store pair stores.
7778 /// This has better performance than a splat of the scalar followed by a split
7779 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7780 /// followed by an ext.b and two stores.
7781 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7782 SDValue StVal = St->getValue();
7783 EVT VT = StVal.getValueType();
7785 // Don't replace floating point stores, they possibly won't be transformed to
7786 // stp because of the store pair suppress pass.
7787 if (VT.isFloatingPoint())
7790 // Check for insert vector elements.
7791 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7794 // We can express a splat as store pair(s) for 2 or 4 elements.
7795 unsigned NumVecElts = VT.getVectorNumElements();
7796 if (NumVecElts != 4 && NumVecElts != 2)
7798 SDValue SplatVal = StVal.getOperand(1);
7799 unsigned RemainInsertElts = NumVecElts - 1;
7801 // Check that this is a splat.
7802 while (--RemainInsertElts) {
7803 SDValue NextInsertElt = StVal.getOperand(0);
7804 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7806 if (NextInsertElt.getOperand(1) != SplatVal)
7808 StVal = NextInsertElt;
7810 unsigned OrigAlignment = St->getAlignment();
7811 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7812 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7814 // Create scalar stores. This is at least as good as the code sequence for a
7815 // split unaligned store wich is a dup.s, ext.b, and two stores.
7816 // Most of the time the three stores should be replaced by store pair
7817 // instructions (stp).
7819 SDValue BasePtr = St->getBasePtr();
7821 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7822 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7824 unsigned Offset = EltOffset;
7825 while (--NumVecElts) {
7826 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7827 DAG.getConstant(Offset, MVT::i64));
7828 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7829 St->getPointerInfo(), St->isVolatile(),
7830 St->isNonTemporal(), Alignment);
7831 Offset += EltOffset;
7836 static SDValue performSTORECombine(SDNode *N,
7837 TargetLowering::DAGCombinerInfo &DCI,
7839 const AArch64Subtarget *Subtarget) {
7840 if (!DCI.isBeforeLegalize())
7843 StoreSDNode *S = cast<StoreSDNode>(N);
7844 if (S->isVolatile())
7847 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7848 // page boundries. We want to split such stores.
7849 if (!Subtarget->isCyclone())
7852 // Don't split at Oz.
7853 MachineFunction &MF = DAG.getMachineFunction();
7854 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7855 AttributeSet::FunctionIndex, Attribute::MinSize);
7859 SDValue StVal = S->getValue();
7860 EVT VT = StVal.getValueType();
7862 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7863 // those up regresses performance on micro-benchmarks and olden/bh.
7864 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7867 // Split unaligned 16B stores. They are terrible for performance.
7868 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7869 // extensions can use this to mark that it does not want splitting to happen
7870 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7871 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7872 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7873 S->getAlignment() <= 2)
7876 // If we get a splat of a scalar convert this vector store to a store of
7877 // scalars. They will be merged into store pairs thereby removing two
7879 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7880 if (ReplacedSplat != SDValue())
7881 return ReplacedSplat;
7884 unsigned NumElts = VT.getVectorNumElements() / 2;
7885 // Split VT into two.
7887 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7888 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7889 DAG.getIntPtrConstant(0));
7890 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7891 DAG.getIntPtrConstant(NumElts));
7892 SDValue BasePtr = S->getBasePtr();
7894 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7895 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7896 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7897 DAG.getConstant(8, MVT::i64));
7898 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7899 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7903 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7904 /// post-increment LD1R.
7905 static SDValue performPostLD1Combine(SDNode *N,
7906 TargetLowering::DAGCombinerInfo &DCI,
7908 if (DCI.isBeforeLegalizeOps())
7911 SelectionDAG &DAG = DCI.DAG;
7912 EVT VT = N->getValueType(0);
7914 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7915 SDNode *LD = N->getOperand(LoadIdx).getNode();
7916 // If it is not LOAD, can not do such combine.
7917 if (LD->getOpcode() != ISD::LOAD)
7920 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7921 EVT MemVT = LoadSDN->getMemoryVT();
7922 // Check if memory operand is the same type as the vector element.
7923 if (MemVT != VT.getVectorElementType())
7926 // Check if there are other uses. If so, do not combine as it will introduce
7928 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7930 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7936 SDValue Addr = LD->getOperand(1);
7937 SDValue Vector = N->getOperand(0);
7938 // Search for a use of the address operand that is an increment.
7939 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7940 Addr.getNode()->use_end(); UI != UE; ++UI) {
7942 if (User->getOpcode() != ISD::ADD
7943 || UI.getUse().getResNo() != Addr.getResNo())
7946 // Check that the add is independent of the load. Otherwise, folding it
7947 // would create a cycle.
7948 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7950 // Also check that add is not used in the vector operand. This would also
7952 if (User->isPredecessorOf(Vector.getNode()))
7955 // If the increment is a constant, it must match the memory ref size.
7956 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7957 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7958 uint32_t IncVal = CInc->getZExtValue();
7959 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7960 if (IncVal != NumBytes)
7962 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7965 SmallVector<SDValue, 8> Ops;
7966 Ops.push_back(LD->getOperand(0)); // Chain
7968 Ops.push_back(Vector); // The vector to be inserted
7969 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7971 Ops.push_back(Addr);
7974 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7975 SDVTList SDTys = DAG.getVTList(Tys);
7976 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7977 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7979 LoadSDN->getMemOperand());
7982 std::vector<SDValue> NewResults;
7983 NewResults.push_back(SDValue(LD, 0)); // The result of load
7984 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7985 DCI.CombineTo(LD, NewResults);
7986 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7987 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7994 /// Target-specific DAG combine function for NEON load/store intrinsics
7995 /// to merge base address updates.
7996 static SDValue performNEONPostLDSTCombine(SDNode *N,
7997 TargetLowering::DAGCombinerInfo &DCI,
7998 SelectionDAG &DAG) {
7999 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8002 unsigned AddrOpIdx = N->getNumOperands() - 1;
8003 SDValue Addr = N->getOperand(AddrOpIdx);
8005 // Search for a use of the address operand that is an increment.
8006 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8007 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8009 if (User->getOpcode() != ISD::ADD ||
8010 UI.getUse().getResNo() != Addr.getResNo())
8013 // Check that the add is independent of the load/store. Otherwise, folding
8014 // it would create a cycle.
8015 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8018 // Find the new opcode for the updating load/store.
8019 bool IsStore = false;
8020 bool IsLaneOp = false;
8021 bool IsDupOp = false;
8022 unsigned NewOpc = 0;
8023 unsigned NumVecs = 0;
8024 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8026 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8027 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8029 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8031 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8033 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8034 NumVecs = 2; IsStore = true; break;
8035 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8036 NumVecs = 3; IsStore = true; break;
8037 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8038 NumVecs = 4; IsStore = true; break;
8039 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8041 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8043 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8045 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8046 NumVecs = 2; IsStore = true; break;
8047 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8048 NumVecs = 3; IsStore = true; break;
8049 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8050 NumVecs = 4; IsStore = true; break;
8051 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8052 NumVecs = 2; IsDupOp = true; break;
8053 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8054 NumVecs = 3; IsDupOp = true; break;
8055 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8056 NumVecs = 4; IsDupOp = true; break;
8057 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8058 NumVecs = 2; IsLaneOp = true; break;
8059 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8060 NumVecs = 3; IsLaneOp = true; break;
8061 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8062 NumVecs = 4; IsLaneOp = true; break;
8063 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8064 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8065 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8066 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8067 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8068 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8073 VecTy = N->getOperand(2).getValueType();
8075 VecTy = N->getValueType(0);
8077 // If the increment is a constant, it must match the memory ref size.
8078 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8079 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8080 uint32_t IncVal = CInc->getZExtValue();
8081 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8082 if (IsLaneOp || IsDupOp)
8083 NumBytes /= VecTy.getVectorNumElements();
8084 if (IncVal != NumBytes)
8086 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8088 SmallVector<SDValue, 8> Ops;
8089 Ops.push_back(N->getOperand(0)); // Incoming chain
8090 // Load lane and store have vector list as input.
8091 if (IsLaneOp || IsStore)
8092 for (unsigned i = 2; i < AddrOpIdx; ++i)
8093 Ops.push_back(N->getOperand(i));
8094 Ops.push_back(Addr); // Base register
8099 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8101 for (n = 0; n < NumResultVecs; ++n)
8103 Tys[n++] = MVT::i64; // Type of write back register
8104 Tys[n] = MVT::Other; // Type of the chain
8105 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8107 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8108 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8109 MemInt->getMemoryVT(),
8110 MemInt->getMemOperand());
8113 std::vector<SDValue> NewResults;
8114 for (unsigned i = 0; i < NumResultVecs; ++i) {
8115 NewResults.push_back(SDValue(UpdN.getNode(), i));
8117 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8118 DCI.CombineTo(N, NewResults);
8119 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8126 // Checks to see if the value is the prescribed width and returns information
8127 // about its extension mode.
8129 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8130 ExtType = ISD::NON_EXTLOAD;
8131 switch(V.getNode()->getOpcode()) {
8135 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8136 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8137 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8138 ExtType = LoadNode->getExtensionType();
8143 case ISD::AssertSext: {
8144 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8145 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8146 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8147 ExtType = ISD::SEXTLOAD;
8152 case ISD::AssertZext: {
8153 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8154 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8155 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8156 ExtType = ISD::ZEXTLOAD;
8162 case ISD::TargetConstant: {
8163 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8173 // This function does a whole lot of voodoo to determine if the tests are
8174 // equivalent without and with a mask. Essentially what happens is that given a
8177 // +-------------+ +-------------+ +-------------+ +-------------+
8178 // | Input | | AddConstant | | CompConstant| | CC |
8179 // +-------------+ +-------------+ +-------------+ +-------------+
8181 // V V | +----------+
8182 // +-------------+ +----+ | |
8183 // | ADD | |0xff| | |
8184 // +-------------+ +----+ | |
8187 // +-------------+ | |
8189 // +-------------+ | |
8198 // The AND node may be safely removed for some combinations of inputs. In
8199 // particular we need to take into account the extension type of the Input,
8200 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8201 // width of the input (this can work for any width inputs, the above graph is
8202 // specific to 8 bits.
8204 // The specific equations were worked out by generating output tables for each
8205 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8206 // problem was simplified by working with 4 bit inputs, which means we only
8207 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8208 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8209 // patterns present in both extensions (0,7). For every distinct set of
8210 // AddConstant and CompConstants bit patterns we can consider the masked and
8211 // unmasked versions to be equivalent if the result of this function is true for
8212 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8215 // and w10, w8, #0x0f
8217 // cset w9, AArch64CC
8219 // cset w11, AArch64CC
8224 // Since the above function shows when the outputs are equivalent it defines
8225 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8226 // would be expensive to run during compiles. The equations below were written
8227 // in a test harness that confirmed they gave equivalent outputs to the above
8228 // for all inputs function, so they can be used determine if the removal is
8231 // isEquivalentMaskless() is the code for testing if the AND can be removed
8232 // factored out of the DAG recognition as the DAG can take several forms.
8235 bool isEquivalentMaskless(unsigned CC, unsigned width,
8236 ISD::LoadExtType ExtType, signed AddConstant,
8237 signed CompConstant) {
8238 // By being careful about our equations and only writing the in term
8239 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8240 // make them generally applicable to all bit widths.
8241 signed MaxUInt = (1 << width);
8243 // For the purposes of these comparisons sign extending the type is
8244 // equivalent to zero extending the add and displacing it by half the integer
8245 // width. Provided we are careful and make sure our equations are valid over
8246 // the whole range we can just adjust the input and avoid writing equations
8247 // for sign extended inputs.
8248 if (ExtType == ISD::SEXTLOAD)
8249 AddConstant -= (1 << (width-1));
8253 case AArch64CC::GT: {
8254 if ((AddConstant == 0) ||
8255 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8256 (AddConstant >= 0 && CompConstant < 0) ||
8257 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8261 case AArch64CC::GE: {
8262 if ((AddConstant == 0) ||
8263 (AddConstant >= 0 && CompConstant <= 0) ||
8264 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8268 case AArch64CC::LS: {
8269 if ((AddConstant >= 0 && CompConstant < 0) ||
8270 (AddConstant <= 0 && CompConstant >= -1 &&
8271 CompConstant < AddConstant + MaxUInt))
8275 case AArch64CC::MI: {
8276 if ((AddConstant == 0) ||
8277 (AddConstant > 0 && CompConstant <= 0) ||
8278 (AddConstant < 0 && CompConstant <= AddConstant))
8282 case AArch64CC::HS: {
8283 if ((AddConstant >= 0 && CompConstant <= 0) ||
8284 (AddConstant <= 0 && CompConstant >= 0 &&
8285 CompConstant <= AddConstant + MaxUInt))
8289 case AArch64CC::NE: {
8290 if ((AddConstant > 0 && CompConstant < 0) ||
8291 (AddConstant < 0 && CompConstant >= 0 &&
8292 CompConstant < AddConstant + MaxUInt) ||
8293 (AddConstant >= 0 && CompConstant >= 0 &&
8294 CompConstant >= AddConstant) ||
8295 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8304 case AArch64CC::Invalid:
8312 SDValue performCONDCombine(SDNode *N,
8313 TargetLowering::DAGCombinerInfo &DCI,
8314 SelectionDAG &DAG, unsigned CCIndex,
8315 unsigned CmpIndex) {
8316 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8317 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8318 unsigned CondOpcode = SubsNode->getOpcode();
8320 if (CondOpcode != AArch64ISD::SUBS)
8323 // There is a SUBS feeding this condition. Is it fed by a mask we can
8326 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8327 unsigned MaskBits = 0;
8329 if (AndNode->getOpcode() != ISD::AND)
8332 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8333 uint32_t CNV = CN->getZExtValue();
8336 else if (CNV == 65535)
8343 SDValue AddValue = AndNode->getOperand(0);
8345 if (AddValue.getOpcode() != ISD::ADD)
8348 // The basic dag structure is correct, grab the inputs and validate them.
8350 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8351 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8352 SDValue SubsInputValue = SubsNode->getOperand(1);
8354 // The mask is present and the provenance of all the values is a smaller type,
8355 // lets see if the mask is superfluous.
8357 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8358 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8361 ISD::LoadExtType ExtType;
8363 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8364 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8365 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8368 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8369 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8370 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8373 // The AND is not necessary, remove it.
8375 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8376 SubsNode->getValueType(1));
8377 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8379 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8380 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8382 return SDValue(N, 0);
8385 // Optimize compare with zero and branch.
8386 static SDValue performBRCONDCombine(SDNode *N,
8387 TargetLowering::DAGCombinerInfo &DCI,
8388 SelectionDAG &DAG) {
8389 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8392 SDValue Chain = N->getOperand(0);
8393 SDValue Dest = N->getOperand(1);
8394 SDValue CCVal = N->getOperand(2);
8395 SDValue Cmp = N->getOperand(3);
8397 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8398 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8399 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8402 unsigned CmpOpc = Cmp.getOpcode();
8403 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8406 // Only attempt folding if there is only one use of the flag and no use of the
8408 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8411 SDValue LHS = Cmp.getOperand(0);
8412 SDValue RHS = Cmp.getOperand(1);
8414 assert(LHS.getValueType() == RHS.getValueType() &&
8415 "Expected the value type to be the same for both operands!");
8416 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8419 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8420 std::swap(LHS, RHS);
8422 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8425 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8426 LHS.getOpcode() == ISD::SRL)
8429 // Fold the compare into the branch instruction.
8431 if (CC == AArch64CC::EQ)
8432 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8434 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8436 // Do not add new nodes to DAG combiner worklist.
8437 DCI.CombineTo(N, BR, false);
8442 // vselect (v1i1 setcc) ->
8443 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8444 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8445 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8447 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8448 SDValue N0 = N->getOperand(0);
8449 EVT CCVT = N0.getValueType();
8451 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8452 CCVT.getVectorElementType() != MVT::i1)
8455 EVT ResVT = N->getValueType(0);
8456 EVT CmpVT = N0.getOperand(0).getValueType();
8457 // Only combine when the result type is of the same size as the compared
8459 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8462 SDValue IfTrue = N->getOperand(1);
8463 SDValue IfFalse = N->getOperand(2);
8465 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8466 N0.getOperand(0), N0.getOperand(1),
8467 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8468 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8472 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8473 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8474 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8475 /// with a vector one followed by a DUP shuffle on the result.
8476 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8477 SDValue N0 = N->getOperand(0);
8478 EVT ResVT = N->getValueType(0);
8480 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8483 // If NumMaskElts == 0, the comparison is larger than select result. The
8484 // largest real NEON comparison is 64-bits per lane, which means the result is
8485 // at most 32-bits and an illegal vector. Just bail out for now.
8486 EVT SrcVT = N0.getOperand(0).getValueType();
8487 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8488 if (!ResVT.isVector() || NumMaskElts == 0)
8491 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8492 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8494 // First perform a vector comparison, where lane 0 is the one we're interested
8498 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8500 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8501 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8503 // Now duplicate the comparison mask we want across all other lanes.
8504 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8505 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8506 Mask = DAG.getNode(ISD::BITCAST, DL,
8507 ResVT.changeVectorElementTypeToInteger(), Mask);
8509 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8512 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8513 DAGCombinerInfo &DCI) const {
8514 SelectionDAG &DAG = DCI.DAG;
8515 switch (N->getOpcode()) {
8520 return performAddSubLongCombine(N, DCI, DAG);
8522 return performXorCombine(N, DAG, DCI, Subtarget);
8524 return performMulCombine(N, DAG, DCI, Subtarget);
8525 case ISD::SINT_TO_FP:
8526 case ISD::UINT_TO_FP:
8527 return performIntToFpCombine(N, DAG);
8529 return performORCombine(N, DCI, Subtarget);
8530 case ISD::INTRINSIC_WO_CHAIN:
8531 return performIntrinsicCombine(N, DCI, Subtarget);
8532 case ISD::ANY_EXTEND:
8533 case ISD::ZERO_EXTEND:
8534 case ISD::SIGN_EXTEND:
8535 return performExtendCombine(N, DCI, DAG);
8537 return performBitcastCombine(N, DCI, DAG);
8538 case ISD::CONCAT_VECTORS:
8539 return performConcatVectorsCombine(N, DCI, DAG);
8541 return performSelectCombine(N, DAG);
8543 return performVSelectCombine(N, DCI.DAG);
8545 return performSTORECombine(N, DCI, DAG, Subtarget);
8546 case AArch64ISD::BRCOND:
8547 return performBRCONDCombine(N, DCI, DAG);
8548 case AArch64ISD::CSEL:
8549 return performCONDCombine(N, DCI, DAG, 2, 3);
8550 case AArch64ISD::DUP:
8551 return performPostLD1Combine(N, DCI, false);
8552 case ISD::INSERT_VECTOR_ELT:
8553 return performPostLD1Combine(N, DCI, true);
8554 case ISD::INTRINSIC_VOID:
8555 case ISD::INTRINSIC_W_CHAIN:
8556 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8557 case Intrinsic::aarch64_neon_ld2:
8558 case Intrinsic::aarch64_neon_ld3:
8559 case Intrinsic::aarch64_neon_ld4:
8560 case Intrinsic::aarch64_neon_ld1x2:
8561 case Intrinsic::aarch64_neon_ld1x3:
8562 case Intrinsic::aarch64_neon_ld1x4:
8563 case Intrinsic::aarch64_neon_ld2lane:
8564 case Intrinsic::aarch64_neon_ld3lane:
8565 case Intrinsic::aarch64_neon_ld4lane:
8566 case Intrinsic::aarch64_neon_ld2r:
8567 case Intrinsic::aarch64_neon_ld3r:
8568 case Intrinsic::aarch64_neon_ld4r:
8569 case Intrinsic::aarch64_neon_st2:
8570 case Intrinsic::aarch64_neon_st3:
8571 case Intrinsic::aarch64_neon_st4:
8572 case Intrinsic::aarch64_neon_st1x2:
8573 case Intrinsic::aarch64_neon_st1x3:
8574 case Intrinsic::aarch64_neon_st1x4:
8575 case Intrinsic::aarch64_neon_st2lane:
8576 case Intrinsic::aarch64_neon_st3lane:
8577 case Intrinsic::aarch64_neon_st4lane:
8578 return performNEONPostLDSTCombine(N, DCI, DAG);
8586 // Check if the return value is used as only a return value, as otherwise
8587 // we can't perform a tail-call. In particular, we need to check for
8588 // target ISD nodes that are returns and any other "odd" constructs
8589 // that the generic analysis code won't necessarily catch.
8590 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8591 SDValue &Chain) const {
8592 if (N->getNumValues() != 1)
8594 if (!N->hasNUsesOfValue(1, 0))
8597 SDValue TCChain = Chain;
8598 SDNode *Copy = *N->use_begin();
8599 if (Copy->getOpcode() == ISD::CopyToReg) {
8600 // If the copy has a glue operand, we conservatively assume it isn't safe to
8601 // perform a tail call.
8602 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8605 TCChain = Copy->getOperand(0);
8606 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8609 bool HasRet = false;
8610 for (SDNode *Node : Copy->uses()) {
8611 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8623 // Return whether the an instruction can potentially be optimized to a tail
8624 // call. This will cause the optimizers to attempt to move, or duplicate,
8625 // return instructions to help enable tail call optimizations for this
8627 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8628 if (!CI->isTailCall())
8634 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8636 ISD::MemIndexedMode &AM,
8638 SelectionDAG &DAG) const {
8639 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8642 Base = Op->getOperand(0);
8643 // All of the indexed addressing mode instructions take a signed
8644 // 9 bit immediate offset.
8645 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8646 int64_t RHSC = (int64_t)RHS->getZExtValue();
8647 if (RHSC >= 256 || RHSC <= -256)
8649 IsInc = (Op->getOpcode() == ISD::ADD);
8650 Offset = Op->getOperand(1);
8656 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8658 ISD::MemIndexedMode &AM,
8659 SelectionDAG &DAG) const {
8662 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8663 VT = LD->getMemoryVT();
8664 Ptr = LD->getBasePtr();
8665 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8666 VT = ST->getMemoryVT();
8667 Ptr = ST->getBasePtr();
8672 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8674 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8678 bool AArch64TargetLowering::getPostIndexedAddressParts(
8679 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8680 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8683 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8684 VT = LD->getMemoryVT();
8685 Ptr = LD->getBasePtr();
8686 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8687 VT = ST->getMemoryVT();
8688 Ptr = ST->getBasePtr();
8693 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8695 // Post-indexing updates the base, so it's not a valid transform
8696 // if that's not the same as the load's pointer.
8699 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8703 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8704 SelectionDAG &DAG) {
8705 if (N->getValueType(0) != MVT::i16)
8709 SDValue Op = N->getOperand(0);
8710 assert(Op.getValueType() == MVT::f16 &&
8711 "Inconsistent bitcast? Only 16-bit types should be i16 or f16");
8713 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8714 DAG.getUNDEF(MVT::i32), Op,
8715 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8717 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8718 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8721 void AArch64TargetLowering::ReplaceNodeResults(
8722 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8723 switch (N->getOpcode()) {
8725 llvm_unreachable("Don't know how to custom expand this");
8727 ReplaceBITCASTResults(N, Results, DAG);
8729 case ISD::FP_TO_UINT:
8730 case ISD::FP_TO_SINT:
8731 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8732 // Let normal code take care of it by not adding anything to Results.
8737 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8741 TargetLoweringBase::LegalizeTypeAction
8742 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8743 MVT SVT = VT.getSimpleVT();
8744 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8745 // v4i16, v2i32 instead of to promote.
8746 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8747 || SVT == MVT::v1f32)
8748 return TypeWidenVector;
8750 return TargetLoweringBase::getPreferredVectorAction(VT);
8753 // Loads and stores less than 128-bits are already atomic; ones above that
8754 // are doomed anyway, so defer to the default libcall and blame the OS when
8756 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8757 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8761 // Loads and stores less than 128-bits are already atomic; ones above that
8762 // are doomed anyway, so defer to the default libcall and blame the OS when
8764 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8765 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8769 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8770 bool AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8771 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8775 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8779 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8780 AtomicOrdering Ord) const {
8781 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8782 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8783 bool IsAcquire = isAtLeastAcquire(Ord);
8785 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8786 // intrinsic must return {i64, i64} and we have to recombine them into a
8787 // single i128 here.
8788 if (ValTy->getPrimitiveSizeInBits() == 128) {
8790 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8791 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8793 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8794 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8796 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8797 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8798 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8799 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8800 return Builder.CreateOr(
8801 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8804 Type *Tys[] = { Addr->getType() };
8806 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8807 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8809 return Builder.CreateTruncOrBitCast(
8810 Builder.CreateCall(Ldxr, Addr),
8811 cast<PointerType>(Addr->getType())->getElementType());
8814 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8815 Value *Val, Value *Addr,
8816 AtomicOrdering Ord) const {
8817 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8818 bool IsRelease = isAtLeastRelease(Ord);
8820 // Since the intrinsics must have legal type, the i128 intrinsics take two
8821 // parameters: "i64, i64". We must marshal Val into the appropriate form
8823 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8825 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8826 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8827 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8829 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8830 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8831 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8832 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8836 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8837 Type *Tys[] = { Addr->getType() };
8838 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8840 return Builder.CreateCall2(
8841 Stxr, Builder.CreateZExtOrBitCast(
8842 Val, Stxr->getFunctionType()->getParamType(0)),