1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is storage-only, so we promote operations to f32 if we know this is
285 // valid, and ignore them otherwise. The operations not mentioned here will
286 // fail to select, but this is not a major problem as no source language
287 // should be emitting native f16 operations yet.
288 setOperationAction(ISD::FADD, MVT::f16, Promote);
289 setOperationAction(ISD::FDIV, MVT::f16, Promote);
290 setOperationAction(ISD::FMUL, MVT::f16, Promote);
291 setOperationAction(ISD::FSUB, MVT::f16, Promote);
293 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
295 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
296 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
297 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
298 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
299 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
301 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
302 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
308 // Expand all other v4f16 operations.
309 // FIXME: We could generate better code by promoting some operations to
311 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
312 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
315 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
316 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
317 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
319 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
321 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
322 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
323 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
324 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
327 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
328 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
329 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
330 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
332 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
334 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
339 // v8f16 is also a storage-only type, so expand it.
340 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
341 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
342 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
345 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
346 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
347 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
349 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
351 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
353 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
354 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
355 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
356 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
360 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
361 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
362 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
363 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
365 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
366 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
368 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
372 // AArch64 has implementations of a lot of rounding-like FP operations.
373 for (MVT Ty : {MVT::f32, MVT::f64}) {
374 setOperationAction(ISD::FFLOOR, Ty, Legal);
375 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
376 setOperationAction(ISD::FCEIL, Ty, Legal);
377 setOperationAction(ISD::FRINT, Ty, Legal);
378 setOperationAction(ISD::FTRUNC, Ty, Legal);
379 setOperationAction(ISD::FROUND, Ty, Legal);
382 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
384 if (Subtarget->isTargetMachO()) {
385 // For iOS, we don't want to the normal expansion of a libcall to
386 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
388 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
389 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
391 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
392 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
395 // Make floating-point constants legal for the large code model, so they don't
396 // become loads from the constant pool.
397 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
398 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
399 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
402 // AArch64 does not have floating-point extending loads, i1 sign-extending
403 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
404 for (MVT VT : MVT::fp_valuetypes()) {
405 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
406 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
407 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
408 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
410 for (MVT VT : MVT::integer_valuetypes())
411 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
413 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
414 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
415 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
416 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
417 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
418 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
419 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
421 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
422 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
424 // Indexed loads and stores are supported.
425 for (unsigned im = (unsigned)ISD::PRE_INC;
426 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
427 setIndexedLoadAction(im, MVT::i8, Legal);
428 setIndexedLoadAction(im, MVT::i16, Legal);
429 setIndexedLoadAction(im, MVT::i32, Legal);
430 setIndexedLoadAction(im, MVT::i64, Legal);
431 setIndexedLoadAction(im, MVT::f64, Legal);
432 setIndexedLoadAction(im, MVT::f32, Legal);
433 setIndexedStoreAction(im, MVT::i8, Legal);
434 setIndexedStoreAction(im, MVT::i16, Legal);
435 setIndexedStoreAction(im, MVT::i32, Legal);
436 setIndexedStoreAction(im, MVT::i64, Legal);
437 setIndexedStoreAction(im, MVT::f64, Legal);
438 setIndexedStoreAction(im, MVT::f32, Legal);
442 setOperationAction(ISD::TRAP, MVT::Other, Legal);
444 // We combine OR nodes for bitfield operations.
445 setTargetDAGCombine(ISD::OR);
447 // Vector add and sub nodes may conceal a high-half opportunity.
448 // Also, try to fold ADD into CSINC/CSINV..
449 setTargetDAGCombine(ISD::ADD);
450 setTargetDAGCombine(ISD::SUB);
452 setTargetDAGCombine(ISD::XOR);
453 setTargetDAGCombine(ISD::SINT_TO_FP);
454 setTargetDAGCombine(ISD::UINT_TO_FP);
456 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::ANY_EXTEND);
459 setTargetDAGCombine(ISD::ZERO_EXTEND);
460 setTargetDAGCombine(ISD::SIGN_EXTEND);
461 setTargetDAGCombine(ISD::BITCAST);
462 setTargetDAGCombine(ISD::CONCAT_VECTORS);
463 setTargetDAGCombine(ISD::STORE);
465 setTargetDAGCombine(ISD::MUL);
467 setTargetDAGCombine(ISD::SELECT);
468 setTargetDAGCombine(ISD::VSELECT);
470 setTargetDAGCombine(ISD::INTRINSIC_VOID);
471 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
472 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
474 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
475 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
476 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
478 setStackPointerRegisterToSaveRestore(AArch64::SP);
480 setSchedulingPreference(Sched::Hybrid);
483 MaskAndBranchFoldingIsLegal = true;
485 setMinFunctionAlignment(2);
487 RequireStrictAlign = (Align == StrictAlign);
489 setHasExtractBitsInsn(true);
491 if (Subtarget->hasNEON()) {
492 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
493 // silliness like this:
494 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
495 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
496 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
498 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
499 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
500 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
501 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
502 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
503 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
504 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
505 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
506 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
507 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
508 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
509 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
510 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
511 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
512 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
513 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
514 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
515 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
516 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
517 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
518 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
520 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
521 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
522 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
523 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
524 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
526 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
528 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
529 // elements smaller than i32, so promote the input to i32 first.
530 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
531 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
532 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
533 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
534 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
535 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
536 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
537 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
538 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
540 // AArch64 doesn't have MUL.2d:
541 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
542 // Custom handling for some quad-vector types to detect MULL.
543 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
544 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
545 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
547 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
548 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
549 // Likewise, narrowing and extending vector loads/stores aren't handled
551 for (MVT VT : MVT::vector_valuetypes()) {
552 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
554 setOperationAction(ISD::MULHS, VT, Expand);
555 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
556 setOperationAction(ISD::MULHU, VT, Expand);
557 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
559 setOperationAction(ISD::BSWAP, VT, Expand);
561 for (MVT InnerVT : MVT::vector_valuetypes()) {
562 setTruncStoreAction(VT, InnerVT, Expand);
563 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
564 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
565 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
569 // AArch64 has implementations of a lot of rounding-like FP operations.
570 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
571 setOperationAction(ISD::FFLOOR, Ty, Legal);
572 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
573 setOperationAction(ISD::FCEIL, Ty, Legal);
574 setOperationAction(ISD::FRINT, Ty, Legal);
575 setOperationAction(ISD::FTRUNC, Ty, Legal);
576 setOperationAction(ISD::FROUND, Ty, Legal);
580 // Prefer likely predicted branches to selects on out-of-order cores.
581 if (Subtarget->isCortexA57())
582 PredictableSelectIsExpensive = true;
585 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
586 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
587 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
588 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
590 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
591 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
592 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
593 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
594 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
596 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
597 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
600 // Mark vector float intrinsics as expand.
601 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
602 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
603 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
604 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
605 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
606 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
607 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
608 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
609 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
610 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
613 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
614 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
615 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
616 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
617 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
618 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
619 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
620 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
621 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
622 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
623 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
624 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
626 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
627 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
629 for (MVT InnerVT : MVT::all_valuetypes())
630 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
632 // CNT supports only B element sizes.
633 if (VT != MVT::v8i8 && VT != MVT::v16i8)
634 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
636 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
637 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
638 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
639 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
640 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
643 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
645 if (Subtarget->isLittleEndian()) {
646 for (unsigned im = (unsigned)ISD::PRE_INC;
647 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
648 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
649 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
654 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
655 addRegisterClass(VT, &AArch64::FPR64RegClass);
656 addTypeForNEON(VT, MVT::v2i32);
659 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
660 addRegisterClass(VT, &AArch64::FPR128RegClass);
661 addTypeForNEON(VT, MVT::v4i32);
664 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
667 return VT.changeVectorElementTypeToInteger();
670 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
671 /// Mask are known to be either zero or one and return them in the
672 /// KnownZero/KnownOne bitsets.
673 void AArch64TargetLowering::computeKnownBitsForTargetNode(
674 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
675 const SelectionDAG &DAG, unsigned Depth) const {
676 switch (Op.getOpcode()) {
679 case AArch64ISD::CSEL: {
680 APInt KnownZero2, KnownOne2;
681 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
682 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
683 KnownZero &= KnownZero2;
684 KnownOne &= KnownOne2;
687 case ISD::INTRINSIC_W_CHAIN: {
688 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
689 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
692 case Intrinsic::aarch64_ldaxr:
693 case Intrinsic::aarch64_ldxr: {
694 unsigned BitWidth = KnownOne.getBitWidth();
695 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
696 unsigned MemBits = VT.getScalarType().getSizeInBits();
697 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
703 case ISD::INTRINSIC_WO_CHAIN:
704 case ISD::INTRINSIC_VOID: {
705 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
709 case Intrinsic::aarch64_neon_umaxv:
710 case Intrinsic::aarch64_neon_uminv: {
711 // Figure out the datatype of the vector operand. The UMINV instruction
712 // will zero extend the result, so we can mark as known zero all the
713 // bits larger than the element datatype. 32-bit or larget doesn't need
714 // this as those are legal types and will be handled by isel directly.
715 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
716 unsigned BitWidth = KnownZero.getBitWidth();
717 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
718 assert(BitWidth >= 8 && "Unexpected width!");
719 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
721 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
722 assert(BitWidth >= 16 && "Unexpected width!");
723 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
733 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
738 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
739 const TargetLibraryInfo *libInfo) const {
740 return AArch64::createFastISel(funcInfo, libInfo);
743 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
747 case AArch64ISD::CALL: return "AArch64ISD::CALL";
748 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
749 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
750 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
751 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
752 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
753 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
754 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
755 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
756 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
757 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
758 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
759 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
760 case AArch64ISD::ADC: return "AArch64ISD::ADC";
761 case AArch64ISD::SBC: return "AArch64ISD::SBC";
762 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
763 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
764 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
765 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
766 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
767 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
768 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
769 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
770 case AArch64ISD::DUP: return "AArch64ISD::DUP";
771 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
772 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
773 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
774 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
775 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
776 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
777 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
778 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
779 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
780 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
781 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
782 case AArch64ISD::BICi: return "AArch64ISD::BICi";
783 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
784 case AArch64ISD::BSL: return "AArch64ISD::BSL";
785 case AArch64ISD::NEG: return "AArch64ISD::NEG";
786 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
787 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
788 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
789 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
790 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
791 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
792 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
793 case AArch64ISD::REV16: return "AArch64ISD::REV16";
794 case AArch64ISD::REV32: return "AArch64ISD::REV32";
795 case AArch64ISD::REV64: return "AArch64ISD::REV64";
796 case AArch64ISD::EXT: return "AArch64ISD::EXT";
797 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
798 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
799 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
800 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
801 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
802 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
803 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
804 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
805 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
806 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
807 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
808 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
809 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
810 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
811 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
812 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
813 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
814 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
815 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
816 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
817 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
818 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
819 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
820 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
821 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
822 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
823 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
824 case AArch64ISD::NOT: return "AArch64ISD::NOT";
825 case AArch64ISD::BIT: return "AArch64ISD::BIT";
826 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
827 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
828 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
829 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
830 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
831 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
832 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
833 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
834 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
835 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
836 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
837 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
838 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
839 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
840 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
841 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
842 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
843 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
844 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
845 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
846 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
847 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
848 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
849 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
850 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
851 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
852 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
853 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
854 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
855 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
856 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
857 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
858 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
859 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
860 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
861 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
862 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
863 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
864 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
869 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
870 MachineBasicBlock *MBB) const {
871 // We materialise the F128CSEL pseudo-instruction as some control flow and a
875 // [... previous instrs leading to comparison ...]
881 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
883 MachineFunction *MF = MBB->getParent();
884 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
885 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
886 DebugLoc DL = MI->getDebugLoc();
887 MachineFunction::iterator It = MBB;
890 unsigned DestReg = MI->getOperand(0).getReg();
891 unsigned IfTrueReg = MI->getOperand(1).getReg();
892 unsigned IfFalseReg = MI->getOperand(2).getReg();
893 unsigned CondCode = MI->getOperand(3).getImm();
894 bool NZCVKilled = MI->getOperand(4).isKill();
896 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
897 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
898 MF->insert(It, TrueBB);
899 MF->insert(It, EndBB);
901 // Transfer rest of current basic-block to EndBB
902 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
904 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
906 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
907 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
908 MBB->addSuccessor(TrueBB);
909 MBB->addSuccessor(EndBB);
911 // TrueBB falls through to the end.
912 TrueBB->addSuccessor(EndBB);
915 TrueBB->addLiveIn(AArch64::NZCV);
916 EndBB->addLiveIn(AArch64::NZCV);
919 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
925 MI->eraseFromParent();
930 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
931 MachineBasicBlock *BB) const {
932 switch (MI->getOpcode()) {
937 llvm_unreachable("Unexpected instruction for custom inserter!");
939 case AArch64::F128CSEL:
940 return EmitF128CSEL(MI, BB);
942 case TargetOpcode::STACKMAP:
943 case TargetOpcode::PATCHPOINT:
944 return emitPatchPoint(MI, BB);
948 //===----------------------------------------------------------------------===//
949 // AArch64 Lowering private implementation.
950 //===----------------------------------------------------------------------===//
952 //===----------------------------------------------------------------------===//
954 //===----------------------------------------------------------------------===//
956 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
958 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
961 llvm_unreachable("Unknown condition code!");
963 return AArch64CC::NE;
965 return AArch64CC::EQ;
967 return AArch64CC::GT;
969 return AArch64CC::GE;
971 return AArch64CC::LT;
973 return AArch64CC::LE;
975 return AArch64CC::HI;
977 return AArch64CC::HS;
979 return AArch64CC::LO;
981 return AArch64CC::LS;
985 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
986 static void changeFPCCToAArch64CC(ISD::CondCode CC,
987 AArch64CC::CondCode &CondCode,
988 AArch64CC::CondCode &CondCode2) {
989 CondCode2 = AArch64CC::AL;
992 llvm_unreachable("Unknown FP condition!");
995 CondCode = AArch64CC::EQ;
999 CondCode = AArch64CC::GT;
1003 CondCode = AArch64CC::GE;
1006 CondCode = AArch64CC::MI;
1009 CondCode = AArch64CC::LS;
1012 CondCode = AArch64CC::MI;
1013 CondCode2 = AArch64CC::GT;
1016 CondCode = AArch64CC::VC;
1019 CondCode = AArch64CC::VS;
1022 CondCode = AArch64CC::EQ;
1023 CondCode2 = AArch64CC::VS;
1026 CondCode = AArch64CC::HI;
1029 CondCode = AArch64CC::PL;
1033 CondCode = AArch64CC::LT;
1037 CondCode = AArch64CC::LE;
1041 CondCode = AArch64CC::NE;
1046 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1047 /// CC usable with the vector instructions. Fewer operations are available
1048 /// without a real NZCV register, so we have to use less efficient combinations
1049 /// to get the same effect.
1050 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1051 AArch64CC::CondCode &CondCode,
1052 AArch64CC::CondCode &CondCode2,
1057 // Mostly the scalar mappings work fine.
1058 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1061 Invert = true; // Fallthrough
1063 CondCode = AArch64CC::MI;
1064 CondCode2 = AArch64CC::GE;
1071 // All of the compare-mask comparisons are ordered, but we can switch
1072 // between the two by a double inversion. E.g. ULE == !OGT.
1074 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1079 static bool isLegalArithImmed(uint64_t C) {
1080 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1081 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1084 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1085 SDLoc dl, SelectionDAG &DAG) {
1086 EVT VT = LHS.getValueType();
1088 if (VT.isFloatingPoint())
1089 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1091 // The CMP instruction is just an alias for SUBS, and representing it as
1092 // SUBS means that it's possible to get CSE with subtract operations.
1093 // A later phase can perform the optimization of setting the destination
1094 // register to WZR/XZR if it ends up being unused.
1095 unsigned Opcode = AArch64ISD::SUBS;
1097 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1098 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1099 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1100 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1101 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1102 // can be set differently by this operation. It comes down to whether
1103 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1104 // everything is fine. If not then the optimization is wrong. Thus general
1105 // comparisons are only valid if op2 != 0.
1107 // So, finally, the only LLVM-native comparisons that don't mention C and V
1108 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1109 // the absence of information about op2.
1110 Opcode = AArch64ISD::ADDS;
1111 RHS = RHS.getOperand(1);
1112 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1113 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1114 !isUnsignedIntSetCC(CC)) {
1115 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1116 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1117 // of the signed comparisons.
1118 Opcode = AArch64ISD::ANDS;
1119 RHS = LHS.getOperand(1);
1120 LHS = LHS.getOperand(0);
1123 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1127 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1128 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1130 AArch64CC::CondCode AArch64CC;
1131 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1132 EVT VT = RHS.getValueType();
1133 uint64_t C = RHSC->getZExtValue();
1134 if (!isLegalArithImmed(C)) {
1135 // Constant does not fit, try adjusting it by one?
1141 if ((VT == MVT::i32 && C != 0x80000000 &&
1142 isLegalArithImmed((uint32_t)(C - 1))) ||
1143 (VT == MVT::i64 && C != 0x80000000ULL &&
1144 isLegalArithImmed(C - 1ULL))) {
1145 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1146 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1147 RHS = DAG.getConstant(C, VT);
1152 if ((VT == MVT::i32 && C != 0 &&
1153 isLegalArithImmed((uint32_t)(C - 1))) ||
1154 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1155 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1156 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1157 RHS = DAG.getConstant(C, VT);
1162 if ((VT == MVT::i32 && C != INT32_MAX &&
1163 isLegalArithImmed((uint32_t)(C + 1))) ||
1164 (VT == MVT::i64 && C != INT64_MAX &&
1165 isLegalArithImmed(C + 1ULL))) {
1166 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1167 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1168 RHS = DAG.getConstant(C, VT);
1173 if ((VT == MVT::i32 && C != UINT32_MAX &&
1174 isLegalArithImmed((uint32_t)(C + 1))) ||
1175 (VT == MVT::i64 && C != UINT64_MAX &&
1176 isLegalArithImmed(C + 1ULL))) {
1177 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1178 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1179 RHS = DAG.getConstant(C, VT);
1185 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1186 // For the i8 operand, the largest immediate is 255, so this can be easily
1187 // encoded in the compare instruction. For the i16 operand, however, the
1188 // largest immediate cannot be encoded in the compare.
1189 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1190 // constant. For example,
1192 // ldrh w0, [x0, #0]
1195 // ldrsh w0, [x0, #0]
1197 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1198 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1199 // both the LHS and RHS are truely zero extended and to make sure the
1200 // transformation is profitable.
1201 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1202 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1203 isa<LoadSDNode>(LHS)) {
1204 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1205 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1206 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1207 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1208 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1210 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1211 DAG.getValueType(MVT::i16));
1212 Cmp = emitComparison(SExt,
1213 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1215 AArch64CC = changeIntCCToAArch64CC(CC);
1216 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1222 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1223 AArch64CC = changeIntCCToAArch64CC(CC);
1224 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1228 static std::pair<SDValue, SDValue>
1229 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1230 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1231 "Unsupported value type");
1232 SDValue Value, Overflow;
1234 SDValue LHS = Op.getOperand(0);
1235 SDValue RHS = Op.getOperand(1);
1237 switch (Op.getOpcode()) {
1239 llvm_unreachable("Unknown overflow instruction!");
1241 Opc = AArch64ISD::ADDS;
1245 Opc = AArch64ISD::ADDS;
1249 Opc = AArch64ISD::SUBS;
1253 Opc = AArch64ISD::SUBS;
1256 // Multiply needs a little bit extra work.
1260 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1261 if (Op.getValueType() == MVT::i32) {
1262 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1263 // For a 32 bit multiply with overflow check we want the instruction
1264 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1265 // need to generate the following pattern:
1266 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1267 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1268 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1269 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1270 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1271 DAG.getConstant(0, MVT::i64));
1272 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1273 // operation. We need to clear out the upper 32 bits, because we used a
1274 // widening multiply that wrote all 64 bits. In the end this should be a
1276 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1278 // The signed overflow check requires more than just a simple check for
1279 // any bit set in the upper 32 bits of the result. These bits could be
1280 // just the sign bits of a negative number. To perform the overflow
1281 // check we have to arithmetic shift right the 32nd bit of the result by
1282 // 31 bits. Then we compare the result to the upper 32 bits.
1283 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1284 DAG.getConstant(32, MVT::i64));
1285 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1286 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1287 DAG.getConstant(31, MVT::i64));
1288 // It is important that LowerBits is last, otherwise the arithmetic
1289 // shift will not be folded into the compare (SUBS).
1290 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1291 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1294 // The overflow check for unsigned multiply is easy. We only need to
1295 // check if any of the upper 32 bits are set. This can be done with a
1296 // CMP (shifted register). For that we need to generate the following
1298 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1299 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1300 DAG.getConstant(32, MVT::i64));
1301 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1303 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1304 UpperBits).getValue(1);
1308 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1309 // For the 64 bit multiply
1310 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1312 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1313 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1314 DAG.getConstant(63, MVT::i64));
1315 // It is important that LowerBits is last, otherwise the arithmetic
1316 // shift will not be folded into the compare (SUBS).
1317 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1318 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1321 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1322 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1324 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1325 UpperBits).getValue(1);
1332 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1334 // Emit the AArch64 operation with overflow check.
1335 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1336 Overflow = Value.getValue(1);
1338 return std::make_pair(Value, Overflow);
1341 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1342 RTLIB::Libcall Call) const {
1343 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1344 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1348 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1349 SDValue Sel = Op.getOperand(0);
1350 SDValue Other = Op.getOperand(1);
1352 // If neither operand is a SELECT_CC, give up.
1353 if (Sel.getOpcode() != ISD::SELECT_CC)
1354 std::swap(Sel, Other);
1355 if (Sel.getOpcode() != ISD::SELECT_CC)
1358 // The folding we want to perform is:
1359 // (xor x, (select_cc a, b, cc, 0, -1) )
1361 // (csel x, (xor x, -1), cc ...)
1363 // The latter will get matched to a CSINV instruction.
1365 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1366 SDValue LHS = Sel.getOperand(0);
1367 SDValue RHS = Sel.getOperand(1);
1368 SDValue TVal = Sel.getOperand(2);
1369 SDValue FVal = Sel.getOperand(3);
1372 // FIXME: This could be generalized to non-integer comparisons.
1373 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1376 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1377 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1379 // The the values aren't constants, this isn't the pattern we're looking for.
1380 if (!CFVal || !CTVal)
1383 // We can commute the SELECT_CC by inverting the condition. This
1384 // might be needed to make this fit into a CSINV pattern.
1385 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1386 std::swap(TVal, FVal);
1387 std::swap(CTVal, CFVal);
1388 CC = ISD::getSetCCInverse(CC, true);
1391 // If the constants line up, perform the transform!
1392 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1394 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1397 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1398 DAG.getConstant(-1ULL, Other.getValueType()));
1400 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1407 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1408 EVT VT = Op.getValueType();
1410 // Let legalize expand this if it isn't a legal type yet.
1411 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1414 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1417 bool ExtraOp = false;
1418 switch (Op.getOpcode()) {
1420 llvm_unreachable("Invalid code");
1422 Opc = AArch64ISD::ADDS;
1425 Opc = AArch64ISD::SUBS;
1428 Opc = AArch64ISD::ADCS;
1432 Opc = AArch64ISD::SBCS;
1438 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1439 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1443 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1444 // Let legalize expand this if it isn't a legal type yet.
1445 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1448 AArch64CC::CondCode CC;
1449 // The actual operation that sets the overflow or carry flag.
1450 SDValue Value, Overflow;
1451 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1453 // We use 0 and 1 as false and true values.
1454 SDValue TVal = DAG.getConstant(1, MVT::i32);
1455 SDValue FVal = DAG.getConstant(0, MVT::i32);
1457 // We use an inverted condition, because the conditional select is inverted
1458 // too. This will allow it to be selected to a single instruction:
1459 // CSINC Wd, WZR, WZR, invert(cond).
1460 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1461 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1464 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1465 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1468 // Prefetch operands are:
1469 // 1: Address to prefetch
1471 // 3: int locality (0 = no locality ... 3 = extreme locality)
1472 // 4: bool isDataCache
1473 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1475 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1476 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1477 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1479 bool IsStream = !Locality;
1480 // When the locality number is set
1482 // The front-end should have filtered out the out-of-range values
1483 assert(Locality <= 3 && "Prefetch locality out-of-range");
1484 // The locality degree is the opposite of the cache speed.
1485 // Put the number the other way around.
1486 // The encoding starts at 0 for level 1
1487 Locality = 3 - Locality;
1490 // built the mask value encoding the expected behavior.
1491 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1492 (!IsData << 3) | // IsDataCache bit
1493 (Locality << 1) | // Cache level bits
1494 (unsigned)IsStream; // Stream bit
1495 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1496 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1499 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1500 SelectionDAG &DAG) const {
1501 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1504 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1506 return LowerF128Call(Op, DAG, LC);
1509 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1510 SelectionDAG &DAG) const {
1511 if (Op.getOperand(0).getValueType() != MVT::f128) {
1512 // It's legal except when f128 is involved
1517 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1519 // FP_ROUND node has a second operand indicating whether it is known to be
1520 // precise. That doesn't take part in the LibCall so we can't directly use
1522 SDValue SrcVal = Op.getOperand(0);
1523 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1524 /*isSigned*/ false, SDLoc(Op)).first;
1527 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1528 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1529 // Any additional optimization in this function should be recorded
1530 // in the cost tables.
1531 EVT InVT = Op.getOperand(0).getValueType();
1532 EVT VT = Op.getValueType();
1534 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1537 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1539 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1542 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1545 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1546 VT.getVectorNumElements());
1547 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1548 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1551 // Type changing conversions are illegal.
1555 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1556 SelectionDAG &DAG) const {
1557 if (Op.getOperand(0).getValueType().isVector())
1558 return LowerVectorFP_TO_INT(Op, DAG);
1560 if (Op.getOperand(0).getValueType() != MVT::f128) {
1561 // It's legal except when f128 is involved
1566 if (Op.getOpcode() == ISD::FP_TO_SINT)
1567 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1569 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1571 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1572 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1576 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1577 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1578 // Any additional optimization in this function should be recorded
1579 // in the cost tables.
1580 EVT VT = Op.getValueType();
1582 SDValue In = Op.getOperand(0);
1583 EVT InVT = In.getValueType();
1585 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1587 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1588 InVT.getVectorNumElements());
1589 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1590 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1593 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1595 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1596 EVT CastVT = VT.changeVectorElementTypeToInteger();
1597 In = DAG.getNode(CastOpc, dl, CastVT, In);
1598 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1604 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1605 SelectionDAG &DAG) const {
1606 if (Op.getValueType().isVector())
1607 return LowerVectorINT_TO_FP(Op, DAG);
1609 // i128 conversions are libcalls.
1610 if (Op.getOperand(0).getValueType() == MVT::i128)
1613 // Other conversions are legal, unless it's to the completely software-based
1615 if (Op.getValueType() != MVT::f128)
1619 if (Op.getOpcode() == ISD::SINT_TO_FP)
1620 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1622 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1624 return LowerF128Call(Op, DAG, LC);
1627 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1628 SelectionDAG &DAG) const {
1629 // For iOS, we want to call an alternative entry point: __sincos_stret,
1630 // which returns the values in two S / D registers.
1632 SDValue Arg = Op.getOperand(0);
1633 EVT ArgVT = Arg.getValueType();
1634 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1641 Entry.isSExt = false;
1642 Entry.isZExt = false;
1643 Args.push_back(Entry);
1645 const char *LibcallName =
1646 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1647 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1649 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1650 TargetLowering::CallLoweringInfo CLI(DAG);
1651 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1652 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1654 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1655 return CallResult.first;
1658 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1659 if (Op.getValueType() != MVT::f16)
1662 assert(Op.getOperand(0).getValueType() == MVT::i16);
1665 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1666 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1668 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1669 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1673 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1674 if (OrigVT.getSizeInBits() >= 64)
1677 assert(OrigVT.isSimple() && "Expecting a simple value type");
1679 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1680 switch (OrigSimpleTy) {
1681 default: llvm_unreachable("Unexpected Vector Type");
1690 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1693 unsigned ExtOpcode) {
1694 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1695 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1696 // 64-bits we need to insert a new extension so that it will be 64-bits.
1697 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1698 if (OrigTy.getSizeInBits() >= 64)
1701 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1702 EVT NewVT = getExtensionTo64Bits(OrigTy);
1704 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1707 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1709 EVT VT = N->getValueType(0);
1711 if (N->getOpcode() != ISD::BUILD_VECTOR)
1714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1715 SDNode *Elt = N->getOperand(i).getNode();
1716 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1717 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1718 unsigned HalfSize = EltSize / 2;
1720 if (!isIntN(HalfSize, C->getSExtValue()))
1723 if (!isUIntN(HalfSize, C->getZExtValue()))
1734 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1735 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1736 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1737 N->getOperand(0)->getValueType(0),
1741 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1742 EVT VT = N->getValueType(0);
1743 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1744 unsigned NumElts = VT.getVectorNumElements();
1745 MVT TruncVT = MVT::getIntegerVT(EltSize);
1746 SmallVector<SDValue, 8> Ops;
1747 for (unsigned i = 0; i != NumElts; ++i) {
1748 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1749 const APInt &CInt = C->getAPIntValue();
1750 // Element types smaller than 32 bits are not legal, so use i32 elements.
1751 // The values are implicitly truncated so sext vs. zext doesn't matter.
1752 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1754 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1755 MVT::getVectorVT(TruncVT, NumElts), Ops);
1758 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1759 if (N->getOpcode() == ISD::SIGN_EXTEND)
1761 if (isExtendedBUILD_VECTOR(N, DAG, true))
1766 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1767 if (N->getOpcode() == ISD::ZERO_EXTEND)
1769 if (isExtendedBUILD_VECTOR(N, DAG, false))
1774 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1775 unsigned Opcode = N->getOpcode();
1776 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1777 SDNode *N0 = N->getOperand(0).getNode();
1778 SDNode *N1 = N->getOperand(1).getNode();
1779 return N0->hasOneUse() && N1->hasOneUse() &&
1780 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1785 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1786 unsigned Opcode = N->getOpcode();
1787 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1788 SDNode *N0 = N->getOperand(0).getNode();
1789 SDNode *N1 = N->getOperand(1).getNode();
1790 return N0->hasOneUse() && N1->hasOneUse() &&
1791 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1796 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1797 // Multiplications are only custom-lowered for 128-bit vectors so that
1798 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1799 EVT VT = Op.getValueType();
1800 assert(VT.is128BitVector() && VT.isInteger() &&
1801 "unexpected type for custom-lowering ISD::MUL");
1802 SDNode *N0 = Op.getOperand(0).getNode();
1803 SDNode *N1 = Op.getOperand(1).getNode();
1804 unsigned NewOpc = 0;
1806 bool isN0SExt = isSignExtended(N0, DAG);
1807 bool isN1SExt = isSignExtended(N1, DAG);
1808 if (isN0SExt && isN1SExt)
1809 NewOpc = AArch64ISD::SMULL;
1811 bool isN0ZExt = isZeroExtended(N0, DAG);
1812 bool isN1ZExt = isZeroExtended(N1, DAG);
1813 if (isN0ZExt && isN1ZExt)
1814 NewOpc = AArch64ISD::UMULL;
1815 else if (isN1SExt || isN1ZExt) {
1816 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1817 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1818 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1819 NewOpc = AArch64ISD::SMULL;
1821 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1822 NewOpc = AArch64ISD::UMULL;
1824 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1826 NewOpc = AArch64ISD::UMULL;
1832 if (VT == MVT::v2i64)
1833 // Fall through to expand this. It is not legal.
1836 // Other vector multiplications are legal.
1841 // Legalize to a S/UMULL instruction
1844 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1846 Op0 = skipExtensionForVectorMULL(N0, DAG);
1847 assert(Op0.getValueType().is64BitVector() &&
1848 Op1.getValueType().is64BitVector() &&
1849 "unexpected types for extended operands to VMULL");
1850 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1852 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1853 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1854 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1855 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1856 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1857 EVT Op1VT = Op1.getValueType();
1858 return DAG.getNode(N0->getOpcode(), DL, VT,
1859 DAG.getNode(NewOpc, DL, VT,
1860 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1861 DAG.getNode(NewOpc, DL, VT,
1862 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1865 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1866 SelectionDAG &DAG) const {
1867 switch (Op.getOpcode()) {
1869 llvm_unreachable("unimplemented operand");
1872 return LowerBITCAST(Op, DAG);
1873 case ISD::GlobalAddress:
1874 return LowerGlobalAddress(Op, DAG);
1875 case ISD::GlobalTLSAddress:
1876 return LowerGlobalTLSAddress(Op, DAG);
1878 return LowerSETCC(Op, DAG);
1880 return LowerBR_CC(Op, DAG);
1882 return LowerSELECT(Op, DAG);
1883 case ISD::SELECT_CC:
1884 return LowerSELECT_CC(Op, DAG);
1885 case ISD::JumpTable:
1886 return LowerJumpTable(Op, DAG);
1887 case ISD::ConstantPool:
1888 return LowerConstantPool(Op, DAG);
1889 case ISD::BlockAddress:
1890 return LowerBlockAddress(Op, DAG);
1892 return LowerVASTART(Op, DAG);
1894 return LowerVACOPY(Op, DAG);
1896 return LowerVAARG(Op, DAG);
1901 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1908 return LowerXALUO(Op, DAG);
1910 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1912 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1914 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1916 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1918 return LowerFP_ROUND(Op, DAG);
1919 case ISD::FP_EXTEND:
1920 return LowerFP_EXTEND(Op, DAG);
1921 case ISD::FRAMEADDR:
1922 return LowerFRAMEADDR(Op, DAG);
1923 case ISD::RETURNADDR:
1924 return LowerRETURNADDR(Op, DAG);
1925 case ISD::INSERT_VECTOR_ELT:
1926 return LowerINSERT_VECTOR_ELT(Op, DAG);
1927 case ISD::EXTRACT_VECTOR_ELT:
1928 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1929 case ISD::BUILD_VECTOR:
1930 return LowerBUILD_VECTOR(Op, DAG);
1931 case ISD::VECTOR_SHUFFLE:
1932 return LowerVECTOR_SHUFFLE(Op, DAG);
1933 case ISD::EXTRACT_SUBVECTOR:
1934 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1938 return LowerVectorSRA_SRL_SHL(Op, DAG);
1939 case ISD::SHL_PARTS:
1940 return LowerShiftLeftParts(Op, DAG);
1941 case ISD::SRL_PARTS:
1942 case ISD::SRA_PARTS:
1943 return LowerShiftRightParts(Op, DAG);
1945 return LowerCTPOP(Op, DAG);
1946 case ISD::FCOPYSIGN:
1947 return LowerFCOPYSIGN(Op, DAG);
1949 return LowerVectorAND(Op, DAG);
1951 return LowerVectorOR(Op, DAG);
1953 return LowerXOR(Op, DAG);
1955 return LowerPREFETCH(Op, DAG);
1956 case ISD::SINT_TO_FP:
1957 case ISD::UINT_TO_FP:
1958 return LowerINT_TO_FP(Op, DAG);
1959 case ISD::FP_TO_SINT:
1960 case ISD::FP_TO_UINT:
1961 return LowerFP_TO_INT(Op, DAG);
1963 return LowerFSINCOS(Op, DAG);
1965 return LowerMUL(Op, DAG);
1969 /// getFunctionAlignment - Return the Log2 alignment of this function.
1970 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1974 //===----------------------------------------------------------------------===//
1975 // Calling Convention Implementation
1976 //===----------------------------------------------------------------------===//
1978 #include "AArch64GenCallingConv.inc"
1980 /// Selects the correct CCAssignFn for a given CallingConvention value.
1981 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1982 bool IsVarArg) const {
1985 llvm_unreachable("Unsupported calling convention.");
1986 case CallingConv::WebKit_JS:
1987 return CC_AArch64_WebKit_JS;
1988 case CallingConv::GHC:
1989 return CC_AArch64_GHC;
1990 case CallingConv::C:
1991 case CallingConv::Fast:
1992 if (!Subtarget->isTargetDarwin())
1993 return CC_AArch64_AAPCS;
1994 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1998 SDValue AArch64TargetLowering::LowerFormalArguments(
1999 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2000 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2001 SmallVectorImpl<SDValue> &InVals) const {
2002 MachineFunction &MF = DAG.getMachineFunction();
2003 MachineFrameInfo *MFI = MF.getFrameInfo();
2005 // Assign locations to all of the incoming arguments.
2006 SmallVector<CCValAssign, 16> ArgLocs;
2007 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2010 // At this point, Ins[].VT may already be promoted to i32. To correctly
2011 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2012 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2013 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2014 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2016 unsigned NumArgs = Ins.size();
2017 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2018 unsigned CurArgIdx = 0;
2019 for (unsigned i = 0; i != NumArgs; ++i) {
2020 MVT ValVT = Ins[i].VT;
2021 if (Ins[i].isOrigArg()) {
2022 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2023 CurArgIdx = Ins[i].getOrigArgIndex();
2025 // Get type of the original argument.
2026 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2027 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2028 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2029 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2031 else if (ActualMVT == MVT::i16)
2034 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2036 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2037 assert(!Res && "Call operand has unhandled type");
2040 assert(ArgLocs.size() == Ins.size());
2041 SmallVector<SDValue, 16> ArgValues;
2042 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2043 CCValAssign &VA = ArgLocs[i];
2045 if (Ins[i].Flags.isByVal()) {
2046 // Byval is used for HFAs in the PCS, but the system should work in a
2047 // non-compliant manner for larger structs.
2048 EVT PtrTy = getPointerTy();
2049 int Size = Ins[i].Flags.getByValSize();
2050 unsigned NumRegs = (Size + 7) / 8;
2052 // FIXME: This works on big-endian for composite byvals, which are the common
2053 // case. It should also work for fundamental types too.
2055 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2056 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2057 InVals.push_back(FrameIdxN);
2062 if (VA.isRegLoc()) {
2063 // Arguments stored in registers.
2064 EVT RegVT = VA.getLocVT();
2067 const TargetRegisterClass *RC;
2069 if (RegVT == MVT::i32)
2070 RC = &AArch64::GPR32RegClass;
2071 else if (RegVT == MVT::i64)
2072 RC = &AArch64::GPR64RegClass;
2073 else if (RegVT == MVT::f16)
2074 RC = &AArch64::FPR16RegClass;
2075 else if (RegVT == MVT::f32)
2076 RC = &AArch64::FPR32RegClass;
2077 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2078 RC = &AArch64::FPR64RegClass;
2079 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2080 RC = &AArch64::FPR128RegClass;
2082 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2084 // Transform the arguments in physical registers into virtual ones.
2085 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2086 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2088 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2089 // to 64 bits. Insert an assert[sz]ext to capture this, then
2090 // truncate to the right size.
2091 switch (VA.getLocInfo()) {
2093 llvm_unreachable("Unknown loc info!");
2094 case CCValAssign::Full:
2096 case CCValAssign::BCvt:
2097 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2099 case CCValAssign::AExt:
2100 case CCValAssign::SExt:
2101 case CCValAssign::ZExt:
2102 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2103 // nodes after our lowering.
2104 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2108 InVals.push_back(ArgValue);
2110 } else { // VA.isRegLoc()
2111 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2112 unsigned ArgOffset = VA.getLocMemOffset();
2113 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2115 uint32_t BEAlign = 0;
2116 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2117 !Ins[i].Flags.isInConsecutiveRegs())
2118 BEAlign = 8 - ArgSize;
2120 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2122 // Create load nodes to retrieve arguments from the stack.
2123 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2126 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2127 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2128 MVT MemVT = VA.getValVT();
2130 switch (VA.getLocInfo()) {
2133 case CCValAssign::BCvt:
2134 MemVT = VA.getLocVT();
2136 case CCValAssign::SExt:
2137 ExtType = ISD::SEXTLOAD;
2139 case CCValAssign::ZExt:
2140 ExtType = ISD::ZEXTLOAD;
2142 case CCValAssign::AExt:
2143 ExtType = ISD::EXTLOAD;
2147 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2148 MachinePointerInfo::getFixedStack(FI),
2149 MemVT, false, false, false, 0);
2151 InVals.push_back(ArgValue);
2157 if (!Subtarget->isTargetDarwin()) {
2158 // The AAPCS variadic function ABI is identical to the non-variadic
2159 // one. As a result there may be more arguments in registers and we should
2160 // save them for future reference.
2161 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2164 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2165 // This will point to the next argument passed via stack.
2166 unsigned StackOffset = CCInfo.getNextStackOffset();
2167 // We currently pass all varargs at 8-byte alignment.
2168 StackOffset = ((StackOffset + 7) & ~7);
2169 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2172 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2173 unsigned StackArgSize = CCInfo.getNextStackOffset();
2174 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2175 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2176 // This is a non-standard ABI so by fiat I say we're allowed to make full
2177 // use of the stack area to be popped, which must be aligned to 16 bytes in
2179 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2181 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2182 // a multiple of 16.
2183 FuncInfo->setArgumentStackToRestore(StackArgSize);
2185 // This realignment carries over to the available bytes below. Our own
2186 // callers will guarantee the space is free by giving an aligned value to
2189 // Even if we're not expected to free up the space, it's useful to know how
2190 // much is there while considering tail calls (because we can reuse it).
2191 FuncInfo->setBytesInStackArgArea(StackArgSize);
2196 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2197 SelectionDAG &DAG, SDLoc DL,
2198 SDValue &Chain) const {
2199 MachineFunction &MF = DAG.getMachineFunction();
2200 MachineFrameInfo *MFI = MF.getFrameInfo();
2201 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2203 SmallVector<SDValue, 8> MemOps;
2205 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2206 AArch64::X3, AArch64::X4, AArch64::X5,
2207 AArch64::X6, AArch64::X7 };
2208 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2209 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2211 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2213 if (GPRSaveSize != 0) {
2214 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2216 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2218 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2219 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2220 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2222 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2223 MachinePointerInfo::getStack(i * 8), false, false, 0);
2224 MemOps.push_back(Store);
2225 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2226 DAG.getConstant(8, getPointerTy()));
2229 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2230 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2232 if (Subtarget->hasFPARMv8()) {
2233 static const MCPhysReg FPRArgRegs[] = {
2234 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2235 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2236 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2237 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2239 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2241 if (FPRSaveSize != 0) {
2242 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2244 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2246 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2247 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2248 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2251 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2252 MachinePointerInfo::getStack(i * 16), false, false, 0);
2253 MemOps.push_back(Store);
2254 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2255 DAG.getConstant(16, getPointerTy()));
2258 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2259 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2262 if (!MemOps.empty()) {
2263 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2267 /// LowerCallResult - Lower the result values of a call into the
2268 /// appropriate copies out of appropriate physical registers.
2269 SDValue AArch64TargetLowering::LowerCallResult(
2270 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2271 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2272 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2273 SDValue ThisVal) const {
2274 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2275 ? RetCC_AArch64_WebKit_JS
2276 : RetCC_AArch64_AAPCS;
2277 // Assign locations to each value returned by this call.
2278 SmallVector<CCValAssign, 16> RVLocs;
2279 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2281 CCInfo.AnalyzeCallResult(Ins, RetCC);
2283 // Copy all of the result registers out of their specified physreg.
2284 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2285 CCValAssign VA = RVLocs[i];
2287 // Pass 'this' value directly from the argument to return value, to avoid
2288 // reg unit interference
2289 if (i == 0 && isThisReturn) {
2290 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2291 "unexpected return calling convention register assignment");
2292 InVals.push_back(ThisVal);
2297 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2298 Chain = Val.getValue(1);
2299 InFlag = Val.getValue(2);
2301 switch (VA.getLocInfo()) {
2303 llvm_unreachable("Unknown loc info!");
2304 case CCValAssign::Full:
2306 case CCValAssign::BCvt:
2307 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2311 InVals.push_back(Val);
2317 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2318 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2319 bool isCalleeStructRet, bool isCallerStructRet,
2320 const SmallVectorImpl<ISD::OutputArg> &Outs,
2321 const SmallVectorImpl<SDValue> &OutVals,
2322 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2323 // For CallingConv::C this function knows whether the ABI needs
2324 // changing. That's not true for other conventions so they will have to opt in
2326 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2329 const MachineFunction &MF = DAG.getMachineFunction();
2330 const Function *CallerF = MF.getFunction();
2331 CallingConv::ID CallerCC = CallerF->getCallingConv();
2332 bool CCMatch = CallerCC == CalleeCC;
2334 // Byval parameters hand the function a pointer directly into the stack area
2335 // we want to reuse during a tail call. Working around this *is* possible (see
2336 // X86) but less efficient and uglier in LowerCall.
2337 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2338 e = CallerF->arg_end();
2340 if (i->hasByValAttr())
2343 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2344 if (IsTailCallConvention(CalleeCC) && CCMatch)
2349 // Externally-defined functions with weak linkage should not be
2350 // tail-called on AArch64 when the OS does not support dynamic
2351 // pre-emption of symbols, as the AAELF spec requires normal calls
2352 // to undefined weak functions to be replaced with a NOP or jump to the
2353 // next instruction. The behaviour of branch instructions in this
2354 // situation (as used for tail calls) is implementation-defined, so we
2355 // cannot rely on the linker replacing the tail call with a return.
2356 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2357 const GlobalValue *GV = G->getGlobal();
2358 const Triple TT(getTargetMachine().getTargetTriple());
2359 if (GV->hasExternalWeakLinkage() &&
2360 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2364 // Now we search for cases where we can use a tail call without changing the
2365 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2368 // I want anyone implementing a new calling convention to think long and hard
2369 // about this assert.
2370 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2371 "Unexpected variadic calling convention");
2373 if (isVarArg && !Outs.empty()) {
2374 // At least two cases here: if caller is fastcc then we can't have any
2375 // memory arguments (we'd be expected to clean up the stack afterwards). If
2376 // caller is C then we could potentially use its argument area.
2378 // FIXME: for now we take the most conservative of these in both cases:
2379 // disallow all variadic memory operands.
2380 SmallVector<CCValAssign, 16> ArgLocs;
2381 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2384 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2385 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2386 if (!ArgLocs[i].isRegLoc())
2390 // If the calling conventions do not match, then we'd better make sure the
2391 // results are returned in the same way as what the caller expects.
2393 SmallVector<CCValAssign, 16> RVLocs1;
2394 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2396 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2398 SmallVector<CCValAssign, 16> RVLocs2;
2399 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2401 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2403 if (RVLocs1.size() != RVLocs2.size())
2405 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2406 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2408 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2410 if (RVLocs1[i].isRegLoc()) {
2411 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2414 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2420 // Nothing more to check if the callee is taking no arguments
2424 SmallVector<CCValAssign, 16> ArgLocs;
2425 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2428 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2430 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2432 // If the stack arguments for this call would fit into our own save area then
2433 // the call can be made tail.
2434 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2437 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2439 MachineFrameInfo *MFI,
2440 int ClobberedFI) const {
2441 SmallVector<SDValue, 8> ArgChains;
2442 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2443 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2445 // Include the original chain at the beginning of the list. When this is
2446 // used by target LowerCall hooks, this helps legalize find the
2447 // CALLSEQ_BEGIN node.
2448 ArgChains.push_back(Chain);
2450 // Add a chain value for each stack argument corresponding
2451 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2452 UE = DAG.getEntryNode().getNode()->use_end();
2454 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2455 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2456 if (FI->getIndex() < 0) {
2457 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2458 int64_t InLastByte = InFirstByte;
2459 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2461 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2462 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2463 ArgChains.push_back(SDValue(L, 1));
2466 // Build a tokenfactor for all the chains.
2467 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2470 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2471 bool TailCallOpt) const {
2472 return CallCC == CallingConv::Fast && TailCallOpt;
2475 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2476 return CallCC == CallingConv::Fast;
2479 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2480 /// and add input and output parameter nodes.
2482 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2483 SmallVectorImpl<SDValue> &InVals) const {
2484 SelectionDAG &DAG = CLI.DAG;
2486 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2487 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2488 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2489 SDValue Chain = CLI.Chain;
2490 SDValue Callee = CLI.Callee;
2491 bool &IsTailCall = CLI.IsTailCall;
2492 CallingConv::ID CallConv = CLI.CallConv;
2493 bool IsVarArg = CLI.IsVarArg;
2495 MachineFunction &MF = DAG.getMachineFunction();
2496 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2497 bool IsThisReturn = false;
2499 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2500 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2501 bool IsSibCall = false;
2504 // Check if it's really possible to do a tail call.
2505 IsTailCall = isEligibleForTailCallOptimization(
2506 Callee, CallConv, IsVarArg, IsStructRet,
2507 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2508 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2509 report_fatal_error("failed to perform tail call elimination on a call "
2510 "site marked musttail");
2512 // A sibling call is one where we're under the usual C ABI and not planning
2513 // to change that but can still do a tail call:
2514 if (!TailCallOpt && IsTailCall)
2521 // Analyze operands of the call, assigning locations to each operand.
2522 SmallVector<CCValAssign, 16> ArgLocs;
2523 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2527 // Handle fixed and variable vector arguments differently.
2528 // Variable vector arguments always go into memory.
2529 unsigned NumArgs = Outs.size();
2531 for (unsigned i = 0; i != NumArgs; ++i) {
2532 MVT ArgVT = Outs[i].VT;
2533 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2534 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2535 /*IsVarArg=*/ !Outs[i].IsFixed);
2536 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2537 assert(!Res && "Call operand has unhandled type");
2541 // At this point, Outs[].VT may already be promoted to i32. To correctly
2542 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2543 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2544 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2545 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2547 unsigned NumArgs = Outs.size();
2548 for (unsigned i = 0; i != NumArgs; ++i) {
2549 MVT ValVT = Outs[i].VT;
2550 // Get type of the original argument.
2551 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2552 /*AllowUnknown*/ true);
2553 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2554 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2555 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2556 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2558 else if (ActualMVT == MVT::i16)
2561 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2562 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2563 assert(!Res && "Call operand has unhandled type");
2568 // Get a count of how many bytes are to be pushed on the stack.
2569 unsigned NumBytes = CCInfo.getNextStackOffset();
2572 // Since we're not changing the ABI to make this a tail call, the memory
2573 // operands are already available in the caller's incoming argument space.
2577 // FPDiff is the byte offset of the call's argument area from the callee's.
2578 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2579 // by this amount for a tail call. In a sibling call it must be 0 because the
2580 // caller will deallocate the entire stack and the callee still expects its
2581 // arguments to begin at SP+0. Completely unused for non-tail calls.
2584 if (IsTailCall && !IsSibCall) {
2585 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2587 // Since callee will pop argument stack as a tail call, we must keep the
2588 // popped size 16-byte aligned.
2589 NumBytes = RoundUpToAlignment(NumBytes, 16);
2591 // FPDiff will be negative if this tail call requires more space than we
2592 // would automatically have in our incoming argument space. Positive if we
2593 // can actually shrink the stack.
2594 FPDiff = NumReusableBytes - NumBytes;
2596 // The stack pointer must be 16-byte aligned at all times it's used for a
2597 // memory operation, which in practice means at *all* times and in
2598 // particular across call boundaries. Therefore our own arguments started at
2599 // a 16-byte aligned SP and the delta applied for the tail call should
2600 // satisfy the same constraint.
2601 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2604 // Adjust the stack pointer for the new arguments...
2605 // These operations are automatically eliminated by the prolog/epilog pass
2608 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2610 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2612 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2613 SmallVector<SDValue, 8> MemOpChains;
2615 // Walk the register/memloc assignments, inserting copies/loads.
2616 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2617 ++i, ++realArgIdx) {
2618 CCValAssign &VA = ArgLocs[i];
2619 SDValue Arg = OutVals[realArgIdx];
2620 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2622 // Promote the value if needed.
2623 switch (VA.getLocInfo()) {
2625 llvm_unreachable("Unknown loc info!");
2626 case CCValAssign::Full:
2628 case CCValAssign::SExt:
2629 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2631 case CCValAssign::ZExt:
2632 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2634 case CCValAssign::AExt:
2635 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2636 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2637 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2638 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2640 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2642 case CCValAssign::BCvt:
2643 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2645 case CCValAssign::FPExt:
2646 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2650 if (VA.isRegLoc()) {
2651 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2652 assert(VA.getLocVT() == MVT::i64 &&
2653 "unexpected calling convention register assignment");
2654 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2655 "unexpected use of 'returned'");
2656 IsThisReturn = true;
2658 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2660 assert(VA.isMemLoc());
2663 MachinePointerInfo DstInfo;
2665 // FIXME: This works on big-endian for composite byvals, which are the
2666 // common case. It should also work for fundamental types too.
2667 uint32_t BEAlign = 0;
2668 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2669 : VA.getValVT().getSizeInBits();
2670 OpSize = (OpSize + 7) / 8;
2671 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2672 !Flags.isInConsecutiveRegs()) {
2674 BEAlign = 8 - OpSize;
2676 unsigned LocMemOffset = VA.getLocMemOffset();
2677 int32_t Offset = LocMemOffset + BEAlign;
2678 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2679 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2682 Offset = Offset + FPDiff;
2683 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2685 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2686 DstInfo = MachinePointerInfo::getFixedStack(FI);
2688 // Make sure any stack arguments overlapping with where we're storing
2689 // are loaded before this eventual operation. Otherwise they'll be
2691 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2693 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2695 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2696 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2699 if (Outs[i].Flags.isByVal()) {
2701 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2702 SDValue Cpy = DAG.getMemcpy(
2703 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2705 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2707 MemOpChains.push_back(Cpy);
2709 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2710 // promoted to a legal register type i32, we should truncate Arg back to
2712 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2713 VA.getValVT() == MVT::i16)
2714 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2717 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2718 MemOpChains.push_back(Store);
2723 if (!MemOpChains.empty())
2724 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2726 // Build a sequence of copy-to-reg nodes chained together with token chain
2727 // and flag operands which copy the outgoing args into the appropriate regs.
2729 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2730 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2731 RegsToPass[i].second, InFlag);
2732 InFlag = Chain.getValue(1);
2735 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2736 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2737 // node so that legalize doesn't hack it.
2738 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2739 Subtarget->isTargetMachO()) {
2740 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2741 const GlobalValue *GV = G->getGlobal();
2742 bool InternalLinkage = GV->hasInternalLinkage();
2743 if (InternalLinkage)
2744 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2746 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2748 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2750 } else if (ExternalSymbolSDNode *S =
2751 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2752 const char *Sym = S->getSymbol();
2754 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2755 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2757 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2758 const GlobalValue *GV = G->getGlobal();
2759 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2760 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2761 const char *Sym = S->getSymbol();
2762 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2765 // We don't usually want to end the call-sequence here because we would tidy
2766 // the frame up *after* the call, however in the ABI-changing tail-call case
2767 // we've carefully laid out the parameters so that when sp is reset they'll be
2768 // in the correct location.
2769 if (IsTailCall && !IsSibCall) {
2770 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2771 DAG.getIntPtrConstant(0, true), InFlag, DL);
2772 InFlag = Chain.getValue(1);
2775 std::vector<SDValue> Ops;
2776 Ops.push_back(Chain);
2777 Ops.push_back(Callee);
2780 // Each tail call may have to adjust the stack by a different amount, so
2781 // this information must travel along with the operation for eventual
2782 // consumption by emitEpilogue.
2783 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2786 // Add argument registers to the end of the list so that they are known live
2788 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2789 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2790 RegsToPass[i].second.getValueType()));
2792 // Add a register mask operand representing the call-preserved registers.
2793 const uint32_t *Mask;
2794 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2796 // For 'this' returns, use the X0-preserving mask if applicable
2797 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2799 IsThisReturn = false;
2800 Mask = TRI->getCallPreservedMask(MF, CallConv);
2803 Mask = TRI->getCallPreservedMask(MF, CallConv);
2805 assert(Mask && "Missing call preserved mask for calling convention");
2806 Ops.push_back(DAG.getRegisterMask(Mask));
2808 if (InFlag.getNode())
2809 Ops.push_back(InFlag);
2811 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2813 // If we're doing a tall call, use a TC_RETURN here rather than an
2814 // actual call instruction.
2816 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2818 // Returns a chain and a flag for retval copy to use.
2819 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2820 InFlag = Chain.getValue(1);
2822 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2823 ? RoundUpToAlignment(NumBytes, 16)
2826 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2827 DAG.getIntPtrConstant(CalleePopBytes, true),
2830 InFlag = Chain.getValue(1);
2832 // Handle result values, copying them out of physregs into vregs that we
2834 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2835 InVals, IsThisReturn,
2836 IsThisReturn ? OutVals[0] : SDValue());
2839 bool AArch64TargetLowering::CanLowerReturn(
2840 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2841 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2842 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2843 ? RetCC_AArch64_WebKit_JS
2844 : RetCC_AArch64_AAPCS;
2845 SmallVector<CCValAssign, 16> RVLocs;
2846 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2847 return CCInfo.CheckReturn(Outs, RetCC);
2851 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2853 const SmallVectorImpl<ISD::OutputArg> &Outs,
2854 const SmallVectorImpl<SDValue> &OutVals,
2855 SDLoc DL, SelectionDAG &DAG) const {
2856 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2857 ? RetCC_AArch64_WebKit_JS
2858 : RetCC_AArch64_AAPCS;
2859 SmallVector<CCValAssign, 16> RVLocs;
2860 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2862 CCInfo.AnalyzeReturn(Outs, RetCC);
2864 // Copy the result values into the output registers.
2866 SmallVector<SDValue, 4> RetOps(1, Chain);
2867 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2868 ++i, ++realRVLocIdx) {
2869 CCValAssign &VA = RVLocs[i];
2870 assert(VA.isRegLoc() && "Can only return in registers!");
2871 SDValue Arg = OutVals[realRVLocIdx];
2873 switch (VA.getLocInfo()) {
2875 llvm_unreachable("Unknown loc info!");
2876 case CCValAssign::Full:
2877 if (Outs[i].ArgVT == MVT::i1) {
2878 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2879 // value. This is strictly redundant on Darwin (which uses "zeroext
2880 // i1"), but will be optimised out before ISel.
2881 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2882 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2885 case CCValAssign::BCvt:
2886 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2890 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2891 Flag = Chain.getValue(1);
2892 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2895 RetOps[0] = Chain; // Update chain.
2897 // Add the flag if we have it.
2899 RetOps.push_back(Flag);
2901 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2904 //===----------------------------------------------------------------------===//
2905 // Other Lowering Code
2906 //===----------------------------------------------------------------------===//
2908 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2909 SelectionDAG &DAG) const {
2910 EVT PtrVT = getPointerTy();
2912 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2913 const GlobalValue *GV = GN->getGlobal();
2914 unsigned char OpFlags =
2915 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2917 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2918 "unexpected offset in global node");
2920 // This also catched the large code model case for Darwin.
2921 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2922 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2923 // FIXME: Once remat is capable of dealing with instructions with register
2924 // operands, expand this into two nodes instead of using a wrapper node.
2925 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2928 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2929 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2930 "use of MO_CONSTPOOL only supported on small model");
2931 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2932 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2933 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2934 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2935 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2936 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2937 MachinePointerInfo::getConstantPool(),
2938 /*isVolatile=*/ false,
2939 /*isNonTemporal=*/ true,
2940 /*isInvariant=*/ true, 8);
2941 if (GN->getOffset() != 0)
2942 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2943 DAG.getConstant(GN->getOffset(), PtrVT));
2947 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2948 const unsigned char MO_NC = AArch64II::MO_NC;
2950 AArch64ISD::WrapperLarge, DL, PtrVT,
2951 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2952 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2953 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2954 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2956 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2957 // the only correct model on Darwin.
2958 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2959 OpFlags | AArch64II::MO_PAGE);
2960 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2961 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2963 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2964 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2968 /// \brief Convert a TLS address reference into the correct sequence of loads
2969 /// and calls to compute the variable's address (for Darwin, currently) and
2970 /// return an SDValue containing the final node.
2972 /// Darwin only has one TLS scheme which must be capable of dealing with the
2973 /// fully general situation, in the worst case. This means:
2974 /// + "extern __thread" declaration.
2975 /// + Defined in a possibly unknown dynamic library.
2977 /// The general system is that each __thread variable has a [3 x i64] descriptor
2978 /// which contains information used by the runtime to calculate the address. The
2979 /// only part of this the compiler needs to know about is the first xword, which
2980 /// contains a function pointer that must be called with the address of the
2981 /// entire descriptor in "x0".
2983 /// Since this descriptor may be in a different unit, in general even the
2984 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2986 /// adrp x0, _var@TLVPPAGE
2987 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2988 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2989 /// ; the function pointer
2990 /// blr x1 ; Uses descriptor address in x0
2991 /// ; Address of _var is now in x0.
2993 /// If the address of _var's descriptor *is* known to the linker, then it can
2994 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2995 /// a slight efficiency gain.
2997 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2998 SelectionDAG &DAG) const {
2999 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3002 MVT PtrVT = getPointerTy();
3003 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3006 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3007 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3009 // The first entry in the descriptor is a function pointer that we must call
3010 // to obtain the address of the variable.
3011 SDValue Chain = DAG.getEntryNode();
3012 SDValue FuncTLVGet =
3013 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3014 false, true, true, 8);
3015 Chain = FuncTLVGet.getValue(1);
3017 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3018 MFI->setAdjustsStack(true);
3020 // TLS calls preserve all registers except those that absolutely must be
3021 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3023 const uint32_t *Mask =
3024 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3026 // Finally, we can make the call. This is just a degenerate version of a
3027 // normal AArch64 call node: x0 takes the address of the descriptor, and
3028 // returns the address of the variable in this thread.
3029 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3031 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3032 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3033 DAG.getRegisterMask(Mask), Chain.getValue(1));
3034 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3037 /// When accessing thread-local variables under either the general-dynamic or
3038 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3039 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3040 /// is a function pointer to carry out the resolution.
3042 /// The sequence is:
3043 /// adrp x0, :tlsdesc:var
3044 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3045 /// add x0, x0, #:tlsdesc_lo12:var
3046 /// .tlsdesccall var
3048 /// (TPIDR_EL0 offset now in x0)
3050 /// The above sequence must be produced unscheduled, to enable the linker to
3051 /// optimize/relax this sequence.
3052 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3053 /// above sequence, and expanded really late in the compilation flow, to ensure
3054 /// the sequence is produced as per above.
3055 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3056 SelectionDAG &DAG) const {
3057 EVT PtrVT = getPointerTy();
3059 SDValue Chain = DAG.getEntryNode();
3060 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3062 SmallVector<SDValue, 2> Ops;
3063 Ops.push_back(Chain);
3064 Ops.push_back(SymAddr);
3066 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3067 SDValue Glue = Chain.getValue(1);
3069 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3073 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3074 SelectionDAG &DAG) const {
3075 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3076 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3077 "ELF TLS only supported in small memory model");
3078 // Different choices can be made for the maximum size of the TLS area for a
3079 // module. For the small address model, the default TLS size is 16MiB and the
3080 // maximum TLS size is 4GiB.
3081 // FIXME: add -mtls-size command line option and make it control the 16MiB
3082 // vs. 4GiB code sequence generation.
3083 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3085 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3086 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3087 if (Model == TLSModel::LocalDynamic)
3088 Model = TLSModel::GeneralDynamic;
3092 EVT PtrVT = getPointerTy();
3094 const GlobalValue *GV = GA->getGlobal();
3096 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3098 if (Model == TLSModel::LocalExec) {
3099 SDValue HiVar = DAG.getTargetGlobalAddress(
3100 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3101 SDValue LoVar = DAG.getTargetGlobalAddress(
3103 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3105 SDValue TPWithOff_lo =
3106 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3107 HiVar, DAG.getTargetConstant(0, MVT::i32)),
3110 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3111 LoVar, DAG.getTargetConstant(0, MVT::i32)),
3114 } else if (Model == TLSModel::InitialExec) {
3115 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3116 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3117 } else if (Model == TLSModel::LocalDynamic) {
3118 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3119 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3120 // the beginning of the module's TLS region, followed by a DTPREL offset
3123 // These accesses will need deduplicating if there's more than one.
3124 AArch64FunctionInfo *MFI =
3125 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3126 MFI->incNumLocalDynamicTLSAccesses();
3128 // The call needs a relocation too for linker relaxation. It doesn't make
3129 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3131 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3134 // Now we can calculate the offset from TPIDR_EL0 to this module's
3135 // thread-local area.
3136 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3138 // Now use :dtprel_whatever: operations to calculate this variable's offset
3139 // in its thread-storage area.
3140 SDValue HiVar = DAG.getTargetGlobalAddress(
3141 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3142 SDValue LoVar = DAG.getTargetGlobalAddress(
3143 GV, DL, MVT::i64, 0,
3144 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3146 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3147 DAG.getTargetConstant(0, MVT::i32)),
3149 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3150 DAG.getTargetConstant(0, MVT::i32)),
3152 } else if (Model == TLSModel::GeneralDynamic) {
3153 // The call needs a relocation too for linker relaxation. It doesn't make
3154 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3157 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3159 // Finally we can make a call to calculate the offset from tpidr_el0.
3160 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3162 llvm_unreachable("Unsupported ELF TLS access model");
3164 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3167 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3168 SelectionDAG &DAG) const {
3169 if (Subtarget->isTargetDarwin())
3170 return LowerDarwinGlobalTLSAddress(Op, DAG);
3171 else if (Subtarget->isTargetELF())
3172 return LowerELFGlobalTLSAddress(Op, DAG);
3174 llvm_unreachable("Unexpected platform trying to use TLS");
3176 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3177 SDValue Chain = Op.getOperand(0);
3178 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3179 SDValue LHS = Op.getOperand(2);
3180 SDValue RHS = Op.getOperand(3);
3181 SDValue Dest = Op.getOperand(4);
3184 // Handle f128 first, since lowering it will result in comparing the return
3185 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3186 // is expecting to deal with.
3187 if (LHS.getValueType() == MVT::f128) {
3188 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3190 // If softenSetCCOperands returned a scalar, we need to compare the result
3191 // against zero to select between true and false values.
3192 if (!RHS.getNode()) {
3193 RHS = DAG.getConstant(0, LHS.getValueType());
3198 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3200 unsigned Opc = LHS.getOpcode();
3201 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3202 cast<ConstantSDNode>(RHS)->isOne() &&
3203 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3204 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3205 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3206 "Unexpected condition code.");
3207 // Only lower legal XALUO ops.
3208 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3211 // The actual operation with overflow check.
3212 AArch64CC::CondCode OFCC;
3213 SDValue Value, Overflow;
3214 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3216 if (CC == ISD::SETNE)
3217 OFCC = getInvertedCondCode(OFCC);
3218 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3220 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3224 if (LHS.getValueType().isInteger()) {
3225 assert((LHS.getValueType() == RHS.getValueType()) &&
3226 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3228 // If the RHS of the comparison is zero, we can potentially fold this
3229 // to a specialized branch.
3230 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3231 if (RHSC && RHSC->getZExtValue() == 0) {
3232 if (CC == ISD::SETEQ) {
3233 // See if we can use a TBZ to fold in an AND as well.
3234 // TBZ has a smaller branch displacement than CBZ. If the offset is
3235 // out of bounds, a late MI-layer pass rewrites branches.
3236 // 403.gcc is an example that hits this case.
3237 if (LHS.getOpcode() == ISD::AND &&
3238 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3239 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3240 SDValue Test = LHS.getOperand(0);
3241 uint64_t Mask = LHS.getConstantOperandVal(1);
3242 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3243 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3246 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3247 } else if (CC == ISD::SETNE) {
3248 // See if we can use a TBZ to fold in an AND as well.
3249 // TBZ has a smaller branch displacement than CBZ. If the offset is
3250 // out of bounds, a late MI-layer pass rewrites branches.
3251 // 403.gcc is an example that hits this case.
3252 if (LHS.getOpcode() == ISD::AND &&
3253 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3254 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3255 SDValue Test = LHS.getOperand(0);
3256 uint64_t Mask = LHS.getConstantOperandVal(1);
3257 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3258 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3261 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3262 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3263 // Don't combine AND since emitComparison converts the AND to an ANDS
3264 // (a.k.a. TST) and the test in the test bit and branch instruction
3265 // becomes redundant. This would also increase register pressure.
3266 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3267 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3268 DAG.getConstant(Mask, MVT::i64), Dest);
3271 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3272 LHS.getOpcode() != ISD::AND) {
3273 // Don't combine AND since emitComparison converts the AND to an ANDS
3274 // (a.k.a. TST) and the test in the test bit and branch instruction
3275 // becomes redundant. This would also increase register pressure.
3276 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3277 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3278 DAG.getConstant(Mask, MVT::i64), Dest);
3282 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3283 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3287 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3289 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3290 // clean. Some of them require two branches to implement.
3291 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3292 AArch64CC::CondCode CC1, CC2;
3293 changeFPCCToAArch64CC(CC, CC1, CC2);
3294 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3296 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3297 if (CC2 != AArch64CC::AL) {
3298 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3299 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3306 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3307 SelectionDAG &DAG) const {
3308 EVT VT = Op.getValueType();
3311 SDValue In1 = Op.getOperand(0);
3312 SDValue In2 = Op.getOperand(1);
3313 EVT SrcVT = In2.getValueType();
3315 if (SrcVT == MVT::f32 && VT == MVT::f64)
3316 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3317 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3318 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3320 // FIXME: Src type is different, bail out for now. Can VT really be a
3328 SDValue VecVal1, VecVal2;
3329 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3332 EltMask = 0x80000000ULL;
3334 if (!VT.isVector()) {
3335 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3336 DAG.getUNDEF(VecVT), In1);
3337 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3338 DAG.getUNDEF(VecVT), In2);
3340 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3341 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3343 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3347 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3348 // immediate moves cannot materialize that in a single instruction for
3349 // 64-bit elements. Instead, materialize zero and then negate it.
3352 if (!VT.isVector()) {
3353 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3354 DAG.getUNDEF(VecVT), In1);
3355 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3356 DAG.getUNDEF(VecVT), In2);
3358 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3359 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3362 llvm_unreachable("Invalid type for copysign!");
3365 SDValue BuildVec = DAG.getConstant(EltMask, VecVT);
3367 // If we couldn't materialize the mask above, then the mask vector will be
3368 // the zero vector, and we need to negate it here.
3369 if (VT == MVT::f64 || VT == MVT::v2f64) {
3370 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3371 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3372 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3376 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3379 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3380 else if (VT == MVT::f64)
3381 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3383 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3386 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3387 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3388 Attribute::NoImplicitFloat))
3391 if (!Subtarget->hasNEON())
3394 // While there is no integer popcount instruction, it can
3395 // be more efficiently lowered to the following sequence that uses
3396 // AdvSIMD registers/instructions as long as the copies to/from
3397 // the AdvSIMD registers are cheap.
3398 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3399 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3400 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3401 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3402 SDValue Val = Op.getOperand(0);
3404 EVT VT = Op.getValueType();
3407 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3408 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3410 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3411 SDValue UaddLV = DAG.getNode(
3412 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3413 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3416 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3420 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3422 if (Op.getValueType().isVector())
3423 return LowerVSETCC(Op, DAG);
3425 SDValue LHS = Op.getOperand(0);
3426 SDValue RHS = Op.getOperand(1);
3427 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3430 // We chose ZeroOrOneBooleanContents, so use zero and one.
3431 EVT VT = Op.getValueType();
3432 SDValue TVal = DAG.getConstant(1, VT);
3433 SDValue FVal = DAG.getConstant(0, VT);
3435 // Handle f128 first, since one possible outcome is a normal integer
3436 // comparison which gets picked up by the next if statement.
3437 if (LHS.getValueType() == MVT::f128) {
3438 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3440 // If softenSetCCOperands returned a scalar, use it.
3441 if (!RHS.getNode()) {
3442 assert(LHS.getValueType() == Op.getValueType() &&
3443 "Unexpected setcc expansion!");
3448 if (LHS.getValueType().isInteger()) {
3451 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3453 // Note that we inverted the condition above, so we reverse the order of
3454 // the true and false operands here. This will allow the setcc to be
3455 // matched to a single CSINC instruction.
3456 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3459 // Now we know we're dealing with FP values.
3460 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3462 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3463 // and do the comparison.
3464 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3466 AArch64CC::CondCode CC1, CC2;
3467 changeFPCCToAArch64CC(CC, CC1, CC2);
3468 if (CC2 == AArch64CC::AL) {
3469 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3470 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3472 // Note that we inverted the condition above, so we reverse the order of
3473 // the true and false operands here. This will allow the setcc to be
3474 // matched to a single CSINC instruction.
3475 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3477 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3478 // totally clean. Some of them require two CSELs to implement. As is in
3479 // this case, we emit the first CSEL and then emit a second using the output
3480 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3482 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3483 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3485 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3487 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3488 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3492 /// A SELECT_CC operation is really some kind of max or min if both values being
3493 /// compared are, in some sense, equal to the results in either case. However,
3494 /// it is permissible to compare f32 values and produce directly extended f64
3497 /// Extending the comparison operands would also be allowed, but is less likely
3498 /// to happen in practice since their use is right here. Note that truncate
3499 /// operations would *not* be semantically equivalent.
3500 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3504 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3505 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3506 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3507 Result.getValueType() == MVT::f64) {
3509 APFloat CmpVal = CCmp->getValueAPF();
3510 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3511 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3514 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3517 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3518 SelectionDAG &DAG) const {
3519 SDValue CC = Op->getOperand(0);
3520 SDValue TVal = Op->getOperand(1);
3521 SDValue FVal = Op->getOperand(2);
3524 unsigned Opc = CC.getOpcode();
3525 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3527 if (CC.getResNo() == 1 &&
3528 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3529 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3530 // Only lower legal XALUO ops.
3531 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3534 AArch64CC::CondCode OFCC;
3535 SDValue Value, Overflow;
3536 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3537 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3539 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3543 if (CC.getOpcode() == ISD::SETCC)
3544 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3545 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3547 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3551 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3552 SelectionDAG &DAG) const {
3553 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3554 SDValue LHS = Op.getOperand(0);
3555 SDValue RHS = Op.getOperand(1);
3556 SDValue TVal = Op.getOperand(2);
3557 SDValue FVal = Op.getOperand(3);
3560 // Handle f128 first, because it will result in a comparison of some RTLIB
3561 // call result against zero.
3562 if (LHS.getValueType() == MVT::f128) {
3563 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3565 // If softenSetCCOperands returned a scalar, we need to compare the result
3566 // against zero to select between true and false values.
3567 if (!RHS.getNode()) {
3568 RHS = DAG.getConstant(0, LHS.getValueType());
3573 // Handle integers first.
3574 if (LHS.getValueType().isInteger()) {
3575 assert((LHS.getValueType() == RHS.getValueType()) &&
3576 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3578 unsigned Opcode = AArch64ISD::CSEL;
3580 // If both the TVal and the FVal are constants, see if we can swap them in
3581 // order to for a CSINV or CSINC out of them.
3582 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3583 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3585 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3586 std::swap(TVal, FVal);
3587 std::swap(CTVal, CFVal);
3588 CC = ISD::getSetCCInverse(CC, true);
3589 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3590 std::swap(TVal, FVal);
3591 std::swap(CTVal, CFVal);
3592 CC = ISD::getSetCCInverse(CC, true);
3593 } else if (TVal.getOpcode() == ISD::XOR) {
3594 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3595 // with a CSINV rather than a CSEL.
3596 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3598 if (CVal && CVal->isAllOnesValue()) {
3599 std::swap(TVal, FVal);
3600 std::swap(CTVal, CFVal);
3601 CC = ISD::getSetCCInverse(CC, true);
3603 } else if (TVal.getOpcode() == ISD::SUB) {
3604 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3605 // that we can match with a CSNEG rather than a CSEL.
3606 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3608 if (CVal && CVal->isNullValue()) {
3609 std::swap(TVal, FVal);
3610 std::swap(CTVal, CFVal);
3611 CC = ISD::getSetCCInverse(CC, true);
3613 } else if (CTVal && CFVal) {
3614 const int64_t TrueVal = CTVal->getSExtValue();
3615 const int64_t FalseVal = CFVal->getSExtValue();
3618 // If both TVal and FVal are constants, see if FVal is the
3619 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3620 // instead of a CSEL in that case.
3621 if (TrueVal == ~FalseVal) {
3622 Opcode = AArch64ISD::CSINV;
3623 } else if (TrueVal == -FalseVal) {
3624 Opcode = AArch64ISD::CSNEG;
3625 } else if (TVal.getValueType() == MVT::i32) {
3626 // If our operands are only 32-bit wide, make sure we use 32-bit
3627 // arithmetic for the check whether we can use CSINC. This ensures that
3628 // the addition in the check will wrap around properly in case there is
3629 // an overflow (which would not be the case if we do the check with
3630 // 64-bit arithmetic).
3631 const uint32_t TrueVal32 = CTVal->getZExtValue();
3632 const uint32_t FalseVal32 = CFVal->getZExtValue();
3634 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3635 Opcode = AArch64ISD::CSINC;
3637 if (TrueVal32 > FalseVal32) {
3641 // 64-bit check whether we can use CSINC.
3642 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3643 Opcode = AArch64ISD::CSINC;
3645 if (TrueVal > FalseVal) {
3650 // Swap TVal and FVal if necessary.
3652 std::swap(TVal, FVal);
3653 std::swap(CTVal, CFVal);
3654 CC = ISD::getSetCCInverse(CC, true);
3657 if (Opcode != AArch64ISD::CSEL) {
3658 // Drop FVal since we can get its value by simply inverting/negating
3665 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3667 EVT VT = Op.getValueType();
3668 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3671 // Now we know we're dealing with FP values.
3672 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3673 assert(LHS.getValueType() == RHS.getValueType());
3674 EVT VT = Op.getValueType();
3676 // Try to match this select into a max/min operation, which have dedicated
3677 // opcode in the instruction set.
3678 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3680 if (getTargetMachine().Options.NoNaNsFPMath) {
3681 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3682 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3683 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3684 CC = ISD::getSetCCSwappedOperands(CC);
3685 std::swap(MinMaxLHS, MinMaxRHS);
3688 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3689 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3699 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3707 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3713 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3714 // and do the comparison.
3715 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3717 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3718 // clean. Some of them require two CSELs to implement.
3719 AArch64CC::CondCode CC1, CC2;
3720 changeFPCCToAArch64CC(CC, CC1, CC2);
3721 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3722 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3724 // If we need a second CSEL, emit it, using the output of the first as the
3725 // RHS. We're effectively OR'ing the two CC's together.
3726 if (CC2 != AArch64CC::AL) {
3727 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3728 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3731 // Otherwise, return the output of the first CSEL.
3735 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3736 SelectionDAG &DAG) const {
3737 // Jump table entries as PC relative offsets. No additional tweaking
3738 // is necessary here. Just get the address of the jump table.
3739 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3740 EVT PtrVT = getPointerTy();
3743 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3744 !Subtarget->isTargetMachO()) {
3745 const unsigned char MO_NC = AArch64II::MO_NC;
3747 AArch64ISD::WrapperLarge, DL, PtrVT,
3748 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3749 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3750 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3751 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3752 AArch64II::MO_G0 | MO_NC));
3756 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3757 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3758 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3759 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3760 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3763 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3764 SelectionDAG &DAG) const {
3765 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3766 EVT PtrVT = getPointerTy();
3769 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3770 // Use the GOT for the large code model on iOS.
3771 if (Subtarget->isTargetMachO()) {
3772 SDValue GotAddr = DAG.getTargetConstantPool(
3773 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3775 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3778 const unsigned char MO_NC = AArch64II::MO_NC;
3780 AArch64ISD::WrapperLarge, DL, PtrVT,
3781 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3782 CP->getOffset(), AArch64II::MO_G3),
3783 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3784 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3785 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3786 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3787 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3788 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3790 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3791 // ELF, the only valid one on Darwin.
3793 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3794 CP->getOffset(), AArch64II::MO_PAGE);
3795 SDValue Lo = DAG.getTargetConstantPool(
3796 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3797 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3799 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3800 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3804 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3805 SelectionDAG &DAG) const {
3806 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3807 EVT PtrVT = getPointerTy();
3809 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3810 !Subtarget->isTargetMachO()) {
3811 const unsigned char MO_NC = AArch64II::MO_NC;
3813 AArch64ISD::WrapperLarge, DL, PtrVT,
3814 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3815 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3816 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3817 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3819 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3820 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3822 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3823 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3827 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3828 SelectionDAG &DAG) const {
3829 AArch64FunctionInfo *FuncInfo =
3830 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3834 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3835 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3836 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3837 MachinePointerInfo(SV), false, false, 0);
3840 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3841 SelectionDAG &DAG) const {
3842 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3843 // Standard, section B.3.
3844 MachineFunction &MF = DAG.getMachineFunction();
3845 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3848 SDValue Chain = Op.getOperand(0);
3849 SDValue VAList = Op.getOperand(1);
3850 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3851 SmallVector<SDValue, 4> MemOps;
3853 // void *__stack at offset 0
3855 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3856 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3857 MachinePointerInfo(SV), false, false, 8));
3859 // void *__gr_top at offset 8
3860 int GPRSize = FuncInfo->getVarArgsGPRSize();
3862 SDValue GRTop, GRTopAddr;
3864 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3865 DAG.getConstant(8, getPointerTy()));
3867 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3868 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3869 DAG.getConstant(GPRSize, getPointerTy()));
3871 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3872 MachinePointerInfo(SV, 8), false, false, 8));
3875 // void *__vr_top at offset 16
3876 int FPRSize = FuncInfo->getVarArgsFPRSize();
3878 SDValue VRTop, VRTopAddr;
3879 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3880 DAG.getConstant(16, getPointerTy()));
3882 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3883 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3884 DAG.getConstant(FPRSize, getPointerTy()));
3886 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3887 MachinePointerInfo(SV, 16), false, false, 8));
3890 // int __gr_offs at offset 24
3891 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3892 DAG.getConstant(24, getPointerTy()));
3893 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3894 GROffsAddr, MachinePointerInfo(SV, 24), false,
3897 // int __vr_offs at offset 28
3898 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3899 DAG.getConstant(28, getPointerTy()));
3900 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3901 VROffsAddr, MachinePointerInfo(SV, 28), false,
3904 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3907 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3908 SelectionDAG &DAG) const {
3909 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3910 : LowerAAPCS_VASTART(Op, DAG);
3913 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3914 SelectionDAG &DAG) const {
3915 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3917 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3918 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3919 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3921 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3922 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3923 8, false, false, MachinePointerInfo(DestSV),
3924 MachinePointerInfo(SrcSV));
3927 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3928 assert(Subtarget->isTargetDarwin() &&
3929 "automatic va_arg instruction only works on Darwin");
3931 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3932 EVT VT = Op.getValueType();
3934 SDValue Chain = Op.getOperand(0);
3935 SDValue Addr = Op.getOperand(1);
3936 unsigned Align = Op.getConstantOperandVal(3);
3938 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3939 MachinePointerInfo(V), false, false, false, 0);
3940 Chain = VAList.getValue(1);
3943 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3944 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3945 DAG.getConstant(Align - 1, getPointerTy()));
3946 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3947 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3950 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3951 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3953 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3954 // up to 64 bits. At the very least, we have to increase the striding of the
3955 // vaargs list to match this, and for FP values we need to introduce
3956 // FP_ROUND nodes as well.
3957 if (VT.isInteger() && !VT.isVector())
3959 bool NeedFPTrunc = false;
3960 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3965 // Increment the pointer, VAList, to the next vaarg
3966 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3967 DAG.getConstant(ArgSize, getPointerTy()));
3968 // Store the incremented VAList to the legalized pointer
3969 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3972 // Load the actual argument out of the pointer VAList
3974 // Load the value as an f64.
3975 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3976 MachinePointerInfo(), false, false, false, 0);
3977 // Round the value down to an f32.
3978 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3979 DAG.getIntPtrConstant(1));
3980 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3981 // Merge the rounded value with the chain output of the load.
3982 return DAG.getMergeValues(Ops, DL);
3985 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3989 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3990 SelectionDAG &DAG) const {
3991 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3992 MFI->setFrameAddressIsTaken(true);
3994 EVT VT = Op.getValueType();
3996 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3998 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4000 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4001 MachinePointerInfo(), false, false, false, 0);
4005 // FIXME? Maybe this could be a TableGen attribute on some registers and
4006 // this table could be generated automatically from RegInfo.
4007 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4009 unsigned Reg = StringSwitch<unsigned>(RegName)
4010 .Case("sp", AArch64::SP)
4014 report_fatal_error("Invalid register name global variable");
4017 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4018 SelectionDAG &DAG) const {
4019 MachineFunction &MF = DAG.getMachineFunction();
4020 MachineFrameInfo *MFI = MF.getFrameInfo();
4021 MFI->setReturnAddressIsTaken(true);
4023 EVT VT = Op.getValueType();
4025 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4027 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4028 SDValue Offset = DAG.getConstant(8, getPointerTy());
4029 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4030 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4031 MachinePointerInfo(), false, false, false, 0);
4034 // Return LR, which contains the return address. Mark it an implicit live-in.
4035 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4036 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4039 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4040 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4041 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4042 SelectionDAG &DAG) const {
4043 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4044 EVT VT = Op.getValueType();
4045 unsigned VTBits = VT.getSizeInBits();
4047 SDValue ShOpLo = Op.getOperand(0);
4048 SDValue ShOpHi = Op.getOperand(1);
4049 SDValue ShAmt = Op.getOperand(2);
4051 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4053 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4055 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4056 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4057 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4058 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4059 DAG.getConstant(VTBits, MVT::i64));
4060 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4062 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4063 ISD::SETGE, dl, DAG);
4064 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4066 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4067 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4069 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4071 // AArch64 shifts larger than the register width are wrapped rather than
4072 // clamped, so we can't just emit "hi >> x".
4073 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4074 SDValue TrueValHi = Opc == ISD::SRA
4075 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4076 DAG.getConstant(VTBits - 1, MVT::i64))
4077 : DAG.getConstant(0, VT);
4079 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4081 SDValue Ops[2] = { Lo, Hi };
4082 return DAG.getMergeValues(Ops, dl);
4085 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4086 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4087 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4088 SelectionDAG &DAG) const {
4089 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4090 EVT VT = Op.getValueType();
4091 unsigned VTBits = VT.getSizeInBits();
4093 SDValue ShOpLo = Op.getOperand(0);
4094 SDValue ShOpHi = Op.getOperand(1);
4095 SDValue ShAmt = Op.getOperand(2);
4098 assert(Op.getOpcode() == ISD::SHL_PARTS);
4099 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4100 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4101 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4102 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4103 DAG.getConstant(VTBits, MVT::i64));
4104 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4105 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4107 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4109 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4110 ISD::SETGE, dl, DAG);
4111 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4113 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4115 // AArch64 shifts of larger than register sizes are wrapped rather than
4116 // clamped, so we can't just emit "lo << a" if a is too big.
4117 SDValue TrueValLo = DAG.getConstant(0, VT);
4118 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4120 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4122 SDValue Ops[2] = { Lo, Hi };
4123 return DAG.getMergeValues(Ops, dl);
4126 bool AArch64TargetLowering::isOffsetFoldingLegal(
4127 const GlobalAddressSDNode *GA) const {
4128 // The AArch64 target doesn't support folding offsets into global addresses.
4132 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4133 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4134 // FIXME: We should be able to handle f128 as well with a clever lowering.
4135 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4139 return AArch64_AM::getFP64Imm(Imm) != -1;
4140 else if (VT == MVT::f32)
4141 return AArch64_AM::getFP32Imm(Imm) != -1;
4145 //===----------------------------------------------------------------------===//
4146 // AArch64 Optimization Hooks
4147 //===----------------------------------------------------------------------===//
4149 //===----------------------------------------------------------------------===//
4150 // AArch64 Inline Assembly Support
4151 //===----------------------------------------------------------------------===//
4153 // Table of Constraints
4154 // TODO: This is the current set of constraints supported by ARM for the
4155 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4157 // r - A general register
4158 // w - An FP/SIMD register of some size in the range v0-v31
4159 // x - An FP/SIMD register of some size in the range v0-v15
4160 // I - Constant that can be used with an ADD instruction
4161 // J - Constant that can be used with a SUB instruction
4162 // K - Constant that can be used with a 32-bit logical instruction
4163 // L - Constant that can be used with a 64-bit logical instruction
4164 // M - Constant that can be used as a 32-bit MOV immediate
4165 // N - Constant that can be used as a 64-bit MOV immediate
4166 // Q - A memory reference with base register and no offset
4167 // S - A symbolic address
4168 // Y - Floating point constant zero
4169 // Z - Integer constant zero
4171 // Note that general register operands will be output using their 64-bit x
4172 // register name, whatever the size of the variable, unless the asm operand
4173 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4174 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4177 /// getConstraintType - Given a constraint letter, return the type of
4178 /// constraint it is for this target.
4179 AArch64TargetLowering::ConstraintType
4180 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4181 if (Constraint.size() == 1) {
4182 switch (Constraint[0]) {
4189 return C_RegisterClass;
4190 // An address with a single base register. Due to the way we
4191 // currently handle addresses it is the same as 'r'.
4196 return TargetLowering::getConstraintType(Constraint);
4199 /// Examine constraint type and operand type and determine a weight value.
4200 /// This object must already have been set up with the operand type
4201 /// and the current alternative constraint selected.
4202 TargetLowering::ConstraintWeight
4203 AArch64TargetLowering::getSingleConstraintMatchWeight(
4204 AsmOperandInfo &info, const char *constraint) const {
4205 ConstraintWeight weight = CW_Invalid;
4206 Value *CallOperandVal = info.CallOperandVal;
4207 // If we don't have a value, we can't do a match,
4208 // but allow it at the lowest weight.
4209 if (!CallOperandVal)
4211 Type *type = CallOperandVal->getType();
4212 // Look at the constraint type.
4213 switch (*constraint) {
4215 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4219 if (type->isFloatingPointTy() || type->isVectorTy())
4220 weight = CW_Register;
4223 weight = CW_Constant;
4229 std::pair<unsigned, const TargetRegisterClass *>
4230 AArch64TargetLowering::getRegForInlineAsmConstraint(
4231 const TargetRegisterInfo *TRI, const std::string &Constraint,
4233 if (Constraint.size() == 1) {
4234 switch (Constraint[0]) {
4236 if (VT.getSizeInBits() == 64)
4237 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4238 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4241 return std::make_pair(0U, &AArch64::FPR32RegClass);
4242 if (VT.getSizeInBits() == 64)
4243 return std::make_pair(0U, &AArch64::FPR64RegClass);
4244 if (VT.getSizeInBits() == 128)
4245 return std::make_pair(0U, &AArch64::FPR128RegClass);
4247 // The instructions that this constraint is designed for can
4248 // only take 128-bit registers so just use that regclass.
4250 if (VT.getSizeInBits() == 128)
4251 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4255 if (StringRef("{cc}").equals_lower(Constraint))
4256 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4258 // Use the default implementation in TargetLowering to convert the register
4259 // constraint into a member of a register class.
4260 std::pair<unsigned, const TargetRegisterClass *> Res;
4261 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4263 // Not found as a standard register?
4265 unsigned Size = Constraint.size();
4266 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4267 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4268 const std::string Reg =
4269 std::string(&Constraint[2], &Constraint[Size - 1]);
4270 int RegNo = atoi(Reg.c_str());
4271 if (RegNo >= 0 && RegNo <= 31) {
4272 // v0 - v31 are aliases of q0 - q31.
4273 // By default we'll emit v0-v31 for this unless there's a modifier where
4274 // we'll emit the correct register as well.
4275 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4276 Res.second = &AArch64::FPR128RegClass;
4284 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4285 /// vector. If it is invalid, don't add anything to Ops.
4286 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4287 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4288 SelectionDAG &DAG) const {
4291 // Currently only support length 1 constraints.
4292 if (Constraint.length() != 1)
4295 char ConstraintLetter = Constraint[0];
4296 switch (ConstraintLetter) {
4300 // This set of constraints deal with valid constants for various instructions.
4301 // Validate and return a target constant for them if we can.
4303 // 'z' maps to xzr or wzr so it needs an input of 0.
4304 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4305 if (!C || C->getZExtValue() != 0)
4308 if (Op.getValueType() == MVT::i64)
4309 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4311 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4321 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4325 // Grab the value and do some validation.
4326 uint64_t CVal = C->getZExtValue();
4327 switch (ConstraintLetter) {
4328 // The I constraint applies only to simple ADD or SUB immediate operands:
4329 // i.e. 0 to 4095 with optional shift by 12
4330 // The J constraint applies only to ADD or SUB immediates that would be
4331 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4332 // instruction [or vice versa], in other words -1 to -4095 with optional
4333 // left shift by 12.
4335 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4339 uint64_t NVal = -C->getSExtValue();
4340 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4341 CVal = C->getSExtValue();
4346 // The K and L constraints apply *only* to logical immediates, including
4347 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4348 // been removed and MOV should be used). So these constraints have to
4349 // distinguish between bit patterns that are valid 32-bit or 64-bit
4350 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4351 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4354 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4358 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4361 // The M and N constraints are a superset of K and L respectively, for use
4362 // with the MOV (immediate) alias. As well as the logical immediates they
4363 // also match 32 or 64-bit immediates that can be loaded either using a
4364 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4365 // (M) or 64-bit 0x1234000000000000 (N) etc.
4366 // As a note some of this code is liberally stolen from the asm parser.
4368 if (!isUInt<32>(CVal))
4370 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4372 if ((CVal & 0xFFFF) == CVal)
4374 if ((CVal & 0xFFFF0000ULL) == CVal)
4376 uint64_t NCVal = ~(uint32_t)CVal;
4377 if ((NCVal & 0xFFFFULL) == NCVal)
4379 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4384 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4386 if ((CVal & 0xFFFFULL) == CVal)
4388 if ((CVal & 0xFFFF0000ULL) == CVal)
4390 if ((CVal & 0xFFFF00000000ULL) == CVal)
4392 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4394 uint64_t NCVal = ~CVal;
4395 if ((NCVal & 0xFFFFULL) == NCVal)
4397 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4399 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4401 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4409 // All assembler immediates are 64-bit integers.
4410 Result = DAG.getTargetConstant(CVal, MVT::i64);
4414 if (Result.getNode()) {
4415 Ops.push_back(Result);
4419 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4422 //===----------------------------------------------------------------------===//
4423 // AArch64 Advanced SIMD Support
4424 //===----------------------------------------------------------------------===//
4426 /// WidenVector - Given a value in the V64 register class, produce the
4427 /// equivalent value in the V128 register class.
4428 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4429 EVT VT = V64Reg.getValueType();
4430 unsigned NarrowSize = VT.getVectorNumElements();
4431 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4432 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4435 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4436 V64Reg, DAG.getConstant(0, MVT::i32));
4439 /// getExtFactor - Determine the adjustment factor for the position when
4440 /// generating an "extract from vector registers" instruction.
4441 static unsigned getExtFactor(SDValue &V) {
4442 EVT EltType = V.getValueType().getVectorElementType();
4443 return EltType.getSizeInBits() / 8;
4446 /// NarrowVector - Given a value in the V128 register class, produce the
4447 /// equivalent value in the V64 register class.
4448 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4449 EVT VT = V128Reg.getValueType();
4450 unsigned WideSize = VT.getVectorNumElements();
4451 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4452 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4455 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4458 // Gather data to see if the operation can be modelled as a
4459 // shuffle in combination with VEXTs.
4460 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4461 SelectionDAG &DAG) const {
4462 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4464 EVT VT = Op.getValueType();
4465 unsigned NumElts = VT.getVectorNumElements();
4467 struct ShuffleSourceInfo {
4472 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4473 // be compatible with the shuffle we intend to construct. As a result
4474 // ShuffleVec will be some sliding window into the original Vec.
4477 // Code should guarantee that element i in Vec starts at element "WindowBase
4478 // + i * WindowScale in ShuffleVec".
4482 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4483 ShuffleSourceInfo(SDValue Vec)
4484 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4488 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4490 SmallVector<ShuffleSourceInfo, 2> Sources;
4491 for (unsigned i = 0; i < NumElts; ++i) {
4492 SDValue V = Op.getOperand(i);
4493 if (V.getOpcode() == ISD::UNDEF)
4495 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4496 // A shuffle can only come from building a vector from various
4497 // elements of other vectors.
4501 // Add this element source to the list if it's not already there.
4502 SDValue SourceVec = V.getOperand(0);
4503 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4504 if (Source == Sources.end())
4505 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4507 // Update the minimum and maximum lane number seen.
4508 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4509 Source->MinElt = std::min(Source->MinElt, EltNo);
4510 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4513 // Currently only do something sane when at most two source vectors
4515 if (Sources.size() > 2)
4518 // Find out the smallest element size among result and two sources, and use
4519 // it as element size to build the shuffle_vector.
4520 EVT SmallestEltTy = VT.getVectorElementType();
4521 for (auto &Source : Sources) {
4522 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4523 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4524 SmallestEltTy = SrcEltTy;
4527 unsigned ResMultiplier =
4528 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4529 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4530 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4532 // If the source vector is too wide or too narrow, we may nevertheless be able
4533 // to construct a compatible shuffle either by concatenating it with UNDEF or
4534 // extracting a suitable range of elements.
4535 for (auto &Src : Sources) {
4536 EVT SrcVT = Src.ShuffleVec.getValueType();
4538 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4541 // This stage of the search produces a source with the same element type as
4542 // the original, but with a total width matching the BUILD_VECTOR output.
4543 EVT EltVT = SrcVT.getVectorElementType();
4544 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4545 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4547 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4548 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4549 // We can pad out the smaller vector for free, so if it's part of a
4552 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4553 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4557 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4559 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4560 // Span too large for a VEXT to cope
4564 if (Src.MinElt >= NumSrcElts) {
4565 // The extraction can just take the second half
4567 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4568 DAG.getConstant(NumSrcElts, MVT::i64));
4569 Src.WindowBase = -NumSrcElts;
4570 } else if (Src.MaxElt < NumSrcElts) {
4571 // The extraction can just take the first half
4573 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4574 DAG.getConstant(0, MVT::i64));
4576 // An actual VEXT is needed
4578 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4579 DAG.getConstant(0, MVT::i64));
4581 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4582 DAG.getConstant(NumSrcElts, MVT::i64));
4583 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4585 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4586 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4587 Src.WindowBase = -Src.MinElt;
4591 // Another possible incompatibility occurs from the vector element types. We
4592 // can fix this by bitcasting the source vectors to the same type we intend
4594 for (auto &Src : Sources) {
4595 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4596 if (SrcEltTy == SmallestEltTy)
4598 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4599 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4600 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4601 Src.WindowBase *= Src.WindowScale;
4604 // Final sanity check before we try to actually produce a shuffle.
4606 for (auto Src : Sources)
4607 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4610 // The stars all align, our next step is to produce the mask for the shuffle.
4611 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4612 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4613 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4614 SDValue Entry = Op.getOperand(i);
4615 if (Entry.getOpcode() == ISD::UNDEF)
4618 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4619 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4621 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4622 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4624 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4625 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4626 VT.getVectorElementType().getSizeInBits());
4627 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4629 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4630 // starting at the appropriate offset.
4631 int *LaneMask = &Mask[i * ResMultiplier];
4633 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4634 ExtractBase += NumElts * (Src - Sources.begin());
4635 for (int j = 0; j < LanesDefined; ++j)
4636 LaneMask[j] = ExtractBase + j;
4639 // Final check before we try to produce nonsense...
4640 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4643 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4644 for (unsigned i = 0; i < Sources.size(); ++i)
4645 ShuffleOps[i] = Sources[i].ShuffleVec;
4647 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4648 ShuffleOps[1], &Mask[0]);
4649 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4652 // check if an EXT instruction can handle the shuffle mask when the
4653 // vector sources of the shuffle are the same.
4654 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4655 unsigned NumElts = VT.getVectorNumElements();
4657 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4663 // If this is a VEXT shuffle, the immediate value is the index of the first
4664 // element. The other shuffle indices must be the successive elements after
4666 unsigned ExpectedElt = Imm;
4667 for (unsigned i = 1; i < NumElts; ++i) {
4668 // Increment the expected index. If it wraps around, just follow it
4669 // back to index zero and keep going.
4671 if (ExpectedElt == NumElts)
4675 continue; // ignore UNDEF indices
4676 if (ExpectedElt != static_cast<unsigned>(M[i]))
4683 // check if an EXT instruction can handle the shuffle mask when the
4684 // vector sources of the shuffle are different.
4685 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4687 // Look for the first non-undef element.
4688 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4689 [](int Elt) {return Elt >= 0;});
4691 // Benefit form APInt to handle overflow when calculating expected element.
4692 unsigned NumElts = VT.getVectorNumElements();
4693 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4694 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4695 // The following shuffle indices must be the successive elements after the
4696 // first real element.
4697 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4698 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4699 if (FirstWrongElt != M.end())
4702 // The index of an EXT is the first element if it is not UNDEF.
4703 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4704 // value of the first element. E.g.
4705 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4706 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4707 // ExpectedElt is the last mask index plus 1.
4708 Imm = ExpectedElt.getZExtValue();
4710 // There are two difference cases requiring to reverse input vectors.
4711 // For example, for vector <4 x i32> we have the following cases,
4712 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4713 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4714 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4715 // to reverse two input vectors.
4724 /// isREVMask - Check if a vector shuffle corresponds to a REV
4725 /// instruction with the specified blocksize. (The order of the elements
4726 /// within each block of the vector is reversed.)
4727 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4728 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4729 "Only possible block sizes for REV are: 16, 32, 64");
4731 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4735 unsigned NumElts = VT.getVectorNumElements();
4736 unsigned BlockElts = M[0] + 1;
4737 // If the first shuffle index is UNDEF, be optimistic.
4739 BlockElts = BlockSize / EltSz;
4741 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4744 for (unsigned i = 0; i < NumElts; ++i) {
4746 continue; // ignore UNDEF indices
4747 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4754 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4755 unsigned NumElts = VT.getVectorNumElements();
4756 WhichResult = (M[0] == 0 ? 0 : 1);
4757 unsigned Idx = WhichResult * NumElts / 2;
4758 for (unsigned i = 0; i != NumElts; i += 2) {
4759 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4760 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4768 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4769 unsigned NumElts = VT.getVectorNumElements();
4770 WhichResult = (M[0] == 0 ? 0 : 1);
4771 for (unsigned i = 0; i != NumElts; ++i) {
4773 continue; // ignore UNDEF indices
4774 if ((unsigned)M[i] != 2 * i + WhichResult)
4781 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4782 unsigned NumElts = VT.getVectorNumElements();
4783 WhichResult = (M[0] == 0 ? 0 : 1);
4784 for (unsigned i = 0; i < NumElts; i += 2) {
4785 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4786 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4792 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4793 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4794 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4795 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4796 unsigned NumElts = VT.getVectorNumElements();
4797 WhichResult = (M[0] == 0 ? 0 : 1);
4798 unsigned Idx = WhichResult * NumElts / 2;
4799 for (unsigned i = 0; i != NumElts; i += 2) {
4800 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4801 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4809 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4810 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4811 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4812 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4813 unsigned Half = VT.getVectorNumElements() / 2;
4814 WhichResult = (M[0] == 0 ? 0 : 1);
4815 for (unsigned j = 0; j != 2; ++j) {
4816 unsigned Idx = WhichResult;
4817 for (unsigned i = 0; i != Half; ++i) {
4818 int MIdx = M[i + j * Half];
4819 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4828 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4829 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4830 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4831 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4832 unsigned NumElts = VT.getVectorNumElements();
4833 WhichResult = (M[0] == 0 ? 0 : 1);
4834 for (unsigned i = 0; i < NumElts; i += 2) {
4835 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4836 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4842 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4843 bool &DstIsLeft, int &Anomaly) {
4844 if (M.size() != static_cast<size_t>(NumInputElements))
4847 int NumLHSMatch = 0, NumRHSMatch = 0;
4848 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4850 for (int i = 0; i < NumInputElements; ++i) {
4860 LastLHSMismatch = i;
4862 if (M[i] == i + NumInputElements)
4865 LastRHSMismatch = i;
4868 if (NumLHSMatch == NumInputElements - 1) {
4870 Anomaly = LastLHSMismatch;
4872 } else if (NumRHSMatch == NumInputElements - 1) {
4874 Anomaly = LastRHSMismatch;
4881 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4882 if (VT.getSizeInBits() != 128)
4885 unsigned NumElts = VT.getVectorNumElements();
4887 for (int I = 0, E = NumElts / 2; I != E; I++) {
4892 int Offset = NumElts / 2;
4893 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4894 if (Mask[I] != I + SplitLHS * Offset)
4901 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4903 EVT VT = Op.getValueType();
4904 SDValue V0 = Op.getOperand(0);
4905 SDValue V1 = Op.getOperand(1);
4906 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4908 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4909 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4912 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4914 if (!isConcatMask(Mask, VT, SplitV0))
4917 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4918 VT.getVectorNumElements() / 2);
4920 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4921 DAG.getConstant(0, MVT::i64));
4923 if (V1.getValueType().getSizeInBits() == 128) {
4924 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4925 DAG.getConstant(0, MVT::i64));
4927 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4930 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4931 /// the specified operations to build the shuffle.
4932 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4933 SDValue RHS, SelectionDAG &DAG,
4935 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4936 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4937 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4940 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4949 OP_VUZPL, // VUZP, left result
4950 OP_VUZPR, // VUZP, right result
4951 OP_VZIPL, // VZIP, left result
4952 OP_VZIPR, // VZIP, right result
4953 OP_VTRNL, // VTRN, left result
4954 OP_VTRNR // VTRN, right result
4957 if (OpNum == OP_COPY) {
4958 if (LHSID == (1 * 9 + 2) * 9 + 3)
4960 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4964 SDValue OpLHS, OpRHS;
4965 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4966 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4967 EVT VT = OpLHS.getValueType();
4971 llvm_unreachable("Unknown shuffle opcode!");
4973 // VREV divides the vector in half and swaps within the half.
4974 if (VT.getVectorElementType() == MVT::i32 ||
4975 VT.getVectorElementType() == MVT::f32)
4976 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4977 // vrev <4 x i16> -> REV32
4978 if (VT.getVectorElementType() == MVT::i16 ||
4979 VT.getVectorElementType() == MVT::f16)
4980 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4981 // vrev <4 x i8> -> REV16
4982 assert(VT.getVectorElementType() == MVT::i8);
4983 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4988 EVT EltTy = VT.getVectorElementType();
4990 if (EltTy == MVT::i8)
4991 Opcode = AArch64ISD::DUPLANE8;
4992 else if (EltTy == MVT::i16)
4993 Opcode = AArch64ISD::DUPLANE16;
4994 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4995 Opcode = AArch64ISD::DUPLANE32;
4996 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4997 Opcode = AArch64ISD::DUPLANE64;
4999 llvm_unreachable("Invalid vector element type?");
5001 if (VT.getSizeInBits() == 64)
5002 OpLHS = WidenVector(OpLHS, DAG);
5003 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5004 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5009 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5010 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5011 DAG.getConstant(Imm, MVT::i32));
5014 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5017 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5020 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5023 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5026 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5029 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5034 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5035 SelectionDAG &DAG) {
5036 // Check to see if we can use the TBL instruction.
5037 SDValue V1 = Op.getOperand(0);
5038 SDValue V2 = Op.getOperand(1);
5041 EVT EltVT = Op.getValueType().getVectorElementType();
5042 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5044 SmallVector<SDValue, 8> TBLMask;
5045 for (int Val : ShuffleMask) {
5046 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5047 unsigned Offset = Byte + Val * BytesPerElt;
5048 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5052 MVT IndexVT = MVT::v8i8;
5053 unsigned IndexLen = 8;
5054 if (Op.getValueType().getSizeInBits() == 128) {
5055 IndexVT = MVT::v16i8;
5059 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5060 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5063 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5065 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5066 Shuffle = DAG.getNode(
5067 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5068 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5069 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5070 makeArrayRef(TBLMask.data(), IndexLen)));
5072 if (IndexLen == 8) {
5073 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5074 Shuffle = DAG.getNode(
5075 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5076 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5077 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5078 makeArrayRef(TBLMask.data(), IndexLen)));
5080 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5081 // cannot currently represent the register constraints on the input
5083 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5084 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5085 // &TBLMask[0], IndexLen));
5086 Shuffle = DAG.getNode(
5087 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5088 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5089 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5090 makeArrayRef(TBLMask.data(), IndexLen)));
5093 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5096 static unsigned getDUPLANEOp(EVT EltType) {
5097 if (EltType == MVT::i8)
5098 return AArch64ISD::DUPLANE8;
5099 if (EltType == MVT::i16 || EltType == MVT::f16)
5100 return AArch64ISD::DUPLANE16;
5101 if (EltType == MVT::i32 || EltType == MVT::f32)
5102 return AArch64ISD::DUPLANE32;
5103 if (EltType == MVT::i64 || EltType == MVT::f64)
5104 return AArch64ISD::DUPLANE64;
5106 llvm_unreachable("Invalid vector element type?");
5109 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5110 SelectionDAG &DAG) const {
5112 EVT VT = Op.getValueType();
5114 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5116 // Convert shuffles that are directly supported on NEON to target-specific
5117 // DAG nodes, instead of keeping them as shuffles and matching them again
5118 // during code selection. This is more efficient and avoids the possibility
5119 // of inconsistencies between legalization and selection.
5120 ArrayRef<int> ShuffleMask = SVN->getMask();
5122 SDValue V1 = Op.getOperand(0);
5123 SDValue V2 = Op.getOperand(1);
5125 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5126 V1.getValueType().getSimpleVT())) {
5127 int Lane = SVN->getSplatIndex();
5128 // If this is undef splat, generate it via "just" vdup, if possible.
5132 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5133 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5135 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5136 // constant. If so, we can just reference the lane's definition directly.
5137 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5138 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5139 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5141 // Otherwise, duplicate from the lane of the input vector.
5142 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5144 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5145 // to make a vector of the same size as this SHUFFLE. We can ignore the
5146 // extract entirely, and canonicalise the concat using WidenVector.
5147 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5148 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5149 V1 = V1.getOperand(0);
5150 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5151 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5152 Lane -= Idx * VT.getVectorNumElements() / 2;
5153 V1 = WidenVector(V1.getOperand(Idx), DAG);
5154 } else if (VT.getSizeInBits() == 64)
5155 V1 = WidenVector(V1, DAG);
5157 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5160 if (isREVMask(ShuffleMask, VT, 64))
5161 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5162 if (isREVMask(ShuffleMask, VT, 32))
5163 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5164 if (isREVMask(ShuffleMask, VT, 16))
5165 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5167 bool ReverseEXT = false;
5169 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5172 Imm *= getExtFactor(V1);
5173 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5174 DAG.getConstant(Imm, MVT::i32));
5175 } else if (V2->getOpcode() == ISD::UNDEF &&
5176 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5177 Imm *= getExtFactor(V1);
5178 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5179 DAG.getConstant(Imm, MVT::i32));
5182 unsigned WhichResult;
5183 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5184 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5185 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5187 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5188 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5189 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5191 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5192 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5193 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5196 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5197 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5198 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5200 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5201 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5202 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5204 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5205 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5206 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5209 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5210 if (Concat.getNode())
5215 int NumInputElements = V1.getValueType().getVectorNumElements();
5216 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5217 SDValue DstVec = DstIsLeft ? V1 : V2;
5218 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5220 SDValue SrcVec = V1;
5221 int SrcLane = ShuffleMask[Anomaly];
5222 if (SrcLane >= NumInputElements) {
5224 SrcLane -= VT.getVectorNumElements();
5226 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5228 EVT ScalarVT = VT.getVectorElementType();
5230 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5231 ScalarVT = MVT::i32;
5234 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5235 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5239 // If the shuffle is not directly supported and it has 4 elements, use
5240 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5241 unsigned NumElts = VT.getVectorNumElements();
5243 unsigned PFIndexes[4];
5244 for (unsigned i = 0; i != 4; ++i) {
5245 if (ShuffleMask[i] < 0)
5248 PFIndexes[i] = ShuffleMask[i];
5251 // Compute the index in the perfect shuffle table.
5252 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5253 PFIndexes[2] * 9 + PFIndexes[3];
5254 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5255 unsigned Cost = (PFEntry >> 30);
5258 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5261 return GenerateTBL(Op, ShuffleMask, DAG);
5264 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5266 EVT VT = BVN->getValueType(0);
5267 APInt SplatBits, SplatUndef;
5268 unsigned SplatBitSize;
5270 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5271 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5273 for (unsigned i = 0; i < NumSplats; ++i) {
5274 CnstBits <<= SplatBitSize;
5275 UndefBits <<= SplatBitSize;
5276 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5277 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5286 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5287 SelectionDAG &DAG) const {
5288 BuildVectorSDNode *BVN =
5289 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5290 SDValue LHS = Op.getOperand(0);
5292 EVT VT = Op.getValueType();
5297 APInt CnstBits(VT.getSizeInBits(), 0);
5298 APInt UndefBits(VT.getSizeInBits(), 0);
5299 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5300 // We only have BIC vector immediate instruction, which is and-not.
5301 CnstBits = ~CnstBits;
5303 // We make use of a little bit of goto ickiness in order to avoid having to
5304 // duplicate the immediate matching logic for the undef toggled case.
5305 bool SecondTry = false;
5308 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5309 CnstBits = CnstBits.zextOrTrunc(64);
5310 uint64_t CnstVal = CnstBits.getZExtValue();
5312 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5313 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5314 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5315 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5316 DAG.getConstant(CnstVal, MVT::i32),
5317 DAG.getConstant(0, MVT::i32));
5318 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5321 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5322 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5323 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5324 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5325 DAG.getConstant(CnstVal, MVT::i32),
5326 DAG.getConstant(8, MVT::i32));
5327 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5330 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5331 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5332 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5333 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5334 DAG.getConstant(CnstVal, MVT::i32),
5335 DAG.getConstant(16, MVT::i32));
5336 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5339 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5340 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5341 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5342 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5343 DAG.getConstant(CnstVal, MVT::i32),
5344 DAG.getConstant(24, MVT::i32));
5345 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5348 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5349 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5350 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5351 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5352 DAG.getConstant(CnstVal, MVT::i32),
5353 DAG.getConstant(0, MVT::i32));
5354 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5357 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5358 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5359 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5360 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5361 DAG.getConstant(CnstVal, MVT::i32),
5362 DAG.getConstant(8, MVT::i32));
5363 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5370 CnstBits = ~UndefBits;
5374 // We can always fall back to a non-immediate AND.
5379 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5380 // consists of only the same constant int value, returned in reference arg
5382 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5383 uint64_t &ConstVal) {
5384 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5387 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5390 EVT VT = Bvec->getValueType(0);
5391 unsigned NumElts = VT.getVectorNumElements();
5392 for (unsigned i = 1; i < NumElts; ++i)
5393 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5395 ConstVal = FirstElt->getZExtValue();
5399 static unsigned getIntrinsicID(const SDNode *N) {
5400 unsigned Opcode = N->getOpcode();
5403 return Intrinsic::not_intrinsic;
5404 case ISD::INTRINSIC_WO_CHAIN: {
5405 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5406 if (IID < Intrinsic::num_intrinsics)
5408 return Intrinsic::not_intrinsic;
5413 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5414 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5415 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5416 // Also, logical shift right -> sri, with the same structure.
5417 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5418 EVT VT = N->getValueType(0);
5425 // Is the first op an AND?
5426 const SDValue And = N->getOperand(0);
5427 if (And.getOpcode() != ISD::AND)
5430 // Is the second op an shl or lshr?
5431 SDValue Shift = N->getOperand(1);
5432 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5433 // or AArch64ISD::VLSHR vector, #shift
5434 unsigned ShiftOpc = Shift.getOpcode();
5435 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5437 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5439 // Is the shift amount constant?
5440 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5444 // Is the and mask vector all constant?
5446 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5449 // Is C1 == ~C2, taking into account how much one can shift elements of a
5451 uint64_t C2 = C2node->getZExtValue();
5452 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5453 if (C2 > ElemSizeInBits)
5455 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5456 if ((C1 & ElemMask) != (~C2 & ElemMask))
5459 SDValue X = And.getOperand(0);
5460 SDValue Y = Shift.getOperand(0);
5463 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5465 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5466 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5468 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5469 DEBUG(N->dump(&DAG));
5470 DEBUG(dbgs() << "into: \n");
5471 DEBUG(ResultSLI->dump(&DAG));
5477 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5478 SelectionDAG &DAG) const {
5479 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5480 if (EnableAArch64SlrGeneration) {
5481 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5486 BuildVectorSDNode *BVN =
5487 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5488 SDValue LHS = Op.getOperand(1);
5490 EVT VT = Op.getValueType();
5492 // OR commutes, so try swapping the operands.
5494 LHS = Op.getOperand(0);
5495 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5500 APInt CnstBits(VT.getSizeInBits(), 0);
5501 APInt UndefBits(VT.getSizeInBits(), 0);
5502 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5503 // We make use of a little bit of goto ickiness in order to avoid having to
5504 // duplicate the immediate matching logic for the undef toggled case.
5505 bool SecondTry = false;
5508 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5509 CnstBits = CnstBits.zextOrTrunc(64);
5510 uint64_t CnstVal = CnstBits.getZExtValue();
5512 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5513 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5514 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5515 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5516 DAG.getConstant(CnstVal, MVT::i32),
5517 DAG.getConstant(0, MVT::i32));
5518 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5521 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5522 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5523 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5524 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5525 DAG.getConstant(CnstVal, MVT::i32),
5526 DAG.getConstant(8, MVT::i32));
5527 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5530 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5531 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5532 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5533 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5534 DAG.getConstant(CnstVal, MVT::i32),
5535 DAG.getConstant(16, MVT::i32));
5536 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5539 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5540 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5541 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5542 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5543 DAG.getConstant(CnstVal, MVT::i32),
5544 DAG.getConstant(24, MVT::i32));
5545 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5548 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5549 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5550 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5551 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5552 DAG.getConstant(CnstVal, MVT::i32),
5553 DAG.getConstant(0, MVT::i32));
5554 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5557 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5558 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5559 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5560 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5561 DAG.getConstant(CnstVal, MVT::i32),
5562 DAG.getConstant(8, MVT::i32));
5563 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5570 CnstBits = UndefBits;
5574 // We can always fall back to a non-immediate OR.
5579 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5580 // be truncated to fit element width.
5581 static SDValue NormalizeBuildVector(SDValue Op,
5582 SelectionDAG &DAG) {
5583 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5585 EVT VT = Op.getValueType();
5586 EVT EltTy= VT.getVectorElementType();
5588 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5591 SmallVector<SDValue, 16> Ops;
5592 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5593 SDValue Lane = Op.getOperand(I);
5594 if (Lane.getOpcode() == ISD::Constant) {
5595 APInt LowBits(EltTy.getSizeInBits(),
5596 cast<ConstantSDNode>(Lane)->getZExtValue());
5597 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5599 Ops.push_back(Lane);
5601 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5604 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5605 SelectionDAG &DAG) const {
5607 EVT VT = Op.getValueType();
5608 Op = NormalizeBuildVector(Op, DAG);
5609 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5611 APInt CnstBits(VT.getSizeInBits(), 0);
5612 APInt UndefBits(VT.getSizeInBits(), 0);
5613 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5614 // We make use of a little bit of goto ickiness in order to avoid having to
5615 // duplicate the immediate matching logic for the undef toggled case.
5616 bool SecondTry = false;
5619 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5620 CnstBits = CnstBits.zextOrTrunc(64);
5621 uint64_t CnstVal = CnstBits.getZExtValue();
5623 // Certain magic vector constants (used to express things like NOT
5624 // and NEG) are passed through unmodified. This allows codegen patterns
5625 // for these operations to match. Special-purpose patterns will lower
5626 // these immediates to MOVIs if it proves necessary.
5627 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5630 // The many faces of MOVI...
5631 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5632 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5633 if (VT.getSizeInBits() == 128) {
5634 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5635 DAG.getConstant(CnstVal, MVT::i32));
5636 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5639 // Support the V64 version via subregister insertion.
5640 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5641 DAG.getConstant(CnstVal, MVT::i32));
5642 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5645 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5646 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5647 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5648 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5649 DAG.getConstant(CnstVal, MVT::i32),
5650 DAG.getConstant(0, MVT::i32));
5651 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5654 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5655 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5656 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5657 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5658 DAG.getConstant(CnstVal, MVT::i32),
5659 DAG.getConstant(8, MVT::i32));
5660 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5663 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5664 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5665 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5666 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5667 DAG.getConstant(CnstVal, MVT::i32),
5668 DAG.getConstant(16, MVT::i32));
5669 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5672 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5673 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5674 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5675 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5676 DAG.getConstant(CnstVal, MVT::i32),
5677 DAG.getConstant(24, MVT::i32));
5678 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5681 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5682 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5683 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5684 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5685 DAG.getConstant(CnstVal, MVT::i32),
5686 DAG.getConstant(0, MVT::i32));
5687 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5690 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5691 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5692 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5693 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5694 DAG.getConstant(CnstVal, MVT::i32),
5695 DAG.getConstant(8, MVT::i32));
5696 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5699 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5700 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5701 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5702 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5703 DAG.getConstant(CnstVal, MVT::i32),
5704 DAG.getConstant(264, MVT::i32));
5705 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5708 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5709 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5710 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5711 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5712 DAG.getConstant(CnstVal, MVT::i32),
5713 DAG.getConstant(272, MVT::i32));
5714 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5717 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5718 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5719 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5720 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5721 DAG.getConstant(CnstVal, MVT::i32));
5722 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5725 // The few faces of FMOV...
5726 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5727 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5728 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5729 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5730 DAG.getConstant(CnstVal, MVT::i32));
5731 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5734 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5735 VT.getSizeInBits() == 128) {
5736 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5737 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5738 DAG.getConstant(CnstVal, MVT::i32));
5739 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5742 // The many faces of MVNI...
5744 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5745 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5746 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5747 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5748 DAG.getConstant(CnstVal, MVT::i32),
5749 DAG.getConstant(0, MVT::i32));
5750 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5753 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5754 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5755 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5756 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5757 DAG.getConstant(CnstVal, MVT::i32),
5758 DAG.getConstant(8, MVT::i32));
5759 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5762 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5763 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5764 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5765 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5766 DAG.getConstant(CnstVal, MVT::i32),
5767 DAG.getConstant(16, MVT::i32));
5768 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5771 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5772 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5773 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5774 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5775 DAG.getConstant(CnstVal, MVT::i32),
5776 DAG.getConstant(24, MVT::i32));
5777 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5780 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5781 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5782 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5783 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5784 DAG.getConstant(CnstVal, MVT::i32),
5785 DAG.getConstant(0, MVT::i32));
5786 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5789 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5790 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5791 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5792 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5793 DAG.getConstant(CnstVal, MVT::i32),
5794 DAG.getConstant(8, MVT::i32));
5795 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5798 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5799 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5800 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5801 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5802 DAG.getConstant(CnstVal, MVT::i32),
5803 DAG.getConstant(264, MVT::i32));
5804 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5807 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5808 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5809 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5810 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5811 DAG.getConstant(CnstVal, MVT::i32),
5812 DAG.getConstant(272, MVT::i32));
5813 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5820 CnstBits = UndefBits;
5825 // Scan through the operands to find some interesting properties we can
5827 // 1) If only one value is used, we can use a DUP, or
5828 // 2) if only the low element is not undef, we can just insert that, or
5829 // 3) if only one constant value is used (w/ some non-constant lanes),
5830 // we can splat the constant value into the whole vector then fill
5831 // in the non-constant lanes.
5832 // 4) FIXME: If different constant values are used, but we can intelligently
5833 // select the values we'll be overwriting for the non-constant
5834 // lanes such that we can directly materialize the vector
5835 // some other way (MOVI, e.g.), we can be sneaky.
5836 unsigned NumElts = VT.getVectorNumElements();
5837 bool isOnlyLowElement = true;
5838 bool usesOnlyOneValue = true;
5839 bool usesOnlyOneConstantValue = true;
5840 bool isConstant = true;
5841 unsigned NumConstantLanes = 0;
5843 SDValue ConstantValue;
5844 for (unsigned i = 0; i < NumElts; ++i) {
5845 SDValue V = Op.getOperand(i);
5846 if (V.getOpcode() == ISD::UNDEF)
5849 isOnlyLowElement = false;
5850 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5853 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5855 if (!ConstantValue.getNode())
5857 else if (ConstantValue != V)
5858 usesOnlyOneConstantValue = false;
5861 if (!Value.getNode())
5863 else if (V != Value)
5864 usesOnlyOneValue = false;
5867 if (!Value.getNode())
5868 return DAG.getUNDEF(VT);
5870 if (isOnlyLowElement)
5871 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5873 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5874 // i32 and try again.
5875 if (usesOnlyOneValue) {
5877 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5878 Value.getValueType() != VT)
5879 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5881 // This is actually a DUPLANExx operation, which keeps everything vectory.
5883 // DUPLANE works on 128-bit vectors, widen it if necessary.
5884 SDValue Lane = Value.getOperand(1);
5885 Value = Value.getOperand(0);
5886 if (Value.getValueType().getSizeInBits() == 64)
5887 Value = WidenVector(Value, DAG);
5889 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5890 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5893 if (VT.getVectorElementType().isFloatingPoint()) {
5894 SmallVector<SDValue, 8> Ops;
5895 EVT EltTy = VT.getVectorElementType();
5896 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5897 "Unsupported floating-point vector type");
5898 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5899 for (unsigned i = 0; i < NumElts; ++i)
5900 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5901 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5902 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5903 Val = LowerBUILD_VECTOR(Val, DAG);
5905 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5909 // If there was only one constant value used and for more than one lane,
5910 // start by splatting that value, then replace the non-constant lanes. This
5911 // is better than the default, which will perform a separate initialization
5913 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5914 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5915 // Now insert the non-constant lanes.
5916 for (unsigned i = 0; i < NumElts; ++i) {
5917 SDValue V = Op.getOperand(i);
5918 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5919 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5920 // Note that type legalization likely mucked about with the VT of the
5921 // source operand, so we may have to convert it here before inserting.
5922 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5928 // If all elements are constants and the case above didn't get hit, fall back
5929 // to the default expansion, which will generate a load from the constant
5934 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5936 SDValue shuffle = ReconstructShuffle(Op, DAG);
5937 if (shuffle != SDValue())
5941 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5942 // know the default expansion would otherwise fall back on something even
5943 // worse. For a vector with one or two non-undef values, that's
5944 // scalar_to_vector for the elements followed by a shuffle (provided the
5945 // shuffle is valid for the target) and materialization element by element
5946 // on the stack followed by a load for everything else.
5947 if (!isConstant && !usesOnlyOneValue) {
5948 SDValue Vec = DAG.getUNDEF(VT);
5949 SDValue Op0 = Op.getOperand(0);
5950 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5952 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5953 // a) Avoid a RMW dependency on the full vector register, and
5954 // b) Allow the register coalescer to fold away the copy if the
5955 // value is already in an S or D register.
5956 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5957 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5959 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5960 DAG.getTargetConstant(SubIdx, MVT::i32));
5961 Vec = SDValue(N, 0);
5964 for (; i < NumElts; ++i) {
5965 SDValue V = Op.getOperand(i);
5966 if (V.getOpcode() == ISD::UNDEF)
5968 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5969 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5974 // Just use the default expansion. We failed to find a better alternative.
5978 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5979 SelectionDAG &DAG) const {
5980 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5982 // Check for non-constant or out of range lane.
5983 EVT VT = Op.getOperand(0).getValueType();
5984 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5985 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5989 // Insertion/extraction are legal for V128 types.
5990 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5991 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5995 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5996 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5999 // For V64 types, we perform insertion by expanding the value
6000 // to a V128 type and perform the insertion on that.
6002 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6003 EVT WideTy = WideVec.getValueType();
6005 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6006 Op.getOperand(1), Op.getOperand(2));
6007 // Re-narrow the resultant vector.
6008 return NarrowVector(Node, DAG);
6012 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6013 SelectionDAG &DAG) const {
6014 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6016 // Check for non-constant or out of range lane.
6017 EVT VT = Op.getOperand(0).getValueType();
6018 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6019 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6023 // Insertion/extraction are legal for V128 types.
6024 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6025 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6029 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6030 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6033 // For V64 types, we perform extraction by expanding the value
6034 // to a V128 type and perform the extraction on that.
6036 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6037 EVT WideTy = WideVec.getValueType();
6039 EVT ExtrTy = WideTy.getVectorElementType();
6040 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6043 // For extractions, we just return the result directly.
6044 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6048 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6049 SelectionDAG &DAG) const {
6050 EVT VT = Op.getOperand(0).getValueType();
6056 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6059 unsigned Val = Cst->getZExtValue();
6061 unsigned Size = Op.getValueType().getSizeInBits();
6065 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6068 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6071 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6074 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6077 llvm_unreachable("Unexpected vector type in extract_subvector!");
6080 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6082 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6088 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6090 if (VT.getVectorNumElements() == 4 &&
6091 (VT.is128BitVector() || VT.is64BitVector())) {
6092 unsigned PFIndexes[4];
6093 for (unsigned i = 0; i != 4; ++i) {
6097 PFIndexes[i] = M[i];
6100 // Compute the index in the perfect shuffle table.
6101 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6102 PFIndexes[2] * 9 + PFIndexes[3];
6103 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6104 unsigned Cost = (PFEntry >> 30);
6112 unsigned DummyUnsigned;
6114 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6115 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6116 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6117 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6118 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6119 isZIPMask(M, VT, DummyUnsigned) ||
6120 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6121 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6122 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6123 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6124 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6127 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6128 /// operand of a vector shift operation, where all the elements of the
6129 /// build_vector must have the same constant integer value.
6130 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6131 // Ignore bit_converts.
6132 while (Op.getOpcode() == ISD::BITCAST)
6133 Op = Op.getOperand(0);
6134 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6135 APInt SplatBits, SplatUndef;
6136 unsigned SplatBitSize;
6138 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6139 HasAnyUndefs, ElementBits) ||
6140 SplatBitSize > ElementBits)
6142 Cnt = SplatBits.getSExtValue();
6146 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6147 /// operand of a vector shift left operation. That value must be in the range:
6148 /// 0 <= Value < ElementBits for a left shift; or
6149 /// 0 <= Value <= ElementBits for a long left shift.
6150 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6151 assert(VT.isVector() && "vector shift count is not a vector type");
6152 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6153 if (!getVShiftImm(Op, ElementBits, Cnt))
6155 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6158 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6159 /// operand of a vector shift right operation. For a shift opcode, the value
6160 /// is positive, but for an intrinsic the value count must be negative. The
6161 /// absolute value must be in the range:
6162 /// 1 <= |Value| <= ElementBits for a right shift; or
6163 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6164 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6166 assert(VT.isVector() && "vector shift count is not a vector type");
6167 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6168 if (!getVShiftImm(Op, ElementBits, Cnt))
6172 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6175 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6176 SelectionDAG &DAG) const {
6177 EVT VT = Op.getValueType();
6181 if (!Op.getOperand(1).getValueType().isVector())
6183 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6185 switch (Op.getOpcode()) {
6187 llvm_unreachable("unexpected shift opcode");
6190 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6191 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6192 DAG.getConstant(Cnt, MVT::i32));
6193 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6194 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6195 Op.getOperand(0), Op.getOperand(1));
6198 // Right shift immediate
6199 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6202 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6203 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6204 DAG.getConstant(Cnt, MVT::i32));
6207 // Right shift register. Note, there is not a shift right register
6208 // instruction, but the shift left register instruction takes a signed
6209 // value, where negative numbers specify a right shift.
6210 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6211 : Intrinsic::aarch64_neon_ushl;
6212 // negate the shift amount
6213 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6214 SDValue NegShiftLeft =
6215 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6216 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6217 return NegShiftLeft;
6223 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6224 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6225 SDLoc dl, SelectionDAG &DAG) {
6226 EVT SrcVT = LHS.getValueType();
6227 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6228 "function only supposed to emit natural comparisons");
6230 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6231 APInt CnstBits(VT.getSizeInBits(), 0);
6232 APInt UndefBits(VT.getSizeInBits(), 0);
6233 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6234 bool IsZero = IsCnst && (CnstBits == 0);
6236 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6240 case AArch64CC::NE: {
6243 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6245 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6246 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6250 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6251 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6254 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6255 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6258 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6259 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6262 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6263 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6267 // If we ignore NaNs then we can use to the MI implementation.
6271 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6272 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6279 case AArch64CC::NE: {
6282 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6284 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6285 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6289 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6290 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6293 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6294 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6297 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6298 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6301 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6302 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6304 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6306 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6309 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6310 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6312 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6314 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6318 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6319 SelectionDAG &DAG) const {
6320 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6321 SDValue LHS = Op.getOperand(0);
6322 SDValue RHS = Op.getOperand(1);
6323 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6326 if (LHS.getValueType().getVectorElementType().isInteger()) {
6327 assert(LHS.getValueType() == RHS.getValueType());
6328 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6330 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6331 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6334 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6335 LHS.getValueType().getVectorElementType() == MVT::f64);
6337 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6338 // clean. Some of them require two branches to implement.
6339 AArch64CC::CondCode CC1, CC2;
6341 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6343 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6345 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6349 if (CC2 != AArch64CC::AL) {
6351 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6352 if (!Cmp2.getNode())
6355 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6358 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6361 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6366 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6367 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6368 /// specified in the intrinsic calls.
6369 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6371 unsigned Intrinsic) const {
6372 switch (Intrinsic) {
6373 case Intrinsic::aarch64_neon_ld2:
6374 case Intrinsic::aarch64_neon_ld3:
6375 case Intrinsic::aarch64_neon_ld4:
6376 case Intrinsic::aarch64_neon_ld1x2:
6377 case Intrinsic::aarch64_neon_ld1x3:
6378 case Intrinsic::aarch64_neon_ld1x4:
6379 case Intrinsic::aarch64_neon_ld2lane:
6380 case Intrinsic::aarch64_neon_ld3lane:
6381 case Intrinsic::aarch64_neon_ld4lane:
6382 case Intrinsic::aarch64_neon_ld2r:
6383 case Intrinsic::aarch64_neon_ld3r:
6384 case Intrinsic::aarch64_neon_ld4r: {
6385 Info.opc = ISD::INTRINSIC_W_CHAIN;
6386 // Conservatively set memVT to the entire set of vectors loaded.
6387 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6388 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6389 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6392 Info.vol = false; // volatile loads with NEON intrinsics not supported
6393 Info.readMem = true;
6394 Info.writeMem = false;
6397 case Intrinsic::aarch64_neon_st2:
6398 case Intrinsic::aarch64_neon_st3:
6399 case Intrinsic::aarch64_neon_st4:
6400 case Intrinsic::aarch64_neon_st1x2:
6401 case Intrinsic::aarch64_neon_st1x3:
6402 case Intrinsic::aarch64_neon_st1x4:
6403 case Intrinsic::aarch64_neon_st2lane:
6404 case Intrinsic::aarch64_neon_st3lane:
6405 case Intrinsic::aarch64_neon_st4lane: {
6406 Info.opc = ISD::INTRINSIC_VOID;
6407 // Conservatively set memVT to the entire set of vectors stored.
6408 unsigned NumElts = 0;
6409 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6410 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6411 if (!ArgTy->isVectorTy())
6413 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6415 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6416 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6419 Info.vol = false; // volatile stores with NEON intrinsics not supported
6420 Info.readMem = false;
6421 Info.writeMem = true;
6424 case Intrinsic::aarch64_ldaxr:
6425 case Intrinsic::aarch64_ldxr: {
6426 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6427 Info.opc = ISD::INTRINSIC_W_CHAIN;
6428 Info.memVT = MVT::getVT(PtrTy->getElementType());
6429 Info.ptrVal = I.getArgOperand(0);
6431 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6433 Info.readMem = true;
6434 Info.writeMem = false;
6437 case Intrinsic::aarch64_stlxr:
6438 case Intrinsic::aarch64_stxr: {
6439 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6440 Info.opc = ISD::INTRINSIC_W_CHAIN;
6441 Info.memVT = MVT::getVT(PtrTy->getElementType());
6442 Info.ptrVal = I.getArgOperand(1);
6444 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6446 Info.readMem = false;
6447 Info.writeMem = true;
6450 case Intrinsic::aarch64_ldaxp:
6451 case Intrinsic::aarch64_ldxp: {
6452 Info.opc = ISD::INTRINSIC_W_CHAIN;
6453 Info.memVT = MVT::i128;
6454 Info.ptrVal = I.getArgOperand(0);
6458 Info.readMem = true;
6459 Info.writeMem = false;
6462 case Intrinsic::aarch64_stlxp:
6463 case Intrinsic::aarch64_stxp: {
6464 Info.opc = ISD::INTRINSIC_W_CHAIN;
6465 Info.memVT = MVT::i128;
6466 Info.ptrVal = I.getArgOperand(2);
6470 Info.readMem = false;
6471 Info.writeMem = true;
6481 // Truncations from 64-bit GPR to 32-bit GPR is free.
6482 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6483 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6485 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6486 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6487 return NumBits1 > NumBits2;
6489 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6490 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6492 unsigned NumBits1 = VT1.getSizeInBits();
6493 unsigned NumBits2 = VT2.getSizeInBits();
6494 return NumBits1 > NumBits2;
6497 /// Check if it is profitable to hoist instruction in then/else to if.
6498 /// Not profitable if I and it's user can form a FMA instruction
6499 /// because we prefer FMSUB/FMADD.
6500 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6501 if (I->getOpcode() != Instruction::FMul)
6504 if (I->getNumUses() != 1)
6507 Instruction *User = I->user_back();
6510 !(User->getOpcode() == Instruction::FSub ||
6511 User->getOpcode() == Instruction::FAdd))
6514 const TargetOptions &Options = getTargetMachine().Options;
6515 EVT VT = getValueType(User->getOperand(0)->getType());
6517 if (isFMAFasterThanFMulAndFAdd(VT) &&
6518 isOperationLegalOrCustom(ISD::FMA, VT) &&
6519 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6525 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6527 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6528 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6530 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6531 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6532 return NumBits1 == 32 && NumBits2 == 64;
6534 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6535 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6537 unsigned NumBits1 = VT1.getSizeInBits();
6538 unsigned NumBits2 = VT2.getSizeInBits();
6539 return NumBits1 == 32 && NumBits2 == 64;
6542 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6543 EVT VT1 = Val.getValueType();
6544 if (isZExtFree(VT1, VT2)) {
6548 if (Val.getOpcode() != ISD::LOAD)
6551 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6552 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6553 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6554 VT1.getSizeInBits() <= 32);
6557 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6558 unsigned &RequiredAligment) const {
6559 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6561 // Cyclone supports unaligned accesses.
6562 RequiredAligment = 0;
6563 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6564 return NumBits == 32 || NumBits == 64;
6567 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6568 unsigned &RequiredAligment) const {
6569 if (!LoadedType.isSimple() ||
6570 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6572 // Cyclone supports unaligned accesses.
6573 RequiredAligment = 0;
6574 unsigned NumBits = LoadedType.getSizeInBits();
6575 return NumBits == 32 || NumBits == 64;
6578 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6579 unsigned AlignCheck) {
6580 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6581 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6584 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6585 unsigned SrcAlign, bool IsMemset,
6588 MachineFunction &MF) const {
6589 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6590 // instruction to materialize the v2i64 zero and one store (with restrictive
6591 // addressing mode). Just do two i64 store of zero-registers.
6593 const Function *F = MF.getFunction();
6594 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6595 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6596 (memOpAlign(SrcAlign, DstAlign, 16) ||
6597 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6600 return Size >= 8 ? MVT::i64 : MVT::i32;
6603 // 12-bit optionally shifted immediates are legal for adds.
6604 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6605 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6610 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6611 // immediates is the same as for an add or a sub.
6612 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6615 return isLegalAddImmediate(Immed);
6618 /// isLegalAddressingMode - Return true if the addressing mode represented
6619 /// by AM is legal for this target, for a load/store of the specified type.
6620 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6622 // AArch64 has five basic addressing modes:
6624 // reg + 9-bit signed offset
6625 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6627 // reg + SIZE_IN_BYTES * reg
6629 // No global is ever allowed as a base.
6633 // No reg+reg+imm addressing.
6634 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6637 // check reg + imm case:
6638 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6639 uint64_t NumBytes = 0;
6640 if (Ty->isSized()) {
6641 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6642 NumBytes = NumBits / 8;
6643 if (!isPowerOf2_64(NumBits))
6648 int64_t Offset = AM.BaseOffs;
6650 // 9-bit signed offset
6651 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6654 // 12-bit unsigned offset
6655 unsigned shift = Log2_64(NumBytes);
6656 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6657 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6658 (Offset >> shift) << shift == Offset)
6663 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6665 if (!AM.Scale || AM.Scale == 1 ||
6666 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6671 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6673 // Scaling factors are not free at all.
6674 // Operands | Rt Latency
6675 // -------------------------------------------
6677 // -------------------------------------------
6678 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6679 // Rt, [Xn, Wm, <extend> #imm] |
6680 if (isLegalAddressingMode(AM, Ty))
6681 // Scale represents reg2 * scale, thus account for 1 if
6682 // it is not equal to 0 or 1.
6683 return AM.Scale != 0 && AM.Scale != 1;
6687 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6688 VT = VT.getScalarType();
6693 switch (VT.getSimpleVT().SimpleTy) {
6705 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6706 // LR is a callee-save register, but we must treat it as clobbered by any call
6707 // site. Hence we include LR in the scratch registers, which are in turn added
6708 // as implicit-defs for stackmaps and patchpoints.
6709 static const MCPhysReg ScratchRegs[] = {
6710 AArch64::X16, AArch64::X17, AArch64::LR, 0
6716 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6717 EVT VT = N->getValueType(0);
6718 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6719 // it with shift to let it be lowered to UBFX.
6720 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6721 isa<ConstantSDNode>(N->getOperand(1))) {
6722 uint64_t TruncMask = N->getConstantOperandVal(1);
6723 if (isMask_64(TruncMask) &&
6724 N->getOperand(0).getOpcode() == ISD::SRL &&
6725 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6731 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6733 assert(Ty->isIntegerTy());
6735 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6739 int64_t Val = Imm.getSExtValue();
6740 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6743 if ((int64_t)Val < 0)
6746 Val &= (1LL << 32) - 1;
6748 unsigned LZ = countLeadingZeros((uint64_t)Val);
6749 unsigned Shift = (63 - LZ) / 16;
6750 // MOVZ is free so return true for one or fewer MOVK.
6751 return (Shift < 3) ? true : false;
6754 // Generate SUBS and CSEL for integer abs.
6755 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6756 EVT VT = N->getValueType(0);
6758 SDValue N0 = N->getOperand(0);
6759 SDValue N1 = N->getOperand(1);
6762 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6763 // and change it to SUB and CSEL.
6764 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6765 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6766 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6767 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6768 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6769 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6771 // Generate SUBS & CSEL.
6773 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6774 N0.getOperand(0), DAG.getConstant(0, VT));
6775 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6776 DAG.getConstant(AArch64CC::PL, MVT::i32),
6777 SDValue(Cmp.getNode(), 1));
6782 // performXorCombine - Attempts to handle integer ABS.
6783 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6784 TargetLowering::DAGCombinerInfo &DCI,
6785 const AArch64Subtarget *Subtarget) {
6786 if (DCI.isBeforeLegalizeOps())
6789 return performIntegerAbsCombine(N, DAG);
6793 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6795 std::vector<SDNode *> *Created) const {
6796 // fold (sdiv X, pow2)
6797 EVT VT = N->getValueType(0);
6798 if ((VT != MVT::i32 && VT != MVT::i64) ||
6799 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6803 SDValue N0 = N->getOperand(0);
6804 unsigned Lg2 = Divisor.countTrailingZeros();
6805 SDValue Zero = DAG.getConstant(0, VT);
6806 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6808 // Add (N0 < 0) ? Pow2 - 1 : 0;
6810 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6811 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6812 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6815 Created->push_back(Cmp.getNode());
6816 Created->push_back(Add.getNode());
6817 Created->push_back(CSel.getNode());
6822 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6824 // If we're dividing by a positive value, we're done. Otherwise, we must
6825 // negate the result.
6826 if (Divisor.isNonNegative())
6830 Created->push_back(SRA.getNode());
6831 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6834 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6835 TargetLowering::DAGCombinerInfo &DCI,
6836 const AArch64Subtarget *Subtarget) {
6837 if (DCI.isBeforeLegalizeOps())
6840 // Multiplication of a power of two plus/minus one can be done more
6841 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6842 // future CPUs have a cheaper MADD instruction, this may need to be
6843 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6844 // 64-bit is 5 cycles, so this is always a win.
6845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6846 APInt Value = C->getAPIntValue();
6847 EVT VT = N->getValueType(0);
6848 if (Value.isNonNegative()) {
6849 // (mul x, 2^N + 1) => (add (shl x, N), x)
6850 APInt VM1 = Value - 1;
6851 if (VM1.isPowerOf2()) {
6852 SDValue ShiftedVal =
6853 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6854 DAG.getConstant(VM1.logBase2(), MVT::i64));
6855 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6858 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6859 APInt VP1 = Value + 1;
6860 if (VP1.isPowerOf2()) {
6861 SDValue ShiftedVal =
6862 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6863 DAG.getConstant(VP1.logBase2(), MVT::i64));
6864 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6868 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6869 APInt VNP1 = -Value + 1;
6870 if (VNP1.isPowerOf2()) {
6871 SDValue ShiftedVal =
6872 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6873 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6874 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6877 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6878 APInt VNM1 = -Value - 1;
6879 if (VNM1.isPowerOf2()) {
6880 SDValue ShiftedVal =
6881 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6882 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6884 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6885 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6892 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6893 SelectionDAG &DAG) {
6894 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6895 // optimize away operation when it's from a constant.
6897 // The general transformation is:
6898 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6899 // AND(VECTOR_CMP(x,y), constant2)
6900 // constant2 = UNARYOP(constant)
6902 // Early exit if this isn't a vector operation, the operand of the
6903 // unary operation isn't a bitwise AND, or if the sizes of the operations
6905 EVT VT = N->getValueType(0);
6906 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6907 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6908 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6911 // Now check that the other operand of the AND is a constant. We could
6912 // make the transformation for non-constant splats as well, but it's unclear
6913 // that would be a benefit as it would not eliminate any operations, just
6914 // perform one more step in scalar code before moving to the vector unit.
6915 if (BuildVectorSDNode *BV =
6916 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6917 // Bail out if the vector isn't a constant.
6918 if (!BV->isConstant())
6921 // Everything checks out. Build up the new and improved node.
6923 EVT IntVT = BV->getValueType(0);
6924 // Create a new constant of the appropriate type for the transformed
6926 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6927 // The AND node needs bitcasts to/from an integer vector type around it.
6928 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6929 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6930 N->getOperand(0)->getOperand(0), MaskConst);
6931 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6938 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
6939 const AArch64Subtarget *Subtarget) {
6940 // First try to optimize away the conversion when it's conditionally from
6941 // a constant. Vectors only.
6942 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6943 if (Res != SDValue())
6946 EVT VT = N->getValueType(0);
6947 if (VT != MVT::f32 && VT != MVT::f64)
6950 // Only optimize when the source and destination types have the same width.
6951 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6954 // If the result of an integer load is only used by an integer-to-float
6955 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6956 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6957 SDValue N0 = N->getOperand(0);
6958 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6959 // Do not change the width of a volatile load.
6960 !cast<LoadSDNode>(N0)->isVolatile()) {
6961 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6962 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6963 LN0->getPointerInfo(), LN0->isVolatile(),
6964 LN0->isNonTemporal(), LN0->isInvariant(),
6965 LN0->getAlignment());
6967 // Make sure successors of the original load stay after it by updating them
6968 // to use the new Chain.
6969 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6972 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6973 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6979 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6980 /// searches for and classifies those shifts.
6981 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6983 if (N.getOpcode() == ISD::SHL)
6985 else if (N.getOpcode() == ISD::SRL)
6990 if (!isa<ConstantSDNode>(N.getOperand(1)))
6993 ShiftAmount = N->getConstantOperandVal(1);
6994 Src = N->getOperand(0);
6998 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6999 /// registers viewed as a high/low pair. This function looks for the pattern:
7000 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7001 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7003 static SDValue tryCombineToEXTR(SDNode *N,
7004 TargetLowering::DAGCombinerInfo &DCI) {
7005 SelectionDAG &DAG = DCI.DAG;
7007 EVT VT = N->getValueType(0);
7009 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7011 if (VT != MVT::i32 && VT != MVT::i64)
7015 uint32_t ShiftLHS = 0;
7017 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7021 uint32_t ShiftRHS = 0;
7023 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7026 // If they're both trying to come from the high part of the register, they're
7027 // not really an EXTR.
7028 if (LHSFromHi == RHSFromHi)
7031 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7035 std::swap(LHS, RHS);
7036 std::swap(ShiftLHS, ShiftRHS);
7039 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7040 DAG.getConstant(ShiftRHS, MVT::i64));
7043 static SDValue tryCombineToBSL(SDNode *N,
7044 TargetLowering::DAGCombinerInfo &DCI) {
7045 EVT VT = N->getValueType(0);
7046 SelectionDAG &DAG = DCI.DAG;
7052 SDValue N0 = N->getOperand(0);
7053 if (N0.getOpcode() != ISD::AND)
7056 SDValue N1 = N->getOperand(1);
7057 if (N1.getOpcode() != ISD::AND)
7060 // We only have to look for constant vectors here since the general, variable
7061 // case can be handled in TableGen.
7062 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7063 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7064 for (int i = 1; i >= 0; --i)
7065 for (int j = 1; j >= 0; --j) {
7066 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7067 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7071 bool FoundMatch = true;
7072 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7073 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7074 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7076 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7083 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7084 N0->getOperand(1 - i), N1->getOperand(1 - j));
7090 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7091 const AArch64Subtarget *Subtarget) {
7092 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7093 if (!EnableAArch64ExtrGeneration)
7095 SelectionDAG &DAG = DCI.DAG;
7096 EVT VT = N->getValueType(0);
7098 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7101 SDValue Res = tryCombineToEXTR(N, DCI);
7105 Res = tryCombineToBSL(N, DCI);
7112 static SDValue performBitcastCombine(SDNode *N,
7113 TargetLowering::DAGCombinerInfo &DCI,
7114 SelectionDAG &DAG) {
7115 // Wait 'til after everything is legalized to try this. That way we have
7116 // legal vector types and such.
7117 if (DCI.isBeforeLegalizeOps())
7120 // Remove extraneous bitcasts around an extract_subvector.
7122 // (v4i16 (bitconvert
7123 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7125 // (extract_subvector ((v8i16 ...), (i64 4)))
7127 // Only interested in 64-bit vectors as the ultimate result.
7128 EVT VT = N->getValueType(0);
7131 if (VT.getSimpleVT().getSizeInBits() != 64)
7133 // Is the operand an extract_subvector starting at the beginning or halfway
7134 // point of the vector? A low half may also come through as an
7135 // EXTRACT_SUBREG, so look for that, too.
7136 SDValue Op0 = N->getOperand(0);
7137 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7138 !(Op0->isMachineOpcode() &&
7139 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7141 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7142 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7143 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7145 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7146 if (idx != AArch64::dsub)
7148 // The dsub reference is equivalent to a lane zero subvector reference.
7151 // Look through the bitcast of the input to the extract.
7152 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7154 SDValue Source = Op0->getOperand(0)->getOperand(0);
7155 // If the source type has twice the number of elements as our destination
7156 // type, we know this is an extract of the high or low half of the vector.
7157 EVT SVT = Source->getValueType(0);
7158 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7161 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7163 // Create the simplified form to just extract the low or high half of the
7164 // vector directly rather than bothering with the bitcasts.
7166 unsigned NumElements = VT.getVectorNumElements();
7168 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7169 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7171 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7172 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7178 static SDValue performConcatVectorsCombine(SDNode *N,
7179 TargetLowering::DAGCombinerInfo &DCI,
7180 SelectionDAG &DAG) {
7182 EVT VT = N->getValueType(0);
7183 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7185 // Optimize concat_vectors of truncated vectors, where the intermediate
7186 // type is illegal, to avoid said illegality, e.g.,
7187 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7188 // (v2i16 (truncate (v2i64)))))
7190 // (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
7191 // (v2i32 (truncate (v2i64)))))))
7192 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7193 // on both input and result type, so we might generate worse code.
7194 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7195 if (N->getNumOperands() == 2 &&
7196 N0->getOpcode() == ISD::TRUNCATE &&
7197 N1->getOpcode() == ISD::TRUNCATE) {
7198 SDValue N00 = N0->getOperand(0);
7199 SDValue N10 = N1->getOperand(0);
7200 EVT N00VT = N00.getValueType();
7202 if (N00VT == N10.getValueType() &&
7203 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7204 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7205 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v2i32 : MVT::v4i16);
7206 #if defined(__GNUC__)
7207 #if __GNUC__ == 4 && __GNUC_MINOR__ == 7 && __GNUC_PATCHLEVEL__ == 2
7208 // FIXME: g++-4.7.2 might miscompile PerformDAGCombine().
7209 asm volatile("":::"memory");
7212 MVT ConcatMidVT = MVT::getVectorVT(MidVT.getVectorElementType(),
7213 MidVT.getVectorNumElements() * 2);
7215 ISD::TRUNCATE, dl, VT,
7216 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatMidVT,
7217 DAG.getNode(ISD::TRUNCATE, dl, MidVT, N00),
7218 DAG.getNode(ISD::TRUNCATE, dl, MidVT, N10)));
7222 // Wait 'til after everything is legalized to try this. That way we have
7223 // legal vector types and such.
7224 if (DCI.isBeforeLegalizeOps())
7227 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7228 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7229 // canonicalise to that.
7230 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7231 assert(VT.getVectorElementType().getSizeInBits() == 64);
7232 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7233 DAG.getConstant(0, MVT::i64));
7236 // Canonicalise concat_vectors so that the right-hand vector has as few
7237 // bit-casts as possible before its real operation. The primary matching
7238 // destination for these operations will be the narrowing "2" instructions,
7239 // which depend on the operation being performed on this right-hand vector.
7241 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7243 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7245 if (N1->getOpcode() != ISD::BITCAST)
7247 SDValue RHS = N1->getOperand(0);
7248 MVT RHSTy = RHS.getValueType().getSimpleVT();
7249 // If the RHS is not a vector, this is not the pattern we're looking for.
7250 if (!RHSTy.isVector())
7253 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7255 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7256 RHSTy.getVectorNumElements() * 2);
7257 return DAG.getNode(ISD::BITCAST, dl, VT,
7258 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7259 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7263 static SDValue tryCombineFixedPointConvert(SDNode *N,
7264 TargetLowering::DAGCombinerInfo &DCI,
7265 SelectionDAG &DAG) {
7266 // Wait 'til after everything is legalized to try this. That way we have
7267 // legal vector types and such.
7268 if (DCI.isBeforeLegalizeOps())
7270 // Transform a scalar conversion of a value from a lane extract into a
7271 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7272 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7273 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7275 // The second form interacts better with instruction selection and the
7276 // register allocator to avoid cross-class register copies that aren't
7277 // coalescable due to a lane reference.
7279 // Check the operand and see if it originates from a lane extract.
7280 SDValue Op1 = N->getOperand(1);
7281 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7282 // Yep, no additional predication needed. Perform the transform.
7283 SDValue IID = N->getOperand(0);
7284 SDValue Shift = N->getOperand(2);
7285 SDValue Vec = Op1.getOperand(0);
7286 SDValue Lane = Op1.getOperand(1);
7287 EVT ResTy = N->getValueType(0);
7291 // The vector width should be 128 bits by the time we get here, even
7292 // if it started as 64 bits (the extract_vector handling will have
7294 assert(Vec.getValueType().getSizeInBits() == 128 &&
7295 "unexpected vector size on extract_vector_elt!");
7296 if (Vec.getValueType() == MVT::v4i32)
7297 VecResTy = MVT::v4f32;
7298 else if (Vec.getValueType() == MVT::v2i64)
7299 VecResTy = MVT::v2f64;
7301 llvm_unreachable("unexpected vector type!");
7304 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7305 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7310 // AArch64 high-vector "long" operations are formed by performing the non-high
7311 // version on an extract_subvector of each operand which gets the high half:
7313 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7315 // However, there are cases which don't have an extract_high explicitly, but
7316 // have another operation that can be made compatible with one for free. For
7319 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7321 // This routine does the actual conversion of such DUPs, once outer routines
7322 // have determined that everything else is in order.
7323 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7324 // We can handle most types of duplicate, but the lane ones have an extra
7325 // operand saying *which* lane, so we need to know.
7327 switch (N.getOpcode()) {
7328 case AArch64ISD::DUP:
7331 case AArch64ISD::DUPLANE8:
7332 case AArch64ISD::DUPLANE16:
7333 case AArch64ISD::DUPLANE32:
7334 case AArch64ISD::DUPLANE64:
7341 MVT NarrowTy = N.getSimpleValueType();
7342 if (!NarrowTy.is64BitVector())
7345 MVT ElementTy = NarrowTy.getVectorElementType();
7346 unsigned NumElems = NarrowTy.getVectorNumElements();
7347 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7351 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7354 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7356 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7357 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7360 static bool isEssentiallyExtractSubvector(SDValue N) {
7361 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7364 return N.getOpcode() == ISD::BITCAST &&
7365 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7368 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7369 struct GenericSetCCInfo {
7370 const SDValue *Opnd0;
7371 const SDValue *Opnd1;
7375 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7376 struct AArch64SetCCInfo {
7378 AArch64CC::CondCode CC;
7381 /// \brief Helper structure to keep track of SetCC information.
7383 GenericSetCCInfo Generic;
7384 AArch64SetCCInfo AArch64;
7387 /// \brief Helper structure to be able to read SetCC information. If set to
7388 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7389 /// GenericSetCCInfo.
7390 struct SetCCInfoAndKind {
7395 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7397 /// AArch64 lowered one.
7398 /// \p SetCCInfo is filled accordingly.
7399 /// \post SetCCInfo is meanginfull only when this function returns true.
7400 /// \return True when Op is a kind of SET_CC operation.
7401 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7402 // If this is a setcc, this is straight forward.
7403 if (Op.getOpcode() == ISD::SETCC) {
7404 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7405 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7406 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7407 SetCCInfo.IsAArch64 = false;
7410 // Otherwise, check if this is a matching csel instruction.
7414 if (Op.getOpcode() != AArch64ISD::CSEL)
7416 // Set the information about the operands.
7417 // TODO: we want the operands of the Cmp not the csel
7418 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7419 SetCCInfo.IsAArch64 = true;
7420 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7421 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7423 // Check that the operands matches the constraints:
7424 // (1) Both operands must be constants.
7425 // (2) One must be 1 and the other must be 0.
7426 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7427 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7430 if (!TValue || !FValue)
7434 if (!TValue->isOne()) {
7435 // Update the comparison when we are interested in !cc.
7436 std::swap(TValue, FValue);
7437 SetCCInfo.Info.AArch64.CC =
7438 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7440 return TValue->isOne() && FValue->isNullValue();
7443 // Returns true if Op is setcc or zext of setcc.
7444 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7445 if (isSetCC(Op, Info))
7447 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7448 isSetCC(Op->getOperand(0), Info));
7451 // The folding we want to perform is:
7452 // (add x, [zext] (setcc cc ...) )
7454 // (csel x, (add x, 1), !cc ...)
7456 // The latter will get matched to a CSINC instruction.
7457 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7458 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7459 SDValue LHS = Op->getOperand(0);
7460 SDValue RHS = Op->getOperand(1);
7461 SetCCInfoAndKind InfoAndKind;
7463 // If neither operand is a SET_CC, give up.
7464 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7465 std::swap(LHS, RHS);
7466 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7470 // FIXME: This could be generatized to work for FP comparisons.
7471 EVT CmpVT = InfoAndKind.IsAArch64
7472 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7473 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7474 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7480 if (InfoAndKind.IsAArch64) {
7481 CCVal = DAG.getConstant(
7482 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7483 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7485 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7486 *InfoAndKind.Info.Generic.Opnd1,
7487 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7490 EVT VT = Op->getValueType(0);
7491 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7492 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7495 // The basic add/sub long vector instructions have variants with "2" on the end
7496 // which act on the high-half of their inputs. They are normally matched by
7499 // (add (zeroext (extract_high LHS)),
7500 // (zeroext (extract_high RHS)))
7501 // -> uaddl2 vD, vN, vM
7503 // However, if one of the extracts is something like a duplicate, this
7504 // instruction can still be used profitably. This function puts the DAG into a
7505 // more appropriate form for those patterns to trigger.
7506 static SDValue performAddSubLongCombine(SDNode *N,
7507 TargetLowering::DAGCombinerInfo &DCI,
7508 SelectionDAG &DAG) {
7509 if (DCI.isBeforeLegalizeOps())
7512 MVT VT = N->getSimpleValueType(0);
7513 if (!VT.is128BitVector()) {
7514 if (N->getOpcode() == ISD::ADD)
7515 return performSetccAddFolding(N, DAG);
7519 // Make sure both branches are extended in the same way.
7520 SDValue LHS = N->getOperand(0);
7521 SDValue RHS = N->getOperand(1);
7522 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7523 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7524 LHS.getOpcode() != RHS.getOpcode())
7527 unsigned ExtType = LHS.getOpcode();
7529 // It's not worth doing if at least one of the inputs isn't already an
7530 // extract, but we don't know which it'll be so we have to try both.
7531 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7532 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7536 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7537 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7538 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7542 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7545 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7548 // Massage DAGs which we can use the high-half "long" operations on into
7549 // something isel will recognize better. E.g.
7551 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7552 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7553 // (extract_high (v2i64 (dup128 scalar)))))
7555 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7556 TargetLowering::DAGCombinerInfo &DCI,
7557 SelectionDAG &DAG) {
7558 if (DCI.isBeforeLegalizeOps())
7561 SDValue LHS = N->getOperand(1);
7562 SDValue RHS = N->getOperand(2);
7563 assert(LHS.getValueType().is64BitVector() &&
7564 RHS.getValueType().is64BitVector() &&
7565 "unexpected shape for long operation");
7567 // Either node could be a DUP, but it's not worth doing both of them (you'd
7568 // just as well use the non-high version) so look for a corresponding extract
7569 // operation on the other "wing".
7570 if (isEssentiallyExtractSubvector(LHS)) {
7571 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7574 } else if (isEssentiallyExtractSubvector(RHS)) {
7575 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7580 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7581 N->getOperand(0), LHS, RHS);
7584 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7585 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7586 unsigned ElemBits = ElemTy.getSizeInBits();
7588 int64_t ShiftAmount;
7589 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7590 APInt SplatValue, SplatUndef;
7591 unsigned SplatBitSize;
7593 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7594 HasAnyUndefs, ElemBits) ||
7595 SplatBitSize != ElemBits)
7598 ShiftAmount = SplatValue.getSExtValue();
7599 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7600 ShiftAmount = CVN->getSExtValue();
7608 llvm_unreachable("Unknown shift intrinsic");
7609 case Intrinsic::aarch64_neon_sqshl:
7610 Opcode = AArch64ISD::SQSHL_I;
7611 IsRightShift = false;
7613 case Intrinsic::aarch64_neon_uqshl:
7614 Opcode = AArch64ISD::UQSHL_I;
7615 IsRightShift = false;
7617 case Intrinsic::aarch64_neon_srshl:
7618 Opcode = AArch64ISD::SRSHR_I;
7619 IsRightShift = true;
7621 case Intrinsic::aarch64_neon_urshl:
7622 Opcode = AArch64ISD::URSHR_I;
7623 IsRightShift = true;
7625 case Intrinsic::aarch64_neon_sqshlu:
7626 Opcode = AArch64ISD::SQSHLU_I;
7627 IsRightShift = false;
7631 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7632 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7633 DAG.getConstant(-ShiftAmount, MVT::i32));
7634 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7635 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7636 DAG.getConstant(ShiftAmount, MVT::i32));
7641 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7642 // the intrinsics must be legal and take an i32, this means there's almost
7643 // certainly going to be a zext in the DAG which we can eliminate.
7644 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7645 SDValue AndN = N->getOperand(2);
7646 if (AndN.getOpcode() != ISD::AND)
7649 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7650 if (!CMask || CMask->getZExtValue() != Mask)
7653 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7654 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7657 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7658 SelectionDAG &DAG) {
7659 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
7660 DAG.getNode(Opc, SDLoc(N),
7661 N->getOperand(1).getSimpleValueType(),
7663 DAG.getConstant(0, MVT::i64));
7666 static SDValue performIntrinsicCombine(SDNode *N,
7667 TargetLowering::DAGCombinerInfo &DCI,
7668 const AArch64Subtarget *Subtarget) {
7669 SelectionDAG &DAG = DCI.DAG;
7670 unsigned IID = getIntrinsicID(N);
7674 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7675 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7676 return tryCombineFixedPointConvert(N, DCI, DAG);
7678 case Intrinsic::aarch64_neon_saddv:
7679 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7680 case Intrinsic::aarch64_neon_uaddv:
7681 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7682 case Intrinsic::aarch64_neon_sminv:
7683 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7684 case Intrinsic::aarch64_neon_uminv:
7685 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7686 case Intrinsic::aarch64_neon_smaxv:
7687 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7688 case Intrinsic::aarch64_neon_umaxv:
7689 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7690 case Intrinsic::aarch64_neon_fmax:
7691 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7692 N->getOperand(1), N->getOperand(2));
7693 case Intrinsic::aarch64_neon_fmin:
7694 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7695 N->getOperand(1), N->getOperand(2));
7696 case Intrinsic::aarch64_neon_smull:
7697 case Intrinsic::aarch64_neon_umull:
7698 case Intrinsic::aarch64_neon_pmull:
7699 case Intrinsic::aarch64_neon_sqdmull:
7700 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7701 case Intrinsic::aarch64_neon_sqshl:
7702 case Intrinsic::aarch64_neon_uqshl:
7703 case Intrinsic::aarch64_neon_sqshlu:
7704 case Intrinsic::aarch64_neon_srshl:
7705 case Intrinsic::aarch64_neon_urshl:
7706 return tryCombineShiftImm(IID, N, DAG);
7707 case Intrinsic::aarch64_crc32b:
7708 case Intrinsic::aarch64_crc32cb:
7709 return tryCombineCRC32(0xff, N, DAG);
7710 case Intrinsic::aarch64_crc32h:
7711 case Intrinsic::aarch64_crc32ch:
7712 return tryCombineCRC32(0xffff, N, DAG);
7717 static SDValue performExtendCombine(SDNode *N,
7718 TargetLowering::DAGCombinerInfo &DCI,
7719 SelectionDAG &DAG) {
7720 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7721 // we can convert that DUP into another extract_high (of a bigger DUP), which
7722 // helps the backend to decide that an sabdl2 would be useful, saving a real
7723 // extract_high operation.
7724 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7725 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7726 SDNode *ABDNode = N->getOperand(0).getNode();
7727 unsigned IID = getIntrinsicID(ABDNode);
7728 if (IID == Intrinsic::aarch64_neon_sabd ||
7729 IID == Intrinsic::aarch64_neon_uabd) {
7730 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7731 if (!NewABD.getNode())
7734 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7739 // This is effectively a custom type legalization for AArch64.
7741 // Type legalization will split an extend of a small, legal, type to a larger
7742 // illegal type by first splitting the destination type, often creating
7743 // illegal source types, which then get legalized in isel-confusing ways,
7744 // leading to really terrible codegen. E.g.,
7745 // %result = v8i32 sext v8i8 %value
7747 // %losrc = extract_subreg %value, ...
7748 // %hisrc = extract_subreg %value, ...
7749 // %lo = v4i32 sext v4i8 %losrc
7750 // %hi = v4i32 sext v4i8 %hisrc
7751 // Things go rapidly downhill from there.
7753 // For AArch64, the [sz]ext vector instructions can only go up one element
7754 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7755 // take two instructions.
7757 // This implies that the most efficient way to do the extend from v8i8
7758 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7759 // the normal splitting to happen for the v8i16->v8i32.
7761 // This is pre-legalization to catch some cases where the default
7762 // type legalization will create ill-tempered code.
7763 if (!DCI.isBeforeLegalizeOps())
7766 // We're only interested in cleaning things up for non-legal vector types
7767 // here. If both the source and destination are legal, things will just
7768 // work naturally without any fiddling.
7769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7770 EVT ResVT = N->getValueType(0);
7771 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7773 // If the vector type isn't a simple VT, it's beyond the scope of what
7774 // we're worried about here. Let legalization do its thing and hope for
7776 SDValue Src = N->getOperand(0);
7777 EVT SrcVT = Src->getValueType(0);
7778 if (!ResVT.isSimple() || !SrcVT.isSimple())
7781 // If the source VT is a 64-bit vector, we can play games and get the
7782 // better results we want.
7783 if (SrcVT.getSizeInBits() != 64)
7786 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7787 unsigned ElementCount = SrcVT.getVectorNumElements();
7788 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7790 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7792 // Now split the rest of the operation into two halves, each with a 64
7796 unsigned NumElements = ResVT.getVectorNumElements();
7797 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7798 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7799 ResVT.getVectorElementType(), NumElements / 2);
7801 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7802 LoVT.getVectorNumElements());
7803 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7804 DAG.getConstant(0, MVT::i64));
7805 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7806 DAG.getConstant(InNVT.getVectorNumElements(), MVT::i64));
7807 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7808 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7810 // Now combine the parts back together so we still have a single result
7811 // like the combiner expects.
7812 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7815 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7816 /// value. The load store optimizer pass will merge them to store pair stores.
7817 /// This has better performance than a splat of the scalar followed by a split
7818 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7819 /// followed by an ext.b and two stores.
7820 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7821 SDValue StVal = St->getValue();
7822 EVT VT = StVal.getValueType();
7824 // Don't replace floating point stores, they possibly won't be transformed to
7825 // stp because of the store pair suppress pass.
7826 if (VT.isFloatingPoint())
7829 // Check for insert vector elements.
7830 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7833 // We can express a splat as store pair(s) for 2 or 4 elements.
7834 unsigned NumVecElts = VT.getVectorNumElements();
7835 if (NumVecElts != 4 && NumVecElts != 2)
7837 SDValue SplatVal = StVal.getOperand(1);
7838 unsigned RemainInsertElts = NumVecElts - 1;
7840 // Check that this is a splat.
7841 while (--RemainInsertElts) {
7842 SDValue NextInsertElt = StVal.getOperand(0);
7843 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7845 if (NextInsertElt.getOperand(1) != SplatVal)
7847 StVal = NextInsertElt;
7849 unsigned OrigAlignment = St->getAlignment();
7850 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7851 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7853 // Create scalar stores. This is at least as good as the code sequence for a
7854 // split unaligned store wich is a dup.s, ext.b, and two stores.
7855 // Most of the time the three stores should be replaced by store pair
7856 // instructions (stp).
7858 SDValue BasePtr = St->getBasePtr();
7860 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7861 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7863 unsigned Offset = EltOffset;
7864 while (--NumVecElts) {
7865 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7866 DAG.getConstant(Offset, MVT::i64));
7867 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7868 St->getPointerInfo(), St->isVolatile(),
7869 St->isNonTemporal(), Alignment);
7870 Offset += EltOffset;
7875 static SDValue performSTORECombine(SDNode *N,
7876 TargetLowering::DAGCombinerInfo &DCI,
7878 const AArch64Subtarget *Subtarget) {
7879 if (!DCI.isBeforeLegalize())
7882 StoreSDNode *S = cast<StoreSDNode>(N);
7883 if (S->isVolatile())
7886 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7887 // page boundaries. We want to split such stores.
7888 if (!Subtarget->isCyclone())
7891 // Don't split at Oz.
7892 MachineFunction &MF = DAG.getMachineFunction();
7893 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
7897 SDValue StVal = S->getValue();
7898 EVT VT = StVal.getValueType();
7900 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7901 // those up regresses performance on micro-benchmarks and olden/bh.
7902 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7905 // Split unaligned 16B stores. They are terrible for performance.
7906 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7907 // extensions can use this to mark that it does not want splitting to happen
7908 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7909 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7910 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7911 S->getAlignment() <= 2)
7914 // If we get a splat of a scalar convert this vector store to a store of
7915 // scalars. They will be merged into store pairs thereby removing two
7917 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7918 if (ReplacedSplat != SDValue())
7919 return ReplacedSplat;
7922 unsigned NumElts = VT.getVectorNumElements() / 2;
7923 // Split VT into two.
7925 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7926 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7927 DAG.getConstant(0, MVT::i64));
7928 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7929 DAG.getConstant(NumElts, MVT::i64));
7930 SDValue BasePtr = S->getBasePtr();
7932 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7933 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7934 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7935 DAG.getConstant(8, MVT::i64));
7936 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7937 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7941 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7942 /// post-increment LD1R.
7943 static SDValue performPostLD1Combine(SDNode *N,
7944 TargetLowering::DAGCombinerInfo &DCI,
7946 if (DCI.isBeforeLegalizeOps())
7949 SelectionDAG &DAG = DCI.DAG;
7950 EVT VT = N->getValueType(0);
7952 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7953 SDNode *LD = N->getOperand(LoadIdx).getNode();
7954 // If it is not LOAD, can not do such combine.
7955 if (LD->getOpcode() != ISD::LOAD)
7958 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7959 EVT MemVT = LoadSDN->getMemoryVT();
7960 // Check if memory operand is the same type as the vector element.
7961 if (MemVT != VT.getVectorElementType())
7964 // Check if there are other uses. If so, do not combine as it will introduce
7966 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7968 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7974 SDValue Addr = LD->getOperand(1);
7975 SDValue Vector = N->getOperand(0);
7976 // Search for a use of the address operand that is an increment.
7977 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7978 Addr.getNode()->use_end(); UI != UE; ++UI) {
7980 if (User->getOpcode() != ISD::ADD
7981 || UI.getUse().getResNo() != Addr.getResNo())
7984 // Check that the add is independent of the load. Otherwise, folding it
7985 // would create a cycle.
7986 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7988 // Also check that add is not used in the vector operand. This would also
7990 if (User->isPredecessorOf(Vector.getNode()))
7993 // If the increment is a constant, it must match the memory ref size.
7994 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7995 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7996 uint32_t IncVal = CInc->getZExtValue();
7997 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7998 if (IncVal != NumBytes)
8000 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8003 SmallVector<SDValue, 8> Ops;
8004 Ops.push_back(LD->getOperand(0)); // Chain
8006 Ops.push_back(Vector); // The vector to be inserted
8007 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8009 Ops.push_back(Addr);
8012 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8013 SDVTList SDTys = DAG.getVTList(Tys);
8014 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8015 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8017 LoadSDN->getMemOperand());
8020 SmallVector<SDValue, 2> NewResults;
8021 NewResults.push_back(SDValue(LD, 0)); // The result of load
8022 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8023 DCI.CombineTo(LD, NewResults);
8024 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8025 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8032 /// Target-specific DAG combine function for NEON load/store intrinsics
8033 /// to merge base address updates.
8034 static SDValue performNEONPostLDSTCombine(SDNode *N,
8035 TargetLowering::DAGCombinerInfo &DCI,
8036 SelectionDAG &DAG) {
8037 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8040 unsigned AddrOpIdx = N->getNumOperands() - 1;
8041 SDValue Addr = N->getOperand(AddrOpIdx);
8043 // Search for a use of the address operand that is an increment.
8044 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8045 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8047 if (User->getOpcode() != ISD::ADD ||
8048 UI.getUse().getResNo() != Addr.getResNo())
8051 // Check that the add is independent of the load/store. Otherwise, folding
8052 // it would create a cycle.
8053 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8056 // Find the new opcode for the updating load/store.
8057 bool IsStore = false;
8058 bool IsLaneOp = false;
8059 bool IsDupOp = false;
8060 unsigned NewOpc = 0;
8061 unsigned NumVecs = 0;
8062 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8064 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8065 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8067 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8069 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8071 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8072 NumVecs = 2; IsStore = true; break;
8073 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8074 NumVecs = 3; IsStore = true; break;
8075 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8076 NumVecs = 4; IsStore = true; break;
8077 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8079 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8081 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8083 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8084 NumVecs = 2; IsStore = true; break;
8085 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8086 NumVecs = 3; IsStore = true; break;
8087 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8088 NumVecs = 4; IsStore = true; break;
8089 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8090 NumVecs = 2; IsDupOp = true; break;
8091 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8092 NumVecs = 3; IsDupOp = true; break;
8093 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8094 NumVecs = 4; IsDupOp = true; break;
8095 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8096 NumVecs = 2; IsLaneOp = true; break;
8097 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8098 NumVecs = 3; IsLaneOp = true; break;
8099 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8100 NumVecs = 4; IsLaneOp = true; break;
8101 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8102 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8103 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8104 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8105 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8106 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8111 VecTy = N->getOperand(2).getValueType();
8113 VecTy = N->getValueType(0);
8115 // If the increment is a constant, it must match the memory ref size.
8116 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8117 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8118 uint32_t IncVal = CInc->getZExtValue();
8119 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8120 if (IsLaneOp || IsDupOp)
8121 NumBytes /= VecTy.getVectorNumElements();
8122 if (IncVal != NumBytes)
8124 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8126 SmallVector<SDValue, 8> Ops;
8127 Ops.push_back(N->getOperand(0)); // Incoming chain
8128 // Load lane and store have vector list as input.
8129 if (IsLaneOp || IsStore)
8130 for (unsigned i = 2; i < AddrOpIdx; ++i)
8131 Ops.push_back(N->getOperand(i));
8132 Ops.push_back(Addr); // Base register
8137 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8139 for (n = 0; n < NumResultVecs; ++n)
8141 Tys[n++] = MVT::i64; // Type of write back register
8142 Tys[n] = MVT::Other; // Type of the chain
8143 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8145 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8146 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8147 MemInt->getMemoryVT(),
8148 MemInt->getMemOperand());
8151 std::vector<SDValue> NewResults;
8152 for (unsigned i = 0; i < NumResultVecs; ++i) {
8153 NewResults.push_back(SDValue(UpdN.getNode(), i));
8155 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8156 DCI.CombineTo(N, NewResults);
8157 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8164 // Checks to see if the value is the prescribed width and returns information
8165 // about its extension mode.
8167 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8168 ExtType = ISD::NON_EXTLOAD;
8169 switch(V.getNode()->getOpcode()) {
8173 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8174 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8175 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8176 ExtType = LoadNode->getExtensionType();
8181 case ISD::AssertSext: {
8182 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8183 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8184 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8185 ExtType = ISD::SEXTLOAD;
8190 case ISD::AssertZext: {
8191 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8192 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8193 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8194 ExtType = ISD::ZEXTLOAD;
8200 case ISD::TargetConstant: {
8201 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8211 // This function does a whole lot of voodoo to determine if the tests are
8212 // equivalent without and with a mask. Essentially what happens is that given a
8215 // +-------------+ +-------------+ +-------------+ +-------------+
8216 // | Input | | AddConstant | | CompConstant| | CC |
8217 // +-------------+ +-------------+ +-------------+ +-------------+
8219 // V V | +----------+
8220 // +-------------+ +----+ | |
8221 // | ADD | |0xff| | |
8222 // +-------------+ +----+ | |
8225 // +-------------+ | |
8227 // +-------------+ | |
8236 // The AND node may be safely removed for some combinations of inputs. In
8237 // particular we need to take into account the extension type of the Input,
8238 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8239 // width of the input (this can work for any width inputs, the above graph is
8240 // specific to 8 bits.
8242 // The specific equations were worked out by generating output tables for each
8243 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8244 // problem was simplified by working with 4 bit inputs, which means we only
8245 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8246 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8247 // patterns present in both extensions (0,7). For every distinct set of
8248 // AddConstant and CompConstants bit patterns we can consider the masked and
8249 // unmasked versions to be equivalent if the result of this function is true for
8250 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8253 // and w10, w8, #0x0f
8255 // cset w9, AArch64CC
8257 // cset w11, AArch64CC
8262 // Since the above function shows when the outputs are equivalent it defines
8263 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8264 // would be expensive to run during compiles. The equations below were written
8265 // in a test harness that confirmed they gave equivalent outputs to the above
8266 // for all inputs function, so they can be used determine if the removal is
8269 // isEquivalentMaskless() is the code for testing if the AND can be removed
8270 // factored out of the DAG recognition as the DAG can take several forms.
8273 bool isEquivalentMaskless(unsigned CC, unsigned width,
8274 ISD::LoadExtType ExtType, signed AddConstant,
8275 signed CompConstant) {
8276 // By being careful about our equations and only writing the in term
8277 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8278 // make them generally applicable to all bit widths.
8279 signed MaxUInt = (1 << width);
8281 // For the purposes of these comparisons sign extending the type is
8282 // equivalent to zero extending the add and displacing it by half the integer
8283 // width. Provided we are careful and make sure our equations are valid over
8284 // the whole range we can just adjust the input and avoid writing equations
8285 // for sign extended inputs.
8286 if (ExtType == ISD::SEXTLOAD)
8287 AddConstant -= (1 << (width-1));
8291 case AArch64CC::GT: {
8292 if ((AddConstant == 0) ||
8293 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8294 (AddConstant >= 0 && CompConstant < 0) ||
8295 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8299 case AArch64CC::GE: {
8300 if ((AddConstant == 0) ||
8301 (AddConstant >= 0 && CompConstant <= 0) ||
8302 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8306 case AArch64CC::LS: {
8307 if ((AddConstant >= 0 && CompConstant < 0) ||
8308 (AddConstant <= 0 && CompConstant >= -1 &&
8309 CompConstant < AddConstant + MaxUInt))
8313 case AArch64CC::MI: {
8314 if ((AddConstant == 0) ||
8315 (AddConstant > 0 && CompConstant <= 0) ||
8316 (AddConstant < 0 && CompConstant <= AddConstant))
8320 case AArch64CC::HS: {
8321 if ((AddConstant >= 0 && CompConstant <= 0) ||
8322 (AddConstant <= 0 && CompConstant >= 0 &&
8323 CompConstant <= AddConstant + MaxUInt))
8327 case AArch64CC::NE: {
8328 if ((AddConstant > 0 && CompConstant < 0) ||
8329 (AddConstant < 0 && CompConstant >= 0 &&
8330 CompConstant < AddConstant + MaxUInt) ||
8331 (AddConstant >= 0 && CompConstant >= 0 &&
8332 CompConstant >= AddConstant) ||
8333 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8342 case AArch64CC::Invalid:
8350 SDValue performCONDCombine(SDNode *N,
8351 TargetLowering::DAGCombinerInfo &DCI,
8352 SelectionDAG &DAG, unsigned CCIndex,
8353 unsigned CmpIndex) {
8354 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8355 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8356 unsigned CondOpcode = SubsNode->getOpcode();
8358 if (CondOpcode != AArch64ISD::SUBS)
8361 // There is a SUBS feeding this condition. Is it fed by a mask we can
8364 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8365 unsigned MaskBits = 0;
8367 if (AndNode->getOpcode() != ISD::AND)
8370 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8371 uint32_t CNV = CN->getZExtValue();
8374 else if (CNV == 65535)
8381 SDValue AddValue = AndNode->getOperand(0);
8383 if (AddValue.getOpcode() != ISD::ADD)
8386 // The basic dag structure is correct, grab the inputs and validate them.
8388 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8389 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8390 SDValue SubsInputValue = SubsNode->getOperand(1);
8392 // The mask is present and the provenance of all the values is a smaller type,
8393 // lets see if the mask is superfluous.
8395 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8396 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8399 ISD::LoadExtType ExtType;
8401 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8402 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8403 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8406 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8407 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8408 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8411 // The AND is not necessary, remove it.
8413 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8414 SubsNode->getValueType(1));
8415 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8417 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8418 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8420 return SDValue(N, 0);
8423 // Optimize compare with zero and branch.
8424 static SDValue performBRCONDCombine(SDNode *N,
8425 TargetLowering::DAGCombinerInfo &DCI,
8426 SelectionDAG &DAG) {
8427 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8430 SDValue Chain = N->getOperand(0);
8431 SDValue Dest = N->getOperand(1);
8432 SDValue CCVal = N->getOperand(2);
8433 SDValue Cmp = N->getOperand(3);
8435 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8436 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8437 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8440 unsigned CmpOpc = Cmp.getOpcode();
8441 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8444 // Only attempt folding if there is only one use of the flag and no use of the
8446 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8449 SDValue LHS = Cmp.getOperand(0);
8450 SDValue RHS = Cmp.getOperand(1);
8452 assert(LHS.getValueType() == RHS.getValueType() &&
8453 "Expected the value type to be the same for both operands!");
8454 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8457 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8458 std::swap(LHS, RHS);
8460 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8463 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8464 LHS.getOpcode() == ISD::SRL)
8467 // Fold the compare into the branch instruction.
8469 if (CC == AArch64CC::EQ)
8470 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8472 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8474 // Do not add new nodes to DAG combiner worklist.
8475 DCI.CombineTo(N, BR, false);
8480 // vselect (v1i1 setcc) ->
8481 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8482 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8483 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8485 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8486 SDValue N0 = N->getOperand(0);
8487 EVT CCVT = N0.getValueType();
8489 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8490 CCVT.getVectorElementType() != MVT::i1)
8493 EVT ResVT = N->getValueType(0);
8494 EVT CmpVT = N0.getOperand(0).getValueType();
8495 // Only combine when the result type is of the same size as the compared
8497 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8500 SDValue IfTrue = N->getOperand(1);
8501 SDValue IfFalse = N->getOperand(2);
8503 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8504 N0.getOperand(0), N0.getOperand(1),
8505 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8506 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8510 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8511 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8512 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8513 /// with a vector one followed by a DUP shuffle on the result.
8514 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8515 SDValue N0 = N->getOperand(0);
8516 EVT ResVT = N->getValueType(0);
8518 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8521 // If NumMaskElts == 0, the comparison is larger than select result. The
8522 // largest real NEON comparison is 64-bits per lane, which means the result is
8523 // at most 32-bits and an illegal vector. Just bail out for now.
8524 EVT SrcVT = N0.getOperand(0).getValueType();
8526 // Don't try to do this optimization when the setcc itself has i1 operands.
8527 // There are no legal vectors of i1, so this would be pointless.
8528 if (SrcVT == MVT::i1)
8531 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8532 if (!ResVT.isVector() || NumMaskElts == 0)
8535 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8536 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8538 // First perform a vector comparison, where lane 0 is the one we're interested
8542 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8544 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8545 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8547 // Now duplicate the comparison mask we want across all other lanes.
8548 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8549 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8550 Mask = DAG.getNode(ISD::BITCAST, DL,
8551 ResVT.changeVectorElementTypeToInteger(), Mask);
8553 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8556 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8557 DAGCombinerInfo &DCI) const {
8558 SelectionDAG &DAG = DCI.DAG;
8559 switch (N->getOpcode()) {
8564 return performAddSubLongCombine(N, DCI, DAG);
8566 return performXorCombine(N, DAG, DCI, Subtarget);
8568 return performMulCombine(N, DAG, DCI, Subtarget);
8569 case ISD::SINT_TO_FP:
8570 case ISD::UINT_TO_FP:
8571 return performIntToFpCombine(N, DAG, Subtarget);
8573 return performORCombine(N, DCI, Subtarget);
8574 case ISD::INTRINSIC_WO_CHAIN:
8575 return performIntrinsicCombine(N, DCI, Subtarget);
8576 case ISD::ANY_EXTEND:
8577 case ISD::ZERO_EXTEND:
8578 case ISD::SIGN_EXTEND:
8579 return performExtendCombine(N, DCI, DAG);
8581 return performBitcastCombine(N, DCI, DAG);
8582 case ISD::CONCAT_VECTORS:
8583 return performConcatVectorsCombine(N, DCI, DAG);
8585 return performSelectCombine(N, DAG);
8587 return performVSelectCombine(N, DCI.DAG);
8589 return performSTORECombine(N, DCI, DAG, Subtarget);
8590 case AArch64ISD::BRCOND:
8591 return performBRCONDCombine(N, DCI, DAG);
8592 case AArch64ISD::CSEL:
8593 return performCONDCombine(N, DCI, DAG, 2, 3);
8594 case AArch64ISD::DUP:
8595 return performPostLD1Combine(N, DCI, false);
8596 case ISD::INSERT_VECTOR_ELT:
8597 return performPostLD1Combine(N, DCI, true);
8598 case ISD::INTRINSIC_VOID:
8599 case ISD::INTRINSIC_W_CHAIN:
8600 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8601 case Intrinsic::aarch64_neon_ld2:
8602 case Intrinsic::aarch64_neon_ld3:
8603 case Intrinsic::aarch64_neon_ld4:
8604 case Intrinsic::aarch64_neon_ld1x2:
8605 case Intrinsic::aarch64_neon_ld1x3:
8606 case Intrinsic::aarch64_neon_ld1x4:
8607 case Intrinsic::aarch64_neon_ld2lane:
8608 case Intrinsic::aarch64_neon_ld3lane:
8609 case Intrinsic::aarch64_neon_ld4lane:
8610 case Intrinsic::aarch64_neon_ld2r:
8611 case Intrinsic::aarch64_neon_ld3r:
8612 case Intrinsic::aarch64_neon_ld4r:
8613 case Intrinsic::aarch64_neon_st2:
8614 case Intrinsic::aarch64_neon_st3:
8615 case Intrinsic::aarch64_neon_st4:
8616 case Intrinsic::aarch64_neon_st1x2:
8617 case Intrinsic::aarch64_neon_st1x3:
8618 case Intrinsic::aarch64_neon_st1x4:
8619 case Intrinsic::aarch64_neon_st2lane:
8620 case Intrinsic::aarch64_neon_st3lane:
8621 case Intrinsic::aarch64_neon_st4lane:
8622 return performNEONPostLDSTCombine(N, DCI, DAG);
8630 // Check if the return value is used as only a return value, as otherwise
8631 // we can't perform a tail-call. In particular, we need to check for
8632 // target ISD nodes that are returns and any other "odd" constructs
8633 // that the generic analysis code won't necessarily catch.
8634 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8635 SDValue &Chain) const {
8636 if (N->getNumValues() != 1)
8638 if (!N->hasNUsesOfValue(1, 0))
8641 SDValue TCChain = Chain;
8642 SDNode *Copy = *N->use_begin();
8643 if (Copy->getOpcode() == ISD::CopyToReg) {
8644 // If the copy has a glue operand, we conservatively assume it isn't safe to
8645 // perform a tail call.
8646 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8649 TCChain = Copy->getOperand(0);
8650 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8653 bool HasRet = false;
8654 for (SDNode *Node : Copy->uses()) {
8655 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8667 // Return whether the an instruction can potentially be optimized to a tail
8668 // call. This will cause the optimizers to attempt to move, or duplicate,
8669 // return instructions to help enable tail call optimizations for this
8671 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8672 if (!CI->isTailCall())
8678 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8680 ISD::MemIndexedMode &AM,
8682 SelectionDAG &DAG) const {
8683 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8686 Base = Op->getOperand(0);
8687 // All of the indexed addressing mode instructions take a signed
8688 // 9 bit immediate offset.
8689 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8690 int64_t RHSC = (int64_t)RHS->getZExtValue();
8691 if (RHSC >= 256 || RHSC <= -256)
8693 IsInc = (Op->getOpcode() == ISD::ADD);
8694 Offset = Op->getOperand(1);
8700 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8702 ISD::MemIndexedMode &AM,
8703 SelectionDAG &DAG) const {
8706 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8707 VT = LD->getMemoryVT();
8708 Ptr = LD->getBasePtr();
8709 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8710 VT = ST->getMemoryVT();
8711 Ptr = ST->getBasePtr();
8716 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8718 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8722 bool AArch64TargetLowering::getPostIndexedAddressParts(
8723 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8724 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8727 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8728 VT = LD->getMemoryVT();
8729 Ptr = LD->getBasePtr();
8730 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8731 VT = ST->getMemoryVT();
8732 Ptr = ST->getBasePtr();
8737 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8739 // Post-indexing updates the base, so it's not a valid transform
8740 // if that's not the same as the load's pointer.
8743 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8747 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8748 SelectionDAG &DAG) {
8750 SDValue Op = N->getOperand(0);
8752 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8756 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8757 DAG.getUNDEF(MVT::i32), Op,
8758 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8760 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8761 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8764 void AArch64TargetLowering::ReplaceNodeResults(
8765 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8766 switch (N->getOpcode()) {
8768 llvm_unreachable("Don't know how to custom expand this");
8770 ReplaceBITCASTResults(N, Results, DAG);
8772 case ISD::FP_TO_UINT:
8773 case ISD::FP_TO_SINT:
8774 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8775 // Let normal code take care of it by not adding anything to Results.
8780 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8784 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8785 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8786 // reciprocal if there are three or more FDIVs.
8787 return NumUsers > 2;
8790 TargetLoweringBase::LegalizeTypeAction
8791 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8792 MVT SVT = VT.getSimpleVT();
8793 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8794 // v4i16, v2i32 instead of to promote.
8795 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8796 || SVT == MVT::v1f32)
8797 return TypeWidenVector;
8799 return TargetLoweringBase::getPreferredVectorAction(VT);
8802 // Loads and stores less than 128-bits are already atomic; ones above that
8803 // are doomed anyway, so defer to the default libcall and blame the OS when
8805 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8806 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8810 // Loads and stores less than 128-bits are already atomic; ones above that
8811 // are doomed anyway, so defer to the default libcall and blame the OS when
8813 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8814 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8818 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8819 TargetLoweringBase::AtomicRMWExpansionKind
8820 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8821 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8822 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
8823 : AtomicRMWExpansionKind::None;
8826 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8830 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8831 AtomicOrdering Ord) const {
8832 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8833 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8834 bool IsAcquire = isAtLeastAcquire(Ord);
8836 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8837 // intrinsic must return {i64, i64} and we have to recombine them into a
8838 // single i128 here.
8839 if (ValTy->getPrimitiveSizeInBits() == 128) {
8841 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8842 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8844 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8845 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8847 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8848 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8849 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8850 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8851 return Builder.CreateOr(
8852 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8855 Type *Tys[] = { Addr->getType() };
8857 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8858 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8860 return Builder.CreateTruncOrBitCast(
8861 Builder.CreateCall(Ldxr, Addr),
8862 cast<PointerType>(Addr->getType())->getElementType());
8865 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8866 Value *Val, Value *Addr,
8867 AtomicOrdering Ord) const {
8868 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8869 bool IsRelease = isAtLeastRelease(Ord);
8871 // Since the intrinsics must have legal type, the i128 intrinsics take two
8872 // parameters: "i64, i64". We must marshal Val into the appropriate form
8874 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8876 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8877 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8878 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8880 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8881 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8882 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8883 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8887 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8888 Type *Tys[] = { Addr->getType() };
8889 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8891 return Builder.CreateCall2(
8892 Stxr, Builder.CreateZExtOrBitCast(
8893 Val, Stxr->getFunctionType()->getParamType(0)),
8897 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
8898 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
8899 return Ty->isArrayTy();