1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
32 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
33 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
35 if (Subtarget->isTargetLinux())
36 return new AArch64LinuxTargetObjectFile();
37 if (Subtarget->isTargetELF())
38 return new TargetLoweringObjectFileELF();
39 llvm_unreachable("unknown subtarget type");
42 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
43 : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
45 // SIMD compares set the entire lane's bits to 1
46 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
48 // Scalar register <-> type mapping
49 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
50 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
51 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
52 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
53 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
54 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
56 computeRegisterProperties();
58 // We combine OR nodes for bitfield and NEON BSL operations.
59 setTargetDAGCombine(ISD::OR);
61 setTargetDAGCombine(ISD::AND);
62 setTargetDAGCombine(ISD::SRA);
64 // AArch64 does not have i1 loads, or much of anything for i1 really.
65 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
69 setStackPointerRegisterToSaveRestore(AArch64::XSP);
70 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
71 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
72 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
74 // We'll lower globals to wrappers for selection.
75 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
76 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
78 // A64 instructions have the comparison predicate attached to the user of the
79 // result, but having a separate comparison is valuable for matching.
80 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
81 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
82 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
83 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
85 setOperationAction(ISD::SELECT, MVT::i32, Custom);
86 setOperationAction(ISD::SELECT, MVT::i64, Custom);
87 setOperationAction(ISD::SELECT, MVT::f32, Custom);
88 setOperationAction(ISD::SELECT, MVT::f64, Custom);
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
92 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
93 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
95 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
98 setOperationAction(ISD::SETCC, MVT::i64, Custom);
99 setOperationAction(ISD::SETCC, MVT::f32, Custom);
100 setOperationAction(ISD::SETCC, MVT::f64, Custom);
102 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
103 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
104 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
107 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
108 setOperationAction(ISD::VAEND, MVT::Other, Expand);
109 setOperationAction(ISD::VAARG, MVT::Other, Expand);
111 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
113 setOperationAction(ISD::ROTL, MVT::i32, Expand);
114 setOperationAction(ISD::ROTL, MVT::i64, Expand);
116 setOperationAction(ISD::UREM, MVT::i32, Expand);
117 setOperationAction(ISD::UREM, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
119 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SREM, MVT::i32, Expand);
122 setOperationAction(ISD::SREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
124 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
127 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
129 // Legal floating-point operations.
130 setOperationAction(ISD::FABS, MVT::f32, Legal);
131 setOperationAction(ISD::FABS, MVT::f64, Legal);
133 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
134 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
136 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
137 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
139 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
140 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
142 setOperationAction(ISD::FNEG, MVT::f32, Legal);
143 setOperationAction(ISD::FNEG, MVT::f64, Legal);
145 setOperationAction(ISD::FRINT, MVT::f32, Legal);
146 setOperationAction(ISD::FRINT, MVT::f64, Legal);
148 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
149 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
151 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
152 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
154 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
155 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
156 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
158 // Illegal floating-point operations.
159 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
160 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
162 setOperationAction(ISD::FCOS, MVT::f32, Expand);
163 setOperationAction(ISD::FCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FEXP, MVT::f32, Expand);
166 setOperationAction(ISD::FEXP, MVT::f64, Expand);
168 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
169 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
171 setOperationAction(ISD::FLOG, MVT::f32, Expand);
172 setOperationAction(ISD::FLOG, MVT::f64, Expand);
174 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
175 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
177 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
178 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
180 setOperationAction(ISD::FPOW, MVT::f32, Expand);
181 setOperationAction(ISD::FPOW, MVT::f64, Expand);
183 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
184 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
186 setOperationAction(ISD::FREM, MVT::f32, Expand);
187 setOperationAction(ISD::FREM, MVT::f64, Expand);
189 setOperationAction(ISD::FSIN, MVT::f32, Expand);
190 setOperationAction(ISD::FSIN, MVT::f64, Expand);
192 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
193 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
195 // Virtually no operation on f128 is legal, but LLVM can't expand them when
196 // there's a valid register class, so we need custom operations in most cases.
197 setOperationAction(ISD::FABS, MVT::f128, Expand);
198 setOperationAction(ISD::FADD, MVT::f128, Custom);
199 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
200 setOperationAction(ISD::FCOS, MVT::f128, Expand);
201 setOperationAction(ISD::FDIV, MVT::f128, Custom);
202 setOperationAction(ISD::FMA, MVT::f128, Expand);
203 setOperationAction(ISD::FMUL, MVT::f128, Custom);
204 setOperationAction(ISD::FNEG, MVT::f128, Expand);
205 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
206 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
207 setOperationAction(ISD::FPOW, MVT::f128, Expand);
208 setOperationAction(ISD::FREM, MVT::f128, Expand);
209 setOperationAction(ISD::FRINT, MVT::f128, Expand);
210 setOperationAction(ISD::FSIN, MVT::f128, Expand);
211 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
212 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
213 setOperationAction(ISD::FSUB, MVT::f128, Custom);
214 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
215 setOperationAction(ISD::SETCC, MVT::f128, Custom);
216 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
217 setOperationAction(ISD::SELECT, MVT::f128, Expand);
218 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
219 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
221 // Lowering for many of the conversions is actually specified by the non-f128
222 // type. The LowerXXX function will be trivial when f128 isn't involved.
223 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
224 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
225 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
226 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
227 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
228 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
229 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
230 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
231 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
232 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
233 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
234 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
235 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
236 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
238 // This prevents LLVM trying to compress double constants into a floating
239 // constant-pool entry and trying to load from there. It's of doubtful benefit
240 // for A64: we'd need LDR followed by FCVT, I believe.
241 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
242 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
243 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
245 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
246 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
247 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
248 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
249 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
252 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
253 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
255 setExceptionPointerRegister(AArch64::X0);
256 setExceptionSelectorRegister(AArch64::X1);
259 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
260 // It's reasonably important that this value matches the "natural" legal
261 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
262 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
263 if (!VT.isVector()) return MVT::i32;
264 return VT.changeVectorElementTypeToInteger();
267 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
270 static unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
271 AArch64::LDXR_word, AArch64::LDXR_dword};
272 static unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
273 AArch64::LDAXR_word, AArch64::LDAXR_dword};
274 static unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
275 AArch64::STXR_word, AArch64::STXR_dword};
276 static unsigned StoreRels[] = {AArch64::STLXR_byte, AArch64::STLXR_hword,
277 AArch64::STLXR_word, AArch64::STLXR_dword};
279 unsigned *LoadOps, *StoreOps;
280 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
285 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
286 StoreOps = StoreRels;
288 StoreOps = StoreBares;
290 assert(isPowerOf2_32(Size) && Size <= 8 &&
291 "unsupported size for atomic binary op!");
293 LdrOpc = LoadOps[Log2_32(Size)];
294 StrOpc = StoreOps[Log2_32(Size)];
298 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
300 unsigned BinOpcode) const {
301 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
302 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
304 const BasicBlock *LLVM_BB = BB->getBasicBlock();
305 MachineFunction *MF = BB->getParent();
306 MachineFunction::iterator It = BB;
309 unsigned dest = MI->getOperand(0).getReg();
310 unsigned ptr = MI->getOperand(1).getReg();
311 unsigned incr = MI->getOperand(2).getReg();
312 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
313 DebugLoc dl = MI->getDebugLoc();
315 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
317 unsigned ldrOpc, strOpc;
318 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
320 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
321 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
322 MF->insert(It, loopMBB);
323 MF->insert(It, exitMBB);
325 // Transfer the remainder of BB and its successor edges to exitMBB.
326 exitMBB->splice(exitMBB->begin(), BB,
327 llvm::next(MachineBasicBlock::iterator(MI)),
329 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
331 const TargetRegisterClass *TRC
332 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
333 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
337 // fallthrough --> loopMBB
338 BB->addSuccessor(loopMBB);
342 // <binop> scratch, dest, incr
343 // stxr stxr_status, scratch, ptr
344 // cbnz stxr_status, loopMBB
345 // fallthrough --> exitMBB
347 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
349 // All arithmetic operations we'll be creating are designed to take an extra
350 // shift or extend operand, which we can conveniently set to zero.
352 // Operand order needs to go the other way for NAND.
353 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
354 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
355 .addReg(incr).addReg(dest).addImm(0);
357 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
358 .addReg(dest).addReg(incr).addImm(0);
361 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
362 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
363 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
365 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
366 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
367 .addReg(stxr_status).addMBB(loopMBB);
369 BB->addSuccessor(loopMBB);
370 BB->addSuccessor(exitMBB);
376 MI->eraseFromParent(); // The instruction is gone now.
382 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
383 MachineBasicBlock *BB,
386 A64CC::CondCodes Cond) const {
387 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
389 const BasicBlock *LLVM_BB = BB->getBasicBlock();
390 MachineFunction *MF = BB->getParent();
391 MachineFunction::iterator It = BB;
394 unsigned dest = MI->getOperand(0).getReg();
395 unsigned ptr = MI->getOperand(1).getReg();
396 unsigned incr = MI->getOperand(2).getReg();
397 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
399 unsigned oldval = dest;
400 DebugLoc dl = MI->getDebugLoc();
402 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
403 const TargetRegisterClass *TRC, *TRCsp;
405 TRC = &AArch64::GPR64RegClass;
406 TRCsp = &AArch64::GPR64xspRegClass;
408 TRC = &AArch64::GPR32RegClass;
409 TRCsp = &AArch64::GPR32wspRegClass;
412 unsigned ldrOpc, strOpc;
413 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
415 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
416 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
417 MF->insert(It, loopMBB);
418 MF->insert(It, exitMBB);
420 // Transfer the remainder of BB and its successor edges to exitMBB.
421 exitMBB->splice(exitMBB->begin(), BB,
422 llvm::next(MachineBasicBlock::iterator(MI)),
424 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
426 unsigned scratch = MRI.createVirtualRegister(TRC);
427 MRI.constrainRegClass(scratch, TRCsp);
431 // fallthrough --> loopMBB
432 BB->addSuccessor(loopMBB);
436 // cmp incr, dest (, sign extend if necessary)
437 // csel scratch, dest, incr, cond
438 // stxr stxr_status, scratch, ptr
439 // cbnz stxr_status, loopMBB
440 // fallthrough --> exitMBB
442 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
444 // Build compare and cmov instructions.
445 MRI.constrainRegClass(incr, TRCsp);
446 BuildMI(BB, dl, TII->get(CmpOp))
447 .addReg(incr).addReg(oldval).addImm(0);
449 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
451 .addReg(oldval).addReg(incr).addImm(Cond);
453 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
454 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
456 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
457 .addReg(scratch).addReg(ptr);
458 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
459 .addReg(stxr_status).addMBB(loopMBB);
461 BB->addSuccessor(loopMBB);
462 BB->addSuccessor(exitMBB);
468 MI->eraseFromParent(); // The instruction is gone now.
474 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
475 MachineBasicBlock *BB,
476 unsigned Size) const {
477 unsigned dest = MI->getOperand(0).getReg();
478 unsigned ptr = MI->getOperand(1).getReg();
479 unsigned oldval = MI->getOperand(2).getReg();
480 unsigned newval = MI->getOperand(3).getReg();
481 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
483 DebugLoc dl = MI->getDebugLoc();
485 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
486 const TargetRegisterClass *TRCsp;
487 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
489 unsigned ldrOpc, strOpc;
490 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
492 MachineFunction *MF = BB->getParent();
493 const BasicBlock *LLVM_BB = BB->getBasicBlock();
494 MachineFunction::iterator It = BB;
495 ++It; // insert the new blocks after the current block
497 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
498 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
499 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
500 MF->insert(It, loop1MBB);
501 MF->insert(It, loop2MBB);
502 MF->insert(It, exitMBB);
504 // Transfer the remainder of BB and its successor edges to exitMBB.
505 exitMBB->splice(exitMBB->begin(), BB,
506 llvm::next(MachineBasicBlock::iterator(MI)),
508 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
512 // fallthrough --> loop1MBB
513 BB->addSuccessor(loop1MBB);
520 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
522 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
523 MRI.constrainRegClass(dest, TRCsp);
524 BuildMI(BB, dl, TII->get(CmpOp))
525 .addReg(dest).addReg(oldval).addImm(0);
526 BuildMI(BB, dl, TII->get(AArch64::Bcc))
527 .addImm(A64CC::NE).addMBB(exitMBB);
528 BB->addSuccessor(loop2MBB);
529 BB->addSuccessor(exitMBB);
532 // strex stxr_status, newval, [ptr]
533 // cbnz stxr_status, loop1MBB
535 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
536 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
538 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
539 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
540 .addReg(stxr_status).addMBB(loop1MBB);
541 BB->addSuccessor(loop1MBB);
542 BB->addSuccessor(exitMBB);
548 MI->eraseFromParent(); // The instruction is gone now.
554 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
555 MachineBasicBlock *MBB) const {
556 // We materialise the F128CSEL pseudo-instruction using conditional branches
557 // and loads, giving an instruciton sequence like:
566 // Using virtual registers would probably not be beneficial since COPY
567 // instructions are expensive for f128 (there's no actual instruction to
570 // An alternative would be to do an integer-CSEL on some address. E.g.:
575 // csel x0, x0, x1, ne
578 // It's unclear which approach is actually optimal.
579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
580 MachineFunction *MF = MBB->getParent();
581 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
582 DebugLoc DL = MI->getDebugLoc();
583 MachineFunction::iterator It = MBB;
586 unsigned DestReg = MI->getOperand(0).getReg();
587 unsigned IfTrueReg = MI->getOperand(1).getReg();
588 unsigned IfFalseReg = MI->getOperand(2).getReg();
589 unsigned CondCode = MI->getOperand(3).getImm();
590 bool NZCVKilled = MI->getOperand(4).isKill();
592 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
593 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
594 MF->insert(It, TrueBB);
595 MF->insert(It, EndBB);
597 // Transfer rest of current basic-block to EndBB
598 EndBB->splice(EndBB->begin(), MBB,
599 llvm::next(MachineBasicBlock::iterator(MI)),
601 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
603 // We need somewhere to store the f128 value needed.
604 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
606 // [... start of incoming MBB ...]
607 // str qIFFALSE, [sp]
610 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
612 .addFrameIndex(ScratchFI)
614 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
617 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
619 MBB->addSuccessor(TrueBB);
620 MBB->addSuccessor(EndBB);
624 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
626 .addFrameIndex(ScratchFI)
629 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
631 TrueBB->addSuccessor(EndBB);
635 // [... rest of incoming MBB ...]
637 EndBB->addLiveIn(AArch64::NZCV);
638 MachineInstr *StartOfEnd = EndBB->begin();
639 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
640 .addFrameIndex(ScratchFI)
643 MI->eraseFromParent();
648 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
649 MachineBasicBlock *MBB) const {
650 switch (MI->getOpcode()) {
651 default: llvm_unreachable("Unhandled instruction with custom inserter");
652 case AArch64::F128CSEL:
653 return EmitF128CSEL(MI, MBB);
654 case AArch64::ATOMIC_LOAD_ADD_I8:
655 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
656 case AArch64::ATOMIC_LOAD_ADD_I16:
657 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
658 case AArch64::ATOMIC_LOAD_ADD_I32:
659 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
660 case AArch64::ATOMIC_LOAD_ADD_I64:
661 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
663 case AArch64::ATOMIC_LOAD_SUB_I8:
664 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
665 case AArch64::ATOMIC_LOAD_SUB_I16:
666 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
667 case AArch64::ATOMIC_LOAD_SUB_I32:
668 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
669 case AArch64::ATOMIC_LOAD_SUB_I64:
670 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
672 case AArch64::ATOMIC_LOAD_AND_I8:
673 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
674 case AArch64::ATOMIC_LOAD_AND_I16:
675 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
676 case AArch64::ATOMIC_LOAD_AND_I32:
677 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
678 case AArch64::ATOMIC_LOAD_AND_I64:
679 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
681 case AArch64::ATOMIC_LOAD_OR_I8:
682 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
683 case AArch64::ATOMIC_LOAD_OR_I16:
684 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
685 case AArch64::ATOMIC_LOAD_OR_I32:
686 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
687 case AArch64::ATOMIC_LOAD_OR_I64:
688 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
690 case AArch64::ATOMIC_LOAD_XOR_I8:
691 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
692 case AArch64::ATOMIC_LOAD_XOR_I16:
693 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
694 case AArch64::ATOMIC_LOAD_XOR_I32:
695 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
696 case AArch64::ATOMIC_LOAD_XOR_I64:
697 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
699 case AArch64::ATOMIC_LOAD_NAND_I8:
700 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
701 case AArch64::ATOMIC_LOAD_NAND_I16:
702 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
703 case AArch64::ATOMIC_LOAD_NAND_I32:
704 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
705 case AArch64::ATOMIC_LOAD_NAND_I64:
706 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
708 case AArch64::ATOMIC_LOAD_MIN_I8:
709 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
710 case AArch64::ATOMIC_LOAD_MIN_I16:
711 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
712 case AArch64::ATOMIC_LOAD_MIN_I32:
713 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
714 case AArch64::ATOMIC_LOAD_MIN_I64:
715 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
717 case AArch64::ATOMIC_LOAD_MAX_I8:
718 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
719 case AArch64::ATOMIC_LOAD_MAX_I16:
720 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
721 case AArch64::ATOMIC_LOAD_MAX_I32:
722 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
723 case AArch64::ATOMIC_LOAD_MAX_I64:
724 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
726 case AArch64::ATOMIC_LOAD_UMIN_I8:
727 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
728 case AArch64::ATOMIC_LOAD_UMIN_I16:
729 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
730 case AArch64::ATOMIC_LOAD_UMIN_I32:
731 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
732 case AArch64::ATOMIC_LOAD_UMIN_I64:
733 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
735 case AArch64::ATOMIC_LOAD_UMAX_I8:
736 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
737 case AArch64::ATOMIC_LOAD_UMAX_I16:
738 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
739 case AArch64::ATOMIC_LOAD_UMAX_I32:
740 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
741 case AArch64::ATOMIC_LOAD_UMAX_I64:
742 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
744 case AArch64::ATOMIC_SWAP_I8:
745 return emitAtomicBinary(MI, MBB, 1, 0);
746 case AArch64::ATOMIC_SWAP_I16:
747 return emitAtomicBinary(MI, MBB, 2, 0);
748 case AArch64::ATOMIC_SWAP_I32:
749 return emitAtomicBinary(MI, MBB, 4, 0);
750 case AArch64::ATOMIC_SWAP_I64:
751 return emitAtomicBinary(MI, MBB, 8, 0);
753 case AArch64::ATOMIC_CMP_SWAP_I8:
754 return emitAtomicCmpSwap(MI, MBB, 1);
755 case AArch64::ATOMIC_CMP_SWAP_I16:
756 return emitAtomicCmpSwap(MI, MBB, 2);
757 case AArch64::ATOMIC_CMP_SWAP_I32:
758 return emitAtomicCmpSwap(MI, MBB, 4);
759 case AArch64::ATOMIC_CMP_SWAP_I64:
760 return emitAtomicCmpSwap(MI, MBB, 8);
765 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
767 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
768 case AArch64ISD::Call: return "AArch64ISD::Call";
769 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
770 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
771 case AArch64ISD::BFI: return "AArch64ISD::BFI";
772 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
773 case AArch64ISD::Ret: return "AArch64ISD::Ret";
774 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
775 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
776 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
777 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
778 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
779 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
780 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
781 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
783 default: return NULL;
787 static const uint16_t AArch64FPRArgRegs[] = {
788 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
789 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
791 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
793 static const uint16_t AArch64ArgRegs[] = {
794 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
795 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
797 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
799 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
800 CCValAssign::LocInfo LocInfo,
801 ISD::ArgFlagsTy ArgFlags, CCState &State) {
802 // Mark all remaining general purpose registers as allocated. We don't
803 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
804 // i64 will go in registers (C.11).
805 for (unsigned i = 0; i < NumArgRegs; ++i)
806 State.AllocateReg(AArch64ArgRegs[i]);
811 #include "AArch64GenCallingConv.inc"
813 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
816 default: llvm_unreachable("Unsupported calling convention");
817 case CallingConv::Fast:
824 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
825 SDLoc DL, SDValue &Chain) const {
826 MachineFunction &MF = DAG.getMachineFunction();
827 MachineFrameInfo *MFI = MF.getFrameInfo();
828 AArch64MachineFunctionInfo *FuncInfo
829 = MF.getInfo<AArch64MachineFunctionInfo>();
831 SmallVector<SDValue, 8> MemOps;
833 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
835 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
838 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
840 if (GPRSaveSize != 0) {
841 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
843 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
845 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
846 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
847 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
848 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
849 MachinePointerInfo::getStack(i * 8),
851 MemOps.push_back(Store);
852 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
853 DAG.getConstant(8, getPointerTy()));
857 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
859 if (FPRSaveSize != 0) {
860 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
862 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
864 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
865 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
866 &AArch64::FPR128RegClass);
867 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
868 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
869 MachinePointerInfo::getStack(i * 16),
871 MemOps.push_back(Store);
872 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
873 DAG.getConstant(16, getPointerTy()));
877 int StackIdx = MFI->CreateFixedObject(8, CCInfo.getNextStackOffset(), true);
879 FuncInfo->setVariadicStackIdx(StackIdx);
880 FuncInfo->setVariadicGPRIdx(GPRIdx);
881 FuncInfo->setVariadicGPRSize(GPRSaveSize);
882 FuncInfo->setVariadicFPRIdx(FPRIdx);
883 FuncInfo->setVariadicFPRSize(FPRSaveSize);
885 if (!MemOps.empty()) {
886 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
893 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
894 CallingConv::ID CallConv, bool isVarArg,
895 const SmallVectorImpl<ISD::InputArg> &Ins,
896 SDLoc dl, SelectionDAG &DAG,
897 SmallVectorImpl<SDValue> &InVals) const {
898 MachineFunction &MF = DAG.getMachineFunction();
899 AArch64MachineFunctionInfo *FuncInfo
900 = MF.getInfo<AArch64MachineFunctionInfo>();
901 MachineFrameInfo *MFI = MF.getFrameInfo();
902 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
904 SmallVector<CCValAssign, 16> ArgLocs;
905 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
906 getTargetMachine(), ArgLocs, *DAG.getContext());
907 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
909 SmallVector<SDValue, 16> ArgValues;
912 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
913 CCValAssign &VA = ArgLocs[i];
914 ISD::ArgFlagsTy Flags = Ins[i].Flags;
916 if (Flags.isByVal()) {
917 // Byval is used for small structs and HFAs in the PCS, but the system
918 // should work in a non-compliant manner for larger structs.
919 EVT PtrTy = getPointerTy();
920 int Size = Flags.getByValSize();
921 unsigned NumRegs = (Size + 7) / 8;
923 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
924 VA.getLocMemOffset(),
926 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
927 InVals.push_back(FrameIdxN);
930 } else if (VA.isRegLoc()) {
931 MVT RegVT = VA.getLocVT();
932 const TargetRegisterClass *RC = getRegClassFor(RegVT);
933 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
935 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
936 } else { // VA.isRegLoc()
937 assert(VA.isMemLoc());
939 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
940 VA.getLocMemOffset(), true);
942 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
943 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
944 MachinePointerInfo::getFixedStack(FI),
945 false, false, false, 0);
950 switch (VA.getLocInfo()) {
951 default: llvm_unreachable("Unknown loc info!");
952 case CCValAssign::Full: break;
953 case CCValAssign::BCvt:
954 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
956 case CCValAssign::SExt:
957 case CCValAssign::ZExt:
958 case CCValAssign::AExt: {
959 unsigned DestSize = VA.getValVT().getSizeInBits();
963 case 8: DestSubReg = AArch64::sub_8; break;
964 case 16: DestSubReg = AArch64::sub_16; break;
965 case 32: DestSubReg = AArch64::sub_32; break;
966 case 64: DestSubReg = AArch64::sub_64; break;
967 default: llvm_unreachable("Unexpected argument promotion");
970 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
971 VA.getValVT(), ArgValue,
972 DAG.getTargetConstant(DestSubReg, MVT::i32)),
978 InVals.push_back(ArgValue);
982 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
984 unsigned StackArgSize = CCInfo.getNextStackOffset();
985 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
986 // This is a non-standard ABI so by fiat I say we're allowed to make full
987 // use of the stack area to be popped, which must be aligned to 16 bytes in
989 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
991 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
993 FuncInfo->setArgumentStackToRestore(StackArgSize);
995 // This realignment carries over to the available bytes below. Our own
996 // callers will guarantee the space is free by giving an aligned value to
999 // Even if we're not expected to free up the space, it's useful to know how
1000 // much is there while considering tail calls (because we can reuse it).
1001 FuncInfo->setBytesInStackArgArea(StackArgSize);
1007 AArch64TargetLowering::LowerReturn(SDValue Chain,
1008 CallingConv::ID CallConv, bool isVarArg,
1009 const SmallVectorImpl<ISD::OutputArg> &Outs,
1010 const SmallVectorImpl<SDValue> &OutVals,
1011 SDLoc dl, SelectionDAG &DAG) const {
1012 // CCValAssign - represent the assignment of the return value to a location.
1013 SmallVector<CCValAssign, 16> RVLocs;
1015 // CCState - Info about the registers and stack slots.
1016 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1017 getTargetMachine(), RVLocs, *DAG.getContext());
1019 // Analyze outgoing return values.
1020 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1023 SmallVector<SDValue, 4> RetOps(1, Chain);
1025 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1026 // PCS: "If the type, T, of the result of a function is such that
1027 // void func(T arg) would require that arg be passed as a value in a
1028 // register (or set of registers) according to the rules in 5.4, then the
1029 // result is returned in the same registers as would be used for such an
1032 // Otherwise, the caller shall reserve a block of memory of sufficient
1033 // size and alignment to hold the result. The address of the memory block
1034 // shall be passed as an additional argument to the function in x8."
1036 // This is implemented in two places. The register-return values are dealt
1037 // with here, more complex returns are passed as an sret parameter, which
1038 // means we don't have to worry about it during actual return.
1039 CCValAssign &VA = RVLocs[i];
1040 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1043 SDValue Arg = OutVals[i];
1045 // There's no convenient note in the ABI about this as there is for normal
1046 // arguments, but it says return values are passed in the same registers as
1047 // an argument would be. I believe that includes the comments about
1048 // unspecified higher bits, putting the burden of widening on the *caller*
1049 // for return values.
1050 switch (VA.getLocInfo()) {
1051 default: llvm_unreachable("Unknown loc info");
1052 case CCValAssign::Full: break;
1053 case CCValAssign::SExt:
1054 case CCValAssign::ZExt:
1055 case CCValAssign::AExt:
1056 // Floating-point values should only be extended when they're going into
1057 // memory, which can't happen here so an integer extend is acceptable.
1058 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1060 case CCValAssign::BCvt:
1061 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1065 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1066 Flag = Chain.getValue(1);
1067 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1070 RetOps[0] = Chain; // Update chain.
1072 // Add the flag if we have it.
1074 RetOps.push_back(Flag);
1076 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1077 &RetOps[0], RetOps.size());
1081 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1082 SmallVectorImpl<SDValue> &InVals) const {
1083 SelectionDAG &DAG = CLI.DAG;
1085 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
1086 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
1087 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
1088 SDValue Chain = CLI.Chain;
1089 SDValue Callee = CLI.Callee;
1090 bool &IsTailCall = CLI.IsTailCall;
1091 CallingConv::ID CallConv = CLI.CallConv;
1092 bool IsVarArg = CLI.IsVarArg;
1094 MachineFunction &MF = DAG.getMachineFunction();
1095 AArch64MachineFunctionInfo *FuncInfo
1096 = MF.getInfo<AArch64MachineFunctionInfo>();
1097 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1098 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1099 bool IsSibCall = false;
1102 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1103 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1104 Outs, OutVals, Ins, DAG);
1106 // A sibling call is one where we're under the usual C ABI and not planning
1107 // to change that but can still do a tail call:
1108 if (!TailCallOpt && IsTailCall)
1112 SmallVector<CCValAssign, 16> ArgLocs;
1113 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1114 getTargetMachine(), ArgLocs, *DAG.getContext());
1115 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1117 // On AArch64 (and all other architectures I'm aware of) the most this has to
1118 // do is adjust the stack pointer.
1119 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1121 // Since we're not changing the ABI to make this a tail call, the memory
1122 // operands are already available in the caller's incoming argument space.
1126 // FPDiff is the byte offset of the call's argument area from the callee's.
1127 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1128 // by this amount for a tail call. In a sibling call it must be 0 because the
1129 // caller will deallocate the entire stack and the callee still expects its
1130 // arguments to begin at SP+0. Completely unused for non-tail calls.
1133 if (IsTailCall && !IsSibCall) {
1134 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1136 // FPDiff will be negative if this tail call requires more space than we
1137 // would automatically have in our incoming argument space. Positive if we
1138 // can actually shrink the stack.
1139 FPDiff = NumReusableBytes - NumBytes;
1141 // The stack pointer must be 16-byte aligned at all times it's used for a
1142 // memory operation, which in practice means at *all* times and in
1143 // particular across call boundaries. Therefore our own arguments started at
1144 // a 16-byte aligned SP and the delta applied for the tail call should
1145 // satisfy the same constraint.
1146 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1150 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1153 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1156 SmallVector<SDValue, 8> MemOpChains;
1157 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1159 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1160 CCValAssign &VA = ArgLocs[i];
1161 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1162 SDValue Arg = OutVals[i];
1164 // Callee does the actual widening, so all extensions just use an implicit
1165 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1166 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1167 // alternative works on integer types too.
1168 switch (VA.getLocInfo()) {
1169 default: llvm_unreachable("Unknown loc info!");
1170 case CCValAssign::Full: break;
1171 case CCValAssign::SExt:
1172 case CCValAssign::ZExt:
1173 case CCValAssign::AExt: {
1174 unsigned SrcSize = VA.getValVT().getSizeInBits();
1178 case 8: SrcSubReg = AArch64::sub_8; break;
1179 case 16: SrcSubReg = AArch64::sub_16; break;
1180 case 32: SrcSubReg = AArch64::sub_32; break;
1181 case 64: SrcSubReg = AArch64::sub_64; break;
1182 default: llvm_unreachable("Unexpected argument promotion");
1185 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1187 DAG.getUNDEF(VA.getLocVT()),
1189 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1194 case CCValAssign::BCvt:
1195 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1199 if (VA.isRegLoc()) {
1200 // A normal register (sub-) argument. For now we just note it down because
1201 // we want to copy things into registers as late as possible to avoid
1202 // register-pressure (and possibly worse).
1203 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1207 assert(VA.isMemLoc() && "unexpected argument location");
1210 MachinePointerInfo DstInfo;
1212 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1213 VA.getLocVT().getSizeInBits();
1214 OpSize = (OpSize + 7) / 8;
1215 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1216 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1218 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1219 DstInfo = MachinePointerInfo::getFixedStack(FI);
1221 // Make sure any stack arguments overlapping with where we're storing are
1222 // loaded before this eventual operation. Otherwise they'll be clobbered.
1223 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1225 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1227 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1228 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1231 if (Flags.isByVal()) {
1232 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1233 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1234 Flags.getByValAlign(),
1235 /*isVolatile = */ false,
1236 /*alwaysInline = */ false,
1237 DstInfo, MachinePointerInfo(0));
1238 MemOpChains.push_back(Cpy);
1240 // Normal stack argument, put it where it's needed.
1241 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1243 MemOpChains.push_back(Store);
1247 // The loads and stores generated above shouldn't clash with each
1248 // other. Combining them with this TokenFactor notes that fact for the rest of
1250 if (!MemOpChains.empty())
1251 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1252 &MemOpChains[0], MemOpChains.size());
1254 // Most of the rest of the instructions need to be glued together; we don't
1255 // want assignments to actual registers used by a call to be rearranged by a
1256 // well-meaning scheduler.
1259 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1260 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1261 RegsToPass[i].second, InFlag);
1262 InFlag = Chain.getValue(1);
1265 // The linker is responsible for inserting veneers when necessary to put a
1266 // function call destination in range, so we don't need to bother with a
1268 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1269 const GlobalValue *GV = G->getGlobal();
1270 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1271 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1272 const char *Sym = S->getSymbol();
1273 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1276 // We don't usually want to end the call-sequence here because we would tidy
1277 // the frame up *after* the call, however in the ABI-changing tail-call case
1278 // we've carefully laid out the parameters so that when sp is reset they'll be
1279 // in the correct location.
1280 if (IsTailCall && !IsSibCall) {
1281 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1282 DAG.getIntPtrConstant(0, true), InFlag, dl);
1283 InFlag = Chain.getValue(1);
1286 // We produce the following DAG scheme for the actual call instruction:
1287 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1289 // Most arguments aren't going to be used and just keep the values live as
1290 // far as LLVM is concerned. It's expected to be selected as simply "bl
1291 // callee" (for a direct, non-tail call).
1292 std::vector<SDValue> Ops;
1293 Ops.push_back(Chain);
1294 Ops.push_back(Callee);
1297 // Each tail call may have to adjust the stack by a different amount, so
1298 // this information must travel along with the operation for eventual
1299 // consumption by emitEpilogue.
1300 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1303 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1304 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1305 RegsToPass[i].second.getValueType()));
1308 // Add a register mask operand representing the call-preserved registers. This
1309 // is used later in codegen to constrain register-allocation.
1310 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1311 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1312 assert(Mask && "Missing call preserved mask for calling convention");
1313 Ops.push_back(DAG.getRegisterMask(Mask));
1315 // If we needed glue, put it in as the last argument.
1316 if (InFlag.getNode())
1317 Ops.push_back(InFlag);
1319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1322 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1325 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1326 InFlag = Chain.getValue(1);
1328 // Now we can reclaim the stack, just as well do it before working out where
1329 // our return value is.
1331 uint64_t CalleePopBytes
1332 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1334 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1335 DAG.getIntPtrConstant(CalleePopBytes, true),
1337 InFlag = Chain.getValue(1);
1340 return LowerCallResult(Chain, InFlag, CallConv,
1341 IsVarArg, Ins, dl, DAG, InVals);
1345 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1346 CallingConv::ID CallConv, bool IsVarArg,
1347 const SmallVectorImpl<ISD::InputArg> &Ins,
1348 SDLoc dl, SelectionDAG &DAG,
1349 SmallVectorImpl<SDValue> &InVals) const {
1350 // Assign locations to each value returned by this call.
1351 SmallVector<CCValAssign, 16> RVLocs;
1352 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1353 getTargetMachine(), RVLocs, *DAG.getContext());
1354 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1356 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1357 CCValAssign VA = RVLocs[i];
1359 // Return values that are too big to fit into registers should use an sret
1360 // pointer, so this can be a lot simpler than the main argument code.
1361 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1363 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1365 Chain = Val.getValue(1);
1366 InFlag = Val.getValue(2);
1368 switch (VA.getLocInfo()) {
1369 default: llvm_unreachable("Unknown loc info!");
1370 case CCValAssign::Full: break;
1371 case CCValAssign::BCvt:
1372 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1374 case CCValAssign::ZExt:
1375 case CCValAssign::SExt:
1376 case CCValAssign::AExt:
1377 // Floating-point arguments only get extended/truncated if they're going
1378 // in memory, so using the integer operation is acceptable here.
1379 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1383 InVals.push_back(Val);
1390 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1391 CallingConv::ID CalleeCC,
1393 bool IsCalleeStructRet,
1394 bool IsCallerStructRet,
1395 const SmallVectorImpl<ISD::OutputArg> &Outs,
1396 const SmallVectorImpl<SDValue> &OutVals,
1397 const SmallVectorImpl<ISD::InputArg> &Ins,
1398 SelectionDAG& DAG) const {
1400 // For CallingConv::C this function knows whether the ABI needs
1401 // changing. That's not true for other conventions so they will have to opt in
1403 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1406 const MachineFunction &MF = DAG.getMachineFunction();
1407 const Function *CallerF = MF.getFunction();
1408 CallingConv::ID CallerCC = CallerF->getCallingConv();
1409 bool CCMatch = CallerCC == CalleeCC;
1411 // Byval parameters hand the function a pointer directly into the stack area
1412 // we want to reuse during a tail call. Working around this *is* possible (see
1413 // X86) but less efficient and uglier in LowerCall.
1414 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1415 e = CallerF->arg_end(); i != e; ++i)
1416 if (i->hasByValAttr())
1419 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1420 if (IsTailCallConvention(CalleeCC) && CCMatch)
1425 // Now we search for cases where we can use a tail call without changing the
1426 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1429 // I want anyone implementing a new calling convention to think long and hard
1430 // about this assert.
1431 assert((!IsVarArg || CalleeCC == CallingConv::C)
1432 && "Unexpected variadic calling convention");
1434 if (IsVarArg && !Outs.empty()) {
1435 // At least two cases here: if caller is fastcc then we can't have any
1436 // memory arguments (we'd be expected to clean up the stack afterwards). If
1437 // caller is C then we could potentially use its argument area.
1439 // FIXME: for now we take the most conservative of these in both cases:
1440 // disallow all variadic memory operands.
1441 SmallVector<CCValAssign, 16> ArgLocs;
1442 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1443 getTargetMachine(), ArgLocs, *DAG.getContext());
1445 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1446 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1447 if (!ArgLocs[i].isRegLoc())
1451 // If the calling conventions do not match, then we'd better make sure the
1452 // results are returned in the same way as what the caller expects.
1454 SmallVector<CCValAssign, 16> RVLocs1;
1455 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1456 getTargetMachine(), RVLocs1, *DAG.getContext());
1457 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1459 SmallVector<CCValAssign, 16> RVLocs2;
1460 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1461 getTargetMachine(), RVLocs2, *DAG.getContext());
1462 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1464 if (RVLocs1.size() != RVLocs2.size())
1466 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1467 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1469 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1471 if (RVLocs1[i].isRegLoc()) {
1472 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1475 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1481 // Nothing more to check if the callee is taking no arguments
1485 SmallVector<CCValAssign, 16> ArgLocs;
1486 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1487 getTargetMachine(), ArgLocs, *DAG.getContext());
1489 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1491 const AArch64MachineFunctionInfo *FuncInfo
1492 = MF.getInfo<AArch64MachineFunctionInfo>();
1494 // If the stack arguments for this call would fit into our own save area then
1495 // the call can be made tail.
1496 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1499 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1500 bool TailCallOpt) const {
1501 return CallCC == CallingConv::Fast && TailCallOpt;
1504 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1505 return CallCC == CallingConv::Fast;
1508 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1510 MachineFrameInfo *MFI,
1511 int ClobberedFI) const {
1512 SmallVector<SDValue, 8> ArgChains;
1513 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1514 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1516 // Include the original chain at the beginning of the list. When this is
1517 // used by target LowerCall hooks, this helps legalize find the
1518 // CALLSEQ_BEGIN node.
1519 ArgChains.push_back(Chain);
1521 // Add a chain value for each stack argument corresponding
1522 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1523 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1524 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1525 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1526 if (FI->getIndex() < 0) {
1527 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1528 int64_t InLastByte = InFirstByte;
1529 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1531 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1532 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1533 ArgChains.push_back(SDValue(L, 1));
1536 // Build a tokenfactor for all the chains.
1537 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1538 &ArgChains[0], ArgChains.size());
1541 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1543 case ISD::SETEQ: return A64CC::EQ;
1544 case ISD::SETGT: return A64CC::GT;
1545 case ISD::SETGE: return A64CC::GE;
1546 case ISD::SETLT: return A64CC::LT;
1547 case ISD::SETLE: return A64CC::LE;
1548 case ISD::SETNE: return A64CC::NE;
1549 case ISD::SETUGT: return A64CC::HI;
1550 case ISD::SETUGE: return A64CC::HS;
1551 case ISD::SETULT: return A64CC::LO;
1552 case ISD::SETULE: return A64CC::LS;
1553 default: llvm_unreachable("Unexpected condition code");
1557 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1558 // icmp is implemented using adds/subs immediate, which take an unsigned
1559 // 12-bit immediate, optionally shifted left by 12 bits.
1561 // Symmetric by using adds/subs
1565 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1568 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1569 ISD::CondCode CC, SDValue &A64cc,
1570 SelectionDAG &DAG, SDLoc &dl) const {
1571 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1573 EVT VT = RHSC->getValueType(0);
1574 bool knownInvalid = false;
1576 // I'm not convinced the rest of LLVM handles these edge cases properly, but
1577 // we can at least get it right.
1578 if (isSignedIntSetCC(CC)) {
1579 C = RHSC->getSExtValue();
1580 } else if (RHSC->getZExtValue() > INT64_MAX) {
1581 // A 64-bit constant not representable by a signed 64-bit integer is far
1582 // too big to fit into a SUBS immediate anyway.
1583 knownInvalid = true;
1585 C = RHSC->getZExtValue();
1588 if (!knownInvalid && !isLegalICmpImmediate(C)) {
1589 // Constant does not fit, try adjusting it by one?
1594 if (isLegalICmpImmediate(C-1)) {
1595 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1596 RHS = DAG.getConstant(C-1, VT);
1601 if (isLegalICmpImmediate(C-1)) {
1602 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1603 RHS = DAG.getConstant(C-1, VT);
1608 if (isLegalICmpImmediate(C+1)) {
1609 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1610 RHS = DAG.getConstant(C+1, VT);
1615 if (isLegalICmpImmediate(C+1)) {
1616 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1617 RHS = DAG.getConstant(C+1, VT);
1624 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
1625 A64cc = DAG.getConstant(CondCode, MVT::i32);
1626 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1627 DAG.getCondCode(CC));
1630 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1631 A64CC::CondCodes &Alternative) {
1632 A64CC::CondCodes CondCode = A64CC::Invalid;
1633 Alternative = A64CC::Invalid;
1636 default: llvm_unreachable("Unknown FP condition!");
1638 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
1640 case ISD::SETOGT: CondCode = A64CC::GT; break;
1642 case ISD::SETOGE: CondCode = A64CC::GE; break;
1643 case ISD::SETOLT: CondCode = A64CC::MI; break;
1644 case ISD::SETOLE: CondCode = A64CC::LS; break;
1645 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
1646 case ISD::SETO: CondCode = A64CC::VC; break;
1647 case ISD::SETUO: CondCode = A64CC::VS; break;
1648 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
1649 case ISD::SETUGT: CondCode = A64CC::HI; break;
1650 case ISD::SETUGE: CondCode = A64CC::PL; break;
1652 case ISD::SETULT: CondCode = A64CC::LT; break;
1654 case ISD::SETULE: CondCode = A64CC::LE; break;
1656 case ISD::SETUNE: CondCode = A64CC::NE; break;
1662 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1664 EVT PtrVT = getPointerTy();
1665 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1667 switch(getTargetMachine().getCodeModel()) {
1668 case CodeModel::Small:
1669 // The most efficient code is PC-relative anyway for the small memory model,
1670 // so we don't need to worry about relocation model.
1671 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
1672 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1673 AArch64II::MO_NO_FLAG),
1674 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1675 AArch64II::MO_LO12),
1676 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
1677 case CodeModel::Large:
1679 AArch64ISD::WrapperLarge, DL, PtrVT,
1680 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3),
1681 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
1682 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
1683 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
1685 llvm_unreachable("Only small and large code models supported now");
1690 // (BRCOND chain, val, dest)
1692 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1694 SDValue Chain = Op.getOperand(0);
1695 SDValue TheBit = Op.getOperand(1);
1696 SDValue DestBB = Op.getOperand(2);
1698 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
1699 // that as the consumer we are responsible for ignoring rubbish in higher
1701 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
1702 DAG.getConstant(1, MVT::i32));
1704 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
1705 DAG.getConstant(0, TheBit.getValueType()),
1706 DAG.getCondCode(ISD::SETNE));
1708 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
1709 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
1713 // (BR_CC chain, condcode, lhs, rhs, dest)
1715 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1717 SDValue Chain = Op.getOperand(0);
1718 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1719 SDValue LHS = Op.getOperand(2);
1720 SDValue RHS = Op.getOperand(3);
1721 SDValue DestBB = Op.getOperand(4);
1723 if (LHS.getValueType() == MVT::f128) {
1724 // f128 comparisons are lowered to runtime calls by a routine which sets
1725 // LHS, RHS and CC appropriately for the rest of this function to continue.
1726 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
1728 // If softenSetCCOperands returned a scalar, we need to compare the result
1729 // against zero to select between true and false values.
1730 if (RHS.getNode() == 0) {
1731 RHS = DAG.getConstant(0, LHS.getValueType());
1736 if (LHS.getValueType().isInteger()) {
1739 // Integers are handled in a separate function because the combinations of
1740 // immediates and tests can get hairy and we may want to fiddle things.
1741 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
1743 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1744 Chain, CmpOp, A64cc, DestBB);
1747 // Note that some LLVM floating-point CondCodes can't be lowered to a single
1748 // conditional branch, hence FPCCToA64CC can set a second test, where either
1749 // passing is sufficient.
1750 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
1751 CondCode = FPCCToA64CC(CC, Alternative);
1752 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
1753 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1754 DAG.getCondCode(CC));
1755 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1756 Chain, SetCC, A64cc, DestBB);
1758 if (Alternative != A64CC::Invalid) {
1759 A64cc = DAG.getConstant(Alternative, MVT::i32);
1760 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1761 A64BR_CC, SetCC, A64cc, DestBB);
1769 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
1770 RTLIB::Libcall Call) const {
1773 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
1774 EVT ArgVT = Op.getOperand(i).getValueType();
1775 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1776 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
1777 Entry.isSExt = false;
1778 Entry.isZExt = false;
1779 Args.push_back(Entry);
1781 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
1783 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
1785 // By default, the input chain to this libcall is the entry node of the
1786 // function. If the libcall is going to be emitted as a tail call then
1787 // isUsedByReturnOnly will change it to the right chain if the return
1788 // node which is being folded has a non-entry input chain.
1789 SDValue InChain = DAG.getEntryNode();
1791 // isTailCall may be true since the callee does not reference caller stack
1792 // frame. Check if it's in the right position.
1793 SDValue TCChain = InChain;
1794 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
1799 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
1800 0, getLibcallCallingConv(Call), isTailCall,
1801 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1802 Callee, Args, DAG, SDLoc(Op));
1803 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1805 if (!CallInfo.second.getNode())
1806 // It's a tailcall, return the chain (which is the DAG root).
1807 return DAG.getRoot();
1809 return CallInfo.first;
1813 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
1814 if (Op.getOperand(0).getValueType() != MVT::f128) {
1815 // It's legal except when f128 is involved
1820 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1822 SDValue SrcVal = Op.getOperand(0);
1823 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1824 /*isSigned*/ false, SDLoc(Op));
1828 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
1829 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1832 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1834 return LowerF128ToCall(Op, DAG, LC);
1838 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1839 bool IsSigned) const {
1840 if (Op.getOperand(0).getValueType() != MVT::f128) {
1841 // It's legal except when f128 is involved
1847 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1849 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1851 return LowerF128ToCall(Op, DAG, LC);
1855 AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op,
1856 SelectionDAG &DAG) const {
1857 assert(getTargetMachine().getCodeModel() == CodeModel::Large);
1858 assert(getTargetMachine().getRelocationModel() == Reloc::Static);
1860 EVT PtrVT = getPointerTy();
1862 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
1863 const GlobalValue *GV = GN->getGlobal();
1865 SDValue GlobalAddr = DAG.getNode(
1866 AArch64ISD::WrapperLarge, dl, PtrVT,
1867 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3),
1868 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
1869 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
1870 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
1872 if (GN->getOffset() != 0)
1873 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
1874 DAG.getConstant(GN->getOffset(), PtrVT));
1880 AArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op,
1881 SelectionDAG &DAG) const {
1882 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
1884 EVT PtrVT = getPointerTy();
1886 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
1887 const GlobalValue *GV = GN->getGlobal();
1888 unsigned Alignment = GV->getAlignment();
1889 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1890 if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) {
1891 // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate
1892 // to zero when they remain undefined. In PIC mode the GOT can take care of
1893 // this, but in absolute mode we use a constant pool load.
1895 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
1896 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
1897 AArch64II::MO_NO_FLAG),
1898 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
1899 AArch64II::MO_LO12),
1900 DAG.getConstant(8, MVT::i32));
1901 SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
1902 MachinePointerInfo::getConstantPool(),
1903 /*isVolatile=*/ false,
1904 /*isNonTemporal=*/ true,
1905 /*isInvariant=*/ true, 8);
1906 if (GN->getOffset() != 0)
1907 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
1908 DAG.getConstant(GN->getOffset(), PtrVT));
1913 if (Alignment == 0) {
1914 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
1915 if (GVPtrTy->getElementType()->isSized()) {
1917 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
1919 // Be conservative if we can't guess, not that it really matters:
1920 // functions and labels aren't valid for loads, and the methods used to
1921 // actually calculate an address work with any alignment.
1926 unsigned char HiFixup, LoFixup;
1927 bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM);
1930 HiFixup = AArch64II::MO_GOT;
1931 LoFixup = AArch64II::MO_GOT_LO12;
1934 HiFixup = AArch64II::MO_NO_FLAG;
1935 LoFixup = AArch64II::MO_LO12;
1938 // AArch64's small model demands the following sequence:
1939 // ADRP x0, somewhere
1940 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
1941 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
1942 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1944 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1946 DAG.getConstant(Alignment, MVT::i32));
1949 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
1953 if (GN->getOffset() != 0)
1954 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
1955 DAG.getConstant(GN->getOffset(), PtrVT));
1961 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
1962 SelectionDAG &DAG) const {
1963 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
1964 // we make those distinctions here.
1966 switch (getTargetMachine().getCodeModel()) {
1967 case CodeModel::Small:
1968 return LowerGlobalAddressELFSmall(Op, DAG);
1969 case CodeModel::Large:
1970 return LowerGlobalAddressELFLarge(Op, DAG);
1972 llvm_unreachable("Only small and large code models supported now");
1976 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
1979 SelectionDAG &DAG) const {
1980 EVT PtrVT = getPointerTy();
1982 // The function we need to call is simply the first entry in the GOT for this
1983 // descriptor, load it in preparation.
1984 SDValue Func, Chain;
1985 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
1988 // The function takes only one argument: the address of the descriptor itself
1991 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
1992 Glue = Chain.getValue(1);
1994 // Finally, there's a special calling-convention which means that the lookup
1995 // must preserve all registers (except X0, obviously).
1996 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1997 const AArch64RegisterInfo *A64RI
1998 = static_cast<const AArch64RegisterInfo *>(TRI);
1999 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
2001 // We're now ready to populate the argument list, as with a normal call:
2002 std::vector<SDValue> Ops;
2003 Ops.push_back(Chain);
2004 Ops.push_back(Func);
2005 Ops.push_back(SymAddr);
2006 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2007 Ops.push_back(DAG.getRegisterMask(Mask));
2008 Ops.push_back(Glue);
2010 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2011 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
2013 Glue = Chain.getValue(1);
2015 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
2016 // back to the generic handling code.
2017 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2021 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2022 SelectionDAG &DAG) const {
2023 assert(getSubtarget()->isTargetELF() &&
2024 "TLS not implemented for non-ELF targets");
2025 assert(getTargetMachine().getCodeModel() == CodeModel::Small
2026 && "TLS only supported in small memory model");
2027 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2029 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2032 EVT PtrVT = getPointerTy();
2034 const GlobalValue *GV = GA->getGlobal();
2036 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2038 if (Model == TLSModel::InitialExec) {
2039 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2040 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2041 AArch64II::MO_GOTTPREL),
2042 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2043 AArch64II::MO_GOTTPREL_LO12),
2044 DAG.getConstant(8, MVT::i32));
2045 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2047 } else if (Model == TLSModel::LocalExec) {
2048 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2049 AArch64II::MO_TPREL_G1);
2050 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2051 AArch64II::MO_TPREL_G0_NC);
2053 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2054 DAG.getTargetConstant(0, MVT::i32)), 0);
2055 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2057 DAG.getTargetConstant(0, MVT::i32)), 0);
2058 } else if (Model == TLSModel::GeneralDynamic) {
2059 // Accesses used in this sequence go via the TLS descriptor which lives in
2060 // the GOT. Prepare an address we can use to handle this.
2061 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2062 AArch64II::MO_TLSDESC);
2063 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2064 AArch64II::MO_TLSDESC_LO12);
2065 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2067 DAG.getConstant(8, MVT::i32));
2068 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2070 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2071 } else if (Model == TLSModel::LocalDynamic) {
2072 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2073 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2074 // the beginning of the module's TLS region, followed by a DTPREL offset
2077 // These accesses will need deduplicating if there's more than one.
2078 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2079 .getInfo<AArch64MachineFunctionInfo>();
2080 MFI->incNumLocalDynamicTLSAccesses();
2083 // Get the location of _TLS_MODULE_BASE_:
2084 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2085 AArch64II::MO_TLSDESC);
2086 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2087 AArch64II::MO_TLSDESC_LO12);
2088 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2090 DAG.getConstant(8, MVT::i32));
2091 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2093 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2095 // Get the variable's offset from _TLS_MODULE_BASE_
2096 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2097 AArch64II::MO_DTPREL_G1);
2098 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2099 AArch64II::MO_DTPREL_G0_NC);
2101 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2102 DAG.getTargetConstant(0, MVT::i32)), 0);
2103 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2105 DAG.getTargetConstant(0, MVT::i32)), 0);
2107 llvm_unreachable("Unsupported TLS access model");
2110 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2114 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2115 bool IsSigned) const {
2116 if (Op.getValueType() != MVT::f128) {
2117 // Legal for everything except f128.
2123 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2125 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2127 return LowerF128ToCall(Op, DAG, LC);
2132 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2133 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2135 EVT PtrVT = getPointerTy();
2137 // When compiling PIC, jump tables get put in the code section so a static
2138 // relocation-style is acceptable for both cases.
2139 switch (getTargetMachine().getCodeModel()) {
2140 case CodeModel::Small:
2141 return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2142 DAG.getTargetJumpTable(JT->getIndex(), PtrVT),
2143 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2144 AArch64II::MO_LO12),
2145 DAG.getConstant(1, MVT::i32));
2146 case CodeModel::Large:
2148 AArch64ISD::WrapperLarge, dl, PtrVT,
2149 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3),
2150 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC),
2151 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC),
2152 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC));
2154 llvm_unreachable("Only small and large code models supported now");
2158 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
2160 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2162 SDValue LHS = Op.getOperand(0);
2163 SDValue RHS = Op.getOperand(1);
2164 SDValue IfTrue = Op.getOperand(2);
2165 SDValue IfFalse = Op.getOperand(3);
2166 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2168 if (LHS.getValueType() == MVT::f128) {
2169 // f128 comparisons are lowered to libcalls, but slot in nicely here
2171 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2173 // If softenSetCCOperands returned a scalar, we need to compare the result
2174 // against zero to select between true and false values.
2175 if (RHS.getNode() == 0) {
2176 RHS = DAG.getConstant(0, LHS.getValueType());
2181 if (LHS.getValueType().isInteger()) {
2184 // Integers are handled in a separate function because the combinations of
2185 // immediates and tests can get hairy and we may want to fiddle things.
2186 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2188 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2189 CmpOp, IfTrue, IfFalse, A64cc);
2192 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2193 // conditional branch, hence FPCCToA64CC can set a second test, where either
2194 // passing is sufficient.
2195 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2196 CondCode = FPCCToA64CC(CC, Alternative);
2197 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2198 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2199 DAG.getCondCode(CC));
2200 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
2202 SetCC, IfTrue, IfFalse, A64cc);
2204 if (Alternative != A64CC::Invalid) {
2205 A64cc = DAG.getConstant(Alternative, MVT::i32);
2206 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2207 SetCC, IfTrue, A64SELECT_CC, A64cc);
2211 return A64SELECT_CC;
2214 // (SELECT testbit, iftrue, iffalse)
2216 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2218 SDValue TheBit = Op.getOperand(0);
2219 SDValue IfTrue = Op.getOperand(1);
2220 SDValue IfFalse = Op.getOperand(2);
2222 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2223 // that as the consumer we are responsible for ignoring rubbish in higher
2225 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2226 DAG.getConstant(1, MVT::i32));
2227 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2228 DAG.getConstant(0, TheBit.getValueType()),
2229 DAG.getCondCode(ISD::SETNE));
2231 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2232 A64CMP, IfTrue, IfFalse,
2233 DAG.getConstant(A64CC::NE, MVT::i32));
2236 // (SETCC lhs, rhs, condcode)
2238 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2240 SDValue LHS = Op.getOperand(0);
2241 SDValue RHS = Op.getOperand(1);
2242 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2243 EVT VT = Op.getValueType();
2245 if (LHS.getValueType() == MVT::f128) {
2246 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
2247 // for the rest of the function (some i32 or i64 values).
2248 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2250 // If softenSetCCOperands returned a scalar, use it.
2251 if (RHS.getNode() == 0) {
2252 assert(LHS.getValueType() == Op.getValueType() &&
2253 "Unexpected setcc expansion!");
2258 if (LHS.getValueType().isInteger()) {
2261 // Integers are handled in a separate function because the combinations of
2262 // immediates and tests can get hairy and we may want to fiddle things.
2263 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2265 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2266 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2270 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2271 // conditional branch, hence FPCCToA64CC can set a second test, where either
2272 // passing is sufficient.
2273 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2274 CondCode = FPCCToA64CC(CC, Alternative);
2275 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2276 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2277 DAG.getCondCode(CC));
2278 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2279 CmpOp, DAG.getConstant(1, VT),
2280 DAG.getConstant(0, VT), A64cc);
2282 if (Alternative != A64CC::Invalid) {
2283 A64cc = DAG.getConstant(Alternative, MVT::i32);
2284 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
2285 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
2288 return A64SELECT_CC;
2292 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2293 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2294 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2296 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
2297 // rather than just 8.
2298 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op),
2299 Op.getOperand(1), Op.getOperand(2),
2300 DAG.getConstant(32, MVT::i32), 8, false, false,
2301 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
2305 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2306 // The layout of the va_list struct is specified in the AArch64 Procedure Call
2307 // Standard, section B.3.
2308 MachineFunction &MF = DAG.getMachineFunction();
2309 AArch64MachineFunctionInfo *FuncInfo
2310 = MF.getInfo<AArch64MachineFunctionInfo>();
2313 SDValue Chain = Op.getOperand(0);
2314 SDValue VAList = Op.getOperand(1);
2315 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2316 SmallVector<SDValue, 4> MemOps;
2318 // void *__stack at offset 0
2319 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
2321 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
2322 MachinePointerInfo(SV), false, false, 0));
2324 // void *__gr_top at offset 8
2325 int GPRSize = FuncInfo->getVariadicGPRSize();
2327 SDValue GRTop, GRTopAddr;
2329 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2330 DAG.getConstant(8, getPointerTy()));
2332 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
2333 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
2334 DAG.getConstant(GPRSize, getPointerTy()));
2336 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
2337 MachinePointerInfo(SV, 8),
2341 // void *__vr_top at offset 16
2342 int FPRSize = FuncInfo->getVariadicFPRSize();
2344 SDValue VRTop, VRTopAddr;
2345 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2346 DAG.getConstant(16, getPointerTy()));
2348 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
2349 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
2350 DAG.getConstant(FPRSize, getPointerTy()));
2352 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
2353 MachinePointerInfo(SV, 16),
2357 // int __gr_offs at offset 24
2358 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2359 DAG.getConstant(24, getPointerTy()));
2360 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
2361 GROffsAddr, MachinePointerInfo(SV, 24),
2364 // int __vr_offs at offset 28
2365 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2366 DAG.getConstant(28, getPointerTy()));
2367 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
2368 VROffsAddr, MachinePointerInfo(SV, 28),
2371 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
2376 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2377 switch (Op.getOpcode()) {
2378 default: llvm_unreachable("Don't know how to custom lower this!");
2379 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
2380 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
2381 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
2382 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
2383 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
2384 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
2385 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
2386 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
2387 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
2388 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
2390 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2391 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
2392 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2393 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
2394 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2395 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2396 case ISD::SELECT: return LowerSELECT(Op, DAG);
2397 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2398 case ISD::SETCC: return LowerSETCC(Op, DAG);
2399 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
2400 case ISD::VASTART: return LowerVASTART(Op, DAG);
2406 static SDValue PerformANDCombine(SDNode *N,
2407 TargetLowering::DAGCombinerInfo &DCI) {
2409 SelectionDAG &DAG = DCI.DAG;
2411 EVT VT = N->getValueType(0);
2413 // We're looking for an SRA/SHL pair which form an SBFX.
2415 if (VT != MVT::i32 && VT != MVT::i64)
2418 if (!isa<ConstantSDNode>(N->getOperand(1)))
2421 uint64_t TruncMask = N->getConstantOperandVal(1);
2422 if (!isMask_64(TruncMask))
2425 uint64_t Width = CountPopulation_64(TruncMask);
2426 SDValue Shift = N->getOperand(0);
2428 if (Shift.getOpcode() != ISD::SRL)
2431 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
2433 uint64_t LSB = Shift->getConstantOperandVal(1);
2435 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
2438 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
2439 DAG.getConstant(LSB, MVT::i64),
2440 DAG.getConstant(LSB + Width - 1, MVT::i64));
2443 /// For a true bitfield insert, the bits getting into that contiguous mask
2444 /// should come from the low part of an existing value: they must be formed from
2445 /// a compatible SHL operation (unless they're already low). This function
2446 /// checks that condition and returns the least-significant bit that's
2447 /// intended. If the operation not a field preparation, -1 is returned.
2448 static int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT,
2449 SDValue &MaskedVal, uint64_t Mask) {
2450 if (!isShiftedMask_64(Mask))
2453 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
2454 // instruction. BFI will do a left-shift by LSB before applying the mask we've
2455 // spotted, so in general we should pre-emptively "undo" that by making sure
2456 // the incoming bits have had a right-shift applied to them.
2458 // This right shift, however, will combine with existing left/right shifts. In
2459 // the simplest case of a completely straight bitfield operation, it will be
2460 // expected to completely cancel out with an existing SHL. More complicated
2461 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
2464 uint64_t LSB = countTrailingZeros(Mask);
2465 int64_t ShiftRightRequired = LSB;
2466 if (MaskedVal.getOpcode() == ISD::SHL &&
2467 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
2468 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
2469 MaskedVal = MaskedVal.getOperand(0);
2470 } else if (MaskedVal.getOpcode() == ISD::SRL &&
2471 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
2472 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
2473 MaskedVal = MaskedVal.getOperand(0);
2476 if (ShiftRightRequired > 0)
2477 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
2478 DAG.getConstant(ShiftRightRequired, MVT::i64));
2479 else if (ShiftRightRequired < 0) {
2480 // We could actually end up with a residual left shift, for example with
2481 // "struc.bitfield = val << 1".
2482 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
2483 DAG.getConstant(-ShiftRightRequired, MVT::i64));
2489 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
2490 /// a mask and an extension. Returns true if a BFI was found and provides
2491 /// information on its surroundings.
2492 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
2495 if (N.getOpcode() == ISD::ZERO_EXTEND) {
2497 N = N.getOperand(0);
2500 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
2501 Mask = N->getConstantOperandVal(1);
2502 N = N.getOperand(0);
2504 // Mask is the whole width.
2505 Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
2508 if (N.getOpcode() == AArch64ISD::BFI) {
2516 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
2517 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
2518 /// can often be further combined with a larger mask. Ultimately, we want mask
2519 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
2520 static SDValue tryCombineToBFI(SDNode *N,
2521 TargetLowering::DAGCombinerInfo &DCI,
2522 const AArch64Subtarget *Subtarget) {
2523 SelectionDAG &DAG = DCI.DAG;
2525 EVT VT = N->getValueType(0);
2527 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2529 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
2530 // abandon the effort.
2531 SDValue LHS = N->getOperand(0);
2532 if (LHS.getOpcode() != ISD::AND)
2536 if (isa<ConstantSDNode>(LHS.getOperand(1)))
2537 LHSMask = LHS->getConstantOperandVal(1);
2541 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
2542 // is or abandon the effort.
2543 SDValue RHS = N->getOperand(1);
2544 if (RHS.getOpcode() != ISD::AND)
2548 if (isa<ConstantSDNode>(RHS.getOperand(1)))
2549 RHSMask = RHS->getConstantOperandVal(1);
2553 // Can't do anything if the masks are incompatible.
2554 if (LHSMask & RHSMask)
2557 // Now we need one of the masks to be a contiguous field. Without loss of
2558 // generality that should be the RHS one.
2559 SDValue Bitfield = LHS.getOperand(0);
2560 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
2561 // We know that LHS is a candidate new value, and RHS isn't already a better
2563 std::swap(LHS, RHS);
2564 std::swap(LHSMask, RHSMask);
2567 // We've done our best to put the right operands in the right places, all we
2568 // can do now is check whether a BFI exists.
2569 Bitfield = RHS.getOperand(0);
2570 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
2574 uint32_t Width = CountPopulation_64(RHSMask);
2575 assert(Width && "Expected non-zero bitfield width");
2577 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
2578 LHS.getOperand(0), Bitfield,
2579 DAG.getConstant(LSB, MVT::i64),
2580 DAG.getConstant(Width, MVT::i64));
2583 if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
2586 return DAG.getNode(ISD::AND, DL, VT, BFI,
2587 DAG.getConstant(LHSMask | RHSMask, VT));
2590 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
2591 /// original input. This is surprisingly common because SROA splits things up
2592 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
2593 /// on the low (say) byte of a word. This is then orred into the rest of the
2594 /// word afterwards.
2596 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
2598 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
2599 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
2601 static SDValue tryCombineToLargerBFI(SDNode *N,
2602 TargetLowering::DAGCombinerInfo &DCI,
2603 const AArch64Subtarget *Subtarget) {
2604 SelectionDAG &DAG = DCI.DAG;
2606 EVT VT = N->getValueType(0);
2608 // First job is to hunt for a MaskedBFI on either the left or right. Swap
2609 // operands if it's actually on the right.
2611 SDValue PossExtraMask;
2612 uint64_t ExistingMask = 0;
2613 bool Extended = false;
2614 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
2615 PossExtraMask = N->getOperand(1);
2616 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
2617 PossExtraMask = N->getOperand(0);
2621 // We can only combine a BFI with another compatible mask.
2622 if (PossExtraMask.getOpcode() != ISD::AND ||
2623 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
2626 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
2628 // Masks must be compatible.
2629 if (ExtraMask & ExistingMask)
2632 SDValue OldBFIVal = BFI.getOperand(0);
2633 SDValue NewBFIVal = BFI.getOperand(1);
2635 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
2636 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
2637 // need to be made compatible.
2638 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
2639 && "Invalid types for BFI");
2640 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
2641 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
2644 // We need the MaskedBFI to be combined with a mask of the *same* value.
2645 if (PossExtraMask.getOperand(0) != OldBFIVal)
2648 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
2649 OldBFIVal, NewBFIVal,
2650 BFI.getOperand(2), BFI.getOperand(3));
2652 // If the masking is trivial, we don't need to create it.
2653 if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
2656 return DAG.getNode(ISD::AND, DL, VT, BFI,
2657 DAG.getConstant(ExtraMask | ExistingMask, VT));
2660 /// An EXTR instruction is made up of two shifts, ORed together. This helper
2661 /// searches for and classifies those shifts.
2662 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
2664 if (N.getOpcode() == ISD::SHL)
2666 else if (N.getOpcode() == ISD::SRL)
2671 if (!isa<ConstantSDNode>(N.getOperand(1)))
2674 ShiftAmount = N->getConstantOperandVal(1);
2675 Src = N->getOperand(0);
2679 /// EXTR instruction extracts a contiguous chunk of bits from two existing
2680 /// registers viewed as a high/low pair. This function looks for the pattern:
2681 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
2682 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
2684 static SDValue tryCombineToEXTR(SDNode *N,
2685 TargetLowering::DAGCombinerInfo &DCI) {
2686 SelectionDAG &DAG = DCI.DAG;
2688 EVT VT = N->getValueType(0);
2690 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2692 if (VT != MVT::i32 && VT != MVT::i64)
2696 uint32_t ShiftLHS = 0;
2698 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
2702 uint32_t ShiftRHS = 0;
2704 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
2707 // If they're both trying to come from the high part of the register, they're
2708 // not really an EXTR.
2709 if (LHSFromHi == RHSFromHi)
2712 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
2716 std::swap(LHS, RHS);
2717 std::swap(ShiftLHS, ShiftRHS);
2720 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
2722 DAG.getConstant(ShiftRHS, MVT::i64));
2725 /// Target-specific dag combine xforms for ISD::OR
2726 static SDValue PerformORCombine(SDNode *N,
2727 TargetLowering::DAGCombinerInfo &DCI,
2728 const AArch64Subtarget *Subtarget) {
2730 SelectionDAG &DAG = DCI.DAG;
2731 EVT VT = N->getValueType(0);
2733 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2736 // Attempt to recognise bitfield-insert operations.
2737 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
2741 // Attempt to combine an existing MaskedBFI operation into one with a larger
2743 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
2747 Res = tryCombineToEXTR(N, DCI);
2754 /// Target-specific dag combine xforms for ISD::SRA
2755 static SDValue PerformSRACombine(SDNode *N,
2756 TargetLowering::DAGCombinerInfo &DCI) {
2758 SelectionDAG &DAG = DCI.DAG;
2760 EVT VT = N->getValueType(0);
2762 // We're looking for an SRA/SHL pair which form an SBFX.
2764 if (VT != MVT::i32 && VT != MVT::i64)
2767 if (!isa<ConstantSDNode>(N->getOperand(1)))
2770 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
2771 SDValue Shift = N->getOperand(0);
2773 if (Shift.getOpcode() != ISD::SHL)
2776 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
2779 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
2780 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
2781 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
2783 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
2786 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
2787 DAG.getConstant(LSB, MVT::i64),
2788 DAG.getConstant(LSB + Width - 1, MVT::i64));
2793 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2794 DAGCombinerInfo &DCI) const {
2795 switch (N->getOpcode()) {
2797 case ISD::AND: return PerformANDCombine(N, DCI);
2798 case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
2799 case ISD::SRA: return PerformSRACombine(N, DCI);
2804 AArch64TargetLowering::ConstraintType
2805 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
2806 if (Constraint.size() == 1) {
2807 switch (Constraint[0]) {
2809 case 'w': // An FP/SIMD vector register
2810 return C_RegisterClass;
2811 case 'I': // Constant that can be used with an ADD instruction
2812 case 'J': // Constant that can be used with a SUB instruction
2813 case 'K': // Constant that can be used with a 32-bit logical instruction
2814 case 'L': // Constant that can be used with a 64-bit logical instruction
2815 case 'M': // Constant that can be used as a 32-bit MOV immediate
2816 case 'N': // Constant that can be used as a 64-bit MOV immediate
2817 case 'Y': // Floating point constant zero
2818 case 'Z': // Integer constant zero
2820 case 'Q': // A memory reference with base register and no offset
2822 case 'S': // A symbolic address
2827 // FIXME: Ump, Utf, Usa, Ush
2828 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
2829 // whatever they may be
2830 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
2831 // Usa: An absolute symbolic address
2832 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
2833 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
2834 && Constraint != "Ush" && "Unimplemented constraints");
2836 return TargetLowering::getConstraintType(Constraint);
2839 TargetLowering::ConstraintWeight
2840 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
2841 const char *Constraint) const {
2843 llvm_unreachable("Constraint weight unimplemented");
2847 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2848 std::string &Constraint,
2849 std::vector<SDValue> &Ops,
2850 SelectionDAG &DAG) const {
2851 SDValue Result(0, 0);
2853 // Only length 1 constraints are C_Other.
2854 if (Constraint.size() != 1) return;
2856 // Only C_Other constraints get lowered like this. That means constants for us
2857 // so return early if there's no hope the constraint can be lowered.
2859 switch(Constraint[0]) {
2861 case 'I': case 'J': case 'K': case 'L':
2862 case 'M': case 'N': case 'Z': {
2863 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2867 uint64_t CVal = C->getZExtValue();
2870 switch (Constraint[0]) {
2872 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
2873 // is a peculiarly useless SUB constraint.
2874 llvm_unreachable("Unimplemented C_Other constraint");
2880 if (A64Imms::isLogicalImm(32, CVal, Bits))
2884 if (A64Imms::isLogicalImm(64, CVal, Bits))
2893 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2897 // An absolute symbolic address or label reference.
2898 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
2899 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
2900 GA->getValueType(0));
2901 } else if (const BlockAddressSDNode *BA
2902 = dyn_cast<BlockAddressSDNode>(Op)) {
2903 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
2904 BA->getValueType(0));
2905 } else if (const ExternalSymbolSDNode *ES
2906 = dyn_cast<ExternalSymbolSDNode>(Op)) {
2907 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
2908 ES->getValueType(0));
2914 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2915 if (CFP->isExactlyValue(0.0)) {
2916 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
2923 if (Result.getNode()) {
2924 Ops.push_back(Result);
2928 // It's an unknown constraint for us. Let generic code have a go.
2929 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2932 std::pair<unsigned, const TargetRegisterClass*>
2933 AArch64TargetLowering::getRegForInlineAsmConstraint(
2934 const std::string &Constraint,
2936 if (Constraint.size() == 1) {
2937 switch (Constraint[0]) {
2939 if (VT.getSizeInBits() <= 32)
2940 return std::make_pair(0U, &AArch64::GPR32RegClass);
2941 else if (VT == MVT::i64)
2942 return std::make_pair(0U, &AArch64::GPR64RegClass);
2946 return std::make_pair(0U, &AArch64::FPR16RegClass);
2947 else if (VT == MVT::f32)
2948 return std::make_pair(0U, &AArch64::FPR32RegClass);
2949 else if (VT == MVT::f64)
2950 return std::make_pair(0U, &AArch64::FPR64RegClass);
2951 else if (VT.getSizeInBits() == 64)
2952 return std::make_pair(0U, &AArch64::VPR64RegClass);
2953 else if (VT == MVT::f128)
2954 return std::make_pair(0U, &AArch64::FPR128RegClass);
2955 else if (VT.getSizeInBits() == 128)
2956 return std::make_pair(0U, &AArch64::VPR128RegClass);
2961 // Use the default implementation in TargetLowering to convert the register
2962 // constraint into a member of a register class.
2963 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);