1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
50 static cl::opt<AlignMode>
51 Align(cl::desc("Load/store alignment support"),
52 cl::Hidden, cl::init(NoStrictAlign),
54 clEnumValN(StrictAlign, "aarch64-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
57 "Allow unaligned memory accesses"),
60 // Place holder until extr generation is tested fully.
62 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
63 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
67 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
68 cl::desc("Allow AArch64 SLI/SRI formation"),
71 // FIXME: The necessary dtprel relocations don't seem to be supported
72 // well in the GNU bfd and gold linkers at the moment. Therefore, by
73 // default, for now, fall back to GeneralDynamic code generation.
74 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
75 "aarch64-elf-ldtls-generation", cl::Hidden,
76 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
79 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
80 const AArch64Subtarget &STI)
81 : TargetLowering(TM), Subtarget(&STI) {
83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
84 // we have to make something up. Arbitrarily, choose ZeroOrOne.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // When comparing vectors the result sets the different elements in the
87 // vector to all-one or all-zero.
88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
90 // Set up the register classes.
91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
94 if (Subtarget->hasFPARMv8()) {
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
101 if (Subtarget->hasNEON()) {
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
104 // Someone set us up the NEON.
105 addDRTypeForNEON(MVT::v2f32);
106 addDRTypeForNEON(MVT::v8i8);
107 addDRTypeForNEON(MVT::v4i16);
108 addDRTypeForNEON(MVT::v2i32);
109 addDRTypeForNEON(MVT::v1i64);
110 addDRTypeForNEON(MVT::v1f64);
111 addDRTypeForNEON(MVT::v4f16);
113 addQRTypeForNEON(MVT::v4f32);
114 addQRTypeForNEON(MVT::v2f64);
115 addQRTypeForNEON(MVT::v16i8);
116 addQRTypeForNEON(MVT::v8i16);
117 addQRTypeForNEON(MVT::v4i32);
118 addQRTypeForNEON(MVT::v2i64);
119 addQRTypeForNEON(MVT::v8f16);
122 // Compute derived properties from the register classes
123 computeRegisterProperties(Subtarget->getRegisterInfo());
125 // Provide all sorts of operation actions
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
128 setOperationAction(ISD::SETCC, MVT::i32, Custom);
129 setOperationAction(ISD::SETCC, MVT::i64, Custom);
130 setOperationAction(ISD::SETCC, MVT::f32, Custom);
131 setOperationAction(ISD::SETCC, MVT::f64, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::FREM, MVT::f32, Expand);
153 setOperationAction(ISD::FREM, MVT::f64, Expand);
154 setOperationAction(ISD::FREM, MVT::f80, Expand);
156 // Custom lowering hooks are needed for XOR
157 // to fold it into CSINC/CSINV.
158 setOperationAction(ISD::XOR, MVT::i32, Custom);
159 setOperationAction(ISD::XOR, MVT::i64, Custom);
161 // Virtually no operation on f128 is legal, but LLVM can't expand them when
162 // there's a valid register class, so we need custom operations in most cases.
163 setOperationAction(ISD::FABS, MVT::f128, Expand);
164 setOperationAction(ISD::FADD, MVT::f128, Custom);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
166 setOperationAction(ISD::FCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FDIV, MVT::f128, Custom);
168 setOperationAction(ISD::FMA, MVT::f128, Expand);
169 setOperationAction(ISD::FMUL, MVT::f128, Custom);
170 setOperationAction(ISD::FNEG, MVT::f128, Expand);
171 setOperationAction(ISD::FPOW, MVT::f128, Expand);
172 setOperationAction(ISD::FREM, MVT::f128, Expand);
173 setOperationAction(ISD::FRINT, MVT::f128, Expand);
174 setOperationAction(ISD::FSIN, MVT::f128, Expand);
175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
176 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
177 setOperationAction(ISD::FSUB, MVT::f128, Custom);
178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
179 setOperationAction(ISD::SETCC, MVT::f128, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT, MVT::f128, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
185 // Lowering for many of the conversions is actually specified by the non-f128
186 // type. The LowerXXX function will be trivial when f128 isn't involved.
187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
202 // Variable arguments.
203 setOperationAction(ISD::VASTART, MVT::Other, Custom);
204 setOperationAction(ISD::VAARG, MVT::Other, Custom);
205 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
206 setOperationAction(ISD::VAEND, MVT::Other, Expand);
208 // Variable-sized objects.
209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
213 // Exception handling.
214 // FIXME: These are guesses. Has this been defined yet?
215 setExceptionPointerRegister(AArch64::X0);
216 setExceptionSelectorRegister(AArch64::X1);
218 // Constant pool entries
219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
225 setOperationAction(ISD::ADDC, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i32, Custom);
227 setOperationAction(ISD::SUBC, MVT::i32, Custom);
228 setOperationAction(ISD::SUBE, MVT::i32, Custom);
229 setOperationAction(ISD::ADDC, MVT::i64, Custom);
230 setOperationAction(ISD::ADDE, MVT::i64, Custom);
231 setOperationAction(ISD::SUBC, MVT::i64, Custom);
232 setOperationAction(ISD::SUBE, MVT::i64, Custom);
234 // AArch64 lacks both left-rotate and popcount instructions.
235 setOperationAction(ISD::ROTL, MVT::i32, Expand);
236 setOperationAction(ISD::ROTL, MVT::i64, Expand);
238 // AArch64 doesn't have {U|S}MUL_LOHI.
239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
244 // counterparts, which AArch64 supports directly.
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
251 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
256 setOperationAction(ISD::SREM, MVT::i64, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i32, Expand);
260 setOperationAction(ISD::UREM, MVT::i64, Expand);
262 // Custom lower Add/Sub/Mul with overflow.
263 setOperationAction(ISD::SADDO, MVT::i32, Custom);
264 setOperationAction(ISD::SADDO, MVT::i64, Custom);
265 setOperationAction(ISD::UADDO, MVT::i32, Custom);
266 setOperationAction(ISD::UADDO, MVT::i64, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
268 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
269 setOperationAction(ISD::USUBO, MVT::i32, Custom);
270 setOperationAction(ISD::USUBO, MVT::i64, Custom);
271 setOperationAction(ISD::SMULO, MVT::i32, Custom);
272 setOperationAction(ISD::SMULO, MVT::i64, Custom);
273 setOperationAction(ISD::UMULO, MVT::i32, Custom);
274 setOperationAction(ISD::UMULO, MVT::i64, Custom);
276 setOperationAction(ISD::FSIN, MVT::f32, Expand);
277 setOperationAction(ISD::FSIN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FCOS, MVT::f64, Expand);
280 setOperationAction(ISD::FPOW, MVT::f32, Expand);
281 setOperationAction(ISD::FPOW, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285 // f16 is a storage-only type, always promote it to f32.
286 setOperationAction(ISD::SETCC, MVT::f16, Promote);
287 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
289 setOperationAction(ISD::SELECT, MVT::f16, Promote);
290 setOperationAction(ISD::FADD, MVT::f16, Promote);
291 setOperationAction(ISD::FSUB, MVT::f16, Promote);
292 setOperationAction(ISD::FMUL, MVT::f16, Promote);
293 setOperationAction(ISD::FDIV, MVT::f16, Promote);
294 setOperationAction(ISD::FREM, MVT::f16, Promote);
295 setOperationAction(ISD::FMA, MVT::f16, Promote);
296 setOperationAction(ISD::FNEG, MVT::f16, Promote);
297 setOperationAction(ISD::FABS, MVT::f16, Promote);
298 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
299 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
300 setOperationAction(ISD::FCOS, MVT::f16, Promote);
301 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
302 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
303 setOperationAction(ISD::FPOW, MVT::f16, Promote);
304 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
305 setOperationAction(ISD::FRINT, MVT::f16, Promote);
306 setOperationAction(ISD::FSIN, MVT::f16, Promote);
307 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
308 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
309 setOperationAction(ISD::FEXP, MVT::f16, Promote);
310 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
311 setOperationAction(ISD::FLOG, MVT::f16, Promote);
312 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
313 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
314 setOperationAction(ISD::FROUND, MVT::f16, Promote);
315 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
316 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
317 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
319 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
321 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
322 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
323 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
324 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
325 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
326 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
327 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
332 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
334 // Expand all other v4f16 operations.
335 // FIXME: We could generate better code by promoting some operations to
337 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
338 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
339 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
340 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
341 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
342 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
343 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
344 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
345 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
346 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
347 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
348 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
349 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
350 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
351 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
352 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
353 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
354 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
355 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
356 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
357 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
358 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
359 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
360 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
361 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
362 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
365 // v8f16 is also a storage-only type, so expand it.
366 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
367 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
368 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
369 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
370 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
371 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
372 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
373 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
374 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
375 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
376 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
377 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
378 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
379 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
380 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
381 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
382 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
383 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
384 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
385 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
386 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
387 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
388 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
389 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
390 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
391 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
392 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
393 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
394 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
395 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
396 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
398 // AArch64 has implementations of a lot of rounding-like FP operations.
399 for (MVT Ty : {MVT::f32, MVT::f64}) {
400 setOperationAction(ISD::FFLOOR, Ty, Legal);
401 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
402 setOperationAction(ISD::FCEIL, Ty, Legal);
403 setOperationAction(ISD::FRINT, Ty, Legal);
404 setOperationAction(ISD::FTRUNC, Ty, Legal);
405 setOperationAction(ISD::FROUND, Ty, Legal);
408 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
410 if (Subtarget->isTargetMachO()) {
411 // For iOS, we don't want to the normal expansion of a libcall to
412 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
414 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
415 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
417 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
418 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
421 // Make floating-point constants legal for the large code model, so they don't
422 // become loads from the constant pool.
423 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
424 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
425 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
428 // AArch64 does not have floating-point extending loads, i1 sign-extending
429 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
430 for (MVT VT : MVT::fp_valuetypes()) {
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
434 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
436 for (MVT VT : MVT::integer_valuetypes())
437 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
439 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
440 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
441 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
443 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
444 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
445 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
447 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
448 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
450 // Indexed loads and stores are supported.
451 for (unsigned im = (unsigned)ISD::PRE_INC;
452 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
453 setIndexedLoadAction(im, MVT::i8, Legal);
454 setIndexedLoadAction(im, MVT::i16, Legal);
455 setIndexedLoadAction(im, MVT::i32, Legal);
456 setIndexedLoadAction(im, MVT::i64, Legal);
457 setIndexedLoadAction(im, MVT::f64, Legal);
458 setIndexedLoadAction(im, MVT::f32, Legal);
459 setIndexedStoreAction(im, MVT::i8, Legal);
460 setIndexedStoreAction(im, MVT::i16, Legal);
461 setIndexedStoreAction(im, MVT::i32, Legal);
462 setIndexedStoreAction(im, MVT::i64, Legal);
463 setIndexedStoreAction(im, MVT::f64, Legal);
464 setIndexedStoreAction(im, MVT::f32, Legal);
468 setOperationAction(ISD::TRAP, MVT::Other, Legal);
470 // We combine OR nodes for bitfield operations.
471 setTargetDAGCombine(ISD::OR);
473 // Vector add and sub nodes may conceal a high-half opportunity.
474 // Also, try to fold ADD into CSINC/CSINV..
475 setTargetDAGCombine(ISD::ADD);
476 setTargetDAGCombine(ISD::SUB);
478 setTargetDAGCombine(ISD::XOR);
479 setTargetDAGCombine(ISD::SINT_TO_FP);
480 setTargetDAGCombine(ISD::UINT_TO_FP);
482 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
484 setTargetDAGCombine(ISD::ANY_EXTEND);
485 setTargetDAGCombine(ISD::ZERO_EXTEND);
486 setTargetDAGCombine(ISD::SIGN_EXTEND);
487 setTargetDAGCombine(ISD::BITCAST);
488 setTargetDAGCombine(ISD::CONCAT_VECTORS);
489 setTargetDAGCombine(ISD::STORE);
491 setTargetDAGCombine(ISD::MUL);
493 setTargetDAGCombine(ISD::SELECT);
494 setTargetDAGCombine(ISD::VSELECT);
495 setTargetDAGCombine(ISD::SELECT_CC);
497 setTargetDAGCombine(ISD::INTRINSIC_VOID);
498 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
499 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
501 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
502 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
503 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
505 setStackPointerRegisterToSaveRestore(AArch64::SP);
507 setSchedulingPreference(Sched::Hybrid);
510 MaskAndBranchFoldingIsLegal = true;
511 EnableExtLdPromotion = true;
513 setMinFunctionAlignment(2);
515 RequireStrictAlign = (Align == StrictAlign);
517 setHasExtractBitsInsn(true);
519 if (Subtarget->hasNEON()) {
520 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
521 // silliness like this:
522 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
523 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
524 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
525 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
526 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
527 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
528 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
529 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
530 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
531 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
532 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
533 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
534 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
535 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
536 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
537 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
538 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
539 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
540 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
541 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
542 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
543 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
544 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
545 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
546 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
548 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
549 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
550 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
551 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
552 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
554 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
556 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
557 // elements smaller than i32, so promote the input to i32 first.
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
561 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
562 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
563 // -> v8f16 conversions.
564 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
565 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
566 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
567 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
568 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
569 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
570 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
571 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
572 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
573 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
574 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
575 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
576 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
578 // AArch64 doesn't have MUL.2d:
579 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
580 // Custom handling for some quad-vector types to detect MULL.
581 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
582 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
583 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
585 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
586 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
587 // Likewise, narrowing and extending vector loads/stores aren't handled
589 for (MVT VT : MVT::vector_valuetypes()) {
590 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
592 setOperationAction(ISD::MULHS, VT, Expand);
593 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
594 setOperationAction(ISD::MULHU, VT, Expand);
595 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
597 setOperationAction(ISD::BSWAP, VT, Expand);
599 for (MVT InnerVT : MVT::vector_valuetypes()) {
600 setTruncStoreAction(VT, InnerVT, Expand);
601 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
602 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
603 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
607 // AArch64 has implementations of a lot of rounding-like FP operations.
608 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
609 setOperationAction(ISD::FFLOOR, Ty, Legal);
610 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
611 setOperationAction(ISD::FCEIL, Ty, Legal);
612 setOperationAction(ISD::FRINT, Ty, Legal);
613 setOperationAction(ISD::FTRUNC, Ty, Legal);
614 setOperationAction(ISD::FROUND, Ty, Legal);
618 // Prefer likely predicted branches to selects on out-of-order cores.
619 if (Subtarget->isCortexA57())
620 PredictableSelectIsExpensive = true;
623 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
624 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
625 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
626 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
628 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
629 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
630 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
631 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
632 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
634 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
635 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
638 // Mark vector float intrinsics as expand.
639 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
640 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
645 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
647 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
648 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
651 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
653 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
654 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
655 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
656 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
661 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
662 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
664 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
665 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
666 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
667 for (MVT InnerVT : MVT::all_valuetypes())
668 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
670 // CNT supports only B element sizes.
671 if (VT != MVT::v8i8 && VT != MVT::v16i8)
672 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
674 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
675 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
676 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
677 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
678 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
680 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
681 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
683 // [SU][MIN|MAX] are available for all NEON types apart from i64.
684 if (!VT.isFloatingPoint() &&
685 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
686 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
687 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
689 if (Subtarget->isLittleEndian()) {
690 for (unsigned im = (unsigned)ISD::PRE_INC;
691 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
692 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
693 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
698 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
699 addRegisterClass(VT, &AArch64::FPR64RegClass);
700 addTypeForNEON(VT, MVT::v2i32);
703 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
704 addRegisterClass(VT, &AArch64::FPR128RegClass);
705 addTypeForNEON(VT, MVT::v4i32);
708 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
711 return VT.changeVectorElementTypeToInteger();
714 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
715 /// Mask are known to be either zero or one and return them in the
716 /// KnownZero/KnownOne bitsets.
717 void AArch64TargetLowering::computeKnownBitsForTargetNode(
718 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
719 const SelectionDAG &DAG, unsigned Depth) const {
720 switch (Op.getOpcode()) {
723 case AArch64ISD::CSEL: {
724 APInt KnownZero2, KnownOne2;
725 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
726 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
727 KnownZero &= KnownZero2;
728 KnownOne &= KnownOne2;
731 case ISD::INTRINSIC_W_CHAIN: {
732 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
733 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
736 case Intrinsic::aarch64_ldaxr:
737 case Intrinsic::aarch64_ldxr: {
738 unsigned BitWidth = KnownOne.getBitWidth();
739 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
740 unsigned MemBits = VT.getScalarType().getSizeInBits();
741 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
747 case ISD::INTRINSIC_WO_CHAIN:
748 case ISD::INTRINSIC_VOID: {
749 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
753 case Intrinsic::aarch64_neon_umaxv:
754 case Intrinsic::aarch64_neon_uminv: {
755 // Figure out the datatype of the vector operand. The UMINV instruction
756 // will zero extend the result, so we can mark as known zero all the
757 // bits larger than the element datatype. 32-bit or larget doesn't need
758 // this as those are legal types and will be handled by isel directly.
759 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
760 unsigned BitWidth = KnownZero.getBitWidth();
761 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
762 assert(BitWidth >= 8 && "Unexpected width!");
763 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
765 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
766 assert(BitWidth >= 16 && "Unexpected width!");
767 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
777 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
782 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
783 const TargetLibraryInfo *libInfo) const {
784 return AArch64::createFastISel(funcInfo, libInfo);
787 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
788 switch ((AArch64ISD::NodeType)Opcode) {
789 case AArch64ISD::FIRST_NUMBER: break;
790 case AArch64ISD::CALL: return "AArch64ISD::CALL";
791 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
792 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
793 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
794 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
795 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
796 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
797 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
798 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
799 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
800 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
801 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
802 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
803 case AArch64ISD::ADC: return "AArch64ISD::ADC";
804 case AArch64ISD::SBC: return "AArch64ISD::SBC";
805 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
806 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
807 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
808 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
809 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
810 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
811 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
812 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
813 case AArch64ISD::DUP: return "AArch64ISD::DUP";
814 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
815 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
816 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
817 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
818 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
819 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
820 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
821 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
822 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
823 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
824 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
825 case AArch64ISD::BICi: return "AArch64ISD::BICi";
826 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
827 case AArch64ISD::BSL: return "AArch64ISD::BSL";
828 case AArch64ISD::NEG: return "AArch64ISD::NEG";
829 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
830 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
831 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
832 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
833 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
834 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
835 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
836 case AArch64ISD::REV16: return "AArch64ISD::REV16";
837 case AArch64ISD::REV32: return "AArch64ISD::REV32";
838 case AArch64ISD::REV64: return "AArch64ISD::REV64";
839 case AArch64ISD::EXT: return "AArch64ISD::EXT";
840 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
841 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
842 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
843 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
844 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
845 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
846 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
847 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
848 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
849 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
850 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
851 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
852 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
853 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
854 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
855 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
856 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
857 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
858 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
859 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
860 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
861 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
862 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
863 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
864 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
865 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
866 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
867 case AArch64ISD::NOT: return "AArch64ISD::NOT";
868 case AArch64ISD::BIT: return "AArch64ISD::BIT";
869 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
870 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
871 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
872 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
873 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
874 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
875 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
876 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
877 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
878 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
879 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
880 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
881 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
882 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
883 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
884 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
885 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
886 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
887 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
888 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
889 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
890 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
891 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
892 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
893 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
894 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
895 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
896 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
897 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
898 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
899 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
900 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
901 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
902 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
903 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
904 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
905 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
906 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
907 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
908 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
914 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
915 MachineBasicBlock *MBB) const {
916 // We materialise the F128CSEL pseudo-instruction as some control flow and a
920 // [... previous instrs leading to comparison ...]
926 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
928 MachineFunction *MF = MBB->getParent();
929 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
930 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
931 DebugLoc DL = MI->getDebugLoc();
932 MachineFunction::iterator It = MBB;
935 unsigned DestReg = MI->getOperand(0).getReg();
936 unsigned IfTrueReg = MI->getOperand(1).getReg();
937 unsigned IfFalseReg = MI->getOperand(2).getReg();
938 unsigned CondCode = MI->getOperand(3).getImm();
939 bool NZCVKilled = MI->getOperand(4).isKill();
941 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
942 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
943 MF->insert(It, TrueBB);
944 MF->insert(It, EndBB);
946 // Transfer rest of current basic-block to EndBB
947 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
949 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
951 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
952 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
953 MBB->addSuccessor(TrueBB);
954 MBB->addSuccessor(EndBB);
956 // TrueBB falls through to the end.
957 TrueBB->addSuccessor(EndBB);
960 TrueBB->addLiveIn(AArch64::NZCV);
961 EndBB->addLiveIn(AArch64::NZCV);
964 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
970 MI->eraseFromParent();
975 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
976 MachineBasicBlock *BB) const {
977 switch (MI->getOpcode()) {
982 llvm_unreachable("Unexpected instruction for custom inserter!");
984 case AArch64::F128CSEL:
985 return EmitF128CSEL(MI, BB);
987 case TargetOpcode::STACKMAP:
988 case TargetOpcode::PATCHPOINT:
989 return emitPatchPoint(MI, BB);
993 //===----------------------------------------------------------------------===//
994 // AArch64 Lowering private implementation.
995 //===----------------------------------------------------------------------===//
997 //===----------------------------------------------------------------------===//
999 //===----------------------------------------------------------------------===//
1001 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1003 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1006 llvm_unreachable("Unknown condition code!");
1008 return AArch64CC::NE;
1010 return AArch64CC::EQ;
1012 return AArch64CC::GT;
1014 return AArch64CC::GE;
1016 return AArch64CC::LT;
1018 return AArch64CC::LE;
1020 return AArch64CC::HI;
1022 return AArch64CC::HS;
1024 return AArch64CC::LO;
1026 return AArch64CC::LS;
1030 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1031 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1032 AArch64CC::CondCode &CondCode,
1033 AArch64CC::CondCode &CondCode2) {
1034 CondCode2 = AArch64CC::AL;
1037 llvm_unreachable("Unknown FP condition!");
1040 CondCode = AArch64CC::EQ;
1044 CondCode = AArch64CC::GT;
1048 CondCode = AArch64CC::GE;
1051 CondCode = AArch64CC::MI;
1054 CondCode = AArch64CC::LS;
1057 CondCode = AArch64CC::MI;
1058 CondCode2 = AArch64CC::GT;
1061 CondCode = AArch64CC::VC;
1064 CondCode = AArch64CC::VS;
1067 CondCode = AArch64CC::EQ;
1068 CondCode2 = AArch64CC::VS;
1071 CondCode = AArch64CC::HI;
1074 CondCode = AArch64CC::PL;
1078 CondCode = AArch64CC::LT;
1082 CondCode = AArch64CC::LE;
1086 CondCode = AArch64CC::NE;
1091 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1092 /// CC usable with the vector instructions. Fewer operations are available
1093 /// without a real NZCV register, so we have to use less efficient combinations
1094 /// to get the same effect.
1095 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1096 AArch64CC::CondCode &CondCode,
1097 AArch64CC::CondCode &CondCode2,
1102 // Mostly the scalar mappings work fine.
1103 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1106 Invert = true; // Fallthrough
1108 CondCode = AArch64CC::MI;
1109 CondCode2 = AArch64CC::GE;
1116 // All of the compare-mask comparisons are ordered, but we can switch
1117 // between the two by a double inversion. E.g. ULE == !OGT.
1119 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1124 static bool isLegalArithImmed(uint64_t C) {
1125 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1126 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1129 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1130 SDLoc dl, SelectionDAG &DAG) {
1131 EVT VT = LHS.getValueType();
1133 if (VT.isFloatingPoint())
1134 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1136 // The CMP instruction is just an alias for SUBS, and representing it as
1137 // SUBS means that it's possible to get CSE with subtract operations.
1138 // A later phase can perform the optimization of setting the destination
1139 // register to WZR/XZR if it ends up being unused.
1140 unsigned Opcode = AArch64ISD::SUBS;
1142 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1143 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1144 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1145 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1146 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1147 // can be set differently by this operation. It comes down to whether
1148 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1149 // everything is fine. If not then the optimization is wrong. Thus general
1150 // comparisons are only valid if op2 != 0.
1152 // So, finally, the only LLVM-native comparisons that don't mention C and V
1153 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1154 // the absence of information about op2.
1155 Opcode = AArch64ISD::ADDS;
1156 RHS = RHS.getOperand(1);
1157 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1158 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1159 !isUnsignedIntSetCC(CC)) {
1160 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1161 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1162 // of the signed comparisons.
1163 Opcode = AArch64ISD::ANDS;
1164 RHS = LHS.getOperand(1);
1165 LHS = LHS.getOperand(0);
1168 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1172 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1173 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1175 AArch64CC::CondCode AArch64CC;
1176 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1177 EVT VT = RHS.getValueType();
1178 uint64_t C = RHSC->getZExtValue();
1179 if (!isLegalArithImmed(C)) {
1180 // Constant does not fit, try adjusting it by one?
1186 if ((VT == MVT::i32 && C != 0x80000000 &&
1187 isLegalArithImmed((uint32_t)(C - 1))) ||
1188 (VT == MVT::i64 && C != 0x80000000ULL &&
1189 isLegalArithImmed(C - 1ULL))) {
1190 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1191 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1192 RHS = DAG.getConstant(C, dl, VT);
1197 if ((VT == MVT::i32 && C != 0 &&
1198 isLegalArithImmed((uint32_t)(C - 1))) ||
1199 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1200 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1201 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1202 RHS = DAG.getConstant(C, dl, VT);
1207 if ((VT == MVT::i32 && C != INT32_MAX &&
1208 isLegalArithImmed((uint32_t)(C + 1))) ||
1209 (VT == MVT::i64 && C != INT64_MAX &&
1210 isLegalArithImmed(C + 1ULL))) {
1211 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1212 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1213 RHS = DAG.getConstant(C, dl, VT);
1218 if ((VT == MVT::i32 && C != UINT32_MAX &&
1219 isLegalArithImmed((uint32_t)(C + 1))) ||
1220 (VT == MVT::i64 && C != UINT64_MAX &&
1221 isLegalArithImmed(C + 1ULL))) {
1222 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1223 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1224 RHS = DAG.getConstant(C, dl, VT);
1230 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1231 // For the i8 operand, the largest immediate is 255, so this can be easily
1232 // encoded in the compare instruction. For the i16 operand, however, the
1233 // largest immediate cannot be encoded in the compare.
1234 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1235 // constant. For example,
1237 // ldrh w0, [x0, #0]
1240 // ldrsh w0, [x0, #0]
1242 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1243 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1244 // both the LHS and RHS are truely zero extended and to make sure the
1245 // transformation is profitable.
1246 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1247 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1248 isa<LoadSDNode>(LHS)) {
1249 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1250 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1251 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1252 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1253 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1255 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1256 DAG.getValueType(MVT::i16));
1257 Cmp = emitComparison(SExt,
1258 DAG.getConstant(ValueofRHS, dl,
1259 RHS.getValueType()),
1261 AArch64CC = changeIntCCToAArch64CC(CC);
1262 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1268 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1269 AArch64CC = changeIntCCToAArch64CC(CC);
1270 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1274 static std::pair<SDValue, SDValue>
1275 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1276 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1277 "Unsupported value type");
1278 SDValue Value, Overflow;
1280 SDValue LHS = Op.getOperand(0);
1281 SDValue RHS = Op.getOperand(1);
1283 switch (Op.getOpcode()) {
1285 llvm_unreachable("Unknown overflow instruction!");
1287 Opc = AArch64ISD::ADDS;
1291 Opc = AArch64ISD::ADDS;
1295 Opc = AArch64ISD::SUBS;
1299 Opc = AArch64ISD::SUBS;
1302 // Multiply needs a little bit extra work.
1306 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1307 if (Op.getValueType() == MVT::i32) {
1308 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1309 // For a 32 bit multiply with overflow check we want the instruction
1310 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1311 // need to generate the following pattern:
1312 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1313 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1314 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1315 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1316 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1317 DAG.getConstant(0, DL, MVT::i64));
1318 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1319 // operation. We need to clear out the upper 32 bits, because we used a
1320 // widening multiply that wrote all 64 bits. In the end this should be a
1322 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1324 // The signed overflow check requires more than just a simple check for
1325 // any bit set in the upper 32 bits of the result. These bits could be
1326 // just the sign bits of a negative number. To perform the overflow
1327 // check we have to arithmetic shift right the 32nd bit of the result by
1328 // 31 bits. Then we compare the result to the upper 32 bits.
1329 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1330 DAG.getConstant(32, DL, MVT::i64));
1331 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1332 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1333 DAG.getConstant(31, DL, MVT::i64));
1334 // It is important that LowerBits is last, otherwise the arithmetic
1335 // shift will not be folded into the compare (SUBS).
1336 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1337 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1340 // The overflow check for unsigned multiply is easy. We only need to
1341 // check if any of the upper 32 bits are set. This can be done with a
1342 // CMP (shifted register). For that we need to generate the following
1344 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1345 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1346 DAG.getConstant(32, DL, MVT::i64));
1347 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1349 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1350 DAG.getConstant(0, DL, MVT::i64),
1351 UpperBits).getValue(1);
1355 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1356 // For the 64 bit multiply
1357 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1359 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1360 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1361 DAG.getConstant(63, DL, MVT::i64));
1362 // It is important that LowerBits is last, otherwise the arithmetic
1363 // shift will not be folded into the compare (SUBS).
1364 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1365 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1368 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1369 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1371 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1372 DAG.getConstant(0, DL, MVT::i64),
1373 UpperBits).getValue(1);
1380 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1382 // Emit the AArch64 operation with overflow check.
1383 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1384 Overflow = Value.getValue(1);
1386 return std::make_pair(Value, Overflow);
1389 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1390 RTLIB::Libcall Call) const {
1391 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1392 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1396 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1397 SDValue Sel = Op.getOperand(0);
1398 SDValue Other = Op.getOperand(1);
1400 // If neither operand is a SELECT_CC, give up.
1401 if (Sel.getOpcode() != ISD::SELECT_CC)
1402 std::swap(Sel, Other);
1403 if (Sel.getOpcode() != ISD::SELECT_CC)
1406 // The folding we want to perform is:
1407 // (xor x, (select_cc a, b, cc, 0, -1) )
1409 // (csel x, (xor x, -1), cc ...)
1411 // The latter will get matched to a CSINV instruction.
1413 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1414 SDValue LHS = Sel.getOperand(0);
1415 SDValue RHS = Sel.getOperand(1);
1416 SDValue TVal = Sel.getOperand(2);
1417 SDValue FVal = Sel.getOperand(3);
1420 // FIXME: This could be generalized to non-integer comparisons.
1421 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1424 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1425 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1427 // The values aren't constants, this isn't the pattern we're looking for.
1428 if (!CFVal || !CTVal)
1431 // We can commute the SELECT_CC by inverting the condition. This
1432 // might be needed to make this fit into a CSINV pattern.
1433 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1434 std::swap(TVal, FVal);
1435 std::swap(CTVal, CFVal);
1436 CC = ISD::getSetCCInverse(CC, true);
1439 // If the constants line up, perform the transform!
1440 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1442 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1445 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1446 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1448 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1455 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1456 EVT VT = Op.getValueType();
1458 // Let legalize expand this if it isn't a legal type yet.
1459 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1462 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1465 bool ExtraOp = false;
1466 switch (Op.getOpcode()) {
1468 llvm_unreachable("Invalid code");
1470 Opc = AArch64ISD::ADDS;
1473 Opc = AArch64ISD::SUBS;
1476 Opc = AArch64ISD::ADCS;
1480 Opc = AArch64ISD::SBCS;
1486 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1487 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1491 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1492 // Let legalize expand this if it isn't a legal type yet.
1493 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1497 AArch64CC::CondCode CC;
1498 // The actual operation that sets the overflow or carry flag.
1499 SDValue Value, Overflow;
1500 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1502 // We use 0 and 1 as false and true values.
1503 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1504 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1506 // We use an inverted condition, because the conditional select is inverted
1507 // too. This will allow it to be selected to a single instruction:
1508 // CSINC Wd, WZR, WZR, invert(cond).
1509 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1510 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1513 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1514 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1517 // Prefetch operands are:
1518 // 1: Address to prefetch
1520 // 3: int locality (0 = no locality ... 3 = extreme locality)
1521 // 4: bool isDataCache
1522 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1524 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1525 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1526 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1528 bool IsStream = !Locality;
1529 // When the locality number is set
1531 // The front-end should have filtered out the out-of-range values
1532 assert(Locality <= 3 && "Prefetch locality out-of-range");
1533 // The locality degree is the opposite of the cache speed.
1534 // Put the number the other way around.
1535 // The encoding starts at 0 for level 1
1536 Locality = 3 - Locality;
1539 // built the mask value encoding the expected behavior.
1540 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1541 (!IsData << 3) | // IsDataCache bit
1542 (Locality << 1) | // Cache level bits
1543 (unsigned)IsStream; // Stream bit
1544 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1545 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1548 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1549 SelectionDAG &DAG) const {
1550 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1553 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1555 return LowerF128Call(Op, DAG, LC);
1558 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1559 SelectionDAG &DAG) const {
1560 if (Op.getOperand(0).getValueType() != MVT::f128) {
1561 // It's legal except when f128 is involved
1566 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1568 // FP_ROUND node has a second operand indicating whether it is known to be
1569 // precise. That doesn't take part in the LibCall so we can't directly use
1571 SDValue SrcVal = Op.getOperand(0);
1572 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1573 /*isSigned*/ false, SDLoc(Op)).first;
1576 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1577 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1578 // Any additional optimization in this function should be recorded
1579 // in the cost tables.
1580 EVT InVT = Op.getOperand(0).getValueType();
1581 EVT VT = Op.getValueType();
1583 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1586 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1588 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1591 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1594 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1595 VT.getVectorNumElements());
1596 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1597 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1600 // Type changing conversions are illegal.
1604 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1605 SelectionDAG &DAG) const {
1606 if (Op.getOperand(0).getValueType().isVector())
1607 return LowerVectorFP_TO_INT(Op, DAG);
1609 // f16 conversions are promoted to f32.
1610 if (Op.getOperand(0).getValueType() == MVT::f16) {
1613 Op.getOpcode(), dl, Op.getValueType(),
1614 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1617 if (Op.getOperand(0).getValueType() != MVT::f128) {
1618 // It's legal except when f128 is involved
1623 if (Op.getOpcode() == ISD::FP_TO_SINT)
1624 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1626 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1628 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1629 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1633 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1634 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1635 // Any additional optimization in this function should be recorded
1636 // in the cost tables.
1637 EVT VT = Op.getValueType();
1639 SDValue In = Op.getOperand(0);
1640 EVT InVT = In.getValueType();
1642 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1644 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1645 InVT.getVectorNumElements());
1646 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1647 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1650 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1652 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1653 EVT CastVT = VT.changeVectorElementTypeToInteger();
1654 In = DAG.getNode(CastOpc, dl, CastVT, In);
1655 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1661 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1662 SelectionDAG &DAG) const {
1663 if (Op.getValueType().isVector())
1664 return LowerVectorINT_TO_FP(Op, DAG);
1666 // f16 conversions are promoted to f32.
1667 if (Op.getValueType() == MVT::f16) {
1670 ISD::FP_ROUND, dl, MVT::f16,
1671 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1672 DAG.getIntPtrConstant(0, dl));
1675 // i128 conversions are libcalls.
1676 if (Op.getOperand(0).getValueType() == MVT::i128)
1679 // Other conversions are legal, unless it's to the completely software-based
1681 if (Op.getValueType() != MVT::f128)
1685 if (Op.getOpcode() == ISD::SINT_TO_FP)
1686 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1688 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1690 return LowerF128Call(Op, DAG, LC);
1693 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1694 SelectionDAG &DAG) const {
1695 // For iOS, we want to call an alternative entry point: __sincos_stret,
1696 // which returns the values in two S / D registers.
1698 SDValue Arg = Op.getOperand(0);
1699 EVT ArgVT = Arg.getValueType();
1700 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1707 Entry.isSExt = false;
1708 Entry.isZExt = false;
1709 Args.push_back(Entry);
1711 const char *LibcallName =
1712 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1713 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1715 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1716 TargetLowering::CallLoweringInfo CLI(DAG);
1717 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1718 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1720 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1721 return CallResult.first;
1724 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1725 if (Op.getValueType() != MVT::f16)
1728 assert(Op.getOperand(0).getValueType() == MVT::i16);
1731 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1732 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1734 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1735 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1739 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1740 if (OrigVT.getSizeInBits() >= 64)
1743 assert(OrigVT.isSimple() && "Expecting a simple value type");
1745 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1746 switch (OrigSimpleTy) {
1747 default: llvm_unreachable("Unexpected Vector Type");
1756 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1759 unsigned ExtOpcode) {
1760 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1761 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1762 // 64-bits we need to insert a new extension so that it will be 64-bits.
1763 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1764 if (OrigTy.getSizeInBits() >= 64)
1767 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1768 EVT NewVT = getExtensionTo64Bits(OrigTy);
1770 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1773 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1775 EVT VT = N->getValueType(0);
1777 if (N->getOpcode() != ISD::BUILD_VECTOR)
1780 for (const SDValue &Elt : N->op_values()) {
1781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1782 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1783 unsigned HalfSize = EltSize / 2;
1785 if (!isIntN(HalfSize, C->getSExtValue()))
1788 if (!isUIntN(HalfSize, C->getZExtValue()))
1799 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1800 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1801 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1802 N->getOperand(0)->getValueType(0),
1806 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1807 EVT VT = N->getValueType(0);
1809 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1810 unsigned NumElts = VT.getVectorNumElements();
1811 MVT TruncVT = MVT::getIntegerVT(EltSize);
1812 SmallVector<SDValue, 8> Ops;
1813 for (unsigned i = 0; i != NumElts; ++i) {
1814 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1815 const APInt &CInt = C->getAPIntValue();
1816 // Element types smaller than 32 bits are not legal, so use i32 elements.
1817 // The values are implicitly truncated so sext vs. zext doesn't matter.
1818 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
1820 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1821 MVT::getVectorVT(TruncVT, NumElts), Ops);
1824 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1825 if (N->getOpcode() == ISD::SIGN_EXTEND)
1827 if (isExtendedBUILD_VECTOR(N, DAG, true))
1832 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1833 if (N->getOpcode() == ISD::ZERO_EXTEND)
1835 if (isExtendedBUILD_VECTOR(N, DAG, false))
1840 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1841 unsigned Opcode = N->getOpcode();
1842 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1843 SDNode *N0 = N->getOperand(0).getNode();
1844 SDNode *N1 = N->getOperand(1).getNode();
1845 return N0->hasOneUse() && N1->hasOneUse() &&
1846 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1851 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1852 unsigned Opcode = N->getOpcode();
1853 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1854 SDNode *N0 = N->getOperand(0).getNode();
1855 SDNode *N1 = N->getOperand(1).getNode();
1856 return N0->hasOneUse() && N1->hasOneUse() &&
1857 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1862 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1863 // Multiplications are only custom-lowered for 128-bit vectors so that
1864 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1865 EVT VT = Op.getValueType();
1866 assert(VT.is128BitVector() && VT.isInteger() &&
1867 "unexpected type for custom-lowering ISD::MUL");
1868 SDNode *N0 = Op.getOperand(0).getNode();
1869 SDNode *N1 = Op.getOperand(1).getNode();
1870 unsigned NewOpc = 0;
1872 bool isN0SExt = isSignExtended(N0, DAG);
1873 bool isN1SExt = isSignExtended(N1, DAG);
1874 if (isN0SExt && isN1SExt)
1875 NewOpc = AArch64ISD::SMULL;
1877 bool isN0ZExt = isZeroExtended(N0, DAG);
1878 bool isN1ZExt = isZeroExtended(N1, DAG);
1879 if (isN0ZExt && isN1ZExt)
1880 NewOpc = AArch64ISD::UMULL;
1881 else if (isN1SExt || isN1ZExt) {
1882 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1883 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1884 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1885 NewOpc = AArch64ISD::SMULL;
1887 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1888 NewOpc = AArch64ISD::UMULL;
1890 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1892 NewOpc = AArch64ISD::UMULL;
1898 if (VT == MVT::v2i64)
1899 // Fall through to expand this. It is not legal.
1902 // Other vector multiplications are legal.
1907 // Legalize to a S/UMULL instruction
1910 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1912 Op0 = skipExtensionForVectorMULL(N0, DAG);
1913 assert(Op0.getValueType().is64BitVector() &&
1914 Op1.getValueType().is64BitVector() &&
1915 "unexpected types for extended operands to VMULL");
1916 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1918 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1919 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1920 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1921 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1922 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1923 EVT Op1VT = Op1.getValueType();
1924 return DAG.getNode(N0->getOpcode(), DL, VT,
1925 DAG.getNode(NewOpc, DL, VT,
1926 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1927 DAG.getNode(NewOpc, DL, VT,
1928 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1931 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1932 SelectionDAG &DAG) const {
1933 switch (Op.getOpcode()) {
1935 llvm_unreachable("unimplemented operand");
1938 return LowerBITCAST(Op, DAG);
1939 case ISD::GlobalAddress:
1940 return LowerGlobalAddress(Op, DAG);
1941 case ISD::GlobalTLSAddress:
1942 return LowerGlobalTLSAddress(Op, DAG);
1944 return LowerSETCC(Op, DAG);
1946 return LowerBR_CC(Op, DAG);
1948 return LowerSELECT(Op, DAG);
1949 case ISD::SELECT_CC:
1950 return LowerSELECT_CC(Op, DAG);
1951 case ISD::JumpTable:
1952 return LowerJumpTable(Op, DAG);
1953 case ISD::ConstantPool:
1954 return LowerConstantPool(Op, DAG);
1955 case ISD::BlockAddress:
1956 return LowerBlockAddress(Op, DAG);
1958 return LowerVASTART(Op, DAG);
1960 return LowerVACOPY(Op, DAG);
1962 return LowerVAARG(Op, DAG);
1967 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1974 return LowerXALUO(Op, DAG);
1976 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1978 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1980 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1982 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1984 return LowerFP_ROUND(Op, DAG);
1985 case ISD::FP_EXTEND:
1986 return LowerFP_EXTEND(Op, DAG);
1987 case ISD::FRAMEADDR:
1988 return LowerFRAMEADDR(Op, DAG);
1989 case ISD::RETURNADDR:
1990 return LowerRETURNADDR(Op, DAG);
1991 case ISD::INSERT_VECTOR_ELT:
1992 return LowerINSERT_VECTOR_ELT(Op, DAG);
1993 case ISD::EXTRACT_VECTOR_ELT:
1994 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1995 case ISD::BUILD_VECTOR:
1996 return LowerBUILD_VECTOR(Op, DAG);
1997 case ISD::VECTOR_SHUFFLE:
1998 return LowerVECTOR_SHUFFLE(Op, DAG);
1999 case ISD::EXTRACT_SUBVECTOR:
2000 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2004 return LowerVectorSRA_SRL_SHL(Op, DAG);
2005 case ISD::SHL_PARTS:
2006 return LowerShiftLeftParts(Op, DAG);
2007 case ISD::SRL_PARTS:
2008 case ISD::SRA_PARTS:
2009 return LowerShiftRightParts(Op, DAG);
2011 return LowerCTPOP(Op, DAG);
2012 case ISD::FCOPYSIGN:
2013 return LowerFCOPYSIGN(Op, DAG);
2015 return LowerVectorAND(Op, DAG);
2017 return LowerVectorOR(Op, DAG);
2019 return LowerXOR(Op, DAG);
2021 return LowerPREFETCH(Op, DAG);
2022 case ISD::SINT_TO_FP:
2023 case ISD::UINT_TO_FP:
2024 return LowerINT_TO_FP(Op, DAG);
2025 case ISD::FP_TO_SINT:
2026 case ISD::FP_TO_UINT:
2027 return LowerFP_TO_INT(Op, DAG);
2029 return LowerFSINCOS(Op, DAG);
2031 return LowerMUL(Op, DAG);
2035 /// getFunctionAlignment - Return the Log2 alignment of this function.
2036 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2040 //===----------------------------------------------------------------------===//
2041 // Calling Convention Implementation
2042 //===----------------------------------------------------------------------===//
2044 #include "AArch64GenCallingConv.inc"
2046 /// Selects the correct CCAssignFn for a given CallingConvention value.
2047 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2048 bool IsVarArg) const {
2051 llvm_unreachable("Unsupported calling convention.");
2052 case CallingConv::WebKit_JS:
2053 return CC_AArch64_WebKit_JS;
2054 case CallingConv::GHC:
2055 return CC_AArch64_GHC;
2056 case CallingConv::C:
2057 case CallingConv::Fast:
2058 if (!Subtarget->isTargetDarwin())
2059 return CC_AArch64_AAPCS;
2060 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2064 SDValue AArch64TargetLowering::LowerFormalArguments(
2065 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2066 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2067 SmallVectorImpl<SDValue> &InVals) const {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 MachineFrameInfo *MFI = MF.getFrameInfo();
2071 // Assign locations to all of the incoming arguments.
2072 SmallVector<CCValAssign, 16> ArgLocs;
2073 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2076 // At this point, Ins[].VT may already be promoted to i32. To correctly
2077 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2078 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2079 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2080 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2082 unsigned NumArgs = Ins.size();
2083 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2084 unsigned CurArgIdx = 0;
2085 for (unsigned i = 0; i != NumArgs; ++i) {
2086 MVT ValVT = Ins[i].VT;
2087 if (Ins[i].isOrigArg()) {
2088 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2089 CurArgIdx = Ins[i].getOrigArgIndex();
2091 // Get type of the original argument.
2092 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2093 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2094 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2095 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2097 else if (ActualMVT == MVT::i16)
2100 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2102 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2103 assert(!Res && "Call operand has unhandled type");
2106 assert(ArgLocs.size() == Ins.size());
2107 SmallVector<SDValue, 16> ArgValues;
2108 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2109 CCValAssign &VA = ArgLocs[i];
2111 if (Ins[i].Flags.isByVal()) {
2112 // Byval is used for HFAs in the PCS, but the system should work in a
2113 // non-compliant manner for larger structs.
2114 EVT PtrTy = getPointerTy();
2115 int Size = Ins[i].Flags.getByValSize();
2116 unsigned NumRegs = (Size + 7) / 8;
2118 // FIXME: This works on big-endian for composite byvals, which are the common
2119 // case. It should also work for fundamental types too.
2121 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2122 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2123 InVals.push_back(FrameIdxN);
2128 if (VA.isRegLoc()) {
2129 // Arguments stored in registers.
2130 EVT RegVT = VA.getLocVT();
2133 const TargetRegisterClass *RC;
2135 if (RegVT == MVT::i32)
2136 RC = &AArch64::GPR32RegClass;
2137 else if (RegVT == MVT::i64)
2138 RC = &AArch64::GPR64RegClass;
2139 else if (RegVT == MVT::f16)
2140 RC = &AArch64::FPR16RegClass;
2141 else if (RegVT == MVT::f32)
2142 RC = &AArch64::FPR32RegClass;
2143 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2144 RC = &AArch64::FPR64RegClass;
2145 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2146 RC = &AArch64::FPR128RegClass;
2148 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2150 // Transform the arguments in physical registers into virtual ones.
2151 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2152 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2154 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2155 // to 64 bits. Insert an assert[sz]ext to capture this, then
2156 // truncate to the right size.
2157 switch (VA.getLocInfo()) {
2159 llvm_unreachable("Unknown loc info!");
2160 case CCValAssign::Full:
2162 case CCValAssign::BCvt:
2163 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2165 case CCValAssign::AExt:
2166 case CCValAssign::SExt:
2167 case CCValAssign::ZExt:
2168 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2169 // nodes after our lowering.
2170 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2174 InVals.push_back(ArgValue);
2176 } else { // VA.isRegLoc()
2177 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2178 unsigned ArgOffset = VA.getLocMemOffset();
2179 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2181 uint32_t BEAlign = 0;
2182 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2183 !Ins[i].Flags.isInConsecutiveRegs())
2184 BEAlign = 8 - ArgSize;
2186 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2188 // Create load nodes to retrieve arguments from the stack.
2189 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2192 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2193 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2194 MVT MemVT = VA.getValVT();
2196 switch (VA.getLocInfo()) {
2199 case CCValAssign::BCvt:
2200 MemVT = VA.getLocVT();
2202 case CCValAssign::SExt:
2203 ExtType = ISD::SEXTLOAD;
2205 case CCValAssign::ZExt:
2206 ExtType = ISD::ZEXTLOAD;
2208 case CCValAssign::AExt:
2209 ExtType = ISD::EXTLOAD;
2213 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2214 MachinePointerInfo::getFixedStack(FI),
2215 MemVT, false, false, false, 0);
2217 InVals.push_back(ArgValue);
2223 if (!Subtarget->isTargetDarwin()) {
2224 // The AAPCS variadic function ABI is identical to the non-variadic
2225 // one. As a result there may be more arguments in registers and we should
2226 // save them for future reference.
2227 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2230 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2231 // This will point to the next argument passed via stack.
2232 unsigned StackOffset = CCInfo.getNextStackOffset();
2233 // We currently pass all varargs at 8-byte alignment.
2234 StackOffset = ((StackOffset + 7) & ~7);
2235 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2238 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2239 unsigned StackArgSize = CCInfo.getNextStackOffset();
2240 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2241 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2242 // This is a non-standard ABI so by fiat I say we're allowed to make full
2243 // use of the stack area to be popped, which must be aligned to 16 bytes in
2245 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2247 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2248 // a multiple of 16.
2249 FuncInfo->setArgumentStackToRestore(StackArgSize);
2251 // This realignment carries over to the available bytes below. Our own
2252 // callers will guarantee the space is free by giving an aligned value to
2255 // Even if we're not expected to free up the space, it's useful to know how
2256 // much is there while considering tail calls (because we can reuse it).
2257 FuncInfo->setBytesInStackArgArea(StackArgSize);
2262 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2263 SelectionDAG &DAG, SDLoc DL,
2264 SDValue &Chain) const {
2265 MachineFunction &MF = DAG.getMachineFunction();
2266 MachineFrameInfo *MFI = MF.getFrameInfo();
2267 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2269 SmallVector<SDValue, 8> MemOps;
2271 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2272 AArch64::X3, AArch64::X4, AArch64::X5,
2273 AArch64::X6, AArch64::X7 };
2274 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2275 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2277 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2279 if (GPRSaveSize != 0) {
2280 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2282 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2284 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2285 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2286 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2288 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2289 MachinePointerInfo::getStack(i * 8), false, false, 0);
2290 MemOps.push_back(Store);
2291 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2292 DAG.getConstant(8, DL, getPointerTy()));
2295 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2296 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2298 if (Subtarget->hasFPARMv8()) {
2299 static const MCPhysReg FPRArgRegs[] = {
2300 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2301 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2302 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2303 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2305 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2307 if (FPRSaveSize != 0) {
2308 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2310 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2312 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2313 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2314 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2317 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2318 MachinePointerInfo::getStack(i * 16), false, false, 0);
2319 MemOps.push_back(Store);
2320 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2321 DAG.getConstant(16, DL, getPointerTy()));
2324 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2325 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2328 if (!MemOps.empty()) {
2329 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2333 /// LowerCallResult - Lower the result values of a call into the
2334 /// appropriate copies out of appropriate physical registers.
2335 SDValue AArch64TargetLowering::LowerCallResult(
2336 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2337 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2338 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2339 SDValue ThisVal) const {
2340 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2341 ? RetCC_AArch64_WebKit_JS
2342 : RetCC_AArch64_AAPCS;
2343 // Assign locations to each value returned by this call.
2344 SmallVector<CCValAssign, 16> RVLocs;
2345 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2347 CCInfo.AnalyzeCallResult(Ins, RetCC);
2349 // Copy all of the result registers out of their specified physreg.
2350 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2351 CCValAssign VA = RVLocs[i];
2353 // Pass 'this' value directly from the argument to return value, to avoid
2354 // reg unit interference
2355 if (i == 0 && isThisReturn) {
2356 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2357 "unexpected return calling convention register assignment");
2358 InVals.push_back(ThisVal);
2363 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2364 Chain = Val.getValue(1);
2365 InFlag = Val.getValue(2);
2367 switch (VA.getLocInfo()) {
2369 llvm_unreachable("Unknown loc info!");
2370 case CCValAssign::Full:
2372 case CCValAssign::BCvt:
2373 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2377 InVals.push_back(Val);
2383 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2384 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2385 bool isCalleeStructRet, bool isCallerStructRet,
2386 const SmallVectorImpl<ISD::OutputArg> &Outs,
2387 const SmallVectorImpl<SDValue> &OutVals,
2388 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2389 // For CallingConv::C this function knows whether the ABI needs
2390 // changing. That's not true for other conventions so they will have to opt in
2392 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2395 const MachineFunction &MF = DAG.getMachineFunction();
2396 const Function *CallerF = MF.getFunction();
2397 CallingConv::ID CallerCC = CallerF->getCallingConv();
2398 bool CCMatch = CallerCC == CalleeCC;
2400 // Byval parameters hand the function a pointer directly into the stack area
2401 // we want to reuse during a tail call. Working around this *is* possible (see
2402 // X86) but less efficient and uglier in LowerCall.
2403 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2404 e = CallerF->arg_end();
2406 if (i->hasByValAttr())
2409 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2410 if (IsTailCallConvention(CalleeCC) && CCMatch)
2415 // Externally-defined functions with weak linkage should not be
2416 // tail-called on AArch64 when the OS does not support dynamic
2417 // pre-emption of symbols, as the AAELF spec requires normal calls
2418 // to undefined weak functions to be replaced with a NOP or jump to the
2419 // next instruction. The behaviour of branch instructions in this
2420 // situation (as used for tail calls) is implementation-defined, so we
2421 // cannot rely on the linker replacing the tail call with a return.
2422 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2423 const GlobalValue *GV = G->getGlobal();
2424 const Triple &TT = getTargetMachine().getTargetTriple();
2425 if (GV->hasExternalWeakLinkage() &&
2426 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2430 // Now we search for cases where we can use a tail call without changing the
2431 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2434 // I want anyone implementing a new calling convention to think long and hard
2435 // about this assert.
2436 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2437 "Unexpected variadic calling convention");
2439 if (isVarArg && !Outs.empty()) {
2440 // At least two cases here: if caller is fastcc then we can't have any
2441 // memory arguments (we'd be expected to clean up the stack afterwards). If
2442 // caller is C then we could potentially use its argument area.
2444 // FIXME: for now we take the most conservative of these in both cases:
2445 // disallow all variadic memory operands.
2446 SmallVector<CCValAssign, 16> ArgLocs;
2447 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2450 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2451 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2452 if (!ArgLocs[i].isRegLoc())
2456 // If the calling conventions do not match, then we'd better make sure the
2457 // results are returned in the same way as what the caller expects.
2459 SmallVector<CCValAssign, 16> RVLocs1;
2460 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2462 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2464 SmallVector<CCValAssign, 16> RVLocs2;
2465 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2467 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2469 if (RVLocs1.size() != RVLocs2.size())
2471 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2472 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2474 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2476 if (RVLocs1[i].isRegLoc()) {
2477 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2480 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2486 // Nothing more to check if the callee is taking no arguments
2490 SmallVector<CCValAssign, 16> ArgLocs;
2491 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2494 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2496 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2498 // If the stack arguments for this call would fit into our own save area then
2499 // the call can be made tail.
2500 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2503 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2505 MachineFrameInfo *MFI,
2506 int ClobberedFI) const {
2507 SmallVector<SDValue, 8> ArgChains;
2508 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2509 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2511 // Include the original chain at the beginning of the list. When this is
2512 // used by target LowerCall hooks, this helps legalize find the
2513 // CALLSEQ_BEGIN node.
2514 ArgChains.push_back(Chain);
2516 // Add a chain value for each stack argument corresponding
2517 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2518 UE = DAG.getEntryNode().getNode()->use_end();
2520 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2521 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2522 if (FI->getIndex() < 0) {
2523 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2524 int64_t InLastByte = InFirstByte;
2525 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2527 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2528 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2529 ArgChains.push_back(SDValue(L, 1));
2532 // Build a tokenfactor for all the chains.
2533 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2536 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2537 bool TailCallOpt) const {
2538 return CallCC == CallingConv::Fast && TailCallOpt;
2541 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2542 return CallCC == CallingConv::Fast;
2545 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2546 /// and add input and output parameter nodes.
2548 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2549 SmallVectorImpl<SDValue> &InVals) const {
2550 SelectionDAG &DAG = CLI.DAG;
2552 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2553 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2554 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2555 SDValue Chain = CLI.Chain;
2556 SDValue Callee = CLI.Callee;
2557 bool &IsTailCall = CLI.IsTailCall;
2558 CallingConv::ID CallConv = CLI.CallConv;
2559 bool IsVarArg = CLI.IsVarArg;
2561 MachineFunction &MF = DAG.getMachineFunction();
2562 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2563 bool IsThisReturn = false;
2565 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2566 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2567 bool IsSibCall = false;
2570 // Check if it's really possible to do a tail call.
2571 IsTailCall = isEligibleForTailCallOptimization(
2572 Callee, CallConv, IsVarArg, IsStructRet,
2573 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2574 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2575 report_fatal_error("failed to perform tail call elimination on a call "
2576 "site marked musttail");
2578 // A sibling call is one where we're under the usual C ABI and not planning
2579 // to change that but can still do a tail call:
2580 if (!TailCallOpt && IsTailCall)
2587 // Analyze operands of the call, assigning locations to each operand.
2588 SmallVector<CCValAssign, 16> ArgLocs;
2589 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2593 // Handle fixed and variable vector arguments differently.
2594 // Variable vector arguments always go into memory.
2595 unsigned NumArgs = Outs.size();
2597 for (unsigned i = 0; i != NumArgs; ++i) {
2598 MVT ArgVT = Outs[i].VT;
2599 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2600 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2601 /*IsVarArg=*/ !Outs[i].IsFixed);
2602 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2603 assert(!Res && "Call operand has unhandled type");
2607 // At this point, Outs[].VT may already be promoted to i32. To correctly
2608 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2609 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2610 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2611 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2613 unsigned NumArgs = Outs.size();
2614 for (unsigned i = 0; i != NumArgs; ++i) {
2615 MVT ValVT = Outs[i].VT;
2616 // Get type of the original argument.
2617 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2618 /*AllowUnknown*/ true);
2619 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2620 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2621 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2622 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2624 else if (ActualMVT == MVT::i16)
2627 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2628 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2629 assert(!Res && "Call operand has unhandled type");
2634 // Get a count of how many bytes are to be pushed on the stack.
2635 unsigned NumBytes = CCInfo.getNextStackOffset();
2638 // Since we're not changing the ABI to make this a tail call, the memory
2639 // operands are already available in the caller's incoming argument space.
2643 // FPDiff is the byte offset of the call's argument area from the callee's.
2644 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2645 // by this amount for a tail call. In a sibling call it must be 0 because the
2646 // caller will deallocate the entire stack and the callee still expects its
2647 // arguments to begin at SP+0. Completely unused for non-tail calls.
2650 if (IsTailCall && !IsSibCall) {
2651 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2653 // Since callee will pop argument stack as a tail call, we must keep the
2654 // popped size 16-byte aligned.
2655 NumBytes = RoundUpToAlignment(NumBytes, 16);
2657 // FPDiff will be negative if this tail call requires more space than we
2658 // would automatically have in our incoming argument space. Positive if we
2659 // can actually shrink the stack.
2660 FPDiff = NumReusableBytes - NumBytes;
2662 // The stack pointer must be 16-byte aligned at all times it's used for a
2663 // memory operation, which in practice means at *all* times and in
2664 // particular across call boundaries. Therefore our own arguments started at
2665 // a 16-byte aligned SP and the delta applied for the tail call should
2666 // satisfy the same constraint.
2667 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2670 // Adjust the stack pointer for the new arguments...
2671 // These operations are automatically eliminated by the prolog/epilog pass
2673 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2677 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2679 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2680 SmallVector<SDValue, 8> MemOpChains;
2682 // Walk the register/memloc assignments, inserting copies/loads.
2683 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2684 ++i, ++realArgIdx) {
2685 CCValAssign &VA = ArgLocs[i];
2686 SDValue Arg = OutVals[realArgIdx];
2687 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2689 // Promote the value if needed.
2690 switch (VA.getLocInfo()) {
2692 llvm_unreachable("Unknown loc info!");
2693 case CCValAssign::Full:
2695 case CCValAssign::SExt:
2696 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2698 case CCValAssign::ZExt:
2699 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2701 case CCValAssign::AExt:
2702 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2703 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2704 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2705 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2707 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2709 case CCValAssign::BCvt:
2710 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2712 case CCValAssign::FPExt:
2713 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2717 if (VA.isRegLoc()) {
2718 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2719 assert(VA.getLocVT() == MVT::i64 &&
2720 "unexpected calling convention register assignment");
2721 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2722 "unexpected use of 'returned'");
2723 IsThisReturn = true;
2725 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2727 assert(VA.isMemLoc());
2730 MachinePointerInfo DstInfo;
2732 // FIXME: This works on big-endian for composite byvals, which are the
2733 // common case. It should also work for fundamental types too.
2734 uint32_t BEAlign = 0;
2735 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2736 : VA.getValVT().getSizeInBits();
2737 OpSize = (OpSize + 7) / 8;
2738 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2739 !Flags.isInConsecutiveRegs()) {
2741 BEAlign = 8 - OpSize;
2743 unsigned LocMemOffset = VA.getLocMemOffset();
2744 int32_t Offset = LocMemOffset + BEAlign;
2745 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2746 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2749 Offset = Offset + FPDiff;
2750 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2752 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2753 DstInfo = MachinePointerInfo::getFixedStack(FI);
2755 // Make sure any stack arguments overlapping with where we're storing
2756 // are loaded before this eventual operation. Otherwise they'll be
2758 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2760 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2762 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2763 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2766 if (Outs[i].Flags.isByVal()) {
2768 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
2769 SDValue Cpy = DAG.getMemcpy(
2770 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2771 /*isVol = */ false, /*AlwaysInline = */ false,
2772 /*isTailCall = */ false,
2773 DstInfo, MachinePointerInfo());
2775 MemOpChains.push_back(Cpy);
2777 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2778 // promoted to a legal register type i32, we should truncate Arg back to
2780 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2781 VA.getValVT() == MVT::i16)
2782 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2785 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2786 MemOpChains.push_back(Store);
2791 if (!MemOpChains.empty())
2792 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2794 // Build a sequence of copy-to-reg nodes chained together with token chain
2795 // and flag operands which copy the outgoing args into the appropriate regs.
2797 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2798 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2799 RegsToPass[i].second, InFlag);
2800 InFlag = Chain.getValue(1);
2803 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2804 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2805 // node so that legalize doesn't hack it.
2806 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2807 Subtarget->isTargetMachO()) {
2808 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2809 const GlobalValue *GV = G->getGlobal();
2810 bool InternalLinkage = GV->hasInternalLinkage();
2811 if (InternalLinkage)
2812 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2814 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2816 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2818 } else if (ExternalSymbolSDNode *S =
2819 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2820 const char *Sym = S->getSymbol();
2822 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2823 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2825 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2826 const GlobalValue *GV = G->getGlobal();
2827 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2828 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2829 const char *Sym = S->getSymbol();
2830 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2833 // We don't usually want to end the call-sequence here because we would tidy
2834 // the frame up *after* the call, however in the ABI-changing tail-call case
2835 // we've carefully laid out the parameters so that when sp is reset they'll be
2836 // in the correct location.
2837 if (IsTailCall && !IsSibCall) {
2838 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2839 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2840 InFlag = Chain.getValue(1);
2843 std::vector<SDValue> Ops;
2844 Ops.push_back(Chain);
2845 Ops.push_back(Callee);
2848 // Each tail call may have to adjust the stack by a different amount, so
2849 // this information must travel along with the operation for eventual
2850 // consumption by emitEpilogue.
2851 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2854 // Add argument registers to the end of the list so that they are known live
2856 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2857 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2858 RegsToPass[i].second.getValueType()));
2860 // Add a register mask operand representing the call-preserved registers.
2861 const uint32_t *Mask;
2862 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2864 // For 'this' returns, use the X0-preserving mask if applicable
2865 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2867 IsThisReturn = false;
2868 Mask = TRI->getCallPreservedMask(MF, CallConv);
2871 Mask = TRI->getCallPreservedMask(MF, CallConv);
2873 assert(Mask && "Missing call preserved mask for calling convention");
2874 Ops.push_back(DAG.getRegisterMask(Mask));
2876 if (InFlag.getNode())
2877 Ops.push_back(InFlag);
2879 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2881 // If we're doing a tall call, use a TC_RETURN here rather than an
2882 // actual call instruction.
2884 MF.getFrameInfo()->setHasTailCall();
2885 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2888 // Returns a chain and a flag for retval copy to use.
2889 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2890 InFlag = Chain.getValue(1);
2892 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2893 ? RoundUpToAlignment(NumBytes, 16)
2896 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2897 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
2900 InFlag = Chain.getValue(1);
2902 // Handle result values, copying them out of physregs into vregs that we
2904 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2905 InVals, IsThisReturn,
2906 IsThisReturn ? OutVals[0] : SDValue());
2909 bool AArch64TargetLowering::CanLowerReturn(
2910 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2911 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2912 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2913 ? RetCC_AArch64_WebKit_JS
2914 : RetCC_AArch64_AAPCS;
2915 SmallVector<CCValAssign, 16> RVLocs;
2916 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2917 return CCInfo.CheckReturn(Outs, RetCC);
2921 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2923 const SmallVectorImpl<ISD::OutputArg> &Outs,
2924 const SmallVectorImpl<SDValue> &OutVals,
2925 SDLoc DL, SelectionDAG &DAG) const {
2926 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2927 ? RetCC_AArch64_WebKit_JS
2928 : RetCC_AArch64_AAPCS;
2929 SmallVector<CCValAssign, 16> RVLocs;
2930 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2932 CCInfo.AnalyzeReturn(Outs, RetCC);
2934 // Copy the result values into the output registers.
2936 SmallVector<SDValue, 4> RetOps(1, Chain);
2937 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2938 ++i, ++realRVLocIdx) {
2939 CCValAssign &VA = RVLocs[i];
2940 assert(VA.isRegLoc() && "Can only return in registers!");
2941 SDValue Arg = OutVals[realRVLocIdx];
2943 switch (VA.getLocInfo()) {
2945 llvm_unreachable("Unknown loc info!");
2946 case CCValAssign::Full:
2947 if (Outs[i].ArgVT == MVT::i1) {
2948 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2949 // value. This is strictly redundant on Darwin (which uses "zeroext
2950 // i1"), but will be optimised out before ISel.
2951 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2952 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2955 case CCValAssign::BCvt:
2956 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2960 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2961 Flag = Chain.getValue(1);
2962 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2965 RetOps[0] = Chain; // Update chain.
2967 // Add the flag if we have it.
2969 RetOps.push_back(Flag);
2971 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2974 //===----------------------------------------------------------------------===//
2975 // Other Lowering Code
2976 //===----------------------------------------------------------------------===//
2978 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2979 SelectionDAG &DAG) const {
2980 EVT PtrVT = getPointerTy();
2982 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2983 const GlobalValue *GV = GN->getGlobal();
2984 unsigned char OpFlags =
2985 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2987 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2988 "unexpected offset in global node");
2990 // This also catched the large code model case for Darwin.
2991 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2992 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2993 // FIXME: Once remat is capable of dealing with instructions with register
2994 // operands, expand this into two nodes instead of using a wrapper node.
2995 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2998 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2999 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3000 "use of MO_CONSTPOOL only supported on small model");
3001 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3002 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3003 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3004 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3005 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3006 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3007 MachinePointerInfo::getConstantPool(),
3008 /*isVolatile=*/ false,
3009 /*isNonTemporal=*/ true,
3010 /*isInvariant=*/ true, 8);
3011 if (GN->getOffset() != 0)
3012 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3013 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3017 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3018 const unsigned char MO_NC = AArch64II::MO_NC;
3020 AArch64ISD::WrapperLarge, DL, PtrVT,
3021 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3022 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3023 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3024 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3026 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3027 // the only correct model on Darwin.
3028 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3029 OpFlags | AArch64II::MO_PAGE);
3030 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3031 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3033 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3034 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3038 /// \brief Convert a TLS address reference into the correct sequence of loads
3039 /// and calls to compute the variable's address (for Darwin, currently) and
3040 /// return an SDValue containing the final node.
3042 /// Darwin only has one TLS scheme which must be capable of dealing with the
3043 /// fully general situation, in the worst case. This means:
3044 /// + "extern __thread" declaration.
3045 /// + Defined in a possibly unknown dynamic library.
3047 /// The general system is that each __thread variable has a [3 x i64] descriptor
3048 /// which contains information used by the runtime to calculate the address. The
3049 /// only part of this the compiler needs to know about is the first xword, which
3050 /// contains a function pointer that must be called with the address of the
3051 /// entire descriptor in "x0".
3053 /// Since this descriptor may be in a different unit, in general even the
3054 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3056 /// adrp x0, _var@TLVPPAGE
3057 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3058 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3059 /// ; the function pointer
3060 /// blr x1 ; Uses descriptor address in x0
3061 /// ; Address of _var is now in x0.
3063 /// If the address of _var's descriptor *is* known to the linker, then it can
3064 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3065 /// a slight efficiency gain.
3067 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3068 SelectionDAG &DAG) const {
3069 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3072 MVT PtrVT = getPointerTy();
3073 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3076 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3077 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3079 // The first entry in the descriptor is a function pointer that we must call
3080 // to obtain the address of the variable.
3081 SDValue Chain = DAG.getEntryNode();
3082 SDValue FuncTLVGet =
3083 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3084 false, true, true, 8);
3085 Chain = FuncTLVGet.getValue(1);
3087 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3088 MFI->setAdjustsStack(true);
3090 // TLS calls preserve all registers except those that absolutely must be
3091 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3093 const uint32_t *Mask =
3094 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3096 // Finally, we can make the call. This is just a degenerate version of a
3097 // normal AArch64 call node: x0 takes the address of the descriptor, and
3098 // returns the address of the variable in this thread.
3099 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3101 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3102 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3103 DAG.getRegisterMask(Mask), Chain.getValue(1));
3104 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3107 /// When accessing thread-local variables under either the general-dynamic or
3108 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3109 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3110 /// is a function pointer to carry out the resolution.
3112 /// The sequence is:
3113 /// adrp x0, :tlsdesc:var
3114 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3115 /// add x0, x0, #:tlsdesc_lo12:var
3116 /// .tlsdesccall var
3118 /// (TPIDR_EL0 offset now in x0)
3120 /// The above sequence must be produced unscheduled, to enable the linker to
3121 /// optimize/relax this sequence.
3122 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3123 /// above sequence, and expanded really late in the compilation flow, to ensure
3124 /// the sequence is produced as per above.
3125 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3126 SelectionDAG &DAG) const {
3127 EVT PtrVT = getPointerTy();
3129 SDValue Chain = DAG.getEntryNode();
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3132 SmallVector<SDValue, 2> Ops;
3133 Ops.push_back(Chain);
3134 Ops.push_back(SymAddr);
3136 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3137 SDValue Glue = Chain.getValue(1);
3139 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3143 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3144 SelectionDAG &DAG) const {
3145 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3146 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3147 "ELF TLS only supported in small memory model");
3148 // Different choices can be made for the maximum size of the TLS area for a
3149 // module. For the small address model, the default TLS size is 16MiB and the
3150 // maximum TLS size is 4GiB.
3151 // FIXME: add -mtls-size command line option and make it control the 16MiB
3152 // vs. 4GiB code sequence generation.
3153 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3155 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3156 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3157 if (Model == TLSModel::LocalDynamic)
3158 Model = TLSModel::GeneralDynamic;
3162 EVT PtrVT = getPointerTy();
3164 const GlobalValue *GV = GA->getGlobal();
3166 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3168 if (Model == TLSModel::LocalExec) {
3169 SDValue HiVar = DAG.getTargetGlobalAddress(
3170 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3171 SDValue LoVar = DAG.getTargetGlobalAddress(
3173 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3175 SDValue TPWithOff_lo =
3176 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3178 DAG.getTargetConstant(0, DL, MVT::i32)),
3181 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3183 DAG.getTargetConstant(0, DL, MVT::i32)),
3186 } else if (Model == TLSModel::InitialExec) {
3187 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3188 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3189 } else if (Model == TLSModel::LocalDynamic) {
3190 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3191 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3192 // the beginning of the module's TLS region, followed by a DTPREL offset
3195 // These accesses will need deduplicating if there's more than one.
3196 AArch64FunctionInfo *MFI =
3197 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3198 MFI->incNumLocalDynamicTLSAccesses();
3200 // The call needs a relocation too for linker relaxation. It doesn't make
3201 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3203 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3206 // Now we can calculate the offset from TPIDR_EL0 to this module's
3207 // thread-local area.
3208 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3210 // Now use :dtprel_whatever: operations to calculate this variable's offset
3211 // in its thread-storage area.
3212 SDValue HiVar = DAG.getTargetGlobalAddress(
3213 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3214 SDValue LoVar = DAG.getTargetGlobalAddress(
3215 GV, DL, MVT::i64, 0,
3216 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3218 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3219 DAG.getTargetConstant(0, DL, MVT::i32)),
3221 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3222 DAG.getTargetConstant(0, DL, MVT::i32)),
3224 } else if (Model == TLSModel::GeneralDynamic) {
3225 // The call needs a relocation too for linker relaxation. It doesn't make
3226 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3229 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3231 // Finally we can make a call to calculate the offset from tpidr_el0.
3232 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3234 llvm_unreachable("Unsupported ELF TLS access model");
3236 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3239 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3240 SelectionDAG &DAG) const {
3241 if (Subtarget->isTargetDarwin())
3242 return LowerDarwinGlobalTLSAddress(Op, DAG);
3243 else if (Subtarget->isTargetELF())
3244 return LowerELFGlobalTLSAddress(Op, DAG);
3246 llvm_unreachable("Unexpected platform trying to use TLS");
3248 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3249 SDValue Chain = Op.getOperand(0);
3250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3251 SDValue LHS = Op.getOperand(2);
3252 SDValue RHS = Op.getOperand(3);
3253 SDValue Dest = Op.getOperand(4);
3256 // Handle f128 first, since lowering it will result in comparing the return
3257 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3258 // is expecting to deal with.
3259 if (LHS.getValueType() == MVT::f128) {
3260 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3262 // If softenSetCCOperands returned a scalar, we need to compare the result
3263 // against zero to select between true and false values.
3264 if (!RHS.getNode()) {
3265 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3270 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3272 unsigned Opc = LHS.getOpcode();
3273 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3274 cast<ConstantSDNode>(RHS)->isOne() &&
3275 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3276 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3277 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3278 "Unexpected condition code.");
3279 // Only lower legal XALUO ops.
3280 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3283 // The actual operation with overflow check.
3284 AArch64CC::CondCode OFCC;
3285 SDValue Value, Overflow;
3286 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3288 if (CC == ISD::SETNE)
3289 OFCC = getInvertedCondCode(OFCC);
3290 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3292 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3296 if (LHS.getValueType().isInteger()) {
3297 assert((LHS.getValueType() == RHS.getValueType()) &&
3298 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3300 // If the RHS of the comparison is zero, we can potentially fold this
3301 // to a specialized branch.
3302 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3303 if (RHSC && RHSC->getZExtValue() == 0) {
3304 if (CC == ISD::SETEQ) {
3305 // See if we can use a TBZ to fold in an AND as well.
3306 // TBZ has a smaller branch displacement than CBZ. If the offset is
3307 // out of bounds, a late MI-layer pass rewrites branches.
3308 // 403.gcc is an example that hits this case.
3309 if (LHS.getOpcode() == ISD::AND &&
3310 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3311 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3312 SDValue Test = LHS.getOperand(0);
3313 uint64_t Mask = LHS.getConstantOperandVal(1);
3314 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3315 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3319 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3320 } else if (CC == ISD::SETNE) {
3321 // See if we can use a TBZ to fold in an AND as well.
3322 // TBZ has a smaller branch displacement than CBZ. If the offset is
3323 // out of bounds, a late MI-layer pass rewrites branches.
3324 // 403.gcc is an example that hits this case.
3325 if (LHS.getOpcode() == ISD::AND &&
3326 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3327 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3328 SDValue Test = LHS.getOperand(0);
3329 uint64_t Mask = LHS.getConstantOperandVal(1);
3330 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3331 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3335 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3336 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3337 // Don't combine AND since emitComparison converts the AND to an ANDS
3338 // (a.k.a. TST) and the test in the test bit and branch instruction
3339 // becomes redundant. This would also increase register pressure.
3340 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3341 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3342 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3345 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3346 LHS.getOpcode() != ISD::AND) {
3347 // Don't combine AND since emitComparison converts the AND to an ANDS
3348 // (a.k.a. TST) and the test in the test bit and branch instruction
3349 // becomes redundant. This would also increase register pressure.
3350 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3351 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3352 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3356 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3357 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3361 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3363 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3364 // clean. Some of them require two branches to implement.
3365 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3366 AArch64CC::CondCode CC1, CC2;
3367 changeFPCCToAArch64CC(CC, CC1, CC2);
3368 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3370 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3371 if (CC2 != AArch64CC::AL) {
3372 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3373 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3380 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3381 SelectionDAG &DAG) const {
3382 EVT VT = Op.getValueType();
3385 SDValue In1 = Op.getOperand(0);
3386 SDValue In2 = Op.getOperand(1);
3387 EVT SrcVT = In2.getValueType();
3389 if (SrcVT == MVT::f32 && VT == MVT::f64)
3390 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3391 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3392 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3393 DAG.getIntPtrConstant(0, DL));
3395 // FIXME: Src type is different, bail out for now. Can VT really be a
3403 SDValue VecVal1, VecVal2;
3404 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3407 EltMask = 0x80000000ULL;
3409 if (!VT.isVector()) {
3410 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3411 DAG.getUNDEF(VecVT), In1);
3412 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3413 DAG.getUNDEF(VecVT), In2);
3415 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3416 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3418 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3422 // We want to materialize a mask with the high bit set, but the AdvSIMD
3423 // immediate moves cannot materialize that in a single instruction for
3424 // 64-bit elements. Instead, materialize zero and then negate it.
3427 if (!VT.isVector()) {
3428 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3429 DAG.getUNDEF(VecVT), In1);
3430 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3431 DAG.getUNDEF(VecVT), In2);
3433 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3434 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3437 llvm_unreachable("Invalid type for copysign!");
3440 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3442 // If we couldn't materialize the mask above, then the mask vector will be
3443 // the zero vector, and we need to negate it here.
3444 if (VT == MVT::f64 || VT == MVT::v2f64) {
3445 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3446 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3447 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3451 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3454 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3455 else if (VT == MVT::f64)
3456 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3458 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3461 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3462 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3463 Attribute::NoImplicitFloat))
3466 if (!Subtarget->hasNEON())
3469 // While there is no integer popcount instruction, it can
3470 // be more efficiently lowered to the following sequence that uses
3471 // AdvSIMD registers/instructions as long as the copies to/from
3472 // the AdvSIMD registers are cheap.
3473 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3474 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3475 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3476 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3477 SDValue Val = Op.getOperand(0);
3479 EVT VT = Op.getValueType();
3482 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3483 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3485 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3486 SDValue UaddLV = DAG.getNode(
3487 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3488 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3491 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3495 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3497 if (Op.getValueType().isVector())
3498 return LowerVSETCC(Op, DAG);
3500 SDValue LHS = Op.getOperand(0);
3501 SDValue RHS = Op.getOperand(1);
3502 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3505 // We chose ZeroOrOneBooleanContents, so use zero and one.
3506 EVT VT = Op.getValueType();
3507 SDValue TVal = DAG.getConstant(1, dl, VT);
3508 SDValue FVal = DAG.getConstant(0, dl, VT);
3510 // Handle f128 first, since one possible outcome is a normal integer
3511 // comparison which gets picked up by the next if statement.
3512 if (LHS.getValueType() == MVT::f128) {
3513 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3515 // If softenSetCCOperands returned a scalar, use it.
3516 if (!RHS.getNode()) {
3517 assert(LHS.getValueType() == Op.getValueType() &&
3518 "Unexpected setcc expansion!");
3523 if (LHS.getValueType().isInteger()) {
3526 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3528 // Note that we inverted the condition above, so we reverse the order of
3529 // the true and false operands here. This will allow the setcc to be
3530 // matched to a single CSINC instruction.
3531 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3534 // Now we know we're dealing with FP values.
3535 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3537 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3538 // and do the comparison.
3539 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3541 AArch64CC::CondCode CC1, CC2;
3542 changeFPCCToAArch64CC(CC, CC1, CC2);
3543 if (CC2 == AArch64CC::AL) {
3544 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3545 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3547 // Note that we inverted the condition above, so we reverse the order of
3548 // the true and false operands here. This will allow the setcc to be
3549 // matched to a single CSINC instruction.
3550 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3552 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3553 // totally clean. Some of them require two CSELs to implement. As is in
3554 // this case, we emit the first CSEL and then emit a second using the output
3555 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3557 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3558 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3560 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3562 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3563 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3567 /// A SELECT_CC operation is really some kind of max or min if both values being
3568 /// compared are, in some sense, equal to the results in either case. However,
3569 /// it is permissible to compare f32 values and produce directly extended f64
3572 /// Extending the comparison operands would also be allowed, but is less likely
3573 /// to happen in practice since their use is right here. Note that truncate
3574 /// operations would *not* be semantically equivalent.
3575 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3577 return (Cmp.getValueType() == MVT::f32 ||
3578 Cmp.getValueType() == MVT::f64);
3580 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3581 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3582 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3583 Result.getValueType() == MVT::f64) {
3585 APFloat CmpVal = CCmp->getValueAPF();
3586 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3587 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3590 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3593 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3594 SDValue RHS, SDValue TVal,
3595 SDValue FVal, SDLoc dl,
3596 SelectionDAG &DAG) const {
3597 // Handle f128 first, because it will result in a comparison of some RTLIB
3598 // call result against zero.
3599 if (LHS.getValueType() == MVT::f128) {
3600 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3602 // If softenSetCCOperands returned a scalar, we need to compare the result
3603 // against zero to select between true and false values.
3604 if (!RHS.getNode()) {
3605 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3610 // Handle integers first.
3611 if (LHS.getValueType().isInteger()) {
3612 assert((LHS.getValueType() == RHS.getValueType()) &&
3613 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3615 unsigned Opcode = AArch64ISD::CSEL;
3617 // If both the TVal and the FVal are constants, see if we can swap them in
3618 // order to for a CSINV or CSINC out of them.
3619 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3620 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3622 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3623 std::swap(TVal, FVal);
3624 std::swap(CTVal, CFVal);
3625 CC = ISD::getSetCCInverse(CC, true);
3626 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3627 std::swap(TVal, FVal);
3628 std::swap(CTVal, CFVal);
3629 CC = ISD::getSetCCInverse(CC, true);
3630 } else if (TVal.getOpcode() == ISD::XOR) {
3631 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3632 // with a CSINV rather than a CSEL.
3633 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3635 if (CVal && CVal->isAllOnesValue()) {
3636 std::swap(TVal, FVal);
3637 std::swap(CTVal, CFVal);
3638 CC = ISD::getSetCCInverse(CC, true);
3640 } else if (TVal.getOpcode() == ISD::SUB) {
3641 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3642 // that we can match with a CSNEG rather than a CSEL.
3643 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3645 if (CVal && CVal->isNullValue()) {
3646 std::swap(TVal, FVal);
3647 std::swap(CTVal, CFVal);
3648 CC = ISD::getSetCCInverse(CC, true);
3650 } else if (CTVal && CFVal) {
3651 const int64_t TrueVal = CTVal->getSExtValue();
3652 const int64_t FalseVal = CFVal->getSExtValue();
3655 // If both TVal and FVal are constants, see if FVal is the
3656 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3657 // instead of a CSEL in that case.
3658 if (TrueVal == ~FalseVal) {
3659 Opcode = AArch64ISD::CSINV;
3660 } else if (TrueVal == -FalseVal) {
3661 Opcode = AArch64ISD::CSNEG;
3662 } else if (TVal.getValueType() == MVT::i32) {
3663 // If our operands are only 32-bit wide, make sure we use 32-bit
3664 // arithmetic for the check whether we can use CSINC. This ensures that
3665 // the addition in the check will wrap around properly in case there is
3666 // an overflow (which would not be the case if we do the check with
3667 // 64-bit arithmetic).
3668 const uint32_t TrueVal32 = CTVal->getZExtValue();
3669 const uint32_t FalseVal32 = CFVal->getZExtValue();
3671 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3672 Opcode = AArch64ISD::CSINC;
3674 if (TrueVal32 > FalseVal32) {
3678 // 64-bit check whether we can use CSINC.
3679 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3680 Opcode = AArch64ISD::CSINC;
3682 if (TrueVal > FalseVal) {
3687 // Swap TVal and FVal if necessary.
3689 std::swap(TVal, FVal);
3690 std::swap(CTVal, CFVal);
3691 CC = ISD::getSetCCInverse(CC, true);
3694 if (Opcode != AArch64ISD::CSEL) {
3695 // Drop FVal since we can get its value by simply inverting/negating
3702 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3704 EVT VT = TVal.getValueType();
3705 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3708 // Now we know we're dealing with FP values.
3709 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3710 assert(LHS.getValueType() == RHS.getValueType());
3711 EVT VT = TVal.getValueType();
3712 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3714 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3715 // clean. Some of them require two CSELs to implement.
3716 AArch64CC::CondCode CC1, CC2;
3717 changeFPCCToAArch64CC(CC, CC1, CC2);
3718 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3719 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3721 // If we need a second CSEL, emit it, using the output of the first as the
3722 // RHS. We're effectively OR'ing the two CC's together.
3723 if (CC2 != AArch64CC::AL) {
3724 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3725 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3728 // Otherwise, return the output of the first CSEL.
3732 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3733 SelectionDAG &DAG) const {
3734 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3735 SDValue LHS = Op.getOperand(0);
3736 SDValue RHS = Op.getOperand(1);
3737 SDValue TVal = Op.getOperand(2);
3738 SDValue FVal = Op.getOperand(3);
3740 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3743 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3744 SelectionDAG &DAG) const {
3745 SDValue CCVal = Op->getOperand(0);
3746 SDValue TVal = Op->getOperand(1);
3747 SDValue FVal = Op->getOperand(2);
3750 unsigned Opc = CCVal.getOpcode();
3751 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3753 if (CCVal.getResNo() == 1 &&
3754 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3755 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3756 // Only lower legal XALUO ops.
3757 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3760 AArch64CC::CondCode OFCC;
3761 SDValue Value, Overflow;
3762 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3763 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
3765 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3769 // Lower it the same way as we would lower a SELECT_CC node.
3772 if (CCVal.getOpcode() == ISD::SETCC) {
3773 LHS = CCVal.getOperand(0);
3774 RHS = CCVal.getOperand(1);
3775 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3778 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
3781 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3784 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3785 SelectionDAG &DAG) const {
3786 // Jump table entries as PC relative offsets. No additional tweaking
3787 // is necessary here. Just get the address of the jump table.
3788 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3789 EVT PtrVT = getPointerTy();
3792 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3793 !Subtarget->isTargetMachO()) {
3794 const unsigned char MO_NC = AArch64II::MO_NC;
3796 AArch64ISD::WrapperLarge, DL, PtrVT,
3797 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3798 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3799 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3800 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3801 AArch64II::MO_G0 | MO_NC));
3805 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3806 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3807 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3808 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3809 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3812 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3813 SelectionDAG &DAG) const {
3814 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3815 EVT PtrVT = getPointerTy();
3818 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3819 // Use the GOT for the large code model on iOS.
3820 if (Subtarget->isTargetMachO()) {
3821 SDValue GotAddr = DAG.getTargetConstantPool(
3822 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3824 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3827 const unsigned char MO_NC = AArch64II::MO_NC;
3829 AArch64ISD::WrapperLarge, DL, PtrVT,
3830 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3831 CP->getOffset(), AArch64II::MO_G3),
3832 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3833 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3834 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3835 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3836 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3837 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3839 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3840 // ELF, the only valid one on Darwin.
3842 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3843 CP->getOffset(), AArch64II::MO_PAGE);
3844 SDValue Lo = DAG.getTargetConstantPool(
3845 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3846 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3848 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3849 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3853 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3854 SelectionDAG &DAG) const {
3855 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3856 EVT PtrVT = getPointerTy();
3858 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3859 !Subtarget->isTargetMachO()) {
3860 const unsigned char MO_NC = AArch64II::MO_NC;
3862 AArch64ISD::WrapperLarge, DL, PtrVT,
3863 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3864 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3865 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3866 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3868 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3869 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3871 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3872 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3876 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3877 SelectionDAG &DAG) const {
3878 AArch64FunctionInfo *FuncInfo =
3879 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3883 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3884 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3885 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3886 MachinePointerInfo(SV), false, false, 0);
3889 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3890 SelectionDAG &DAG) const {
3891 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3892 // Standard, section B.3.
3893 MachineFunction &MF = DAG.getMachineFunction();
3894 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3897 SDValue Chain = Op.getOperand(0);
3898 SDValue VAList = Op.getOperand(1);
3899 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3900 SmallVector<SDValue, 4> MemOps;
3902 // void *__stack at offset 0
3904 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3905 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3906 MachinePointerInfo(SV), false, false, 8));
3908 // void *__gr_top at offset 8
3909 int GPRSize = FuncInfo->getVarArgsGPRSize();
3911 SDValue GRTop, GRTopAddr;
3913 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3914 DAG.getConstant(8, DL, getPointerTy()));
3916 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3917 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3918 DAG.getConstant(GPRSize, DL, getPointerTy()));
3920 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3921 MachinePointerInfo(SV, 8), false, false, 8));
3924 // void *__vr_top at offset 16
3925 int FPRSize = FuncInfo->getVarArgsFPRSize();
3927 SDValue VRTop, VRTopAddr;
3928 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3929 DAG.getConstant(16, DL, getPointerTy()));
3931 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3932 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3933 DAG.getConstant(FPRSize, DL, getPointerTy()));
3935 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3936 MachinePointerInfo(SV, 16), false, false, 8));
3939 // int __gr_offs at offset 24
3940 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3941 DAG.getConstant(24, DL, getPointerTy()));
3942 MemOps.push_back(DAG.getStore(Chain, DL,
3943 DAG.getConstant(-GPRSize, DL, MVT::i32),
3944 GROffsAddr, MachinePointerInfo(SV, 24), false,
3947 // int __vr_offs at offset 28
3948 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3949 DAG.getConstant(28, DL, getPointerTy()));
3950 MemOps.push_back(DAG.getStore(Chain, DL,
3951 DAG.getConstant(-FPRSize, DL, MVT::i32),
3952 VROffsAddr, MachinePointerInfo(SV, 28), false,
3955 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3958 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3959 SelectionDAG &DAG) const {
3960 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3961 : LowerAAPCS_VASTART(Op, DAG);
3964 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3965 SelectionDAG &DAG) const {
3966 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3969 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3970 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3971 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3973 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
3975 DAG.getConstant(VaListSize, DL, MVT::i32),
3976 8, false, false, false, MachinePointerInfo(DestSV),
3977 MachinePointerInfo(SrcSV));
3980 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3981 assert(Subtarget->isTargetDarwin() &&
3982 "automatic va_arg instruction only works on Darwin");
3984 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3985 EVT VT = Op.getValueType();
3987 SDValue Chain = Op.getOperand(0);
3988 SDValue Addr = Op.getOperand(1);
3989 unsigned Align = Op.getConstantOperandVal(3);
3991 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3992 MachinePointerInfo(V), false, false, false, 0);
3993 Chain = VAList.getValue(1);
3996 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3997 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3998 DAG.getConstant(Align - 1, DL, getPointerTy()));
3999 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
4000 DAG.getConstant(-(int64_t)Align, DL, getPointerTy()));
4003 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4004 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4006 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4007 // up to 64 bits. At the very least, we have to increase the striding of the
4008 // vaargs list to match this, and for FP values we need to introduce
4009 // FP_ROUND nodes as well.
4010 if (VT.isInteger() && !VT.isVector())
4012 bool NeedFPTrunc = false;
4013 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4018 // Increment the pointer, VAList, to the next vaarg
4019 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4020 DAG.getConstant(ArgSize, DL, getPointerTy()));
4021 // Store the incremented VAList to the legalized pointer
4022 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4025 // Load the actual argument out of the pointer VAList
4027 // Load the value as an f64.
4028 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4029 MachinePointerInfo(), false, false, false, 0);
4030 // Round the value down to an f32.
4031 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4032 DAG.getIntPtrConstant(1, DL));
4033 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4034 // Merge the rounded value with the chain output of the load.
4035 return DAG.getMergeValues(Ops, DL);
4038 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4042 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4043 SelectionDAG &DAG) const {
4044 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4045 MFI->setFrameAddressIsTaken(true);
4047 EVT VT = Op.getValueType();
4049 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4051 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4053 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4054 MachinePointerInfo(), false, false, false, 0);
4058 // FIXME? Maybe this could be a TableGen attribute on some registers and
4059 // this table could be generated automatically from RegInfo.
4060 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4062 unsigned Reg = StringSwitch<unsigned>(RegName)
4063 .Case("sp", AArch64::SP)
4067 report_fatal_error(Twine("Invalid register name \""
4068 + StringRef(RegName) + "\"."));
4071 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4072 SelectionDAG &DAG) const {
4073 MachineFunction &MF = DAG.getMachineFunction();
4074 MachineFrameInfo *MFI = MF.getFrameInfo();
4075 MFI->setReturnAddressIsTaken(true);
4077 EVT VT = Op.getValueType();
4079 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4081 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4082 SDValue Offset = DAG.getConstant(8, DL, getPointerTy());
4083 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4084 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4085 MachinePointerInfo(), false, false, false, 0);
4088 // Return LR, which contains the return address. Mark it an implicit live-in.
4089 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4090 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4093 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4094 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4095 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4096 SelectionDAG &DAG) const {
4097 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4098 EVT VT = Op.getValueType();
4099 unsigned VTBits = VT.getSizeInBits();
4101 SDValue ShOpLo = Op.getOperand(0);
4102 SDValue ShOpHi = Op.getOperand(1);
4103 SDValue ShAmt = Op.getOperand(2);
4105 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4107 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4109 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4110 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4111 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4112 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4113 DAG.getConstant(VTBits, dl, MVT::i64));
4114 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4116 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4117 ISD::SETGE, dl, DAG);
4118 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4120 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4121 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4123 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4125 // AArch64 shifts larger than the register width are wrapped rather than
4126 // clamped, so we can't just emit "hi >> x".
4127 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4128 SDValue TrueValHi = Opc == ISD::SRA
4129 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4130 DAG.getConstant(VTBits - 1, dl,
4132 : DAG.getConstant(0, dl, VT);
4134 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4136 SDValue Ops[2] = { Lo, Hi };
4137 return DAG.getMergeValues(Ops, dl);
4140 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4141 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4142 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4143 SelectionDAG &DAG) const {
4144 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4145 EVT VT = Op.getValueType();
4146 unsigned VTBits = VT.getSizeInBits();
4148 SDValue ShOpLo = Op.getOperand(0);
4149 SDValue ShOpHi = Op.getOperand(1);
4150 SDValue ShAmt = Op.getOperand(2);
4153 assert(Op.getOpcode() == ISD::SHL_PARTS);
4154 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4155 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4156 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4157 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4158 DAG.getConstant(VTBits, dl, MVT::i64));
4159 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4160 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4162 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4164 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4165 ISD::SETGE, dl, DAG);
4166 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4168 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4170 // AArch64 shifts of larger than register sizes are wrapped rather than
4171 // clamped, so we can't just emit "lo << a" if a is too big.
4172 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4173 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4175 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4177 SDValue Ops[2] = { Lo, Hi };
4178 return DAG.getMergeValues(Ops, dl);
4181 bool AArch64TargetLowering::isOffsetFoldingLegal(
4182 const GlobalAddressSDNode *GA) const {
4183 // The AArch64 target doesn't support folding offsets into global addresses.
4187 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4188 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4189 // FIXME: We should be able to handle f128 as well with a clever lowering.
4190 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4194 return AArch64_AM::getFP64Imm(Imm) != -1;
4195 else if (VT == MVT::f32)
4196 return AArch64_AM::getFP32Imm(Imm) != -1;
4200 //===----------------------------------------------------------------------===//
4201 // AArch64 Optimization Hooks
4202 //===----------------------------------------------------------------------===//
4204 //===----------------------------------------------------------------------===//
4205 // AArch64 Inline Assembly Support
4206 //===----------------------------------------------------------------------===//
4208 // Table of Constraints
4209 // TODO: This is the current set of constraints supported by ARM for the
4210 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4212 // r - A general register
4213 // w - An FP/SIMD register of some size in the range v0-v31
4214 // x - An FP/SIMD register of some size in the range v0-v15
4215 // I - Constant that can be used with an ADD instruction
4216 // J - Constant that can be used with a SUB instruction
4217 // K - Constant that can be used with a 32-bit logical instruction
4218 // L - Constant that can be used with a 64-bit logical instruction
4219 // M - Constant that can be used as a 32-bit MOV immediate
4220 // N - Constant that can be used as a 64-bit MOV immediate
4221 // Q - A memory reference with base register and no offset
4222 // S - A symbolic address
4223 // Y - Floating point constant zero
4224 // Z - Integer constant zero
4226 // Note that general register operands will be output using their 64-bit x
4227 // register name, whatever the size of the variable, unless the asm operand
4228 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4229 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4232 /// getConstraintType - Given a constraint letter, return the type of
4233 /// constraint it is for this target.
4234 AArch64TargetLowering::ConstraintType
4235 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4236 if (Constraint.size() == 1) {
4237 switch (Constraint[0]) {
4244 return C_RegisterClass;
4245 // An address with a single base register. Due to the way we
4246 // currently handle addresses it is the same as 'r'.
4251 return TargetLowering::getConstraintType(Constraint);
4254 /// Examine constraint type and operand type and determine a weight value.
4255 /// This object must already have been set up with the operand type
4256 /// and the current alternative constraint selected.
4257 TargetLowering::ConstraintWeight
4258 AArch64TargetLowering::getSingleConstraintMatchWeight(
4259 AsmOperandInfo &info, const char *constraint) const {
4260 ConstraintWeight weight = CW_Invalid;
4261 Value *CallOperandVal = info.CallOperandVal;
4262 // If we don't have a value, we can't do a match,
4263 // but allow it at the lowest weight.
4264 if (!CallOperandVal)
4266 Type *type = CallOperandVal->getType();
4267 // Look at the constraint type.
4268 switch (*constraint) {
4270 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4274 if (type->isFloatingPointTy() || type->isVectorTy())
4275 weight = CW_Register;
4278 weight = CW_Constant;
4284 std::pair<unsigned, const TargetRegisterClass *>
4285 AArch64TargetLowering::getRegForInlineAsmConstraint(
4286 const TargetRegisterInfo *TRI, const std::string &Constraint,
4288 if (Constraint.size() == 1) {
4289 switch (Constraint[0]) {
4291 if (VT.getSizeInBits() == 64)
4292 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4293 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4296 return std::make_pair(0U, &AArch64::FPR32RegClass);
4297 if (VT.getSizeInBits() == 64)
4298 return std::make_pair(0U, &AArch64::FPR64RegClass);
4299 if (VT.getSizeInBits() == 128)
4300 return std::make_pair(0U, &AArch64::FPR128RegClass);
4302 // The instructions that this constraint is designed for can
4303 // only take 128-bit registers so just use that regclass.
4305 if (VT.getSizeInBits() == 128)
4306 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4310 if (StringRef("{cc}").equals_lower(Constraint))
4311 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4313 // Use the default implementation in TargetLowering to convert the register
4314 // constraint into a member of a register class.
4315 std::pair<unsigned, const TargetRegisterClass *> Res;
4316 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4318 // Not found as a standard register?
4320 unsigned Size = Constraint.size();
4321 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4322 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4323 const std::string Reg =
4324 std::string(&Constraint[2], &Constraint[Size - 1]);
4325 int RegNo = atoi(Reg.c_str());
4326 if (RegNo >= 0 && RegNo <= 31) {
4327 // v0 - v31 are aliases of q0 - q31.
4328 // By default we'll emit v0-v31 for this unless there's a modifier where
4329 // we'll emit the correct register as well.
4330 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4331 Res.second = &AArch64::FPR128RegClass;
4339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4340 /// vector. If it is invalid, don't add anything to Ops.
4341 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4342 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4343 SelectionDAG &DAG) const {
4346 // Currently only support length 1 constraints.
4347 if (Constraint.length() != 1)
4350 char ConstraintLetter = Constraint[0];
4351 switch (ConstraintLetter) {
4355 // This set of constraints deal with valid constants for various instructions.
4356 // Validate and return a target constant for them if we can.
4358 // 'z' maps to xzr or wzr so it needs an input of 0.
4359 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4360 if (!C || C->getZExtValue() != 0)
4363 if (Op.getValueType() == MVT::i64)
4364 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4366 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4376 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4380 // Grab the value and do some validation.
4381 uint64_t CVal = C->getZExtValue();
4382 switch (ConstraintLetter) {
4383 // The I constraint applies only to simple ADD or SUB immediate operands:
4384 // i.e. 0 to 4095 with optional shift by 12
4385 // The J constraint applies only to ADD or SUB immediates that would be
4386 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4387 // instruction [or vice versa], in other words -1 to -4095 with optional
4388 // left shift by 12.
4390 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4394 uint64_t NVal = -C->getSExtValue();
4395 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4396 CVal = C->getSExtValue();
4401 // The K and L constraints apply *only* to logical immediates, including
4402 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4403 // been removed and MOV should be used). So these constraints have to
4404 // distinguish between bit patterns that are valid 32-bit or 64-bit
4405 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4406 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4409 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4413 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4416 // The M and N constraints are a superset of K and L respectively, for use
4417 // with the MOV (immediate) alias. As well as the logical immediates they
4418 // also match 32 or 64-bit immediates that can be loaded either using a
4419 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4420 // (M) or 64-bit 0x1234000000000000 (N) etc.
4421 // As a note some of this code is liberally stolen from the asm parser.
4423 if (!isUInt<32>(CVal))
4425 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4427 if ((CVal & 0xFFFF) == CVal)
4429 if ((CVal & 0xFFFF0000ULL) == CVal)
4431 uint64_t NCVal = ~(uint32_t)CVal;
4432 if ((NCVal & 0xFFFFULL) == NCVal)
4434 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4439 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4441 if ((CVal & 0xFFFFULL) == CVal)
4443 if ((CVal & 0xFFFF0000ULL) == CVal)
4445 if ((CVal & 0xFFFF00000000ULL) == CVal)
4447 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4449 uint64_t NCVal = ~CVal;
4450 if ((NCVal & 0xFFFFULL) == NCVal)
4452 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4454 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4456 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4464 // All assembler immediates are 64-bit integers.
4465 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4469 if (Result.getNode()) {
4470 Ops.push_back(Result);
4474 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4477 //===----------------------------------------------------------------------===//
4478 // AArch64 Advanced SIMD Support
4479 //===----------------------------------------------------------------------===//
4481 /// WidenVector - Given a value in the V64 register class, produce the
4482 /// equivalent value in the V128 register class.
4483 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4484 EVT VT = V64Reg.getValueType();
4485 unsigned NarrowSize = VT.getVectorNumElements();
4486 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4487 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4490 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4491 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4494 /// getExtFactor - Determine the adjustment factor for the position when
4495 /// generating an "extract from vector registers" instruction.
4496 static unsigned getExtFactor(SDValue &V) {
4497 EVT EltType = V.getValueType().getVectorElementType();
4498 return EltType.getSizeInBits() / 8;
4501 /// NarrowVector - Given a value in the V128 register class, produce the
4502 /// equivalent value in the V64 register class.
4503 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4504 EVT VT = V128Reg.getValueType();
4505 unsigned WideSize = VT.getVectorNumElements();
4506 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4507 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4510 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4513 // Gather data to see if the operation can be modelled as a
4514 // shuffle in combination with VEXTs.
4515 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4516 SelectionDAG &DAG) const {
4517 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4519 EVT VT = Op.getValueType();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 struct ShuffleSourceInfo {
4527 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4528 // be compatible with the shuffle we intend to construct. As a result
4529 // ShuffleVec will be some sliding window into the original Vec.
4532 // Code should guarantee that element i in Vec starts at element "WindowBase
4533 // + i * WindowScale in ShuffleVec".
4537 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4538 ShuffleSourceInfo(SDValue Vec)
4539 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4543 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4545 SmallVector<ShuffleSourceInfo, 2> Sources;
4546 for (unsigned i = 0; i < NumElts; ++i) {
4547 SDValue V = Op.getOperand(i);
4548 if (V.getOpcode() == ISD::UNDEF)
4550 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4551 // A shuffle can only come from building a vector from various
4552 // elements of other vectors.
4556 // Add this element source to the list if it's not already there.
4557 SDValue SourceVec = V.getOperand(0);
4558 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4559 if (Source == Sources.end())
4560 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4562 // Update the minimum and maximum lane number seen.
4563 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4564 Source->MinElt = std::min(Source->MinElt, EltNo);
4565 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4568 // Currently only do something sane when at most two source vectors
4570 if (Sources.size() > 2)
4573 // Find out the smallest element size among result and two sources, and use
4574 // it as element size to build the shuffle_vector.
4575 EVT SmallestEltTy = VT.getVectorElementType();
4576 for (auto &Source : Sources) {
4577 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4578 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4579 SmallestEltTy = SrcEltTy;
4582 unsigned ResMultiplier =
4583 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4584 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4585 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4587 // If the source vector is too wide or too narrow, we may nevertheless be able
4588 // to construct a compatible shuffle either by concatenating it with UNDEF or
4589 // extracting a suitable range of elements.
4590 for (auto &Src : Sources) {
4591 EVT SrcVT = Src.ShuffleVec.getValueType();
4593 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4596 // This stage of the search produces a source with the same element type as
4597 // the original, but with a total width matching the BUILD_VECTOR output.
4598 EVT EltVT = SrcVT.getVectorElementType();
4599 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4600 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4602 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4603 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4604 // We can pad out the smaller vector for free, so if it's part of a
4607 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4608 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4612 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4614 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4615 // Span too large for a VEXT to cope
4619 if (Src.MinElt >= NumSrcElts) {
4620 // The extraction can just take the second half
4622 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4623 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4624 Src.WindowBase = -NumSrcElts;
4625 } else if (Src.MaxElt < NumSrcElts) {
4626 // The extraction can just take the first half
4628 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4629 DAG.getConstant(0, dl, MVT::i64));
4631 // An actual VEXT is needed
4633 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4634 DAG.getConstant(0, dl, MVT::i64));
4636 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4637 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4638 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4640 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4642 DAG.getConstant(Imm, dl, MVT::i32));
4643 Src.WindowBase = -Src.MinElt;
4647 // Another possible incompatibility occurs from the vector element types. We
4648 // can fix this by bitcasting the source vectors to the same type we intend
4650 for (auto &Src : Sources) {
4651 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4652 if (SrcEltTy == SmallestEltTy)
4654 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4655 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4656 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4657 Src.WindowBase *= Src.WindowScale;
4660 // Final sanity check before we try to actually produce a shuffle.
4662 for (auto Src : Sources)
4663 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4666 // The stars all align, our next step is to produce the mask for the shuffle.
4667 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4668 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4669 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4670 SDValue Entry = Op.getOperand(i);
4671 if (Entry.getOpcode() == ISD::UNDEF)
4674 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4675 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4677 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4678 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4680 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4681 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4682 VT.getVectorElementType().getSizeInBits());
4683 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4685 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4686 // starting at the appropriate offset.
4687 int *LaneMask = &Mask[i * ResMultiplier];
4689 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4690 ExtractBase += NumElts * (Src - Sources.begin());
4691 for (int j = 0; j < LanesDefined; ++j)
4692 LaneMask[j] = ExtractBase + j;
4695 // Final check before we try to produce nonsense...
4696 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4699 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4700 for (unsigned i = 0; i < Sources.size(); ++i)
4701 ShuffleOps[i] = Sources[i].ShuffleVec;
4703 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4704 ShuffleOps[1], &Mask[0]);
4705 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4708 // check if an EXT instruction can handle the shuffle mask when the
4709 // vector sources of the shuffle are the same.
4710 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4711 unsigned NumElts = VT.getVectorNumElements();
4713 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4719 // If this is a VEXT shuffle, the immediate value is the index of the first
4720 // element. The other shuffle indices must be the successive elements after
4722 unsigned ExpectedElt = Imm;
4723 for (unsigned i = 1; i < NumElts; ++i) {
4724 // Increment the expected index. If it wraps around, just follow it
4725 // back to index zero and keep going.
4727 if (ExpectedElt == NumElts)
4731 continue; // ignore UNDEF indices
4732 if (ExpectedElt != static_cast<unsigned>(M[i]))
4739 // check if an EXT instruction can handle the shuffle mask when the
4740 // vector sources of the shuffle are different.
4741 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4743 // Look for the first non-undef element.
4744 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4745 [](int Elt) {return Elt >= 0;});
4747 // Benefit form APInt to handle overflow when calculating expected element.
4748 unsigned NumElts = VT.getVectorNumElements();
4749 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4750 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4751 // The following shuffle indices must be the successive elements after the
4752 // first real element.
4753 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4754 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4755 if (FirstWrongElt != M.end())
4758 // The index of an EXT is the first element if it is not UNDEF.
4759 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4760 // value of the first element. E.g.
4761 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4762 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4763 // ExpectedElt is the last mask index plus 1.
4764 Imm = ExpectedElt.getZExtValue();
4766 // There are two difference cases requiring to reverse input vectors.
4767 // For example, for vector <4 x i32> we have the following cases,
4768 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4769 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4770 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4771 // to reverse two input vectors.
4780 /// isREVMask - Check if a vector shuffle corresponds to a REV
4781 /// instruction with the specified blocksize. (The order of the elements
4782 /// within each block of the vector is reversed.)
4783 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4784 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4785 "Only possible block sizes for REV are: 16, 32, 64");
4787 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4791 unsigned NumElts = VT.getVectorNumElements();
4792 unsigned BlockElts = M[0] + 1;
4793 // If the first shuffle index is UNDEF, be optimistic.
4795 BlockElts = BlockSize / EltSz;
4797 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4800 for (unsigned i = 0; i < NumElts; ++i) {
4802 continue; // ignore UNDEF indices
4803 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4810 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4811 unsigned NumElts = VT.getVectorNumElements();
4812 WhichResult = (M[0] == 0 ? 0 : 1);
4813 unsigned Idx = WhichResult * NumElts / 2;
4814 for (unsigned i = 0; i != NumElts; i += 2) {
4815 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4816 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4824 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4825 unsigned NumElts = VT.getVectorNumElements();
4826 WhichResult = (M[0] == 0 ? 0 : 1);
4827 for (unsigned i = 0; i != NumElts; ++i) {
4829 continue; // ignore UNDEF indices
4830 if ((unsigned)M[i] != 2 * i + WhichResult)
4837 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4838 unsigned NumElts = VT.getVectorNumElements();
4839 WhichResult = (M[0] == 0 ? 0 : 1);
4840 for (unsigned i = 0; i < NumElts; i += 2) {
4841 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4842 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4848 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4849 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4850 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4851 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4852 unsigned NumElts = VT.getVectorNumElements();
4853 WhichResult = (M[0] == 0 ? 0 : 1);
4854 unsigned Idx = WhichResult * NumElts / 2;
4855 for (unsigned i = 0; i != NumElts; i += 2) {
4856 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4857 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4865 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4866 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4867 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4868 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4869 unsigned Half = VT.getVectorNumElements() / 2;
4870 WhichResult = (M[0] == 0 ? 0 : 1);
4871 for (unsigned j = 0; j != 2; ++j) {
4872 unsigned Idx = WhichResult;
4873 for (unsigned i = 0; i != Half; ++i) {
4874 int MIdx = M[i + j * Half];
4875 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4884 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4885 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4886 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4887 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4888 unsigned NumElts = VT.getVectorNumElements();
4889 WhichResult = (M[0] == 0 ? 0 : 1);
4890 for (unsigned i = 0; i < NumElts; i += 2) {
4891 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4892 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4898 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4899 bool &DstIsLeft, int &Anomaly) {
4900 if (M.size() != static_cast<size_t>(NumInputElements))
4903 int NumLHSMatch = 0, NumRHSMatch = 0;
4904 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4906 for (int i = 0; i < NumInputElements; ++i) {
4916 LastLHSMismatch = i;
4918 if (M[i] == i + NumInputElements)
4921 LastRHSMismatch = i;
4924 if (NumLHSMatch == NumInputElements - 1) {
4926 Anomaly = LastLHSMismatch;
4928 } else if (NumRHSMatch == NumInputElements - 1) {
4930 Anomaly = LastRHSMismatch;
4937 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4938 if (VT.getSizeInBits() != 128)
4941 unsigned NumElts = VT.getVectorNumElements();
4943 for (int I = 0, E = NumElts / 2; I != E; I++) {
4948 int Offset = NumElts / 2;
4949 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4950 if (Mask[I] != I + SplitLHS * Offset)
4957 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4959 EVT VT = Op.getValueType();
4960 SDValue V0 = Op.getOperand(0);
4961 SDValue V1 = Op.getOperand(1);
4962 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4964 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4965 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4968 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4970 if (!isConcatMask(Mask, VT, SplitV0))
4973 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4974 VT.getVectorNumElements() / 2);
4976 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4977 DAG.getConstant(0, DL, MVT::i64));
4979 if (V1.getValueType().getSizeInBits() == 128) {
4980 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4981 DAG.getConstant(0, DL, MVT::i64));
4983 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4986 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4987 /// the specified operations to build the shuffle.
4988 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4989 SDValue RHS, SelectionDAG &DAG,
4991 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4992 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4993 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4996 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5005 OP_VUZPL, // VUZP, left result
5006 OP_VUZPR, // VUZP, right result
5007 OP_VZIPL, // VZIP, left result
5008 OP_VZIPR, // VZIP, right result
5009 OP_VTRNL, // VTRN, left result
5010 OP_VTRNR // VTRN, right result
5013 if (OpNum == OP_COPY) {
5014 if (LHSID == (1 * 9 + 2) * 9 + 3)
5016 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5020 SDValue OpLHS, OpRHS;
5021 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5022 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5023 EVT VT = OpLHS.getValueType();
5027 llvm_unreachable("Unknown shuffle opcode!");
5029 // VREV divides the vector in half and swaps within the half.
5030 if (VT.getVectorElementType() == MVT::i32 ||
5031 VT.getVectorElementType() == MVT::f32)
5032 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5033 // vrev <4 x i16> -> REV32
5034 if (VT.getVectorElementType() == MVT::i16 ||
5035 VT.getVectorElementType() == MVT::f16)
5036 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5037 // vrev <4 x i8> -> REV16
5038 assert(VT.getVectorElementType() == MVT::i8);
5039 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5044 EVT EltTy = VT.getVectorElementType();
5046 if (EltTy == MVT::i8)
5047 Opcode = AArch64ISD::DUPLANE8;
5048 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5049 Opcode = AArch64ISD::DUPLANE16;
5050 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5051 Opcode = AArch64ISD::DUPLANE32;
5052 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5053 Opcode = AArch64ISD::DUPLANE64;
5055 llvm_unreachable("Invalid vector element type?");
5057 if (VT.getSizeInBits() == 64)
5058 OpLHS = WidenVector(OpLHS, DAG);
5059 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5060 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5065 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5066 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5067 DAG.getConstant(Imm, dl, MVT::i32));
5070 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5073 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5076 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5079 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5082 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5085 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5090 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5091 SelectionDAG &DAG) {
5092 // Check to see if we can use the TBL instruction.
5093 SDValue V1 = Op.getOperand(0);
5094 SDValue V2 = Op.getOperand(1);
5097 EVT EltVT = Op.getValueType().getVectorElementType();
5098 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5100 SmallVector<SDValue, 8> TBLMask;
5101 for (int Val : ShuffleMask) {
5102 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5103 unsigned Offset = Byte + Val * BytesPerElt;
5104 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5108 MVT IndexVT = MVT::v8i8;
5109 unsigned IndexLen = 8;
5110 if (Op.getValueType().getSizeInBits() == 128) {
5111 IndexVT = MVT::v16i8;
5115 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5116 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5119 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5121 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5122 Shuffle = DAG.getNode(
5123 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5124 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5125 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5126 makeArrayRef(TBLMask.data(), IndexLen)));
5128 if (IndexLen == 8) {
5129 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5130 Shuffle = DAG.getNode(
5131 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5132 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5133 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5134 makeArrayRef(TBLMask.data(), IndexLen)));
5136 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5137 // cannot currently represent the register constraints on the input
5139 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5140 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5141 // &TBLMask[0], IndexLen));
5142 Shuffle = DAG.getNode(
5143 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5144 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5146 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5147 makeArrayRef(TBLMask.data(), IndexLen)));
5150 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5153 static unsigned getDUPLANEOp(EVT EltType) {
5154 if (EltType == MVT::i8)
5155 return AArch64ISD::DUPLANE8;
5156 if (EltType == MVT::i16 || EltType == MVT::f16)
5157 return AArch64ISD::DUPLANE16;
5158 if (EltType == MVT::i32 || EltType == MVT::f32)
5159 return AArch64ISD::DUPLANE32;
5160 if (EltType == MVT::i64 || EltType == MVT::f64)
5161 return AArch64ISD::DUPLANE64;
5163 llvm_unreachable("Invalid vector element type?");
5166 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5167 SelectionDAG &DAG) const {
5169 EVT VT = Op.getValueType();
5171 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5173 // Convert shuffles that are directly supported on NEON to target-specific
5174 // DAG nodes, instead of keeping them as shuffles and matching them again
5175 // during code selection. This is more efficient and avoids the possibility
5176 // of inconsistencies between legalization and selection.
5177 ArrayRef<int> ShuffleMask = SVN->getMask();
5179 SDValue V1 = Op.getOperand(0);
5180 SDValue V2 = Op.getOperand(1);
5182 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5183 V1.getValueType().getSimpleVT())) {
5184 int Lane = SVN->getSplatIndex();
5185 // If this is undef splat, generate it via "just" vdup, if possible.
5189 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5190 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5192 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5193 // constant. If so, we can just reference the lane's definition directly.
5194 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5195 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5196 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5198 // Otherwise, duplicate from the lane of the input vector.
5199 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5201 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5202 // to make a vector of the same size as this SHUFFLE. We can ignore the
5203 // extract entirely, and canonicalise the concat using WidenVector.
5204 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5205 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5206 V1 = V1.getOperand(0);
5207 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5208 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5209 Lane -= Idx * VT.getVectorNumElements() / 2;
5210 V1 = WidenVector(V1.getOperand(Idx), DAG);
5211 } else if (VT.getSizeInBits() == 64)
5212 V1 = WidenVector(V1, DAG);
5214 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5217 if (isREVMask(ShuffleMask, VT, 64))
5218 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5219 if (isREVMask(ShuffleMask, VT, 32))
5220 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5221 if (isREVMask(ShuffleMask, VT, 16))
5222 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5224 bool ReverseEXT = false;
5226 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5229 Imm *= getExtFactor(V1);
5230 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5231 DAG.getConstant(Imm, dl, MVT::i32));
5232 } else if (V2->getOpcode() == ISD::UNDEF &&
5233 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5234 Imm *= getExtFactor(V1);
5235 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5236 DAG.getConstant(Imm, dl, MVT::i32));
5239 unsigned WhichResult;
5240 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5241 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5242 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5244 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5245 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5246 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5248 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5249 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5250 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5253 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5254 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5255 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5257 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5258 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5259 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5261 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5262 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5263 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5266 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5267 if (Concat.getNode())
5272 int NumInputElements = V1.getValueType().getVectorNumElements();
5273 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5274 SDValue DstVec = DstIsLeft ? V1 : V2;
5275 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5277 SDValue SrcVec = V1;
5278 int SrcLane = ShuffleMask[Anomaly];
5279 if (SrcLane >= NumInputElements) {
5281 SrcLane -= VT.getVectorNumElements();
5283 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5285 EVT ScalarVT = VT.getVectorElementType();
5287 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5288 ScalarVT = MVT::i32;
5291 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5292 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5296 // If the shuffle is not directly supported and it has 4 elements, use
5297 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5298 unsigned NumElts = VT.getVectorNumElements();
5300 unsigned PFIndexes[4];
5301 for (unsigned i = 0; i != 4; ++i) {
5302 if (ShuffleMask[i] < 0)
5305 PFIndexes[i] = ShuffleMask[i];
5308 // Compute the index in the perfect shuffle table.
5309 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5310 PFIndexes[2] * 9 + PFIndexes[3];
5311 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5312 unsigned Cost = (PFEntry >> 30);
5315 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5318 return GenerateTBL(Op, ShuffleMask, DAG);
5321 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5323 EVT VT = BVN->getValueType(0);
5324 APInt SplatBits, SplatUndef;
5325 unsigned SplatBitSize;
5327 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5328 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5330 for (unsigned i = 0; i < NumSplats; ++i) {
5331 CnstBits <<= SplatBitSize;
5332 UndefBits <<= SplatBitSize;
5333 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5334 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5343 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5344 SelectionDAG &DAG) const {
5345 BuildVectorSDNode *BVN =
5346 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5347 SDValue LHS = Op.getOperand(0);
5349 EVT VT = Op.getValueType();
5354 APInt CnstBits(VT.getSizeInBits(), 0);
5355 APInt UndefBits(VT.getSizeInBits(), 0);
5356 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5357 // We only have BIC vector immediate instruction, which is and-not.
5358 CnstBits = ~CnstBits;
5360 // We make use of a little bit of goto ickiness in order to avoid having to
5361 // duplicate the immediate matching logic for the undef toggled case.
5362 bool SecondTry = false;
5365 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5366 CnstBits = CnstBits.zextOrTrunc(64);
5367 uint64_t CnstVal = CnstBits.getZExtValue();
5369 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5370 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5371 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5372 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5373 DAG.getConstant(CnstVal, dl, MVT::i32),
5374 DAG.getConstant(0, dl, MVT::i32));
5375 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5378 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5379 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5380 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5381 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5382 DAG.getConstant(CnstVal, dl, MVT::i32),
5383 DAG.getConstant(8, dl, MVT::i32));
5384 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5387 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5388 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5389 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5390 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5391 DAG.getConstant(CnstVal, dl, MVT::i32),
5392 DAG.getConstant(16, dl, MVT::i32));
5393 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5396 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5397 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5398 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5399 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5400 DAG.getConstant(CnstVal, dl, MVT::i32),
5401 DAG.getConstant(24, dl, MVT::i32));
5402 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5405 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5406 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5407 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5408 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5409 DAG.getConstant(CnstVal, dl, MVT::i32),
5410 DAG.getConstant(0, dl, MVT::i32));
5411 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5414 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5415 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5416 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5417 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5418 DAG.getConstant(CnstVal, dl, MVT::i32),
5419 DAG.getConstant(8, dl, MVT::i32));
5420 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5427 CnstBits = ~UndefBits;
5431 // We can always fall back to a non-immediate AND.
5436 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5437 // consists of only the same constant int value, returned in reference arg
5439 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5440 uint64_t &ConstVal) {
5441 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5444 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5447 EVT VT = Bvec->getValueType(0);
5448 unsigned NumElts = VT.getVectorNumElements();
5449 for (unsigned i = 1; i < NumElts; ++i)
5450 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5452 ConstVal = FirstElt->getZExtValue();
5456 static unsigned getIntrinsicID(const SDNode *N) {
5457 unsigned Opcode = N->getOpcode();
5460 return Intrinsic::not_intrinsic;
5461 case ISD::INTRINSIC_WO_CHAIN: {
5462 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5463 if (IID < Intrinsic::num_intrinsics)
5465 return Intrinsic::not_intrinsic;
5470 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5471 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5472 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5473 // Also, logical shift right -> sri, with the same structure.
5474 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5475 EVT VT = N->getValueType(0);
5482 // Is the first op an AND?
5483 const SDValue And = N->getOperand(0);
5484 if (And.getOpcode() != ISD::AND)
5487 // Is the second op an shl or lshr?
5488 SDValue Shift = N->getOperand(1);
5489 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5490 // or AArch64ISD::VLSHR vector, #shift
5491 unsigned ShiftOpc = Shift.getOpcode();
5492 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5494 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5496 // Is the shift amount constant?
5497 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5501 // Is the and mask vector all constant?
5503 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5506 // Is C1 == ~C2, taking into account how much one can shift elements of a
5508 uint64_t C2 = C2node->getZExtValue();
5509 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5510 if (C2 > ElemSizeInBits)
5512 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5513 if ((C1 & ElemMask) != (~C2 & ElemMask))
5516 SDValue X = And.getOperand(0);
5517 SDValue Y = Shift.getOperand(0);
5520 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5522 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5523 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5524 Shift.getOperand(1));
5526 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5527 DEBUG(N->dump(&DAG));
5528 DEBUG(dbgs() << "into: \n");
5529 DEBUG(ResultSLI->dump(&DAG));
5535 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5536 SelectionDAG &DAG) const {
5537 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5538 if (EnableAArch64SlrGeneration) {
5539 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5544 BuildVectorSDNode *BVN =
5545 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5546 SDValue LHS = Op.getOperand(1);
5548 EVT VT = Op.getValueType();
5550 // OR commutes, so try swapping the operands.
5552 LHS = Op.getOperand(0);
5553 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5558 APInt CnstBits(VT.getSizeInBits(), 0);
5559 APInt UndefBits(VT.getSizeInBits(), 0);
5560 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5561 // We make use of a little bit of goto ickiness in order to avoid having to
5562 // duplicate the immediate matching logic for the undef toggled case.
5563 bool SecondTry = false;
5566 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5567 CnstBits = CnstBits.zextOrTrunc(64);
5568 uint64_t CnstVal = CnstBits.getZExtValue();
5570 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5571 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5572 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5573 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5574 DAG.getConstant(CnstVal, dl, MVT::i32),
5575 DAG.getConstant(0, dl, MVT::i32));
5576 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5579 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5580 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5581 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5582 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5583 DAG.getConstant(CnstVal, dl, MVT::i32),
5584 DAG.getConstant(8, dl, MVT::i32));
5585 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5588 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5589 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5590 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5591 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5592 DAG.getConstant(CnstVal, dl, MVT::i32),
5593 DAG.getConstant(16, dl, MVT::i32));
5594 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5597 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5598 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5599 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5600 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5601 DAG.getConstant(CnstVal, dl, MVT::i32),
5602 DAG.getConstant(24, dl, MVT::i32));
5603 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5606 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5607 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5608 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5609 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5610 DAG.getConstant(CnstVal, dl, MVT::i32),
5611 DAG.getConstant(0, dl, MVT::i32));
5612 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5615 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5616 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5617 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5618 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5619 DAG.getConstant(CnstVal, dl, MVT::i32),
5620 DAG.getConstant(8, dl, MVT::i32));
5621 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5628 CnstBits = UndefBits;
5632 // We can always fall back to a non-immediate OR.
5637 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5638 // be truncated to fit element width.
5639 static SDValue NormalizeBuildVector(SDValue Op,
5640 SelectionDAG &DAG) {
5641 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5643 EVT VT = Op.getValueType();
5644 EVT EltTy= VT.getVectorElementType();
5646 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5649 SmallVector<SDValue, 16> Ops;
5650 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5651 SDValue Lane = Op.getOperand(I);
5652 if (Lane.getOpcode() == ISD::Constant) {
5653 APInt LowBits(EltTy.getSizeInBits(),
5654 cast<ConstantSDNode>(Lane)->getZExtValue());
5655 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5657 Ops.push_back(Lane);
5659 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5662 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5663 SelectionDAG &DAG) const {
5665 EVT VT = Op.getValueType();
5666 Op = NormalizeBuildVector(Op, DAG);
5667 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5669 APInt CnstBits(VT.getSizeInBits(), 0);
5670 APInt UndefBits(VT.getSizeInBits(), 0);
5671 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5672 // We make use of a little bit of goto ickiness in order to avoid having to
5673 // duplicate the immediate matching logic for the undef toggled case.
5674 bool SecondTry = false;
5677 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5678 CnstBits = CnstBits.zextOrTrunc(64);
5679 uint64_t CnstVal = CnstBits.getZExtValue();
5681 // Certain magic vector constants (used to express things like NOT
5682 // and NEG) are passed through unmodified. This allows codegen patterns
5683 // for these operations to match. Special-purpose patterns will lower
5684 // these immediates to MOVIs if it proves necessary.
5685 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5688 // The many faces of MOVI...
5689 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5690 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5691 if (VT.getSizeInBits() == 128) {
5692 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5693 DAG.getConstant(CnstVal, dl, MVT::i32));
5694 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5697 // Support the V64 version via subregister insertion.
5698 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5699 DAG.getConstant(CnstVal, dl, MVT::i32));
5700 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5703 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5704 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5705 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5706 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5707 DAG.getConstant(CnstVal, dl, MVT::i32),
5708 DAG.getConstant(0, dl, MVT::i32));
5709 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5712 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5713 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5714 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5715 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5716 DAG.getConstant(CnstVal, dl, MVT::i32),
5717 DAG.getConstant(8, dl, MVT::i32));
5718 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5721 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5722 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5723 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5724 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5725 DAG.getConstant(CnstVal, dl, MVT::i32),
5726 DAG.getConstant(16, dl, MVT::i32));
5727 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5730 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5731 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5732 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5733 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5734 DAG.getConstant(CnstVal, dl, MVT::i32),
5735 DAG.getConstant(24, dl, MVT::i32));
5736 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5739 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5740 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5741 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5742 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5743 DAG.getConstant(CnstVal, dl, MVT::i32),
5744 DAG.getConstant(0, dl, MVT::i32));
5745 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5748 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5749 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5750 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5751 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5752 DAG.getConstant(CnstVal, dl, MVT::i32),
5753 DAG.getConstant(8, dl, MVT::i32));
5754 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5757 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5758 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5759 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5760 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5761 DAG.getConstant(CnstVal, dl, MVT::i32),
5762 DAG.getConstant(264, dl, MVT::i32));
5763 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5766 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5767 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5768 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5769 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5770 DAG.getConstant(CnstVal, dl, MVT::i32),
5771 DAG.getConstant(272, dl, MVT::i32));
5772 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5775 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5776 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5777 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5778 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5779 DAG.getConstant(CnstVal, dl, MVT::i32));
5780 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5783 // The few faces of FMOV...
5784 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5785 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5786 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5787 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5788 DAG.getConstant(CnstVal, dl, MVT::i32));
5789 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5792 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5793 VT.getSizeInBits() == 128) {
5794 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5795 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5796 DAG.getConstant(CnstVal, dl, MVT::i32));
5797 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5800 // The many faces of MVNI...
5802 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5803 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5804 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5805 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5806 DAG.getConstant(CnstVal, dl, MVT::i32),
5807 DAG.getConstant(0, dl, MVT::i32));
5808 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5811 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5812 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5813 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5814 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5815 DAG.getConstant(CnstVal, dl, MVT::i32),
5816 DAG.getConstant(8, dl, MVT::i32));
5817 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5820 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5821 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5822 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5823 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5824 DAG.getConstant(CnstVal, dl, MVT::i32),
5825 DAG.getConstant(16, dl, MVT::i32));
5826 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5829 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5830 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5831 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5832 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5833 DAG.getConstant(CnstVal, dl, MVT::i32),
5834 DAG.getConstant(24, dl, MVT::i32));
5835 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5838 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5839 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5840 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5841 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5842 DAG.getConstant(CnstVal, dl, MVT::i32),
5843 DAG.getConstant(0, dl, MVT::i32));
5844 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5847 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5848 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5849 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5850 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5851 DAG.getConstant(CnstVal, dl, MVT::i32),
5852 DAG.getConstant(8, dl, MVT::i32));
5853 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5856 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5857 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5858 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5859 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5860 DAG.getConstant(CnstVal, dl, MVT::i32),
5861 DAG.getConstant(264, dl, MVT::i32));
5862 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5865 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5866 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5867 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5868 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5869 DAG.getConstant(CnstVal, dl, MVT::i32),
5870 DAG.getConstant(272, dl, MVT::i32));
5871 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5878 CnstBits = UndefBits;
5883 // Scan through the operands to find some interesting properties we can
5885 // 1) If only one value is used, we can use a DUP, or
5886 // 2) if only the low element is not undef, we can just insert that, or
5887 // 3) if only one constant value is used (w/ some non-constant lanes),
5888 // we can splat the constant value into the whole vector then fill
5889 // in the non-constant lanes.
5890 // 4) FIXME: If different constant values are used, but we can intelligently
5891 // select the values we'll be overwriting for the non-constant
5892 // lanes such that we can directly materialize the vector
5893 // some other way (MOVI, e.g.), we can be sneaky.
5894 unsigned NumElts = VT.getVectorNumElements();
5895 bool isOnlyLowElement = true;
5896 bool usesOnlyOneValue = true;
5897 bool usesOnlyOneConstantValue = true;
5898 bool isConstant = true;
5899 unsigned NumConstantLanes = 0;
5901 SDValue ConstantValue;
5902 for (unsigned i = 0; i < NumElts; ++i) {
5903 SDValue V = Op.getOperand(i);
5904 if (V.getOpcode() == ISD::UNDEF)
5907 isOnlyLowElement = false;
5908 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5911 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5913 if (!ConstantValue.getNode())
5915 else if (ConstantValue != V)
5916 usesOnlyOneConstantValue = false;
5919 if (!Value.getNode())
5921 else if (V != Value)
5922 usesOnlyOneValue = false;
5925 if (!Value.getNode())
5926 return DAG.getUNDEF(VT);
5928 if (isOnlyLowElement)
5929 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5931 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5932 // i32 and try again.
5933 if (usesOnlyOneValue) {
5935 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5936 Value.getValueType() != VT)
5937 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5939 // This is actually a DUPLANExx operation, which keeps everything vectory.
5941 // DUPLANE works on 128-bit vectors, widen it if necessary.
5942 SDValue Lane = Value.getOperand(1);
5943 Value = Value.getOperand(0);
5944 if (Value.getValueType().getSizeInBits() == 64)
5945 Value = WidenVector(Value, DAG);
5947 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5948 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5951 if (VT.getVectorElementType().isFloatingPoint()) {
5952 SmallVector<SDValue, 8> Ops;
5953 EVT EltTy = VT.getVectorElementType();
5954 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5955 "Unsupported floating-point vector type");
5956 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5957 for (unsigned i = 0; i < NumElts; ++i)
5958 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5959 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5960 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5961 Val = LowerBUILD_VECTOR(Val, DAG);
5963 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5967 // If there was only one constant value used and for more than one lane,
5968 // start by splatting that value, then replace the non-constant lanes. This
5969 // is better than the default, which will perform a separate initialization
5971 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5972 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5973 // Now insert the non-constant lanes.
5974 for (unsigned i = 0; i < NumElts; ++i) {
5975 SDValue V = Op.getOperand(i);
5976 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
5977 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5978 // Note that type legalization likely mucked about with the VT of the
5979 // source operand, so we may have to convert it here before inserting.
5980 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5986 // If all elements are constants and the case above didn't get hit, fall back
5987 // to the default expansion, which will generate a load from the constant
5992 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5994 SDValue shuffle = ReconstructShuffle(Op, DAG);
5995 if (shuffle != SDValue())
5999 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6000 // know the default expansion would otherwise fall back on something even
6001 // worse. For a vector with one or two non-undef values, that's
6002 // scalar_to_vector for the elements followed by a shuffle (provided the
6003 // shuffle is valid for the target) and materialization element by element
6004 // on the stack followed by a load for everything else.
6005 if (!isConstant && !usesOnlyOneValue) {
6006 SDValue Vec = DAG.getUNDEF(VT);
6007 SDValue Op0 = Op.getOperand(0);
6008 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6010 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6011 // a) Avoid a RMW dependency on the full vector register, and
6012 // b) Allow the register coalescer to fold away the copy if the
6013 // value is already in an S or D register.
6014 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6015 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6017 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6018 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6019 Vec = SDValue(N, 0);
6022 for (; i < NumElts; ++i) {
6023 SDValue V = Op.getOperand(i);
6024 if (V.getOpcode() == ISD::UNDEF)
6026 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6027 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6032 // Just use the default expansion. We failed to find a better alternative.
6036 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6037 SelectionDAG &DAG) const {
6038 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6040 // Check for non-constant or out of range lane.
6041 EVT VT = Op.getOperand(0).getValueType();
6042 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6043 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6047 // Insertion/extraction are legal for V128 types.
6048 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6049 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6053 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6054 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6057 // For V64 types, we perform insertion by expanding the value
6058 // to a V128 type and perform the insertion on that.
6060 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6061 EVT WideTy = WideVec.getValueType();
6063 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6064 Op.getOperand(1), Op.getOperand(2));
6065 // Re-narrow the resultant vector.
6066 return NarrowVector(Node, DAG);
6070 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6071 SelectionDAG &DAG) const {
6072 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6074 // Check for non-constant or out of range lane.
6075 EVT VT = Op.getOperand(0).getValueType();
6076 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6077 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6081 // Insertion/extraction are legal for V128 types.
6082 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6083 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6087 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6088 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6091 // For V64 types, we perform extraction by expanding the value
6092 // to a V128 type and perform the extraction on that.
6094 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6095 EVT WideTy = WideVec.getValueType();
6097 EVT ExtrTy = WideTy.getVectorElementType();
6098 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6101 // For extractions, we just return the result directly.
6102 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6106 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6107 SelectionDAG &DAG) const {
6108 EVT VT = Op.getOperand(0).getValueType();
6114 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6117 unsigned Val = Cst->getZExtValue();
6119 unsigned Size = Op.getValueType().getSizeInBits();
6123 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6126 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6129 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6132 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6135 llvm_unreachable("Unexpected vector type in extract_subvector!");
6138 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6140 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6146 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6148 if (VT.getVectorNumElements() == 4 &&
6149 (VT.is128BitVector() || VT.is64BitVector())) {
6150 unsigned PFIndexes[4];
6151 for (unsigned i = 0; i != 4; ++i) {
6155 PFIndexes[i] = M[i];
6158 // Compute the index in the perfect shuffle table.
6159 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6160 PFIndexes[2] * 9 + PFIndexes[3];
6161 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6162 unsigned Cost = (PFEntry >> 30);
6170 unsigned DummyUnsigned;
6172 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6173 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6174 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6175 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6176 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6177 isZIPMask(M, VT, DummyUnsigned) ||
6178 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6179 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6180 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6181 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6182 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6185 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6186 /// operand of a vector shift operation, where all the elements of the
6187 /// build_vector must have the same constant integer value.
6188 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6189 // Ignore bit_converts.
6190 while (Op.getOpcode() == ISD::BITCAST)
6191 Op = Op.getOperand(0);
6192 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6193 APInt SplatBits, SplatUndef;
6194 unsigned SplatBitSize;
6196 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6197 HasAnyUndefs, ElementBits) ||
6198 SplatBitSize > ElementBits)
6200 Cnt = SplatBits.getSExtValue();
6204 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6205 /// operand of a vector shift left operation. That value must be in the range:
6206 /// 0 <= Value < ElementBits for a left shift; or
6207 /// 0 <= Value <= ElementBits for a long left shift.
6208 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6209 assert(VT.isVector() && "vector shift count is not a vector type");
6210 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6211 if (!getVShiftImm(Op, ElementBits, Cnt))
6213 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6216 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6217 /// operand of a vector shift right operation. For a shift opcode, the value
6218 /// is positive, but for an intrinsic the value count must be negative. The
6219 /// absolute value must be in the range:
6220 /// 1 <= |Value| <= ElementBits for a right shift; or
6221 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6222 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6224 assert(VT.isVector() && "vector shift count is not a vector type");
6225 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6226 if (!getVShiftImm(Op, ElementBits, Cnt))
6230 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6233 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6234 SelectionDAG &DAG) const {
6235 EVT VT = Op.getValueType();
6239 if (!Op.getOperand(1).getValueType().isVector())
6241 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6243 switch (Op.getOpcode()) {
6245 llvm_unreachable("unexpected shift opcode");
6248 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6249 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6250 DAG.getConstant(Cnt, DL, MVT::i32));
6251 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6252 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6254 Op.getOperand(0), Op.getOperand(1));
6257 // Right shift immediate
6258 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6261 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6262 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6263 DAG.getConstant(Cnt, DL, MVT::i32));
6266 // Right shift register. Note, there is not a shift right register
6267 // instruction, but the shift left register instruction takes a signed
6268 // value, where negative numbers specify a right shift.
6269 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6270 : Intrinsic::aarch64_neon_ushl;
6271 // negate the shift amount
6272 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6273 SDValue NegShiftLeft =
6274 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6275 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6277 return NegShiftLeft;
6283 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6284 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6285 SDLoc dl, SelectionDAG &DAG) {
6286 EVT SrcVT = LHS.getValueType();
6287 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6288 "function only supposed to emit natural comparisons");
6290 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6291 APInt CnstBits(VT.getSizeInBits(), 0);
6292 APInt UndefBits(VT.getSizeInBits(), 0);
6293 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6294 bool IsZero = IsCnst && (CnstBits == 0);
6296 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6300 case AArch64CC::NE: {
6303 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6305 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6306 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6310 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6311 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6314 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6315 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6318 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6319 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6322 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6323 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6327 // If we ignore NaNs then we can use to the MI implementation.
6331 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6332 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6339 case AArch64CC::NE: {
6342 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6344 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6345 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6349 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6350 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6353 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6354 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6357 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6358 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6361 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6362 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6364 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6366 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6369 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6370 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6372 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6374 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6378 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6379 SelectionDAG &DAG) const {
6380 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6381 SDValue LHS = Op.getOperand(0);
6382 SDValue RHS = Op.getOperand(1);
6383 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6386 if (LHS.getValueType().getVectorElementType().isInteger()) {
6387 assert(LHS.getValueType() == RHS.getValueType());
6388 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6390 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6391 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6394 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6395 LHS.getValueType().getVectorElementType() == MVT::f64);
6397 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6398 // clean. Some of them require two branches to implement.
6399 AArch64CC::CondCode CC1, CC2;
6401 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6403 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6405 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6409 if (CC2 != AArch64CC::AL) {
6411 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6412 if (!Cmp2.getNode())
6415 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6418 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6421 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6426 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6427 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6428 /// specified in the intrinsic calls.
6429 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6431 unsigned Intrinsic) const {
6432 switch (Intrinsic) {
6433 case Intrinsic::aarch64_neon_ld2:
6434 case Intrinsic::aarch64_neon_ld3:
6435 case Intrinsic::aarch64_neon_ld4:
6436 case Intrinsic::aarch64_neon_ld1x2:
6437 case Intrinsic::aarch64_neon_ld1x3:
6438 case Intrinsic::aarch64_neon_ld1x4:
6439 case Intrinsic::aarch64_neon_ld2lane:
6440 case Intrinsic::aarch64_neon_ld3lane:
6441 case Intrinsic::aarch64_neon_ld4lane:
6442 case Intrinsic::aarch64_neon_ld2r:
6443 case Intrinsic::aarch64_neon_ld3r:
6444 case Intrinsic::aarch64_neon_ld4r: {
6445 Info.opc = ISD::INTRINSIC_W_CHAIN;
6446 // Conservatively set memVT to the entire set of vectors loaded.
6447 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6448 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6449 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6452 Info.vol = false; // volatile loads with NEON intrinsics not supported
6453 Info.readMem = true;
6454 Info.writeMem = false;
6457 case Intrinsic::aarch64_neon_st2:
6458 case Intrinsic::aarch64_neon_st3:
6459 case Intrinsic::aarch64_neon_st4:
6460 case Intrinsic::aarch64_neon_st1x2:
6461 case Intrinsic::aarch64_neon_st1x3:
6462 case Intrinsic::aarch64_neon_st1x4:
6463 case Intrinsic::aarch64_neon_st2lane:
6464 case Intrinsic::aarch64_neon_st3lane:
6465 case Intrinsic::aarch64_neon_st4lane: {
6466 Info.opc = ISD::INTRINSIC_VOID;
6467 // Conservatively set memVT to the entire set of vectors stored.
6468 unsigned NumElts = 0;
6469 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6470 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6471 if (!ArgTy->isVectorTy())
6473 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6475 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6476 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6479 Info.vol = false; // volatile stores with NEON intrinsics not supported
6480 Info.readMem = false;
6481 Info.writeMem = true;
6484 case Intrinsic::aarch64_ldaxr:
6485 case Intrinsic::aarch64_ldxr: {
6486 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6487 Info.opc = ISD::INTRINSIC_W_CHAIN;
6488 Info.memVT = MVT::getVT(PtrTy->getElementType());
6489 Info.ptrVal = I.getArgOperand(0);
6491 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6493 Info.readMem = true;
6494 Info.writeMem = false;
6497 case Intrinsic::aarch64_stlxr:
6498 case Intrinsic::aarch64_stxr: {
6499 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6500 Info.opc = ISD::INTRINSIC_W_CHAIN;
6501 Info.memVT = MVT::getVT(PtrTy->getElementType());
6502 Info.ptrVal = I.getArgOperand(1);
6504 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6506 Info.readMem = false;
6507 Info.writeMem = true;
6510 case Intrinsic::aarch64_ldaxp:
6511 case Intrinsic::aarch64_ldxp: {
6512 Info.opc = ISD::INTRINSIC_W_CHAIN;
6513 Info.memVT = MVT::i128;
6514 Info.ptrVal = I.getArgOperand(0);
6518 Info.readMem = true;
6519 Info.writeMem = false;
6522 case Intrinsic::aarch64_stlxp:
6523 case Intrinsic::aarch64_stxp: {
6524 Info.opc = ISD::INTRINSIC_W_CHAIN;
6525 Info.memVT = MVT::i128;
6526 Info.ptrVal = I.getArgOperand(2);
6530 Info.readMem = false;
6531 Info.writeMem = true;
6541 // Truncations from 64-bit GPR to 32-bit GPR is free.
6542 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6543 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6545 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6546 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6547 return NumBits1 > NumBits2;
6549 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6550 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6552 unsigned NumBits1 = VT1.getSizeInBits();
6553 unsigned NumBits2 = VT2.getSizeInBits();
6554 return NumBits1 > NumBits2;
6557 /// Check if it is profitable to hoist instruction in then/else to if.
6558 /// Not profitable if I and it's user can form a FMA instruction
6559 /// because we prefer FMSUB/FMADD.
6560 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6561 if (I->getOpcode() != Instruction::FMul)
6564 if (I->getNumUses() != 1)
6567 Instruction *User = I->user_back();
6570 !(User->getOpcode() == Instruction::FSub ||
6571 User->getOpcode() == Instruction::FAdd))
6574 const TargetOptions &Options = getTargetMachine().Options;
6575 EVT VT = getValueType(User->getOperand(0)->getType());
6577 if (isFMAFasterThanFMulAndFAdd(VT) &&
6578 isOperationLegalOrCustom(ISD::FMA, VT) &&
6579 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6585 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6587 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6588 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6590 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6591 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6592 return NumBits1 == 32 && NumBits2 == 64;
6594 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6595 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6597 unsigned NumBits1 = VT1.getSizeInBits();
6598 unsigned NumBits2 = VT2.getSizeInBits();
6599 return NumBits1 == 32 && NumBits2 == 64;
6602 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6603 EVT VT1 = Val.getValueType();
6604 if (isZExtFree(VT1, VT2)) {
6608 if (Val.getOpcode() != ISD::LOAD)
6611 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6612 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6613 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6614 VT1.getSizeInBits() <= 32);
6617 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6618 if (isa<FPExtInst>(Ext))
6621 // Vector types are next free.
6622 if (Ext->getType()->isVectorTy())
6625 for (const Use &U : Ext->uses()) {
6626 // The extension is free if we can fold it with a left shift in an
6627 // addressing mode or an arithmetic operation: add, sub, and cmp.
6629 // Is there a shift?
6630 const Instruction *Instr = cast<Instruction>(U.getUser());
6632 // Is this a constant shift?
6633 switch (Instr->getOpcode()) {
6634 case Instruction::Shl:
6635 if (!isa<ConstantInt>(Instr->getOperand(1)))
6638 case Instruction::GetElementPtr: {
6639 gep_type_iterator GTI = gep_type_begin(Instr);
6640 std::advance(GTI, U.getOperandNo());
6642 // This extension will end up with a shift because of the scaling factor.
6643 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6644 // Get the shift amount based on the scaling factor:
6645 // log2(sizeof(IdxTy)) - log2(8).
6647 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6648 // Is the constant foldable in the shift of the addressing mode?
6649 // I.e., shift amount is between 1 and 4 inclusive.
6650 if (ShiftAmt == 0 || ShiftAmt > 4)
6654 case Instruction::Trunc:
6655 // Check if this is a noop.
6656 // trunc(sext ty1 to ty2) to ty1.
6657 if (Instr->getType() == Ext->getOperand(0)->getType())
6664 // At this point we can use the bfm family, so this extension is free
6670 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6671 unsigned &RequiredAligment) const {
6672 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6674 // Cyclone supports unaligned accesses.
6675 RequiredAligment = 0;
6676 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6677 return NumBits == 32 || NumBits == 64;
6680 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6681 unsigned &RequiredAligment) const {
6682 if (!LoadedType.isSimple() ||
6683 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6685 // Cyclone supports unaligned accesses.
6686 RequiredAligment = 0;
6687 unsigned NumBits = LoadedType.getSizeInBits();
6688 return NumBits == 32 || NumBits == 64;
6691 /// \brief Lower an interleaved load into a ldN intrinsic.
6693 /// E.g. Lower an interleaved load (Factor = 2):
6694 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6695 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6696 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6699 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6700 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6701 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6702 bool AArch64TargetLowering::lowerInterleavedLoad(
6703 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6704 ArrayRef<unsigned> Indices, unsigned Factor) const {
6705 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6706 "Invalid interleave factor");
6707 assert(!Shuffles.empty() && "Empty shufflevector input");
6708 assert(Shuffles.size() == Indices.size() &&
6709 "Unmatched number of shufflevectors and indices");
6711 const DataLayout *DL = getDataLayout();
6713 VectorType *VecTy = Shuffles[0]->getType();
6714 unsigned VecSize = DL->getTypeAllocSizeInBits(VecTy);
6716 // Skip illegal vector types.
6717 if (VecSize != 64 && VecSize != 128)
6720 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6721 // load integer vectors first and then convert to pointer vectors.
6722 Type *EltTy = VecTy->getVectorElementType();
6723 if (EltTy->isPointerTy())
6724 VecTy = VectorType::get(DL->getIntPtrType(EltTy),
6725 VecTy->getVectorNumElements());
6727 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
6728 Type *Tys[2] = {VecTy, PtrTy};
6729 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
6730 Intrinsic::aarch64_neon_ld3,
6731 Intrinsic::aarch64_neon_ld4};
6733 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
6735 IRBuilder<> Builder(LI);
6736 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
6738 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
6740 // Replace uses of each shufflevector with the corresponding vector loaded
6742 for (unsigned i = 0; i < Shuffles.size(); i++) {
6743 ShuffleVectorInst *SVI = Shuffles[i];
6744 unsigned Index = Indices[i];
6746 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
6748 // Convert the integer vector to pointer vector if the element is pointer.
6749 if (EltTy->isPointerTy())
6750 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
6752 SVI->replaceAllUsesWith(SubVec);
6758 /// \brief Get a mask consisting of sequential integers starting from \p Start.
6760 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
6761 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
6763 SmallVector<Constant *, 16> Mask;
6764 for (unsigned i = 0; i < NumElts; i++)
6765 Mask.push_back(Builder.getInt32(Start + i));
6767 return ConstantVector::get(Mask);
6770 /// \brief Lower an interleaved store into a stN intrinsic.
6772 /// E.g. Lower an interleaved store (Factor = 3):
6773 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
6774 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
6775 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
6778 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
6779 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
6780 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
6781 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
6783 /// Note that the new shufflevectors will be removed and we'll only generate one
6784 /// st3 instruction in CodeGen.
6785 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
6786 ShuffleVectorInst *SVI,
6787 unsigned Factor) const {
6788 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6789 "Invalid interleave factor");
6791 VectorType *VecTy = SVI->getType();
6792 assert(VecTy->getVectorNumElements() % Factor == 0 &&
6793 "Invalid interleaved store");
6795 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
6796 Type *EltTy = VecTy->getVectorElementType();
6797 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
6799 const DataLayout *DL = getDataLayout();
6800 unsigned SubVecSize = DL->getTypeAllocSizeInBits(SubVecTy);
6802 // Skip illegal vector types.
6803 if (SubVecSize != 64 && SubVecSize != 128)
6806 Value *Op0 = SVI->getOperand(0);
6807 Value *Op1 = SVI->getOperand(1);
6808 IRBuilder<> Builder(SI);
6810 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
6811 // vectors to integer vectors.
6812 if (EltTy->isPointerTy()) {
6813 Type *IntTy = DL->getIntPtrType(EltTy);
6814 unsigned NumOpElts =
6815 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
6817 // Convert to the corresponding integer vector.
6818 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
6819 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
6820 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
6822 SubVecTy = VectorType::get(IntTy, NumSubElts);
6825 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
6826 Type *Tys[2] = {SubVecTy, PtrTy};
6827 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
6828 Intrinsic::aarch64_neon_st3,
6829 Intrinsic::aarch64_neon_st4};
6831 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
6833 SmallVector<Value *, 5> Ops;
6835 // Split the shufflevector operands into sub vectors for the new stN call.
6836 for (unsigned i = 0; i < Factor; i++)
6837 Ops.push_back(Builder.CreateShuffleVector(
6838 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
6840 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
6841 Builder.CreateCall(StNFunc, Ops);
6845 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6846 unsigned AlignCheck) {
6847 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6848 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6851 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6852 unsigned SrcAlign, bool IsMemset,
6855 MachineFunction &MF) const {
6856 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6857 // instruction to materialize the v2i64 zero and one store (with restrictive
6858 // addressing mode). Just do two i64 store of zero-registers.
6860 const Function *F = MF.getFunction();
6861 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6862 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6863 (memOpAlign(SrcAlign, DstAlign, 16) ||
6864 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6868 (memOpAlign(SrcAlign, DstAlign, 8) ||
6869 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
6873 (memOpAlign(SrcAlign, DstAlign, 4) ||
6874 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
6880 // 12-bit optionally shifted immediates are legal for adds.
6881 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6882 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6887 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6888 // immediates is the same as for an add or a sub.
6889 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6892 return isLegalAddImmediate(Immed);
6895 /// isLegalAddressingMode - Return true if the addressing mode represented
6896 /// by AM is legal for this target, for a load/store of the specified type.
6897 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6899 unsigned AS) const {
6900 // AArch64 has five basic addressing modes:
6902 // reg + 9-bit signed offset
6903 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6905 // reg + SIZE_IN_BYTES * reg
6907 // No global is ever allowed as a base.
6911 // No reg+reg+imm addressing.
6912 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6915 // check reg + imm case:
6916 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6917 uint64_t NumBytes = 0;
6918 if (Ty->isSized()) {
6919 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6920 NumBytes = NumBits / 8;
6921 if (!isPowerOf2_64(NumBits))
6926 int64_t Offset = AM.BaseOffs;
6928 // 9-bit signed offset
6929 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6932 // 12-bit unsigned offset
6933 unsigned shift = Log2_64(NumBytes);
6934 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6935 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6936 (Offset >> shift) << shift == Offset)
6941 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6943 if (!AM.Scale || AM.Scale == 1 ||
6944 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6949 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6951 unsigned AS) const {
6952 // Scaling factors are not free at all.
6953 // Operands | Rt Latency
6954 // -------------------------------------------
6956 // -------------------------------------------
6957 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6958 // Rt, [Xn, Wm, <extend> #imm] |
6959 if (isLegalAddressingMode(AM, Ty, AS))
6960 // Scale represents reg2 * scale, thus account for 1 if
6961 // it is not equal to 0 or 1.
6962 return AM.Scale != 0 && AM.Scale != 1;
6966 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6967 VT = VT.getScalarType();
6972 switch (VT.getSimpleVT().SimpleTy) {
6984 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6985 // LR is a callee-save register, but we must treat it as clobbered by any call
6986 // site. Hence we include LR in the scratch registers, which are in turn added
6987 // as implicit-defs for stackmaps and patchpoints.
6988 static const MCPhysReg ScratchRegs[] = {
6989 AArch64::X16, AArch64::X17, AArch64::LR, 0
6995 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6996 EVT VT = N->getValueType(0);
6997 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6998 // it with shift to let it be lowered to UBFX.
6999 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7000 isa<ConstantSDNode>(N->getOperand(1))) {
7001 uint64_t TruncMask = N->getConstantOperandVal(1);
7002 if (isMask_64(TruncMask) &&
7003 N->getOperand(0).getOpcode() == ISD::SRL &&
7004 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7010 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7012 assert(Ty->isIntegerTy());
7014 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7018 int64_t Val = Imm.getSExtValue();
7019 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7022 if ((int64_t)Val < 0)
7025 Val &= (1LL << 32) - 1;
7027 unsigned LZ = countLeadingZeros((uint64_t)Val);
7028 unsigned Shift = (63 - LZ) / 16;
7029 // MOVZ is free so return true for one or fewer MOVK.
7033 // Generate SUBS and CSEL for integer abs.
7034 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7035 EVT VT = N->getValueType(0);
7037 SDValue N0 = N->getOperand(0);
7038 SDValue N1 = N->getOperand(1);
7041 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7042 // and change it to SUB and CSEL.
7043 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7044 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7045 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7046 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7047 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7048 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7050 // Generate SUBS & CSEL.
7052 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7053 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7054 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7055 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7056 SDValue(Cmp.getNode(), 1));
7061 // performXorCombine - Attempts to handle integer ABS.
7062 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7063 TargetLowering::DAGCombinerInfo &DCI,
7064 const AArch64Subtarget *Subtarget) {
7065 if (DCI.isBeforeLegalizeOps())
7068 return performIntegerAbsCombine(N, DAG);
7072 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7074 std::vector<SDNode *> *Created) const {
7075 // fold (sdiv X, pow2)
7076 EVT VT = N->getValueType(0);
7077 if ((VT != MVT::i32 && VT != MVT::i64) ||
7078 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7082 SDValue N0 = N->getOperand(0);
7083 unsigned Lg2 = Divisor.countTrailingZeros();
7084 SDValue Zero = DAG.getConstant(0, DL, VT);
7085 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7087 // Add (N0 < 0) ? Pow2 - 1 : 0;
7089 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7090 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7091 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7094 Created->push_back(Cmp.getNode());
7095 Created->push_back(Add.getNode());
7096 Created->push_back(CSel.getNode());
7101 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7103 // If we're dividing by a positive value, we're done. Otherwise, we must
7104 // negate the result.
7105 if (Divisor.isNonNegative())
7109 Created->push_back(SRA.getNode());
7110 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7113 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7114 TargetLowering::DAGCombinerInfo &DCI,
7115 const AArch64Subtarget *Subtarget) {
7116 if (DCI.isBeforeLegalizeOps())
7119 // Multiplication of a power of two plus/minus one can be done more
7120 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7121 // future CPUs have a cheaper MADD instruction, this may need to be
7122 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7123 // 64-bit is 5 cycles, so this is always a win.
7124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7125 APInt Value = C->getAPIntValue();
7126 EVT VT = N->getValueType(0);
7128 if (Value.isNonNegative()) {
7129 // (mul x, 2^N + 1) => (add (shl x, N), x)
7130 APInt VM1 = Value - 1;
7131 if (VM1.isPowerOf2()) {
7132 SDValue ShiftedVal =
7133 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7134 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7135 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7138 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7139 APInt VP1 = Value + 1;
7140 if (VP1.isPowerOf2()) {
7141 SDValue ShiftedVal =
7142 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7143 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7144 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7148 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7149 APInt VNP1 = -Value + 1;
7150 if (VNP1.isPowerOf2()) {
7151 SDValue ShiftedVal =
7152 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7153 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7154 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7157 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7158 APInt VNM1 = -Value - 1;
7159 if (VNM1.isPowerOf2()) {
7160 SDValue ShiftedVal =
7161 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7162 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7164 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7165 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7172 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7173 SelectionDAG &DAG) {
7174 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7175 // optimize away operation when it's from a constant.
7177 // The general transformation is:
7178 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7179 // AND(VECTOR_CMP(x,y), constant2)
7180 // constant2 = UNARYOP(constant)
7182 // Early exit if this isn't a vector operation, the operand of the
7183 // unary operation isn't a bitwise AND, or if the sizes of the operations
7185 EVT VT = N->getValueType(0);
7186 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7187 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7188 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7191 // Now check that the other operand of the AND is a constant. We could
7192 // make the transformation for non-constant splats as well, but it's unclear
7193 // that would be a benefit as it would not eliminate any operations, just
7194 // perform one more step in scalar code before moving to the vector unit.
7195 if (BuildVectorSDNode *BV =
7196 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7197 // Bail out if the vector isn't a constant.
7198 if (!BV->isConstant())
7201 // Everything checks out. Build up the new and improved node.
7203 EVT IntVT = BV->getValueType(0);
7204 // Create a new constant of the appropriate type for the transformed
7206 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7207 // The AND node needs bitcasts to/from an integer vector type around it.
7208 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7209 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7210 N->getOperand(0)->getOperand(0), MaskConst);
7211 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7218 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7219 const AArch64Subtarget *Subtarget) {
7220 // First try to optimize away the conversion when it's conditionally from
7221 // a constant. Vectors only.
7222 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7223 if (Res != SDValue())
7226 EVT VT = N->getValueType(0);
7227 if (VT != MVT::f32 && VT != MVT::f64)
7230 // Only optimize when the source and destination types have the same width.
7231 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7234 // If the result of an integer load is only used by an integer-to-float
7235 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7236 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7237 SDValue N0 = N->getOperand(0);
7238 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7239 // Do not change the width of a volatile load.
7240 !cast<LoadSDNode>(N0)->isVolatile()) {
7241 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7242 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7243 LN0->getPointerInfo(), LN0->isVolatile(),
7244 LN0->isNonTemporal(), LN0->isInvariant(),
7245 LN0->getAlignment());
7247 // Make sure successors of the original load stay after it by updating them
7248 // to use the new Chain.
7249 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7252 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7253 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7259 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7260 /// searches for and classifies those shifts.
7261 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7263 if (N.getOpcode() == ISD::SHL)
7265 else if (N.getOpcode() == ISD::SRL)
7270 if (!isa<ConstantSDNode>(N.getOperand(1)))
7273 ShiftAmount = N->getConstantOperandVal(1);
7274 Src = N->getOperand(0);
7278 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7279 /// registers viewed as a high/low pair. This function looks for the pattern:
7280 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7281 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7283 static SDValue tryCombineToEXTR(SDNode *N,
7284 TargetLowering::DAGCombinerInfo &DCI) {
7285 SelectionDAG &DAG = DCI.DAG;
7287 EVT VT = N->getValueType(0);
7289 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7291 if (VT != MVT::i32 && VT != MVT::i64)
7295 uint32_t ShiftLHS = 0;
7297 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7301 uint32_t ShiftRHS = 0;
7303 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7306 // If they're both trying to come from the high part of the register, they're
7307 // not really an EXTR.
7308 if (LHSFromHi == RHSFromHi)
7311 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7315 std::swap(LHS, RHS);
7316 std::swap(ShiftLHS, ShiftRHS);
7319 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7320 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7323 static SDValue tryCombineToBSL(SDNode *N,
7324 TargetLowering::DAGCombinerInfo &DCI) {
7325 EVT VT = N->getValueType(0);
7326 SelectionDAG &DAG = DCI.DAG;
7332 SDValue N0 = N->getOperand(0);
7333 if (N0.getOpcode() != ISD::AND)
7336 SDValue N1 = N->getOperand(1);
7337 if (N1.getOpcode() != ISD::AND)
7340 // We only have to look for constant vectors here since the general, variable
7341 // case can be handled in TableGen.
7342 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7343 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7344 for (int i = 1; i >= 0; --i)
7345 for (int j = 1; j >= 0; --j) {
7346 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7347 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7351 bool FoundMatch = true;
7352 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7353 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7354 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7356 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7363 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7364 N0->getOperand(1 - i), N1->getOperand(1 - j));
7370 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7371 const AArch64Subtarget *Subtarget) {
7372 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7373 if (!EnableAArch64ExtrGeneration)
7375 SelectionDAG &DAG = DCI.DAG;
7376 EVT VT = N->getValueType(0);
7378 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7381 SDValue Res = tryCombineToEXTR(N, DCI);
7385 Res = tryCombineToBSL(N, DCI);
7392 static SDValue performBitcastCombine(SDNode *N,
7393 TargetLowering::DAGCombinerInfo &DCI,
7394 SelectionDAG &DAG) {
7395 // Wait 'til after everything is legalized to try this. That way we have
7396 // legal vector types and such.
7397 if (DCI.isBeforeLegalizeOps())
7400 // Remove extraneous bitcasts around an extract_subvector.
7402 // (v4i16 (bitconvert
7403 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7405 // (extract_subvector ((v8i16 ...), (i64 4)))
7407 // Only interested in 64-bit vectors as the ultimate result.
7408 EVT VT = N->getValueType(0);
7411 if (VT.getSimpleVT().getSizeInBits() != 64)
7413 // Is the operand an extract_subvector starting at the beginning or halfway
7414 // point of the vector? A low half may also come through as an
7415 // EXTRACT_SUBREG, so look for that, too.
7416 SDValue Op0 = N->getOperand(0);
7417 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7418 !(Op0->isMachineOpcode() &&
7419 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7421 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7422 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7423 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7425 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7426 if (idx != AArch64::dsub)
7428 // The dsub reference is equivalent to a lane zero subvector reference.
7431 // Look through the bitcast of the input to the extract.
7432 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7434 SDValue Source = Op0->getOperand(0)->getOperand(0);
7435 // If the source type has twice the number of elements as our destination
7436 // type, we know this is an extract of the high or low half of the vector.
7437 EVT SVT = Source->getValueType(0);
7438 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7441 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7443 // Create the simplified form to just extract the low or high half of the
7444 // vector directly rather than bothering with the bitcasts.
7446 unsigned NumElements = VT.getVectorNumElements();
7448 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7449 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7451 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7452 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7458 static SDValue performConcatVectorsCombine(SDNode *N,
7459 TargetLowering::DAGCombinerInfo &DCI,
7460 SelectionDAG &DAG) {
7462 EVT VT = N->getValueType(0);
7463 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7465 // Optimize concat_vectors of truncated vectors, where the intermediate
7466 // type is illegal, to avoid said illegality, e.g.,
7467 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7468 // (v2i16 (truncate (v2i64)))))
7470 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7471 // (v4i32 (bitcast (v2i64))),
7473 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7474 // on both input and result type, so we might generate worse code.
7475 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7476 if (N->getNumOperands() == 2 &&
7477 N0->getOpcode() == ISD::TRUNCATE &&
7478 N1->getOpcode() == ISD::TRUNCATE) {
7479 SDValue N00 = N0->getOperand(0);
7480 SDValue N10 = N1->getOperand(0);
7481 EVT N00VT = N00.getValueType();
7483 if (N00VT == N10.getValueType() &&
7484 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7485 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7486 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7487 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7488 for (size_t i = 0; i < Mask.size(); ++i)
7490 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7491 DAG.getVectorShuffle(
7493 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7494 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7498 // Wait 'til after everything is legalized to try this. That way we have
7499 // legal vector types and such.
7500 if (DCI.isBeforeLegalizeOps())
7503 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7504 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7505 // canonicalise to that.
7506 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7507 assert(VT.getVectorElementType().getSizeInBits() == 64);
7508 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7509 DAG.getConstant(0, dl, MVT::i64));
7512 // Canonicalise concat_vectors so that the right-hand vector has as few
7513 // bit-casts as possible before its real operation. The primary matching
7514 // destination for these operations will be the narrowing "2" instructions,
7515 // which depend on the operation being performed on this right-hand vector.
7517 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7519 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7521 if (N1->getOpcode() != ISD::BITCAST)
7523 SDValue RHS = N1->getOperand(0);
7524 MVT RHSTy = RHS.getValueType().getSimpleVT();
7525 // If the RHS is not a vector, this is not the pattern we're looking for.
7526 if (!RHSTy.isVector())
7529 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7531 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7532 RHSTy.getVectorNumElements() * 2);
7533 return DAG.getNode(ISD::BITCAST, dl, VT,
7534 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7535 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7539 static SDValue tryCombineFixedPointConvert(SDNode *N,
7540 TargetLowering::DAGCombinerInfo &DCI,
7541 SelectionDAG &DAG) {
7542 // Wait 'til after everything is legalized to try this. That way we have
7543 // legal vector types and such.
7544 if (DCI.isBeforeLegalizeOps())
7546 // Transform a scalar conversion of a value from a lane extract into a
7547 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7548 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7549 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7551 // The second form interacts better with instruction selection and the
7552 // register allocator to avoid cross-class register copies that aren't
7553 // coalescable due to a lane reference.
7555 // Check the operand and see if it originates from a lane extract.
7556 SDValue Op1 = N->getOperand(1);
7557 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7558 // Yep, no additional predication needed. Perform the transform.
7559 SDValue IID = N->getOperand(0);
7560 SDValue Shift = N->getOperand(2);
7561 SDValue Vec = Op1.getOperand(0);
7562 SDValue Lane = Op1.getOperand(1);
7563 EVT ResTy = N->getValueType(0);
7567 // The vector width should be 128 bits by the time we get here, even
7568 // if it started as 64 bits (the extract_vector handling will have
7570 assert(Vec.getValueType().getSizeInBits() == 128 &&
7571 "unexpected vector size on extract_vector_elt!");
7572 if (Vec.getValueType() == MVT::v4i32)
7573 VecResTy = MVT::v4f32;
7574 else if (Vec.getValueType() == MVT::v2i64)
7575 VecResTy = MVT::v2f64;
7577 llvm_unreachable("unexpected vector type!");
7580 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7581 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7586 // AArch64 high-vector "long" operations are formed by performing the non-high
7587 // version on an extract_subvector of each operand which gets the high half:
7589 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7591 // However, there are cases which don't have an extract_high explicitly, but
7592 // have another operation that can be made compatible with one for free. For
7595 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7597 // This routine does the actual conversion of such DUPs, once outer routines
7598 // have determined that everything else is in order.
7599 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7601 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7602 switch (N.getOpcode()) {
7603 case AArch64ISD::DUP:
7604 case AArch64ISD::DUPLANE8:
7605 case AArch64ISD::DUPLANE16:
7606 case AArch64ISD::DUPLANE32:
7607 case AArch64ISD::DUPLANE64:
7608 case AArch64ISD::MOVI:
7609 case AArch64ISD::MOVIshift:
7610 case AArch64ISD::MOVIedit:
7611 case AArch64ISD::MOVImsl:
7612 case AArch64ISD::MVNIshift:
7613 case AArch64ISD::MVNImsl:
7616 // FMOV could be supported, but isn't very useful, as it would only occur
7617 // if you passed a bitcast' floating point immediate to an eligible long
7618 // integer op (addl, smull, ...).
7622 MVT NarrowTy = N.getSimpleValueType();
7623 if (!NarrowTy.is64BitVector())
7626 MVT ElementTy = NarrowTy.getVectorElementType();
7627 unsigned NumElems = NarrowTy.getVectorNumElements();
7628 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7631 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7632 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7633 DAG.getConstant(NumElems, dl, MVT::i64));
7636 static bool isEssentiallyExtractSubvector(SDValue N) {
7637 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7640 return N.getOpcode() == ISD::BITCAST &&
7641 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7644 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7645 struct GenericSetCCInfo {
7646 const SDValue *Opnd0;
7647 const SDValue *Opnd1;
7651 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7652 struct AArch64SetCCInfo {
7654 AArch64CC::CondCode CC;
7657 /// \brief Helper structure to keep track of SetCC information.
7659 GenericSetCCInfo Generic;
7660 AArch64SetCCInfo AArch64;
7663 /// \brief Helper structure to be able to read SetCC information. If set to
7664 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7665 /// GenericSetCCInfo.
7666 struct SetCCInfoAndKind {
7671 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7673 /// AArch64 lowered one.
7674 /// \p SetCCInfo is filled accordingly.
7675 /// \post SetCCInfo is meanginfull only when this function returns true.
7676 /// \return True when Op is a kind of SET_CC operation.
7677 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7678 // If this is a setcc, this is straight forward.
7679 if (Op.getOpcode() == ISD::SETCC) {
7680 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7681 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7682 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7683 SetCCInfo.IsAArch64 = false;
7686 // Otherwise, check if this is a matching csel instruction.
7690 if (Op.getOpcode() != AArch64ISD::CSEL)
7692 // Set the information about the operands.
7693 // TODO: we want the operands of the Cmp not the csel
7694 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7695 SetCCInfo.IsAArch64 = true;
7696 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7697 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7699 // Check that the operands matches the constraints:
7700 // (1) Both operands must be constants.
7701 // (2) One must be 1 and the other must be 0.
7702 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7703 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7706 if (!TValue || !FValue)
7710 if (!TValue->isOne()) {
7711 // Update the comparison when we are interested in !cc.
7712 std::swap(TValue, FValue);
7713 SetCCInfo.Info.AArch64.CC =
7714 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7716 return TValue->isOne() && FValue->isNullValue();
7719 // Returns true if Op is setcc or zext of setcc.
7720 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7721 if (isSetCC(Op, Info))
7723 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7724 isSetCC(Op->getOperand(0), Info));
7727 // The folding we want to perform is:
7728 // (add x, [zext] (setcc cc ...) )
7730 // (csel x, (add x, 1), !cc ...)
7732 // The latter will get matched to a CSINC instruction.
7733 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7734 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7735 SDValue LHS = Op->getOperand(0);
7736 SDValue RHS = Op->getOperand(1);
7737 SetCCInfoAndKind InfoAndKind;
7739 // If neither operand is a SET_CC, give up.
7740 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7741 std::swap(LHS, RHS);
7742 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7746 // FIXME: This could be generatized to work for FP comparisons.
7747 EVT CmpVT = InfoAndKind.IsAArch64
7748 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7749 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7750 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7756 if (InfoAndKind.IsAArch64) {
7757 CCVal = DAG.getConstant(
7758 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
7760 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7762 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7763 *InfoAndKind.Info.Generic.Opnd1,
7764 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7767 EVT VT = Op->getValueType(0);
7768 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
7769 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7772 // The basic add/sub long vector instructions have variants with "2" on the end
7773 // which act on the high-half of their inputs. They are normally matched by
7776 // (add (zeroext (extract_high LHS)),
7777 // (zeroext (extract_high RHS)))
7778 // -> uaddl2 vD, vN, vM
7780 // However, if one of the extracts is something like a duplicate, this
7781 // instruction can still be used profitably. This function puts the DAG into a
7782 // more appropriate form for those patterns to trigger.
7783 static SDValue performAddSubLongCombine(SDNode *N,
7784 TargetLowering::DAGCombinerInfo &DCI,
7785 SelectionDAG &DAG) {
7786 if (DCI.isBeforeLegalizeOps())
7789 MVT VT = N->getSimpleValueType(0);
7790 if (!VT.is128BitVector()) {
7791 if (N->getOpcode() == ISD::ADD)
7792 return performSetccAddFolding(N, DAG);
7796 // Make sure both branches are extended in the same way.
7797 SDValue LHS = N->getOperand(0);
7798 SDValue RHS = N->getOperand(1);
7799 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7800 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7801 LHS.getOpcode() != RHS.getOpcode())
7804 unsigned ExtType = LHS.getOpcode();
7806 // It's not worth doing if at least one of the inputs isn't already an
7807 // extract, but we don't know which it'll be so we have to try both.
7808 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7809 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7813 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7814 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7815 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7819 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7822 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7825 // Massage DAGs which we can use the high-half "long" operations on into
7826 // something isel will recognize better. E.g.
7828 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7829 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7830 // (extract_high (v2i64 (dup128 scalar)))))
7832 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7833 TargetLowering::DAGCombinerInfo &DCI,
7834 SelectionDAG &DAG) {
7835 if (DCI.isBeforeLegalizeOps())
7838 SDValue LHS = N->getOperand(1);
7839 SDValue RHS = N->getOperand(2);
7840 assert(LHS.getValueType().is64BitVector() &&
7841 RHS.getValueType().is64BitVector() &&
7842 "unexpected shape for long operation");
7844 // Either node could be a DUP, but it's not worth doing both of them (you'd
7845 // just as well use the non-high version) so look for a corresponding extract
7846 // operation on the other "wing".
7847 if (isEssentiallyExtractSubvector(LHS)) {
7848 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7851 } else if (isEssentiallyExtractSubvector(RHS)) {
7852 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7857 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7858 N->getOperand(0), LHS, RHS);
7861 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7862 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7863 unsigned ElemBits = ElemTy.getSizeInBits();
7865 int64_t ShiftAmount;
7866 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7867 APInt SplatValue, SplatUndef;
7868 unsigned SplatBitSize;
7870 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7871 HasAnyUndefs, ElemBits) ||
7872 SplatBitSize != ElemBits)
7875 ShiftAmount = SplatValue.getSExtValue();
7876 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7877 ShiftAmount = CVN->getSExtValue();
7885 llvm_unreachable("Unknown shift intrinsic");
7886 case Intrinsic::aarch64_neon_sqshl:
7887 Opcode = AArch64ISD::SQSHL_I;
7888 IsRightShift = false;
7890 case Intrinsic::aarch64_neon_uqshl:
7891 Opcode = AArch64ISD::UQSHL_I;
7892 IsRightShift = false;
7894 case Intrinsic::aarch64_neon_srshl:
7895 Opcode = AArch64ISD::SRSHR_I;
7896 IsRightShift = true;
7898 case Intrinsic::aarch64_neon_urshl:
7899 Opcode = AArch64ISD::URSHR_I;
7900 IsRightShift = true;
7902 case Intrinsic::aarch64_neon_sqshlu:
7903 Opcode = AArch64ISD::SQSHLU_I;
7904 IsRightShift = false;
7908 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
7910 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7911 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
7912 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
7914 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7915 DAG.getConstant(ShiftAmount, dl, MVT::i32));
7921 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7922 // the intrinsics must be legal and take an i32, this means there's almost
7923 // certainly going to be a zext in the DAG which we can eliminate.
7924 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7925 SDValue AndN = N->getOperand(2);
7926 if (AndN.getOpcode() != ISD::AND)
7929 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7930 if (!CMask || CMask->getZExtValue() != Mask)
7933 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7934 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7937 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7938 SelectionDAG &DAG) {
7940 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
7941 DAG.getNode(Opc, dl,
7942 N->getOperand(1).getSimpleValueType(),
7944 DAG.getConstant(0, dl, MVT::i64));
7947 static SDValue performIntrinsicCombine(SDNode *N,
7948 TargetLowering::DAGCombinerInfo &DCI,
7949 const AArch64Subtarget *Subtarget) {
7950 SelectionDAG &DAG = DCI.DAG;
7951 unsigned IID = getIntrinsicID(N);
7955 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7956 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7957 return tryCombineFixedPointConvert(N, DCI, DAG);
7959 case Intrinsic::aarch64_neon_saddv:
7960 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7961 case Intrinsic::aarch64_neon_uaddv:
7962 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7963 case Intrinsic::aarch64_neon_sminv:
7964 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7965 case Intrinsic::aarch64_neon_uminv:
7966 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7967 case Intrinsic::aarch64_neon_smaxv:
7968 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7969 case Intrinsic::aarch64_neon_umaxv:
7970 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7971 case Intrinsic::aarch64_neon_fmax:
7972 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7973 N->getOperand(1), N->getOperand(2));
7974 case Intrinsic::aarch64_neon_fmin:
7975 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7976 N->getOperand(1), N->getOperand(2));
7977 case Intrinsic::aarch64_neon_smull:
7978 case Intrinsic::aarch64_neon_umull:
7979 case Intrinsic::aarch64_neon_pmull:
7980 case Intrinsic::aarch64_neon_sqdmull:
7981 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7982 case Intrinsic::aarch64_neon_sqshl:
7983 case Intrinsic::aarch64_neon_uqshl:
7984 case Intrinsic::aarch64_neon_sqshlu:
7985 case Intrinsic::aarch64_neon_srshl:
7986 case Intrinsic::aarch64_neon_urshl:
7987 return tryCombineShiftImm(IID, N, DAG);
7988 case Intrinsic::aarch64_crc32b:
7989 case Intrinsic::aarch64_crc32cb:
7990 return tryCombineCRC32(0xff, N, DAG);
7991 case Intrinsic::aarch64_crc32h:
7992 case Intrinsic::aarch64_crc32ch:
7993 return tryCombineCRC32(0xffff, N, DAG);
7998 static SDValue performExtendCombine(SDNode *N,
7999 TargetLowering::DAGCombinerInfo &DCI,
8000 SelectionDAG &DAG) {
8001 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8002 // we can convert that DUP into another extract_high (of a bigger DUP), which
8003 // helps the backend to decide that an sabdl2 would be useful, saving a real
8004 // extract_high operation.
8005 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8006 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
8007 SDNode *ABDNode = N->getOperand(0).getNode();
8008 unsigned IID = getIntrinsicID(ABDNode);
8009 if (IID == Intrinsic::aarch64_neon_sabd ||
8010 IID == Intrinsic::aarch64_neon_uabd) {
8011 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
8012 if (!NewABD.getNode())
8015 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8020 // This is effectively a custom type legalization for AArch64.
8022 // Type legalization will split an extend of a small, legal, type to a larger
8023 // illegal type by first splitting the destination type, often creating
8024 // illegal source types, which then get legalized in isel-confusing ways,
8025 // leading to really terrible codegen. E.g.,
8026 // %result = v8i32 sext v8i8 %value
8028 // %losrc = extract_subreg %value, ...
8029 // %hisrc = extract_subreg %value, ...
8030 // %lo = v4i32 sext v4i8 %losrc
8031 // %hi = v4i32 sext v4i8 %hisrc
8032 // Things go rapidly downhill from there.
8034 // For AArch64, the [sz]ext vector instructions can only go up one element
8035 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8036 // take two instructions.
8038 // This implies that the most efficient way to do the extend from v8i8
8039 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8040 // the normal splitting to happen for the v8i16->v8i32.
8042 // This is pre-legalization to catch some cases where the default
8043 // type legalization will create ill-tempered code.
8044 if (!DCI.isBeforeLegalizeOps())
8047 // We're only interested in cleaning things up for non-legal vector types
8048 // here. If both the source and destination are legal, things will just
8049 // work naturally without any fiddling.
8050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8051 EVT ResVT = N->getValueType(0);
8052 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8054 // If the vector type isn't a simple VT, it's beyond the scope of what
8055 // we're worried about here. Let legalization do its thing and hope for
8057 SDValue Src = N->getOperand(0);
8058 EVT SrcVT = Src->getValueType(0);
8059 if (!ResVT.isSimple() || !SrcVT.isSimple())
8062 // If the source VT is a 64-bit vector, we can play games and get the
8063 // better results we want.
8064 if (SrcVT.getSizeInBits() != 64)
8067 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8068 unsigned ElementCount = SrcVT.getVectorNumElements();
8069 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8071 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8073 // Now split the rest of the operation into two halves, each with a 64
8077 unsigned NumElements = ResVT.getVectorNumElements();
8078 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8079 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8080 ResVT.getVectorElementType(), NumElements / 2);
8082 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8083 LoVT.getVectorNumElements());
8084 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8085 DAG.getConstant(0, DL, MVT::i64));
8086 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8087 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8088 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8089 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8091 // Now combine the parts back together so we still have a single result
8092 // like the combiner expects.
8093 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8096 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8097 /// value. The load store optimizer pass will merge them to store pair stores.
8098 /// This has better performance than a splat of the scalar followed by a split
8099 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8100 /// followed by an ext.b and two stores.
8101 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8102 SDValue StVal = St->getValue();
8103 EVT VT = StVal.getValueType();
8105 // Don't replace floating point stores, they possibly won't be transformed to
8106 // stp because of the store pair suppress pass.
8107 if (VT.isFloatingPoint())
8110 // Check for insert vector elements.
8111 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8114 // We can express a splat as store pair(s) for 2 or 4 elements.
8115 unsigned NumVecElts = VT.getVectorNumElements();
8116 if (NumVecElts != 4 && NumVecElts != 2)
8118 SDValue SplatVal = StVal.getOperand(1);
8119 unsigned RemainInsertElts = NumVecElts - 1;
8121 // Check that this is a splat.
8122 while (--RemainInsertElts) {
8123 SDValue NextInsertElt = StVal.getOperand(0);
8124 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8126 if (NextInsertElt.getOperand(1) != SplatVal)
8128 StVal = NextInsertElt;
8130 unsigned OrigAlignment = St->getAlignment();
8131 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8132 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8134 // Create scalar stores. This is at least as good as the code sequence for a
8135 // split unaligned store wich is a dup.s, ext.b, and two stores.
8136 // Most of the time the three stores should be replaced by store pair
8137 // instructions (stp).
8139 SDValue BasePtr = St->getBasePtr();
8141 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8142 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8144 unsigned Offset = EltOffset;
8145 while (--NumVecElts) {
8146 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8147 DAG.getConstant(Offset, DL, MVT::i64));
8148 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8149 St->getPointerInfo(), St->isVolatile(),
8150 St->isNonTemporal(), Alignment);
8151 Offset += EltOffset;
8156 static SDValue performSTORECombine(SDNode *N,
8157 TargetLowering::DAGCombinerInfo &DCI,
8159 const AArch64Subtarget *Subtarget) {
8160 if (!DCI.isBeforeLegalize())
8163 StoreSDNode *S = cast<StoreSDNode>(N);
8164 if (S->isVolatile())
8167 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8168 // page boundaries. We want to split such stores.
8169 if (!Subtarget->isCyclone())
8172 // Don't split at Oz.
8173 MachineFunction &MF = DAG.getMachineFunction();
8174 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8178 SDValue StVal = S->getValue();
8179 EVT VT = StVal.getValueType();
8181 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8182 // those up regresses performance on micro-benchmarks and olden/bh.
8183 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8186 // Split unaligned 16B stores. They are terrible for performance.
8187 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8188 // extensions can use this to mark that it does not want splitting to happen
8189 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8190 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8191 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8192 S->getAlignment() <= 2)
8195 // If we get a splat of a scalar convert this vector store to a store of
8196 // scalars. They will be merged into store pairs thereby removing two
8198 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8199 if (ReplacedSplat != SDValue())
8200 return ReplacedSplat;
8203 unsigned NumElts = VT.getVectorNumElements() / 2;
8204 // Split VT into two.
8206 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8207 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8208 DAG.getConstant(0, DL, MVT::i64));
8209 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8210 DAG.getConstant(NumElts, DL, MVT::i64));
8211 SDValue BasePtr = S->getBasePtr();
8213 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8214 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8215 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8216 DAG.getConstant(8, DL, MVT::i64));
8217 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8218 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8222 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8223 /// post-increment LD1R.
8224 static SDValue performPostLD1Combine(SDNode *N,
8225 TargetLowering::DAGCombinerInfo &DCI,
8227 if (DCI.isBeforeLegalizeOps())
8230 SelectionDAG &DAG = DCI.DAG;
8231 EVT VT = N->getValueType(0);
8233 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8234 SDNode *LD = N->getOperand(LoadIdx).getNode();
8235 // If it is not LOAD, can not do such combine.
8236 if (LD->getOpcode() != ISD::LOAD)
8239 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8240 EVT MemVT = LoadSDN->getMemoryVT();
8241 // Check if memory operand is the same type as the vector element.
8242 if (MemVT != VT.getVectorElementType())
8245 // Check if there are other uses. If so, do not combine as it will introduce
8247 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8249 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8255 SDValue Addr = LD->getOperand(1);
8256 SDValue Vector = N->getOperand(0);
8257 // Search for a use of the address operand that is an increment.
8258 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8259 Addr.getNode()->use_end(); UI != UE; ++UI) {
8261 if (User->getOpcode() != ISD::ADD
8262 || UI.getUse().getResNo() != Addr.getResNo())
8265 // Check that the add is independent of the load. Otherwise, folding it
8266 // would create a cycle.
8267 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8269 // Also check that add is not used in the vector operand. This would also
8271 if (User->isPredecessorOf(Vector.getNode()))
8274 // If the increment is a constant, it must match the memory ref size.
8275 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8276 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8277 uint32_t IncVal = CInc->getZExtValue();
8278 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8279 if (IncVal != NumBytes)
8281 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8284 // Finally, check that the vector doesn't depend on the load.
8285 // Again, this would create a cycle.
8286 // The load depending on the vector is fine, as that's the case for the
8287 // LD1*post we'll eventually generate anyway.
8288 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8291 SmallVector<SDValue, 8> Ops;
8292 Ops.push_back(LD->getOperand(0)); // Chain
8294 Ops.push_back(Vector); // The vector to be inserted
8295 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8297 Ops.push_back(Addr);
8300 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8301 SDVTList SDTys = DAG.getVTList(Tys);
8302 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8303 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8305 LoadSDN->getMemOperand());
8308 SmallVector<SDValue, 2> NewResults;
8309 NewResults.push_back(SDValue(LD, 0)); // The result of load
8310 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8311 DCI.CombineTo(LD, NewResults);
8312 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8313 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8320 /// Target-specific DAG combine function for NEON load/store intrinsics
8321 /// to merge base address updates.
8322 static SDValue performNEONPostLDSTCombine(SDNode *N,
8323 TargetLowering::DAGCombinerInfo &DCI,
8324 SelectionDAG &DAG) {
8325 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8328 unsigned AddrOpIdx = N->getNumOperands() - 1;
8329 SDValue Addr = N->getOperand(AddrOpIdx);
8331 // Search for a use of the address operand that is an increment.
8332 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8333 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8335 if (User->getOpcode() != ISD::ADD ||
8336 UI.getUse().getResNo() != Addr.getResNo())
8339 // Check that the add is independent of the load/store. Otherwise, folding
8340 // it would create a cycle.
8341 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8344 // Find the new opcode for the updating load/store.
8345 bool IsStore = false;
8346 bool IsLaneOp = false;
8347 bool IsDupOp = false;
8348 unsigned NewOpc = 0;
8349 unsigned NumVecs = 0;
8350 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8352 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8353 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8355 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8357 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8359 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8360 NumVecs = 2; IsStore = true; break;
8361 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8362 NumVecs = 3; IsStore = true; break;
8363 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8364 NumVecs = 4; IsStore = true; break;
8365 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8367 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8369 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8371 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8372 NumVecs = 2; IsStore = true; break;
8373 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8374 NumVecs = 3; IsStore = true; break;
8375 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8376 NumVecs = 4; IsStore = true; break;
8377 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8378 NumVecs = 2; IsDupOp = true; break;
8379 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8380 NumVecs = 3; IsDupOp = true; break;
8381 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8382 NumVecs = 4; IsDupOp = true; break;
8383 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8384 NumVecs = 2; IsLaneOp = true; break;
8385 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8386 NumVecs = 3; IsLaneOp = true; break;
8387 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8388 NumVecs = 4; IsLaneOp = true; break;
8389 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8390 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8391 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8392 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8393 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8394 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8399 VecTy = N->getOperand(2).getValueType();
8401 VecTy = N->getValueType(0);
8403 // If the increment is a constant, it must match the memory ref size.
8404 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8405 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8406 uint32_t IncVal = CInc->getZExtValue();
8407 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8408 if (IsLaneOp || IsDupOp)
8409 NumBytes /= VecTy.getVectorNumElements();
8410 if (IncVal != NumBytes)
8412 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8414 SmallVector<SDValue, 8> Ops;
8415 Ops.push_back(N->getOperand(0)); // Incoming chain
8416 // Load lane and store have vector list as input.
8417 if (IsLaneOp || IsStore)
8418 for (unsigned i = 2; i < AddrOpIdx; ++i)
8419 Ops.push_back(N->getOperand(i));
8420 Ops.push_back(Addr); // Base register
8425 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8427 for (n = 0; n < NumResultVecs; ++n)
8429 Tys[n++] = MVT::i64; // Type of write back register
8430 Tys[n] = MVT::Other; // Type of the chain
8431 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8433 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8434 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8435 MemInt->getMemoryVT(),
8436 MemInt->getMemOperand());
8439 std::vector<SDValue> NewResults;
8440 for (unsigned i = 0; i < NumResultVecs; ++i) {
8441 NewResults.push_back(SDValue(UpdN.getNode(), i));
8443 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8444 DCI.CombineTo(N, NewResults);
8445 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8452 // Checks to see if the value is the prescribed width and returns information
8453 // about its extension mode.
8455 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8456 ExtType = ISD::NON_EXTLOAD;
8457 switch(V.getNode()->getOpcode()) {
8461 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8462 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8463 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8464 ExtType = LoadNode->getExtensionType();
8469 case ISD::AssertSext: {
8470 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8471 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8472 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8473 ExtType = ISD::SEXTLOAD;
8478 case ISD::AssertZext: {
8479 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8480 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8481 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8482 ExtType = ISD::ZEXTLOAD;
8488 case ISD::TargetConstant: {
8489 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8499 // This function does a whole lot of voodoo to determine if the tests are
8500 // equivalent without and with a mask. Essentially what happens is that given a
8503 // +-------------+ +-------------+ +-------------+ +-------------+
8504 // | Input | | AddConstant | | CompConstant| | CC |
8505 // +-------------+ +-------------+ +-------------+ +-------------+
8507 // V V | +----------+
8508 // +-------------+ +----+ | |
8509 // | ADD | |0xff| | |
8510 // +-------------+ +----+ | |
8513 // +-------------+ | |
8515 // +-------------+ | |
8524 // The AND node may be safely removed for some combinations of inputs. In
8525 // particular we need to take into account the extension type of the Input,
8526 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8527 // width of the input (this can work for any width inputs, the above graph is
8528 // specific to 8 bits.
8530 // The specific equations were worked out by generating output tables for each
8531 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8532 // problem was simplified by working with 4 bit inputs, which means we only
8533 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8534 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8535 // patterns present in both extensions (0,7). For every distinct set of
8536 // AddConstant and CompConstants bit patterns we can consider the masked and
8537 // unmasked versions to be equivalent if the result of this function is true for
8538 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8541 // and w10, w8, #0x0f
8543 // cset w9, AArch64CC
8545 // cset w11, AArch64CC
8550 // Since the above function shows when the outputs are equivalent it defines
8551 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8552 // would be expensive to run during compiles. The equations below were written
8553 // in a test harness that confirmed they gave equivalent outputs to the above
8554 // for all inputs function, so they can be used determine if the removal is
8557 // isEquivalentMaskless() is the code for testing if the AND can be removed
8558 // factored out of the DAG recognition as the DAG can take several forms.
8561 bool isEquivalentMaskless(unsigned CC, unsigned width,
8562 ISD::LoadExtType ExtType, signed AddConstant,
8563 signed CompConstant) {
8564 // By being careful about our equations and only writing the in term
8565 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8566 // make them generally applicable to all bit widths.
8567 signed MaxUInt = (1 << width);
8569 // For the purposes of these comparisons sign extending the type is
8570 // equivalent to zero extending the add and displacing it by half the integer
8571 // width. Provided we are careful and make sure our equations are valid over
8572 // the whole range we can just adjust the input and avoid writing equations
8573 // for sign extended inputs.
8574 if (ExtType == ISD::SEXTLOAD)
8575 AddConstant -= (1 << (width-1));
8579 case AArch64CC::GT: {
8580 if ((AddConstant == 0) ||
8581 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8582 (AddConstant >= 0 && CompConstant < 0) ||
8583 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8587 case AArch64CC::GE: {
8588 if ((AddConstant == 0) ||
8589 (AddConstant >= 0 && CompConstant <= 0) ||
8590 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8594 case AArch64CC::LS: {
8595 if ((AddConstant >= 0 && CompConstant < 0) ||
8596 (AddConstant <= 0 && CompConstant >= -1 &&
8597 CompConstant < AddConstant + MaxUInt))
8601 case AArch64CC::MI: {
8602 if ((AddConstant == 0) ||
8603 (AddConstant > 0 && CompConstant <= 0) ||
8604 (AddConstant < 0 && CompConstant <= AddConstant))
8608 case AArch64CC::HS: {
8609 if ((AddConstant >= 0 && CompConstant <= 0) ||
8610 (AddConstant <= 0 && CompConstant >= 0 &&
8611 CompConstant <= AddConstant + MaxUInt))
8615 case AArch64CC::NE: {
8616 if ((AddConstant > 0 && CompConstant < 0) ||
8617 (AddConstant < 0 && CompConstant >= 0 &&
8618 CompConstant < AddConstant + MaxUInt) ||
8619 (AddConstant >= 0 && CompConstant >= 0 &&
8620 CompConstant >= AddConstant) ||
8621 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8630 case AArch64CC::Invalid:
8638 SDValue performCONDCombine(SDNode *N,
8639 TargetLowering::DAGCombinerInfo &DCI,
8640 SelectionDAG &DAG, unsigned CCIndex,
8641 unsigned CmpIndex) {
8642 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8643 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8644 unsigned CondOpcode = SubsNode->getOpcode();
8646 if (CondOpcode != AArch64ISD::SUBS)
8649 // There is a SUBS feeding this condition. Is it fed by a mask we can
8652 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8653 unsigned MaskBits = 0;
8655 if (AndNode->getOpcode() != ISD::AND)
8658 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8659 uint32_t CNV = CN->getZExtValue();
8662 else if (CNV == 65535)
8669 SDValue AddValue = AndNode->getOperand(0);
8671 if (AddValue.getOpcode() != ISD::ADD)
8674 // The basic dag structure is correct, grab the inputs and validate them.
8676 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8677 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8678 SDValue SubsInputValue = SubsNode->getOperand(1);
8680 // The mask is present and the provenance of all the values is a smaller type,
8681 // lets see if the mask is superfluous.
8683 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8684 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8687 ISD::LoadExtType ExtType;
8689 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8690 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8691 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8694 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8695 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8696 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8699 // The AND is not necessary, remove it.
8701 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8702 SubsNode->getValueType(1));
8703 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8705 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8706 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8708 return SDValue(N, 0);
8711 // Optimize compare with zero and branch.
8712 static SDValue performBRCONDCombine(SDNode *N,
8713 TargetLowering::DAGCombinerInfo &DCI,
8714 SelectionDAG &DAG) {
8715 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8718 SDValue Chain = N->getOperand(0);
8719 SDValue Dest = N->getOperand(1);
8720 SDValue CCVal = N->getOperand(2);
8721 SDValue Cmp = N->getOperand(3);
8723 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8724 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8725 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8728 unsigned CmpOpc = Cmp.getOpcode();
8729 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8732 // Only attempt folding if there is only one use of the flag and no use of the
8734 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8737 SDValue LHS = Cmp.getOperand(0);
8738 SDValue RHS = Cmp.getOperand(1);
8740 assert(LHS.getValueType() == RHS.getValueType() &&
8741 "Expected the value type to be the same for both operands!");
8742 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8745 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8746 std::swap(LHS, RHS);
8748 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8751 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8752 LHS.getOpcode() == ISD::SRL)
8755 // Fold the compare into the branch instruction.
8757 if (CC == AArch64CC::EQ)
8758 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8760 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8762 // Do not add new nodes to DAG combiner worklist.
8763 DCI.CombineTo(N, BR, false);
8768 // vselect (v1i1 setcc) ->
8769 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8770 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8771 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8773 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8774 SDValue N0 = N->getOperand(0);
8775 EVT CCVT = N0.getValueType();
8777 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8778 CCVT.getVectorElementType() != MVT::i1)
8781 EVT ResVT = N->getValueType(0);
8782 EVT CmpVT = N0.getOperand(0).getValueType();
8783 // Only combine when the result type is of the same size as the compared
8785 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8788 SDValue IfTrue = N->getOperand(1);
8789 SDValue IfFalse = N->getOperand(2);
8791 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8792 N0.getOperand(0), N0.getOperand(1),
8793 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8794 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8798 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8799 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8800 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8801 /// with a vector one followed by a DUP shuffle on the result.
8802 static SDValue performSelectCombine(SDNode *N,
8803 TargetLowering::DAGCombinerInfo &DCI) {
8804 SelectionDAG &DAG = DCI.DAG;
8805 SDValue N0 = N->getOperand(0);
8806 EVT ResVT = N->getValueType(0);
8808 if (N0.getOpcode() != ISD::SETCC)
8811 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
8812 // scalar SetCCResultType. We also don't expect vectors, because we assume
8813 // that selects fed by vector SETCCs are canonicalized to VSELECT.
8814 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
8815 "Scalar-SETCC feeding SELECT has unexpected result type!");
8817 // If NumMaskElts == 0, the comparison is larger than select result. The
8818 // largest real NEON comparison is 64-bits per lane, which means the result is
8819 // at most 32-bits and an illegal vector. Just bail out for now.
8820 EVT SrcVT = N0.getOperand(0).getValueType();
8822 // Don't try to do this optimization when the setcc itself has i1 operands.
8823 // There are no legal vectors of i1, so this would be pointless.
8824 if (SrcVT == MVT::i1)
8827 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8828 if (!ResVT.isVector() || NumMaskElts == 0)
8831 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8832 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8834 // Also bail out if the vector CCVT isn't the same size as ResVT.
8835 // This can happen if the SETCC operand size doesn't divide the ResVT size
8836 // (e.g., f64 vs v3f32).
8837 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
8840 // Make sure we didn't create illegal types, if we're not supposed to.
8841 assert(DCI.isBeforeLegalize() ||
8842 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
8844 // First perform a vector comparison, where lane 0 is the one we're interested
8848 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8850 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8851 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8853 // Now duplicate the comparison mask we want across all other lanes.
8854 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8855 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8856 Mask = DAG.getNode(ISD::BITCAST, DL,
8857 ResVT.changeVectorElementTypeToInteger(), Mask);
8859 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8862 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
8863 /// to match FMIN/FMAX patterns.
8864 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
8865 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
8866 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
8867 // vmax/vmin return NaN if either operand is a NaN;
8868 // only do the transformation when it matches that behavior.
8870 SDValue CondLHS = N->getOperand(0);
8871 SDValue CondRHS = N->getOperand(1);
8872 SDValue LHS = N->getOperand(2);
8873 SDValue RHS = N->getOperand(3);
8874 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
8878 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
8879 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
8880 IsReversed = false; // x CC y ? x : y
8881 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
8882 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
8883 IsReversed = true ; // x CC y ? y : x
8888 bool IsUnordered = false, IsOrEqual;
8899 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
8900 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
8910 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
8911 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
8915 // If LHS is NaN, an ordered comparison will be false and the result will be
8916 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
8917 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
8918 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8921 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
8922 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
8923 // used for unsafe math or if one of the operands is known to be nonzero.
8924 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
8925 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8928 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
8931 /// Get rid of unnecessary NVCASTs (that don't change the type).
8932 static SDValue performNVCASTCombine(SDNode *N) {
8933 if (N->getValueType(0) == N->getOperand(0).getValueType())
8934 return N->getOperand(0);
8939 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8940 DAGCombinerInfo &DCI) const {
8941 SelectionDAG &DAG = DCI.DAG;
8942 switch (N->getOpcode()) {
8947 return performAddSubLongCombine(N, DCI, DAG);
8949 return performXorCombine(N, DAG, DCI, Subtarget);
8951 return performMulCombine(N, DAG, DCI, Subtarget);
8952 case ISD::SINT_TO_FP:
8953 case ISD::UINT_TO_FP:
8954 return performIntToFpCombine(N, DAG, Subtarget);
8956 return performORCombine(N, DCI, Subtarget);
8957 case ISD::INTRINSIC_WO_CHAIN:
8958 return performIntrinsicCombine(N, DCI, Subtarget);
8959 case ISD::ANY_EXTEND:
8960 case ISD::ZERO_EXTEND:
8961 case ISD::SIGN_EXTEND:
8962 return performExtendCombine(N, DCI, DAG);
8964 return performBitcastCombine(N, DCI, DAG);
8965 case ISD::CONCAT_VECTORS:
8966 return performConcatVectorsCombine(N, DCI, DAG);
8968 return performSelectCombine(N, DCI);
8970 return performVSelectCombine(N, DCI.DAG);
8971 case ISD::SELECT_CC:
8972 return performSelectCCCombine(N, DCI.DAG);
8974 return performSTORECombine(N, DCI, DAG, Subtarget);
8975 case AArch64ISD::BRCOND:
8976 return performBRCONDCombine(N, DCI, DAG);
8977 case AArch64ISD::CSEL:
8978 return performCONDCombine(N, DCI, DAG, 2, 3);
8979 case AArch64ISD::DUP:
8980 return performPostLD1Combine(N, DCI, false);
8981 case AArch64ISD::NVCAST:
8982 return performNVCASTCombine(N);
8983 case ISD::INSERT_VECTOR_ELT:
8984 return performPostLD1Combine(N, DCI, true);
8985 case ISD::INTRINSIC_VOID:
8986 case ISD::INTRINSIC_W_CHAIN:
8987 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8988 case Intrinsic::aarch64_neon_ld2:
8989 case Intrinsic::aarch64_neon_ld3:
8990 case Intrinsic::aarch64_neon_ld4:
8991 case Intrinsic::aarch64_neon_ld1x2:
8992 case Intrinsic::aarch64_neon_ld1x3:
8993 case Intrinsic::aarch64_neon_ld1x4:
8994 case Intrinsic::aarch64_neon_ld2lane:
8995 case Intrinsic::aarch64_neon_ld3lane:
8996 case Intrinsic::aarch64_neon_ld4lane:
8997 case Intrinsic::aarch64_neon_ld2r:
8998 case Intrinsic::aarch64_neon_ld3r:
8999 case Intrinsic::aarch64_neon_ld4r:
9000 case Intrinsic::aarch64_neon_st2:
9001 case Intrinsic::aarch64_neon_st3:
9002 case Intrinsic::aarch64_neon_st4:
9003 case Intrinsic::aarch64_neon_st1x2:
9004 case Intrinsic::aarch64_neon_st1x3:
9005 case Intrinsic::aarch64_neon_st1x4:
9006 case Intrinsic::aarch64_neon_st2lane:
9007 case Intrinsic::aarch64_neon_st3lane:
9008 case Intrinsic::aarch64_neon_st4lane:
9009 return performNEONPostLDSTCombine(N, DCI, DAG);
9017 // Check if the return value is used as only a return value, as otherwise
9018 // we can't perform a tail-call. In particular, we need to check for
9019 // target ISD nodes that are returns and any other "odd" constructs
9020 // that the generic analysis code won't necessarily catch.
9021 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9022 SDValue &Chain) const {
9023 if (N->getNumValues() != 1)
9025 if (!N->hasNUsesOfValue(1, 0))
9028 SDValue TCChain = Chain;
9029 SDNode *Copy = *N->use_begin();
9030 if (Copy->getOpcode() == ISD::CopyToReg) {
9031 // If the copy has a glue operand, we conservatively assume it isn't safe to
9032 // perform a tail call.
9033 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9036 TCChain = Copy->getOperand(0);
9037 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9040 bool HasRet = false;
9041 for (SDNode *Node : Copy->uses()) {
9042 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9054 // Return whether the an instruction can potentially be optimized to a tail
9055 // call. This will cause the optimizers to attempt to move, or duplicate,
9056 // return instructions to help enable tail call optimizations for this
9058 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9059 if (!CI->isTailCall())
9065 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9067 ISD::MemIndexedMode &AM,
9069 SelectionDAG &DAG) const {
9070 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9073 Base = Op->getOperand(0);
9074 // All of the indexed addressing mode instructions take a signed
9075 // 9 bit immediate offset.
9076 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9077 int64_t RHSC = (int64_t)RHS->getZExtValue();
9078 if (RHSC >= 256 || RHSC <= -256)
9080 IsInc = (Op->getOpcode() == ISD::ADD);
9081 Offset = Op->getOperand(1);
9087 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9089 ISD::MemIndexedMode &AM,
9090 SelectionDAG &DAG) const {
9093 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9094 VT = LD->getMemoryVT();
9095 Ptr = LD->getBasePtr();
9096 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9097 VT = ST->getMemoryVT();
9098 Ptr = ST->getBasePtr();
9103 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9105 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9109 bool AArch64TargetLowering::getPostIndexedAddressParts(
9110 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9111 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9114 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9115 VT = LD->getMemoryVT();
9116 Ptr = LD->getBasePtr();
9117 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9118 VT = ST->getMemoryVT();
9119 Ptr = ST->getBasePtr();
9124 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9126 // Post-indexing updates the base, so it's not a valid transform
9127 // if that's not the same as the load's pointer.
9130 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9134 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9135 SelectionDAG &DAG) {
9137 SDValue Op = N->getOperand(0);
9139 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9143 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9144 DAG.getUNDEF(MVT::i32), Op,
9145 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9147 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9148 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9151 void AArch64TargetLowering::ReplaceNodeResults(
9152 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9153 switch (N->getOpcode()) {
9155 llvm_unreachable("Don't know how to custom expand this");
9157 ReplaceBITCASTResults(N, Results, DAG);
9159 case ISD::FP_TO_UINT:
9160 case ISD::FP_TO_SINT:
9161 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9162 // Let normal code take care of it by not adding anything to Results.
9167 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9171 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9172 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9173 // reciprocal if there are three or more FDIVs.
9174 return NumUsers > 2;
9177 TargetLoweringBase::LegalizeTypeAction
9178 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9179 MVT SVT = VT.getSimpleVT();
9180 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9181 // v4i16, v2i32 instead of to promote.
9182 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9183 || SVT == MVT::v1f32)
9184 return TypeWidenVector;
9186 return TargetLoweringBase::getPreferredVectorAction(VT);
9189 // Loads and stores less than 128-bits are already atomic; ones above that
9190 // are doomed anyway, so defer to the default libcall and blame the OS when
9192 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9193 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9197 // Loads and stores less than 128-bits are already atomic; ones above that
9198 // are doomed anyway, so defer to the default libcall and blame the OS when
9200 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9201 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9205 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9206 TargetLoweringBase::AtomicRMWExpansionKind
9207 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9208 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9209 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9210 : AtomicRMWExpansionKind::None;
9213 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9217 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9218 AtomicOrdering Ord) const {
9219 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9220 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9221 bool IsAcquire = isAtLeastAcquire(Ord);
9223 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9224 // intrinsic must return {i64, i64} and we have to recombine them into a
9225 // single i128 here.
9226 if (ValTy->getPrimitiveSizeInBits() == 128) {
9228 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9229 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9231 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9232 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9234 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9235 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9236 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9237 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9238 return Builder.CreateOr(
9239 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9242 Type *Tys[] = { Addr->getType() };
9244 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9245 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9247 return Builder.CreateTruncOrBitCast(
9248 Builder.CreateCall(Ldxr, Addr),
9249 cast<PointerType>(Addr->getType())->getElementType());
9252 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9253 Value *Val, Value *Addr,
9254 AtomicOrdering Ord) const {
9255 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9256 bool IsRelease = isAtLeastRelease(Ord);
9258 // Since the intrinsics must have legal type, the i128 intrinsics take two
9259 // parameters: "i64, i64". We must marshal Val into the appropriate form
9261 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9263 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9264 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9265 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9267 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9268 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9269 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9270 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9274 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9275 Type *Tys[] = { Addr->getType() };
9276 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9278 return Builder.CreateCall(Stxr,
9279 {Builder.CreateZExtOrBitCast(
9280 Val, Stxr->getFunctionType()->getParamType(0)),
9284 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9285 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9286 return Ty->isArrayTy();