1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is storage-only, so we promote operations to f32 if we know this is
285 // valid, and ignore them otherwise. The operations not mentioned here will
286 // fail to select, but this is not a major problem as no source language
287 // should be emitting native f16 operations yet.
288 setOperationAction(ISD::FADD, MVT::f16, Promote);
289 setOperationAction(ISD::FDIV, MVT::f16, Promote);
290 setOperationAction(ISD::FMUL, MVT::f16, Promote);
291 setOperationAction(ISD::FSUB, MVT::f16, Promote);
293 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
295 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
296 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
297 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
298 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
299 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
301 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
302 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
308 // Expand all other v4f16 operations.
309 // FIXME: We could generate better code by promoting some operations to
311 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
312 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
315 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
316 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
317 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
319 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
321 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
322 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
323 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
324 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
327 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
328 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
329 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
330 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
332 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
334 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
339 // v8f16 is also a storage-only type, so expand it.
340 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
341 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
342 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
345 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
346 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
347 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
349 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
351 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
353 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
354 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
355 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
356 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
360 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
361 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
362 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
363 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
365 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
366 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
368 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
372 // AArch64 has implementations of a lot of rounding-like FP operations.
373 for (MVT Ty : {MVT::f32, MVT::f64}) {
374 setOperationAction(ISD::FFLOOR, Ty, Legal);
375 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
376 setOperationAction(ISD::FCEIL, Ty, Legal);
377 setOperationAction(ISD::FRINT, Ty, Legal);
378 setOperationAction(ISD::FTRUNC, Ty, Legal);
379 setOperationAction(ISD::FROUND, Ty, Legal);
382 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
384 if (Subtarget->isTargetMachO()) {
385 // For iOS, we don't want to the normal expansion of a libcall to
386 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
388 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
389 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
391 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
392 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
395 // Make floating-point constants legal for the large code model, so they don't
396 // become loads from the constant pool.
397 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
398 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
399 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
402 // AArch64 does not have floating-point extending loads, i1 sign-extending
403 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
404 for (MVT VT : MVT::fp_valuetypes()) {
405 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
406 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
407 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
408 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
410 for (MVT VT : MVT::integer_valuetypes())
411 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
413 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
414 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
415 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
416 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
417 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
418 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
419 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
421 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
422 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
424 // Indexed loads and stores are supported.
425 for (unsigned im = (unsigned)ISD::PRE_INC;
426 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
427 setIndexedLoadAction(im, MVT::i8, Legal);
428 setIndexedLoadAction(im, MVT::i16, Legal);
429 setIndexedLoadAction(im, MVT::i32, Legal);
430 setIndexedLoadAction(im, MVT::i64, Legal);
431 setIndexedLoadAction(im, MVT::f64, Legal);
432 setIndexedLoadAction(im, MVT::f32, Legal);
433 setIndexedStoreAction(im, MVT::i8, Legal);
434 setIndexedStoreAction(im, MVT::i16, Legal);
435 setIndexedStoreAction(im, MVT::i32, Legal);
436 setIndexedStoreAction(im, MVT::i64, Legal);
437 setIndexedStoreAction(im, MVT::f64, Legal);
438 setIndexedStoreAction(im, MVT::f32, Legal);
442 setOperationAction(ISD::TRAP, MVT::Other, Legal);
444 // We combine OR nodes for bitfield operations.
445 setTargetDAGCombine(ISD::OR);
447 // Vector add and sub nodes may conceal a high-half opportunity.
448 // Also, try to fold ADD into CSINC/CSINV..
449 setTargetDAGCombine(ISD::ADD);
450 setTargetDAGCombine(ISD::SUB);
452 setTargetDAGCombine(ISD::XOR);
453 setTargetDAGCombine(ISD::SINT_TO_FP);
454 setTargetDAGCombine(ISD::UINT_TO_FP);
456 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::ANY_EXTEND);
459 setTargetDAGCombine(ISD::ZERO_EXTEND);
460 setTargetDAGCombine(ISD::SIGN_EXTEND);
461 setTargetDAGCombine(ISD::BITCAST);
462 setTargetDAGCombine(ISD::CONCAT_VECTORS);
463 setTargetDAGCombine(ISD::STORE);
465 setTargetDAGCombine(ISD::MUL);
467 setTargetDAGCombine(ISD::SELECT);
468 setTargetDAGCombine(ISD::VSELECT);
470 setTargetDAGCombine(ISD::INTRINSIC_VOID);
471 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
472 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
474 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
475 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
476 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
478 setStackPointerRegisterToSaveRestore(AArch64::SP);
480 setSchedulingPreference(Sched::Hybrid);
483 MaskAndBranchFoldingIsLegal = true;
484 EnableExtLdPromotion = true;
486 setMinFunctionAlignment(2);
488 RequireStrictAlign = (Align == StrictAlign);
490 setHasExtractBitsInsn(true);
492 if (Subtarget->hasNEON()) {
493 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
494 // silliness like this:
495 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
496 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
497 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
499 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
500 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
501 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
502 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
503 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
504 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
505 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
506 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
507 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
508 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
509 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
510 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
511 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
512 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
513 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
514 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
515 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
516 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
517 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
518 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
519 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
521 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
522 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
523 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
524 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
525 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
527 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
529 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
530 // elements smaller than i32, so promote the input to i32 first.
531 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
532 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
533 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
534 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
535 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
536 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
537 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
538 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
539 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
541 // AArch64 doesn't have MUL.2d:
542 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
543 // Custom handling for some quad-vector types to detect MULL.
544 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
545 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
546 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
548 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
549 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
550 // Likewise, narrowing and extending vector loads/stores aren't handled
552 for (MVT VT : MVT::vector_valuetypes()) {
553 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
555 setOperationAction(ISD::MULHS, VT, Expand);
556 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
557 setOperationAction(ISD::MULHU, VT, Expand);
558 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
560 setOperationAction(ISD::BSWAP, VT, Expand);
562 for (MVT InnerVT : MVT::vector_valuetypes()) {
563 setTruncStoreAction(VT, InnerVT, Expand);
564 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
565 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
566 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
570 // AArch64 has implementations of a lot of rounding-like FP operations.
571 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
572 setOperationAction(ISD::FFLOOR, Ty, Legal);
573 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
574 setOperationAction(ISD::FCEIL, Ty, Legal);
575 setOperationAction(ISD::FRINT, Ty, Legal);
576 setOperationAction(ISD::FTRUNC, Ty, Legal);
577 setOperationAction(ISD::FROUND, Ty, Legal);
581 // Prefer likely predicted branches to selects on out-of-order cores.
582 if (Subtarget->isCortexA57())
583 PredictableSelectIsExpensive = true;
586 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
587 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
588 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
589 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
591 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
592 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
593 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
594 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
595 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
597 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
598 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
601 // Mark vector float intrinsics as expand.
602 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
603 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
604 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
605 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
606 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
607 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
608 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
609 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
610 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
611 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
614 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
615 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
616 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
617 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
618 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
619 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
620 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
621 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
622 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
623 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
624 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
625 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
627 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
630 for (MVT InnerVT : MVT::all_valuetypes())
631 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
633 // CNT supports only B element sizes.
634 if (VT != MVT::v8i8 && VT != MVT::v16i8)
635 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
637 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
638 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
639 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
640 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
644 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
646 if (Subtarget->isLittleEndian()) {
647 for (unsigned im = (unsigned)ISD::PRE_INC;
648 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
649 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
650 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
655 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
656 addRegisterClass(VT, &AArch64::FPR64RegClass);
657 addTypeForNEON(VT, MVT::v2i32);
660 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
661 addRegisterClass(VT, &AArch64::FPR128RegClass);
662 addTypeForNEON(VT, MVT::v4i32);
665 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
668 return VT.changeVectorElementTypeToInteger();
671 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
672 /// Mask are known to be either zero or one and return them in the
673 /// KnownZero/KnownOne bitsets.
674 void AArch64TargetLowering::computeKnownBitsForTargetNode(
675 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
676 const SelectionDAG &DAG, unsigned Depth) const {
677 switch (Op.getOpcode()) {
680 case AArch64ISD::CSEL: {
681 APInt KnownZero2, KnownOne2;
682 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
683 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
684 KnownZero &= KnownZero2;
685 KnownOne &= KnownOne2;
688 case ISD::INTRINSIC_W_CHAIN: {
689 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
690 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
693 case Intrinsic::aarch64_ldaxr:
694 case Intrinsic::aarch64_ldxr: {
695 unsigned BitWidth = KnownOne.getBitWidth();
696 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
697 unsigned MemBits = VT.getScalarType().getSizeInBits();
698 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
704 case ISD::INTRINSIC_WO_CHAIN:
705 case ISD::INTRINSIC_VOID: {
706 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
710 case Intrinsic::aarch64_neon_umaxv:
711 case Intrinsic::aarch64_neon_uminv: {
712 // Figure out the datatype of the vector operand. The UMINV instruction
713 // will zero extend the result, so we can mark as known zero all the
714 // bits larger than the element datatype. 32-bit or larget doesn't need
715 // this as those are legal types and will be handled by isel directly.
716 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
717 unsigned BitWidth = KnownZero.getBitWidth();
718 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
719 assert(BitWidth >= 8 && "Unexpected width!");
720 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
722 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
723 assert(BitWidth >= 16 && "Unexpected width!");
724 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
734 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
739 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
740 const TargetLibraryInfo *libInfo) const {
741 return AArch64::createFastISel(funcInfo, libInfo);
744 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
748 case AArch64ISD::CALL: return "AArch64ISD::CALL";
749 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
750 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
751 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
752 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
753 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
754 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
755 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
756 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
757 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
758 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
759 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
760 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
761 case AArch64ISD::ADC: return "AArch64ISD::ADC";
762 case AArch64ISD::SBC: return "AArch64ISD::SBC";
763 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
764 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
765 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
766 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
767 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
768 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
769 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
770 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
771 case AArch64ISD::DUP: return "AArch64ISD::DUP";
772 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
773 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
774 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
775 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
776 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
777 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
778 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
779 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
780 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
781 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
782 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
783 case AArch64ISD::BICi: return "AArch64ISD::BICi";
784 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
785 case AArch64ISD::BSL: return "AArch64ISD::BSL";
786 case AArch64ISD::NEG: return "AArch64ISD::NEG";
787 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
788 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
789 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
790 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
791 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
792 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
793 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
794 case AArch64ISD::REV16: return "AArch64ISD::REV16";
795 case AArch64ISD::REV32: return "AArch64ISD::REV32";
796 case AArch64ISD::REV64: return "AArch64ISD::REV64";
797 case AArch64ISD::EXT: return "AArch64ISD::EXT";
798 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
799 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
800 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
801 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
802 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
803 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
804 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
805 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
806 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
807 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
808 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
809 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
810 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
811 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
812 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
813 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
814 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
815 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
816 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
817 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
818 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
819 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
820 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
821 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
822 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
823 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
824 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
825 case AArch64ISD::NOT: return "AArch64ISD::NOT";
826 case AArch64ISD::BIT: return "AArch64ISD::BIT";
827 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
828 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
829 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
830 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
831 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
832 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
833 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
834 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
835 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
836 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
837 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
838 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
839 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
840 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
841 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
842 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
843 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
844 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
845 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
846 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
847 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
848 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
849 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
850 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
851 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
852 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
853 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
854 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
855 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
856 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
857 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
858 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
859 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
860 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
861 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
862 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
863 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
864 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
865 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
870 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
871 MachineBasicBlock *MBB) const {
872 // We materialise the F128CSEL pseudo-instruction as some control flow and a
876 // [... previous instrs leading to comparison ...]
882 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
884 MachineFunction *MF = MBB->getParent();
885 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
886 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
887 DebugLoc DL = MI->getDebugLoc();
888 MachineFunction::iterator It = MBB;
891 unsigned DestReg = MI->getOperand(0).getReg();
892 unsigned IfTrueReg = MI->getOperand(1).getReg();
893 unsigned IfFalseReg = MI->getOperand(2).getReg();
894 unsigned CondCode = MI->getOperand(3).getImm();
895 bool NZCVKilled = MI->getOperand(4).isKill();
897 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
898 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
899 MF->insert(It, TrueBB);
900 MF->insert(It, EndBB);
902 // Transfer rest of current basic-block to EndBB
903 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
905 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
907 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
908 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
909 MBB->addSuccessor(TrueBB);
910 MBB->addSuccessor(EndBB);
912 // TrueBB falls through to the end.
913 TrueBB->addSuccessor(EndBB);
916 TrueBB->addLiveIn(AArch64::NZCV);
917 EndBB->addLiveIn(AArch64::NZCV);
920 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
926 MI->eraseFromParent();
931 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
932 MachineBasicBlock *BB) const {
933 switch (MI->getOpcode()) {
938 llvm_unreachable("Unexpected instruction for custom inserter!");
940 case AArch64::F128CSEL:
941 return EmitF128CSEL(MI, BB);
943 case TargetOpcode::STACKMAP:
944 case TargetOpcode::PATCHPOINT:
945 return emitPatchPoint(MI, BB);
949 //===----------------------------------------------------------------------===//
950 // AArch64 Lowering private implementation.
951 //===----------------------------------------------------------------------===//
953 //===----------------------------------------------------------------------===//
955 //===----------------------------------------------------------------------===//
957 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
959 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
962 llvm_unreachable("Unknown condition code!");
964 return AArch64CC::NE;
966 return AArch64CC::EQ;
968 return AArch64CC::GT;
970 return AArch64CC::GE;
972 return AArch64CC::LT;
974 return AArch64CC::LE;
976 return AArch64CC::HI;
978 return AArch64CC::HS;
980 return AArch64CC::LO;
982 return AArch64CC::LS;
986 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
987 static void changeFPCCToAArch64CC(ISD::CondCode CC,
988 AArch64CC::CondCode &CondCode,
989 AArch64CC::CondCode &CondCode2) {
990 CondCode2 = AArch64CC::AL;
993 llvm_unreachable("Unknown FP condition!");
996 CondCode = AArch64CC::EQ;
1000 CondCode = AArch64CC::GT;
1004 CondCode = AArch64CC::GE;
1007 CondCode = AArch64CC::MI;
1010 CondCode = AArch64CC::LS;
1013 CondCode = AArch64CC::MI;
1014 CondCode2 = AArch64CC::GT;
1017 CondCode = AArch64CC::VC;
1020 CondCode = AArch64CC::VS;
1023 CondCode = AArch64CC::EQ;
1024 CondCode2 = AArch64CC::VS;
1027 CondCode = AArch64CC::HI;
1030 CondCode = AArch64CC::PL;
1034 CondCode = AArch64CC::LT;
1038 CondCode = AArch64CC::LE;
1042 CondCode = AArch64CC::NE;
1047 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1048 /// CC usable with the vector instructions. Fewer operations are available
1049 /// without a real NZCV register, so we have to use less efficient combinations
1050 /// to get the same effect.
1051 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1052 AArch64CC::CondCode &CondCode,
1053 AArch64CC::CondCode &CondCode2,
1058 // Mostly the scalar mappings work fine.
1059 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1062 Invert = true; // Fallthrough
1064 CondCode = AArch64CC::MI;
1065 CondCode2 = AArch64CC::GE;
1072 // All of the compare-mask comparisons are ordered, but we can switch
1073 // between the two by a double inversion. E.g. ULE == !OGT.
1075 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1080 static bool isLegalArithImmed(uint64_t C) {
1081 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1082 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1085 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1086 SDLoc dl, SelectionDAG &DAG) {
1087 EVT VT = LHS.getValueType();
1089 if (VT.isFloatingPoint())
1090 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1092 // The CMP instruction is just an alias for SUBS, and representing it as
1093 // SUBS means that it's possible to get CSE with subtract operations.
1094 // A later phase can perform the optimization of setting the destination
1095 // register to WZR/XZR if it ends up being unused.
1096 unsigned Opcode = AArch64ISD::SUBS;
1098 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1099 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1100 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1101 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1102 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1103 // can be set differently by this operation. It comes down to whether
1104 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1105 // everything is fine. If not then the optimization is wrong. Thus general
1106 // comparisons are only valid if op2 != 0.
1108 // So, finally, the only LLVM-native comparisons that don't mention C and V
1109 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1110 // the absence of information about op2.
1111 Opcode = AArch64ISD::ADDS;
1112 RHS = RHS.getOperand(1);
1113 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1114 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1115 !isUnsignedIntSetCC(CC)) {
1116 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1117 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1118 // of the signed comparisons.
1119 Opcode = AArch64ISD::ANDS;
1120 RHS = LHS.getOperand(1);
1121 LHS = LHS.getOperand(0);
1124 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1128 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1129 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1131 AArch64CC::CondCode AArch64CC;
1132 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1133 EVT VT = RHS.getValueType();
1134 uint64_t C = RHSC->getZExtValue();
1135 if (!isLegalArithImmed(C)) {
1136 // Constant does not fit, try adjusting it by one?
1142 if ((VT == MVT::i32 && C != 0x80000000 &&
1143 isLegalArithImmed((uint32_t)(C - 1))) ||
1144 (VT == MVT::i64 && C != 0x80000000ULL &&
1145 isLegalArithImmed(C - 1ULL))) {
1146 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1147 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1148 RHS = DAG.getConstant(C, VT);
1153 if ((VT == MVT::i32 && C != 0 &&
1154 isLegalArithImmed((uint32_t)(C - 1))) ||
1155 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1156 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1157 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1158 RHS = DAG.getConstant(C, VT);
1163 if ((VT == MVT::i32 && C != INT32_MAX &&
1164 isLegalArithImmed((uint32_t)(C + 1))) ||
1165 (VT == MVT::i64 && C != INT64_MAX &&
1166 isLegalArithImmed(C + 1ULL))) {
1167 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1168 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1169 RHS = DAG.getConstant(C, VT);
1174 if ((VT == MVT::i32 && C != UINT32_MAX &&
1175 isLegalArithImmed((uint32_t)(C + 1))) ||
1176 (VT == MVT::i64 && C != UINT64_MAX &&
1177 isLegalArithImmed(C + 1ULL))) {
1178 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1179 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1180 RHS = DAG.getConstant(C, VT);
1186 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1187 // For the i8 operand, the largest immediate is 255, so this can be easily
1188 // encoded in the compare instruction. For the i16 operand, however, the
1189 // largest immediate cannot be encoded in the compare.
1190 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1191 // constant. For example,
1193 // ldrh w0, [x0, #0]
1196 // ldrsh w0, [x0, #0]
1198 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1199 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1200 // both the LHS and RHS are truely zero extended and to make sure the
1201 // transformation is profitable.
1202 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1203 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1204 isa<LoadSDNode>(LHS)) {
1205 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1206 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1207 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1208 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1209 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1211 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1212 DAG.getValueType(MVT::i16));
1213 Cmp = emitComparison(SExt,
1214 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1216 AArch64CC = changeIntCCToAArch64CC(CC);
1217 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1223 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1224 AArch64CC = changeIntCCToAArch64CC(CC);
1225 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1229 static std::pair<SDValue, SDValue>
1230 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1231 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1232 "Unsupported value type");
1233 SDValue Value, Overflow;
1235 SDValue LHS = Op.getOperand(0);
1236 SDValue RHS = Op.getOperand(1);
1238 switch (Op.getOpcode()) {
1240 llvm_unreachable("Unknown overflow instruction!");
1242 Opc = AArch64ISD::ADDS;
1246 Opc = AArch64ISD::ADDS;
1250 Opc = AArch64ISD::SUBS;
1254 Opc = AArch64ISD::SUBS;
1257 // Multiply needs a little bit extra work.
1261 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1262 if (Op.getValueType() == MVT::i32) {
1263 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1264 // For a 32 bit multiply with overflow check we want the instruction
1265 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1266 // need to generate the following pattern:
1267 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1268 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1269 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1270 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1271 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1272 DAG.getConstant(0, MVT::i64));
1273 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1274 // operation. We need to clear out the upper 32 bits, because we used a
1275 // widening multiply that wrote all 64 bits. In the end this should be a
1277 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1279 // The signed overflow check requires more than just a simple check for
1280 // any bit set in the upper 32 bits of the result. These bits could be
1281 // just the sign bits of a negative number. To perform the overflow
1282 // check we have to arithmetic shift right the 32nd bit of the result by
1283 // 31 bits. Then we compare the result to the upper 32 bits.
1284 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1285 DAG.getConstant(32, MVT::i64));
1286 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1287 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1288 DAG.getConstant(31, MVT::i64));
1289 // It is important that LowerBits is last, otherwise the arithmetic
1290 // shift will not be folded into the compare (SUBS).
1291 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1292 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1295 // The overflow check for unsigned multiply is easy. We only need to
1296 // check if any of the upper 32 bits are set. This can be done with a
1297 // CMP (shifted register). For that we need to generate the following
1299 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1300 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1301 DAG.getConstant(32, MVT::i64));
1302 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1304 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1305 UpperBits).getValue(1);
1309 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1310 // For the 64 bit multiply
1311 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1313 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1314 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1315 DAG.getConstant(63, MVT::i64));
1316 // It is important that LowerBits is last, otherwise the arithmetic
1317 // shift will not be folded into the compare (SUBS).
1318 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1319 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1322 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1323 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1325 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1326 UpperBits).getValue(1);
1333 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1335 // Emit the AArch64 operation with overflow check.
1336 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1337 Overflow = Value.getValue(1);
1339 return std::make_pair(Value, Overflow);
1342 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1343 RTLIB::Libcall Call) const {
1344 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1345 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1349 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1350 SDValue Sel = Op.getOperand(0);
1351 SDValue Other = Op.getOperand(1);
1353 // If neither operand is a SELECT_CC, give up.
1354 if (Sel.getOpcode() != ISD::SELECT_CC)
1355 std::swap(Sel, Other);
1356 if (Sel.getOpcode() != ISD::SELECT_CC)
1359 // The folding we want to perform is:
1360 // (xor x, (select_cc a, b, cc, 0, -1) )
1362 // (csel x, (xor x, -1), cc ...)
1364 // The latter will get matched to a CSINV instruction.
1366 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1367 SDValue LHS = Sel.getOperand(0);
1368 SDValue RHS = Sel.getOperand(1);
1369 SDValue TVal = Sel.getOperand(2);
1370 SDValue FVal = Sel.getOperand(3);
1373 // FIXME: This could be generalized to non-integer comparisons.
1374 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1377 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1378 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1380 // The the values aren't constants, this isn't the pattern we're looking for.
1381 if (!CFVal || !CTVal)
1384 // We can commute the SELECT_CC by inverting the condition. This
1385 // might be needed to make this fit into a CSINV pattern.
1386 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1387 std::swap(TVal, FVal);
1388 std::swap(CTVal, CFVal);
1389 CC = ISD::getSetCCInverse(CC, true);
1392 // If the constants line up, perform the transform!
1393 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1395 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1398 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1399 DAG.getConstant(-1ULL, Other.getValueType()));
1401 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1408 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1409 EVT VT = Op.getValueType();
1411 // Let legalize expand this if it isn't a legal type yet.
1412 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1415 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1418 bool ExtraOp = false;
1419 switch (Op.getOpcode()) {
1421 llvm_unreachable("Invalid code");
1423 Opc = AArch64ISD::ADDS;
1426 Opc = AArch64ISD::SUBS;
1429 Opc = AArch64ISD::ADCS;
1433 Opc = AArch64ISD::SBCS;
1439 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1440 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1444 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1445 // Let legalize expand this if it isn't a legal type yet.
1446 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1449 AArch64CC::CondCode CC;
1450 // The actual operation that sets the overflow or carry flag.
1451 SDValue Value, Overflow;
1452 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1454 // We use 0 and 1 as false and true values.
1455 SDValue TVal = DAG.getConstant(1, MVT::i32);
1456 SDValue FVal = DAG.getConstant(0, MVT::i32);
1458 // We use an inverted condition, because the conditional select is inverted
1459 // too. This will allow it to be selected to a single instruction:
1460 // CSINC Wd, WZR, WZR, invert(cond).
1461 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1462 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1465 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1466 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1469 // Prefetch operands are:
1470 // 1: Address to prefetch
1472 // 3: int locality (0 = no locality ... 3 = extreme locality)
1473 // 4: bool isDataCache
1474 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1476 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1477 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1478 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1480 bool IsStream = !Locality;
1481 // When the locality number is set
1483 // The front-end should have filtered out the out-of-range values
1484 assert(Locality <= 3 && "Prefetch locality out-of-range");
1485 // The locality degree is the opposite of the cache speed.
1486 // Put the number the other way around.
1487 // The encoding starts at 0 for level 1
1488 Locality = 3 - Locality;
1491 // built the mask value encoding the expected behavior.
1492 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1493 (!IsData << 3) | // IsDataCache bit
1494 (Locality << 1) | // Cache level bits
1495 (unsigned)IsStream; // Stream bit
1496 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1497 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1500 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1501 SelectionDAG &DAG) const {
1502 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1505 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1507 return LowerF128Call(Op, DAG, LC);
1510 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1511 SelectionDAG &DAG) const {
1512 if (Op.getOperand(0).getValueType() != MVT::f128) {
1513 // It's legal except when f128 is involved
1518 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1520 // FP_ROUND node has a second operand indicating whether it is known to be
1521 // precise. That doesn't take part in the LibCall so we can't directly use
1523 SDValue SrcVal = Op.getOperand(0);
1524 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1525 /*isSigned*/ false, SDLoc(Op)).first;
1528 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1529 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1530 // Any additional optimization in this function should be recorded
1531 // in the cost tables.
1532 EVT InVT = Op.getOperand(0).getValueType();
1533 EVT VT = Op.getValueType();
1535 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1538 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1540 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1543 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1546 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1547 VT.getVectorNumElements());
1548 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1549 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1552 // Type changing conversions are illegal.
1556 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1557 SelectionDAG &DAG) const {
1558 if (Op.getOperand(0).getValueType().isVector())
1559 return LowerVectorFP_TO_INT(Op, DAG);
1561 if (Op.getOperand(0).getValueType() != MVT::f128) {
1562 // It's legal except when f128 is involved
1567 if (Op.getOpcode() == ISD::FP_TO_SINT)
1568 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1570 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1572 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1573 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1577 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1578 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1579 // Any additional optimization in this function should be recorded
1580 // in the cost tables.
1581 EVT VT = Op.getValueType();
1583 SDValue In = Op.getOperand(0);
1584 EVT InVT = In.getValueType();
1586 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1588 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1589 InVT.getVectorNumElements());
1590 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1591 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1594 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1596 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1597 EVT CastVT = VT.changeVectorElementTypeToInteger();
1598 In = DAG.getNode(CastOpc, dl, CastVT, In);
1599 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1605 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1606 SelectionDAG &DAG) const {
1607 if (Op.getValueType().isVector())
1608 return LowerVectorINT_TO_FP(Op, DAG);
1610 // i128 conversions are libcalls.
1611 if (Op.getOperand(0).getValueType() == MVT::i128)
1614 // Other conversions are legal, unless it's to the completely software-based
1616 if (Op.getValueType() != MVT::f128)
1620 if (Op.getOpcode() == ISD::SINT_TO_FP)
1621 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1623 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1625 return LowerF128Call(Op, DAG, LC);
1628 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1629 SelectionDAG &DAG) const {
1630 // For iOS, we want to call an alternative entry point: __sincos_stret,
1631 // which returns the values in two S / D registers.
1633 SDValue Arg = Op.getOperand(0);
1634 EVT ArgVT = Arg.getValueType();
1635 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1642 Entry.isSExt = false;
1643 Entry.isZExt = false;
1644 Args.push_back(Entry);
1646 const char *LibcallName =
1647 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1648 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1650 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1651 TargetLowering::CallLoweringInfo CLI(DAG);
1652 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1653 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1655 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1656 return CallResult.first;
1659 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1660 if (Op.getValueType() != MVT::f16)
1663 assert(Op.getOperand(0).getValueType() == MVT::i16);
1666 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1667 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1669 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1670 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1674 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1675 if (OrigVT.getSizeInBits() >= 64)
1678 assert(OrigVT.isSimple() && "Expecting a simple value type");
1680 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1681 switch (OrigSimpleTy) {
1682 default: llvm_unreachable("Unexpected Vector Type");
1691 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1694 unsigned ExtOpcode) {
1695 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1696 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1697 // 64-bits we need to insert a new extension so that it will be 64-bits.
1698 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1699 if (OrigTy.getSizeInBits() >= 64)
1702 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1703 EVT NewVT = getExtensionTo64Bits(OrigTy);
1705 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1708 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1710 EVT VT = N->getValueType(0);
1712 if (N->getOpcode() != ISD::BUILD_VECTOR)
1715 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1716 SDNode *Elt = N->getOperand(i).getNode();
1717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1718 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1719 unsigned HalfSize = EltSize / 2;
1721 if (!isIntN(HalfSize, C->getSExtValue()))
1724 if (!isUIntN(HalfSize, C->getZExtValue()))
1735 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1736 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1737 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1738 N->getOperand(0)->getValueType(0),
1742 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1743 EVT VT = N->getValueType(0);
1744 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1745 unsigned NumElts = VT.getVectorNumElements();
1746 MVT TruncVT = MVT::getIntegerVT(EltSize);
1747 SmallVector<SDValue, 8> Ops;
1748 for (unsigned i = 0; i != NumElts; ++i) {
1749 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1750 const APInt &CInt = C->getAPIntValue();
1751 // Element types smaller than 32 bits are not legal, so use i32 elements.
1752 // The values are implicitly truncated so sext vs. zext doesn't matter.
1753 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1755 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1756 MVT::getVectorVT(TruncVT, NumElts), Ops);
1759 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1760 if (N->getOpcode() == ISD::SIGN_EXTEND)
1762 if (isExtendedBUILD_VECTOR(N, DAG, true))
1767 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1768 if (N->getOpcode() == ISD::ZERO_EXTEND)
1770 if (isExtendedBUILD_VECTOR(N, DAG, false))
1775 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1776 unsigned Opcode = N->getOpcode();
1777 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1778 SDNode *N0 = N->getOperand(0).getNode();
1779 SDNode *N1 = N->getOperand(1).getNode();
1780 return N0->hasOneUse() && N1->hasOneUse() &&
1781 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1786 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1787 unsigned Opcode = N->getOpcode();
1788 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1789 SDNode *N0 = N->getOperand(0).getNode();
1790 SDNode *N1 = N->getOperand(1).getNode();
1791 return N0->hasOneUse() && N1->hasOneUse() &&
1792 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1797 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1798 // Multiplications are only custom-lowered for 128-bit vectors so that
1799 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1800 EVT VT = Op.getValueType();
1801 assert(VT.is128BitVector() && VT.isInteger() &&
1802 "unexpected type for custom-lowering ISD::MUL");
1803 SDNode *N0 = Op.getOperand(0).getNode();
1804 SDNode *N1 = Op.getOperand(1).getNode();
1805 unsigned NewOpc = 0;
1807 bool isN0SExt = isSignExtended(N0, DAG);
1808 bool isN1SExt = isSignExtended(N1, DAG);
1809 if (isN0SExt && isN1SExt)
1810 NewOpc = AArch64ISD::SMULL;
1812 bool isN0ZExt = isZeroExtended(N0, DAG);
1813 bool isN1ZExt = isZeroExtended(N1, DAG);
1814 if (isN0ZExt && isN1ZExt)
1815 NewOpc = AArch64ISD::UMULL;
1816 else if (isN1SExt || isN1ZExt) {
1817 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1818 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1819 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1820 NewOpc = AArch64ISD::SMULL;
1822 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1823 NewOpc = AArch64ISD::UMULL;
1825 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1827 NewOpc = AArch64ISD::UMULL;
1833 if (VT == MVT::v2i64)
1834 // Fall through to expand this. It is not legal.
1837 // Other vector multiplications are legal.
1842 // Legalize to a S/UMULL instruction
1845 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1847 Op0 = skipExtensionForVectorMULL(N0, DAG);
1848 assert(Op0.getValueType().is64BitVector() &&
1849 Op1.getValueType().is64BitVector() &&
1850 "unexpected types for extended operands to VMULL");
1851 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1853 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1854 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1855 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1856 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1857 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1858 EVT Op1VT = Op1.getValueType();
1859 return DAG.getNode(N0->getOpcode(), DL, VT,
1860 DAG.getNode(NewOpc, DL, VT,
1861 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1862 DAG.getNode(NewOpc, DL, VT,
1863 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1866 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1867 SelectionDAG &DAG) const {
1868 switch (Op.getOpcode()) {
1870 llvm_unreachable("unimplemented operand");
1873 return LowerBITCAST(Op, DAG);
1874 case ISD::GlobalAddress:
1875 return LowerGlobalAddress(Op, DAG);
1876 case ISD::GlobalTLSAddress:
1877 return LowerGlobalTLSAddress(Op, DAG);
1879 return LowerSETCC(Op, DAG);
1881 return LowerBR_CC(Op, DAG);
1883 return LowerSELECT(Op, DAG);
1884 case ISD::SELECT_CC:
1885 return LowerSELECT_CC(Op, DAG);
1886 case ISD::JumpTable:
1887 return LowerJumpTable(Op, DAG);
1888 case ISD::ConstantPool:
1889 return LowerConstantPool(Op, DAG);
1890 case ISD::BlockAddress:
1891 return LowerBlockAddress(Op, DAG);
1893 return LowerVASTART(Op, DAG);
1895 return LowerVACOPY(Op, DAG);
1897 return LowerVAARG(Op, DAG);
1902 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1909 return LowerXALUO(Op, DAG);
1911 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1913 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1915 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1917 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1919 return LowerFP_ROUND(Op, DAG);
1920 case ISD::FP_EXTEND:
1921 return LowerFP_EXTEND(Op, DAG);
1922 case ISD::FRAMEADDR:
1923 return LowerFRAMEADDR(Op, DAG);
1924 case ISD::RETURNADDR:
1925 return LowerRETURNADDR(Op, DAG);
1926 case ISD::INSERT_VECTOR_ELT:
1927 return LowerINSERT_VECTOR_ELT(Op, DAG);
1928 case ISD::EXTRACT_VECTOR_ELT:
1929 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1930 case ISD::BUILD_VECTOR:
1931 return LowerBUILD_VECTOR(Op, DAG);
1932 case ISD::VECTOR_SHUFFLE:
1933 return LowerVECTOR_SHUFFLE(Op, DAG);
1934 case ISD::EXTRACT_SUBVECTOR:
1935 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1939 return LowerVectorSRA_SRL_SHL(Op, DAG);
1940 case ISD::SHL_PARTS:
1941 return LowerShiftLeftParts(Op, DAG);
1942 case ISD::SRL_PARTS:
1943 case ISD::SRA_PARTS:
1944 return LowerShiftRightParts(Op, DAG);
1946 return LowerCTPOP(Op, DAG);
1947 case ISD::FCOPYSIGN:
1948 return LowerFCOPYSIGN(Op, DAG);
1950 return LowerVectorAND(Op, DAG);
1952 return LowerVectorOR(Op, DAG);
1954 return LowerXOR(Op, DAG);
1956 return LowerPREFETCH(Op, DAG);
1957 case ISD::SINT_TO_FP:
1958 case ISD::UINT_TO_FP:
1959 return LowerINT_TO_FP(Op, DAG);
1960 case ISD::FP_TO_SINT:
1961 case ISD::FP_TO_UINT:
1962 return LowerFP_TO_INT(Op, DAG);
1964 return LowerFSINCOS(Op, DAG);
1966 return LowerMUL(Op, DAG);
1970 /// getFunctionAlignment - Return the Log2 alignment of this function.
1971 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1975 //===----------------------------------------------------------------------===//
1976 // Calling Convention Implementation
1977 //===----------------------------------------------------------------------===//
1979 #include "AArch64GenCallingConv.inc"
1981 /// Selects the correct CCAssignFn for a given CallingConvention value.
1982 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1983 bool IsVarArg) const {
1986 llvm_unreachable("Unsupported calling convention.");
1987 case CallingConv::WebKit_JS:
1988 return CC_AArch64_WebKit_JS;
1989 case CallingConv::GHC:
1990 return CC_AArch64_GHC;
1991 case CallingConv::C:
1992 case CallingConv::Fast:
1993 if (!Subtarget->isTargetDarwin())
1994 return CC_AArch64_AAPCS;
1995 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1999 SDValue AArch64TargetLowering::LowerFormalArguments(
2000 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2002 SmallVectorImpl<SDValue> &InVals) const {
2003 MachineFunction &MF = DAG.getMachineFunction();
2004 MachineFrameInfo *MFI = MF.getFrameInfo();
2006 // Assign locations to all of the incoming arguments.
2007 SmallVector<CCValAssign, 16> ArgLocs;
2008 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2011 // At this point, Ins[].VT may already be promoted to i32. To correctly
2012 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2013 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2014 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2015 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2017 unsigned NumArgs = Ins.size();
2018 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2019 unsigned CurArgIdx = 0;
2020 for (unsigned i = 0; i != NumArgs; ++i) {
2021 MVT ValVT = Ins[i].VT;
2022 if (Ins[i].isOrigArg()) {
2023 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2024 CurArgIdx = Ins[i].getOrigArgIndex();
2026 // Get type of the original argument.
2027 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2028 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2029 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2030 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2032 else if (ActualMVT == MVT::i16)
2035 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2037 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2038 assert(!Res && "Call operand has unhandled type");
2041 assert(ArgLocs.size() == Ins.size());
2042 SmallVector<SDValue, 16> ArgValues;
2043 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2044 CCValAssign &VA = ArgLocs[i];
2046 if (Ins[i].Flags.isByVal()) {
2047 // Byval is used for HFAs in the PCS, but the system should work in a
2048 // non-compliant manner for larger structs.
2049 EVT PtrTy = getPointerTy();
2050 int Size = Ins[i].Flags.getByValSize();
2051 unsigned NumRegs = (Size + 7) / 8;
2053 // FIXME: This works on big-endian for composite byvals, which are the common
2054 // case. It should also work for fundamental types too.
2056 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2057 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2058 InVals.push_back(FrameIdxN);
2063 if (VA.isRegLoc()) {
2064 // Arguments stored in registers.
2065 EVT RegVT = VA.getLocVT();
2068 const TargetRegisterClass *RC;
2070 if (RegVT == MVT::i32)
2071 RC = &AArch64::GPR32RegClass;
2072 else if (RegVT == MVT::i64)
2073 RC = &AArch64::GPR64RegClass;
2074 else if (RegVT == MVT::f16)
2075 RC = &AArch64::FPR16RegClass;
2076 else if (RegVT == MVT::f32)
2077 RC = &AArch64::FPR32RegClass;
2078 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2079 RC = &AArch64::FPR64RegClass;
2080 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2081 RC = &AArch64::FPR128RegClass;
2083 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2085 // Transform the arguments in physical registers into virtual ones.
2086 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2087 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2089 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2090 // to 64 bits. Insert an assert[sz]ext to capture this, then
2091 // truncate to the right size.
2092 switch (VA.getLocInfo()) {
2094 llvm_unreachable("Unknown loc info!");
2095 case CCValAssign::Full:
2097 case CCValAssign::BCvt:
2098 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2100 case CCValAssign::AExt:
2101 case CCValAssign::SExt:
2102 case CCValAssign::ZExt:
2103 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2104 // nodes after our lowering.
2105 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2109 InVals.push_back(ArgValue);
2111 } else { // VA.isRegLoc()
2112 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2113 unsigned ArgOffset = VA.getLocMemOffset();
2114 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2116 uint32_t BEAlign = 0;
2117 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2118 !Ins[i].Flags.isInConsecutiveRegs())
2119 BEAlign = 8 - ArgSize;
2121 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2123 // Create load nodes to retrieve arguments from the stack.
2124 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2127 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2128 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2129 MVT MemVT = VA.getValVT();
2131 switch (VA.getLocInfo()) {
2134 case CCValAssign::BCvt:
2135 MemVT = VA.getLocVT();
2137 case CCValAssign::SExt:
2138 ExtType = ISD::SEXTLOAD;
2140 case CCValAssign::ZExt:
2141 ExtType = ISD::ZEXTLOAD;
2143 case CCValAssign::AExt:
2144 ExtType = ISD::EXTLOAD;
2148 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2149 MachinePointerInfo::getFixedStack(FI),
2150 MemVT, false, false, false, 0);
2152 InVals.push_back(ArgValue);
2158 if (!Subtarget->isTargetDarwin()) {
2159 // The AAPCS variadic function ABI is identical to the non-variadic
2160 // one. As a result there may be more arguments in registers and we should
2161 // save them for future reference.
2162 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2165 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2166 // This will point to the next argument passed via stack.
2167 unsigned StackOffset = CCInfo.getNextStackOffset();
2168 // We currently pass all varargs at 8-byte alignment.
2169 StackOffset = ((StackOffset + 7) & ~7);
2170 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2173 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2174 unsigned StackArgSize = CCInfo.getNextStackOffset();
2175 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2176 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2177 // This is a non-standard ABI so by fiat I say we're allowed to make full
2178 // use of the stack area to be popped, which must be aligned to 16 bytes in
2180 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2182 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2183 // a multiple of 16.
2184 FuncInfo->setArgumentStackToRestore(StackArgSize);
2186 // This realignment carries over to the available bytes below. Our own
2187 // callers will guarantee the space is free by giving an aligned value to
2190 // Even if we're not expected to free up the space, it's useful to know how
2191 // much is there while considering tail calls (because we can reuse it).
2192 FuncInfo->setBytesInStackArgArea(StackArgSize);
2197 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2198 SelectionDAG &DAG, SDLoc DL,
2199 SDValue &Chain) const {
2200 MachineFunction &MF = DAG.getMachineFunction();
2201 MachineFrameInfo *MFI = MF.getFrameInfo();
2202 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2204 SmallVector<SDValue, 8> MemOps;
2206 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2207 AArch64::X3, AArch64::X4, AArch64::X5,
2208 AArch64::X6, AArch64::X7 };
2209 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2210 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2212 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2214 if (GPRSaveSize != 0) {
2215 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2217 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2219 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2220 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2221 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2223 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2224 MachinePointerInfo::getStack(i * 8), false, false, 0);
2225 MemOps.push_back(Store);
2226 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2227 DAG.getConstant(8, getPointerTy()));
2230 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2231 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2233 if (Subtarget->hasFPARMv8()) {
2234 static const MCPhysReg FPRArgRegs[] = {
2235 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2236 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2237 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2238 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2240 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2242 if (FPRSaveSize != 0) {
2243 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2245 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2247 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2248 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2249 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2252 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2253 MachinePointerInfo::getStack(i * 16), false, false, 0);
2254 MemOps.push_back(Store);
2255 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2256 DAG.getConstant(16, getPointerTy()));
2259 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2260 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2263 if (!MemOps.empty()) {
2264 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2268 /// LowerCallResult - Lower the result values of a call into the
2269 /// appropriate copies out of appropriate physical registers.
2270 SDValue AArch64TargetLowering::LowerCallResult(
2271 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2272 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2273 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2274 SDValue ThisVal) const {
2275 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2276 ? RetCC_AArch64_WebKit_JS
2277 : RetCC_AArch64_AAPCS;
2278 // Assign locations to each value returned by this call.
2279 SmallVector<CCValAssign, 16> RVLocs;
2280 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2282 CCInfo.AnalyzeCallResult(Ins, RetCC);
2284 // Copy all of the result registers out of their specified physreg.
2285 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2286 CCValAssign VA = RVLocs[i];
2288 // Pass 'this' value directly from the argument to return value, to avoid
2289 // reg unit interference
2290 if (i == 0 && isThisReturn) {
2291 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2292 "unexpected return calling convention register assignment");
2293 InVals.push_back(ThisVal);
2298 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2299 Chain = Val.getValue(1);
2300 InFlag = Val.getValue(2);
2302 switch (VA.getLocInfo()) {
2304 llvm_unreachable("Unknown loc info!");
2305 case CCValAssign::Full:
2307 case CCValAssign::BCvt:
2308 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2312 InVals.push_back(Val);
2318 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2319 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2320 bool isCalleeStructRet, bool isCallerStructRet,
2321 const SmallVectorImpl<ISD::OutputArg> &Outs,
2322 const SmallVectorImpl<SDValue> &OutVals,
2323 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2324 // For CallingConv::C this function knows whether the ABI needs
2325 // changing. That's not true for other conventions so they will have to opt in
2327 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2330 const MachineFunction &MF = DAG.getMachineFunction();
2331 const Function *CallerF = MF.getFunction();
2332 CallingConv::ID CallerCC = CallerF->getCallingConv();
2333 bool CCMatch = CallerCC == CalleeCC;
2335 // Byval parameters hand the function a pointer directly into the stack area
2336 // we want to reuse during a tail call. Working around this *is* possible (see
2337 // X86) but less efficient and uglier in LowerCall.
2338 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2339 e = CallerF->arg_end();
2341 if (i->hasByValAttr())
2344 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2345 if (IsTailCallConvention(CalleeCC) && CCMatch)
2350 // Externally-defined functions with weak linkage should not be
2351 // tail-called on AArch64 when the OS does not support dynamic
2352 // pre-emption of symbols, as the AAELF spec requires normal calls
2353 // to undefined weak functions to be replaced with a NOP or jump to the
2354 // next instruction. The behaviour of branch instructions in this
2355 // situation (as used for tail calls) is implementation-defined, so we
2356 // cannot rely on the linker replacing the tail call with a return.
2357 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2358 const GlobalValue *GV = G->getGlobal();
2359 const Triple TT(getTargetMachine().getTargetTriple());
2360 if (GV->hasExternalWeakLinkage() &&
2361 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2365 // Now we search for cases where we can use a tail call without changing the
2366 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2369 // I want anyone implementing a new calling convention to think long and hard
2370 // about this assert.
2371 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2372 "Unexpected variadic calling convention");
2374 if (isVarArg && !Outs.empty()) {
2375 // At least two cases here: if caller is fastcc then we can't have any
2376 // memory arguments (we'd be expected to clean up the stack afterwards). If
2377 // caller is C then we could potentially use its argument area.
2379 // FIXME: for now we take the most conservative of these in both cases:
2380 // disallow all variadic memory operands.
2381 SmallVector<CCValAssign, 16> ArgLocs;
2382 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2385 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2387 if (!ArgLocs[i].isRegLoc())
2391 // If the calling conventions do not match, then we'd better make sure the
2392 // results are returned in the same way as what the caller expects.
2394 SmallVector<CCValAssign, 16> RVLocs1;
2395 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2397 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2399 SmallVector<CCValAssign, 16> RVLocs2;
2400 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2402 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2404 if (RVLocs1.size() != RVLocs2.size())
2406 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2407 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2409 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2411 if (RVLocs1[i].isRegLoc()) {
2412 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2415 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2421 // Nothing more to check if the callee is taking no arguments
2425 SmallVector<CCValAssign, 16> ArgLocs;
2426 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2429 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2431 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2433 // If the stack arguments for this call would fit into our own save area then
2434 // the call can be made tail.
2435 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2438 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2440 MachineFrameInfo *MFI,
2441 int ClobberedFI) const {
2442 SmallVector<SDValue, 8> ArgChains;
2443 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2444 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2446 // Include the original chain at the beginning of the list. When this is
2447 // used by target LowerCall hooks, this helps legalize find the
2448 // CALLSEQ_BEGIN node.
2449 ArgChains.push_back(Chain);
2451 // Add a chain value for each stack argument corresponding
2452 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2453 UE = DAG.getEntryNode().getNode()->use_end();
2455 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2456 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2457 if (FI->getIndex() < 0) {
2458 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2459 int64_t InLastByte = InFirstByte;
2460 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2462 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2463 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2464 ArgChains.push_back(SDValue(L, 1));
2467 // Build a tokenfactor for all the chains.
2468 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2471 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2472 bool TailCallOpt) const {
2473 return CallCC == CallingConv::Fast && TailCallOpt;
2476 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2477 return CallCC == CallingConv::Fast;
2480 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2481 /// and add input and output parameter nodes.
2483 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2484 SmallVectorImpl<SDValue> &InVals) const {
2485 SelectionDAG &DAG = CLI.DAG;
2487 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2488 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2489 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2490 SDValue Chain = CLI.Chain;
2491 SDValue Callee = CLI.Callee;
2492 bool &IsTailCall = CLI.IsTailCall;
2493 CallingConv::ID CallConv = CLI.CallConv;
2494 bool IsVarArg = CLI.IsVarArg;
2496 MachineFunction &MF = DAG.getMachineFunction();
2497 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2498 bool IsThisReturn = false;
2500 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2501 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2502 bool IsSibCall = false;
2505 // Check if it's really possible to do a tail call.
2506 IsTailCall = isEligibleForTailCallOptimization(
2507 Callee, CallConv, IsVarArg, IsStructRet,
2508 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2509 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2510 report_fatal_error("failed to perform tail call elimination on a call "
2511 "site marked musttail");
2513 // A sibling call is one where we're under the usual C ABI and not planning
2514 // to change that but can still do a tail call:
2515 if (!TailCallOpt && IsTailCall)
2522 // Analyze operands of the call, assigning locations to each operand.
2523 SmallVector<CCValAssign, 16> ArgLocs;
2524 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2528 // Handle fixed and variable vector arguments differently.
2529 // Variable vector arguments always go into memory.
2530 unsigned NumArgs = Outs.size();
2532 for (unsigned i = 0; i != NumArgs; ++i) {
2533 MVT ArgVT = Outs[i].VT;
2534 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2535 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2536 /*IsVarArg=*/ !Outs[i].IsFixed);
2537 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2538 assert(!Res && "Call operand has unhandled type");
2542 // At this point, Outs[].VT may already be promoted to i32. To correctly
2543 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2544 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2545 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2546 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2548 unsigned NumArgs = Outs.size();
2549 for (unsigned i = 0; i != NumArgs; ++i) {
2550 MVT ValVT = Outs[i].VT;
2551 // Get type of the original argument.
2552 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2553 /*AllowUnknown*/ true);
2554 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2555 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2556 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2557 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2559 else if (ActualMVT == MVT::i16)
2562 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2563 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2564 assert(!Res && "Call operand has unhandled type");
2569 // Get a count of how many bytes are to be pushed on the stack.
2570 unsigned NumBytes = CCInfo.getNextStackOffset();
2573 // Since we're not changing the ABI to make this a tail call, the memory
2574 // operands are already available in the caller's incoming argument space.
2578 // FPDiff is the byte offset of the call's argument area from the callee's.
2579 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2580 // by this amount for a tail call. In a sibling call it must be 0 because the
2581 // caller will deallocate the entire stack and the callee still expects its
2582 // arguments to begin at SP+0. Completely unused for non-tail calls.
2585 if (IsTailCall && !IsSibCall) {
2586 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2588 // Since callee will pop argument stack as a tail call, we must keep the
2589 // popped size 16-byte aligned.
2590 NumBytes = RoundUpToAlignment(NumBytes, 16);
2592 // FPDiff will be negative if this tail call requires more space than we
2593 // would automatically have in our incoming argument space. Positive if we
2594 // can actually shrink the stack.
2595 FPDiff = NumReusableBytes - NumBytes;
2597 // The stack pointer must be 16-byte aligned at all times it's used for a
2598 // memory operation, which in practice means at *all* times and in
2599 // particular across call boundaries. Therefore our own arguments started at
2600 // a 16-byte aligned SP and the delta applied for the tail call should
2601 // satisfy the same constraint.
2602 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2605 // Adjust the stack pointer for the new arguments...
2606 // These operations are automatically eliminated by the prolog/epilog pass
2609 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2611 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2613 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2614 SmallVector<SDValue, 8> MemOpChains;
2616 // Walk the register/memloc assignments, inserting copies/loads.
2617 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2618 ++i, ++realArgIdx) {
2619 CCValAssign &VA = ArgLocs[i];
2620 SDValue Arg = OutVals[realArgIdx];
2621 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2623 // Promote the value if needed.
2624 switch (VA.getLocInfo()) {
2626 llvm_unreachable("Unknown loc info!");
2627 case CCValAssign::Full:
2629 case CCValAssign::SExt:
2630 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2632 case CCValAssign::ZExt:
2633 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2635 case CCValAssign::AExt:
2636 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2637 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2638 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2639 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2641 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2643 case CCValAssign::BCvt:
2644 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2646 case CCValAssign::FPExt:
2647 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2651 if (VA.isRegLoc()) {
2652 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2653 assert(VA.getLocVT() == MVT::i64 &&
2654 "unexpected calling convention register assignment");
2655 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2656 "unexpected use of 'returned'");
2657 IsThisReturn = true;
2659 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2661 assert(VA.isMemLoc());
2664 MachinePointerInfo DstInfo;
2666 // FIXME: This works on big-endian for composite byvals, which are the
2667 // common case. It should also work for fundamental types too.
2668 uint32_t BEAlign = 0;
2669 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2670 : VA.getValVT().getSizeInBits();
2671 OpSize = (OpSize + 7) / 8;
2672 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2673 !Flags.isInConsecutiveRegs()) {
2675 BEAlign = 8 - OpSize;
2677 unsigned LocMemOffset = VA.getLocMemOffset();
2678 int32_t Offset = LocMemOffset + BEAlign;
2679 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2680 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2683 Offset = Offset + FPDiff;
2684 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2686 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2687 DstInfo = MachinePointerInfo::getFixedStack(FI);
2689 // Make sure any stack arguments overlapping with where we're storing
2690 // are loaded before this eventual operation. Otherwise they'll be
2692 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2694 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2696 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2697 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2700 if (Outs[i].Flags.isByVal()) {
2702 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2703 SDValue Cpy = DAG.getMemcpy(
2704 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2706 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2708 MemOpChains.push_back(Cpy);
2710 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2711 // promoted to a legal register type i32, we should truncate Arg back to
2713 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2714 VA.getValVT() == MVT::i16)
2715 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2718 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2719 MemOpChains.push_back(Store);
2724 if (!MemOpChains.empty())
2725 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2727 // Build a sequence of copy-to-reg nodes chained together with token chain
2728 // and flag operands which copy the outgoing args into the appropriate regs.
2730 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2731 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2732 RegsToPass[i].second, InFlag);
2733 InFlag = Chain.getValue(1);
2736 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2737 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2738 // node so that legalize doesn't hack it.
2739 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2740 Subtarget->isTargetMachO()) {
2741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2742 const GlobalValue *GV = G->getGlobal();
2743 bool InternalLinkage = GV->hasInternalLinkage();
2744 if (InternalLinkage)
2745 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2747 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2749 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2751 } else if (ExternalSymbolSDNode *S =
2752 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2753 const char *Sym = S->getSymbol();
2755 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2756 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2758 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2759 const GlobalValue *GV = G->getGlobal();
2760 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2761 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2762 const char *Sym = S->getSymbol();
2763 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2766 // We don't usually want to end the call-sequence here because we would tidy
2767 // the frame up *after* the call, however in the ABI-changing tail-call case
2768 // we've carefully laid out the parameters so that when sp is reset they'll be
2769 // in the correct location.
2770 if (IsTailCall && !IsSibCall) {
2771 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2772 DAG.getIntPtrConstant(0, true), InFlag, DL);
2773 InFlag = Chain.getValue(1);
2776 std::vector<SDValue> Ops;
2777 Ops.push_back(Chain);
2778 Ops.push_back(Callee);
2781 // Each tail call may have to adjust the stack by a different amount, so
2782 // this information must travel along with the operation for eventual
2783 // consumption by emitEpilogue.
2784 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2787 // Add argument registers to the end of the list so that they are known live
2789 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2790 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2791 RegsToPass[i].second.getValueType()));
2793 // Add a register mask operand representing the call-preserved registers.
2794 const uint32_t *Mask;
2795 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2797 // For 'this' returns, use the X0-preserving mask if applicable
2798 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2800 IsThisReturn = false;
2801 Mask = TRI->getCallPreservedMask(MF, CallConv);
2804 Mask = TRI->getCallPreservedMask(MF, CallConv);
2806 assert(Mask && "Missing call preserved mask for calling convention");
2807 Ops.push_back(DAG.getRegisterMask(Mask));
2809 if (InFlag.getNode())
2810 Ops.push_back(InFlag);
2812 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2814 // If we're doing a tall call, use a TC_RETURN here rather than an
2815 // actual call instruction.
2817 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2819 // Returns a chain and a flag for retval copy to use.
2820 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2821 InFlag = Chain.getValue(1);
2823 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2824 ? RoundUpToAlignment(NumBytes, 16)
2827 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2828 DAG.getIntPtrConstant(CalleePopBytes, true),
2831 InFlag = Chain.getValue(1);
2833 // Handle result values, copying them out of physregs into vregs that we
2835 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2836 InVals, IsThisReturn,
2837 IsThisReturn ? OutVals[0] : SDValue());
2840 bool AArch64TargetLowering::CanLowerReturn(
2841 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2842 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2843 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2844 ? RetCC_AArch64_WebKit_JS
2845 : RetCC_AArch64_AAPCS;
2846 SmallVector<CCValAssign, 16> RVLocs;
2847 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2848 return CCInfo.CheckReturn(Outs, RetCC);
2852 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2854 const SmallVectorImpl<ISD::OutputArg> &Outs,
2855 const SmallVectorImpl<SDValue> &OutVals,
2856 SDLoc DL, SelectionDAG &DAG) const {
2857 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2858 ? RetCC_AArch64_WebKit_JS
2859 : RetCC_AArch64_AAPCS;
2860 SmallVector<CCValAssign, 16> RVLocs;
2861 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2863 CCInfo.AnalyzeReturn(Outs, RetCC);
2865 // Copy the result values into the output registers.
2867 SmallVector<SDValue, 4> RetOps(1, Chain);
2868 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2869 ++i, ++realRVLocIdx) {
2870 CCValAssign &VA = RVLocs[i];
2871 assert(VA.isRegLoc() && "Can only return in registers!");
2872 SDValue Arg = OutVals[realRVLocIdx];
2874 switch (VA.getLocInfo()) {
2876 llvm_unreachable("Unknown loc info!");
2877 case CCValAssign::Full:
2878 if (Outs[i].ArgVT == MVT::i1) {
2879 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2880 // value. This is strictly redundant on Darwin (which uses "zeroext
2881 // i1"), but will be optimised out before ISel.
2882 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2883 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2886 case CCValAssign::BCvt:
2887 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2891 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2892 Flag = Chain.getValue(1);
2893 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2896 RetOps[0] = Chain; // Update chain.
2898 // Add the flag if we have it.
2900 RetOps.push_back(Flag);
2902 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2905 //===----------------------------------------------------------------------===//
2906 // Other Lowering Code
2907 //===----------------------------------------------------------------------===//
2909 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2910 SelectionDAG &DAG) const {
2911 EVT PtrVT = getPointerTy();
2913 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2914 const GlobalValue *GV = GN->getGlobal();
2915 unsigned char OpFlags =
2916 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2918 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2919 "unexpected offset in global node");
2921 // This also catched the large code model case for Darwin.
2922 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2923 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2924 // FIXME: Once remat is capable of dealing with instructions with register
2925 // operands, expand this into two nodes instead of using a wrapper node.
2926 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2929 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2930 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2931 "use of MO_CONSTPOOL only supported on small model");
2932 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2933 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2934 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2935 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2936 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2937 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2938 MachinePointerInfo::getConstantPool(),
2939 /*isVolatile=*/ false,
2940 /*isNonTemporal=*/ true,
2941 /*isInvariant=*/ true, 8);
2942 if (GN->getOffset() != 0)
2943 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2944 DAG.getConstant(GN->getOffset(), PtrVT));
2948 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2949 const unsigned char MO_NC = AArch64II::MO_NC;
2951 AArch64ISD::WrapperLarge, DL, PtrVT,
2952 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2953 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2954 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2955 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2957 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2958 // the only correct model on Darwin.
2959 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2960 OpFlags | AArch64II::MO_PAGE);
2961 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2962 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2964 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2965 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2969 /// \brief Convert a TLS address reference into the correct sequence of loads
2970 /// and calls to compute the variable's address (for Darwin, currently) and
2971 /// return an SDValue containing the final node.
2973 /// Darwin only has one TLS scheme which must be capable of dealing with the
2974 /// fully general situation, in the worst case. This means:
2975 /// + "extern __thread" declaration.
2976 /// + Defined in a possibly unknown dynamic library.
2978 /// The general system is that each __thread variable has a [3 x i64] descriptor
2979 /// which contains information used by the runtime to calculate the address. The
2980 /// only part of this the compiler needs to know about is the first xword, which
2981 /// contains a function pointer that must be called with the address of the
2982 /// entire descriptor in "x0".
2984 /// Since this descriptor may be in a different unit, in general even the
2985 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2987 /// adrp x0, _var@TLVPPAGE
2988 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2989 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2990 /// ; the function pointer
2991 /// blr x1 ; Uses descriptor address in x0
2992 /// ; Address of _var is now in x0.
2994 /// If the address of _var's descriptor *is* known to the linker, then it can
2995 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2996 /// a slight efficiency gain.
2998 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2999 SelectionDAG &DAG) const {
3000 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3003 MVT PtrVT = getPointerTy();
3004 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3007 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3008 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3010 // The first entry in the descriptor is a function pointer that we must call
3011 // to obtain the address of the variable.
3012 SDValue Chain = DAG.getEntryNode();
3013 SDValue FuncTLVGet =
3014 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3015 false, true, true, 8);
3016 Chain = FuncTLVGet.getValue(1);
3018 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3019 MFI->setAdjustsStack(true);
3021 // TLS calls preserve all registers except those that absolutely must be
3022 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3024 const uint32_t *Mask =
3025 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3027 // Finally, we can make the call. This is just a degenerate version of a
3028 // normal AArch64 call node: x0 takes the address of the descriptor, and
3029 // returns the address of the variable in this thread.
3030 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3032 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3033 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3034 DAG.getRegisterMask(Mask), Chain.getValue(1));
3035 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3038 /// When accessing thread-local variables under either the general-dynamic or
3039 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3040 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3041 /// is a function pointer to carry out the resolution.
3043 /// The sequence is:
3044 /// adrp x0, :tlsdesc:var
3045 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3046 /// add x0, x0, #:tlsdesc_lo12:var
3047 /// .tlsdesccall var
3049 /// (TPIDR_EL0 offset now in x0)
3051 /// The above sequence must be produced unscheduled, to enable the linker to
3052 /// optimize/relax this sequence.
3053 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3054 /// above sequence, and expanded really late in the compilation flow, to ensure
3055 /// the sequence is produced as per above.
3056 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3057 SelectionDAG &DAG) const {
3058 EVT PtrVT = getPointerTy();
3060 SDValue Chain = DAG.getEntryNode();
3061 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3063 SmallVector<SDValue, 2> Ops;
3064 Ops.push_back(Chain);
3065 Ops.push_back(SymAddr);
3067 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3068 SDValue Glue = Chain.getValue(1);
3070 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3074 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3075 SelectionDAG &DAG) const {
3076 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3077 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3078 "ELF TLS only supported in small memory model");
3079 // Different choices can be made for the maximum size of the TLS area for a
3080 // module. For the small address model, the default TLS size is 16MiB and the
3081 // maximum TLS size is 4GiB.
3082 // FIXME: add -mtls-size command line option and make it control the 16MiB
3083 // vs. 4GiB code sequence generation.
3084 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3086 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3087 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3088 if (Model == TLSModel::LocalDynamic)
3089 Model = TLSModel::GeneralDynamic;
3093 EVT PtrVT = getPointerTy();
3095 const GlobalValue *GV = GA->getGlobal();
3097 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3099 if (Model == TLSModel::LocalExec) {
3100 SDValue HiVar = DAG.getTargetGlobalAddress(
3101 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3102 SDValue LoVar = DAG.getTargetGlobalAddress(
3104 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3106 SDValue TPWithOff_lo =
3107 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3108 HiVar, DAG.getTargetConstant(0, MVT::i32)),
3111 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3112 LoVar, DAG.getTargetConstant(0, MVT::i32)),
3115 } else if (Model == TLSModel::InitialExec) {
3116 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3117 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3118 } else if (Model == TLSModel::LocalDynamic) {
3119 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3120 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3121 // the beginning of the module's TLS region, followed by a DTPREL offset
3124 // These accesses will need deduplicating if there's more than one.
3125 AArch64FunctionInfo *MFI =
3126 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3127 MFI->incNumLocalDynamicTLSAccesses();
3129 // The call needs a relocation too for linker relaxation. It doesn't make
3130 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3132 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3135 // Now we can calculate the offset from TPIDR_EL0 to this module's
3136 // thread-local area.
3137 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3139 // Now use :dtprel_whatever: operations to calculate this variable's offset
3140 // in its thread-storage area.
3141 SDValue HiVar = DAG.getTargetGlobalAddress(
3142 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3143 SDValue LoVar = DAG.getTargetGlobalAddress(
3144 GV, DL, MVT::i64, 0,
3145 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3147 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3148 DAG.getTargetConstant(0, MVT::i32)),
3150 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3151 DAG.getTargetConstant(0, MVT::i32)),
3153 } else if (Model == TLSModel::GeneralDynamic) {
3154 // The call needs a relocation too for linker relaxation. It doesn't make
3155 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3158 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3160 // Finally we can make a call to calculate the offset from tpidr_el0.
3161 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3163 llvm_unreachable("Unsupported ELF TLS access model");
3165 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3168 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3169 SelectionDAG &DAG) const {
3170 if (Subtarget->isTargetDarwin())
3171 return LowerDarwinGlobalTLSAddress(Op, DAG);
3172 else if (Subtarget->isTargetELF())
3173 return LowerELFGlobalTLSAddress(Op, DAG);
3175 llvm_unreachable("Unexpected platform trying to use TLS");
3177 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3178 SDValue Chain = Op.getOperand(0);
3179 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3180 SDValue LHS = Op.getOperand(2);
3181 SDValue RHS = Op.getOperand(3);
3182 SDValue Dest = Op.getOperand(4);
3185 // Handle f128 first, since lowering it will result in comparing the return
3186 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3187 // is expecting to deal with.
3188 if (LHS.getValueType() == MVT::f128) {
3189 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3191 // If softenSetCCOperands returned a scalar, we need to compare the result
3192 // against zero to select between true and false values.
3193 if (!RHS.getNode()) {
3194 RHS = DAG.getConstant(0, LHS.getValueType());
3199 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3201 unsigned Opc = LHS.getOpcode();
3202 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3203 cast<ConstantSDNode>(RHS)->isOne() &&
3204 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3205 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3206 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3207 "Unexpected condition code.");
3208 // Only lower legal XALUO ops.
3209 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3212 // The actual operation with overflow check.
3213 AArch64CC::CondCode OFCC;
3214 SDValue Value, Overflow;
3215 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3217 if (CC == ISD::SETNE)
3218 OFCC = getInvertedCondCode(OFCC);
3219 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3221 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3225 if (LHS.getValueType().isInteger()) {
3226 assert((LHS.getValueType() == RHS.getValueType()) &&
3227 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3229 // If the RHS of the comparison is zero, we can potentially fold this
3230 // to a specialized branch.
3231 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3232 if (RHSC && RHSC->getZExtValue() == 0) {
3233 if (CC == ISD::SETEQ) {
3234 // See if we can use a TBZ to fold in an AND as well.
3235 // TBZ has a smaller branch displacement than CBZ. If the offset is
3236 // out of bounds, a late MI-layer pass rewrites branches.
3237 // 403.gcc is an example that hits this case.
3238 if (LHS.getOpcode() == ISD::AND &&
3239 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3240 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3241 SDValue Test = LHS.getOperand(0);
3242 uint64_t Mask = LHS.getConstantOperandVal(1);
3243 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3244 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3247 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3248 } else if (CC == ISD::SETNE) {
3249 // See if we can use a TBZ to fold in an AND as well.
3250 // TBZ has a smaller branch displacement than CBZ. If the offset is
3251 // out of bounds, a late MI-layer pass rewrites branches.
3252 // 403.gcc is an example that hits this case.
3253 if (LHS.getOpcode() == ISD::AND &&
3254 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3255 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3256 SDValue Test = LHS.getOperand(0);
3257 uint64_t Mask = LHS.getConstantOperandVal(1);
3258 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3259 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3262 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3263 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3264 // Don't combine AND since emitComparison converts the AND to an ANDS
3265 // (a.k.a. TST) and the test in the test bit and branch instruction
3266 // becomes redundant. This would also increase register pressure.
3267 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3268 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3269 DAG.getConstant(Mask, MVT::i64), Dest);
3272 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3273 LHS.getOpcode() != ISD::AND) {
3274 // Don't combine AND since emitComparison converts the AND to an ANDS
3275 // (a.k.a. TST) and the test in the test bit and branch instruction
3276 // becomes redundant. This would also increase register pressure.
3277 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3278 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3279 DAG.getConstant(Mask, MVT::i64), Dest);
3283 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3284 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3288 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3290 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3291 // clean. Some of them require two branches to implement.
3292 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3293 AArch64CC::CondCode CC1, CC2;
3294 changeFPCCToAArch64CC(CC, CC1, CC2);
3295 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3297 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3298 if (CC2 != AArch64CC::AL) {
3299 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3300 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3307 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3308 SelectionDAG &DAG) const {
3309 EVT VT = Op.getValueType();
3312 SDValue In1 = Op.getOperand(0);
3313 SDValue In2 = Op.getOperand(1);
3314 EVT SrcVT = In2.getValueType();
3316 if (SrcVT == MVT::f32 && VT == MVT::f64)
3317 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3318 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3319 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3321 // FIXME: Src type is different, bail out for now. Can VT really be a
3329 SDValue VecVal1, VecVal2;
3330 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3333 EltMask = 0x80000000ULL;
3335 if (!VT.isVector()) {
3336 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3337 DAG.getUNDEF(VecVT), In1);
3338 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3339 DAG.getUNDEF(VecVT), In2);
3341 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3342 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3344 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3348 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3349 // immediate moves cannot materialize that in a single instruction for
3350 // 64-bit elements. Instead, materialize zero and then negate it.
3353 if (!VT.isVector()) {
3354 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3355 DAG.getUNDEF(VecVT), In1);
3356 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3357 DAG.getUNDEF(VecVT), In2);
3359 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3360 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3363 llvm_unreachable("Invalid type for copysign!");
3366 SDValue BuildVec = DAG.getConstant(EltMask, VecVT);
3368 // If we couldn't materialize the mask above, then the mask vector will be
3369 // the zero vector, and we need to negate it here.
3370 if (VT == MVT::f64 || VT == MVT::v2f64) {
3371 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3372 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3373 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3377 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3380 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3381 else if (VT == MVT::f64)
3382 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3384 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3387 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3388 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3389 Attribute::NoImplicitFloat))
3392 if (!Subtarget->hasNEON())
3395 // While there is no integer popcount instruction, it can
3396 // be more efficiently lowered to the following sequence that uses
3397 // AdvSIMD registers/instructions as long as the copies to/from
3398 // the AdvSIMD registers are cheap.
3399 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3400 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3401 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3402 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3403 SDValue Val = Op.getOperand(0);
3405 EVT VT = Op.getValueType();
3408 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3409 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3411 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3412 SDValue UaddLV = DAG.getNode(
3413 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3414 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3417 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3421 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3423 if (Op.getValueType().isVector())
3424 return LowerVSETCC(Op, DAG);
3426 SDValue LHS = Op.getOperand(0);
3427 SDValue RHS = Op.getOperand(1);
3428 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3431 // We chose ZeroOrOneBooleanContents, so use zero and one.
3432 EVT VT = Op.getValueType();
3433 SDValue TVal = DAG.getConstant(1, VT);
3434 SDValue FVal = DAG.getConstant(0, VT);
3436 // Handle f128 first, since one possible outcome is a normal integer
3437 // comparison which gets picked up by the next if statement.
3438 if (LHS.getValueType() == MVT::f128) {
3439 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3441 // If softenSetCCOperands returned a scalar, use it.
3442 if (!RHS.getNode()) {
3443 assert(LHS.getValueType() == Op.getValueType() &&
3444 "Unexpected setcc expansion!");
3449 if (LHS.getValueType().isInteger()) {
3452 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3454 // Note that we inverted the condition above, so we reverse the order of
3455 // the true and false operands here. This will allow the setcc to be
3456 // matched to a single CSINC instruction.
3457 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3460 // Now we know we're dealing with FP values.
3461 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3463 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3464 // and do the comparison.
3465 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3467 AArch64CC::CondCode CC1, CC2;
3468 changeFPCCToAArch64CC(CC, CC1, CC2);
3469 if (CC2 == AArch64CC::AL) {
3470 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3471 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3473 // Note that we inverted the condition above, so we reverse the order of
3474 // the true and false operands here. This will allow the setcc to be
3475 // matched to a single CSINC instruction.
3476 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3478 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3479 // totally clean. Some of them require two CSELs to implement. As is in
3480 // this case, we emit the first CSEL and then emit a second using the output
3481 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3483 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3484 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3486 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3488 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3489 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3493 /// A SELECT_CC operation is really some kind of max or min if both values being
3494 /// compared are, in some sense, equal to the results in either case. However,
3495 /// it is permissible to compare f32 values and produce directly extended f64
3498 /// Extending the comparison operands would also be allowed, but is less likely
3499 /// to happen in practice since their use is right here. Note that truncate
3500 /// operations would *not* be semantically equivalent.
3501 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3505 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3506 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3507 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3508 Result.getValueType() == MVT::f64) {
3510 APFloat CmpVal = CCmp->getValueAPF();
3511 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3512 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3515 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3518 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3519 SDValue RHS, SDValue TVal,
3520 SDValue FVal, SDLoc dl,
3521 SelectionDAG &DAG) const {
3522 // Handle f128 first, because it will result in a comparison of some RTLIB
3523 // call result against zero.
3524 if (LHS.getValueType() == MVT::f128) {
3525 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3527 // If softenSetCCOperands returned a scalar, we need to compare the result
3528 // against zero to select between true and false values.
3529 if (!RHS.getNode()) {
3530 RHS = DAG.getConstant(0, LHS.getValueType());
3535 // Handle integers first.
3536 if (LHS.getValueType().isInteger()) {
3537 assert((LHS.getValueType() == RHS.getValueType()) &&
3538 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3540 unsigned Opcode = AArch64ISD::CSEL;
3542 // If both the TVal and the FVal are constants, see if we can swap them in
3543 // order to for a CSINV or CSINC out of them.
3544 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3545 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3547 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3548 std::swap(TVal, FVal);
3549 std::swap(CTVal, CFVal);
3550 CC = ISD::getSetCCInverse(CC, true);
3551 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3552 std::swap(TVal, FVal);
3553 std::swap(CTVal, CFVal);
3554 CC = ISD::getSetCCInverse(CC, true);
3555 } else if (TVal.getOpcode() == ISD::XOR) {
3556 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3557 // with a CSINV rather than a CSEL.
3558 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3560 if (CVal && CVal->isAllOnesValue()) {
3561 std::swap(TVal, FVal);
3562 std::swap(CTVal, CFVal);
3563 CC = ISD::getSetCCInverse(CC, true);
3565 } else if (TVal.getOpcode() == ISD::SUB) {
3566 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3567 // that we can match with a CSNEG rather than a CSEL.
3568 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3570 if (CVal && CVal->isNullValue()) {
3571 std::swap(TVal, FVal);
3572 std::swap(CTVal, CFVal);
3573 CC = ISD::getSetCCInverse(CC, true);
3575 } else if (CTVal && CFVal) {
3576 const int64_t TrueVal = CTVal->getSExtValue();
3577 const int64_t FalseVal = CFVal->getSExtValue();
3580 // If both TVal and FVal are constants, see if FVal is the
3581 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3582 // instead of a CSEL in that case.
3583 if (TrueVal == ~FalseVal) {
3584 Opcode = AArch64ISD::CSINV;
3585 } else if (TrueVal == -FalseVal) {
3586 Opcode = AArch64ISD::CSNEG;
3587 } else if (TVal.getValueType() == MVT::i32) {
3588 // If our operands are only 32-bit wide, make sure we use 32-bit
3589 // arithmetic for the check whether we can use CSINC. This ensures that
3590 // the addition in the check will wrap around properly in case there is
3591 // an overflow (which would not be the case if we do the check with
3592 // 64-bit arithmetic).
3593 const uint32_t TrueVal32 = CTVal->getZExtValue();
3594 const uint32_t FalseVal32 = CFVal->getZExtValue();
3596 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3597 Opcode = AArch64ISD::CSINC;
3599 if (TrueVal32 > FalseVal32) {
3603 // 64-bit check whether we can use CSINC.
3604 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3605 Opcode = AArch64ISD::CSINC;
3607 if (TrueVal > FalseVal) {
3612 // Swap TVal and FVal if necessary.
3614 std::swap(TVal, FVal);
3615 std::swap(CTVal, CFVal);
3616 CC = ISD::getSetCCInverse(CC, true);
3619 if (Opcode != AArch64ISD::CSEL) {
3620 // Drop FVal since we can get its value by simply inverting/negating
3627 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3629 EVT VT = TVal.getValueType();
3630 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3633 // Now we know we're dealing with FP values.
3634 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3635 assert(LHS.getValueType() == RHS.getValueType());
3636 EVT VT = TVal.getValueType();
3638 // Try to match this select into a max/min operation, which have dedicated
3639 // opcode in the instruction set.
3640 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3642 if (getTargetMachine().Options.NoNaNsFPMath) {
3643 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3644 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3645 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3646 CC = ISD::getSetCCSwappedOperands(CC);
3647 std::swap(MinMaxLHS, MinMaxRHS);
3650 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3651 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3661 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3669 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3675 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3676 // and do the comparison.
3677 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3679 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3680 // clean. Some of them require two CSELs to implement.
3681 AArch64CC::CondCode CC1, CC2;
3682 changeFPCCToAArch64CC(CC, CC1, CC2);
3683 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3684 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3686 // If we need a second CSEL, emit it, using the output of the first as the
3687 // RHS. We're effectively OR'ing the two CC's together.
3688 if (CC2 != AArch64CC::AL) {
3689 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3690 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3693 // Otherwise, return the output of the first CSEL.
3697 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3698 SelectionDAG &DAG) const {
3699 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3700 SDValue LHS = Op.getOperand(0);
3701 SDValue RHS = Op.getOperand(1);
3702 SDValue TVal = Op.getOperand(2);
3703 SDValue FVal = Op.getOperand(3);
3705 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3708 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3709 SelectionDAG &DAG) const {
3710 SDValue CCVal = Op->getOperand(0);
3711 SDValue TVal = Op->getOperand(1);
3712 SDValue FVal = Op->getOperand(2);
3715 unsigned Opc = CCVal.getOpcode();
3716 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3718 if (CCVal.getResNo() == 1 &&
3719 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3720 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3721 // Only lower legal XALUO ops.
3722 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3725 AArch64CC::CondCode OFCC;
3726 SDValue Value, Overflow;
3727 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3728 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3730 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3734 // Lower it the same way as we would lower a SELECT_CC node.
3737 if (CCVal.getOpcode() == ISD::SETCC) {
3738 LHS = CCVal.getOperand(0);
3739 RHS = CCVal.getOperand(1);
3740 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3743 RHS = DAG.getConstant(0, CCVal.getValueType());
3746 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3749 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3750 SelectionDAG &DAG) const {
3751 // Jump table entries as PC relative offsets. No additional tweaking
3752 // is necessary here. Just get the address of the jump table.
3753 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3754 EVT PtrVT = getPointerTy();
3757 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3758 !Subtarget->isTargetMachO()) {
3759 const unsigned char MO_NC = AArch64II::MO_NC;
3761 AArch64ISD::WrapperLarge, DL, PtrVT,
3762 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3763 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3764 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3765 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3766 AArch64II::MO_G0 | MO_NC));
3770 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3771 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3772 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3773 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3774 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3777 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3778 SelectionDAG &DAG) const {
3779 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3780 EVT PtrVT = getPointerTy();
3783 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3784 // Use the GOT for the large code model on iOS.
3785 if (Subtarget->isTargetMachO()) {
3786 SDValue GotAddr = DAG.getTargetConstantPool(
3787 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3789 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3792 const unsigned char MO_NC = AArch64II::MO_NC;
3794 AArch64ISD::WrapperLarge, DL, PtrVT,
3795 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3796 CP->getOffset(), AArch64II::MO_G3),
3797 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3798 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3799 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3800 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3801 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3802 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3804 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3805 // ELF, the only valid one on Darwin.
3807 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3808 CP->getOffset(), AArch64II::MO_PAGE);
3809 SDValue Lo = DAG.getTargetConstantPool(
3810 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3811 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3813 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3814 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3818 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3819 SelectionDAG &DAG) const {
3820 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3821 EVT PtrVT = getPointerTy();
3823 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3824 !Subtarget->isTargetMachO()) {
3825 const unsigned char MO_NC = AArch64II::MO_NC;
3827 AArch64ISD::WrapperLarge, DL, PtrVT,
3828 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3829 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3830 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3831 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3833 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3834 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3836 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3837 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3841 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3842 SelectionDAG &DAG) const {
3843 AArch64FunctionInfo *FuncInfo =
3844 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3848 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3849 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3850 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3851 MachinePointerInfo(SV), false, false, 0);
3854 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3855 SelectionDAG &DAG) const {
3856 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3857 // Standard, section B.3.
3858 MachineFunction &MF = DAG.getMachineFunction();
3859 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3862 SDValue Chain = Op.getOperand(0);
3863 SDValue VAList = Op.getOperand(1);
3864 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3865 SmallVector<SDValue, 4> MemOps;
3867 // void *__stack at offset 0
3869 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3870 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3871 MachinePointerInfo(SV), false, false, 8));
3873 // void *__gr_top at offset 8
3874 int GPRSize = FuncInfo->getVarArgsGPRSize();
3876 SDValue GRTop, GRTopAddr;
3878 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3879 DAG.getConstant(8, getPointerTy()));
3881 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3882 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3883 DAG.getConstant(GPRSize, getPointerTy()));
3885 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3886 MachinePointerInfo(SV, 8), false, false, 8));
3889 // void *__vr_top at offset 16
3890 int FPRSize = FuncInfo->getVarArgsFPRSize();
3892 SDValue VRTop, VRTopAddr;
3893 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3894 DAG.getConstant(16, getPointerTy()));
3896 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3897 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3898 DAG.getConstant(FPRSize, getPointerTy()));
3900 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3901 MachinePointerInfo(SV, 16), false, false, 8));
3904 // int __gr_offs at offset 24
3905 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3906 DAG.getConstant(24, getPointerTy()));
3907 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3908 GROffsAddr, MachinePointerInfo(SV, 24), false,
3911 // int __vr_offs at offset 28
3912 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3913 DAG.getConstant(28, getPointerTy()));
3914 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3915 VROffsAddr, MachinePointerInfo(SV, 28), false,
3918 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3921 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3922 SelectionDAG &DAG) const {
3923 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3924 : LowerAAPCS_VASTART(Op, DAG);
3927 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3928 SelectionDAG &DAG) const {
3929 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3931 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3932 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3933 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3935 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3936 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3937 8, false, false, MachinePointerInfo(DestSV),
3938 MachinePointerInfo(SrcSV));
3941 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3942 assert(Subtarget->isTargetDarwin() &&
3943 "automatic va_arg instruction only works on Darwin");
3945 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3946 EVT VT = Op.getValueType();
3948 SDValue Chain = Op.getOperand(0);
3949 SDValue Addr = Op.getOperand(1);
3950 unsigned Align = Op.getConstantOperandVal(3);
3952 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3953 MachinePointerInfo(V), false, false, false, 0);
3954 Chain = VAList.getValue(1);
3957 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3958 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3959 DAG.getConstant(Align - 1, getPointerTy()));
3960 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3961 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3964 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3965 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3967 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3968 // up to 64 bits. At the very least, we have to increase the striding of the
3969 // vaargs list to match this, and for FP values we need to introduce
3970 // FP_ROUND nodes as well.
3971 if (VT.isInteger() && !VT.isVector())
3973 bool NeedFPTrunc = false;
3974 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3979 // Increment the pointer, VAList, to the next vaarg
3980 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3981 DAG.getConstant(ArgSize, getPointerTy()));
3982 // Store the incremented VAList to the legalized pointer
3983 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3986 // Load the actual argument out of the pointer VAList
3988 // Load the value as an f64.
3989 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3990 MachinePointerInfo(), false, false, false, 0);
3991 // Round the value down to an f32.
3992 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3993 DAG.getIntPtrConstant(1));
3994 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3995 // Merge the rounded value with the chain output of the load.
3996 return DAG.getMergeValues(Ops, DL);
3999 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4003 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4004 SelectionDAG &DAG) const {
4005 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4006 MFI->setFrameAddressIsTaken(true);
4008 EVT VT = Op.getValueType();
4010 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4012 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4014 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4015 MachinePointerInfo(), false, false, false, 0);
4019 // FIXME? Maybe this could be a TableGen attribute on some registers and
4020 // this table could be generated automatically from RegInfo.
4021 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4023 unsigned Reg = StringSwitch<unsigned>(RegName)
4024 .Case("sp", AArch64::SP)
4028 report_fatal_error("Invalid register name global variable");
4031 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4032 SelectionDAG &DAG) const {
4033 MachineFunction &MF = DAG.getMachineFunction();
4034 MachineFrameInfo *MFI = MF.getFrameInfo();
4035 MFI->setReturnAddressIsTaken(true);
4037 EVT VT = Op.getValueType();
4039 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4041 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4042 SDValue Offset = DAG.getConstant(8, getPointerTy());
4043 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4044 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4045 MachinePointerInfo(), false, false, false, 0);
4048 // Return LR, which contains the return address. Mark it an implicit live-in.
4049 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4050 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4053 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4054 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4055 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4056 SelectionDAG &DAG) const {
4057 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4058 EVT VT = Op.getValueType();
4059 unsigned VTBits = VT.getSizeInBits();
4061 SDValue ShOpLo = Op.getOperand(0);
4062 SDValue ShOpHi = Op.getOperand(1);
4063 SDValue ShAmt = Op.getOperand(2);
4065 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4067 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4069 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4070 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4071 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4072 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4073 DAG.getConstant(VTBits, MVT::i64));
4074 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4076 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4077 ISD::SETGE, dl, DAG);
4078 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4080 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4081 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4083 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4085 // AArch64 shifts larger than the register width are wrapped rather than
4086 // clamped, so we can't just emit "hi >> x".
4087 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4088 SDValue TrueValHi = Opc == ISD::SRA
4089 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4090 DAG.getConstant(VTBits - 1, MVT::i64))
4091 : DAG.getConstant(0, VT);
4093 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4095 SDValue Ops[2] = { Lo, Hi };
4096 return DAG.getMergeValues(Ops, dl);
4099 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4100 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4101 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4102 SelectionDAG &DAG) const {
4103 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4104 EVT VT = Op.getValueType();
4105 unsigned VTBits = VT.getSizeInBits();
4107 SDValue ShOpLo = Op.getOperand(0);
4108 SDValue ShOpHi = Op.getOperand(1);
4109 SDValue ShAmt = Op.getOperand(2);
4112 assert(Op.getOpcode() == ISD::SHL_PARTS);
4113 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4114 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4115 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4116 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4117 DAG.getConstant(VTBits, MVT::i64));
4118 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4119 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4121 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4123 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4124 ISD::SETGE, dl, DAG);
4125 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4127 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4129 // AArch64 shifts of larger than register sizes are wrapped rather than
4130 // clamped, so we can't just emit "lo << a" if a is too big.
4131 SDValue TrueValLo = DAG.getConstant(0, VT);
4132 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4134 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4136 SDValue Ops[2] = { Lo, Hi };
4137 return DAG.getMergeValues(Ops, dl);
4140 bool AArch64TargetLowering::isOffsetFoldingLegal(
4141 const GlobalAddressSDNode *GA) const {
4142 // The AArch64 target doesn't support folding offsets into global addresses.
4146 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4147 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4148 // FIXME: We should be able to handle f128 as well with a clever lowering.
4149 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4153 return AArch64_AM::getFP64Imm(Imm) != -1;
4154 else if (VT == MVT::f32)
4155 return AArch64_AM::getFP32Imm(Imm) != -1;
4159 //===----------------------------------------------------------------------===//
4160 // AArch64 Optimization Hooks
4161 //===----------------------------------------------------------------------===//
4163 //===----------------------------------------------------------------------===//
4164 // AArch64 Inline Assembly Support
4165 //===----------------------------------------------------------------------===//
4167 // Table of Constraints
4168 // TODO: This is the current set of constraints supported by ARM for the
4169 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4171 // r - A general register
4172 // w - An FP/SIMD register of some size in the range v0-v31
4173 // x - An FP/SIMD register of some size in the range v0-v15
4174 // I - Constant that can be used with an ADD instruction
4175 // J - Constant that can be used with a SUB instruction
4176 // K - Constant that can be used with a 32-bit logical instruction
4177 // L - Constant that can be used with a 64-bit logical instruction
4178 // M - Constant that can be used as a 32-bit MOV immediate
4179 // N - Constant that can be used as a 64-bit MOV immediate
4180 // Q - A memory reference with base register and no offset
4181 // S - A symbolic address
4182 // Y - Floating point constant zero
4183 // Z - Integer constant zero
4185 // Note that general register operands will be output using their 64-bit x
4186 // register name, whatever the size of the variable, unless the asm operand
4187 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4188 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4191 /// getConstraintType - Given a constraint letter, return the type of
4192 /// constraint it is for this target.
4193 AArch64TargetLowering::ConstraintType
4194 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4195 if (Constraint.size() == 1) {
4196 switch (Constraint[0]) {
4203 return C_RegisterClass;
4204 // An address with a single base register. Due to the way we
4205 // currently handle addresses it is the same as 'r'.
4210 return TargetLowering::getConstraintType(Constraint);
4213 /// Examine constraint type and operand type and determine a weight value.
4214 /// This object must already have been set up with the operand type
4215 /// and the current alternative constraint selected.
4216 TargetLowering::ConstraintWeight
4217 AArch64TargetLowering::getSingleConstraintMatchWeight(
4218 AsmOperandInfo &info, const char *constraint) const {
4219 ConstraintWeight weight = CW_Invalid;
4220 Value *CallOperandVal = info.CallOperandVal;
4221 // If we don't have a value, we can't do a match,
4222 // but allow it at the lowest weight.
4223 if (!CallOperandVal)
4225 Type *type = CallOperandVal->getType();
4226 // Look at the constraint type.
4227 switch (*constraint) {
4229 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4233 if (type->isFloatingPointTy() || type->isVectorTy())
4234 weight = CW_Register;
4237 weight = CW_Constant;
4243 std::pair<unsigned, const TargetRegisterClass *>
4244 AArch64TargetLowering::getRegForInlineAsmConstraint(
4245 const TargetRegisterInfo *TRI, const std::string &Constraint,
4247 if (Constraint.size() == 1) {
4248 switch (Constraint[0]) {
4250 if (VT.getSizeInBits() == 64)
4251 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4252 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4255 return std::make_pair(0U, &AArch64::FPR32RegClass);
4256 if (VT.getSizeInBits() == 64)
4257 return std::make_pair(0U, &AArch64::FPR64RegClass);
4258 if (VT.getSizeInBits() == 128)
4259 return std::make_pair(0U, &AArch64::FPR128RegClass);
4261 // The instructions that this constraint is designed for can
4262 // only take 128-bit registers so just use that regclass.
4264 if (VT.getSizeInBits() == 128)
4265 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4269 if (StringRef("{cc}").equals_lower(Constraint))
4270 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4272 // Use the default implementation in TargetLowering to convert the register
4273 // constraint into a member of a register class.
4274 std::pair<unsigned, const TargetRegisterClass *> Res;
4275 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4277 // Not found as a standard register?
4279 unsigned Size = Constraint.size();
4280 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4281 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4282 const std::string Reg =
4283 std::string(&Constraint[2], &Constraint[Size - 1]);
4284 int RegNo = atoi(Reg.c_str());
4285 if (RegNo >= 0 && RegNo <= 31) {
4286 // v0 - v31 are aliases of q0 - q31.
4287 // By default we'll emit v0-v31 for this unless there's a modifier where
4288 // we'll emit the correct register as well.
4289 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4290 Res.second = &AArch64::FPR128RegClass;
4298 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4299 /// vector. If it is invalid, don't add anything to Ops.
4300 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4301 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4302 SelectionDAG &DAG) const {
4305 // Currently only support length 1 constraints.
4306 if (Constraint.length() != 1)
4309 char ConstraintLetter = Constraint[0];
4310 switch (ConstraintLetter) {
4314 // This set of constraints deal with valid constants for various instructions.
4315 // Validate and return a target constant for them if we can.
4317 // 'z' maps to xzr or wzr so it needs an input of 0.
4318 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4319 if (!C || C->getZExtValue() != 0)
4322 if (Op.getValueType() == MVT::i64)
4323 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4325 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4335 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4339 // Grab the value and do some validation.
4340 uint64_t CVal = C->getZExtValue();
4341 switch (ConstraintLetter) {
4342 // The I constraint applies only to simple ADD or SUB immediate operands:
4343 // i.e. 0 to 4095 with optional shift by 12
4344 // The J constraint applies only to ADD or SUB immediates that would be
4345 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4346 // instruction [or vice versa], in other words -1 to -4095 with optional
4347 // left shift by 12.
4349 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4353 uint64_t NVal = -C->getSExtValue();
4354 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4355 CVal = C->getSExtValue();
4360 // The K and L constraints apply *only* to logical immediates, including
4361 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4362 // been removed and MOV should be used). So these constraints have to
4363 // distinguish between bit patterns that are valid 32-bit or 64-bit
4364 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4365 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4368 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4372 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4375 // The M and N constraints are a superset of K and L respectively, for use
4376 // with the MOV (immediate) alias. As well as the logical immediates they
4377 // also match 32 or 64-bit immediates that can be loaded either using a
4378 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4379 // (M) or 64-bit 0x1234000000000000 (N) etc.
4380 // As a note some of this code is liberally stolen from the asm parser.
4382 if (!isUInt<32>(CVal))
4384 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4386 if ((CVal & 0xFFFF) == CVal)
4388 if ((CVal & 0xFFFF0000ULL) == CVal)
4390 uint64_t NCVal = ~(uint32_t)CVal;
4391 if ((NCVal & 0xFFFFULL) == NCVal)
4393 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4398 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4400 if ((CVal & 0xFFFFULL) == CVal)
4402 if ((CVal & 0xFFFF0000ULL) == CVal)
4404 if ((CVal & 0xFFFF00000000ULL) == CVal)
4406 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4408 uint64_t NCVal = ~CVal;
4409 if ((NCVal & 0xFFFFULL) == NCVal)
4411 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4413 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4415 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4423 // All assembler immediates are 64-bit integers.
4424 Result = DAG.getTargetConstant(CVal, MVT::i64);
4428 if (Result.getNode()) {
4429 Ops.push_back(Result);
4433 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4436 //===----------------------------------------------------------------------===//
4437 // AArch64 Advanced SIMD Support
4438 //===----------------------------------------------------------------------===//
4440 /// WidenVector - Given a value in the V64 register class, produce the
4441 /// equivalent value in the V128 register class.
4442 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4443 EVT VT = V64Reg.getValueType();
4444 unsigned NarrowSize = VT.getVectorNumElements();
4445 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4446 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4449 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4450 V64Reg, DAG.getConstant(0, MVT::i32));
4453 /// getExtFactor - Determine the adjustment factor for the position when
4454 /// generating an "extract from vector registers" instruction.
4455 static unsigned getExtFactor(SDValue &V) {
4456 EVT EltType = V.getValueType().getVectorElementType();
4457 return EltType.getSizeInBits() / 8;
4460 /// NarrowVector - Given a value in the V128 register class, produce the
4461 /// equivalent value in the V64 register class.
4462 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4463 EVT VT = V128Reg.getValueType();
4464 unsigned WideSize = VT.getVectorNumElements();
4465 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4466 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4469 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4472 // Gather data to see if the operation can be modelled as a
4473 // shuffle in combination with VEXTs.
4474 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4475 SelectionDAG &DAG) const {
4476 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4478 EVT VT = Op.getValueType();
4479 unsigned NumElts = VT.getVectorNumElements();
4481 struct ShuffleSourceInfo {
4486 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4487 // be compatible with the shuffle we intend to construct. As a result
4488 // ShuffleVec will be some sliding window into the original Vec.
4491 // Code should guarantee that element i in Vec starts at element "WindowBase
4492 // + i * WindowScale in ShuffleVec".
4496 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4497 ShuffleSourceInfo(SDValue Vec)
4498 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4502 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4504 SmallVector<ShuffleSourceInfo, 2> Sources;
4505 for (unsigned i = 0; i < NumElts; ++i) {
4506 SDValue V = Op.getOperand(i);
4507 if (V.getOpcode() == ISD::UNDEF)
4509 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4510 // A shuffle can only come from building a vector from various
4511 // elements of other vectors.
4515 // Add this element source to the list if it's not already there.
4516 SDValue SourceVec = V.getOperand(0);
4517 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4518 if (Source == Sources.end())
4519 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4521 // Update the minimum and maximum lane number seen.
4522 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4523 Source->MinElt = std::min(Source->MinElt, EltNo);
4524 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4527 // Currently only do something sane when at most two source vectors
4529 if (Sources.size() > 2)
4532 // Find out the smallest element size among result and two sources, and use
4533 // it as element size to build the shuffle_vector.
4534 EVT SmallestEltTy = VT.getVectorElementType();
4535 for (auto &Source : Sources) {
4536 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4537 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4538 SmallestEltTy = SrcEltTy;
4541 unsigned ResMultiplier =
4542 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4543 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4544 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4546 // If the source vector is too wide or too narrow, we may nevertheless be able
4547 // to construct a compatible shuffle either by concatenating it with UNDEF or
4548 // extracting a suitable range of elements.
4549 for (auto &Src : Sources) {
4550 EVT SrcVT = Src.ShuffleVec.getValueType();
4552 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4555 // This stage of the search produces a source with the same element type as
4556 // the original, but with a total width matching the BUILD_VECTOR output.
4557 EVT EltVT = SrcVT.getVectorElementType();
4558 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4559 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4561 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4562 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4563 // We can pad out the smaller vector for free, so if it's part of a
4566 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4567 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4571 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4573 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4574 // Span too large for a VEXT to cope
4578 if (Src.MinElt >= NumSrcElts) {
4579 // The extraction can just take the second half
4581 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4582 DAG.getConstant(NumSrcElts, MVT::i64));
4583 Src.WindowBase = -NumSrcElts;
4584 } else if (Src.MaxElt < NumSrcElts) {
4585 // The extraction can just take the first half
4587 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4588 DAG.getConstant(0, MVT::i64));
4590 // An actual VEXT is needed
4592 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4593 DAG.getConstant(0, MVT::i64));
4595 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4596 DAG.getConstant(NumSrcElts, MVT::i64));
4597 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4599 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4600 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4601 Src.WindowBase = -Src.MinElt;
4605 // Another possible incompatibility occurs from the vector element types. We
4606 // can fix this by bitcasting the source vectors to the same type we intend
4608 for (auto &Src : Sources) {
4609 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4610 if (SrcEltTy == SmallestEltTy)
4612 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4613 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4614 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4615 Src.WindowBase *= Src.WindowScale;
4618 // Final sanity check before we try to actually produce a shuffle.
4620 for (auto Src : Sources)
4621 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4624 // The stars all align, our next step is to produce the mask for the shuffle.
4625 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4626 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4627 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4628 SDValue Entry = Op.getOperand(i);
4629 if (Entry.getOpcode() == ISD::UNDEF)
4632 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4633 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4635 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4636 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4638 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4639 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4640 VT.getVectorElementType().getSizeInBits());
4641 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4643 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4644 // starting at the appropriate offset.
4645 int *LaneMask = &Mask[i * ResMultiplier];
4647 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4648 ExtractBase += NumElts * (Src - Sources.begin());
4649 for (int j = 0; j < LanesDefined; ++j)
4650 LaneMask[j] = ExtractBase + j;
4653 // Final check before we try to produce nonsense...
4654 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4657 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4658 for (unsigned i = 0; i < Sources.size(); ++i)
4659 ShuffleOps[i] = Sources[i].ShuffleVec;
4661 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4662 ShuffleOps[1], &Mask[0]);
4663 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4666 // check if an EXT instruction can handle the shuffle mask when the
4667 // vector sources of the shuffle are the same.
4668 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4669 unsigned NumElts = VT.getVectorNumElements();
4671 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4677 // If this is a VEXT shuffle, the immediate value is the index of the first
4678 // element. The other shuffle indices must be the successive elements after
4680 unsigned ExpectedElt = Imm;
4681 for (unsigned i = 1; i < NumElts; ++i) {
4682 // Increment the expected index. If it wraps around, just follow it
4683 // back to index zero and keep going.
4685 if (ExpectedElt == NumElts)
4689 continue; // ignore UNDEF indices
4690 if (ExpectedElt != static_cast<unsigned>(M[i]))
4697 // check if an EXT instruction can handle the shuffle mask when the
4698 // vector sources of the shuffle are different.
4699 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4701 // Look for the first non-undef element.
4702 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4703 [](int Elt) {return Elt >= 0;});
4705 // Benefit form APInt to handle overflow when calculating expected element.
4706 unsigned NumElts = VT.getVectorNumElements();
4707 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4708 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4709 // The following shuffle indices must be the successive elements after the
4710 // first real element.
4711 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4712 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4713 if (FirstWrongElt != M.end())
4716 // The index of an EXT is the first element if it is not UNDEF.
4717 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4718 // value of the first element. E.g.
4719 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4720 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4721 // ExpectedElt is the last mask index plus 1.
4722 Imm = ExpectedElt.getZExtValue();
4724 // There are two difference cases requiring to reverse input vectors.
4725 // For example, for vector <4 x i32> we have the following cases,
4726 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4727 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4728 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4729 // to reverse two input vectors.
4738 /// isREVMask - Check if a vector shuffle corresponds to a REV
4739 /// instruction with the specified blocksize. (The order of the elements
4740 /// within each block of the vector is reversed.)
4741 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4742 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4743 "Only possible block sizes for REV are: 16, 32, 64");
4745 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4749 unsigned NumElts = VT.getVectorNumElements();
4750 unsigned BlockElts = M[0] + 1;
4751 // If the first shuffle index is UNDEF, be optimistic.
4753 BlockElts = BlockSize / EltSz;
4755 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4758 for (unsigned i = 0; i < NumElts; ++i) {
4760 continue; // ignore UNDEF indices
4761 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4768 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4769 unsigned NumElts = VT.getVectorNumElements();
4770 WhichResult = (M[0] == 0 ? 0 : 1);
4771 unsigned Idx = WhichResult * NumElts / 2;
4772 for (unsigned i = 0; i != NumElts; i += 2) {
4773 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4774 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4782 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4783 unsigned NumElts = VT.getVectorNumElements();
4784 WhichResult = (M[0] == 0 ? 0 : 1);
4785 for (unsigned i = 0; i != NumElts; ++i) {
4787 continue; // ignore UNDEF indices
4788 if ((unsigned)M[i] != 2 * i + WhichResult)
4795 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4796 unsigned NumElts = VT.getVectorNumElements();
4797 WhichResult = (M[0] == 0 ? 0 : 1);
4798 for (unsigned i = 0; i < NumElts; i += 2) {
4799 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4800 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4806 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4807 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4808 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4809 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4810 unsigned NumElts = VT.getVectorNumElements();
4811 WhichResult = (M[0] == 0 ? 0 : 1);
4812 unsigned Idx = WhichResult * NumElts / 2;
4813 for (unsigned i = 0; i != NumElts; i += 2) {
4814 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4815 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4823 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4824 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4825 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4826 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4827 unsigned Half = VT.getVectorNumElements() / 2;
4828 WhichResult = (M[0] == 0 ? 0 : 1);
4829 for (unsigned j = 0; j != 2; ++j) {
4830 unsigned Idx = WhichResult;
4831 for (unsigned i = 0; i != Half; ++i) {
4832 int MIdx = M[i + j * Half];
4833 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4842 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4843 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4844 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4845 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4846 unsigned NumElts = VT.getVectorNumElements();
4847 WhichResult = (M[0] == 0 ? 0 : 1);
4848 for (unsigned i = 0; i < NumElts; i += 2) {
4849 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4850 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4856 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4857 bool &DstIsLeft, int &Anomaly) {
4858 if (M.size() != static_cast<size_t>(NumInputElements))
4861 int NumLHSMatch = 0, NumRHSMatch = 0;
4862 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4864 for (int i = 0; i < NumInputElements; ++i) {
4874 LastLHSMismatch = i;
4876 if (M[i] == i + NumInputElements)
4879 LastRHSMismatch = i;
4882 if (NumLHSMatch == NumInputElements - 1) {
4884 Anomaly = LastLHSMismatch;
4886 } else if (NumRHSMatch == NumInputElements - 1) {
4888 Anomaly = LastRHSMismatch;
4895 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4896 if (VT.getSizeInBits() != 128)
4899 unsigned NumElts = VT.getVectorNumElements();
4901 for (int I = 0, E = NumElts / 2; I != E; I++) {
4906 int Offset = NumElts / 2;
4907 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4908 if (Mask[I] != I + SplitLHS * Offset)
4915 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4917 EVT VT = Op.getValueType();
4918 SDValue V0 = Op.getOperand(0);
4919 SDValue V1 = Op.getOperand(1);
4920 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4922 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4923 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4926 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4928 if (!isConcatMask(Mask, VT, SplitV0))
4931 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4932 VT.getVectorNumElements() / 2);
4934 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4935 DAG.getConstant(0, MVT::i64));
4937 if (V1.getValueType().getSizeInBits() == 128) {
4938 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4939 DAG.getConstant(0, MVT::i64));
4941 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4944 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4945 /// the specified operations to build the shuffle.
4946 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4947 SDValue RHS, SelectionDAG &DAG,
4949 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4950 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4951 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4954 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4963 OP_VUZPL, // VUZP, left result
4964 OP_VUZPR, // VUZP, right result
4965 OP_VZIPL, // VZIP, left result
4966 OP_VZIPR, // VZIP, right result
4967 OP_VTRNL, // VTRN, left result
4968 OP_VTRNR // VTRN, right result
4971 if (OpNum == OP_COPY) {
4972 if (LHSID == (1 * 9 + 2) * 9 + 3)
4974 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4978 SDValue OpLHS, OpRHS;
4979 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4980 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4981 EVT VT = OpLHS.getValueType();
4985 llvm_unreachable("Unknown shuffle opcode!");
4987 // VREV divides the vector in half and swaps within the half.
4988 if (VT.getVectorElementType() == MVT::i32 ||
4989 VT.getVectorElementType() == MVT::f32)
4990 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4991 // vrev <4 x i16> -> REV32
4992 if (VT.getVectorElementType() == MVT::i16 ||
4993 VT.getVectorElementType() == MVT::f16)
4994 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4995 // vrev <4 x i8> -> REV16
4996 assert(VT.getVectorElementType() == MVT::i8);
4997 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5002 EVT EltTy = VT.getVectorElementType();
5004 if (EltTy == MVT::i8)
5005 Opcode = AArch64ISD::DUPLANE8;
5006 else if (EltTy == MVT::i16)
5007 Opcode = AArch64ISD::DUPLANE16;
5008 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5009 Opcode = AArch64ISD::DUPLANE32;
5010 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5011 Opcode = AArch64ISD::DUPLANE64;
5013 llvm_unreachable("Invalid vector element type?");
5015 if (VT.getSizeInBits() == 64)
5016 OpLHS = WidenVector(OpLHS, DAG);
5017 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5018 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5023 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5024 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5025 DAG.getConstant(Imm, MVT::i32));
5028 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5031 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5034 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5037 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5040 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5043 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5048 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5049 SelectionDAG &DAG) {
5050 // Check to see if we can use the TBL instruction.
5051 SDValue V1 = Op.getOperand(0);
5052 SDValue V2 = Op.getOperand(1);
5055 EVT EltVT = Op.getValueType().getVectorElementType();
5056 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5058 SmallVector<SDValue, 8> TBLMask;
5059 for (int Val : ShuffleMask) {
5060 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5061 unsigned Offset = Byte + Val * BytesPerElt;
5062 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5066 MVT IndexVT = MVT::v8i8;
5067 unsigned IndexLen = 8;
5068 if (Op.getValueType().getSizeInBits() == 128) {
5069 IndexVT = MVT::v16i8;
5073 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5074 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5077 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5079 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5080 Shuffle = DAG.getNode(
5081 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5082 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5083 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5084 makeArrayRef(TBLMask.data(), IndexLen)));
5086 if (IndexLen == 8) {
5087 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5088 Shuffle = DAG.getNode(
5089 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5090 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5091 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5092 makeArrayRef(TBLMask.data(), IndexLen)));
5094 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5095 // cannot currently represent the register constraints on the input
5097 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5098 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5099 // &TBLMask[0], IndexLen));
5100 Shuffle = DAG.getNode(
5101 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5102 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5103 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5104 makeArrayRef(TBLMask.data(), IndexLen)));
5107 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5110 static unsigned getDUPLANEOp(EVT EltType) {
5111 if (EltType == MVT::i8)
5112 return AArch64ISD::DUPLANE8;
5113 if (EltType == MVT::i16 || EltType == MVT::f16)
5114 return AArch64ISD::DUPLANE16;
5115 if (EltType == MVT::i32 || EltType == MVT::f32)
5116 return AArch64ISD::DUPLANE32;
5117 if (EltType == MVT::i64 || EltType == MVT::f64)
5118 return AArch64ISD::DUPLANE64;
5120 llvm_unreachable("Invalid vector element type?");
5123 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5124 SelectionDAG &DAG) const {
5126 EVT VT = Op.getValueType();
5128 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5130 // Convert shuffles that are directly supported on NEON to target-specific
5131 // DAG nodes, instead of keeping them as shuffles and matching them again
5132 // during code selection. This is more efficient and avoids the possibility
5133 // of inconsistencies between legalization and selection.
5134 ArrayRef<int> ShuffleMask = SVN->getMask();
5136 SDValue V1 = Op.getOperand(0);
5137 SDValue V2 = Op.getOperand(1);
5139 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5140 V1.getValueType().getSimpleVT())) {
5141 int Lane = SVN->getSplatIndex();
5142 // If this is undef splat, generate it via "just" vdup, if possible.
5146 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5147 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5149 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5150 // constant. If so, we can just reference the lane's definition directly.
5151 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5152 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5153 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5155 // Otherwise, duplicate from the lane of the input vector.
5156 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5158 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5159 // to make a vector of the same size as this SHUFFLE. We can ignore the
5160 // extract entirely, and canonicalise the concat using WidenVector.
5161 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5162 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5163 V1 = V1.getOperand(0);
5164 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5165 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5166 Lane -= Idx * VT.getVectorNumElements() / 2;
5167 V1 = WidenVector(V1.getOperand(Idx), DAG);
5168 } else if (VT.getSizeInBits() == 64)
5169 V1 = WidenVector(V1, DAG);
5171 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5174 if (isREVMask(ShuffleMask, VT, 64))
5175 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5176 if (isREVMask(ShuffleMask, VT, 32))
5177 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5178 if (isREVMask(ShuffleMask, VT, 16))
5179 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5181 bool ReverseEXT = false;
5183 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5186 Imm *= getExtFactor(V1);
5187 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5188 DAG.getConstant(Imm, MVT::i32));
5189 } else if (V2->getOpcode() == ISD::UNDEF &&
5190 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5191 Imm *= getExtFactor(V1);
5192 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5193 DAG.getConstant(Imm, MVT::i32));
5196 unsigned WhichResult;
5197 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5198 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5199 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5201 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5202 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5203 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5205 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5206 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5207 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5210 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5211 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5212 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5214 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5215 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5216 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5218 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5219 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5220 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5223 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5224 if (Concat.getNode())
5229 int NumInputElements = V1.getValueType().getVectorNumElements();
5230 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5231 SDValue DstVec = DstIsLeft ? V1 : V2;
5232 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5234 SDValue SrcVec = V1;
5235 int SrcLane = ShuffleMask[Anomaly];
5236 if (SrcLane >= NumInputElements) {
5238 SrcLane -= VT.getVectorNumElements();
5240 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5242 EVT ScalarVT = VT.getVectorElementType();
5244 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5245 ScalarVT = MVT::i32;
5248 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5249 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5253 // If the shuffle is not directly supported and it has 4 elements, use
5254 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5255 unsigned NumElts = VT.getVectorNumElements();
5257 unsigned PFIndexes[4];
5258 for (unsigned i = 0; i != 4; ++i) {
5259 if (ShuffleMask[i] < 0)
5262 PFIndexes[i] = ShuffleMask[i];
5265 // Compute the index in the perfect shuffle table.
5266 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5267 PFIndexes[2] * 9 + PFIndexes[3];
5268 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5269 unsigned Cost = (PFEntry >> 30);
5272 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5275 return GenerateTBL(Op, ShuffleMask, DAG);
5278 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5280 EVT VT = BVN->getValueType(0);
5281 APInt SplatBits, SplatUndef;
5282 unsigned SplatBitSize;
5284 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5285 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5287 for (unsigned i = 0; i < NumSplats; ++i) {
5288 CnstBits <<= SplatBitSize;
5289 UndefBits <<= SplatBitSize;
5290 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5291 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5300 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5301 SelectionDAG &DAG) const {
5302 BuildVectorSDNode *BVN =
5303 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5304 SDValue LHS = Op.getOperand(0);
5306 EVT VT = Op.getValueType();
5311 APInt CnstBits(VT.getSizeInBits(), 0);
5312 APInt UndefBits(VT.getSizeInBits(), 0);
5313 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5314 // We only have BIC vector immediate instruction, which is and-not.
5315 CnstBits = ~CnstBits;
5317 // We make use of a little bit of goto ickiness in order to avoid having to
5318 // duplicate the immediate matching logic for the undef toggled case.
5319 bool SecondTry = false;
5322 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5323 CnstBits = CnstBits.zextOrTrunc(64);
5324 uint64_t CnstVal = CnstBits.getZExtValue();
5326 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5327 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5328 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5329 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5330 DAG.getConstant(CnstVal, MVT::i32),
5331 DAG.getConstant(0, MVT::i32));
5332 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5335 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5336 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5337 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5338 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5339 DAG.getConstant(CnstVal, MVT::i32),
5340 DAG.getConstant(8, MVT::i32));
5341 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5344 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5345 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5346 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5347 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5348 DAG.getConstant(CnstVal, MVT::i32),
5349 DAG.getConstant(16, MVT::i32));
5350 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5353 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5354 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5355 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5356 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5357 DAG.getConstant(CnstVal, MVT::i32),
5358 DAG.getConstant(24, MVT::i32));
5359 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5362 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5363 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5364 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5365 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5366 DAG.getConstant(CnstVal, MVT::i32),
5367 DAG.getConstant(0, MVT::i32));
5368 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5371 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5372 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5373 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5374 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5375 DAG.getConstant(CnstVal, MVT::i32),
5376 DAG.getConstant(8, MVT::i32));
5377 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5384 CnstBits = ~UndefBits;
5388 // We can always fall back to a non-immediate AND.
5393 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5394 // consists of only the same constant int value, returned in reference arg
5396 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5397 uint64_t &ConstVal) {
5398 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5401 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5404 EVT VT = Bvec->getValueType(0);
5405 unsigned NumElts = VT.getVectorNumElements();
5406 for (unsigned i = 1; i < NumElts; ++i)
5407 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5409 ConstVal = FirstElt->getZExtValue();
5413 static unsigned getIntrinsicID(const SDNode *N) {
5414 unsigned Opcode = N->getOpcode();
5417 return Intrinsic::not_intrinsic;
5418 case ISD::INTRINSIC_WO_CHAIN: {
5419 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5420 if (IID < Intrinsic::num_intrinsics)
5422 return Intrinsic::not_intrinsic;
5427 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5428 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5429 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5430 // Also, logical shift right -> sri, with the same structure.
5431 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5432 EVT VT = N->getValueType(0);
5439 // Is the first op an AND?
5440 const SDValue And = N->getOperand(0);
5441 if (And.getOpcode() != ISD::AND)
5444 // Is the second op an shl or lshr?
5445 SDValue Shift = N->getOperand(1);
5446 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5447 // or AArch64ISD::VLSHR vector, #shift
5448 unsigned ShiftOpc = Shift.getOpcode();
5449 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5451 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5453 // Is the shift amount constant?
5454 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5458 // Is the and mask vector all constant?
5460 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5463 // Is C1 == ~C2, taking into account how much one can shift elements of a
5465 uint64_t C2 = C2node->getZExtValue();
5466 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5467 if (C2 > ElemSizeInBits)
5469 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5470 if ((C1 & ElemMask) != (~C2 & ElemMask))
5473 SDValue X = And.getOperand(0);
5474 SDValue Y = Shift.getOperand(0);
5477 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5479 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5480 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5482 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5483 DEBUG(N->dump(&DAG));
5484 DEBUG(dbgs() << "into: \n");
5485 DEBUG(ResultSLI->dump(&DAG));
5491 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5492 SelectionDAG &DAG) const {
5493 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5494 if (EnableAArch64SlrGeneration) {
5495 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5500 BuildVectorSDNode *BVN =
5501 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5502 SDValue LHS = Op.getOperand(1);
5504 EVT VT = Op.getValueType();
5506 // OR commutes, so try swapping the operands.
5508 LHS = Op.getOperand(0);
5509 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5514 APInt CnstBits(VT.getSizeInBits(), 0);
5515 APInt UndefBits(VT.getSizeInBits(), 0);
5516 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5517 // We make use of a little bit of goto ickiness in order to avoid having to
5518 // duplicate the immediate matching logic for the undef toggled case.
5519 bool SecondTry = false;
5522 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5523 CnstBits = CnstBits.zextOrTrunc(64);
5524 uint64_t CnstVal = CnstBits.getZExtValue();
5526 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5527 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5528 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5529 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5530 DAG.getConstant(CnstVal, MVT::i32),
5531 DAG.getConstant(0, MVT::i32));
5532 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5535 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5536 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5537 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5538 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5539 DAG.getConstant(CnstVal, MVT::i32),
5540 DAG.getConstant(8, MVT::i32));
5541 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5544 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5545 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5546 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5547 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5548 DAG.getConstant(CnstVal, MVT::i32),
5549 DAG.getConstant(16, MVT::i32));
5550 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5553 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5554 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5555 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5556 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5557 DAG.getConstant(CnstVal, MVT::i32),
5558 DAG.getConstant(24, MVT::i32));
5559 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5562 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5563 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5564 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5565 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5566 DAG.getConstant(CnstVal, MVT::i32),
5567 DAG.getConstant(0, MVT::i32));
5568 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5571 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5572 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5573 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5574 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5575 DAG.getConstant(CnstVal, MVT::i32),
5576 DAG.getConstant(8, MVT::i32));
5577 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5584 CnstBits = UndefBits;
5588 // We can always fall back to a non-immediate OR.
5593 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5594 // be truncated to fit element width.
5595 static SDValue NormalizeBuildVector(SDValue Op,
5596 SelectionDAG &DAG) {
5597 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5599 EVT VT = Op.getValueType();
5600 EVT EltTy= VT.getVectorElementType();
5602 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5605 SmallVector<SDValue, 16> Ops;
5606 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5607 SDValue Lane = Op.getOperand(I);
5608 if (Lane.getOpcode() == ISD::Constant) {
5609 APInt LowBits(EltTy.getSizeInBits(),
5610 cast<ConstantSDNode>(Lane)->getZExtValue());
5611 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5613 Ops.push_back(Lane);
5615 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5618 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5619 SelectionDAG &DAG) const {
5621 EVT VT = Op.getValueType();
5622 Op = NormalizeBuildVector(Op, DAG);
5623 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5625 APInt CnstBits(VT.getSizeInBits(), 0);
5626 APInt UndefBits(VT.getSizeInBits(), 0);
5627 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5628 // We make use of a little bit of goto ickiness in order to avoid having to
5629 // duplicate the immediate matching logic for the undef toggled case.
5630 bool SecondTry = false;
5633 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5634 CnstBits = CnstBits.zextOrTrunc(64);
5635 uint64_t CnstVal = CnstBits.getZExtValue();
5637 // Certain magic vector constants (used to express things like NOT
5638 // and NEG) are passed through unmodified. This allows codegen patterns
5639 // for these operations to match. Special-purpose patterns will lower
5640 // these immediates to MOVIs if it proves necessary.
5641 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5644 // The many faces of MOVI...
5645 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5646 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5647 if (VT.getSizeInBits() == 128) {
5648 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5649 DAG.getConstant(CnstVal, MVT::i32));
5650 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5653 // Support the V64 version via subregister insertion.
5654 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5655 DAG.getConstant(CnstVal, MVT::i32));
5656 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5659 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5660 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5661 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5662 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5663 DAG.getConstant(CnstVal, MVT::i32),
5664 DAG.getConstant(0, MVT::i32));
5665 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5668 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5669 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5670 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5671 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5672 DAG.getConstant(CnstVal, MVT::i32),
5673 DAG.getConstant(8, MVT::i32));
5674 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5677 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5678 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5679 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5680 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5681 DAG.getConstant(CnstVal, MVT::i32),
5682 DAG.getConstant(16, MVT::i32));
5683 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5686 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5687 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5688 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5689 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5690 DAG.getConstant(CnstVal, MVT::i32),
5691 DAG.getConstant(24, MVT::i32));
5692 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5695 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5696 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5697 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5698 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5699 DAG.getConstant(CnstVal, MVT::i32),
5700 DAG.getConstant(0, MVT::i32));
5701 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5704 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5705 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5706 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5707 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5708 DAG.getConstant(CnstVal, MVT::i32),
5709 DAG.getConstant(8, MVT::i32));
5710 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5713 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5714 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5715 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5716 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5717 DAG.getConstant(CnstVal, MVT::i32),
5718 DAG.getConstant(264, MVT::i32));
5719 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5722 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5723 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5724 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5725 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5726 DAG.getConstant(CnstVal, MVT::i32),
5727 DAG.getConstant(272, MVT::i32));
5728 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5731 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5732 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5733 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5734 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5735 DAG.getConstant(CnstVal, MVT::i32));
5736 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5739 // The few faces of FMOV...
5740 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5741 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5742 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5743 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5744 DAG.getConstant(CnstVal, MVT::i32));
5745 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5748 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5749 VT.getSizeInBits() == 128) {
5750 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5751 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5752 DAG.getConstant(CnstVal, MVT::i32));
5753 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5756 // The many faces of MVNI...
5758 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5759 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5760 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5761 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5762 DAG.getConstant(CnstVal, MVT::i32),
5763 DAG.getConstant(0, MVT::i32));
5764 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5767 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5768 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5769 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5770 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5771 DAG.getConstant(CnstVal, MVT::i32),
5772 DAG.getConstant(8, MVT::i32));
5773 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5776 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5777 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5778 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5779 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5780 DAG.getConstant(CnstVal, MVT::i32),
5781 DAG.getConstant(16, MVT::i32));
5782 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5785 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5786 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5787 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5788 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5789 DAG.getConstant(CnstVal, MVT::i32),
5790 DAG.getConstant(24, MVT::i32));
5791 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5794 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5795 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5796 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5797 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5798 DAG.getConstant(CnstVal, MVT::i32),
5799 DAG.getConstant(0, MVT::i32));
5800 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5803 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5804 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5805 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5806 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5807 DAG.getConstant(CnstVal, MVT::i32),
5808 DAG.getConstant(8, MVT::i32));
5809 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5812 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5813 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5814 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5815 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5816 DAG.getConstant(CnstVal, MVT::i32),
5817 DAG.getConstant(264, MVT::i32));
5818 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5821 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5822 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5823 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5824 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5825 DAG.getConstant(CnstVal, MVT::i32),
5826 DAG.getConstant(272, MVT::i32));
5827 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5834 CnstBits = UndefBits;
5839 // Scan through the operands to find some interesting properties we can
5841 // 1) If only one value is used, we can use a DUP, or
5842 // 2) if only the low element is not undef, we can just insert that, or
5843 // 3) if only one constant value is used (w/ some non-constant lanes),
5844 // we can splat the constant value into the whole vector then fill
5845 // in the non-constant lanes.
5846 // 4) FIXME: If different constant values are used, but we can intelligently
5847 // select the values we'll be overwriting for the non-constant
5848 // lanes such that we can directly materialize the vector
5849 // some other way (MOVI, e.g.), we can be sneaky.
5850 unsigned NumElts = VT.getVectorNumElements();
5851 bool isOnlyLowElement = true;
5852 bool usesOnlyOneValue = true;
5853 bool usesOnlyOneConstantValue = true;
5854 bool isConstant = true;
5855 unsigned NumConstantLanes = 0;
5857 SDValue ConstantValue;
5858 for (unsigned i = 0; i < NumElts; ++i) {
5859 SDValue V = Op.getOperand(i);
5860 if (V.getOpcode() == ISD::UNDEF)
5863 isOnlyLowElement = false;
5864 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5867 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5869 if (!ConstantValue.getNode())
5871 else if (ConstantValue != V)
5872 usesOnlyOneConstantValue = false;
5875 if (!Value.getNode())
5877 else if (V != Value)
5878 usesOnlyOneValue = false;
5881 if (!Value.getNode())
5882 return DAG.getUNDEF(VT);
5884 if (isOnlyLowElement)
5885 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5887 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5888 // i32 and try again.
5889 if (usesOnlyOneValue) {
5891 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5892 Value.getValueType() != VT)
5893 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5895 // This is actually a DUPLANExx operation, which keeps everything vectory.
5897 // DUPLANE works on 128-bit vectors, widen it if necessary.
5898 SDValue Lane = Value.getOperand(1);
5899 Value = Value.getOperand(0);
5900 if (Value.getValueType().getSizeInBits() == 64)
5901 Value = WidenVector(Value, DAG);
5903 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5904 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5907 if (VT.getVectorElementType().isFloatingPoint()) {
5908 SmallVector<SDValue, 8> Ops;
5909 EVT EltTy = VT.getVectorElementType();
5910 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5911 "Unsupported floating-point vector type");
5912 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5913 for (unsigned i = 0; i < NumElts; ++i)
5914 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5915 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5916 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5917 Val = LowerBUILD_VECTOR(Val, DAG);
5919 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5923 // If there was only one constant value used and for more than one lane,
5924 // start by splatting that value, then replace the non-constant lanes. This
5925 // is better than the default, which will perform a separate initialization
5927 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5928 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5929 // Now insert the non-constant lanes.
5930 for (unsigned i = 0; i < NumElts; ++i) {
5931 SDValue V = Op.getOperand(i);
5932 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5933 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5934 // Note that type legalization likely mucked about with the VT of the
5935 // source operand, so we may have to convert it here before inserting.
5936 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5942 // If all elements are constants and the case above didn't get hit, fall back
5943 // to the default expansion, which will generate a load from the constant
5948 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5950 SDValue shuffle = ReconstructShuffle(Op, DAG);
5951 if (shuffle != SDValue())
5955 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5956 // know the default expansion would otherwise fall back on something even
5957 // worse. For a vector with one or two non-undef values, that's
5958 // scalar_to_vector for the elements followed by a shuffle (provided the
5959 // shuffle is valid for the target) and materialization element by element
5960 // on the stack followed by a load for everything else.
5961 if (!isConstant && !usesOnlyOneValue) {
5962 SDValue Vec = DAG.getUNDEF(VT);
5963 SDValue Op0 = Op.getOperand(0);
5964 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5966 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5967 // a) Avoid a RMW dependency on the full vector register, and
5968 // b) Allow the register coalescer to fold away the copy if the
5969 // value is already in an S or D register.
5970 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5971 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5973 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5974 DAG.getTargetConstant(SubIdx, MVT::i32));
5975 Vec = SDValue(N, 0);
5978 for (; i < NumElts; ++i) {
5979 SDValue V = Op.getOperand(i);
5980 if (V.getOpcode() == ISD::UNDEF)
5982 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5983 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5988 // Just use the default expansion. We failed to find a better alternative.
5992 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5993 SelectionDAG &DAG) const {
5994 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5996 // Check for non-constant or out of range lane.
5997 EVT VT = Op.getOperand(0).getValueType();
5998 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5999 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6003 // Insertion/extraction are legal for V128 types.
6004 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6005 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6009 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6010 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6013 // For V64 types, we perform insertion by expanding the value
6014 // to a V128 type and perform the insertion on that.
6016 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6017 EVT WideTy = WideVec.getValueType();
6019 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6020 Op.getOperand(1), Op.getOperand(2));
6021 // Re-narrow the resultant vector.
6022 return NarrowVector(Node, DAG);
6026 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6027 SelectionDAG &DAG) const {
6028 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6030 // Check for non-constant or out of range lane.
6031 EVT VT = Op.getOperand(0).getValueType();
6032 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6033 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6037 // Insertion/extraction are legal for V128 types.
6038 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6039 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6043 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6044 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6047 // For V64 types, we perform extraction by expanding the value
6048 // to a V128 type and perform the extraction on that.
6050 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6051 EVT WideTy = WideVec.getValueType();
6053 EVT ExtrTy = WideTy.getVectorElementType();
6054 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6057 // For extractions, we just return the result directly.
6058 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6062 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6063 SelectionDAG &DAG) const {
6064 EVT VT = Op.getOperand(0).getValueType();
6070 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6073 unsigned Val = Cst->getZExtValue();
6075 unsigned Size = Op.getValueType().getSizeInBits();
6079 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6082 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6085 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6088 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6091 llvm_unreachable("Unexpected vector type in extract_subvector!");
6094 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6096 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6102 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6104 if (VT.getVectorNumElements() == 4 &&
6105 (VT.is128BitVector() || VT.is64BitVector())) {
6106 unsigned PFIndexes[4];
6107 for (unsigned i = 0; i != 4; ++i) {
6111 PFIndexes[i] = M[i];
6114 // Compute the index in the perfect shuffle table.
6115 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6116 PFIndexes[2] * 9 + PFIndexes[3];
6117 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6118 unsigned Cost = (PFEntry >> 30);
6126 unsigned DummyUnsigned;
6128 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6129 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6130 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6131 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6132 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6133 isZIPMask(M, VT, DummyUnsigned) ||
6134 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6135 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6136 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6137 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6138 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6141 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6142 /// operand of a vector shift operation, where all the elements of the
6143 /// build_vector must have the same constant integer value.
6144 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6145 // Ignore bit_converts.
6146 while (Op.getOpcode() == ISD::BITCAST)
6147 Op = Op.getOperand(0);
6148 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6149 APInt SplatBits, SplatUndef;
6150 unsigned SplatBitSize;
6152 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6153 HasAnyUndefs, ElementBits) ||
6154 SplatBitSize > ElementBits)
6156 Cnt = SplatBits.getSExtValue();
6160 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6161 /// operand of a vector shift left operation. That value must be in the range:
6162 /// 0 <= Value < ElementBits for a left shift; or
6163 /// 0 <= Value <= ElementBits for a long left shift.
6164 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6165 assert(VT.isVector() && "vector shift count is not a vector type");
6166 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6167 if (!getVShiftImm(Op, ElementBits, Cnt))
6169 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6172 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6173 /// operand of a vector shift right operation. For a shift opcode, the value
6174 /// is positive, but for an intrinsic the value count must be negative. The
6175 /// absolute value must be in the range:
6176 /// 1 <= |Value| <= ElementBits for a right shift; or
6177 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6178 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6180 assert(VT.isVector() && "vector shift count is not a vector type");
6181 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6182 if (!getVShiftImm(Op, ElementBits, Cnt))
6186 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6189 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6190 SelectionDAG &DAG) const {
6191 EVT VT = Op.getValueType();
6195 if (!Op.getOperand(1).getValueType().isVector())
6197 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6199 switch (Op.getOpcode()) {
6201 llvm_unreachable("unexpected shift opcode");
6204 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6205 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6206 DAG.getConstant(Cnt, MVT::i32));
6207 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6208 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6209 Op.getOperand(0), Op.getOperand(1));
6212 // Right shift immediate
6213 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6216 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6217 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6218 DAG.getConstant(Cnt, MVT::i32));
6221 // Right shift register. Note, there is not a shift right register
6222 // instruction, but the shift left register instruction takes a signed
6223 // value, where negative numbers specify a right shift.
6224 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6225 : Intrinsic::aarch64_neon_ushl;
6226 // negate the shift amount
6227 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6228 SDValue NegShiftLeft =
6229 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6230 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6231 return NegShiftLeft;
6237 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6238 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6239 SDLoc dl, SelectionDAG &DAG) {
6240 EVT SrcVT = LHS.getValueType();
6241 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6242 "function only supposed to emit natural comparisons");
6244 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6245 APInt CnstBits(VT.getSizeInBits(), 0);
6246 APInt UndefBits(VT.getSizeInBits(), 0);
6247 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6248 bool IsZero = IsCnst && (CnstBits == 0);
6250 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6254 case AArch64CC::NE: {
6257 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6259 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6260 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6264 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6265 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6268 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6269 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6272 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6273 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6276 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6277 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6281 // If we ignore NaNs then we can use to the MI implementation.
6285 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6286 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6293 case AArch64CC::NE: {
6296 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6298 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6299 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6303 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6304 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6307 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6308 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6311 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6312 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6315 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6316 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6318 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6320 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6323 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6324 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6326 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6328 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6332 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6333 SelectionDAG &DAG) const {
6334 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6335 SDValue LHS = Op.getOperand(0);
6336 SDValue RHS = Op.getOperand(1);
6337 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6340 if (LHS.getValueType().getVectorElementType().isInteger()) {
6341 assert(LHS.getValueType() == RHS.getValueType());
6342 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6344 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6345 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6348 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6349 LHS.getValueType().getVectorElementType() == MVT::f64);
6351 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6352 // clean. Some of them require two branches to implement.
6353 AArch64CC::CondCode CC1, CC2;
6355 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6357 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6359 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6363 if (CC2 != AArch64CC::AL) {
6365 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6366 if (!Cmp2.getNode())
6369 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6372 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6375 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6380 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6381 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6382 /// specified in the intrinsic calls.
6383 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6385 unsigned Intrinsic) const {
6386 switch (Intrinsic) {
6387 case Intrinsic::aarch64_neon_ld2:
6388 case Intrinsic::aarch64_neon_ld3:
6389 case Intrinsic::aarch64_neon_ld4:
6390 case Intrinsic::aarch64_neon_ld1x2:
6391 case Intrinsic::aarch64_neon_ld1x3:
6392 case Intrinsic::aarch64_neon_ld1x4:
6393 case Intrinsic::aarch64_neon_ld2lane:
6394 case Intrinsic::aarch64_neon_ld3lane:
6395 case Intrinsic::aarch64_neon_ld4lane:
6396 case Intrinsic::aarch64_neon_ld2r:
6397 case Intrinsic::aarch64_neon_ld3r:
6398 case Intrinsic::aarch64_neon_ld4r: {
6399 Info.opc = ISD::INTRINSIC_W_CHAIN;
6400 // Conservatively set memVT to the entire set of vectors loaded.
6401 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6402 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6403 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6406 Info.vol = false; // volatile loads with NEON intrinsics not supported
6407 Info.readMem = true;
6408 Info.writeMem = false;
6411 case Intrinsic::aarch64_neon_st2:
6412 case Intrinsic::aarch64_neon_st3:
6413 case Intrinsic::aarch64_neon_st4:
6414 case Intrinsic::aarch64_neon_st1x2:
6415 case Intrinsic::aarch64_neon_st1x3:
6416 case Intrinsic::aarch64_neon_st1x4:
6417 case Intrinsic::aarch64_neon_st2lane:
6418 case Intrinsic::aarch64_neon_st3lane:
6419 case Intrinsic::aarch64_neon_st4lane: {
6420 Info.opc = ISD::INTRINSIC_VOID;
6421 // Conservatively set memVT to the entire set of vectors stored.
6422 unsigned NumElts = 0;
6423 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6424 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6425 if (!ArgTy->isVectorTy())
6427 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6429 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6430 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6433 Info.vol = false; // volatile stores with NEON intrinsics not supported
6434 Info.readMem = false;
6435 Info.writeMem = true;
6438 case Intrinsic::aarch64_ldaxr:
6439 case Intrinsic::aarch64_ldxr: {
6440 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6441 Info.opc = ISD::INTRINSIC_W_CHAIN;
6442 Info.memVT = MVT::getVT(PtrTy->getElementType());
6443 Info.ptrVal = I.getArgOperand(0);
6445 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6447 Info.readMem = true;
6448 Info.writeMem = false;
6451 case Intrinsic::aarch64_stlxr:
6452 case Intrinsic::aarch64_stxr: {
6453 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6454 Info.opc = ISD::INTRINSIC_W_CHAIN;
6455 Info.memVT = MVT::getVT(PtrTy->getElementType());
6456 Info.ptrVal = I.getArgOperand(1);
6458 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6460 Info.readMem = false;
6461 Info.writeMem = true;
6464 case Intrinsic::aarch64_ldaxp:
6465 case Intrinsic::aarch64_ldxp: {
6466 Info.opc = ISD::INTRINSIC_W_CHAIN;
6467 Info.memVT = MVT::i128;
6468 Info.ptrVal = I.getArgOperand(0);
6472 Info.readMem = true;
6473 Info.writeMem = false;
6476 case Intrinsic::aarch64_stlxp:
6477 case Intrinsic::aarch64_stxp: {
6478 Info.opc = ISD::INTRINSIC_W_CHAIN;
6479 Info.memVT = MVT::i128;
6480 Info.ptrVal = I.getArgOperand(2);
6484 Info.readMem = false;
6485 Info.writeMem = true;
6495 // Truncations from 64-bit GPR to 32-bit GPR is free.
6496 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6497 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6499 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6500 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6501 return NumBits1 > NumBits2;
6503 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6504 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6506 unsigned NumBits1 = VT1.getSizeInBits();
6507 unsigned NumBits2 = VT2.getSizeInBits();
6508 return NumBits1 > NumBits2;
6511 /// Check if it is profitable to hoist instruction in then/else to if.
6512 /// Not profitable if I and it's user can form a FMA instruction
6513 /// because we prefer FMSUB/FMADD.
6514 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6515 if (I->getOpcode() != Instruction::FMul)
6518 if (I->getNumUses() != 1)
6521 Instruction *User = I->user_back();
6524 !(User->getOpcode() == Instruction::FSub ||
6525 User->getOpcode() == Instruction::FAdd))
6528 const TargetOptions &Options = getTargetMachine().Options;
6529 EVT VT = getValueType(User->getOperand(0)->getType());
6531 if (isFMAFasterThanFMulAndFAdd(VT) &&
6532 isOperationLegalOrCustom(ISD::FMA, VT) &&
6533 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6539 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6541 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6542 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6544 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6545 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6546 return NumBits1 == 32 && NumBits2 == 64;
6548 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6549 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6551 unsigned NumBits1 = VT1.getSizeInBits();
6552 unsigned NumBits2 = VT2.getSizeInBits();
6553 return NumBits1 == 32 && NumBits2 == 64;
6556 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6557 EVT VT1 = Val.getValueType();
6558 if (isZExtFree(VT1, VT2)) {
6562 if (Val.getOpcode() != ISD::LOAD)
6565 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6566 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6567 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6568 VT1.getSizeInBits() <= 32);
6571 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6572 if (isa<FPExtInst>(Ext))
6575 // Vector types are next free.
6576 if (Ext->getType()->isVectorTy())
6579 for (const Use &U : Ext->uses()) {
6580 // The extension is free if we can fold it with a left shift in an
6581 // addressing mode or an arithmetic operation: add, sub, and cmp.
6583 // Is there a shift?
6584 const Instruction *Instr = cast<Instruction>(U.getUser());
6586 // Is this a constant shift?
6587 switch (Instr->getOpcode()) {
6588 case Instruction::Shl:
6589 if (!isa<ConstantInt>(Instr->getOperand(1)))
6592 case Instruction::GetElementPtr: {
6593 gep_type_iterator GTI = gep_type_begin(Instr);
6594 std::advance(GTI, U.getOperandNo());
6596 // This extension will end up with a shift because of the scaling factor.
6597 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6598 // Get the shift amount based on the scaling factor:
6599 // log2(sizeof(IdxTy)) - log2(8).
6601 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6602 // Is the constant foldable in the shift of the addressing mode?
6603 // I.e., shift amount is between 1 and 4 inclusive.
6604 if (ShiftAmt == 0 || ShiftAmt > 4)
6608 case Instruction::Trunc:
6609 // Check if this is a noop.
6610 // trunc(sext ty1 to ty2) to ty1.
6611 if (Instr->getType() == Ext->getOperand(0)->getType())
6618 // At this point we can use the bfm family, so this extension is free
6624 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6625 unsigned &RequiredAligment) const {
6626 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6628 // Cyclone supports unaligned accesses.
6629 RequiredAligment = 0;
6630 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6631 return NumBits == 32 || NumBits == 64;
6634 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6635 unsigned &RequiredAligment) const {
6636 if (!LoadedType.isSimple() ||
6637 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6639 // Cyclone supports unaligned accesses.
6640 RequiredAligment = 0;
6641 unsigned NumBits = LoadedType.getSizeInBits();
6642 return NumBits == 32 || NumBits == 64;
6645 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6646 unsigned AlignCheck) {
6647 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6648 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6651 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6652 unsigned SrcAlign, bool IsMemset,
6655 MachineFunction &MF) const {
6656 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6657 // instruction to materialize the v2i64 zero and one store (with restrictive
6658 // addressing mode). Just do two i64 store of zero-registers.
6660 const Function *F = MF.getFunction();
6661 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6662 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6663 (memOpAlign(SrcAlign, DstAlign, 16) ||
6664 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6667 return Size >= 8 ? MVT::i64 : MVT::i32;
6670 // 12-bit optionally shifted immediates are legal for adds.
6671 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6672 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6677 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6678 // immediates is the same as for an add or a sub.
6679 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6682 return isLegalAddImmediate(Immed);
6685 /// isLegalAddressingMode - Return true if the addressing mode represented
6686 /// by AM is legal for this target, for a load/store of the specified type.
6687 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6689 // AArch64 has five basic addressing modes:
6691 // reg + 9-bit signed offset
6692 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6694 // reg + SIZE_IN_BYTES * reg
6696 // No global is ever allowed as a base.
6700 // No reg+reg+imm addressing.
6701 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6704 // check reg + imm case:
6705 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6706 uint64_t NumBytes = 0;
6707 if (Ty->isSized()) {
6708 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6709 NumBytes = NumBits / 8;
6710 if (!isPowerOf2_64(NumBits))
6715 int64_t Offset = AM.BaseOffs;
6717 // 9-bit signed offset
6718 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6721 // 12-bit unsigned offset
6722 unsigned shift = Log2_64(NumBytes);
6723 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6724 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6725 (Offset >> shift) << shift == Offset)
6730 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6732 if (!AM.Scale || AM.Scale == 1 ||
6733 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6738 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6740 // Scaling factors are not free at all.
6741 // Operands | Rt Latency
6742 // -------------------------------------------
6744 // -------------------------------------------
6745 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6746 // Rt, [Xn, Wm, <extend> #imm] |
6747 if (isLegalAddressingMode(AM, Ty))
6748 // Scale represents reg2 * scale, thus account for 1 if
6749 // it is not equal to 0 or 1.
6750 return AM.Scale != 0 && AM.Scale != 1;
6754 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6755 VT = VT.getScalarType();
6760 switch (VT.getSimpleVT().SimpleTy) {
6772 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6773 // LR is a callee-save register, but we must treat it as clobbered by any call
6774 // site. Hence we include LR in the scratch registers, which are in turn added
6775 // as implicit-defs for stackmaps and patchpoints.
6776 static const MCPhysReg ScratchRegs[] = {
6777 AArch64::X16, AArch64::X17, AArch64::LR, 0
6783 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6784 EVT VT = N->getValueType(0);
6785 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6786 // it with shift to let it be lowered to UBFX.
6787 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6788 isa<ConstantSDNode>(N->getOperand(1))) {
6789 uint64_t TruncMask = N->getConstantOperandVal(1);
6790 if (isMask_64(TruncMask) &&
6791 N->getOperand(0).getOpcode() == ISD::SRL &&
6792 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6798 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6800 assert(Ty->isIntegerTy());
6802 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6806 int64_t Val = Imm.getSExtValue();
6807 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6810 if ((int64_t)Val < 0)
6813 Val &= (1LL << 32) - 1;
6815 unsigned LZ = countLeadingZeros((uint64_t)Val);
6816 unsigned Shift = (63 - LZ) / 16;
6817 // MOVZ is free so return true for one or fewer MOVK.
6821 // Generate SUBS and CSEL for integer abs.
6822 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6823 EVT VT = N->getValueType(0);
6825 SDValue N0 = N->getOperand(0);
6826 SDValue N1 = N->getOperand(1);
6829 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6830 // and change it to SUB and CSEL.
6831 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6832 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6833 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6834 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6835 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6836 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6838 // Generate SUBS & CSEL.
6840 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6841 N0.getOperand(0), DAG.getConstant(0, VT));
6842 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6843 DAG.getConstant(AArch64CC::PL, MVT::i32),
6844 SDValue(Cmp.getNode(), 1));
6849 // performXorCombine - Attempts to handle integer ABS.
6850 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6851 TargetLowering::DAGCombinerInfo &DCI,
6852 const AArch64Subtarget *Subtarget) {
6853 if (DCI.isBeforeLegalizeOps())
6856 return performIntegerAbsCombine(N, DAG);
6860 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6862 std::vector<SDNode *> *Created) const {
6863 // fold (sdiv X, pow2)
6864 EVT VT = N->getValueType(0);
6865 if ((VT != MVT::i32 && VT != MVT::i64) ||
6866 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6870 SDValue N0 = N->getOperand(0);
6871 unsigned Lg2 = Divisor.countTrailingZeros();
6872 SDValue Zero = DAG.getConstant(0, VT);
6873 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6875 // Add (N0 < 0) ? Pow2 - 1 : 0;
6877 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6878 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6879 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6882 Created->push_back(Cmp.getNode());
6883 Created->push_back(Add.getNode());
6884 Created->push_back(CSel.getNode());
6889 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6891 // If we're dividing by a positive value, we're done. Otherwise, we must
6892 // negate the result.
6893 if (Divisor.isNonNegative())
6897 Created->push_back(SRA.getNode());
6898 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6901 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6902 TargetLowering::DAGCombinerInfo &DCI,
6903 const AArch64Subtarget *Subtarget) {
6904 if (DCI.isBeforeLegalizeOps())
6907 // Multiplication of a power of two plus/minus one can be done more
6908 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6909 // future CPUs have a cheaper MADD instruction, this may need to be
6910 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6911 // 64-bit is 5 cycles, so this is always a win.
6912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6913 APInt Value = C->getAPIntValue();
6914 EVT VT = N->getValueType(0);
6915 if (Value.isNonNegative()) {
6916 // (mul x, 2^N + 1) => (add (shl x, N), x)
6917 APInt VM1 = Value - 1;
6918 if (VM1.isPowerOf2()) {
6919 SDValue ShiftedVal =
6920 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6921 DAG.getConstant(VM1.logBase2(), MVT::i64));
6922 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6925 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6926 APInt VP1 = Value + 1;
6927 if (VP1.isPowerOf2()) {
6928 SDValue ShiftedVal =
6929 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6930 DAG.getConstant(VP1.logBase2(), MVT::i64));
6931 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6935 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6936 APInt VNP1 = -Value + 1;
6937 if (VNP1.isPowerOf2()) {
6938 SDValue ShiftedVal =
6939 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6940 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6941 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6944 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6945 APInt VNM1 = -Value - 1;
6946 if (VNM1.isPowerOf2()) {
6947 SDValue ShiftedVal =
6948 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6949 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6951 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6952 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6959 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6960 SelectionDAG &DAG) {
6961 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6962 // optimize away operation when it's from a constant.
6964 // The general transformation is:
6965 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6966 // AND(VECTOR_CMP(x,y), constant2)
6967 // constant2 = UNARYOP(constant)
6969 // Early exit if this isn't a vector operation, the operand of the
6970 // unary operation isn't a bitwise AND, or if the sizes of the operations
6972 EVT VT = N->getValueType(0);
6973 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6974 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6975 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6978 // Now check that the other operand of the AND is a constant. We could
6979 // make the transformation for non-constant splats as well, but it's unclear
6980 // that would be a benefit as it would not eliminate any operations, just
6981 // perform one more step in scalar code before moving to the vector unit.
6982 if (BuildVectorSDNode *BV =
6983 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6984 // Bail out if the vector isn't a constant.
6985 if (!BV->isConstant())
6988 // Everything checks out. Build up the new and improved node.
6990 EVT IntVT = BV->getValueType(0);
6991 // Create a new constant of the appropriate type for the transformed
6993 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6994 // The AND node needs bitcasts to/from an integer vector type around it.
6995 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6996 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6997 N->getOperand(0)->getOperand(0), MaskConst);
6998 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7005 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7006 const AArch64Subtarget *Subtarget) {
7007 // First try to optimize away the conversion when it's conditionally from
7008 // a constant. Vectors only.
7009 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7010 if (Res != SDValue())
7013 EVT VT = N->getValueType(0);
7014 if (VT != MVT::f32 && VT != MVT::f64)
7017 // Only optimize when the source and destination types have the same width.
7018 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7021 // If the result of an integer load is only used by an integer-to-float
7022 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7023 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7024 SDValue N0 = N->getOperand(0);
7025 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7026 // Do not change the width of a volatile load.
7027 !cast<LoadSDNode>(N0)->isVolatile()) {
7028 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7029 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7030 LN0->getPointerInfo(), LN0->isVolatile(),
7031 LN0->isNonTemporal(), LN0->isInvariant(),
7032 LN0->getAlignment());
7034 // Make sure successors of the original load stay after it by updating them
7035 // to use the new Chain.
7036 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7039 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7040 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7046 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7047 /// searches for and classifies those shifts.
7048 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7050 if (N.getOpcode() == ISD::SHL)
7052 else if (N.getOpcode() == ISD::SRL)
7057 if (!isa<ConstantSDNode>(N.getOperand(1)))
7060 ShiftAmount = N->getConstantOperandVal(1);
7061 Src = N->getOperand(0);
7065 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7066 /// registers viewed as a high/low pair. This function looks for the pattern:
7067 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7068 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7070 static SDValue tryCombineToEXTR(SDNode *N,
7071 TargetLowering::DAGCombinerInfo &DCI) {
7072 SelectionDAG &DAG = DCI.DAG;
7074 EVT VT = N->getValueType(0);
7076 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7078 if (VT != MVT::i32 && VT != MVT::i64)
7082 uint32_t ShiftLHS = 0;
7084 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7088 uint32_t ShiftRHS = 0;
7090 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7093 // If they're both trying to come from the high part of the register, they're
7094 // not really an EXTR.
7095 if (LHSFromHi == RHSFromHi)
7098 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7102 std::swap(LHS, RHS);
7103 std::swap(ShiftLHS, ShiftRHS);
7106 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7107 DAG.getConstant(ShiftRHS, MVT::i64));
7110 static SDValue tryCombineToBSL(SDNode *N,
7111 TargetLowering::DAGCombinerInfo &DCI) {
7112 EVT VT = N->getValueType(0);
7113 SelectionDAG &DAG = DCI.DAG;
7119 SDValue N0 = N->getOperand(0);
7120 if (N0.getOpcode() != ISD::AND)
7123 SDValue N1 = N->getOperand(1);
7124 if (N1.getOpcode() != ISD::AND)
7127 // We only have to look for constant vectors here since the general, variable
7128 // case can be handled in TableGen.
7129 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7130 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7131 for (int i = 1; i >= 0; --i)
7132 for (int j = 1; j >= 0; --j) {
7133 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7134 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7138 bool FoundMatch = true;
7139 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7140 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7141 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7143 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7150 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7151 N0->getOperand(1 - i), N1->getOperand(1 - j));
7157 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7158 const AArch64Subtarget *Subtarget) {
7159 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7160 if (!EnableAArch64ExtrGeneration)
7162 SelectionDAG &DAG = DCI.DAG;
7163 EVT VT = N->getValueType(0);
7165 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7168 SDValue Res = tryCombineToEXTR(N, DCI);
7172 Res = tryCombineToBSL(N, DCI);
7179 static SDValue performBitcastCombine(SDNode *N,
7180 TargetLowering::DAGCombinerInfo &DCI,
7181 SelectionDAG &DAG) {
7182 // Wait 'til after everything is legalized to try this. That way we have
7183 // legal vector types and such.
7184 if (DCI.isBeforeLegalizeOps())
7187 // Remove extraneous bitcasts around an extract_subvector.
7189 // (v4i16 (bitconvert
7190 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7192 // (extract_subvector ((v8i16 ...), (i64 4)))
7194 // Only interested in 64-bit vectors as the ultimate result.
7195 EVT VT = N->getValueType(0);
7198 if (VT.getSimpleVT().getSizeInBits() != 64)
7200 // Is the operand an extract_subvector starting at the beginning or halfway
7201 // point of the vector? A low half may also come through as an
7202 // EXTRACT_SUBREG, so look for that, too.
7203 SDValue Op0 = N->getOperand(0);
7204 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7205 !(Op0->isMachineOpcode() &&
7206 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7208 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7209 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7210 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7212 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7213 if (idx != AArch64::dsub)
7215 // The dsub reference is equivalent to a lane zero subvector reference.
7218 // Look through the bitcast of the input to the extract.
7219 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7221 SDValue Source = Op0->getOperand(0)->getOperand(0);
7222 // If the source type has twice the number of elements as our destination
7223 // type, we know this is an extract of the high or low half of the vector.
7224 EVT SVT = Source->getValueType(0);
7225 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7228 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7230 // Create the simplified form to just extract the low or high half of the
7231 // vector directly rather than bothering with the bitcasts.
7233 unsigned NumElements = VT.getVectorNumElements();
7235 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7236 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7238 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7239 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7245 static SDValue performConcatVectorsCombine(SDNode *N,
7246 TargetLowering::DAGCombinerInfo &DCI,
7247 SelectionDAG &DAG) {
7249 EVT VT = N->getValueType(0);
7250 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7252 // Optimize concat_vectors of truncated vectors, where the intermediate
7253 // type is illegal, to avoid said illegality, e.g.,
7254 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7255 // (v2i16 (truncate (v2i64)))))
7257 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7258 // (v4i32 (bitcast (v2i64))),
7260 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7261 // on both input and result type, so we might generate worse code.
7262 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7263 if (N->getNumOperands() == 2 &&
7264 N0->getOpcode() == ISD::TRUNCATE &&
7265 N1->getOpcode() == ISD::TRUNCATE) {
7266 SDValue N00 = N0->getOperand(0);
7267 SDValue N10 = N1->getOperand(0);
7268 EVT N00VT = N00.getValueType();
7270 if (N00VT == N10.getValueType() &&
7271 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7272 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7273 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7274 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7275 for (size_t i = 0; i < Mask.size(); ++i)
7277 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7278 DAG.getVectorShuffle(
7280 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7281 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7285 // Wait 'til after everything is legalized to try this. That way we have
7286 // legal vector types and such.
7287 if (DCI.isBeforeLegalizeOps())
7290 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7291 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7292 // canonicalise to that.
7293 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7294 assert(VT.getVectorElementType().getSizeInBits() == 64);
7295 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7296 DAG.getConstant(0, MVT::i64));
7299 // Canonicalise concat_vectors so that the right-hand vector has as few
7300 // bit-casts as possible before its real operation. The primary matching
7301 // destination for these operations will be the narrowing "2" instructions,
7302 // which depend on the operation being performed on this right-hand vector.
7304 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7306 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7308 if (N1->getOpcode() != ISD::BITCAST)
7310 SDValue RHS = N1->getOperand(0);
7311 MVT RHSTy = RHS.getValueType().getSimpleVT();
7312 // If the RHS is not a vector, this is not the pattern we're looking for.
7313 if (!RHSTy.isVector())
7316 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7318 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7319 RHSTy.getVectorNumElements() * 2);
7320 return DAG.getNode(ISD::BITCAST, dl, VT,
7321 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7322 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7326 static SDValue tryCombineFixedPointConvert(SDNode *N,
7327 TargetLowering::DAGCombinerInfo &DCI,
7328 SelectionDAG &DAG) {
7329 // Wait 'til after everything is legalized to try this. That way we have
7330 // legal vector types and such.
7331 if (DCI.isBeforeLegalizeOps())
7333 // Transform a scalar conversion of a value from a lane extract into a
7334 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7335 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7336 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7338 // The second form interacts better with instruction selection and the
7339 // register allocator to avoid cross-class register copies that aren't
7340 // coalescable due to a lane reference.
7342 // Check the operand and see if it originates from a lane extract.
7343 SDValue Op1 = N->getOperand(1);
7344 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7345 // Yep, no additional predication needed. Perform the transform.
7346 SDValue IID = N->getOperand(0);
7347 SDValue Shift = N->getOperand(2);
7348 SDValue Vec = Op1.getOperand(0);
7349 SDValue Lane = Op1.getOperand(1);
7350 EVT ResTy = N->getValueType(0);
7354 // The vector width should be 128 bits by the time we get here, even
7355 // if it started as 64 bits (the extract_vector handling will have
7357 assert(Vec.getValueType().getSizeInBits() == 128 &&
7358 "unexpected vector size on extract_vector_elt!");
7359 if (Vec.getValueType() == MVT::v4i32)
7360 VecResTy = MVT::v4f32;
7361 else if (Vec.getValueType() == MVT::v2i64)
7362 VecResTy = MVT::v2f64;
7364 llvm_unreachable("unexpected vector type!");
7367 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7368 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7373 // AArch64 high-vector "long" operations are formed by performing the non-high
7374 // version on an extract_subvector of each operand which gets the high half:
7376 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7378 // However, there are cases which don't have an extract_high explicitly, but
7379 // have another operation that can be made compatible with one for free. For
7382 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7384 // This routine does the actual conversion of such DUPs, once outer routines
7385 // have determined that everything else is in order.
7386 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7387 // We can handle most types of duplicate, but the lane ones have an extra
7388 // operand saying *which* lane, so we need to know.
7390 switch (N.getOpcode()) {
7391 case AArch64ISD::DUP:
7394 case AArch64ISD::DUPLANE8:
7395 case AArch64ISD::DUPLANE16:
7396 case AArch64ISD::DUPLANE32:
7397 case AArch64ISD::DUPLANE64:
7404 MVT NarrowTy = N.getSimpleValueType();
7405 if (!NarrowTy.is64BitVector())
7408 MVT ElementTy = NarrowTy.getVectorElementType();
7409 unsigned NumElems = NarrowTy.getVectorNumElements();
7410 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7414 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7417 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7419 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7420 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7423 static bool isEssentiallyExtractSubvector(SDValue N) {
7424 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7427 return N.getOpcode() == ISD::BITCAST &&
7428 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7431 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7432 struct GenericSetCCInfo {
7433 const SDValue *Opnd0;
7434 const SDValue *Opnd1;
7438 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7439 struct AArch64SetCCInfo {
7441 AArch64CC::CondCode CC;
7444 /// \brief Helper structure to keep track of SetCC information.
7446 GenericSetCCInfo Generic;
7447 AArch64SetCCInfo AArch64;
7450 /// \brief Helper structure to be able to read SetCC information. If set to
7451 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7452 /// GenericSetCCInfo.
7453 struct SetCCInfoAndKind {
7458 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7460 /// AArch64 lowered one.
7461 /// \p SetCCInfo is filled accordingly.
7462 /// \post SetCCInfo is meanginfull only when this function returns true.
7463 /// \return True when Op is a kind of SET_CC operation.
7464 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7465 // If this is a setcc, this is straight forward.
7466 if (Op.getOpcode() == ISD::SETCC) {
7467 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7468 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7469 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7470 SetCCInfo.IsAArch64 = false;
7473 // Otherwise, check if this is a matching csel instruction.
7477 if (Op.getOpcode() != AArch64ISD::CSEL)
7479 // Set the information about the operands.
7480 // TODO: we want the operands of the Cmp not the csel
7481 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7482 SetCCInfo.IsAArch64 = true;
7483 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7484 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7486 // Check that the operands matches the constraints:
7487 // (1) Both operands must be constants.
7488 // (2) One must be 1 and the other must be 0.
7489 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7490 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7493 if (!TValue || !FValue)
7497 if (!TValue->isOne()) {
7498 // Update the comparison when we are interested in !cc.
7499 std::swap(TValue, FValue);
7500 SetCCInfo.Info.AArch64.CC =
7501 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7503 return TValue->isOne() && FValue->isNullValue();
7506 // Returns true if Op is setcc or zext of setcc.
7507 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7508 if (isSetCC(Op, Info))
7510 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7511 isSetCC(Op->getOperand(0), Info));
7514 // The folding we want to perform is:
7515 // (add x, [zext] (setcc cc ...) )
7517 // (csel x, (add x, 1), !cc ...)
7519 // The latter will get matched to a CSINC instruction.
7520 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7521 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7522 SDValue LHS = Op->getOperand(0);
7523 SDValue RHS = Op->getOperand(1);
7524 SetCCInfoAndKind InfoAndKind;
7526 // If neither operand is a SET_CC, give up.
7527 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7528 std::swap(LHS, RHS);
7529 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7533 // FIXME: This could be generatized to work for FP comparisons.
7534 EVT CmpVT = InfoAndKind.IsAArch64
7535 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7536 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7537 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7543 if (InfoAndKind.IsAArch64) {
7544 CCVal = DAG.getConstant(
7545 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7546 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7548 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7549 *InfoAndKind.Info.Generic.Opnd1,
7550 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7553 EVT VT = Op->getValueType(0);
7554 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7555 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7558 // The basic add/sub long vector instructions have variants with "2" on the end
7559 // which act on the high-half of their inputs. They are normally matched by
7562 // (add (zeroext (extract_high LHS)),
7563 // (zeroext (extract_high RHS)))
7564 // -> uaddl2 vD, vN, vM
7566 // However, if one of the extracts is something like a duplicate, this
7567 // instruction can still be used profitably. This function puts the DAG into a
7568 // more appropriate form for those patterns to trigger.
7569 static SDValue performAddSubLongCombine(SDNode *N,
7570 TargetLowering::DAGCombinerInfo &DCI,
7571 SelectionDAG &DAG) {
7572 if (DCI.isBeforeLegalizeOps())
7575 MVT VT = N->getSimpleValueType(0);
7576 if (!VT.is128BitVector()) {
7577 if (N->getOpcode() == ISD::ADD)
7578 return performSetccAddFolding(N, DAG);
7582 // Make sure both branches are extended in the same way.
7583 SDValue LHS = N->getOperand(0);
7584 SDValue RHS = N->getOperand(1);
7585 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7586 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7587 LHS.getOpcode() != RHS.getOpcode())
7590 unsigned ExtType = LHS.getOpcode();
7592 // It's not worth doing if at least one of the inputs isn't already an
7593 // extract, but we don't know which it'll be so we have to try both.
7594 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7595 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7599 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7600 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7601 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7605 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7608 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7611 // Massage DAGs which we can use the high-half "long" operations on into
7612 // something isel will recognize better. E.g.
7614 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7615 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7616 // (extract_high (v2i64 (dup128 scalar)))))
7618 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7619 TargetLowering::DAGCombinerInfo &DCI,
7620 SelectionDAG &DAG) {
7621 if (DCI.isBeforeLegalizeOps())
7624 SDValue LHS = N->getOperand(1);
7625 SDValue RHS = N->getOperand(2);
7626 assert(LHS.getValueType().is64BitVector() &&
7627 RHS.getValueType().is64BitVector() &&
7628 "unexpected shape for long operation");
7630 // Either node could be a DUP, but it's not worth doing both of them (you'd
7631 // just as well use the non-high version) so look for a corresponding extract
7632 // operation on the other "wing".
7633 if (isEssentiallyExtractSubvector(LHS)) {
7634 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7637 } else if (isEssentiallyExtractSubvector(RHS)) {
7638 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7643 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7644 N->getOperand(0), LHS, RHS);
7647 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7648 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7649 unsigned ElemBits = ElemTy.getSizeInBits();
7651 int64_t ShiftAmount;
7652 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7653 APInt SplatValue, SplatUndef;
7654 unsigned SplatBitSize;
7656 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7657 HasAnyUndefs, ElemBits) ||
7658 SplatBitSize != ElemBits)
7661 ShiftAmount = SplatValue.getSExtValue();
7662 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7663 ShiftAmount = CVN->getSExtValue();
7671 llvm_unreachable("Unknown shift intrinsic");
7672 case Intrinsic::aarch64_neon_sqshl:
7673 Opcode = AArch64ISD::SQSHL_I;
7674 IsRightShift = false;
7676 case Intrinsic::aarch64_neon_uqshl:
7677 Opcode = AArch64ISD::UQSHL_I;
7678 IsRightShift = false;
7680 case Intrinsic::aarch64_neon_srshl:
7681 Opcode = AArch64ISD::SRSHR_I;
7682 IsRightShift = true;
7684 case Intrinsic::aarch64_neon_urshl:
7685 Opcode = AArch64ISD::URSHR_I;
7686 IsRightShift = true;
7688 case Intrinsic::aarch64_neon_sqshlu:
7689 Opcode = AArch64ISD::SQSHLU_I;
7690 IsRightShift = false;
7694 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7695 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7696 DAG.getConstant(-ShiftAmount, MVT::i32));
7697 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7698 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7699 DAG.getConstant(ShiftAmount, MVT::i32));
7704 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7705 // the intrinsics must be legal and take an i32, this means there's almost
7706 // certainly going to be a zext in the DAG which we can eliminate.
7707 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7708 SDValue AndN = N->getOperand(2);
7709 if (AndN.getOpcode() != ISD::AND)
7712 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7713 if (!CMask || CMask->getZExtValue() != Mask)
7716 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7717 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7720 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7721 SelectionDAG &DAG) {
7722 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
7723 DAG.getNode(Opc, SDLoc(N),
7724 N->getOperand(1).getSimpleValueType(),
7726 DAG.getConstant(0, MVT::i64));
7729 static SDValue performIntrinsicCombine(SDNode *N,
7730 TargetLowering::DAGCombinerInfo &DCI,
7731 const AArch64Subtarget *Subtarget) {
7732 SelectionDAG &DAG = DCI.DAG;
7733 unsigned IID = getIntrinsicID(N);
7737 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7738 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7739 return tryCombineFixedPointConvert(N, DCI, DAG);
7741 case Intrinsic::aarch64_neon_saddv:
7742 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7743 case Intrinsic::aarch64_neon_uaddv:
7744 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7745 case Intrinsic::aarch64_neon_sminv:
7746 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7747 case Intrinsic::aarch64_neon_uminv:
7748 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7749 case Intrinsic::aarch64_neon_smaxv:
7750 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7751 case Intrinsic::aarch64_neon_umaxv:
7752 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7753 case Intrinsic::aarch64_neon_fmax:
7754 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7755 N->getOperand(1), N->getOperand(2));
7756 case Intrinsic::aarch64_neon_fmin:
7757 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7758 N->getOperand(1), N->getOperand(2));
7759 case Intrinsic::aarch64_neon_smull:
7760 case Intrinsic::aarch64_neon_umull:
7761 case Intrinsic::aarch64_neon_pmull:
7762 case Intrinsic::aarch64_neon_sqdmull:
7763 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7764 case Intrinsic::aarch64_neon_sqshl:
7765 case Intrinsic::aarch64_neon_uqshl:
7766 case Intrinsic::aarch64_neon_sqshlu:
7767 case Intrinsic::aarch64_neon_srshl:
7768 case Intrinsic::aarch64_neon_urshl:
7769 return tryCombineShiftImm(IID, N, DAG);
7770 case Intrinsic::aarch64_crc32b:
7771 case Intrinsic::aarch64_crc32cb:
7772 return tryCombineCRC32(0xff, N, DAG);
7773 case Intrinsic::aarch64_crc32h:
7774 case Intrinsic::aarch64_crc32ch:
7775 return tryCombineCRC32(0xffff, N, DAG);
7780 static SDValue performExtendCombine(SDNode *N,
7781 TargetLowering::DAGCombinerInfo &DCI,
7782 SelectionDAG &DAG) {
7783 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7784 // we can convert that DUP into another extract_high (of a bigger DUP), which
7785 // helps the backend to decide that an sabdl2 would be useful, saving a real
7786 // extract_high operation.
7787 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7788 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7789 SDNode *ABDNode = N->getOperand(0).getNode();
7790 unsigned IID = getIntrinsicID(ABDNode);
7791 if (IID == Intrinsic::aarch64_neon_sabd ||
7792 IID == Intrinsic::aarch64_neon_uabd) {
7793 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7794 if (!NewABD.getNode())
7797 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7802 // This is effectively a custom type legalization for AArch64.
7804 // Type legalization will split an extend of a small, legal, type to a larger
7805 // illegal type by first splitting the destination type, often creating
7806 // illegal source types, which then get legalized in isel-confusing ways,
7807 // leading to really terrible codegen. E.g.,
7808 // %result = v8i32 sext v8i8 %value
7810 // %losrc = extract_subreg %value, ...
7811 // %hisrc = extract_subreg %value, ...
7812 // %lo = v4i32 sext v4i8 %losrc
7813 // %hi = v4i32 sext v4i8 %hisrc
7814 // Things go rapidly downhill from there.
7816 // For AArch64, the [sz]ext vector instructions can only go up one element
7817 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7818 // take two instructions.
7820 // This implies that the most efficient way to do the extend from v8i8
7821 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7822 // the normal splitting to happen for the v8i16->v8i32.
7824 // This is pre-legalization to catch some cases where the default
7825 // type legalization will create ill-tempered code.
7826 if (!DCI.isBeforeLegalizeOps())
7829 // We're only interested in cleaning things up for non-legal vector types
7830 // here. If both the source and destination are legal, things will just
7831 // work naturally without any fiddling.
7832 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7833 EVT ResVT = N->getValueType(0);
7834 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7836 // If the vector type isn't a simple VT, it's beyond the scope of what
7837 // we're worried about here. Let legalization do its thing and hope for
7839 SDValue Src = N->getOperand(0);
7840 EVT SrcVT = Src->getValueType(0);
7841 if (!ResVT.isSimple() || !SrcVT.isSimple())
7844 // If the source VT is a 64-bit vector, we can play games and get the
7845 // better results we want.
7846 if (SrcVT.getSizeInBits() != 64)
7849 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7850 unsigned ElementCount = SrcVT.getVectorNumElements();
7851 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7853 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7855 // Now split the rest of the operation into two halves, each with a 64
7859 unsigned NumElements = ResVT.getVectorNumElements();
7860 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7861 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7862 ResVT.getVectorElementType(), NumElements / 2);
7864 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7865 LoVT.getVectorNumElements());
7866 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7867 DAG.getConstant(0, MVT::i64));
7868 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7869 DAG.getConstant(InNVT.getVectorNumElements(), MVT::i64));
7870 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7871 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7873 // Now combine the parts back together so we still have a single result
7874 // like the combiner expects.
7875 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7878 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7879 /// value. The load store optimizer pass will merge them to store pair stores.
7880 /// This has better performance than a splat of the scalar followed by a split
7881 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7882 /// followed by an ext.b and two stores.
7883 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7884 SDValue StVal = St->getValue();
7885 EVT VT = StVal.getValueType();
7887 // Don't replace floating point stores, they possibly won't be transformed to
7888 // stp because of the store pair suppress pass.
7889 if (VT.isFloatingPoint())
7892 // Check for insert vector elements.
7893 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7896 // We can express a splat as store pair(s) for 2 or 4 elements.
7897 unsigned NumVecElts = VT.getVectorNumElements();
7898 if (NumVecElts != 4 && NumVecElts != 2)
7900 SDValue SplatVal = StVal.getOperand(1);
7901 unsigned RemainInsertElts = NumVecElts - 1;
7903 // Check that this is a splat.
7904 while (--RemainInsertElts) {
7905 SDValue NextInsertElt = StVal.getOperand(0);
7906 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7908 if (NextInsertElt.getOperand(1) != SplatVal)
7910 StVal = NextInsertElt;
7912 unsigned OrigAlignment = St->getAlignment();
7913 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7914 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7916 // Create scalar stores. This is at least as good as the code sequence for a
7917 // split unaligned store wich is a dup.s, ext.b, and two stores.
7918 // Most of the time the three stores should be replaced by store pair
7919 // instructions (stp).
7921 SDValue BasePtr = St->getBasePtr();
7923 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7924 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7926 unsigned Offset = EltOffset;
7927 while (--NumVecElts) {
7928 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7929 DAG.getConstant(Offset, MVT::i64));
7930 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7931 St->getPointerInfo(), St->isVolatile(),
7932 St->isNonTemporal(), Alignment);
7933 Offset += EltOffset;
7938 static SDValue performSTORECombine(SDNode *N,
7939 TargetLowering::DAGCombinerInfo &DCI,
7941 const AArch64Subtarget *Subtarget) {
7942 if (!DCI.isBeforeLegalize())
7945 StoreSDNode *S = cast<StoreSDNode>(N);
7946 if (S->isVolatile())
7949 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7950 // page boundaries. We want to split such stores.
7951 if (!Subtarget->isCyclone())
7954 // Don't split at Oz.
7955 MachineFunction &MF = DAG.getMachineFunction();
7956 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
7960 SDValue StVal = S->getValue();
7961 EVT VT = StVal.getValueType();
7963 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7964 // those up regresses performance on micro-benchmarks and olden/bh.
7965 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7968 // Split unaligned 16B stores. They are terrible for performance.
7969 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7970 // extensions can use this to mark that it does not want splitting to happen
7971 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7972 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7973 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7974 S->getAlignment() <= 2)
7977 // If we get a splat of a scalar convert this vector store to a store of
7978 // scalars. They will be merged into store pairs thereby removing two
7980 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7981 if (ReplacedSplat != SDValue())
7982 return ReplacedSplat;
7985 unsigned NumElts = VT.getVectorNumElements() / 2;
7986 // Split VT into two.
7988 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7989 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7990 DAG.getConstant(0, MVT::i64));
7991 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7992 DAG.getConstant(NumElts, MVT::i64));
7993 SDValue BasePtr = S->getBasePtr();
7995 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7996 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7997 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7998 DAG.getConstant(8, MVT::i64));
7999 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8000 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8004 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8005 /// post-increment LD1R.
8006 static SDValue performPostLD1Combine(SDNode *N,
8007 TargetLowering::DAGCombinerInfo &DCI,
8009 if (DCI.isBeforeLegalizeOps())
8012 SelectionDAG &DAG = DCI.DAG;
8013 EVT VT = N->getValueType(0);
8015 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8016 SDNode *LD = N->getOperand(LoadIdx).getNode();
8017 // If it is not LOAD, can not do such combine.
8018 if (LD->getOpcode() != ISD::LOAD)
8021 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8022 EVT MemVT = LoadSDN->getMemoryVT();
8023 // Check if memory operand is the same type as the vector element.
8024 if (MemVT != VT.getVectorElementType())
8027 // Check if there are other uses. If so, do not combine as it will introduce
8029 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8031 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8037 SDValue Addr = LD->getOperand(1);
8038 SDValue Vector = N->getOperand(0);
8039 // Search for a use of the address operand that is an increment.
8040 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8041 Addr.getNode()->use_end(); UI != UE; ++UI) {
8043 if (User->getOpcode() != ISD::ADD
8044 || UI.getUse().getResNo() != Addr.getResNo())
8047 // Check that the add is independent of the load. Otherwise, folding it
8048 // would create a cycle.
8049 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8051 // Also check that add is not used in the vector operand. This would also
8053 if (User->isPredecessorOf(Vector.getNode()))
8056 // If the increment is a constant, it must match the memory ref size.
8057 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8058 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8059 uint32_t IncVal = CInc->getZExtValue();
8060 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8061 if (IncVal != NumBytes)
8063 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8066 SmallVector<SDValue, 8> Ops;
8067 Ops.push_back(LD->getOperand(0)); // Chain
8069 Ops.push_back(Vector); // The vector to be inserted
8070 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8072 Ops.push_back(Addr);
8075 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8076 SDVTList SDTys = DAG.getVTList(Tys);
8077 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8078 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8080 LoadSDN->getMemOperand());
8083 SmallVector<SDValue, 2> NewResults;
8084 NewResults.push_back(SDValue(LD, 0)); // The result of load
8085 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8086 DCI.CombineTo(LD, NewResults);
8087 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8088 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8095 /// Target-specific DAG combine function for NEON load/store intrinsics
8096 /// to merge base address updates.
8097 static SDValue performNEONPostLDSTCombine(SDNode *N,
8098 TargetLowering::DAGCombinerInfo &DCI,
8099 SelectionDAG &DAG) {
8100 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8103 unsigned AddrOpIdx = N->getNumOperands() - 1;
8104 SDValue Addr = N->getOperand(AddrOpIdx);
8106 // Search for a use of the address operand that is an increment.
8107 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8108 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8110 if (User->getOpcode() != ISD::ADD ||
8111 UI.getUse().getResNo() != Addr.getResNo())
8114 // Check that the add is independent of the load/store. Otherwise, folding
8115 // it would create a cycle.
8116 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8119 // Find the new opcode for the updating load/store.
8120 bool IsStore = false;
8121 bool IsLaneOp = false;
8122 bool IsDupOp = false;
8123 unsigned NewOpc = 0;
8124 unsigned NumVecs = 0;
8125 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8127 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8128 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8130 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8132 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8134 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8135 NumVecs = 2; IsStore = true; break;
8136 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8137 NumVecs = 3; IsStore = true; break;
8138 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8139 NumVecs = 4; IsStore = true; break;
8140 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8142 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8144 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8146 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8147 NumVecs = 2; IsStore = true; break;
8148 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8149 NumVecs = 3; IsStore = true; break;
8150 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8151 NumVecs = 4; IsStore = true; break;
8152 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8153 NumVecs = 2; IsDupOp = true; break;
8154 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8155 NumVecs = 3; IsDupOp = true; break;
8156 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8157 NumVecs = 4; IsDupOp = true; break;
8158 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8159 NumVecs = 2; IsLaneOp = true; break;
8160 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8161 NumVecs = 3; IsLaneOp = true; break;
8162 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8163 NumVecs = 4; IsLaneOp = true; break;
8164 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8165 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8166 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8167 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8168 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8169 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8174 VecTy = N->getOperand(2).getValueType();
8176 VecTy = N->getValueType(0);
8178 // If the increment is a constant, it must match the memory ref size.
8179 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8180 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8181 uint32_t IncVal = CInc->getZExtValue();
8182 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8183 if (IsLaneOp || IsDupOp)
8184 NumBytes /= VecTy.getVectorNumElements();
8185 if (IncVal != NumBytes)
8187 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8189 SmallVector<SDValue, 8> Ops;
8190 Ops.push_back(N->getOperand(0)); // Incoming chain
8191 // Load lane and store have vector list as input.
8192 if (IsLaneOp || IsStore)
8193 for (unsigned i = 2; i < AddrOpIdx; ++i)
8194 Ops.push_back(N->getOperand(i));
8195 Ops.push_back(Addr); // Base register
8200 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8202 for (n = 0; n < NumResultVecs; ++n)
8204 Tys[n++] = MVT::i64; // Type of write back register
8205 Tys[n] = MVT::Other; // Type of the chain
8206 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8208 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8209 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8210 MemInt->getMemoryVT(),
8211 MemInt->getMemOperand());
8214 std::vector<SDValue> NewResults;
8215 for (unsigned i = 0; i < NumResultVecs; ++i) {
8216 NewResults.push_back(SDValue(UpdN.getNode(), i));
8218 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8219 DCI.CombineTo(N, NewResults);
8220 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8227 // Checks to see if the value is the prescribed width and returns information
8228 // about its extension mode.
8230 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8231 ExtType = ISD::NON_EXTLOAD;
8232 switch(V.getNode()->getOpcode()) {
8236 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8237 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8238 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8239 ExtType = LoadNode->getExtensionType();
8244 case ISD::AssertSext: {
8245 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8246 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8247 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8248 ExtType = ISD::SEXTLOAD;
8253 case ISD::AssertZext: {
8254 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8255 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8256 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8257 ExtType = ISD::ZEXTLOAD;
8263 case ISD::TargetConstant: {
8264 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8274 // This function does a whole lot of voodoo to determine if the tests are
8275 // equivalent without and with a mask. Essentially what happens is that given a
8278 // +-------------+ +-------------+ +-------------+ +-------------+
8279 // | Input | | AddConstant | | CompConstant| | CC |
8280 // +-------------+ +-------------+ +-------------+ +-------------+
8282 // V V | +----------+
8283 // +-------------+ +----+ | |
8284 // | ADD | |0xff| | |
8285 // +-------------+ +----+ | |
8288 // +-------------+ | |
8290 // +-------------+ | |
8299 // The AND node may be safely removed for some combinations of inputs. In
8300 // particular we need to take into account the extension type of the Input,
8301 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8302 // width of the input (this can work for any width inputs, the above graph is
8303 // specific to 8 bits.
8305 // The specific equations were worked out by generating output tables for each
8306 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8307 // problem was simplified by working with 4 bit inputs, which means we only
8308 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8309 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8310 // patterns present in both extensions (0,7). For every distinct set of
8311 // AddConstant and CompConstants bit patterns we can consider the masked and
8312 // unmasked versions to be equivalent if the result of this function is true for
8313 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8316 // and w10, w8, #0x0f
8318 // cset w9, AArch64CC
8320 // cset w11, AArch64CC
8325 // Since the above function shows when the outputs are equivalent it defines
8326 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8327 // would be expensive to run during compiles. The equations below were written
8328 // in a test harness that confirmed they gave equivalent outputs to the above
8329 // for all inputs function, so they can be used determine if the removal is
8332 // isEquivalentMaskless() is the code for testing if the AND can be removed
8333 // factored out of the DAG recognition as the DAG can take several forms.
8336 bool isEquivalentMaskless(unsigned CC, unsigned width,
8337 ISD::LoadExtType ExtType, signed AddConstant,
8338 signed CompConstant) {
8339 // By being careful about our equations and only writing the in term
8340 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8341 // make them generally applicable to all bit widths.
8342 signed MaxUInt = (1 << width);
8344 // For the purposes of these comparisons sign extending the type is
8345 // equivalent to zero extending the add and displacing it by half the integer
8346 // width. Provided we are careful and make sure our equations are valid over
8347 // the whole range we can just adjust the input and avoid writing equations
8348 // for sign extended inputs.
8349 if (ExtType == ISD::SEXTLOAD)
8350 AddConstant -= (1 << (width-1));
8354 case AArch64CC::GT: {
8355 if ((AddConstant == 0) ||
8356 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8357 (AddConstant >= 0 && CompConstant < 0) ||
8358 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8362 case AArch64CC::GE: {
8363 if ((AddConstant == 0) ||
8364 (AddConstant >= 0 && CompConstant <= 0) ||
8365 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8369 case AArch64CC::LS: {
8370 if ((AddConstant >= 0 && CompConstant < 0) ||
8371 (AddConstant <= 0 && CompConstant >= -1 &&
8372 CompConstant < AddConstant + MaxUInt))
8376 case AArch64CC::MI: {
8377 if ((AddConstant == 0) ||
8378 (AddConstant > 0 && CompConstant <= 0) ||
8379 (AddConstant < 0 && CompConstant <= AddConstant))
8383 case AArch64CC::HS: {
8384 if ((AddConstant >= 0 && CompConstant <= 0) ||
8385 (AddConstant <= 0 && CompConstant >= 0 &&
8386 CompConstant <= AddConstant + MaxUInt))
8390 case AArch64CC::NE: {
8391 if ((AddConstant > 0 && CompConstant < 0) ||
8392 (AddConstant < 0 && CompConstant >= 0 &&
8393 CompConstant < AddConstant + MaxUInt) ||
8394 (AddConstant >= 0 && CompConstant >= 0 &&
8395 CompConstant >= AddConstant) ||
8396 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8405 case AArch64CC::Invalid:
8413 SDValue performCONDCombine(SDNode *N,
8414 TargetLowering::DAGCombinerInfo &DCI,
8415 SelectionDAG &DAG, unsigned CCIndex,
8416 unsigned CmpIndex) {
8417 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8418 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8419 unsigned CondOpcode = SubsNode->getOpcode();
8421 if (CondOpcode != AArch64ISD::SUBS)
8424 // There is a SUBS feeding this condition. Is it fed by a mask we can
8427 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8428 unsigned MaskBits = 0;
8430 if (AndNode->getOpcode() != ISD::AND)
8433 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8434 uint32_t CNV = CN->getZExtValue();
8437 else if (CNV == 65535)
8444 SDValue AddValue = AndNode->getOperand(0);
8446 if (AddValue.getOpcode() != ISD::ADD)
8449 // The basic dag structure is correct, grab the inputs and validate them.
8451 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8452 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8453 SDValue SubsInputValue = SubsNode->getOperand(1);
8455 // The mask is present and the provenance of all the values is a smaller type,
8456 // lets see if the mask is superfluous.
8458 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8459 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8462 ISD::LoadExtType ExtType;
8464 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8465 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8466 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8469 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8470 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8471 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8474 // The AND is not necessary, remove it.
8476 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8477 SubsNode->getValueType(1));
8478 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8480 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8481 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8483 return SDValue(N, 0);
8486 // Optimize compare with zero and branch.
8487 static SDValue performBRCONDCombine(SDNode *N,
8488 TargetLowering::DAGCombinerInfo &DCI,
8489 SelectionDAG &DAG) {
8490 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8493 SDValue Chain = N->getOperand(0);
8494 SDValue Dest = N->getOperand(1);
8495 SDValue CCVal = N->getOperand(2);
8496 SDValue Cmp = N->getOperand(3);
8498 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8499 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8500 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8503 unsigned CmpOpc = Cmp.getOpcode();
8504 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8507 // Only attempt folding if there is only one use of the flag and no use of the
8509 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8512 SDValue LHS = Cmp.getOperand(0);
8513 SDValue RHS = Cmp.getOperand(1);
8515 assert(LHS.getValueType() == RHS.getValueType() &&
8516 "Expected the value type to be the same for both operands!");
8517 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8520 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8521 std::swap(LHS, RHS);
8523 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8526 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8527 LHS.getOpcode() == ISD::SRL)
8530 // Fold the compare into the branch instruction.
8532 if (CC == AArch64CC::EQ)
8533 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8535 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8537 // Do not add new nodes to DAG combiner worklist.
8538 DCI.CombineTo(N, BR, false);
8543 // vselect (v1i1 setcc) ->
8544 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8545 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8546 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8548 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8549 SDValue N0 = N->getOperand(0);
8550 EVT CCVT = N0.getValueType();
8552 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8553 CCVT.getVectorElementType() != MVT::i1)
8556 EVT ResVT = N->getValueType(0);
8557 EVT CmpVT = N0.getOperand(0).getValueType();
8558 // Only combine when the result type is of the same size as the compared
8560 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8563 SDValue IfTrue = N->getOperand(1);
8564 SDValue IfFalse = N->getOperand(2);
8566 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8567 N0.getOperand(0), N0.getOperand(1),
8568 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8569 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8573 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8574 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8575 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8576 /// with a vector one followed by a DUP shuffle on the result.
8577 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8578 SDValue N0 = N->getOperand(0);
8579 EVT ResVT = N->getValueType(0);
8581 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8584 // If NumMaskElts == 0, the comparison is larger than select result. The
8585 // largest real NEON comparison is 64-bits per lane, which means the result is
8586 // at most 32-bits and an illegal vector. Just bail out for now.
8587 EVT SrcVT = N0.getOperand(0).getValueType();
8589 // Don't try to do this optimization when the setcc itself has i1 operands.
8590 // There are no legal vectors of i1, so this would be pointless.
8591 if (SrcVT == MVT::i1)
8594 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8595 if (!ResVT.isVector() || NumMaskElts == 0)
8598 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8599 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8601 // First perform a vector comparison, where lane 0 is the one we're interested
8605 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8607 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8608 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8610 // Now duplicate the comparison mask we want across all other lanes.
8611 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8612 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8613 Mask = DAG.getNode(ISD::BITCAST, DL,
8614 ResVT.changeVectorElementTypeToInteger(), Mask);
8616 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8619 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8620 DAGCombinerInfo &DCI) const {
8621 SelectionDAG &DAG = DCI.DAG;
8622 switch (N->getOpcode()) {
8627 return performAddSubLongCombine(N, DCI, DAG);
8629 return performXorCombine(N, DAG, DCI, Subtarget);
8631 return performMulCombine(N, DAG, DCI, Subtarget);
8632 case ISD::SINT_TO_FP:
8633 case ISD::UINT_TO_FP:
8634 return performIntToFpCombine(N, DAG, Subtarget);
8636 return performORCombine(N, DCI, Subtarget);
8637 case ISD::INTRINSIC_WO_CHAIN:
8638 return performIntrinsicCombine(N, DCI, Subtarget);
8639 case ISD::ANY_EXTEND:
8640 case ISD::ZERO_EXTEND:
8641 case ISD::SIGN_EXTEND:
8642 return performExtendCombine(N, DCI, DAG);
8644 return performBitcastCombine(N, DCI, DAG);
8645 case ISD::CONCAT_VECTORS:
8646 return performConcatVectorsCombine(N, DCI, DAG);
8648 return performSelectCombine(N, DAG);
8650 return performVSelectCombine(N, DCI.DAG);
8652 return performSTORECombine(N, DCI, DAG, Subtarget);
8653 case AArch64ISD::BRCOND:
8654 return performBRCONDCombine(N, DCI, DAG);
8655 case AArch64ISD::CSEL:
8656 return performCONDCombine(N, DCI, DAG, 2, 3);
8657 case AArch64ISD::DUP:
8658 return performPostLD1Combine(N, DCI, false);
8659 case ISD::INSERT_VECTOR_ELT:
8660 return performPostLD1Combine(N, DCI, true);
8661 case ISD::INTRINSIC_VOID:
8662 case ISD::INTRINSIC_W_CHAIN:
8663 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8664 case Intrinsic::aarch64_neon_ld2:
8665 case Intrinsic::aarch64_neon_ld3:
8666 case Intrinsic::aarch64_neon_ld4:
8667 case Intrinsic::aarch64_neon_ld1x2:
8668 case Intrinsic::aarch64_neon_ld1x3:
8669 case Intrinsic::aarch64_neon_ld1x4:
8670 case Intrinsic::aarch64_neon_ld2lane:
8671 case Intrinsic::aarch64_neon_ld3lane:
8672 case Intrinsic::aarch64_neon_ld4lane:
8673 case Intrinsic::aarch64_neon_ld2r:
8674 case Intrinsic::aarch64_neon_ld3r:
8675 case Intrinsic::aarch64_neon_ld4r:
8676 case Intrinsic::aarch64_neon_st2:
8677 case Intrinsic::aarch64_neon_st3:
8678 case Intrinsic::aarch64_neon_st4:
8679 case Intrinsic::aarch64_neon_st1x2:
8680 case Intrinsic::aarch64_neon_st1x3:
8681 case Intrinsic::aarch64_neon_st1x4:
8682 case Intrinsic::aarch64_neon_st2lane:
8683 case Intrinsic::aarch64_neon_st3lane:
8684 case Intrinsic::aarch64_neon_st4lane:
8685 return performNEONPostLDSTCombine(N, DCI, DAG);
8693 // Check if the return value is used as only a return value, as otherwise
8694 // we can't perform a tail-call. In particular, we need to check for
8695 // target ISD nodes that are returns and any other "odd" constructs
8696 // that the generic analysis code won't necessarily catch.
8697 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8698 SDValue &Chain) const {
8699 if (N->getNumValues() != 1)
8701 if (!N->hasNUsesOfValue(1, 0))
8704 SDValue TCChain = Chain;
8705 SDNode *Copy = *N->use_begin();
8706 if (Copy->getOpcode() == ISD::CopyToReg) {
8707 // If the copy has a glue operand, we conservatively assume it isn't safe to
8708 // perform a tail call.
8709 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8712 TCChain = Copy->getOperand(0);
8713 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8716 bool HasRet = false;
8717 for (SDNode *Node : Copy->uses()) {
8718 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8730 // Return whether the an instruction can potentially be optimized to a tail
8731 // call. This will cause the optimizers to attempt to move, or duplicate,
8732 // return instructions to help enable tail call optimizations for this
8734 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8735 if (!CI->isTailCall())
8741 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8743 ISD::MemIndexedMode &AM,
8745 SelectionDAG &DAG) const {
8746 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8749 Base = Op->getOperand(0);
8750 // All of the indexed addressing mode instructions take a signed
8751 // 9 bit immediate offset.
8752 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8753 int64_t RHSC = (int64_t)RHS->getZExtValue();
8754 if (RHSC >= 256 || RHSC <= -256)
8756 IsInc = (Op->getOpcode() == ISD::ADD);
8757 Offset = Op->getOperand(1);
8763 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8765 ISD::MemIndexedMode &AM,
8766 SelectionDAG &DAG) const {
8769 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8770 VT = LD->getMemoryVT();
8771 Ptr = LD->getBasePtr();
8772 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8773 VT = ST->getMemoryVT();
8774 Ptr = ST->getBasePtr();
8779 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8781 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8785 bool AArch64TargetLowering::getPostIndexedAddressParts(
8786 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8787 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8790 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8791 VT = LD->getMemoryVT();
8792 Ptr = LD->getBasePtr();
8793 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8794 VT = ST->getMemoryVT();
8795 Ptr = ST->getBasePtr();
8800 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8802 // Post-indexing updates the base, so it's not a valid transform
8803 // if that's not the same as the load's pointer.
8806 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8810 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8811 SelectionDAG &DAG) {
8813 SDValue Op = N->getOperand(0);
8815 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8819 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8820 DAG.getUNDEF(MVT::i32), Op,
8821 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8823 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8824 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8827 void AArch64TargetLowering::ReplaceNodeResults(
8828 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8829 switch (N->getOpcode()) {
8831 llvm_unreachable("Don't know how to custom expand this");
8833 ReplaceBITCASTResults(N, Results, DAG);
8835 case ISD::FP_TO_UINT:
8836 case ISD::FP_TO_SINT:
8837 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8838 // Let normal code take care of it by not adding anything to Results.
8843 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8847 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8848 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8849 // reciprocal if there are three or more FDIVs.
8850 return NumUsers > 2;
8853 TargetLoweringBase::LegalizeTypeAction
8854 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8855 MVT SVT = VT.getSimpleVT();
8856 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8857 // v4i16, v2i32 instead of to promote.
8858 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8859 || SVT == MVT::v1f32)
8860 return TypeWidenVector;
8862 return TargetLoweringBase::getPreferredVectorAction(VT);
8865 // Loads and stores less than 128-bits are already atomic; ones above that
8866 // are doomed anyway, so defer to the default libcall and blame the OS when
8868 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8869 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8873 // Loads and stores less than 128-bits are already atomic; ones above that
8874 // are doomed anyway, so defer to the default libcall and blame the OS when
8876 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8877 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8881 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8882 TargetLoweringBase::AtomicRMWExpansionKind
8883 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8884 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8885 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
8886 : AtomicRMWExpansionKind::None;
8889 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8893 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8894 AtomicOrdering Ord) const {
8895 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8896 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8897 bool IsAcquire = isAtLeastAcquire(Ord);
8899 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8900 // intrinsic must return {i64, i64} and we have to recombine them into a
8901 // single i128 here.
8902 if (ValTy->getPrimitiveSizeInBits() == 128) {
8904 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8905 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8907 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8908 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8910 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8911 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8912 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8913 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8914 return Builder.CreateOr(
8915 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8918 Type *Tys[] = { Addr->getType() };
8920 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8921 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8923 return Builder.CreateTruncOrBitCast(
8924 Builder.CreateCall(Ldxr, Addr),
8925 cast<PointerType>(Addr->getType())->getElementType());
8928 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8929 Value *Val, Value *Addr,
8930 AtomicOrdering Ord) const {
8931 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8932 bool IsRelease = isAtLeastRelease(Ord);
8934 // Since the intrinsics must have legal type, the i128 intrinsics take two
8935 // parameters: "i64, i64". We must marshal Val into the appropriate form
8937 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8939 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8940 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8941 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8943 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8944 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8945 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8946 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8950 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8951 Type *Tys[] = { Addr->getType() };
8952 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8954 return Builder.CreateCall2(
8955 Stxr, Builder.CreateZExtOrBitCast(
8956 Val, Stxr->getFunctionType()->getParamType(0)),
8960 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
8961 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
8962 return Ty->isArrayTy();