1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
32 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
33 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
35 if (Subtarget->isTargetLinux())
36 return new AArch64LinuxTargetObjectFile();
37 if (Subtarget->isTargetELF())
38 return new TargetLoweringObjectFileELF();
39 llvm_unreachable("unknown subtarget type");
43 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
44 : TargetLowering(TM, createTLOF(TM)),
45 Subtarget(&TM.getSubtarget<AArch64Subtarget>()),
46 RegInfo(TM.getRegisterInfo()),
47 Itins(TM.getInstrItineraryData()) {
49 // SIMD compares set the entire lane's bits to 1
50 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
52 // Scalar register <-> type mapping
53 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
54 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
55 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
56 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
57 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
58 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
60 computeRegisterProperties();
62 // Some atomic operations can be folded into load-acquire or store-release
63 // instructions on AArch64. It's marginally simpler to let LLVM expand
64 // everything out to a barrier and then recombine the (few) barriers we can.
65 setInsertFencesForAtomic(true);
66 setTargetDAGCombine(ISD::ATOMIC_FENCE);
67 setTargetDAGCombine(ISD::ATOMIC_STORE);
69 // We combine OR nodes for bitfield and NEON BSL operations.
70 setTargetDAGCombine(ISD::OR);
72 setTargetDAGCombine(ISD::AND);
73 setTargetDAGCombine(ISD::SRA);
75 // AArch64 does not have i1 loads, or much of anything for i1 really.
76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
80 setStackPointerRegisterToSaveRestore(AArch64::XSP);
81 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
82 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
83 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
85 // We'll lower globals to wrappers for selection.
86 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
87 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
89 // A64 instructions have the comparison predicate attached to the user of the
90 // result, but having a separate comparison is valuable for matching.
91 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
92 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
93 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
94 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
96 setOperationAction(ISD::SELECT, MVT::i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::i64, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
101 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
103 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
106 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
108 setOperationAction(ISD::SETCC, MVT::i32, Custom);
109 setOperationAction(ISD::SETCC, MVT::i64, Custom);
110 setOperationAction(ISD::SETCC, MVT::f32, Custom);
111 setOperationAction(ISD::SETCC, MVT::f64, Custom);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
115 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
117 setOperationAction(ISD::VASTART, MVT::Other, Custom);
118 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
119 setOperationAction(ISD::VAEND, MVT::Other, Expand);
120 setOperationAction(ISD::VAARG, MVT::Other, Expand);
122 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
124 setOperationAction(ISD::ROTL, MVT::i32, Expand);
125 setOperationAction(ISD::ROTL, MVT::i64, Expand);
127 setOperationAction(ISD::UREM, MVT::i32, Expand);
128 setOperationAction(ISD::UREM, MVT::i64, Expand);
129 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
130 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
132 setOperationAction(ISD::SREM, MVT::i32, Expand);
133 setOperationAction(ISD::SREM, MVT::i64, Expand);
134 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
135 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
137 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
138 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
140 // Legal floating-point operations.
141 setOperationAction(ISD::FABS, MVT::f32, Legal);
142 setOperationAction(ISD::FABS, MVT::f64, Legal);
144 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
145 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
147 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
148 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
150 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
151 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
153 setOperationAction(ISD::FNEG, MVT::f32, Legal);
154 setOperationAction(ISD::FNEG, MVT::f64, Legal);
156 setOperationAction(ISD::FRINT, MVT::f32, Legal);
157 setOperationAction(ISD::FRINT, MVT::f64, Legal);
159 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
160 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
162 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
165 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
166 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
167 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
169 // Illegal floating-point operations.
170 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
171 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
173 setOperationAction(ISD::FCOS, MVT::f32, Expand);
174 setOperationAction(ISD::FCOS, MVT::f64, Expand);
176 setOperationAction(ISD::FEXP, MVT::f32, Expand);
177 setOperationAction(ISD::FEXP, MVT::f64, Expand);
179 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
180 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
182 setOperationAction(ISD::FLOG, MVT::f32, Expand);
183 setOperationAction(ISD::FLOG, MVT::f64, Expand);
185 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
186 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
188 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
189 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
191 setOperationAction(ISD::FPOW, MVT::f32, Expand);
192 setOperationAction(ISD::FPOW, MVT::f64, Expand);
194 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
195 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
197 setOperationAction(ISD::FREM, MVT::f32, Expand);
198 setOperationAction(ISD::FREM, MVT::f64, Expand);
200 setOperationAction(ISD::FSIN, MVT::f32, Expand);
201 setOperationAction(ISD::FSIN, MVT::f64, Expand);
204 // Virtually no operation on f128 is legal, but LLVM can't expand them when
205 // there's a valid register class, so we need custom operations in most cases.
206 setOperationAction(ISD::FABS, MVT::f128, Expand);
207 setOperationAction(ISD::FADD, MVT::f128, Custom);
208 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
209 setOperationAction(ISD::FCOS, MVT::f128, Expand);
210 setOperationAction(ISD::FDIV, MVT::f128, Custom);
211 setOperationAction(ISD::FMA, MVT::f128, Expand);
212 setOperationAction(ISD::FMUL, MVT::f128, Custom);
213 setOperationAction(ISD::FNEG, MVT::f128, Expand);
214 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
215 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
216 setOperationAction(ISD::FPOW, MVT::f128, Expand);
217 setOperationAction(ISD::FREM, MVT::f128, Expand);
218 setOperationAction(ISD::FRINT, MVT::f128, Expand);
219 setOperationAction(ISD::FSIN, MVT::f128, Expand);
220 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
221 setOperationAction(ISD::FSUB, MVT::f128, Custom);
222 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
223 setOperationAction(ISD::SETCC, MVT::f128, Custom);
224 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
225 setOperationAction(ISD::SELECT, MVT::f128, Expand);
226 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
227 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
229 // Lowering for many of the conversions is actually specified by the non-f128
230 // type. The LowerXXX function will be trivial when f128 isn't involved.
231 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
232 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
233 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
234 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
235 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
236 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
237 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
238 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
239 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
240 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
241 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
242 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
243 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
244 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
246 // This prevents LLVM trying to compress double constants into a floating
247 // constant-pool entry and trying to load from there. It's of doubtful benefit
248 // for A64: we'd need LDR followed by FCVT, I believe.
249 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
250 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
251 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
253 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
254 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
255 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
256 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
257 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
258 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
260 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
261 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
263 setExceptionPointerRegister(AArch64::X0);
264 setExceptionSelectorRegister(AArch64::X1);
267 EVT AArch64TargetLowering::getSetCCResultType(EVT VT) const {
268 // It's reasonably important that this value matches the "natural" legal
269 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
270 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
271 if (!VT.isVector()) return MVT::i32;
272 return VT.changeVectorElementTypeToInteger();
275 static void getExclusiveOperation(unsigned Size, unsigned &ldrOpc,
278 default: llvm_unreachable("unsupported size for atomic binary op!");
280 ldrOpc = AArch64::LDXR_byte;
281 strOpc = AArch64::STXR_byte;
284 ldrOpc = AArch64::LDXR_hword;
285 strOpc = AArch64::STXR_hword;
288 ldrOpc = AArch64::LDXR_word;
289 strOpc = AArch64::STXR_word;
292 ldrOpc = AArch64::LDXR_dword;
293 strOpc = AArch64::STXR_dword;
299 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
301 unsigned BinOpcode) const {
302 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
303 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
305 const BasicBlock *LLVM_BB = BB->getBasicBlock();
306 MachineFunction *MF = BB->getParent();
307 MachineFunction::iterator It = BB;
310 unsigned dest = MI->getOperand(0).getReg();
311 unsigned ptr = MI->getOperand(1).getReg();
312 unsigned incr = MI->getOperand(2).getReg();
313 DebugLoc dl = MI->getDebugLoc();
315 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
317 unsigned ldrOpc, strOpc;
318 getExclusiveOperation(Size, ldrOpc, strOpc);
320 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
321 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
322 MF->insert(It, loopMBB);
323 MF->insert(It, exitMBB);
325 // Transfer the remainder of BB and its successor edges to exitMBB.
326 exitMBB->splice(exitMBB->begin(), BB,
327 llvm::next(MachineBasicBlock::iterator(MI)),
329 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
331 const TargetRegisterClass *TRC
332 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
333 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
337 // fallthrough --> loopMBB
338 BB->addSuccessor(loopMBB);
342 // <binop> scratch, dest, incr
343 // stxr stxr_status, scratch, ptr
344 // cmp stxr_status, #0
346 // fallthrough --> exitMBB
348 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
350 // All arithmetic operations we'll be creating are designed to take an extra
351 // shift or extend operand, which we can conveniently set to zero.
353 // Operand order needs to go the other way for NAND.
354 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
355 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
356 .addReg(incr).addReg(dest).addImm(0);
358 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
359 .addReg(dest).addReg(incr).addImm(0);
362 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
363 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
364 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
366 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
367 BuildMI(BB, dl, TII->get(AArch64::SUBwwi_lsl0_cmp))
368 .addReg(stxr_status).addImm(0);
369 BuildMI(BB, dl, TII->get(AArch64::Bcc))
370 .addImm(A64CC::NE).addMBB(loopMBB);
372 BB->addSuccessor(loopMBB);
373 BB->addSuccessor(exitMBB);
379 MI->eraseFromParent(); // The instruction is gone now.
385 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
386 MachineBasicBlock *BB,
389 A64CC::CondCodes Cond) const {
390 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
392 const BasicBlock *LLVM_BB = BB->getBasicBlock();
393 MachineFunction *MF = BB->getParent();
394 MachineFunction::iterator It = BB;
397 unsigned dest = MI->getOperand(0).getReg();
398 unsigned ptr = MI->getOperand(1).getReg();
399 unsigned incr = MI->getOperand(2).getReg();
400 unsigned oldval = dest;
401 DebugLoc dl = MI->getDebugLoc();
403 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
404 const TargetRegisterClass *TRC, *TRCsp;
406 TRC = &AArch64::GPR64RegClass;
407 TRCsp = &AArch64::GPR64xspRegClass;
409 TRC = &AArch64::GPR32RegClass;
410 TRCsp = &AArch64::GPR32wspRegClass;
413 unsigned ldrOpc, strOpc;
414 getExclusiveOperation(Size, ldrOpc, strOpc);
416 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
417 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
418 MF->insert(It, loopMBB);
419 MF->insert(It, exitMBB);
421 // Transfer the remainder of BB and its successor edges to exitMBB.
422 exitMBB->splice(exitMBB->begin(), BB,
423 llvm::next(MachineBasicBlock::iterator(MI)),
425 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
427 unsigned scratch = MRI.createVirtualRegister(TRC);
428 MRI.constrainRegClass(scratch, TRCsp);
432 // fallthrough --> loopMBB
433 BB->addSuccessor(loopMBB);
437 // cmp incr, dest (, sign extend if necessary)
438 // csel scratch, dest, incr, cond
439 // stxr stxr_status, scratch, ptr
440 // cmp stxr_status, #0
442 // fallthrough --> exitMBB
444 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
446 // Build compare and cmov instructions.
447 MRI.constrainRegClass(incr, TRCsp);
448 BuildMI(BB, dl, TII->get(CmpOp))
449 .addReg(incr).addReg(oldval).addImm(0);
451 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
453 .addReg(oldval).addReg(incr).addImm(Cond);
455 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
456 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
458 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
459 .addReg(scratch).addReg(ptr);
460 BuildMI(BB, dl, TII->get(AArch64::SUBwwi_lsl0_cmp))
461 .addReg(stxr_status).addImm(0);
462 BuildMI(BB, dl, TII->get(AArch64::Bcc))
463 .addImm(A64CC::NE).addMBB(loopMBB);
465 BB->addSuccessor(loopMBB);
466 BB->addSuccessor(exitMBB);
472 MI->eraseFromParent(); // The instruction is gone now.
478 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
479 MachineBasicBlock *BB,
480 unsigned Size) const {
481 unsigned dest = MI->getOperand(0).getReg();
482 unsigned ptr = MI->getOperand(1).getReg();
483 unsigned oldval = MI->getOperand(2).getReg();
484 unsigned newval = MI->getOperand(3).getReg();
485 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
486 DebugLoc dl = MI->getDebugLoc();
488 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
489 const TargetRegisterClass *TRCsp;
490 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
492 unsigned ldrOpc, strOpc;
493 getExclusiveOperation(Size, ldrOpc, strOpc);
495 MachineFunction *MF = BB->getParent();
496 const BasicBlock *LLVM_BB = BB->getBasicBlock();
497 MachineFunction::iterator It = BB;
498 ++It; // insert the new blocks after the current block
500 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
501 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
502 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
503 MF->insert(It, loop1MBB);
504 MF->insert(It, loop2MBB);
505 MF->insert(It, exitMBB);
507 // Transfer the remainder of BB and its successor edges to exitMBB.
508 exitMBB->splice(exitMBB->begin(), BB,
509 llvm::next(MachineBasicBlock::iterator(MI)),
511 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
515 // fallthrough --> loop1MBB
516 BB->addSuccessor(loop1MBB);
523 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
525 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
526 MRI.constrainRegClass(dest, TRCsp);
527 BuildMI(BB, dl, TII->get(CmpOp))
528 .addReg(dest).addReg(oldval).addImm(0);
529 BuildMI(BB, dl, TII->get(AArch64::Bcc))
530 .addImm(A64CC::NE).addMBB(exitMBB);
531 BB->addSuccessor(loop2MBB);
532 BB->addSuccessor(exitMBB);
535 // strex stxr_status, newval, [ptr]
536 // cmp stxr_status, #0
539 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
540 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
542 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
543 BuildMI(BB, dl, TII->get(AArch64::SUBwwi_lsl0_cmp))
544 .addReg(stxr_status).addImm(0);
545 BuildMI(BB, dl, TII->get(AArch64::Bcc))
546 .addImm(A64CC::NE).addMBB(loop1MBB);
547 BB->addSuccessor(loop1MBB);
548 BB->addSuccessor(exitMBB);
554 MI->eraseFromParent(); // The instruction is gone now.
560 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
561 MachineBasicBlock *MBB) const {
562 // We materialise the F128CSEL pseudo-instruction using conditional branches
563 // and loads, giving an instruciton sequence like:
572 // Using virtual registers would probably not be beneficial since COPY
573 // instructions are expensive for f128 (there's no actual instruction to
576 // An alternative would be to do an integer-CSEL on some address. E.g.:
581 // csel x0, x0, x1, ne
584 // It's unclear which approach is actually optimal.
585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
586 MachineFunction *MF = MBB->getParent();
587 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
588 DebugLoc DL = MI->getDebugLoc();
589 MachineFunction::iterator It = MBB;
592 unsigned DestReg = MI->getOperand(0).getReg();
593 unsigned IfTrueReg = MI->getOperand(1).getReg();
594 unsigned IfFalseReg = MI->getOperand(2).getReg();
595 unsigned CondCode = MI->getOperand(3).getImm();
596 bool NZCVKilled = MI->getOperand(4).isKill();
598 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
599 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
600 MF->insert(It, TrueBB);
601 MF->insert(It, EndBB);
603 // Transfer rest of current basic-block to EndBB
604 EndBB->splice(EndBB->begin(), MBB,
605 llvm::next(MachineBasicBlock::iterator(MI)),
607 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
609 // We need somewhere to store the f128 value needed.
610 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
612 // [... start of incoming MBB ...]
613 // str qIFFALSE, [sp]
616 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
618 .addFrameIndex(ScratchFI)
620 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
623 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
625 MBB->addSuccessor(TrueBB);
626 MBB->addSuccessor(EndBB);
630 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
632 .addFrameIndex(ScratchFI)
635 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
637 TrueBB->addSuccessor(EndBB);
641 // [... rest of incoming MBB ...]
643 EndBB->addLiveIn(AArch64::NZCV);
644 MachineInstr *StartOfEnd = EndBB->begin();
645 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
646 .addFrameIndex(ScratchFI)
649 MI->eraseFromParent();
654 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
655 MachineBasicBlock *MBB) const {
656 switch (MI->getOpcode()) {
657 default: llvm_unreachable("Unhandled instruction with custom inserter");
658 case AArch64::F128CSEL:
659 return EmitF128CSEL(MI, MBB);
660 case AArch64::ATOMIC_LOAD_ADD_I8:
661 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
662 case AArch64::ATOMIC_LOAD_ADD_I16:
663 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
664 case AArch64::ATOMIC_LOAD_ADD_I32:
665 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
666 case AArch64::ATOMIC_LOAD_ADD_I64:
667 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
669 case AArch64::ATOMIC_LOAD_SUB_I8:
670 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
671 case AArch64::ATOMIC_LOAD_SUB_I16:
672 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
673 case AArch64::ATOMIC_LOAD_SUB_I32:
674 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
675 case AArch64::ATOMIC_LOAD_SUB_I64:
676 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
678 case AArch64::ATOMIC_LOAD_AND_I8:
679 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
680 case AArch64::ATOMIC_LOAD_AND_I16:
681 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
682 case AArch64::ATOMIC_LOAD_AND_I32:
683 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
684 case AArch64::ATOMIC_LOAD_AND_I64:
685 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
687 case AArch64::ATOMIC_LOAD_OR_I8:
688 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
689 case AArch64::ATOMIC_LOAD_OR_I16:
690 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
691 case AArch64::ATOMIC_LOAD_OR_I32:
692 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
693 case AArch64::ATOMIC_LOAD_OR_I64:
694 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
696 case AArch64::ATOMIC_LOAD_XOR_I8:
697 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
698 case AArch64::ATOMIC_LOAD_XOR_I16:
699 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
700 case AArch64::ATOMIC_LOAD_XOR_I32:
701 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
702 case AArch64::ATOMIC_LOAD_XOR_I64:
703 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
705 case AArch64::ATOMIC_LOAD_NAND_I8:
706 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
707 case AArch64::ATOMIC_LOAD_NAND_I16:
708 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
709 case AArch64::ATOMIC_LOAD_NAND_I32:
710 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
711 case AArch64::ATOMIC_LOAD_NAND_I64:
712 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
714 case AArch64::ATOMIC_LOAD_MIN_I8:
715 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
716 case AArch64::ATOMIC_LOAD_MIN_I16:
717 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
718 case AArch64::ATOMIC_LOAD_MIN_I32:
719 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
720 case AArch64::ATOMIC_LOAD_MIN_I64:
721 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
723 case AArch64::ATOMIC_LOAD_MAX_I8:
724 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
725 case AArch64::ATOMIC_LOAD_MAX_I16:
726 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
727 case AArch64::ATOMIC_LOAD_MAX_I32:
728 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
729 case AArch64::ATOMIC_LOAD_MAX_I64:
730 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
732 case AArch64::ATOMIC_LOAD_UMIN_I8:
733 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
734 case AArch64::ATOMIC_LOAD_UMIN_I16:
735 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
736 case AArch64::ATOMIC_LOAD_UMIN_I32:
737 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
738 case AArch64::ATOMIC_LOAD_UMIN_I64:
739 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
741 case AArch64::ATOMIC_LOAD_UMAX_I8:
742 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
743 case AArch64::ATOMIC_LOAD_UMAX_I16:
744 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
745 case AArch64::ATOMIC_LOAD_UMAX_I32:
746 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
747 case AArch64::ATOMIC_LOAD_UMAX_I64:
748 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
750 case AArch64::ATOMIC_SWAP_I8:
751 return emitAtomicBinary(MI, MBB, 1, 0);
752 case AArch64::ATOMIC_SWAP_I16:
753 return emitAtomicBinary(MI, MBB, 2, 0);
754 case AArch64::ATOMIC_SWAP_I32:
755 return emitAtomicBinary(MI, MBB, 4, 0);
756 case AArch64::ATOMIC_SWAP_I64:
757 return emitAtomicBinary(MI, MBB, 8, 0);
759 case AArch64::ATOMIC_CMP_SWAP_I8:
760 return emitAtomicCmpSwap(MI, MBB, 1);
761 case AArch64::ATOMIC_CMP_SWAP_I16:
762 return emitAtomicCmpSwap(MI, MBB, 2);
763 case AArch64::ATOMIC_CMP_SWAP_I32:
764 return emitAtomicCmpSwap(MI, MBB, 4);
765 case AArch64::ATOMIC_CMP_SWAP_I64:
766 return emitAtomicCmpSwap(MI, MBB, 8);
771 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
773 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
774 case AArch64ISD::Call: return "AArch64ISD::Call";
775 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
776 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
777 case AArch64ISD::BFI: return "AArch64ISD::BFI";
778 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
779 case AArch64ISD::Ret: return "AArch64ISD::Ret";
780 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
781 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
782 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
783 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
784 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
785 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
786 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
788 default: return NULL;
792 static const uint16_t AArch64FPRArgRegs[] = {
793 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
794 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
796 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
798 static const uint16_t AArch64ArgRegs[] = {
799 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
800 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
802 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
804 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
805 CCValAssign::LocInfo LocInfo,
806 ISD::ArgFlagsTy ArgFlags, CCState &State) {
807 // Mark all remaining general purpose registers as allocated. We don't
808 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
809 // i64 will go in registers (C.11).
810 for (unsigned i = 0; i < NumArgRegs; ++i)
811 State.AllocateReg(AArch64ArgRegs[i]);
816 #include "AArch64GenCallingConv.inc"
818 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
821 default: llvm_unreachable("Unsupported calling convention");
822 case CallingConv::Fast:
829 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
830 DebugLoc DL, SDValue &Chain) const {
831 MachineFunction &MF = DAG.getMachineFunction();
832 MachineFrameInfo *MFI = MF.getFrameInfo();
833 AArch64MachineFunctionInfo *FuncInfo
834 = MF.getInfo<AArch64MachineFunctionInfo>();
836 SmallVector<SDValue, 8> MemOps;
838 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
840 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
843 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
845 if (GPRSaveSize != 0) {
846 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
848 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
850 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
851 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
852 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
853 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
854 MachinePointerInfo::getStack(i * 8),
856 MemOps.push_back(Store);
857 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
858 DAG.getConstant(8, getPointerTy()));
862 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
864 if (FPRSaveSize != 0) {
865 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
867 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
869 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
870 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
871 &AArch64::FPR128RegClass);
872 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
873 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
874 MachinePointerInfo::getStack(i * 16),
876 MemOps.push_back(Store);
877 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
878 DAG.getConstant(16, getPointerTy()));
882 int StackIdx = MFI->CreateFixedObject(8, CCInfo.getNextStackOffset(), true);
884 FuncInfo->setVariadicStackIdx(StackIdx);
885 FuncInfo->setVariadicGPRIdx(GPRIdx);
886 FuncInfo->setVariadicGPRSize(GPRSaveSize);
887 FuncInfo->setVariadicFPRIdx(FPRIdx);
888 FuncInfo->setVariadicFPRSize(FPRSaveSize);
890 if (!MemOps.empty()) {
891 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
898 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
899 CallingConv::ID CallConv, bool isVarArg,
900 const SmallVectorImpl<ISD::InputArg> &Ins,
901 DebugLoc dl, SelectionDAG &DAG,
902 SmallVectorImpl<SDValue> &InVals) const {
903 MachineFunction &MF = DAG.getMachineFunction();
904 AArch64MachineFunctionInfo *FuncInfo
905 = MF.getInfo<AArch64MachineFunctionInfo>();
906 MachineFrameInfo *MFI = MF.getFrameInfo();
907 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
909 SmallVector<CCValAssign, 16> ArgLocs;
910 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
911 getTargetMachine(), ArgLocs, *DAG.getContext());
912 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
914 SmallVector<SDValue, 16> ArgValues;
917 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
918 CCValAssign &VA = ArgLocs[i];
919 ISD::ArgFlagsTy Flags = Ins[i].Flags;
921 if (Flags.isByVal()) {
922 // Byval is used for small structs and HFAs in the PCS, but the system
923 // should work in a non-compliant manner for larger structs.
924 EVT PtrTy = getPointerTy();
925 int Size = Flags.getByValSize();
926 unsigned NumRegs = (Size + 7) / 8;
928 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
929 VA.getLocMemOffset(),
931 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
932 InVals.push_back(FrameIdxN);
935 } else if (VA.isRegLoc()) {
936 MVT RegVT = VA.getLocVT();
937 const TargetRegisterClass *RC = getRegClassFor(RegVT);
938 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
940 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
941 } else { // VA.isRegLoc()
942 assert(VA.isMemLoc());
944 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
945 VA.getLocMemOffset(), true);
947 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
948 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
949 MachinePointerInfo::getFixedStack(FI),
950 false, false, false, 0);
955 switch (VA.getLocInfo()) {
956 default: llvm_unreachable("Unknown loc info!");
957 case CCValAssign::Full: break;
958 case CCValAssign::BCvt:
959 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
961 case CCValAssign::SExt:
962 case CCValAssign::ZExt:
963 case CCValAssign::AExt: {
964 unsigned DestSize = VA.getValVT().getSizeInBits();
968 case 8: DestSubReg = AArch64::sub_8; break;
969 case 16: DestSubReg = AArch64::sub_16; break;
970 case 32: DestSubReg = AArch64::sub_32; break;
971 case 64: DestSubReg = AArch64::sub_64; break;
972 default: llvm_unreachable("Unexpected argument promotion");
975 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
976 VA.getValVT(), ArgValue,
977 DAG.getTargetConstant(DestSubReg, MVT::i32)),
983 InVals.push_back(ArgValue);
987 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
989 unsigned StackArgSize = CCInfo.getNextStackOffset();
990 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
991 // This is a non-standard ABI so by fiat I say we're allowed to make full
992 // use of the stack area to be popped, which must be aligned to 16 bytes in
994 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
996 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
998 FuncInfo->setArgumentStackToRestore(StackArgSize);
1000 // This realignment carries over to the available bytes below. Our own
1001 // callers will guarantee the space is free by giving an aligned value to
1004 // Even if we're not expected to free up the space, it's useful to know how
1005 // much is there while considering tail calls (because we can reuse it).
1006 FuncInfo->setBytesInStackArgArea(StackArgSize);
1012 AArch64TargetLowering::LowerReturn(SDValue Chain,
1013 CallingConv::ID CallConv, bool isVarArg,
1014 const SmallVectorImpl<ISD::OutputArg> &Outs,
1015 const SmallVectorImpl<SDValue> &OutVals,
1016 DebugLoc dl, SelectionDAG &DAG) const {
1017 // CCValAssign - represent the assignment of the return value to a location.
1018 SmallVector<CCValAssign, 16> RVLocs;
1020 // CCState - Info about the registers and stack slots.
1021 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1022 getTargetMachine(), RVLocs, *DAG.getContext());
1024 // Analyze outgoing return values.
1025 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1028 SmallVector<SDValue, 4> RetOps(1, Chain);
1030 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1031 // PCS: "If the type, T, of the result of a function is such that
1032 // void func(T arg) would require that arg be passed as a value in a
1033 // register (or set of registers) according to the rules in 5.4, then the
1034 // result is returned in the same registers as would be used for such an
1037 // Otherwise, the caller shall reserve a block of memory of sufficient
1038 // size and alignment to hold the result. The address of the memory block
1039 // shall be passed as an additional argument to the function in x8."
1041 // This is implemented in two places. The register-return values are dealt
1042 // with here, more complex returns are passed as an sret parameter, which
1043 // means we don't have to worry about it during actual return.
1044 CCValAssign &VA = RVLocs[i];
1045 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1048 SDValue Arg = OutVals[i];
1050 // There's no convenient note in the ABI about this as there is for normal
1051 // arguments, but it says return values are passed in the same registers as
1052 // an argument would be. I believe that includes the comments about
1053 // unspecified higher bits, putting the burden of widening on the *caller*
1054 // for return values.
1055 switch (VA.getLocInfo()) {
1056 default: llvm_unreachable("Unknown loc info");
1057 case CCValAssign::Full: break;
1058 case CCValAssign::SExt:
1059 case CCValAssign::ZExt:
1060 case CCValAssign::AExt:
1061 // Floating-point values should only be extended when they're going into
1062 // memory, which can't happen here so an integer extend is acceptable.
1063 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1065 case CCValAssign::BCvt:
1066 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1070 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1071 Flag = Chain.getValue(1);
1072 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1075 RetOps[0] = Chain; // Update chain.
1077 // Add the flag if we have it.
1079 RetOps.push_back(Flag);
1081 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1082 &RetOps[0], RetOps.size());
1086 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1087 SmallVectorImpl<SDValue> &InVals) const {
1088 SelectionDAG &DAG = CLI.DAG;
1089 DebugLoc &dl = CLI.DL;
1090 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
1091 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
1092 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
1093 SDValue Chain = CLI.Chain;
1094 SDValue Callee = CLI.Callee;
1095 bool &IsTailCall = CLI.IsTailCall;
1096 CallingConv::ID CallConv = CLI.CallConv;
1097 bool IsVarArg = CLI.IsVarArg;
1099 MachineFunction &MF = DAG.getMachineFunction();
1100 AArch64MachineFunctionInfo *FuncInfo
1101 = MF.getInfo<AArch64MachineFunctionInfo>();
1102 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1103 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1104 bool IsSibCall = false;
1107 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1108 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1109 Outs, OutVals, Ins, DAG);
1111 // A sibling call is one where we're under the usual C ABI and not planning
1112 // to change that but can still do a tail call:
1113 if (!TailCallOpt && IsTailCall)
1117 SmallVector<CCValAssign, 16> ArgLocs;
1118 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1119 getTargetMachine(), ArgLocs, *DAG.getContext());
1120 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1122 // On AArch64 (and all other architectures I'm aware of) the most this has to
1123 // do is adjust the stack pointer.
1124 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1126 // Since we're not changing the ABI to make this a tail call, the memory
1127 // operands are already available in the caller's incoming argument space.
1131 // FPDiff is the byte offset of the call's argument area from the callee's.
1132 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1133 // by this amount for a tail call. In a sibling call it must be 0 because the
1134 // caller will deallocate the entire stack and the callee still expects its
1135 // arguments to begin at SP+0. Completely unused for non-tail calls.
1138 if (IsTailCall && !IsSibCall) {
1139 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1141 // FPDiff will be negative if this tail call requires more space than we
1142 // would automatically have in our incoming argument space. Positive if we
1143 // can actually shrink the stack.
1144 FPDiff = NumReusableBytes - NumBytes;
1146 // The stack pointer must be 16-byte aligned at all times it's used for a
1147 // memory operation, which in practice means at *all* times and in
1148 // particular across call boundaries. Therefore our own arguments started at
1149 // a 16-byte aligned SP and the delta applied for the tail call should
1150 // satisfy the same constraint.
1151 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1155 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1157 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1160 SmallVector<SDValue, 8> MemOpChains;
1161 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1164 CCValAssign &VA = ArgLocs[i];
1165 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1166 SDValue Arg = OutVals[i];
1168 // Callee does the actual widening, so all extensions just use an implicit
1169 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1170 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1171 // alternative works on integer types too.
1172 switch (VA.getLocInfo()) {
1173 default: llvm_unreachable("Unknown loc info!");
1174 case CCValAssign::Full: break;
1175 case CCValAssign::SExt:
1176 case CCValAssign::ZExt:
1177 case CCValAssign::AExt: {
1178 unsigned SrcSize = VA.getValVT().getSizeInBits();
1182 case 8: SrcSubReg = AArch64::sub_8; break;
1183 case 16: SrcSubReg = AArch64::sub_16; break;
1184 case 32: SrcSubReg = AArch64::sub_32; break;
1185 case 64: SrcSubReg = AArch64::sub_64; break;
1186 default: llvm_unreachable("Unexpected argument promotion");
1189 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1191 DAG.getUNDEF(VA.getLocVT()),
1193 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1198 case CCValAssign::BCvt:
1199 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1203 if (VA.isRegLoc()) {
1204 // A normal register (sub-) argument. For now we just note it down because
1205 // we want to copy things into registers as late as possible to avoid
1206 // register-pressure (and possibly worse).
1207 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1211 assert(VA.isMemLoc() && "unexpected argument location");
1214 MachinePointerInfo DstInfo;
1216 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1217 VA.getLocVT().getSizeInBits();
1218 OpSize = (OpSize + 7) / 8;
1219 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1220 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1222 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1223 DstInfo = MachinePointerInfo::getFixedStack(FI);
1225 // Make sure any stack arguments overlapping with where we're storing are
1226 // loaded before this eventual operation. Otherwise they'll be clobbered.
1227 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1229 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1231 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1232 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1235 if (Flags.isByVal()) {
1236 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1237 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1238 Flags.getByValAlign(),
1239 /*isVolatile = */ false,
1240 /*alwaysInline = */ false,
1241 DstInfo, MachinePointerInfo(0));
1242 MemOpChains.push_back(Cpy);
1244 // Normal stack argument, put it where it's needed.
1245 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1247 MemOpChains.push_back(Store);
1251 // The loads and stores generated above shouldn't clash with each
1252 // other. Combining them with this TokenFactor notes that fact for the rest of
1254 if (!MemOpChains.empty())
1255 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1256 &MemOpChains[0], MemOpChains.size());
1258 // Most of the rest of the instructions need to be glued together; we don't
1259 // want assignments to actual registers used by a call to be rearranged by a
1260 // well-meaning scheduler.
1263 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1264 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1265 RegsToPass[i].second, InFlag);
1266 InFlag = Chain.getValue(1);
1269 // The linker is responsible for inserting veneers when necessary to put a
1270 // function call destination in range, so we don't need to bother with a
1272 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1273 const GlobalValue *GV = G->getGlobal();
1274 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1275 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1276 const char *Sym = S->getSymbol();
1277 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1280 // We don't usually want to end the call-sequence here because we would tidy
1281 // the frame up *after* the call, however in the ABI-changing tail-call case
1282 // we've carefully laid out the parameters so that when sp is reset they'll be
1283 // in the correct location.
1284 if (IsTailCall && !IsSibCall) {
1285 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1286 DAG.getIntPtrConstant(0, true), InFlag);
1287 InFlag = Chain.getValue(1);
1290 // We produce the following DAG scheme for the actual call instruction:
1291 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1293 // Most arguments aren't going to be used and just keep the values live as
1294 // far as LLVM is concerned. It's expected to be selected as simply "bl
1295 // callee" (for a direct, non-tail call).
1296 std::vector<SDValue> Ops;
1297 Ops.push_back(Chain);
1298 Ops.push_back(Callee);
1301 // Each tail call may have to adjust the stack by a different amount, so
1302 // this information must travel along with the operation for eventual
1303 // consumption by emitEpilogue.
1304 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1307 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1308 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1309 RegsToPass[i].second.getValueType()));
1312 // Add a register mask operand representing the call-preserved registers. This
1313 // is used later in codegen to constrain register-allocation.
1314 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1315 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1316 assert(Mask && "Missing call preserved mask for calling convention");
1317 Ops.push_back(DAG.getRegisterMask(Mask));
1319 // If we needed glue, put it in as the last argument.
1320 if (InFlag.getNode())
1321 Ops.push_back(InFlag);
1323 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1326 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1329 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1330 InFlag = Chain.getValue(1);
1332 // Now we can reclaim the stack, just as well do it before working out where
1333 // our return value is.
1335 uint64_t CalleePopBytes
1336 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1338 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1339 DAG.getIntPtrConstant(CalleePopBytes, true),
1341 InFlag = Chain.getValue(1);
1344 return LowerCallResult(Chain, InFlag, CallConv,
1345 IsVarArg, Ins, dl, DAG, InVals);
1349 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1350 CallingConv::ID CallConv, bool IsVarArg,
1351 const SmallVectorImpl<ISD::InputArg> &Ins,
1352 DebugLoc dl, SelectionDAG &DAG,
1353 SmallVectorImpl<SDValue> &InVals) const {
1354 // Assign locations to each value returned by this call.
1355 SmallVector<CCValAssign, 16> RVLocs;
1356 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1357 getTargetMachine(), RVLocs, *DAG.getContext());
1358 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1360 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1361 CCValAssign VA = RVLocs[i];
1363 // Return values that are too big to fit into registers should use an sret
1364 // pointer, so this can be a lot simpler than the main argument code.
1365 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1367 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1369 Chain = Val.getValue(1);
1370 InFlag = Val.getValue(2);
1372 switch (VA.getLocInfo()) {
1373 default: llvm_unreachable("Unknown loc info!");
1374 case CCValAssign::Full: break;
1375 case CCValAssign::BCvt:
1376 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1378 case CCValAssign::ZExt:
1379 case CCValAssign::SExt:
1380 case CCValAssign::AExt:
1381 // Floating-point arguments only get extended/truncated if they're going
1382 // in memory, so using the integer operation is acceptable here.
1383 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1387 InVals.push_back(Val);
1394 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1395 CallingConv::ID CalleeCC,
1397 bool IsCalleeStructRet,
1398 bool IsCallerStructRet,
1399 const SmallVectorImpl<ISD::OutputArg> &Outs,
1400 const SmallVectorImpl<SDValue> &OutVals,
1401 const SmallVectorImpl<ISD::InputArg> &Ins,
1402 SelectionDAG& DAG) const {
1404 // For CallingConv::C this function knows whether the ABI needs
1405 // changing. That's not true for other conventions so they will have to opt in
1407 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1410 const MachineFunction &MF = DAG.getMachineFunction();
1411 const Function *CallerF = MF.getFunction();
1412 CallingConv::ID CallerCC = CallerF->getCallingConv();
1413 bool CCMatch = CallerCC == CalleeCC;
1415 // Byval parameters hand the function a pointer directly into the stack area
1416 // we want to reuse during a tail call. Working around this *is* possible (see
1417 // X86) but less efficient and uglier in LowerCall.
1418 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1419 e = CallerF->arg_end(); i != e; ++i)
1420 if (i->hasByValAttr())
1423 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1424 if (IsTailCallConvention(CalleeCC) && CCMatch)
1429 // Now we search for cases where we can use a tail call without changing the
1430 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1433 // I want anyone implementing a new calling convention to think long and hard
1434 // about this assert.
1435 assert((!IsVarArg || CalleeCC == CallingConv::C)
1436 && "Unexpected variadic calling convention");
1438 if (IsVarArg && !Outs.empty()) {
1439 // At least two cases here: if caller is fastcc then we can't have any
1440 // memory arguments (we'd be expected to clean up the stack afterwards). If
1441 // caller is C then we could potentially use its argument area.
1443 // FIXME: for now we take the most conservative of these in both cases:
1444 // disallow all variadic memory operands.
1445 SmallVector<CCValAssign, 16> ArgLocs;
1446 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1447 getTargetMachine(), ArgLocs, *DAG.getContext());
1449 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1450 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1451 if (!ArgLocs[i].isRegLoc())
1455 // If the calling conventions do not match, then we'd better make sure the
1456 // results are returned in the same way as what the caller expects.
1458 SmallVector<CCValAssign, 16> RVLocs1;
1459 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1460 getTargetMachine(), RVLocs1, *DAG.getContext());
1461 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1463 SmallVector<CCValAssign, 16> RVLocs2;
1464 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1465 getTargetMachine(), RVLocs2, *DAG.getContext());
1466 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1468 if (RVLocs1.size() != RVLocs2.size())
1470 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1471 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1473 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1475 if (RVLocs1[i].isRegLoc()) {
1476 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1479 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1485 // Nothing more to check if the callee is taking no arguments
1489 SmallVector<CCValAssign, 16> ArgLocs;
1490 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1491 getTargetMachine(), ArgLocs, *DAG.getContext());
1493 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1495 const AArch64MachineFunctionInfo *FuncInfo
1496 = MF.getInfo<AArch64MachineFunctionInfo>();
1498 // If the stack arguments for this call would fit into our own save area then
1499 // the call can be made tail.
1500 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1503 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1504 bool TailCallOpt) const {
1505 return CallCC == CallingConv::Fast && TailCallOpt;
1508 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1509 return CallCC == CallingConv::Fast;
1512 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1514 MachineFrameInfo *MFI,
1515 int ClobberedFI) const {
1516 SmallVector<SDValue, 8> ArgChains;
1517 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1518 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1520 // Include the original chain at the beginning of the list. When this is
1521 // used by target LowerCall hooks, this helps legalize find the
1522 // CALLSEQ_BEGIN node.
1523 ArgChains.push_back(Chain);
1525 // Add a chain value for each stack argument corresponding
1526 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1527 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1528 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1529 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1530 if (FI->getIndex() < 0) {
1531 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1532 int64_t InLastByte = InFirstByte;
1533 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1535 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1536 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1537 ArgChains.push_back(SDValue(L, 1));
1540 // Build a tokenfactor for all the chains.
1541 return DAG.getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
1542 &ArgChains[0], ArgChains.size());
1545 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1547 case ISD::SETEQ: return A64CC::EQ;
1548 case ISD::SETGT: return A64CC::GT;
1549 case ISD::SETGE: return A64CC::GE;
1550 case ISD::SETLT: return A64CC::LT;
1551 case ISD::SETLE: return A64CC::LE;
1552 case ISD::SETNE: return A64CC::NE;
1553 case ISD::SETUGT: return A64CC::HI;
1554 case ISD::SETUGE: return A64CC::HS;
1555 case ISD::SETULT: return A64CC::LO;
1556 case ISD::SETULE: return A64CC::LS;
1557 default: llvm_unreachable("Unexpected condition code");
1561 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1562 // icmp is implemented using adds/subs immediate, which take an unsigned
1563 // 12-bit immediate, optionally shifted left by 12 bits.
1565 // Symmetric by using adds/subs
1569 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1572 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1573 ISD::CondCode CC, SDValue &A64cc,
1574 SelectionDAG &DAG, DebugLoc &dl) const {
1575 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1577 EVT VT = RHSC->getValueType(0);
1578 bool knownInvalid = false;
1580 // I'm not convinced the rest of LLVM handles these edge cases properly, but
1581 // we can at least get it right.
1582 if (isSignedIntSetCC(CC)) {
1583 C = RHSC->getSExtValue();
1584 } else if (RHSC->getZExtValue() > INT64_MAX) {
1585 // A 64-bit constant not representable by a signed 64-bit integer is far
1586 // too big to fit into a SUBS immediate anyway.
1587 knownInvalid = true;
1589 C = RHSC->getZExtValue();
1592 if (!knownInvalid && !isLegalICmpImmediate(C)) {
1593 // Constant does not fit, try adjusting it by one?
1598 if (isLegalICmpImmediate(C-1)) {
1599 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1600 RHS = DAG.getConstant(C-1, VT);
1605 if (isLegalICmpImmediate(C-1)) {
1606 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1607 RHS = DAG.getConstant(C-1, VT);
1612 if (isLegalICmpImmediate(C+1)) {
1613 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1614 RHS = DAG.getConstant(C+1, VT);
1619 if (isLegalICmpImmediate(C+1)) {
1620 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1621 RHS = DAG.getConstant(C+1, VT);
1628 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
1629 A64cc = DAG.getConstant(CondCode, MVT::i32);
1630 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1631 DAG.getCondCode(CC));
1634 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1635 A64CC::CondCodes &Alternative) {
1636 A64CC::CondCodes CondCode = A64CC::Invalid;
1637 Alternative = A64CC::Invalid;
1640 default: llvm_unreachable("Unknown FP condition!");
1642 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
1644 case ISD::SETOGT: CondCode = A64CC::GT; break;
1646 case ISD::SETOGE: CondCode = A64CC::GE; break;
1647 case ISD::SETOLT: CondCode = A64CC::MI; break;
1648 case ISD::SETOLE: CondCode = A64CC::LS; break;
1649 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
1650 case ISD::SETO: CondCode = A64CC::VC; break;
1651 case ISD::SETUO: CondCode = A64CC::VS; break;
1652 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
1653 case ISD::SETUGT: CondCode = A64CC::HI; break;
1654 case ISD::SETUGE: CondCode = A64CC::PL; break;
1656 case ISD::SETULT: CondCode = A64CC::LT; break;
1658 case ISD::SETULE: CondCode = A64CC::LE; break;
1660 case ISD::SETUNE: CondCode = A64CC::NE; break;
1666 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1667 DebugLoc DL = Op.getDebugLoc();
1668 EVT PtrVT = getPointerTy();
1669 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1671 assert(getTargetMachine().getCodeModel() == CodeModel::Small
1672 && "Only small code model supported at the moment");
1674 // The most efficient code is PC-relative anyway for the small memory model,
1675 // so we don't need to worry about relocation model.
1676 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
1677 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1678 AArch64II::MO_NO_FLAG),
1679 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1680 AArch64II::MO_LO12),
1681 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
1685 // (BRCOND chain, val, dest)
1687 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1688 DebugLoc dl = Op.getDebugLoc();
1689 SDValue Chain = Op.getOperand(0);
1690 SDValue TheBit = Op.getOperand(1);
1691 SDValue DestBB = Op.getOperand(2);
1693 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
1694 // that as the consumer we are responsible for ignoring rubbish in higher
1696 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
1697 DAG.getConstant(1, MVT::i32));
1699 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
1700 DAG.getConstant(0, TheBit.getValueType()),
1701 DAG.getCondCode(ISD::SETNE));
1703 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
1704 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
1708 // (BR_CC chain, condcode, lhs, rhs, dest)
1710 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1711 DebugLoc dl = Op.getDebugLoc();
1712 SDValue Chain = Op.getOperand(0);
1713 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1714 SDValue LHS = Op.getOperand(2);
1715 SDValue RHS = Op.getOperand(3);
1716 SDValue DestBB = Op.getOperand(4);
1718 if (LHS.getValueType() == MVT::f128) {
1719 // f128 comparisons are lowered to runtime calls by a routine which sets
1720 // LHS, RHS and CC appropriately for the rest of this function to continue.
1721 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
1723 // If softenSetCCOperands returned a scalar, we need to compare the result
1724 // against zero to select between true and false values.
1725 if (RHS.getNode() == 0) {
1726 RHS = DAG.getConstant(0, LHS.getValueType());
1731 if (LHS.getValueType().isInteger()) {
1734 // Integers are handled in a separate function because the combinations of
1735 // immediates and tests can get hairy and we may want to fiddle things.
1736 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
1738 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1739 Chain, CmpOp, A64cc, DestBB);
1742 // Note that some LLVM floating-point CondCodes can't be lowered to a single
1743 // conditional branch, hence FPCCToA64CC can set a second test, where either
1744 // passing is sufficient.
1745 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
1746 CondCode = FPCCToA64CC(CC, Alternative);
1747 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
1748 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1749 DAG.getCondCode(CC));
1750 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1751 Chain, SetCC, A64cc, DestBB);
1753 if (Alternative != A64CC::Invalid) {
1754 A64cc = DAG.getConstant(Alternative, MVT::i32);
1755 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1756 A64BR_CC, SetCC, A64cc, DestBB);
1764 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
1765 RTLIB::Libcall Call) const {
1768 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
1769 EVT ArgVT = Op.getOperand(i).getValueType();
1770 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1771 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
1772 Entry.isSExt = false;
1773 Entry.isZExt = false;
1774 Args.push_back(Entry);
1776 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
1778 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
1780 // By default, the input chain to this libcall is the entry node of the
1781 // function. If the libcall is going to be emitted as a tail call then
1782 // isUsedByReturnOnly will change it to the right chain if the return
1783 // node which is being folded has a non-entry input chain.
1784 SDValue InChain = DAG.getEntryNode();
1786 // isTailCall may be true since the callee does not reference caller stack
1787 // frame. Check if it's in the right position.
1788 SDValue TCChain = InChain;
1789 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
1794 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
1795 0, getLibcallCallingConv(Call), isTailCall,
1796 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1797 Callee, Args, DAG, Op->getDebugLoc());
1798 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1800 if (!CallInfo.second.getNode())
1801 // It's a tailcall, return the chain (which is the DAG root).
1802 return DAG.getRoot();
1804 return CallInfo.first;
1808 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
1809 if (Op.getOperand(0).getValueType() != MVT::f128) {
1810 // It's legal except when f128 is involved
1815 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1817 SDValue SrcVal = Op.getOperand(0);
1818 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1819 /*isSigned*/ false, Op.getDebugLoc());
1823 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
1824 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1827 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1829 return LowerF128ToCall(Op, DAG, LC);
1833 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1834 bool IsSigned) const {
1835 if (Op.getOperand(0).getValueType() != MVT::f128) {
1836 // It's legal except when f128 is involved
1842 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1844 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1846 return LowerF128ToCall(Op, DAG, LC);
1850 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
1851 SelectionDAG &DAG) const {
1852 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
1853 // we make that distinction here.
1855 // We support the small memory model for now.
1856 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
1858 EVT PtrVT = getPointerTy();
1859 DebugLoc dl = Op.getDebugLoc();
1860 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
1861 const GlobalValue *GV = GN->getGlobal();
1862 unsigned Alignment = GV->getAlignment();
1863 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1865 if (GV->isWeakForLinker() && RelocM == Reloc::Static) {
1866 // Weak symbols can't use ADRP/ADD pair since they should evaluate to
1867 // zero when undefined. In PIC mode the GOT can take care of this, but in
1868 // absolute mode we use a constant pool load.
1870 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
1871 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
1872 AArch64II::MO_NO_FLAG),
1873 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
1874 AArch64II::MO_LO12),
1875 DAG.getConstant(8, MVT::i32));
1876 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
1877 MachinePointerInfo::getConstantPool(),
1878 /*isVolatile=*/ false, /*isNonTemporal=*/ true,
1879 /*isInvariant=*/ true, 8);
1882 if (Alignment == 0) {
1883 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
1884 if (GVPtrTy->getElementType()->isSized()) {
1886 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
1888 // Be conservative if we can't guess, not that it really matters:
1889 // functions and labels aren't valid for loads, and the methods used to
1890 // actually calculate an address work with any alignment.
1895 unsigned char HiFixup, LoFixup;
1896 bool UseGOT = Subtarget->GVIsIndirectSymbol(GV, RelocM);
1899 HiFixup = AArch64II::MO_GOT;
1900 LoFixup = AArch64II::MO_GOT_LO12;
1903 HiFixup = AArch64II::MO_NO_FLAG;
1904 LoFixup = AArch64II::MO_LO12;
1907 // AArch64's small model demands the following sequence:
1908 // ADRP x0, somewhere
1909 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
1910 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
1911 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1913 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1915 DAG.getConstant(Alignment, MVT::i32));
1918 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
1922 if (GN->getOffset() != 0)
1923 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
1924 DAG.getConstant(GN->getOffset(), PtrVT));
1929 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
1932 SelectionDAG &DAG) const {
1933 EVT PtrVT = getPointerTy();
1935 // The function we need to call is simply the first entry in the GOT for this
1936 // descriptor, load it in preparation.
1937 SDValue Func, Chain;
1938 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
1941 // The function takes only one argument: the address of the descriptor itself
1944 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
1945 Glue = Chain.getValue(1);
1947 // Finally, there's a special calling-convention which means that the lookup
1948 // must preserve all registers (except X0, obviously).
1949 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1950 const AArch64RegisterInfo *A64RI
1951 = static_cast<const AArch64RegisterInfo *>(TRI);
1952 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
1954 // We're now ready to populate the argument list, as with a normal call:
1955 std::vector<SDValue> Ops;
1956 Ops.push_back(Chain);
1957 Ops.push_back(Func);
1958 Ops.push_back(SymAddr);
1959 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
1960 Ops.push_back(DAG.getRegisterMask(Mask));
1961 Ops.push_back(Glue);
1963 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1964 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
1966 Glue = Chain.getValue(1);
1968 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
1969 // back to the generic handling code.
1970 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
1974 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
1975 SelectionDAG &DAG) const {
1976 assert(Subtarget->isTargetELF() &&
1977 "TLS not implemented for non-ELF targets");
1978 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1980 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
1983 EVT PtrVT = getPointerTy();
1984 DebugLoc DL = Op.getDebugLoc();
1985 const GlobalValue *GV = GA->getGlobal();
1987 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
1989 if (Model == TLSModel::InitialExec) {
1990 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
1991 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1992 AArch64II::MO_GOTTPREL),
1993 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1994 AArch64II::MO_GOTTPREL_LO12),
1995 DAG.getConstant(8, MVT::i32));
1996 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
1998 } else if (Model == TLSModel::LocalExec) {
1999 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2000 AArch64II::MO_TPREL_G1);
2001 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2002 AArch64II::MO_TPREL_G0_NC);
2004 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2005 DAG.getTargetConstant(0, MVT::i32)), 0);
2006 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2008 DAG.getTargetConstant(0, MVT::i32)), 0);
2009 } else if (Model == TLSModel::GeneralDynamic) {
2010 // Accesses used in this sequence go via the TLS descriptor which lives in
2011 // the GOT. Prepare an address we can use to handle this.
2012 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2013 AArch64II::MO_TLSDESC);
2014 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2015 AArch64II::MO_TLSDESC_LO12);
2016 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2018 DAG.getConstant(8, MVT::i32));
2019 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2021 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2022 } else if (Model == TLSModel::LocalDynamic) {
2023 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2024 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2025 // the beginning of the module's TLS region, followed by a DTPREL offset
2028 // These accesses will need deduplicating if there's more than one.
2029 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2030 .getInfo<AArch64MachineFunctionInfo>();
2031 MFI->incNumLocalDynamicTLSAccesses();
2034 // Get the location of _TLS_MODULE_BASE_:
2035 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2036 AArch64II::MO_TLSDESC);
2037 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2038 AArch64II::MO_TLSDESC_LO12);
2039 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2041 DAG.getConstant(8, MVT::i32));
2042 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2044 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2046 // Get the variable's offset from _TLS_MODULE_BASE_
2047 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2048 AArch64II::MO_DTPREL_G1);
2049 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2050 AArch64II::MO_DTPREL_G0_NC);
2052 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2053 DAG.getTargetConstant(0, MVT::i32)), 0);
2054 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2056 DAG.getTargetConstant(0, MVT::i32)), 0);
2058 llvm_unreachable("Unsupported TLS access model");
2061 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2065 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2066 bool IsSigned) const {
2067 if (Op.getValueType() != MVT::f128) {
2068 // Legal for everything except f128.
2074 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2076 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2078 return LowerF128ToCall(Op, DAG, LC);
2083 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2084 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2085 DebugLoc dl = JT->getDebugLoc();
2087 // When compiling PIC, jump tables get put in the code section so a static
2088 // relocation-style is acceptable for both cases.
2089 return DAG.getNode(AArch64ISD::WrapperSmall, dl, getPointerTy(),
2090 DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()),
2091 DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
2092 AArch64II::MO_LO12),
2093 DAG.getConstant(1, MVT::i32));
2096 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
2098 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2099 DebugLoc dl = Op.getDebugLoc();
2100 SDValue LHS = Op.getOperand(0);
2101 SDValue RHS = Op.getOperand(1);
2102 SDValue IfTrue = Op.getOperand(2);
2103 SDValue IfFalse = Op.getOperand(3);
2104 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2106 if (LHS.getValueType() == MVT::f128) {
2107 // f128 comparisons are lowered to libcalls, but slot in nicely here
2109 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2111 // If softenSetCCOperands returned a scalar, we need to compare the result
2112 // against zero to select between true and false values.
2113 if (RHS.getNode() == 0) {
2114 RHS = DAG.getConstant(0, LHS.getValueType());
2119 if (LHS.getValueType().isInteger()) {
2122 // Integers are handled in a separate function because the combinations of
2123 // immediates and tests can get hairy and we may want to fiddle things.
2124 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2126 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2127 CmpOp, IfTrue, IfFalse, A64cc);
2130 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2131 // conditional branch, hence FPCCToA64CC can set a second test, where either
2132 // passing is sufficient.
2133 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2134 CondCode = FPCCToA64CC(CC, Alternative);
2135 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2136 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2137 DAG.getCondCode(CC));
2138 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
2140 SetCC, IfTrue, IfFalse, A64cc);
2142 if (Alternative != A64CC::Invalid) {
2143 A64cc = DAG.getConstant(Alternative, MVT::i32);
2144 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2145 SetCC, IfTrue, A64SELECT_CC, A64cc);
2149 return A64SELECT_CC;
2152 // (SELECT testbit, iftrue, iffalse)
2154 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2155 DebugLoc dl = Op.getDebugLoc();
2156 SDValue TheBit = Op.getOperand(0);
2157 SDValue IfTrue = Op.getOperand(1);
2158 SDValue IfFalse = Op.getOperand(2);
2160 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2161 // that as the consumer we are responsible for ignoring rubbish in higher
2163 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2164 DAG.getConstant(1, MVT::i32));
2165 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2166 DAG.getConstant(0, TheBit.getValueType()),
2167 DAG.getCondCode(ISD::SETNE));
2169 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2170 A64CMP, IfTrue, IfFalse,
2171 DAG.getConstant(A64CC::NE, MVT::i32));
2174 // (SETCC lhs, rhs, condcode)
2176 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2177 DebugLoc dl = Op.getDebugLoc();
2178 SDValue LHS = Op.getOperand(0);
2179 SDValue RHS = Op.getOperand(1);
2180 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2181 EVT VT = Op.getValueType();
2183 if (LHS.getValueType() == MVT::f128) {
2184 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
2185 // for the rest of the function (some i32 or i64 values).
2186 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2188 // If softenSetCCOperands returned a scalar, use it.
2189 if (RHS.getNode() == 0) {
2190 assert(LHS.getValueType() == Op.getValueType() &&
2191 "Unexpected setcc expansion!");
2196 if (LHS.getValueType().isInteger()) {
2199 // Integers are handled in a separate function because the combinations of
2200 // immediates and tests can get hairy and we may want to fiddle things.
2201 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2203 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2204 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2208 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2209 // conditional branch, hence FPCCToA64CC can set a second test, where either
2210 // passing is sufficient.
2211 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2212 CondCode = FPCCToA64CC(CC, Alternative);
2213 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2214 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2215 DAG.getCondCode(CC));
2216 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2217 CmpOp, DAG.getConstant(1, VT),
2218 DAG.getConstant(0, VT), A64cc);
2220 if (Alternative != A64CC::Invalid) {
2221 A64cc = DAG.getConstant(Alternative, MVT::i32);
2222 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
2223 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
2226 return A64SELECT_CC;
2230 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2231 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2232 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2234 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
2235 // rather than just 8.
2236 return DAG.getMemcpy(Op.getOperand(0), Op.getDebugLoc(),
2237 Op.getOperand(1), Op.getOperand(2),
2238 DAG.getConstant(32, MVT::i32), 8, false, false,
2239 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
2243 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2244 // The layout of the va_list struct is specified in the AArch64 Procedure Call
2245 // Standard, section B.3.
2246 MachineFunction &MF = DAG.getMachineFunction();
2247 AArch64MachineFunctionInfo *FuncInfo
2248 = MF.getInfo<AArch64MachineFunctionInfo>();
2249 DebugLoc DL = Op.getDebugLoc();
2251 SDValue Chain = Op.getOperand(0);
2252 SDValue VAList = Op.getOperand(1);
2253 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2254 SmallVector<SDValue, 4> MemOps;
2256 // void *__stack at offset 0
2257 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
2259 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
2260 MachinePointerInfo(SV), false, false, 0));
2262 // void *__gr_top at offset 8
2263 int GPRSize = FuncInfo->getVariadicGPRSize();
2265 SDValue GRTop, GRTopAddr;
2267 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2268 DAG.getConstant(8, getPointerTy()));
2270 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
2271 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
2272 DAG.getConstant(GPRSize, getPointerTy()));
2274 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
2275 MachinePointerInfo(SV, 8),
2279 // void *__vr_top at offset 16
2280 int FPRSize = FuncInfo->getVariadicFPRSize();
2282 SDValue VRTop, VRTopAddr;
2283 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2284 DAG.getConstant(16, getPointerTy()));
2286 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
2287 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
2288 DAG.getConstant(FPRSize, getPointerTy()));
2290 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
2291 MachinePointerInfo(SV, 16),
2295 // int __gr_offs at offset 24
2296 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2297 DAG.getConstant(24, getPointerTy()));
2298 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
2299 GROffsAddr, MachinePointerInfo(SV, 24),
2302 // int __vr_offs at offset 28
2303 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2304 DAG.getConstant(28, getPointerTy()));
2305 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
2306 VROffsAddr, MachinePointerInfo(SV, 28),
2309 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
2314 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2315 switch (Op.getOpcode()) {
2316 default: llvm_unreachable("Don't know how to custom lower this!");
2317 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
2318 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
2319 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
2320 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
2321 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
2322 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
2323 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
2324 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
2325 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
2326 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
2328 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2329 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
2330 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2331 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
2332 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2333 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2334 case ISD::SELECT: return LowerSELECT(Op, DAG);
2335 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2336 case ISD::SETCC: return LowerSETCC(Op, DAG);
2337 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
2338 case ISD::VASTART: return LowerVASTART(Op, DAG);
2344 static SDValue PerformANDCombine(SDNode *N,
2345 TargetLowering::DAGCombinerInfo &DCI) {
2347 SelectionDAG &DAG = DCI.DAG;
2348 DebugLoc DL = N->getDebugLoc();
2349 EVT VT = N->getValueType(0);
2351 // We're looking for an SRA/SHL pair which form an SBFX.
2353 if (VT != MVT::i32 && VT != MVT::i64)
2356 if (!isa<ConstantSDNode>(N->getOperand(1)))
2359 uint64_t TruncMask = N->getConstantOperandVal(1);
2360 if (!isMask_64(TruncMask))
2363 uint64_t Width = CountPopulation_64(TruncMask);
2364 SDValue Shift = N->getOperand(0);
2366 if (Shift.getOpcode() != ISD::SRL)
2369 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
2371 uint64_t LSB = Shift->getConstantOperandVal(1);
2373 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
2376 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
2377 DAG.getConstant(LSB, MVT::i64),
2378 DAG.getConstant(LSB + Width - 1, MVT::i64));
2381 static SDValue PerformATOMIC_FENCECombine(SDNode *FenceNode,
2382 TargetLowering::DAGCombinerInfo &DCI) {
2383 // An atomic operation followed by an acquiring atomic fence can be reduced to
2384 // an acquiring load. The atomic operation provides a convenient pointer to
2385 // load from. If the original operation was a load anyway we can actually
2386 // combine the two operations into an acquiring load.
2387 SelectionDAG &DAG = DCI.DAG;
2388 SDValue AtomicOp = FenceNode->getOperand(0);
2389 AtomicSDNode *AtomicNode = dyn_cast<AtomicSDNode>(AtomicOp);
2391 // A fence on its own can't be optimised
2395 AtomicOrdering FenceOrder
2396 = static_cast<AtomicOrdering>(FenceNode->getConstantOperandVal(1));
2397 SynchronizationScope FenceScope
2398 = static_cast<SynchronizationScope>(FenceNode->getConstantOperandVal(2));
2400 if (FenceOrder != Acquire || FenceScope != AtomicNode->getSynchScope())
2403 // If the original operation was an ATOMIC_LOAD then we'll be replacing it, so
2404 // the chain we use should be its input, otherwise we'll put our store after
2405 // it so we use its output chain.
2406 SDValue Chain = AtomicNode->getOpcode() == ISD::ATOMIC_LOAD ?
2407 AtomicNode->getChain() : AtomicOp;
2409 // We have an acquire fence with a handy atomic operation nearby, we can
2410 // convert the fence into a load-acquire, discarding the result.
2411 DebugLoc DL = FenceNode->getDebugLoc();
2412 SDValue Op = DAG.getAtomic(ISD::ATOMIC_LOAD, DL, AtomicNode->getMemoryVT(),
2413 AtomicNode->getValueType(0),
2415 AtomicOp.getOperand(1), // Pointer
2416 AtomicNode->getMemOperand(), Acquire,
2419 if (AtomicNode->getOpcode() == ISD::ATOMIC_LOAD)
2420 DAG.ReplaceAllUsesWith(AtomicNode, Op.getNode());
2422 return Op.getValue(1);
2425 static SDValue PerformATOMIC_STORECombine(SDNode *N,
2426 TargetLowering::DAGCombinerInfo &DCI) {
2427 // A releasing atomic fence followed by an atomic store can be combined into a
2428 // single store operation.
2429 SelectionDAG &DAG = DCI.DAG;
2430 AtomicSDNode *AtomicNode = cast<AtomicSDNode>(N);
2431 SDValue FenceOp = AtomicNode->getOperand(0);
2433 if (FenceOp.getOpcode() != ISD::ATOMIC_FENCE)
2436 AtomicOrdering FenceOrder
2437 = static_cast<AtomicOrdering>(FenceOp->getConstantOperandVal(1));
2438 SynchronizationScope FenceScope
2439 = static_cast<SynchronizationScope>(FenceOp->getConstantOperandVal(2));
2441 if (FenceOrder != Release || FenceScope != AtomicNode->getSynchScope())
2444 DebugLoc DL = AtomicNode->getDebugLoc();
2445 return DAG.getAtomic(ISD::ATOMIC_STORE, DL, AtomicNode->getMemoryVT(),
2446 FenceOp.getOperand(0), // Chain
2447 AtomicNode->getOperand(1), // Pointer
2448 AtomicNode->getOperand(2), // Value
2449 AtomicNode->getMemOperand(), Release,
2453 /// For a true bitfield insert, the bits getting into that contiguous mask
2454 /// should come from the low part of an existing value: they must be formed from
2455 /// a compatible SHL operation (unless they're already low). This function
2456 /// checks that condition and returns the least-significant bit that's
2457 /// intended. If the operation not a field preparation, -1 is returned.
2458 static int32_t getLSBForBFI(SelectionDAG &DAG, DebugLoc DL, EVT VT,
2459 SDValue &MaskedVal, uint64_t Mask) {
2460 if (!isShiftedMask_64(Mask))
2463 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
2464 // instruction. BFI will do a left-shift by LSB before applying the mask we've
2465 // spotted, so in general we should pre-emptively "undo" that by making sure
2466 // the incoming bits have had a right-shift applied to them.
2468 // This right shift, however, will combine with existing left/right shifts. In
2469 // the simplest case of a completely straight bitfield operation, it will be
2470 // expected to completely cancel out with an existing SHL. More complicated
2471 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
2474 uint64_t LSB = CountTrailingZeros_64(Mask);
2475 int64_t ShiftRightRequired = LSB;
2476 if (MaskedVal.getOpcode() == ISD::SHL &&
2477 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
2478 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
2479 MaskedVal = MaskedVal.getOperand(0);
2480 } else if (MaskedVal.getOpcode() == ISD::SRL &&
2481 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
2482 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
2483 MaskedVal = MaskedVal.getOperand(0);
2486 if (ShiftRightRequired > 0)
2487 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
2488 DAG.getConstant(ShiftRightRequired, MVT::i64));
2489 else if (ShiftRightRequired < 0) {
2490 // We could actually end up with a residual left shift, for example with
2491 // "struc.bitfield = val << 1".
2492 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
2493 DAG.getConstant(-ShiftRightRequired, MVT::i64));
2499 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
2500 /// a mask and an extension. Returns true if a BFI was found and provides
2501 /// information on its surroundings.
2502 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
2505 if (N.getOpcode() == ISD::ZERO_EXTEND) {
2507 N = N.getOperand(0);
2510 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
2511 Mask = N->getConstantOperandVal(1);
2512 N = N.getOperand(0);
2514 // Mask is the whole width.
2515 Mask = (1ULL << N.getValueType().getSizeInBits()) - 1;
2518 if (N.getOpcode() == AArch64ISD::BFI) {
2526 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
2527 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
2528 /// can often be further combined with a larger mask. Ultimately, we want mask
2529 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
2530 static SDValue tryCombineToBFI(SDNode *N,
2531 TargetLowering::DAGCombinerInfo &DCI,
2532 const AArch64Subtarget *Subtarget) {
2533 SelectionDAG &DAG = DCI.DAG;
2534 DebugLoc DL = N->getDebugLoc();
2535 EVT VT = N->getValueType(0);
2537 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2539 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
2540 // abandon the effort.
2541 SDValue LHS = N->getOperand(0);
2542 if (LHS.getOpcode() != ISD::AND)
2546 if (isa<ConstantSDNode>(LHS.getOperand(1)))
2547 LHSMask = LHS->getConstantOperandVal(1);
2551 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
2552 // is or abandon the effort.
2553 SDValue RHS = N->getOperand(1);
2554 if (RHS.getOpcode() != ISD::AND)
2558 if (isa<ConstantSDNode>(RHS.getOperand(1)))
2559 RHSMask = RHS->getConstantOperandVal(1);
2563 // Can't do anything if the masks are incompatible.
2564 if (LHSMask & RHSMask)
2567 // Now we need one of the masks to be a contiguous field. Without loss of
2568 // generality that should be the RHS one.
2569 SDValue Bitfield = LHS.getOperand(0);
2570 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
2571 // We know that LHS is a candidate new value, and RHS isn't already a better
2573 std::swap(LHS, RHS);
2574 std::swap(LHSMask, RHSMask);
2577 // We've done our best to put the right operands in the right places, all we
2578 // can do now is check whether a BFI exists.
2579 Bitfield = RHS.getOperand(0);
2580 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
2584 uint32_t Width = CountPopulation_64(RHSMask);
2585 assert(Width && "Expected non-zero bitfield width");
2587 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
2588 LHS.getOperand(0), Bitfield,
2589 DAG.getConstant(LSB, MVT::i64),
2590 DAG.getConstant(Width, MVT::i64));
2593 if ((LHSMask | RHSMask) == (1ULL << VT.getSizeInBits()) - 1)
2596 return DAG.getNode(ISD::AND, DL, VT, BFI,
2597 DAG.getConstant(LHSMask | RHSMask, VT));
2600 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
2601 /// original input. This is surprisingly common because SROA splits things up
2602 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
2603 /// on the low (say) byte of a word. This is then orred into the rest of the
2604 /// word afterwards.
2606 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
2608 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
2609 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
2611 static SDValue tryCombineToLargerBFI(SDNode *N,
2612 TargetLowering::DAGCombinerInfo &DCI,
2613 const AArch64Subtarget *Subtarget) {
2614 SelectionDAG &DAG = DCI.DAG;
2615 DebugLoc DL = N->getDebugLoc();
2616 EVT VT = N->getValueType(0);
2618 // First job is to hunt for a MaskedBFI on either the left or right. Swap
2619 // operands if it's actually on the right.
2621 SDValue PossExtraMask;
2622 uint64_t ExistingMask = 0;
2623 bool Extended = false;
2624 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
2625 PossExtraMask = N->getOperand(1);
2626 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
2627 PossExtraMask = N->getOperand(0);
2631 // We can only combine a BFI with another compatible mask.
2632 if (PossExtraMask.getOpcode() != ISD::AND ||
2633 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
2636 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
2638 // Masks must be compatible.
2639 if (ExtraMask & ExistingMask)
2642 SDValue OldBFIVal = BFI.getOperand(0);
2643 SDValue NewBFIVal = BFI.getOperand(1);
2645 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
2646 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
2647 // need to be made compatible.
2648 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
2649 && "Invalid types for BFI");
2650 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
2651 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
2654 // We need the MaskedBFI to be combined with a mask of the *same* value.
2655 if (PossExtraMask.getOperand(0) != OldBFIVal)
2658 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
2659 OldBFIVal, NewBFIVal,
2660 BFI.getOperand(2), BFI.getOperand(3));
2662 // If the masking is trivial, we don't need to create it.
2663 if ((ExtraMask | ExistingMask) == (1ULL << VT.getSizeInBits()) - 1)
2666 return DAG.getNode(ISD::AND, DL, VT, BFI,
2667 DAG.getConstant(ExtraMask | ExistingMask, VT));
2670 /// An EXTR instruction is made up of two shifts, ORed together. This helper
2671 /// searches for and classifies those shifts.
2672 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
2674 if (N.getOpcode() == ISD::SHL)
2676 else if (N.getOpcode() == ISD::SRL)
2681 if (!isa<ConstantSDNode>(N.getOperand(1)))
2684 ShiftAmount = N->getConstantOperandVal(1);
2685 Src = N->getOperand(0);
2689 /// EXTR instruction extracts a contiguous chunk of bits from two existing
2690 /// registers viewed as a high/low pair. This function looks for the pattern:
2691 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
2692 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
2694 static SDValue tryCombineToEXTR(SDNode *N,
2695 TargetLowering::DAGCombinerInfo &DCI) {
2696 SelectionDAG &DAG = DCI.DAG;
2697 DebugLoc DL = N->getDebugLoc();
2698 EVT VT = N->getValueType(0);
2700 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2702 if (VT != MVT::i32 && VT != MVT::i64)
2706 uint32_t ShiftLHS = 0;
2708 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
2712 uint32_t ShiftRHS = 0;
2714 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
2717 // If they're both trying to come from the high part of the register, they're
2718 // not really an EXTR.
2719 if (LHSFromHi == RHSFromHi)
2722 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
2726 std::swap(LHS, RHS);
2727 std::swap(ShiftLHS, ShiftRHS);
2730 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
2732 DAG.getConstant(ShiftRHS, MVT::i64));
2735 /// Target-specific dag combine xforms for ISD::OR
2736 static SDValue PerformORCombine(SDNode *N,
2737 TargetLowering::DAGCombinerInfo &DCI,
2738 const AArch64Subtarget *Subtarget) {
2740 SelectionDAG &DAG = DCI.DAG;
2741 EVT VT = N->getValueType(0);
2743 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2746 // Attempt to recognise bitfield-insert operations.
2747 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
2751 // Attempt to combine an existing MaskedBFI operation into one with a larger
2753 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
2757 Res = tryCombineToEXTR(N, DCI);
2764 /// Target-specific dag combine xforms for ISD::SRA
2765 static SDValue PerformSRACombine(SDNode *N,
2766 TargetLowering::DAGCombinerInfo &DCI) {
2768 SelectionDAG &DAG = DCI.DAG;
2769 DebugLoc DL = N->getDebugLoc();
2770 EVT VT = N->getValueType(0);
2772 // We're looking for an SRA/SHL pair which form an SBFX.
2774 if (VT != MVT::i32 && VT != MVT::i64)
2777 if (!isa<ConstantSDNode>(N->getOperand(1)))
2780 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
2781 SDValue Shift = N->getOperand(0);
2783 if (Shift.getOpcode() != ISD::SHL)
2786 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
2789 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
2790 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
2791 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
2793 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
2796 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
2797 DAG.getConstant(LSB, MVT::i64),
2798 DAG.getConstant(LSB + Width - 1, MVT::i64));
2803 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2804 DAGCombinerInfo &DCI) const {
2805 switch (N->getOpcode()) {
2807 case ISD::AND: return PerformANDCombine(N, DCI);
2808 case ISD::ATOMIC_FENCE: return PerformATOMIC_FENCECombine(N, DCI);
2809 case ISD::ATOMIC_STORE: return PerformATOMIC_STORECombine(N, DCI);
2810 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
2811 case ISD::SRA: return PerformSRACombine(N, DCI);
2816 AArch64TargetLowering::ConstraintType
2817 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
2818 if (Constraint.size() == 1) {
2819 switch (Constraint[0]) {
2821 case 'w': // An FP/SIMD vector register
2822 return C_RegisterClass;
2823 case 'I': // Constant that can be used with an ADD instruction
2824 case 'J': // Constant that can be used with a SUB instruction
2825 case 'K': // Constant that can be used with a 32-bit logical instruction
2826 case 'L': // Constant that can be used with a 64-bit logical instruction
2827 case 'M': // Constant that can be used as a 32-bit MOV immediate
2828 case 'N': // Constant that can be used as a 64-bit MOV immediate
2829 case 'Y': // Floating point constant zero
2830 case 'Z': // Integer constant zero
2832 case 'Q': // A memory reference with base register and no offset
2834 case 'S': // A symbolic address
2839 // FIXME: Ump, Utf, Usa, Ush
2840 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
2841 // whatever they may be
2842 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
2843 // Usa: An absolute symbolic address
2844 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
2845 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
2846 && Constraint != "Ush" && "Unimplemented constraints");
2848 return TargetLowering::getConstraintType(Constraint);
2851 TargetLowering::ConstraintWeight
2852 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
2853 const char *Constraint) const {
2855 llvm_unreachable("Constraint weight unimplemented");
2859 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2860 std::string &Constraint,
2861 std::vector<SDValue> &Ops,
2862 SelectionDAG &DAG) const {
2863 SDValue Result(0, 0);
2865 // Only length 1 constraints are C_Other.
2866 if (Constraint.size() != 1) return;
2868 // Only C_Other constraints get lowered like this. That means constants for us
2869 // so return early if there's no hope the constraint can be lowered.
2871 switch(Constraint[0]) {
2873 case 'I': case 'J': case 'K': case 'L':
2874 case 'M': case 'N': case 'Z': {
2875 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2879 uint64_t CVal = C->getZExtValue();
2882 switch (Constraint[0]) {
2884 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
2885 // is a peculiarly useless SUB constraint.
2886 llvm_unreachable("Unimplemented C_Other constraint");
2892 if (A64Imms::isLogicalImm(32, CVal, Bits))
2896 if (A64Imms::isLogicalImm(64, CVal, Bits))
2905 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2909 // An absolute symbolic address or label reference.
2910 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
2911 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
2912 GA->getValueType(0));
2913 } else if (const BlockAddressSDNode *BA
2914 = dyn_cast<BlockAddressSDNode>(Op)) {
2915 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
2916 BA->getValueType(0));
2917 } else if (const ExternalSymbolSDNode *ES
2918 = dyn_cast<ExternalSymbolSDNode>(Op)) {
2919 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
2920 ES->getValueType(0));
2926 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2927 if (CFP->isExactlyValue(0.0)) {
2928 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
2935 if (Result.getNode()) {
2936 Ops.push_back(Result);
2940 // It's an unknown constraint for us. Let generic code have a go.
2941 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2944 std::pair<unsigned, const TargetRegisterClass*>
2945 AArch64TargetLowering::getRegForInlineAsmConstraint(
2946 const std::string &Constraint,
2948 if (Constraint.size() == 1) {
2949 switch (Constraint[0]) {
2951 if (VT.getSizeInBits() <= 32)
2952 return std::make_pair(0U, &AArch64::GPR32RegClass);
2953 else if (VT == MVT::i64)
2954 return std::make_pair(0U, &AArch64::GPR64RegClass);
2958 return std::make_pair(0U, &AArch64::FPR16RegClass);
2959 else if (VT == MVT::f32)
2960 return std::make_pair(0U, &AArch64::FPR32RegClass);
2961 else if (VT == MVT::f64)
2962 return std::make_pair(0U, &AArch64::FPR64RegClass);
2963 else if (VT.getSizeInBits() == 64)
2964 return std::make_pair(0U, &AArch64::VPR64RegClass);
2965 else if (VT == MVT::f128)
2966 return std::make_pair(0U, &AArch64::FPR128RegClass);
2967 else if (VT.getSizeInBits() == 128)
2968 return std::make_pair(0U, &AArch64::VPR128RegClass);
2973 // Use the default implementation in TargetLowering to convert the register
2974 // constraint into a member of a register class.
2975 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);