1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64PerfectShuffle.h"
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
48 static cl::opt<AlignMode>
49 Align(cl::desc("Load/store alignment support"),
50 cl::Hidden, cl::init(NoStrictAlign),
52 clEnumValN(StrictAlign, "aarch64-strict-align",
53 "Disallow all unaligned memory accesses"),
54 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
55 "Allow unaligned memory accesses"),
58 // Place holder until extr generation is tested fully.
60 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
61 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
65 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
66 cl::desc("Allow AArch64 SLI/SRI formation"),
69 //===----------------------------------------------------------------------===//
70 // AArch64 Lowering public interface.
71 //===----------------------------------------------------------------------===//
72 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
73 if (TT.isOSBinFormatMachO())
74 return new AArch64_MachoTargetObjectFile();
76 return new AArch64_ELFTargetObjectFile();
79 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
81 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
84 // we have to make something up. Arbitrarily, choose ZeroOrOne.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // When comparing vectors the result sets the different elements in the
87 // vector to all-one or all-zero.
88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
90 // Set up the register classes.
91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
94 if (Subtarget->hasFPARMv8()) {
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
101 if (Subtarget->hasNEON()) {
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
104 // Someone set us up the NEON.
105 addDRTypeForNEON(MVT::v2f32);
106 addDRTypeForNEON(MVT::v8i8);
107 addDRTypeForNEON(MVT::v4i16);
108 addDRTypeForNEON(MVT::v2i32);
109 addDRTypeForNEON(MVT::v1i64);
110 addDRTypeForNEON(MVT::v1f64);
111 addDRTypeForNEON(MVT::v4f16);
113 addQRTypeForNEON(MVT::v4f32);
114 addQRTypeForNEON(MVT::v2f64);
115 addQRTypeForNEON(MVT::v16i8);
116 addQRTypeForNEON(MVT::v8i16);
117 addQRTypeForNEON(MVT::v4i32);
118 addQRTypeForNEON(MVT::v2i64);
119 addQRTypeForNEON(MVT::v8f16);
122 // Compute derived properties from the register classes
123 computeRegisterProperties();
125 // Provide all sorts of operation actions
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
128 setOperationAction(ISD::SETCC, MVT::i32, Custom);
129 setOperationAction(ISD::SETCC, MVT::i64, Custom);
130 setOperationAction(ISD::SETCC, MVT::f32, Custom);
131 setOperationAction(ISD::SETCC, MVT::f64, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::FREM, MVT::f32, Expand);
153 setOperationAction(ISD::FREM, MVT::f64, Expand);
154 setOperationAction(ISD::FREM, MVT::f80, Expand);
156 // Custom lowering hooks are needed for XOR
157 // to fold it into CSINC/CSINV.
158 setOperationAction(ISD::XOR, MVT::i32, Custom);
159 setOperationAction(ISD::XOR, MVT::i64, Custom);
161 // Virtually no operation on f128 is legal, but LLVM can't expand them when
162 // there's a valid register class, so we need custom operations in most cases.
163 setOperationAction(ISD::FABS, MVT::f128, Expand);
164 setOperationAction(ISD::FADD, MVT::f128, Custom);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
166 setOperationAction(ISD::FCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FDIV, MVT::f128, Custom);
168 setOperationAction(ISD::FMA, MVT::f128, Expand);
169 setOperationAction(ISD::FMUL, MVT::f128, Custom);
170 setOperationAction(ISD::FNEG, MVT::f128, Expand);
171 setOperationAction(ISD::FPOW, MVT::f128, Expand);
172 setOperationAction(ISD::FREM, MVT::f128, Expand);
173 setOperationAction(ISD::FRINT, MVT::f128, Expand);
174 setOperationAction(ISD::FSIN, MVT::f128, Expand);
175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
176 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
177 setOperationAction(ISD::FSUB, MVT::f128, Custom);
178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
179 setOperationAction(ISD::SETCC, MVT::f128, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT, MVT::f128, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
185 // Lowering for many of the conversions is actually specified by the non-f128
186 // type. The LowerXXX function will be trivial when f128 isn't involved.
187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
202 // Variable arguments.
203 setOperationAction(ISD::VASTART, MVT::Other, Custom);
204 setOperationAction(ISD::VAARG, MVT::Other, Custom);
205 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
206 setOperationAction(ISD::VAEND, MVT::Other, Expand);
208 // Variable-sized objects.
209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
213 // Exception handling.
214 // FIXME: These are guesses. Has this been defined yet?
215 setExceptionPointerRegister(AArch64::X0);
216 setExceptionSelectorRegister(AArch64::X1);
218 // Constant pool entries
219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
225 setOperationAction(ISD::ADDC, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i32, Custom);
227 setOperationAction(ISD::SUBC, MVT::i32, Custom);
228 setOperationAction(ISD::SUBE, MVT::i32, Custom);
229 setOperationAction(ISD::ADDC, MVT::i64, Custom);
230 setOperationAction(ISD::ADDE, MVT::i64, Custom);
231 setOperationAction(ISD::SUBC, MVT::i64, Custom);
232 setOperationAction(ISD::SUBE, MVT::i64, Custom);
234 // AArch64 lacks both left-rotate and popcount instructions.
235 setOperationAction(ISD::ROTL, MVT::i32, Expand);
236 setOperationAction(ISD::ROTL, MVT::i64, Expand);
238 // AArch64 doesn't have {U|S}MUL_LOHI.
239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
244 // counterparts, which AArch64 supports directly.
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
251 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
256 setOperationAction(ISD::SREM, MVT::i64, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i32, Expand);
260 setOperationAction(ISD::UREM, MVT::i64, Expand);
262 // Custom lower Add/Sub/Mul with overflow.
263 setOperationAction(ISD::SADDO, MVT::i32, Custom);
264 setOperationAction(ISD::SADDO, MVT::i64, Custom);
265 setOperationAction(ISD::UADDO, MVT::i32, Custom);
266 setOperationAction(ISD::UADDO, MVT::i64, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
268 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
269 setOperationAction(ISD::USUBO, MVT::i32, Custom);
270 setOperationAction(ISD::USUBO, MVT::i64, Custom);
271 setOperationAction(ISD::SMULO, MVT::i32, Custom);
272 setOperationAction(ISD::SMULO, MVT::i64, Custom);
273 setOperationAction(ISD::UMULO, MVT::i32, Custom);
274 setOperationAction(ISD::UMULO, MVT::i64, Custom);
276 setOperationAction(ISD::FSIN, MVT::f32, Expand);
277 setOperationAction(ISD::FSIN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FCOS, MVT::f64, Expand);
280 setOperationAction(ISD::FPOW, MVT::f32, Expand);
281 setOperationAction(ISD::FPOW, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285 // f16 is storage-only, so we promote operations to f32 if we know this is
286 // valid, and ignore them otherwise. The operations not mentioned here will
287 // fail to select, but this is not a major problem as no source language
288 // should be emitting native f16 operations yet.
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FDIV, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FSUB, MVT::f16, Promote);
294 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
296 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
297 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
298 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
299 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
301 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
302 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
307 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
309 // Expand all other v4f16 operations.
310 // FIXME: We could generate better code by promoting some operations to
312 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
315 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
316 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
317 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
319 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
321 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
322 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
323 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
324 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
328 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
329 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
330 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
332 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
334 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
337 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
340 // v8f16 is also a storage-only type, so expand it.
341 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
342 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
345 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
346 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
347 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
349 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
351 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
353 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
354 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
355 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
356 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
360 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
361 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
362 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
363 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
365 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
366 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
368 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
371 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
373 // AArch64 has implementations of a lot of rounding-like FP operations.
374 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
375 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
376 MVT Ty = RoundingTypes[I];
377 setOperationAction(ISD::FFLOOR, Ty, Legal);
378 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
379 setOperationAction(ISD::FCEIL, Ty, Legal);
380 setOperationAction(ISD::FRINT, Ty, Legal);
381 setOperationAction(ISD::FTRUNC, Ty, Legal);
382 setOperationAction(ISD::FROUND, Ty, Legal);
385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
387 if (Subtarget->isTargetMachO()) {
388 // For iOS, we don't want to the normal expansion of a libcall to
389 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
391 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
392 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
394 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
395 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
398 // AArch64 does not have floating-point extending loads, i1 sign-extending
399 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
400 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
401 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
402 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
403 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
404 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
405 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
406 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
407 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
408 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
409 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
410 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
411 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
413 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
414 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
416 // Indexed loads and stores are supported.
417 for (unsigned im = (unsigned)ISD::PRE_INC;
418 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
419 setIndexedLoadAction(im, MVT::i8, Legal);
420 setIndexedLoadAction(im, MVT::i16, Legal);
421 setIndexedLoadAction(im, MVT::i32, Legal);
422 setIndexedLoadAction(im, MVT::i64, Legal);
423 setIndexedLoadAction(im, MVT::f64, Legal);
424 setIndexedLoadAction(im, MVT::f32, Legal);
425 setIndexedStoreAction(im, MVT::i8, Legal);
426 setIndexedStoreAction(im, MVT::i16, Legal);
427 setIndexedStoreAction(im, MVT::i32, Legal);
428 setIndexedStoreAction(im, MVT::i64, Legal);
429 setIndexedStoreAction(im, MVT::f64, Legal);
430 setIndexedStoreAction(im, MVT::f32, Legal);
434 setOperationAction(ISD::TRAP, MVT::Other, Legal);
436 // We combine OR nodes for bitfield operations.
437 setTargetDAGCombine(ISD::OR);
439 // Vector add and sub nodes may conceal a high-half opportunity.
440 // Also, try to fold ADD into CSINC/CSINV..
441 setTargetDAGCombine(ISD::ADD);
442 setTargetDAGCombine(ISD::SUB);
444 setTargetDAGCombine(ISD::XOR);
445 setTargetDAGCombine(ISD::SINT_TO_FP);
446 setTargetDAGCombine(ISD::UINT_TO_FP);
448 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
450 setTargetDAGCombine(ISD::ANY_EXTEND);
451 setTargetDAGCombine(ISD::ZERO_EXTEND);
452 setTargetDAGCombine(ISD::SIGN_EXTEND);
453 setTargetDAGCombine(ISD::BITCAST);
454 setTargetDAGCombine(ISD::CONCAT_VECTORS);
455 setTargetDAGCombine(ISD::STORE);
457 setTargetDAGCombine(ISD::MUL);
459 setTargetDAGCombine(ISD::SELECT);
460 setTargetDAGCombine(ISD::VSELECT);
462 setTargetDAGCombine(ISD::INTRINSIC_VOID);
463 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
464 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
466 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
467 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
468 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
470 setStackPointerRegisterToSaveRestore(AArch64::SP);
472 setSchedulingPreference(Sched::Hybrid);
475 MaskAndBranchFoldingIsLegal = true;
477 setMinFunctionAlignment(2);
479 RequireStrictAlign = (Align == StrictAlign);
481 setHasExtractBitsInsn(true);
483 if (Subtarget->hasNEON()) {
484 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
485 // silliness like this:
486 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
487 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
488 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
489 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
490 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
491 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
492 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
493 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
494 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
495 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
496 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
497 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
498 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
499 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
500 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
501 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
502 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
503 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
504 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
505 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
506 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
507 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
508 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
509 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
510 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
512 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
513 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
514 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
515 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
516 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
518 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
521 // elements smaller than i32, so promote the input to i32 first.
522 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
523 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
524 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
525 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
526 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
527 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
528 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
529 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
530 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
532 // AArch64 doesn't have MUL.2d:
533 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
534 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
535 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
536 // Likewise, narrowing and extending vector loads/stores aren't handled
538 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
539 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
541 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
544 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
551 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
552 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
553 setTruncStoreAction((MVT::SimpleValueType)VT,
554 (MVT::SimpleValueType)InnerVT, Expand);
555 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
556 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
557 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
560 // AArch64 has implementations of a lot of rounding-like FP operations.
561 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
562 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
563 MVT Ty = RoundingVecTypes[I];
564 setOperationAction(ISD::FFLOOR, Ty, Legal);
565 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
566 setOperationAction(ISD::FCEIL, Ty, Legal);
567 setOperationAction(ISD::FRINT, Ty, Legal);
568 setOperationAction(ISD::FTRUNC, Ty, Legal);
569 setOperationAction(ISD::FROUND, Ty, Legal);
573 // Prefer likely predicted branches to selects on out-of-order cores.
574 if (Subtarget->isCortexA57())
575 PredictableSelectIsExpensive = true;
578 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
579 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
580 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
581 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
583 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
584 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
585 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
586 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
587 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
589 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
590 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
593 // Mark vector float intrinsics as expand.
594 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
595 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
596 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
597 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
598 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
599 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
600 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
601 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
602 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
603 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
606 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
607 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
608 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
609 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
610 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
611 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
612 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
613 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
614 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
615 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
616 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
617 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
619 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
620 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
621 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
622 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
624 // CNT supports only B element sizes.
625 if (VT != MVT::v8i8 && VT != MVT::v16i8)
626 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
635 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
637 if (Subtarget->isLittleEndian()) {
638 for (unsigned im = (unsigned)ISD::PRE_INC;
639 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
640 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
641 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
646 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
647 addRegisterClass(VT, &AArch64::FPR64RegClass);
648 addTypeForNEON(VT, MVT::v2i32);
651 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
652 addRegisterClass(VT, &AArch64::FPR128RegClass);
653 addTypeForNEON(VT, MVT::v4i32);
656 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
659 return VT.changeVectorElementTypeToInteger();
662 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
663 /// Mask are known to be either zero or one and return them in the
664 /// KnownZero/KnownOne bitsets.
665 void AArch64TargetLowering::computeKnownBitsForTargetNode(
666 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
667 const SelectionDAG &DAG, unsigned Depth) const {
668 switch (Op.getOpcode()) {
671 case AArch64ISD::CSEL: {
672 APInt KnownZero2, KnownOne2;
673 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
674 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
675 KnownZero &= KnownZero2;
676 KnownOne &= KnownOne2;
679 case ISD::INTRINSIC_W_CHAIN: {
680 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
681 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
684 case Intrinsic::aarch64_ldaxr:
685 case Intrinsic::aarch64_ldxr: {
686 unsigned BitWidth = KnownOne.getBitWidth();
687 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
688 unsigned MemBits = VT.getScalarType().getSizeInBits();
689 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
695 case ISD::INTRINSIC_WO_CHAIN:
696 case ISD::INTRINSIC_VOID: {
697 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
701 case Intrinsic::aarch64_neon_umaxv:
702 case Intrinsic::aarch64_neon_uminv: {
703 // Figure out the datatype of the vector operand. The UMINV instruction
704 // will zero extend the result, so we can mark as known zero all the
705 // bits larger than the element datatype. 32-bit or larget doesn't need
706 // this as those are legal types and will be handled by isel directly.
707 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
708 unsigned BitWidth = KnownZero.getBitWidth();
709 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
710 assert(BitWidth >= 8 && "Unexpected width!");
711 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
713 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
714 assert(BitWidth >= 16 && "Unexpected width!");
715 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
725 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
729 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
730 // FIXME: On AArch64, this depends on the type.
731 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
732 // and the offset has to be a multiple of the related size in bytes.
737 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
738 const TargetLibraryInfo *libInfo) const {
739 return AArch64::createFastISel(funcInfo, libInfo);
742 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
746 case AArch64ISD::CALL: return "AArch64ISD::CALL";
747 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
748 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
749 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
750 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
751 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
752 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
753 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
754 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
755 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
756 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
757 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
758 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
759 case AArch64ISD::ADC: return "AArch64ISD::ADC";
760 case AArch64ISD::SBC: return "AArch64ISD::SBC";
761 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
762 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
763 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
764 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
765 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
766 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
767 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
768 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
769 case AArch64ISD::DUP: return "AArch64ISD::DUP";
770 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
771 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
772 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
773 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
774 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
775 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
776 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
777 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
778 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
779 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
780 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
781 case AArch64ISD::BICi: return "AArch64ISD::BICi";
782 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
783 case AArch64ISD::BSL: return "AArch64ISD::BSL";
784 case AArch64ISD::NEG: return "AArch64ISD::NEG";
785 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
786 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
787 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
788 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
789 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
790 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
791 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
792 case AArch64ISD::REV16: return "AArch64ISD::REV16";
793 case AArch64ISD::REV32: return "AArch64ISD::REV32";
794 case AArch64ISD::REV64: return "AArch64ISD::REV64";
795 case AArch64ISD::EXT: return "AArch64ISD::EXT";
796 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
797 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
798 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
799 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
800 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
801 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
802 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
803 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
804 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
805 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
806 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
807 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
808 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
809 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
810 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
811 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
812 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
813 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
814 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
815 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
816 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
817 case AArch64ISD::NOT: return "AArch64ISD::NOT";
818 case AArch64ISD::BIT: return "AArch64ISD::BIT";
819 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
820 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
821 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
822 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
823 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
824 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
825 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
826 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
827 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
828 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
829 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
830 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
831 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
832 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
833 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
834 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
835 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
836 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
837 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
838 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
839 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
840 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
841 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
842 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
843 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
844 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
845 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
846 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
847 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
848 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
849 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
850 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
851 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
852 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
853 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
854 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
859 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
860 MachineBasicBlock *MBB) const {
861 // We materialise the F128CSEL pseudo-instruction as some control flow and a
865 // [... previous instrs leading to comparison ...]
871 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
873 const TargetInstrInfo *TII =
874 getTargetMachine().getSubtargetImpl()->getInstrInfo();
875 MachineFunction *MF = MBB->getParent();
876 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
877 DebugLoc DL = MI->getDebugLoc();
878 MachineFunction::iterator It = MBB;
881 unsigned DestReg = MI->getOperand(0).getReg();
882 unsigned IfTrueReg = MI->getOperand(1).getReg();
883 unsigned IfFalseReg = MI->getOperand(2).getReg();
884 unsigned CondCode = MI->getOperand(3).getImm();
885 bool NZCVKilled = MI->getOperand(4).isKill();
887 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
888 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
889 MF->insert(It, TrueBB);
890 MF->insert(It, EndBB);
892 // Transfer rest of current basic-block to EndBB
893 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
895 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
897 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
898 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
899 MBB->addSuccessor(TrueBB);
900 MBB->addSuccessor(EndBB);
902 // TrueBB falls through to the end.
903 TrueBB->addSuccessor(EndBB);
906 TrueBB->addLiveIn(AArch64::NZCV);
907 EndBB->addLiveIn(AArch64::NZCV);
910 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
916 MI->eraseFromParent();
921 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
922 MachineBasicBlock *BB) const {
923 switch (MI->getOpcode()) {
928 llvm_unreachable("Unexpected instruction for custom inserter!");
930 case AArch64::F128CSEL:
931 return EmitF128CSEL(MI, BB);
933 case TargetOpcode::STACKMAP:
934 case TargetOpcode::PATCHPOINT:
935 return emitPatchPoint(MI, BB);
939 //===----------------------------------------------------------------------===//
940 // AArch64 Lowering private implementation.
941 //===----------------------------------------------------------------------===//
943 //===----------------------------------------------------------------------===//
945 //===----------------------------------------------------------------------===//
947 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
949 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
952 llvm_unreachable("Unknown condition code!");
954 return AArch64CC::NE;
956 return AArch64CC::EQ;
958 return AArch64CC::GT;
960 return AArch64CC::GE;
962 return AArch64CC::LT;
964 return AArch64CC::LE;
966 return AArch64CC::HI;
968 return AArch64CC::HS;
970 return AArch64CC::LO;
972 return AArch64CC::LS;
976 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
977 static void changeFPCCToAArch64CC(ISD::CondCode CC,
978 AArch64CC::CondCode &CondCode,
979 AArch64CC::CondCode &CondCode2) {
980 CondCode2 = AArch64CC::AL;
983 llvm_unreachable("Unknown FP condition!");
986 CondCode = AArch64CC::EQ;
990 CondCode = AArch64CC::GT;
994 CondCode = AArch64CC::GE;
997 CondCode = AArch64CC::MI;
1000 CondCode = AArch64CC::LS;
1003 CondCode = AArch64CC::MI;
1004 CondCode2 = AArch64CC::GT;
1007 CondCode = AArch64CC::VC;
1010 CondCode = AArch64CC::VS;
1013 CondCode = AArch64CC::EQ;
1014 CondCode2 = AArch64CC::VS;
1017 CondCode = AArch64CC::HI;
1020 CondCode = AArch64CC::PL;
1024 CondCode = AArch64CC::LT;
1028 CondCode = AArch64CC::LE;
1032 CondCode = AArch64CC::NE;
1037 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1038 /// CC usable with the vector instructions. Fewer operations are available
1039 /// without a real NZCV register, so we have to use less efficient combinations
1040 /// to get the same effect.
1041 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1042 AArch64CC::CondCode &CondCode,
1043 AArch64CC::CondCode &CondCode2,
1048 // Mostly the scalar mappings work fine.
1049 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1052 Invert = true; // Fallthrough
1054 CondCode = AArch64CC::MI;
1055 CondCode2 = AArch64CC::GE;
1062 // All of the compare-mask comparisons are ordered, but we can switch
1063 // between the two by a double inversion. E.g. ULE == !OGT.
1065 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1070 static bool isLegalArithImmed(uint64_t C) {
1071 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1072 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1075 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1076 SDLoc dl, SelectionDAG &DAG) {
1077 EVT VT = LHS.getValueType();
1079 if (VT.isFloatingPoint())
1080 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1082 // The CMP instruction is just an alias for SUBS, and representing it as
1083 // SUBS means that it's possible to get CSE with subtract operations.
1084 // A later phase can perform the optimization of setting the destination
1085 // register to WZR/XZR if it ends up being unused.
1086 unsigned Opcode = AArch64ISD::SUBS;
1088 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1089 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1090 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1091 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1092 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1093 // can be set differently by this operation. It comes down to whether
1094 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1095 // everything is fine. If not then the optimization is wrong. Thus general
1096 // comparisons are only valid if op2 != 0.
1098 // So, finally, the only LLVM-native comparisons that don't mention C and V
1099 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1100 // the absence of information about op2.
1101 Opcode = AArch64ISD::ADDS;
1102 RHS = RHS.getOperand(1);
1103 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1104 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1105 !isUnsignedIntSetCC(CC)) {
1106 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1107 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1108 // of the signed comparisons.
1109 Opcode = AArch64ISD::ANDS;
1110 RHS = LHS.getOperand(1);
1111 LHS = LHS.getOperand(0);
1114 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1118 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1119 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1121 AArch64CC::CondCode AArch64CC;
1122 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1123 EVT VT = RHS.getValueType();
1124 uint64_t C = RHSC->getZExtValue();
1125 if (!isLegalArithImmed(C)) {
1126 // Constant does not fit, try adjusting it by one?
1132 if ((VT == MVT::i32 && C != 0x80000000 &&
1133 isLegalArithImmed((uint32_t)(C - 1))) ||
1134 (VT == MVT::i64 && C != 0x80000000ULL &&
1135 isLegalArithImmed(C - 1ULL))) {
1136 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1137 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1138 RHS = DAG.getConstant(C, VT);
1143 if ((VT == MVT::i32 && C != 0 &&
1144 isLegalArithImmed((uint32_t)(C - 1))) ||
1145 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1146 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1147 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1148 RHS = DAG.getConstant(C, VT);
1153 if ((VT == MVT::i32 && C != 0x7fffffff &&
1154 isLegalArithImmed((uint32_t)(C + 1))) ||
1155 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1156 isLegalArithImmed(C + 1ULL))) {
1157 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1158 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1159 RHS = DAG.getConstant(C, VT);
1164 if ((VT == MVT::i32 && C != 0xffffffff &&
1165 isLegalArithImmed((uint32_t)(C + 1))) ||
1166 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1167 isLegalArithImmed(C + 1ULL))) {
1168 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1169 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1170 RHS = DAG.getConstant(C, VT);
1176 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1177 // For the i8 operand, the largest immediate is 255, so this can be easily
1178 // encoded in the compare instruction. For the i16 operand, however, the
1179 // largest immediate cannot be encoded in the compare.
1180 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1181 // constant. For example,
1183 // ldrh w0, [x0, #0]
1186 // ldrsh w0, [x0, #0]
1188 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1189 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1190 // both the LHS and RHS are truely zero extended and to make sure the
1191 // transformation is profitable.
1192 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1193 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1194 isa<LoadSDNode>(LHS)) {
1195 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1196 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1197 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1198 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1199 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1201 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1202 DAG.getValueType(MVT::i16));
1203 Cmp = emitComparison(SExt,
1204 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1206 AArch64CC = changeIntCCToAArch64CC(CC);
1207 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1213 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1214 AArch64CC = changeIntCCToAArch64CC(CC);
1215 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1219 static std::pair<SDValue, SDValue>
1220 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1221 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1222 "Unsupported value type");
1223 SDValue Value, Overflow;
1225 SDValue LHS = Op.getOperand(0);
1226 SDValue RHS = Op.getOperand(1);
1228 switch (Op.getOpcode()) {
1230 llvm_unreachable("Unknown overflow instruction!");
1232 Opc = AArch64ISD::ADDS;
1236 Opc = AArch64ISD::ADDS;
1240 Opc = AArch64ISD::SUBS;
1244 Opc = AArch64ISD::SUBS;
1247 // Multiply needs a little bit extra work.
1251 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1252 if (Op.getValueType() == MVT::i32) {
1253 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1254 // For a 32 bit multiply with overflow check we want the instruction
1255 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1256 // need to generate the following pattern:
1257 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1258 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1259 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1260 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1261 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1262 DAG.getConstant(0, MVT::i64));
1263 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1264 // operation. We need to clear out the upper 32 bits, because we used a
1265 // widening multiply that wrote all 64 bits. In the end this should be a
1267 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1269 // The signed overflow check requires more than just a simple check for
1270 // any bit set in the upper 32 bits of the result. These bits could be
1271 // just the sign bits of a negative number. To perform the overflow
1272 // check we have to arithmetic shift right the 32nd bit of the result by
1273 // 31 bits. Then we compare the result to the upper 32 bits.
1274 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1275 DAG.getConstant(32, MVT::i64));
1276 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1277 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1278 DAG.getConstant(31, MVT::i64));
1279 // It is important that LowerBits is last, otherwise the arithmetic
1280 // shift will not be folded into the compare (SUBS).
1281 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1282 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1285 // The overflow check for unsigned multiply is easy. We only need to
1286 // check if any of the upper 32 bits are set. This can be done with a
1287 // CMP (shifted register). For that we need to generate the following
1289 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1290 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1291 DAG.getConstant(32, MVT::i64));
1292 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1294 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1295 UpperBits).getValue(1);
1299 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1300 // For the 64 bit multiply
1301 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1303 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1304 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1305 DAG.getConstant(63, MVT::i64));
1306 // It is important that LowerBits is last, otherwise the arithmetic
1307 // shift will not be folded into the compare (SUBS).
1308 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1309 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1312 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1313 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1315 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1316 UpperBits).getValue(1);
1323 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1325 // Emit the AArch64 operation with overflow check.
1326 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1327 Overflow = Value.getValue(1);
1329 return std::make_pair(Value, Overflow);
1332 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1333 RTLIB::Libcall Call) const {
1334 SmallVector<SDValue, 2> Ops;
1335 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1336 Ops.push_back(Op.getOperand(i));
1338 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1342 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1343 SDValue Sel = Op.getOperand(0);
1344 SDValue Other = Op.getOperand(1);
1346 // If neither operand is a SELECT_CC, give up.
1347 if (Sel.getOpcode() != ISD::SELECT_CC)
1348 std::swap(Sel, Other);
1349 if (Sel.getOpcode() != ISD::SELECT_CC)
1352 // The folding we want to perform is:
1353 // (xor x, (select_cc a, b, cc, 0, -1) )
1355 // (csel x, (xor x, -1), cc ...)
1357 // The latter will get matched to a CSINV instruction.
1359 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1360 SDValue LHS = Sel.getOperand(0);
1361 SDValue RHS = Sel.getOperand(1);
1362 SDValue TVal = Sel.getOperand(2);
1363 SDValue FVal = Sel.getOperand(3);
1366 // FIXME: This could be generalized to non-integer comparisons.
1367 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1370 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1371 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1373 // The the values aren't constants, this isn't the pattern we're looking for.
1374 if (!CFVal || !CTVal)
1377 // We can commute the SELECT_CC by inverting the condition. This
1378 // might be needed to make this fit into a CSINV pattern.
1379 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1380 std::swap(TVal, FVal);
1381 std::swap(CTVal, CFVal);
1382 CC = ISD::getSetCCInverse(CC, true);
1385 // If the constants line up, perform the transform!
1386 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1388 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1391 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1392 DAG.getConstant(-1ULL, Other.getValueType()));
1394 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1401 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1402 EVT VT = Op.getValueType();
1404 // Let legalize expand this if it isn't a legal type yet.
1405 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1408 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1411 bool ExtraOp = false;
1412 switch (Op.getOpcode()) {
1414 llvm_unreachable("Invalid code");
1416 Opc = AArch64ISD::ADDS;
1419 Opc = AArch64ISD::SUBS;
1422 Opc = AArch64ISD::ADCS;
1426 Opc = AArch64ISD::SBCS;
1432 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1433 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1437 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1438 // Let legalize expand this if it isn't a legal type yet.
1439 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1442 AArch64CC::CondCode CC;
1443 // The actual operation that sets the overflow or carry flag.
1444 SDValue Value, Overflow;
1445 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1447 // We use 0 and 1 as false and true values.
1448 SDValue TVal = DAG.getConstant(1, MVT::i32);
1449 SDValue FVal = DAG.getConstant(0, MVT::i32);
1451 // We use an inverted condition, because the conditional select is inverted
1452 // too. This will allow it to be selected to a single instruction:
1453 // CSINC Wd, WZR, WZR, invert(cond).
1454 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1455 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1458 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1459 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1462 // Prefetch operands are:
1463 // 1: Address to prefetch
1465 // 3: int locality (0 = no locality ... 3 = extreme locality)
1466 // 4: bool isDataCache
1467 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1469 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1470 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1471 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1473 bool IsStream = !Locality;
1474 // When the locality number is set
1476 // The front-end should have filtered out the out-of-range values
1477 assert(Locality <= 3 && "Prefetch locality out-of-range");
1478 // The locality degree is the opposite of the cache speed.
1479 // Put the number the other way around.
1480 // The encoding starts at 0 for level 1
1481 Locality = 3 - Locality;
1484 // built the mask value encoding the expected behavior.
1485 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1486 (!IsData << 3) | // IsDataCache bit
1487 (Locality << 1) | // Cache level bits
1488 (unsigned)IsStream; // Stream bit
1489 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1490 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1493 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1494 SelectionDAG &DAG) const {
1495 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1498 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1500 return LowerF128Call(Op, DAG, LC);
1503 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1504 SelectionDAG &DAG) const {
1505 if (Op.getOperand(0).getValueType() != MVT::f128) {
1506 // It's legal except when f128 is involved
1511 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1513 // FP_ROUND node has a second operand indicating whether it is known to be
1514 // precise. That doesn't take part in the LibCall so we can't directly use
1516 SDValue SrcVal = Op.getOperand(0);
1517 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1518 /*isSigned*/ false, SDLoc(Op)).first;
1521 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1522 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1523 // Any additional optimization in this function should be recorded
1524 // in the cost tables.
1525 EVT InVT = Op.getOperand(0).getValueType();
1526 EVT VT = Op.getValueType();
1528 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1531 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1533 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1536 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1539 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1540 VT.getVectorNumElements());
1541 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1542 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1545 // Type changing conversions are illegal.
1549 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1550 SelectionDAG &DAG) const {
1551 if (Op.getOperand(0).getValueType().isVector())
1552 return LowerVectorFP_TO_INT(Op, DAG);
1554 if (Op.getOperand(0).getValueType() != MVT::f128) {
1555 // It's legal except when f128 is involved
1560 if (Op.getOpcode() == ISD::FP_TO_SINT)
1561 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1563 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1565 SmallVector<SDValue, 2> Ops;
1566 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1567 Ops.push_back(Op.getOperand(i));
1569 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1573 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1574 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1575 // Any additional optimization in this function should be recorded
1576 // in the cost tables.
1577 EVT VT = Op.getValueType();
1579 SDValue In = Op.getOperand(0);
1580 EVT InVT = In.getValueType();
1582 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1584 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1585 InVT.getVectorNumElements());
1586 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1587 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1590 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1592 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1593 EVT CastVT = VT.changeVectorElementTypeToInteger();
1594 In = DAG.getNode(CastOpc, dl, CastVT, In);
1595 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1601 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1602 SelectionDAG &DAG) const {
1603 if (Op.getValueType().isVector())
1604 return LowerVectorINT_TO_FP(Op, DAG);
1606 // i128 conversions are libcalls.
1607 if (Op.getOperand(0).getValueType() == MVT::i128)
1610 // Other conversions are legal, unless it's to the completely software-based
1612 if (Op.getValueType() != MVT::f128)
1616 if (Op.getOpcode() == ISD::SINT_TO_FP)
1617 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1619 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1621 return LowerF128Call(Op, DAG, LC);
1624 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1625 SelectionDAG &DAG) const {
1626 // For iOS, we want to call an alternative entry point: __sincos_stret,
1627 // which returns the values in two S / D registers.
1629 SDValue Arg = Op.getOperand(0);
1630 EVT ArgVT = Arg.getValueType();
1631 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1638 Entry.isSExt = false;
1639 Entry.isZExt = false;
1640 Args.push_back(Entry);
1642 const char *LibcallName =
1643 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1644 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1646 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1647 TargetLowering::CallLoweringInfo CLI(DAG);
1648 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1649 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1651 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1652 return CallResult.first;
1655 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1656 if (Op.getValueType() != MVT::f16)
1659 assert(Op.getOperand(0).getValueType() == MVT::i16);
1662 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1663 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1665 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1666 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1671 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1672 SelectionDAG &DAG) const {
1673 switch (Op.getOpcode()) {
1675 llvm_unreachable("unimplemented operand");
1678 return LowerBITCAST(Op, DAG);
1679 case ISD::GlobalAddress:
1680 return LowerGlobalAddress(Op, DAG);
1681 case ISD::GlobalTLSAddress:
1682 return LowerGlobalTLSAddress(Op, DAG);
1684 return LowerSETCC(Op, DAG);
1686 return LowerBR_CC(Op, DAG);
1688 return LowerSELECT(Op, DAG);
1689 case ISD::SELECT_CC:
1690 return LowerSELECT_CC(Op, DAG);
1691 case ISD::JumpTable:
1692 return LowerJumpTable(Op, DAG);
1693 case ISD::ConstantPool:
1694 return LowerConstantPool(Op, DAG);
1695 case ISD::BlockAddress:
1696 return LowerBlockAddress(Op, DAG);
1698 return LowerVASTART(Op, DAG);
1700 return LowerVACOPY(Op, DAG);
1702 return LowerVAARG(Op, DAG);
1707 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1714 return LowerXALUO(Op, DAG);
1716 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1718 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1720 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1722 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1724 return LowerFP_ROUND(Op, DAG);
1725 case ISD::FP_EXTEND:
1726 return LowerFP_EXTEND(Op, DAG);
1727 case ISD::FRAMEADDR:
1728 return LowerFRAMEADDR(Op, DAG);
1729 case ISD::RETURNADDR:
1730 return LowerRETURNADDR(Op, DAG);
1731 case ISD::INSERT_VECTOR_ELT:
1732 return LowerINSERT_VECTOR_ELT(Op, DAG);
1733 case ISD::EXTRACT_VECTOR_ELT:
1734 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1735 case ISD::BUILD_VECTOR:
1736 return LowerBUILD_VECTOR(Op, DAG);
1737 case ISD::VECTOR_SHUFFLE:
1738 return LowerVECTOR_SHUFFLE(Op, DAG);
1739 case ISD::EXTRACT_SUBVECTOR:
1740 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1744 return LowerVectorSRA_SRL_SHL(Op, DAG);
1745 case ISD::SHL_PARTS:
1746 return LowerShiftLeftParts(Op, DAG);
1747 case ISD::SRL_PARTS:
1748 case ISD::SRA_PARTS:
1749 return LowerShiftRightParts(Op, DAG);
1751 return LowerCTPOP(Op, DAG);
1752 case ISD::FCOPYSIGN:
1753 return LowerFCOPYSIGN(Op, DAG);
1755 return LowerVectorAND(Op, DAG);
1757 return LowerVectorOR(Op, DAG);
1759 return LowerXOR(Op, DAG);
1761 return LowerPREFETCH(Op, DAG);
1762 case ISD::SINT_TO_FP:
1763 case ISD::UINT_TO_FP:
1764 return LowerINT_TO_FP(Op, DAG);
1765 case ISD::FP_TO_SINT:
1766 case ISD::FP_TO_UINT:
1767 return LowerFP_TO_INT(Op, DAG);
1769 return LowerFSINCOS(Op, DAG);
1773 /// getFunctionAlignment - Return the Log2 alignment of this function.
1774 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1778 //===----------------------------------------------------------------------===//
1779 // Calling Convention Implementation
1780 //===----------------------------------------------------------------------===//
1782 #include "AArch64GenCallingConv.inc"
1784 /// Selects the correct CCAssignFn for a the given CallingConvention
1786 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1787 bool IsVarArg) const {
1790 llvm_unreachable("Unsupported calling convention.");
1791 case CallingConv::WebKit_JS:
1792 return CC_AArch64_WebKit_JS;
1793 case CallingConv::C:
1794 case CallingConv::Fast:
1795 if (!Subtarget->isTargetDarwin())
1796 return CC_AArch64_AAPCS;
1797 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1801 SDValue AArch64TargetLowering::LowerFormalArguments(
1802 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1803 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1804 SmallVectorImpl<SDValue> &InVals) const {
1805 MachineFunction &MF = DAG.getMachineFunction();
1806 MachineFrameInfo *MFI = MF.getFrameInfo();
1808 // Assign locations to all of the incoming arguments.
1809 SmallVector<CCValAssign, 16> ArgLocs;
1810 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1813 // At this point, Ins[].VT may already be promoted to i32. To correctly
1814 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1815 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1816 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1817 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1819 unsigned NumArgs = Ins.size();
1820 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1821 unsigned CurArgIdx = 0;
1822 for (unsigned i = 0; i != NumArgs; ++i) {
1823 MVT ValVT = Ins[i].VT;
1824 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1825 CurArgIdx = Ins[i].OrigArgIndex;
1827 // Get type of the original argument.
1828 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1829 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1830 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1831 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1833 else if (ActualMVT == MVT::i16)
1836 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1838 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1839 assert(!Res && "Call operand has unhandled type");
1842 assert(ArgLocs.size() == Ins.size());
1843 SmallVector<SDValue, 16> ArgValues;
1844 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1845 CCValAssign &VA = ArgLocs[i];
1847 if (Ins[i].Flags.isByVal()) {
1848 // Byval is used for HFAs in the PCS, but the system should work in a
1849 // non-compliant manner for larger structs.
1850 EVT PtrTy = getPointerTy();
1851 int Size = Ins[i].Flags.getByValSize();
1852 unsigned NumRegs = (Size + 7) / 8;
1854 // FIXME: This works on big-endian for composite byvals, which are the common
1855 // case. It should also work for fundamental types too.
1857 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1858 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1859 InVals.push_back(FrameIdxN);
1864 if (VA.isRegLoc()) {
1865 // Arguments stored in registers.
1866 EVT RegVT = VA.getLocVT();
1869 const TargetRegisterClass *RC;
1871 if (RegVT == MVT::i32)
1872 RC = &AArch64::GPR32RegClass;
1873 else if (RegVT == MVT::i64)
1874 RC = &AArch64::GPR64RegClass;
1875 else if (RegVT == MVT::f16)
1876 RC = &AArch64::FPR16RegClass;
1877 else if (RegVT == MVT::f32)
1878 RC = &AArch64::FPR32RegClass;
1879 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1880 RC = &AArch64::FPR64RegClass;
1881 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1882 RC = &AArch64::FPR128RegClass;
1884 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1886 // Transform the arguments in physical registers into virtual ones.
1887 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1888 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1890 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1891 // to 64 bits. Insert an assert[sz]ext to capture this, then
1892 // truncate to the right size.
1893 switch (VA.getLocInfo()) {
1895 llvm_unreachable("Unknown loc info!");
1896 case CCValAssign::Full:
1898 case CCValAssign::BCvt:
1899 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1901 case CCValAssign::AExt:
1902 case CCValAssign::SExt:
1903 case CCValAssign::ZExt:
1904 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1905 // nodes after our lowering.
1906 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1910 InVals.push_back(ArgValue);
1912 } else { // VA.isRegLoc()
1913 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1914 unsigned ArgOffset = VA.getLocMemOffset();
1915 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
1917 uint32_t BEAlign = 0;
1918 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1919 BEAlign = 8 - ArgSize;
1921 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1923 // Create load nodes to retrieve arguments from the stack.
1924 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1927 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1928 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1929 MVT MemVT = VA.getValVT();
1931 switch (VA.getLocInfo()) {
1934 case CCValAssign::BCvt:
1935 MemVT = VA.getLocVT();
1937 case CCValAssign::SExt:
1938 ExtType = ISD::SEXTLOAD;
1940 case CCValAssign::ZExt:
1941 ExtType = ISD::ZEXTLOAD;
1943 case CCValAssign::AExt:
1944 ExtType = ISD::EXTLOAD;
1948 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1949 MachinePointerInfo::getFixedStack(FI),
1950 MemVT, false, false, false, 0, nullptr);
1952 InVals.push_back(ArgValue);
1958 if (!Subtarget->isTargetDarwin()) {
1959 // The AAPCS variadic function ABI is identical to the non-variadic
1960 // one. As a result there may be more arguments in registers and we should
1961 // save them for future reference.
1962 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1965 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1966 // This will point to the next argument passed via stack.
1967 unsigned StackOffset = CCInfo.getNextStackOffset();
1968 // We currently pass all varargs at 8-byte alignment.
1969 StackOffset = ((StackOffset + 7) & ~7);
1970 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1973 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1974 unsigned StackArgSize = CCInfo.getNextStackOffset();
1975 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1976 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1977 // This is a non-standard ABI so by fiat I say we're allowed to make full
1978 // use of the stack area to be popped, which must be aligned to 16 bytes in
1980 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1982 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1983 // a multiple of 16.
1984 FuncInfo->setArgumentStackToRestore(StackArgSize);
1986 // This realignment carries over to the available bytes below. Our own
1987 // callers will guarantee the space is free by giving an aligned value to
1990 // Even if we're not expected to free up the space, it's useful to know how
1991 // much is there while considering tail calls (because we can reuse it).
1992 FuncInfo->setBytesInStackArgArea(StackArgSize);
1997 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1998 SelectionDAG &DAG, SDLoc DL,
1999 SDValue &Chain) const {
2000 MachineFunction &MF = DAG.getMachineFunction();
2001 MachineFrameInfo *MFI = MF.getFrameInfo();
2002 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2004 SmallVector<SDValue, 8> MemOps;
2006 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2007 AArch64::X3, AArch64::X4, AArch64::X5,
2008 AArch64::X6, AArch64::X7 };
2009 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2010 unsigned FirstVariadicGPR =
2011 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
2013 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2015 if (GPRSaveSize != 0) {
2016 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2018 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2020 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2021 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2022 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2024 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2025 MachinePointerInfo::getStack(i * 8), false, false, 0);
2026 MemOps.push_back(Store);
2027 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2028 DAG.getConstant(8, getPointerTy()));
2031 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2032 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2034 if (Subtarget->hasFPARMv8()) {
2035 static const MCPhysReg FPRArgRegs[] = {
2036 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2037 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2038 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2039 unsigned FirstVariadicFPR =
2040 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
2042 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2044 if (FPRSaveSize != 0) {
2045 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2047 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2049 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2050 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2051 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2054 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2055 MachinePointerInfo::getStack(i * 16), false, false, 0);
2056 MemOps.push_back(Store);
2057 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2058 DAG.getConstant(16, getPointerTy()));
2061 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2062 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2065 if (!MemOps.empty()) {
2066 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2070 /// LowerCallResult - Lower the result values of a call into the
2071 /// appropriate copies out of appropriate physical registers.
2072 SDValue AArch64TargetLowering::LowerCallResult(
2073 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2074 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2075 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2076 SDValue ThisVal) const {
2077 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2078 ? RetCC_AArch64_WebKit_JS
2079 : RetCC_AArch64_AAPCS;
2080 // Assign locations to each value returned by this call.
2081 SmallVector<CCValAssign, 16> RVLocs;
2082 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2084 CCInfo.AnalyzeCallResult(Ins, RetCC);
2086 // Copy all of the result registers out of their specified physreg.
2087 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2088 CCValAssign VA = RVLocs[i];
2090 // Pass 'this' value directly from the argument to return value, to avoid
2091 // reg unit interference
2092 if (i == 0 && isThisReturn) {
2093 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2094 "unexpected return calling convention register assignment");
2095 InVals.push_back(ThisVal);
2100 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2101 Chain = Val.getValue(1);
2102 InFlag = Val.getValue(2);
2104 switch (VA.getLocInfo()) {
2106 llvm_unreachable("Unknown loc info!");
2107 case CCValAssign::Full:
2109 case CCValAssign::BCvt:
2110 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2114 InVals.push_back(Val);
2120 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2121 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2122 bool isCalleeStructRet, bool isCallerStructRet,
2123 const SmallVectorImpl<ISD::OutputArg> &Outs,
2124 const SmallVectorImpl<SDValue> &OutVals,
2125 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2126 // For CallingConv::C this function knows whether the ABI needs
2127 // changing. That's not true for other conventions so they will have to opt in
2129 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2132 const MachineFunction &MF = DAG.getMachineFunction();
2133 const Function *CallerF = MF.getFunction();
2134 CallingConv::ID CallerCC = CallerF->getCallingConv();
2135 bool CCMatch = CallerCC == CalleeCC;
2137 // Byval parameters hand the function a pointer directly into the stack area
2138 // we want to reuse during a tail call. Working around this *is* possible (see
2139 // X86) but less efficient and uglier in LowerCall.
2140 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2141 e = CallerF->arg_end();
2143 if (i->hasByValAttr())
2146 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2147 if (IsTailCallConvention(CalleeCC) && CCMatch)
2152 // Externally-defined functions with weak linkage should not be
2153 // tail-called on AArch64 when the OS does not support dynamic
2154 // pre-emption of symbols, as the AAELF spec requires normal calls
2155 // to undefined weak functions to be replaced with a NOP or jump to the
2156 // next instruction. The behaviour of branch instructions in this
2157 // situation (as used for tail calls) is implementation-defined, so we
2158 // cannot rely on the linker replacing the tail call with a return.
2159 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2160 const GlobalValue *GV = G->getGlobal();
2161 if (GV->hasExternalWeakLinkage())
2165 // Now we search for cases where we can use a tail call without changing the
2166 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2169 // I want anyone implementing a new calling convention to think long and hard
2170 // about this assert.
2171 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2172 "Unexpected variadic calling convention");
2174 if (isVarArg && !Outs.empty()) {
2175 // At least two cases here: if caller is fastcc then we can't have any
2176 // memory arguments (we'd be expected to clean up the stack afterwards). If
2177 // caller is C then we could potentially use its argument area.
2179 // FIXME: for now we take the most conservative of these in both cases:
2180 // disallow all variadic memory operands.
2181 SmallVector<CCValAssign, 16> ArgLocs;
2182 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2185 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2186 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2187 if (!ArgLocs[i].isRegLoc())
2191 // If the calling conventions do not match, then we'd better make sure the
2192 // results are returned in the same way as what the caller expects.
2194 SmallVector<CCValAssign, 16> RVLocs1;
2195 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2197 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2199 SmallVector<CCValAssign, 16> RVLocs2;
2200 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2202 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2204 if (RVLocs1.size() != RVLocs2.size())
2206 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2207 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2209 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2211 if (RVLocs1[i].isRegLoc()) {
2212 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2215 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2221 // Nothing more to check if the callee is taking no arguments
2225 SmallVector<CCValAssign, 16> ArgLocs;
2226 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2229 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2231 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2233 // If the stack arguments for this call would fit into our own save area then
2234 // the call can be made tail.
2235 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2238 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2240 MachineFrameInfo *MFI,
2241 int ClobberedFI) const {
2242 SmallVector<SDValue, 8> ArgChains;
2243 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2244 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2246 // Include the original chain at the beginning of the list. When this is
2247 // used by target LowerCall hooks, this helps legalize find the
2248 // CALLSEQ_BEGIN node.
2249 ArgChains.push_back(Chain);
2251 // Add a chain value for each stack argument corresponding
2252 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2253 UE = DAG.getEntryNode().getNode()->use_end();
2255 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2256 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2257 if (FI->getIndex() < 0) {
2258 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2259 int64_t InLastByte = InFirstByte;
2260 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2262 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2263 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2264 ArgChains.push_back(SDValue(L, 1));
2267 // Build a tokenfactor for all the chains.
2268 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2271 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2272 bool TailCallOpt) const {
2273 return CallCC == CallingConv::Fast && TailCallOpt;
2276 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2277 return CallCC == CallingConv::Fast;
2280 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2281 /// and add input and output parameter nodes.
2283 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2284 SmallVectorImpl<SDValue> &InVals) const {
2285 SelectionDAG &DAG = CLI.DAG;
2287 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2288 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2289 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2290 SDValue Chain = CLI.Chain;
2291 SDValue Callee = CLI.Callee;
2292 bool &IsTailCall = CLI.IsTailCall;
2293 CallingConv::ID CallConv = CLI.CallConv;
2294 bool IsVarArg = CLI.IsVarArg;
2296 MachineFunction &MF = DAG.getMachineFunction();
2297 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2298 bool IsThisReturn = false;
2300 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2301 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2302 bool IsSibCall = false;
2305 // Check if it's really possible to do a tail call.
2306 IsTailCall = isEligibleForTailCallOptimization(
2307 Callee, CallConv, IsVarArg, IsStructRet,
2308 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2309 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2310 report_fatal_error("failed to perform tail call elimination on a call "
2311 "site marked musttail");
2313 // A sibling call is one where we're under the usual C ABI and not planning
2314 // to change that but can still do a tail call:
2315 if (!TailCallOpt && IsTailCall)
2322 // Analyze operands of the call, assigning locations to each operand.
2323 SmallVector<CCValAssign, 16> ArgLocs;
2324 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2328 // Handle fixed and variable vector arguments differently.
2329 // Variable vector arguments always go into memory.
2330 unsigned NumArgs = Outs.size();
2332 for (unsigned i = 0; i != NumArgs; ++i) {
2333 MVT ArgVT = Outs[i].VT;
2334 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2335 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2336 /*IsVarArg=*/ !Outs[i].IsFixed);
2337 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2338 assert(!Res && "Call operand has unhandled type");
2342 // At this point, Outs[].VT may already be promoted to i32. To correctly
2343 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2344 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2345 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2346 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2348 unsigned NumArgs = Outs.size();
2349 for (unsigned i = 0; i != NumArgs; ++i) {
2350 MVT ValVT = Outs[i].VT;
2351 // Get type of the original argument.
2352 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2353 /*AllowUnknown*/ true);
2354 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2355 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2356 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2357 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2359 else if (ActualMVT == MVT::i16)
2362 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2363 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2364 assert(!Res && "Call operand has unhandled type");
2369 // Get a count of how many bytes are to be pushed on the stack.
2370 unsigned NumBytes = CCInfo.getNextStackOffset();
2373 // Since we're not changing the ABI to make this a tail call, the memory
2374 // operands are already available in the caller's incoming argument space.
2378 // FPDiff is the byte offset of the call's argument area from the callee's.
2379 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2380 // by this amount for a tail call. In a sibling call it must be 0 because the
2381 // caller will deallocate the entire stack and the callee still expects its
2382 // arguments to begin at SP+0. Completely unused for non-tail calls.
2385 if (IsTailCall && !IsSibCall) {
2386 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2388 // Since callee will pop argument stack as a tail call, we must keep the
2389 // popped size 16-byte aligned.
2390 NumBytes = RoundUpToAlignment(NumBytes, 16);
2392 // FPDiff will be negative if this tail call requires more space than we
2393 // would automatically have in our incoming argument space. Positive if we
2394 // can actually shrink the stack.
2395 FPDiff = NumReusableBytes - NumBytes;
2397 // The stack pointer must be 16-byte aligned at all times it's used for a
2398 // memory operation, which in practice means at *all* times and in
2399 // particular across call boundaries. Therefore our own arguments started at
2400 // a 16-byte aligned SP and the delta applied for the tail call should
2401 // satisfy the same constraint.
2402 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2405 // Adjust the stack pointer for the new arguments...
2406 // These operations are automatically eliminated by the prolog/epilog pass
2409 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2411 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2413 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2414 SmallVector<SDValue, 8> MemOpChains;
2416 // Walk the register/memloc assignments, inserting copies/loads.
2417 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2418 ++i, ++realArgIdx) {
2419 CCValAssign &VA = ArgLocs[i];
2420 SDValue Arg = OutVals[realArgIdx];
2421 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2423 // Promote the value if needed.
2424 switch (VA.getLocInfo()) {
2426 llvm_unreachable("Unknown loc info!");
2427 case CCValAssign::Full:
2429 case CCValAssign::SExt:
2430 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2432 case CCValAssign::ZExt:
2433 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2435 case CCValAssign::AExt:
2436 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2437 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2438 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2439 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2441 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2443 case CCValAssign::BCvt:
2444 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2446 case CCValAssign::FPExt:
2447 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2451 if (VA.isRegLoc()) {
2452 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2453 assert(VA.getLocVT() == MVT::i64 &&
2454 "unexpected calling convention register assignment");
2455 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2456 "unexpected use of 'returned'");
2457 IsThisReturn = true;
2459 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2461 assert(VA.isMemLoc());
2464 MachinePointerInfo DstInfo;
2466 // FIXME: This works on big-endian for composite byvals, which are the
2467 // common case. It should also work for fundamental types too.
2468 uint32_t BEAlign = 0;
2469 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2470 : VA.getValVT().getSizeInBits();
2471 OpSize = (OpSize + 7) / 8;
2472 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2474 BEAlign = 8 - OpSize;
2476 unsigned LocMemOffset = VA.getLocMemOffset();
2477 int32_t Offset = LocMemOffset + BEAlign;
2478 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2479 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2482 Offset = Offset + FPDiff;
2483 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2485 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2486 DstInfo = MachinePointerInfo::getFixedStack(FI);
2488 // Make sure any stack arguments overlapping with where we're storing
2489 // are loaded before this eventual operation. Otherwise they'll be
2491 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2493 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2495 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2496 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2499 if (Outs[i].Flags.isByVal()) {
2501 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2502 SDValue Cpy = DAG.getMemcpy(
2503 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2505 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2507 MemOpChains.push_back(Cpy);
2509 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2510 // promoted to a legal register type i32, we should truncate Arg back to
2512 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2513 VA.getValVT() == MVT::i16)
2514 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2517 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2518 MemOpChains.push_back(Store);
2523 if (!MemOpChains.empty())
2524 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2526 // Build a sequence of copy-to-reg nodes chained together with token chain
2527 // and flag operands which copy the outgoing args into the appropriate regs.
2529 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2530 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2531 RegsToPass[i].second, InFlag);
2532 InFlag = Chain.getValue(1);
2535 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2536 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2537 // node so that legalize doesn't hack it.
2538 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2539 Subtarget->isTargetMachO()) {
2540 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2541 const GlobalValue *GV = G->getGlobal();
2542 bool InternalLinkage = GV->hasInternalLinkage();
2543 if (InternalLinkage)
2544 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2546 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2548 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2550 } else if (ExternalSymbolSDNode *S =
2551 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2552 const char *Sym = S->getSymbol();
2554 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2555 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2557 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2558 const GlobalValue *GV = G->getGlobal();
2559 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2560 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2561 const char *Sym = S->getSymbol();
2562 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2565 // We don't usually want to end the call-sequence here because we would tidy
2566 // the frame up *after* the call, however in the ABI-changing tail-call case
2567 // we've carefully laid out the parameters so that when sp is reset they'll be
2568 // in the correct location.
2569 if (IsTailCall && !IsSibCall) {
2570 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2571 DAG.getIntPtrConstant(0, true), InFlag, DL);
2572 InFlag = Chain.getValue(1);
2575 std::vector<SDValue> Ops;
2576 Ops.push_back(Chain);
2577 Ops.push_back(Callee);
2580 // Each tail call may have to adjust the stack by a different amount, so
2581 // this information must travel along with the operation for eventual
2582 // consumption by emitEpilogue.
2583 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2586 // Add argument registers to the end of the list so that they are known live
2588 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2589 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2590 RegsToPass[i].second.getValueType()));
2592 // Add a register mask operand representing the call-preserved registers.
2593 const uint32_t *Mask;
2594 const TargetRegisterInfo *TRI =
2595 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2596 const AArch64RegisterInfo *ARI =
2597 static_cast<const AArch64RegisterInfo *>(TRI);
2599 // For 'this' returns, use the X0-preserving mask if applicable
2600 Mask = ARI->getThisReturnPreservedMask(CallConv);
2602 IsThisReturn = false;
2603 Mask = ARI->getCallPreservedMask(CallConv);
2606 Mask = ARI->getCallPreservedMask(CallConv);
2608 assert(Mask && "Missing call preserved mask for calling convention");
2609 Ops.push_back(DAG.getRegisterMask(Mask));
2611 if (InFlag.getNode())
2612 Ops.push_back(InFlag);
2614 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2616 // If we're doing a tall call, use a TC_RETURN here rather than an
2617 // actual call instruction.
2619 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2621 // Returns a chain and a flag for retval copy to use.
2622 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2623 InFlag = Chain.getValue(1);
2625 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2626 ? RoundUpToAlignment(NumBytes, 16)
2629 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2630 DAG.getIntPtrConstant(CalleePopBytes, true),
2633 InFlag = Chain.getValue(1);
2635 // Handle result values, copying them out of physregs into vregs that we
2637 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2638 InVals, IsThisReturn,
2639 IsThisReturn ? OutVals[0] : SDValue());
2642 bool AArch64TargetLowering::CanLowerReturn(
2643 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2644 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2645 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2646 ? RetCC_AArch64_WebKit_JS
2647 : RetCC_AArch64_AAPCS;
2648 SmallVector<CCValAssign, 16> RVLocs;
2649 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2650 return CCInfo.CheckReturn(Outs, RetCC);
2654 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2656 const SmallVectorImpl<ISD::OutputArg> &Outs,
2657 const SmallVectorImpl<SDValue> &OutVals,
2658 SDLoc DL, SelectionDAG &DAG) const {
2659 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2660 ? RetCC_AArch64_WebKit_JS
2661 : RetCC_AArch64_AAPCS;
2662 SmallVector<CCValAssign, 16> RVLocs;
2663 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2665 CCInfo.AnalyzeReturn(Outs, RetCC);
2667 // Copy the result values into the output registers.
2669 SmallVector<SDValue, 4> RetOps(1, Chain);
2670 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2671 ++i, ++realRVLocIdx) {
2672 CCValAssign &VA = RVLocs[i];
2673 assert(VA.isRegLoc() && "Can only return in registers!");
2674 SDValue Arg = OutVals[realRVLocIdx];
2676 switch (VA.getLocInfo()) {
2678 llvm_unreachable("Unknown loc info!");
2679 case CCValAssign::Full:
2680 if (Outs[i].ArgVT == MVT::i1) {
2681 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2682 // value. This is strictly redundant on Darwin (which uses "zeroext
2683 // i1"), but will be optimised out before ISel.
2684 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2685 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2688 case CCValAssign::BCvt:
2689 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2693 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2694 Flag = Chain.getValue(1);
2695 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2698 RetOps[0] = Chain; // Update chain.
2700 // Add the flag if we have it.
2702 RetOps.push_back(Flag);
2704 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2707 //===----------------------------------------------------------------------===//
2708 // Other Lowering Code
2709 //===----------------------------------------------------------------------===//
2711 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2712 SelectionDAG &DAG) const {
2713 EVT PtrVT = getPointerTy();
2715 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2716 unsigned char OpFlags =
2717 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2719 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2720 "unexpected offset in global node");
2722 // This also catched the large code model case for Darwin.
2723 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2724 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2725 // FIXME: Once remat is capable of dealing with instructions with register
2726 // operands, expand this into two nodes instead of using a wrapper node.
2727 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2730 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2731 const unsigned char MO_NC = AArch64II::MO_NC;
2733 AArch64ISD::WrapperLarge, DL, PtrVT,
2734 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2735 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2736 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2737 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2739 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2740 // the only correct model on Darwin.
2741 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2742 OpFlags | AArch64II::MO_PAGE);
2743 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2744 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2746 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2747 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2751 /// \brief Convert a TLS address reference into the correct sequence of loads
2752 /// and calls to compute the variable's address (for Darwin, currently) and
2753 /// return an SDValue containing the final node.
2755 /// Darwin only has one TLS scheme which must be capable of dealing with the
2756 /// fully general situation, in the worst case. This means:
2757 /// + "extern __thread" declaration.
2758 /// + Defined in a possibly unknown dynamic library.
2760 /// The general system is that each __thread variable has a [3 x i64] descriptor
2761 /// which contains information used by the runtime to calculate the address. The
2762 /// only part of this the compiler needs to know about is the first xword, which
2763 /// contains a function pointer that must be called with the address of the
2764 /// entire descriptor in "x0".
2766 /// Since this descriptor may be in a different unit, in general even the
2767 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2769 /// adrp x0, _var@TLVPPAGE
2770 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2771 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2772 /// ; the function pointer
2773 /// blr x1 ; Uses descriptor address in x0
2774 /// ; Address of _var is now in x0.
2776 /// If the address of _var's descriptor *is* known to the linker, then it can
2777 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2778 /// a slight efficiency gain.
2780 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2781 SelectionDAG &DAG) const {
2782 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2785 MVT PtrVT = getPointerTy();
2786 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2789 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2790 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2792 // The first entry in the descriptor is a function pointer that we must call
2793 // to obtain the address of the variable.
2794 SDValue Chain = DAG.getEntryNode();
2795 SDValue FuncTLVGet =
2796 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2797 false, true, true, 8);
2798 Chain = FuncTLVGet.getValue(1);
2800 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2801 MFI->setAdjustsStack(true);
2803 // TLS calls preserve all registers except those that absolutely must be
2804 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2806 const TargetRegisterInfo *TRI =
2807 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2808 const AArch64RegisterInfo *ARI =
2809 static_cast<const AArch64RegisterInfo *>(TRI);
2810 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2812 // Finally, we can make the call. This is just a degenerate version of a
2813 // normal AArch64 call node: x0 takes the address of the descriptor, and
2814 // returns the address of the variable in this thread.
2815 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2817 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2818 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2819 DAG.getRegisterMask(Mask), Chain.getValue(1));
2820 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2823 /// When accessing thread-local variables under either the general-dynamic or
2824 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2825 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2826 /// is a function pointer to carry out the resolution. This function takes the
2827 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2828 /// other registers (except LR, NZCV) are preserved.
2830 /// Thus, the ideal call sequence on AArch64 is:
2832 /// adrp x0, :tlsdesc:thread_var
2833 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2834 /// add x0, x0, :tlsdesc_lo12:thread_var
2835 /// .tlsdesccall thread_var
2837 /// (TPIDR_EL0 offset now in x0).
2839 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2840 /// relocation to help the linker relax this sequence if it turns out to be too
2843 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2845 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2846 SDValue DescAddr, SDLoc DL,
2847 SelectionDAG &DAG) const {
2848 EVT PtrVT = getPointerTy();
2850 // The function we need to call is simply the first entry in the GOT for this
2851 // descriptor, load it in preparation.
2852 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2854 // TLS calls preserve all registers except those that absolutely must be
2855 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2857 const TargetRegisterInfo *TRI =
2858 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2859 const AArch64RegisterInfo *ARI =
2860 static_cast<const AArch64RegisterInfo *>(TRI);
2861 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2863 // The function takes only one argument: the address of the descriptor itself
2865 SDValue Glue, Chain;
2866 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2867 Glue = Chain.getValue(1);
2869 // We're now ready to populate the argument list, as with a normal call:
2870 SmallVector<SDValue, 6> Ops;
2871 Ops.push_back(Chain);
2872 Ops.push_back(Func);
2873 Ops.push_back(SymAddr);
2874 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2875 Ops.push_back(DAG.getRegisterMask(Mask));
2876 Ops.push_back(Glue);
2878 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2879 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2880 Glue = Chain.getValue(1);
2882 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2886 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2887 SelectionDAG &DAG) const {
2888 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2889 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2890 "ELF TLS only supported in small memory model");
2891 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2893 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2896 EVT PtrVT = getPointerTy();
2898 const GlobalValue *GV = GA->getGlobal();
2900 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2902 if (Model == TLSModel::LocalExec) {
2903 SDValue HiVar = DAG.getTargetGlobalAddress(
2904 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2905 SDValue LoVar = DAG.getTargetGlobalAddress(
2907 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2909 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2910 DAG.getTargetConstant(16, MVT::i32)),
2912 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2913 DAG.getTargetConstant(0, MVT::i32)),
2915 } else if (Model == TLSModel::InitialExec) {
2916 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2917 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2918 } else if (Model == TLSModel::LocalDynamic) {
2919 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2920 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2921 // the beginning of the module's TLS region, followed by a DTPREL offset
2924 // These accesses will need deduplicating if there's more than one.
2925 AArch64FunctionInfo *MFI =
2926 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2927 MFI->incNumLocalDynamicTLSAccesses();
2929 // Accesses used in this sequence go via the TLS descriptor which lives in
2930 // the GOT. Prepare an address we can use to handle this.
2931 SDValue HiDesc = DAG.getTargetExternalSymbol(
2932 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2933 SDValue LoDesc = DAG.getTargetExternalSymbol(
2934 "_TLS_MODULE_BASE_", PtrVT,
2935 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2937 // First argument to the descriptor call is the address of the descriptor
2939 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2940 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2942 // The call needs a relocation too for linker relaxation. It doesn't make
2943 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2945 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2948 // Now we can calculate the offset from TPIDR_EL0 to this module's
2949 // thread-local area.
2950 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2952 // Now use :dtprel_whatever: operations to calculate this variable's offset
2953 // in its thread-storage area.
2954 SDValue HiVar = DAG.getTargetGlobalAddress(
2955 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2956 SDValue LoVar = DAG.getTargetGlobalAddress(
2957 GV, DL, MVT::i64, 0,
2958 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2961 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2962 DAG.getTargetConstant(16, MVT::i32)),
2965 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2966 DAG.getTargetConstant(0, MVT::i32)),
2969 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2970 } else if (Model == TLSModel::GeneralDynamic) {
2971 // Accesses used in this sequence go via the TLS descriptor which lives in
2972 // the GOT. Prepare an address we can use to handle this.
2973 SDValue HiDesc = DAG.getTargetGlobalAddress(
2974 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2975 SDValue LoDesc = DAG.getTargetGlobalAddress(
2977 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2979 // First argument to the descriptor call is the address of the descriptor
2981 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2982 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2984 // The call needs a relocation too for linker relaxation. It doesn't make
2985 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2988 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2990 // Finally we can make a call to calculate the offset from tpidr_el0.
2991 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2993 llvm_unreachable("Unsupported ELF TLS access model");
2995 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2998 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2999 SelectionDAG &DAG) const {
3000 if (Subtarget->isTargetDarwin())
3001 return LowerDarwinGlobalTLSAddress(Op, DAG);
3002 else if (Subtarget->isTargetELF())
3003 return LowerELFGlobalTLSAddress(Op, DAG);
3005 llvm_unreachable("Unexpected platform trying to use TLS");
3007 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3008 SDValue Chain = Op.getOperand(0);
3009 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3010 SDValue LHS = Op.getOperand(2);
3011 SDValue RHS = Op.getOperand(3);
3012 SDValue Dest = Op.getOperand(4);
3015 // Handle f128 first, since lowering it will result in comparing the return
3016 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3017 // is expecting to deal with.
3018 if (LHS.getValueType() == MVT::f128) {
3019 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3021 // If softenSetCCOperands returned a scalar, we need to compare the result
3022 // against zero to select between true and false values.
3023 if (!RHS.getNode()) {
3024 RHS = DAG.getConstant(0, LHS.getValueType());
3029 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3031 unsigned Opc = LHS.getOpcode();
3032 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3033 cast<ConstantSDNode>(RHS)->isOne() &&
3034 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3035 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3036 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3037 "Unexpected condition code.");
3038 // Only lower legal XALUO ops.
3039 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3042 // The actual operation with overflow check.
3043 AArch64CC::CondCode OFCC;
3044 SDValue Value, Overflow;
3045 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3047 if (CC == ISD::SETNE)
3048 OFCC = getInvertedCondCode(OFCC);
3049 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3051 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
3055 if (LHS.getValueType().isInteger()) {
3056 assert((LHS.getValueType() == RHS.getValueType()) &&
3057 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3059 // If the RHS of the comparison is zero, we can potentially fold this
3060 // to a specialized branch.
3061 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3062 if (RHSC && RHSC->getZExtValue() == 0) {
3063 if (CC == ISD::SETEQ) {
3064 // See if we can use a TBZ to fold in an AND as well.
3065 // TBZ has a smaller branch displacement than CBZ. If the offset is
3066 // out of bounds, a late MI-layer pass rewrites branches.
3067 // 403.gcc is an example that hits this case.
3068 if (LHS.getOpcode() == ISD::AND &&
3069 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3070 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3071 SDValue Test = LHS.getOperand(0);
3072 uint64_t Mask = LHS.getConstantOperandVal(1);
3073 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3074 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3077 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3078 } else if (CC == ISD::SETNE) {
3079 // See if we can use a TBZ to fold in an AND as well.
3080 // TBZ has a smaller branch displacement than CBZ. If the offset is
3081 // out of bounds, a late MI-layer pass rewrites branches.
3082 // 403.gcc is an example that hits this case.
3083 if (LHS.getOpcode() == ISD::AND &&
3084 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3085 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3086 SDValue Test = LHS.getOperand(0);
3087 uint64_t Mask = LHS.getConstantOperandVal(1);
3088 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3089 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3092 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3093 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3094 // Don't combine AND since emitComparison converts the AND to an ANDS
3095 // (a.k.a. TST) and the test in the test bit and branch instruction
3096 // becomes redundant. This would also increase register pressure.
3097 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3098 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3099 DAG.getConstant(Mask, MVT::i64), Dest);
3102 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3103 LHS.getOpcode() != ISD::AND) {
3104 // Don't combine AND since emitComparison converts the AND to an ANDS
3105 // (a.k.a. TST) and the test in the test bit and branch instruction
3106 // becomes redundant. This would also increase register pressure.
3107 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3108 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3109 DAG.getConstant(Mask, MVT::i64), Dest);
3113 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3114 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3118 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3120 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3121 // clean. Some of them require two branches to implement.
3122 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3123 AArch64CC::CondCode CC1, CC2;
3124 changeFPCCToAArch64CC(CC, CC1, CC2);
3125 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3127 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3128 if (CC2 != AArch64CC::AL) {
3129 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3130 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3137 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3138 SelectionDAG &DAG) const {
3139 EVT VT = Op.getValueType();
3142 SDValue In1 = Op.getOperand(0);
3143 SDValue In2 = Op.getOperand(1);
3144 EVT SrcVT = In2.getValueType();
3146 if (SrcVT == MVT::f32 && VT == MVT::f64)
3147 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3148 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3149 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3151 // FIXME: Src type is different, bail out for now. Can VT really be a
3158 SDValue EltMask, VecVal1, VecVal2;
3159 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3162 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3164 if (!VT.isVector()) {
3165 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3166 DAG.getUNDEF(VecVT), In1);
3167 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3168 DAG.getUNDEF(VecVT), In2);
3170 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3171 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3173 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3177 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3178 // immediate moves cannot materialize that in a single instruction for
3179 // 64-bit elements. Instead, materialize zero and then negate it.
3180 EltMask = DAG.getConstant(0, EltVT);
3182 if (!VT.isVector()) {
3183 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3184 DAG.getUNDEF(VecVT), In1);
3185 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3186 DAG.getUNDEF(VecVT), In2);
3188 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3189 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3192 llvm_unreachable("Invalid type for copysign!");
3195 std::vector<SDValue> BuildVectorOps;
3196 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3197 BuildVectorOps.push_back(EltMask);
3199 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3201 // If we couldn't materialize the mask above, then the mask vector will be
3202 // the zero vector, and we need to negate it here.
3203 if (VT == MVT::f64 || VT == MVT::v2f64) {
3204 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3205 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3206 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3210 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3213 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3214 else if (VT == MVT::f64)
3215 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3217 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3220 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3221 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3222 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3225 // While there is no integer popcount instruction, it can
3226 // be more efficiently lowered to the following sequence that uses
3227 // AdvSIMD registers/instructions as long as the copies to/from
3228 // the AdvSIMD registers are cheap.
3229 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3230 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3231 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3232 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3233 SDValue Val = Op.getOperand(0);
3235 EVT VT = Op.getValueType();
3236 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3239 if (VT == MVT::i32) {
3240 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3241 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3244 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3247 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3248 SDValue UaddLV = DAG.getNode(
3249 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3250 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3253 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3257 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3259 if (Op.getValueType().isVector())
3260 return LowerVSETCC(Op, DAG);
3262 SDValue LHS = Op.getOperand(0);
3263 SDValue RHS = Op.getOperand(1);
3264 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3267 // We chose ZeroOrOneBooleanContents, so use zero and one.
3268 EVT VT = Op.getValueType();
3269 SDValue TVal = DAG.getConstant(1, VT);
3270 SDValue FVal = DAG.getConstant(0, VT);
3272 // Handle f128 first, since one possible outcome is a normal integer
3273 // comparison which gets picked up by the next if statement.
3274 if (LHS.getValueType() == MVT::f128) {
3275 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3277 // If softenSetCCOperands returned a scalar, use it.
3278 if (!RHS.getNode()) {
3279 assert(LHS.getValueType() == Op.getValueType() &&
3280 "Unexpected setcc expansion!");
3285 if (LHS.getValueType().isInteger()) {
3288 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3290 // Note that we inverted the condition above, so we reverse the order of
3291 // the true and false operands here. This will allow the setcc to be
3292 // matched to a single CSINC instruction.
3293 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3296 // Now we know we're dealing with FP values.
3297 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3299 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3300 // and do the comparison.
3301 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3303 AArch64CC::CondCode CC1, CC2;
3304 changeFPCCToAArch64CC(CC, CC1, CC2);
3305 if (CC2 == AArch64CC::AL) {
3306 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3307 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3309 // Note that we inverted the condition above, so we reverse the order of
3310 // the true and false operands here. This will allow the setcc to be
3311 // matched to a single CSINC instruction.
3312 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3314 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3315 // totally clean. Some of them require two CSELs to implement. As is in
3316 // this case, we emit the first CSEL and then emit a second using the output
3317 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3319 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3320 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3322 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3324 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3325 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3329 /// A SELECT_CC operation is really some kind of max or min if both values being
3330 /// compared are, in some sense, equal to the results in either case. However,
3331 /// it is permissible to compare f32 values and produce directly extended f64
3334 /// Extending the comparison operands would also be allowed, but is less likely
3335 /// to happen in practice since their use is right here. Note that truncate
3336 /// operations would *not* be semantically equivalent.
3337 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3341 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3342 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3343 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3344 Result.getValueType() == MVT::f64) {
3346 APFloat CmpVal = CCmp->getValueAPF();
3347 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3348 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3351 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3354 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3355 SelectionDAG &DAG) const {
3356 SDValue CC = Op->getOperand(0);
3357 SDValue TVal = Op->getOperand(1);
3358 SDValue FVal = Op->getOperand(2);
3361 unsigned Opc = CC.getOpcode();
3362 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3364 if (CC.getResNo() == 1 &&
3365 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3366 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3367 // Only lower legal XALUO ops.
3368 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3371 AArch64CC::CondCode OFCC;
3372 SDValue Value, Overflow;
3373 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3374 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3376 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3380 if (CC.getOpcode() == ISD::SETCC)
3381 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3382 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3384 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3388 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3389 SelectionDAG &DAG) const {
3390 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3391 SDValue LHS = Op.getOperand(0);
3392 SDValue RHS = Op.getOperand(1);
3393 SDValue TVal = Op.getOperand(2);
3394 SDValue FVal = Op.getOperand(3);
3397 // Handle f128 first, because it will result in a comparison of some RTLIB
3398 // call result against zero.
3399 if (LHS.getValueType() == MVT::f128) {
3400 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3402 // If softenSetCCOperands returned a scalar, we need to compare the result
3403 // against zero to select between true and false values.
3404 if (!RHS.getNode()) {
3405 RHS = DAG.getConstant(0, LHS.getValueType());
3410 // Handle integers first.
3411 if (LHS.getValueType().isInteger()) {
3412 assert((LHS.getValueType() == RHS.getValueType()) &&
3413 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3415 unsigned Opcode = AArch64ISD::CSEL;
3417 // If both the TVal and the FVal are constants, see if we can swap them in
3418 // order to for a CSINV or CSINC out of them.
3419 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3420 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3422 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3423 std::swap(TVal, FVal);
3424 std::swap(CTVal, CFVal);
3425 CC = ISD::getSetCCInverse(CC, true);
3426 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3427 std::swap(TVal, FVal);
3428 std::swap(CTVal, CFVal);
3429 CC = ISD::getSetCCInverse(CC, true);
3430 } else if (TVal.getOpcode() == ISD::XOR) {
3431 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3432 // with a CSINV rather than a CSEL.
3433 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3435 if (CVal && CVal->isAllOnesValue()) {
3436 std::swap(TVal, FVal);
3437 std::swap(CTVal, CFVal);
3438 CC = ISD::getSetCCInverse(CC, true);
3440 } else if (TVal.getOpcode() == ISD::SUB) {
3441 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3442 // that we can match with a CSNEG rather than a CSEL.
3443 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3445 if (CVal && CVal->isNullValue()) {
3446 std::swap(TVal, FVal);
3447 std::swap(CTVal, CFVal);
3448 CC = ISD::getSetCCInverse(CC, true);
3450 } else if (CTVal && CFVal) {
3451 const int64_t TrueVal = CTVal->getSExtValue();
3452 const int64_t FalseVal = CFVal->getSExtValue();
3455 // If both TVal and FVal are constants, see if FVal is the
3456 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3457 // instead of a CSEL in that case.
3458 if (TrueVal == ~FalseVal) {
3459 Opcode = AArch64ISD::CSINV;
3460 } else if (TrueVal == -FalseVal) {
3461 Opcode = AArch64ISD::CSNEG;
3462 } else if (TVal.getValueType() == MVT::i32) {
3463 // If our operands are only 32-bit wide, make sure we use 32-bit
3464 // arithmetic for the check whether we can use CSINC. This ensures that
3465 // the addition in the check will wrap around properly in case there is
3466 // an overflow (which would not be the case if we do the check with
3467 // 64-bit arithmetic).
3468 const uint32_t TrueVal32 = CTVal->getZExtValue();
3469 const uint32_t FalseVal32 = CFVal->getZExtValue();
3471 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3472 Opcode = AArch64ISD::CSINC;
3474 if (TrueVal32 > FalseVal32) {
3478 // 64-bit check whether we can use CSINC.
3479 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3480 Opcode = AArch64ISD::CSINC;
3482 if (TrueVal > FalseVal) {
3487 // Swap TVal and FVal if necessary.
3489 std::swap(TVal, FVal);
3490 std::swap(CTVal, CFVal);
3491 CC = ISD::getSetCCInverse(CC, true);
3494 if (Opcode != AArch64ISD::CSEL) {
3495 // Drop FVal since we can get its value by simply inverting/negating
3502 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3504 EVT VT = Op.getValueType();
3505 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3508 // Now we know we're dealing with FP values.
3509 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3510 assert(LHS.getValueType() == RHS.getValueType());
3511 EVT VT = Op.getValueType();
3513 // Try to match this select into a max/min operation, which have dedicated
3514 // opcode in the instruction set.
3515 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3517 if (getTargetMachine().Options.NoNaNsFPMath) {
3518 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3519 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3520 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3521 CC = ISD::getSetCCSwappedOperands(CC);
3522 std::swap(MinMaxLHS, MinMaxRHS);
3525 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3526 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3536 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3544 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3550 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3551 // and do the comparison.
3552 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3554 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3555 // clean. Some of them require two CSELs to implement.
3556 AArch64CC::CondCode CC1, CC2;
3557 changeFPCCToAArch64CC(CC, CC1, CC2);
3558 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3559 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3561 // If we need a second CSEL, emit it, using the output of the first as the
3562 // RHS. We're effectively OR'ing the two CC's together.
3563 if (CC2 != AArch64CC::AL) {
3564 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3565 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3568 // Otherwise, return the output of the first CSEL.
3572 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3573 SelectionDAG &DAG) const {
3574 // Jump table entries as PC relative offsets. No additional tweaking
3575 // is necessary here. Just get the address of the jump table.
3576 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3577 EVT PtrVT = getPointerTy();
3580 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3581 !Subtarget->isTargetMachO()) {
3582 const unsigned char MO_NC = AArch64II::MO_NC;
3584 AArch64ISD::WrapperLarge, DL, PtrVT,
3585 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3586 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3587 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3588 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3589 AArch64II::MO_G0 | MO_NC));
3593 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3594 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3595 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3596 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3597 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3600 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3601 SelectionDAG &DAG) const {
3602 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3603 EVT PtrVT = getPointerTy();
3606 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3607 // Use the GOT for the large code model on iOS.
3608 if (Subtarget->isTargetMachO()) {
3609 SDValue GotAddr = DAG.getTargetConstantPool(
3610 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3612 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3615 const unsigned char MO_NC = AArch64II::MO_NC;
3617 AArch64ISD::WrapperLarge, DL, PtrVT,
3618 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3619 CP->getOffset(), AArch64II::MO_G3),
3620 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3621 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3622 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3623 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3624 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3625 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3627 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3628 // ELF, the only valid one on Darwin.
3630 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3631 CP->getOffset(), AArch64II::MO_PAGE);
3632 SDValue Lo = DAG.getTargetConstantPool(
3633 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3634 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3636 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3637 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3641 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3642 SelectionDAG &DAG) const {
3643 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3644 EVT PtrVT = getPointerTy();
3646 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3647 !Subtarget->isTargetMachO()) {
3648 const unsigned char MO_NC = AArch64II::MO_NC;
3650 AArch64ISD::WrapperLarge, DL, PtrVT,
3651 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3652 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3653 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3654 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3656 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3657 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3659 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3660 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3664 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3665 SelectionDAG &DAG) const {
3666 AArch64FunctionInfo *FuncInfo =
3667 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3671 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3672 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3673 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3674 MachinePointerInfo(SV), false, false, 0);
3677 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3678 SelectionDAG &DAG) const {
3679 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3680 // Standard, section B.3.
3681 MachineFunction &MF = DAG.getMachineFunction();
3682 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3685 SDValue Chain = Op.getOperand(0);
3686 SDValue VAList = Op.getOperand(1);
3687 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3688 SmallVector<SDValue, 4> MemOps;
3690 // void *__stack at offset 0
3692 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3693 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3694 MachinePointerInfo(SV), false, false, 8));
3696 // void *__gr_top at offset 8
3697 int GPRSize = FuncInfo->getVarArgsGPRSize();
3699 SDValue GRTop, GRTopAddr;
3701 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3702 DAG.getConstant(8, getPointerTy()));
3704 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3705 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3706 DAG.getConstant(GPRSize, getPointerTy()));
3708 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3709 MachinePointerInfo(SV, 8), false, false, 8));
3712 // void *__vr_top at offset 16
3713 int FPRSize = FuncInfo->getVarArgsFPRSize();
3715 SDValue VRTop, VRTopAddr;
3716 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3717 DAG.getConstant(16, getPointerTy()));
3719 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3720 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3721 DAG.getConstant(FPRSize, getPointerTy()));
3723 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3724 MachinePointerInfo(SV, 16), false, false, 8));
3727 // int __gr_offs at offset 24
3728 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3729 DAG.getConstant(24, getPointerTy()));
3730 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3731 GROffsAddr, MachinePointerInfo(SV, 24), false,
3734 // int __vr_offs at offset 28
3735 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3736 DAG.getConstant(28, getPointerTy()));
3737 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3738 VROffsAddr, MachinePointerInfo(SV, 28), false,
3741 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3744 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3745 SelectionDAG &DAG) const {
3746 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3747 : LowerAAPCS_VASTART(Op, DAG);
3750 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3751 SelectionDAG &DAG) const {
3752 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3754 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3755 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3756 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3758 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3759 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3760 8, false, false, MachinePointerInfo(DestSV),
3761 MachinePointerInfo(SrcSV));
3764 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3765 assert(Subtarget->isTargetDarwin() &&
3766 "automatic va_arg instruction only works on Darwin");
3768 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3769 EVT VT = Op.getValueType();
3771 SDValue Chain = Op.getOperand(0);
3772 SDValue Addr = Op.getOperand(1);
3773 unsigned Align = Op.getConstantOperandVal(3);
3775 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3776 MachinePointerInfo(V), false, false, false, 0);
3777 Chain = VAList.getValue(1);
3780 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3781 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3782 DAG.getConstant(Align - 1, getPointerTy()));
3783 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3784 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3787 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3788 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3790 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3791 // up to 64 bits. At the very least, we have to increase the striding of the
3792 // vaargs list to match this, and for FP values we need to introduce
3793 // FP_ROUND nodes as well.
3794 if (VT.isInteger() && !VT.isVector())
3796 bool NeedFPTrunc = false;
3797 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3802 // Increment the pointer, VAList, to the next vaarg
3803 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3804 DAG.getConstant(ArgSize, getPointerTy()));
3805 // Store the incremented VAList to the legalized pointer
3806 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3809 // Load the actual argument out of the pointer VAList
3811 // Load the value as an f64.
3812 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3813 MachinePointerInfo(), false, false, false, 0);
3814 // Round the value down to an f32.
3815 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3816 DAG.getIntPtrConstant(1));
3817 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3818 // Merge the rounded value with the chain output of the load.
3819 return DAG.getMergeValues(Ops, DL);
3822 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3826 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3827 SelectionDAG &DAG) const {
3828 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3829 MFI->setFrameAddressIsTaken(true);
3831 EVT VT = Op.getValueType();
3833 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3835 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3837 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3838 MachinePointerInfo(), false, false, false, 0);
3842 // FIXME? Maybe this could be a TableGen attribute on some registers and
3843 // this table could be generated automatically from RegInfo.
3844 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3846 unsigned Reg = StringSwitch<unsigned>(RegName)
3847 .Case("sp", AArch64::SP)
3851 report_fatal_error("Invalid register name global variable");
3854 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3855 SelectionDAG &DAG) const {
3856 MachineFunction &MF = DAG.getMachineFunction();
3857 MachineFrameInfo *MFI = MF.getFrameInfo();
3858 MFI->setReturnAddressIsTaken(true);
3860 EVT VT = Op.getValueType();
3862 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3864 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3865 SDValue Offset = DAG.getConstant(8, getPointerTy());
3866 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3867 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3868 MachinePointerInfo(), false, false, false, 0);
3871 // Return LR, which contains the return address. Mark it an implicit live-in.
3872 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3873 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3876 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3877 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3878 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3879 SelectionDAG &DAG) const {
3880 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3881 EVT VT = Op.getValueType();
3882 unsigned VTBits = VT.getSizeInBits();
3884 SDValue ShOpLo = Op.getOperand(0);
3885 SDValue ShOpHi = Op.getOperand(1);
3886 SDValue ShAmt = Op.getOperand(2);
3888 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3890 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3892 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3893 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3894 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3895 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3896 DAG.getConstant(VTBits, MVT::i64));
3897 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3899 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3900 ISD::SETGE, dl, DAG);
3901 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3903 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3904 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3906 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3908 // AArch64 shifts larger than the register width are wrapped rather than
3909 // clamped, so we can't just emit "hi >> x".
3910 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3911 SDValue TrueValHi = Opc == ISD::SRA
3912 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3913 DAG.getConstant(VTBits - 1, MVT::i64))
3914 : DAG.getConstant(0, VT);
3916 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3918 SDValue Ops[2] = { Lo, Hi };
3919 return DAG.getMergeValues(Ops, dl);
3922 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3923 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3924 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3925 SelectionDAG &DAG) const {
3926 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3927 EVT VT = Op.getValueType();
3928 unsigned VTBits = VT.getSizeInBits();
3930 SDValue ShOpLo = Op.getOperand(0);
3931 SDValue ShOpHi = Op.getOperand(1);
3932 SDValue ShAmt = Op.getOperand(2);
3935 assert(Op.getOpcode() == ISD::SHL_PARTS);
3936 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3937 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3938 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3939 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3940 DAG.getConstant(VTBits, MVT::i64));
3941 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3942 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3944 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3946 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3947 ISD::SETGE, dl, DAG);
3948 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3950 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3952 // AArch64 shifts of larger than register sizes are wrapped rather than
3953 // clamped, so we can't just emit "lo << a" if a is too big.
3954 SDValue TrueValLo = DAG.getConstant(0, VT);
3955 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3957 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3959 SDValue Ops[2] = { Lo, Hi };
3960 return DAG.getMergeValues(Ops, dl);
3963 bool AArch64TargetLowering::isOffsetFoldingLegal(
3964 const GlobalAddressSDNode *GA) const {
3965 // The AArch64 target doesn't support folding offsets into global addresses.
3969 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3970 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3971 // FIXME: We should be able to handle f128 as well with a clever lowering.
3972 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3976 return AArch64_AM::getFP64Imm(Imm) != -1;
3977 else if (VT == MVT::f32)
3978 return AArch64_AM::getFP32Imm(Imm) != -1;
3982 //===----------------------------------------------------------------------===//
3983 // AArch64 Optimization Hooks
3984 //===----------------------------------------------------------------------===//
3986 //===----------------------------------------------------------------------===//
3987 // AArch64 Inline Assembly Support
3988 //===----------------------------------------------------------------------===//
3990 // Table of Constraints
3991 // TODO: This is the current set of constraints supported by ARM for the
3992 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3994 // r - A general register
3995 // w - An FP/SIMD register of some size in the range v0-v31
3996 // x - An FP/SIMD register of some size in the range v0-v15
3997 // I - Constant that can be used with an ADD instruction
3998 // J - Constant that can be used with a SUB instruction
3999 // K - Constant that can be used with a 32-bit logical instruction
4000 // L - Constant that can be used with a 64-bit logical instruction
4001 // M - Constant that can be used as a 32-bit MOV immediate
4002 // N - Constant that can be used as a 64-bit MOV immediate
4003 // Q - A memory reference with base register and no offset
4004 // S - A symbolic address
4005 // Y - Floating point constant zero
4006 // Z - Integer constant zero
4008 // Note that general register operands will be output using their 64-bit x
4009 // register name, whatever the size of the variable, unless the asm operand
4010 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4011 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4014 /// getConstraintType - Given a constraint letter, return the type of
4015 /// constraint it is for this target.
4016 AArch64TargetLowering::ConstraintType
4017 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4018 if (Constraint.size() == 1) {
4019 switch (Constraint[0]) {
4026 return C_RegisterClass;
4027 // An address with a single base register. Due to the way we
4028 // currently handle addresses it is the same as 'r'.
4033 return TargetLowering::getConstraintType(Constraint);
4036 /// Examine constraint type and operand type and determine a weight value.
4037 /// This object must already have been set up with the operand type
4038 /// and the current alternative constraint selected.
4039 TargetLowering::ConstraintWeight
4040 AArch64TargetLowering::getSingleConstraintMatchWeight(
4041 AsmOperandInfo &info, const char *constraint) const {
4042 ConstraintWeight weight = CW_Invalid;
4043 Value *CallOperandVal = info.CallOperandVal;
4044 // If we don't have a value, we can't do a match,
4045 // but allow it at the lowest weight.
4046 if (!CallOperandVal)
4048 Type *type = CallOperandVal->getType();
4049 // Look at the constraint type.
4050 switch (*constraint) {
4052 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4056 if (type->isFloatingPointTy() || type->isVectorTy())
4057 weight = CW_Register;
4060 weight = CW_Constant;
4066 std::pair<unsigned, const TargetRegisterClass *>
4067 AArch64TargetLowering::getRegForInlineAsmConstraint(
4068 const std::string &Constraint, MVT VT) const {
4069 if (Constraint.size() == 1) {
4070 switch (Constraint[0]) {
4072 if (VT.getSizeInBits() == 64)
4073 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4074 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4077 return std::make_pair(0U, &AArch64::FPR32RegClass);
4078 if (VT.getSizeInBits() == 64)
4079 return std::make_pair(0U, &AArch64::FPR64RegClass);
4080 if (VT.getSizeInBits() == 128)
4081 return std::make_pair(0U, &AArch64::FPR128RegClass);
4083 // The instructions that this constraint is designed for can
4084 // only take 128-bit registers so just use that regclass.
4086 if (VT.getSizeInBits() == 128)
4087 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4091 if (StringRef("{cc}").equals_lower(Constraint))
4092 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4094 // Use the default implementation in TargetLowering to convert the register
4095 // constraint into a member of a register class.
4096 std::pair<unsigned, const TargetRegisterClass *> Res;
4097 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4099 // Not found as a standard register?
4101 unsigned Size = Constraint.size();
4102 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4103 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4104 const std::string Reg =
4105 std::string(&Constraint[2], &Constraint[Size - 1]);
4106 int RegNo = atoi(Reg.c_str());
4107 if (RegNo >= 0 && RegNo <= 31) {
4108 // v0 - v31 are aliases of q0 - q31.
4109 // By default we'll emit v0-v31 for this unless there's a modifier where
4110 // we'll emit the correct register as well.
4111 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4112 Res.second = &AArch64::FPR128RegClass;
4120 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4121 /// vector. If it is invalid, don't add anything to Ops.
4122 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4123 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4124 SelectionDAG &DAG) const {
4127 // Currently only support length 1 constraints.
4128 if (Constraint.length() != 1)
4131 char ConstraintLetter = Constraint[0];
4132 switch (ConstraintLetter) {
4136 // This set of constraints deal with valid constants for various instructions.
4137 // Validate and return a target constant for them if we can.
4139 // 'z' maps to xzr or wzr so it needs an input of 0.
4140 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4141 if (!C || C->getZExtValue() != 0)
4144 if (Op.getValueType() == MVT::i64)
4145 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4147 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4157 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4161 // Grab the value and do some validation.
4162 uint64_t CVal = C->getZExtValue();
4163 switch (ConstraintLetter) {
4164 // The I constraint applies only to simple ADD or SUB immediate operands:
4165 // i.e. 0 to 4095 with optional shift by 12
4166 // The J constraint applies only to ADD or SUB immediates that would be
4167 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4168 // instruction [or vice versa], in other words -1 to -4095 with optional
4169 // left shift by 12.
4171 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4175 uint64_t NVal = -C->getSExtValue();
4176 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4177 CVal = C->getSExtValue();
4182 // The K and L constraints apply *only* to logical immediates, including
4183 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4184 // been removed and MOV should be used). So these constraints have to
4185 // distinguish between bit patterns that are valid 32-bit or 64-bit
4186 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4187 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4190 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4194 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4197 // The M and N constraints are a superset of K and L respectively, for use
4198 // with the MOV (immediate) alias. As well as the logical immediates they
4199 // also match 32 or 64-bit immediates that can be loaded either using a
4200 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4201 // (M) or 64-bit 0x1234000000000000 (N) etc.
4202 // As a note some of this code is liberally stolen from the asm parser.
4204 if (!isUInt<32>(CVal))
4206 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4208 if ((CVal & 0xFFFF) == CVal)
4210 if ((CVal & 0xFFFF0000ULL) == CVal)
4212 uint64_t NCVal = ~(uint32_t)CVal;
4213 if ((NCVal & 0xFFFFULL) == NCVal)
4215 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4220 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4222 if ((CVal & 0xFFFFULL) == CVal)
4224 if ((CVal & 0xFFFF0000ULL) == CVal)
4226 if ((CVal & 0xFFFF00000000ULL) == CVal)
4228 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4230 uint64_t NCVal = ~CVal;
4231 if ((NCVal & 0xFFFFULL) == NCVal)
4233 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4235 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4237 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4245 // All assembler immediates are 64-bit integers.
4246 Result = DAG.getTargetConstant(CVal, MVT::i64);
4250 if (Result.getNode()) {
4251 Ops.push_back(Result);
4255 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4258 //===----------------------------------------------------------------------===//
4259 // AArch64 Advanced SIMD Support
4260 //===----------------------------------------------------------------------===//
4262 /// WidenVector - Given a value in the V64 register class, produce the
4263 /// equivalent value in the V128 register class.
4264 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4265 EVT VT = V64Reg.getValueType();
4266 unsigned NarrowSize = VT.getVectorNumElements();
4267 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4268 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4271 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4272 V64Reg, DAG.getConstant(0, MVT::i32));
4275 /// getExtFactor - Determine the adjustment factor for the position when
4276 /// generating an "extract from vector registers" instruction.
4277 static unsigned getExtFactor(SDValue &V) {
4278 EVT EltType = V.getValueType().getVectorElementType();
4279 return EltType.getSizeInBits() / 8;
4282 /// NarrowVector - Given a value in the V128 register class, produce the
4283 /// equivalent value in the V64 register class.
4284 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4285 EVT VT = V128Reg.getValueType();
4286 unsigned WideSize = VT.getVectorNumElements();
4287 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4288 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4291 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4294 // Gather data to see if the operation can be modelled as a
4295 // shuffle in combination with VEXTs.
4296 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4297 SelectionDAG &DAG) const {
4298 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4300 EVT VT = Op.getValueType();
4301 unsigned NumElts = VT.getVectorNumElements();
4303 struct ShuffleSourceInfo {
4308 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4309 // be compatible with the shuffle we intend to construct. As a result
4310 // ShuffleVec will be some sliding window into the original Vec.
4313 // Code should guarantee that element i in Vec starts at element "WindowBase
4314 // + i * WindowScale in ShuffleVec".
4318 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4319 ShuffleSourceInfo(SDValue Vec)
4320 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4324 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4326 SmallVector<ShuffleSourceInfo, 2> Sources;
4327 for (unsigned i = 0; i < NumElts; ++i) {
4328 SDValue V = Op.getOperand(i);
4329 if (V.getOpcode() == ISD::UNDEF)
4331 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4332 // A shuffle can only come from building a vector from various
4333 // elements of other vectors.
4337 // Add this element source to the list if it's not already there.
4338 SDValue SourceVec = V.getOperand(0);
4339 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4340 if (Source == Sources.end())
4341 Sources.push_back(ShuffleSourceInfo(SourceVec));
4343 // Update the minimum and maximum lane number seen.
4344 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4345 Source->MinElt = std::min(Source->MinElt, EltNo);
4346 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4349 // Currently only do something sane when at most two source vectors
4351 if (Sources.size() > 2)
4354 // Find out the smallest element size among result and two sources, and use
4355 // it as element size to build the shuffle_vector.
4356 EVT SmallestEltTy = VT.getVectorElementType();
4357 for (auto &Source : Sources) {
4358 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4359 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4360 SmallestEltTy = SrcEltTy;
4363 unsigned ResMultiplier =
4364 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4365 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4366 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4368 // If the source vector is too wide or too narrow, we may nevertheless be able
4369 // to construct a compatible shuffle either by concatenating it with UNDEF or
4370 // extracting a suitable range of elements.
4371 for (auto &Src : Sources) {
4372 EVT SrcVT = Src.ShuffleVec.getValueType();
4374 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4377 // This stage of the search produces a source with the same element type as
4378 // the original, but with a total width matching the BUILD_VECTOR output.
4379 EVT EltVT = SrcVT.getVectorElementType();
4380 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4381 VT.getSizeInBits() / EltVT.getSizeInBits());
4383 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4384 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4385 // We can pad out the smaller vector for free, so if it's part of a
4388 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4389 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4393 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4395 if (Src.MaxElt - Src.MinElt >= NumElts) {
4396 // Span too large for a VEXT to cope
4400 if (Src.MinElt >= NumElts) {
4401 // The extraction can just take the second half
4403 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4404 DAG.getIntPtrConstant(NumElts));
4405 Src.WindowBase = -NumElts;
4406 } else if (Src.MaxElt < NumElts) {
4407 // The extraction can just take the first half
4408 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4409 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4411 // An actual VEXT is needed
4412 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4413 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4415 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4416 DAG.getIntPtrConstant(NumElts));
4417 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4419 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4420 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4421 Src.WindowBase = -Src.MinElt;
4425 // Another possible incompatibility occurs from the vector element types. We
4426 // can fix this by bitcasting the source vectors to the same type we intend
4428 for (auto &Src : Sources) {
4429 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4430 if (SrcEltTy == SmallestEltTy)
4432 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4433 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4434 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4435 Src.WindowBase *= Src.WindowScale;
4438 // Final sanity check before we try to actually produce a shuffle.
4440 for (auto Src : Sources)
4441 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4444 // The stars all align, our next step is to produce the mask for the shuffle.
4445 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4446 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4447 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4448 SDValue Entry = Op.getOperand(i);
4449 if (Entry.getOpcode() == ISD::UNDEF)
4452 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4453 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4455 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4456 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4458 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4459 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4460 VT.getVectorElementType().getSizeInBits());
4461 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4463 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4464 // starting at the appropriate offset.
4465 int *LaneMask = &Mask[i * ResMultiplier];
4467 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4468 ExtractBase += NumElts * (Src - Sources.begin());
4469 for (int j = 0; j < LanesDefined; ++j)
4470 LaneMask[j] = ExtractBase + j;
4473 // Final check before we try to produce nonsense...
4474 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4477 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4478 for (unsigned i = 0; i < Sources.size(); ++i)
4479 ShuffleOps[i] = Sources[i].ShuffleVec;
4481 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4482 ShuffleOps[1], &Mask[0]);
4483 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4486 // check if an EXT instruction can handle the shuffle mask when the
4487 // vector sources of the shuffle are the same.
4488 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4489 unsigned NumElts = VT.getVectorNumElements();
4491 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4497 // If this is a VEXT shuffle, the immediate value is the index of the first
4498 // element. The other shuffle indices must be the successive elements after
4500 unsigned ExpectedElt = Imm;
4501 for (unsigned i = 1; i < NumElts; ++i) {
4502 // Increment the expected index. If it wraps around, just follow it
4503 // back to index zero and keep going.
4505 if (ExpectedElt == NumElts)
4509 continue; // ignore UNDEF indices
4510 if (ExpectedElt != static_cast<unsigned>(M[i]))
4517 // check if an EXT instruction can handle the shuffle mask when the
4518 // vector sources of the shuffle are different.
4519 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4521 // Look for the first non-undef element.
4522 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4523 [](int Elt) {return Elt >= 0;});
4525 // Benefit form APInt to handle overflow when calculating expected element.
4526 unsigned NumElts = VT.getVectorNumElements();
4527 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4528 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4529 // The following shuffle indices must be the successive elements after the
4530 // first real element.
4531 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4532 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4533 if (FirstWrongElt != M.end())
4536 // The index of an EXT is the first element if it is not UNDEF.
4537 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4538 // value of the first element. E.g.
4539 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4540 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4541 // ExpectedElt is the last mask index plus 1.
4542 Imm = ExpectedElt.getZExtValue();
4544 // There are two difference cases requiring to reverse input vectors.
4545 // For example, for vector <4 x i32> we have the following cases,
4546 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4547 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4548 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4549 // to reverse two input vectors.
4558 /// isREVMask - Check if a vector shuffle corresponds to a REV
4559 /// instruction with the specified blocksize. (The order of the elements
4560 /// within each block of the vector is reversed.)
4561 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4562 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4563 "Only possible block sizes for REV are: 16, 32, 64");
4565 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4569 unsigned NumElts = VT.getVectorNumElements();
4570 unsigned BlockElts = M[0] + 1;
4571 // If the first shuffle index is UNDEF, be optimistic.
4573 BlockElts = BlockSize / EltSz;
4575 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4578 for (unsigned i = 0; i < NumElts; ++i) {
4580 continue; // ignore UNDEF indices
4581 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4588 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4589 unsigned NumElts = VT.getVectorNumElements();
4590 WhichResult = (M[0] == 0 ? 0 : 1);
4591 unsigned Idx = WhichResult * NumElts / 2;
4592 for (unsigned i = 0; i != NumElts; i += 2) {
4593 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4594 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4602 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4603 unsigned NumElts = VT.getVectorNumElements();
4604 WhichResult = (M[0] == 0 ? 0 : 1);
4605 for (unsigned i = 0; i != NumElts; ++i) {
4607 continue; // ignore UNDEF indices
4608 if ((unsigned)M[i] != 2 * i + WhichResult)
4615 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4616 unsigned NumElts = VT.getVectorNumElements();
4617 WhichResult = (M[0] == 0 ? 0 : 1);
4618 for (unsigned i = 0; i < NumElts; i += 2) {
4619 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4620 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4626 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4627 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4628 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4629 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4630 unsigned NumElts = VT.getVectorNumElements();
4631 WhichResult = (M[0] == 0 ? 0 : 1);
4632 unsigned Idx = WhichResult * NumElts / 2;
4633 for (unsigned i = 0; i != NumElts; i += 2) {
4634 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4635 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4643 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4644 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4645 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4646 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4647 unsigned Half = VT.getVectorNumElements() / 2;
4648 WhichResult = (M[0] == 0 ? 0 : 1);
4649 for (unsigned j = 0; j != 2; ++j) {
4650 unsigned Idx = WhichResult;
4651 for (unsigned i = 0; i != Half; ++i) {
4652 int MIdx = M[i + j * Half];
4653 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4662 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4663 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4664 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4665 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4666 unsigned NumElts = VT.getVectorNumElements();
4667 WhichResult = (M[0] == 0 ? 0 : 1);
4668 for (unsigned i = 0; i < NumElts; i += 2) {
4669 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4670 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4676 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4677 bool &DstIsLeft, int &Anomaly) {
4678 if (M.size() != static_cast<size_t>(NumInputElements))
4681 int NumLHSMatch = 0, NumRHSMatch = 0;
4682 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4684 for (int i = 0; i < NumInputElements; ++i) {
4694 LastLHSMismatch = i;
4696 if (M[i] == i + NumInputElements)
4699 LastRHSMismatch = i;
4702 if (NumLHSMatch == NumInputElements - 1) {
4704 Anomaly = LastLHSMismatch;
4706 } else if (NumRHSMatch == NumInputElements - 1) {
4708 Anomaly = LastRHSMismatch;
4715 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4716 if (VT.getSizeInBits() != 128)
4719 unsigned NumElts = VT.getVectorNumElements();
4721 for (int I = 0, E = NumElts / 2; I != E; I++) {
4726 int Offset = NumElts / 2;
4727 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4728 if (Mask[I] != I + SplitLHS * Offset)
4735 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4737 EVT VT = Op.getValueType();
4738 SDValue V0 = Op.getOperand(0);
4739 SDValue V1 = Op.getOperand(1);
4740 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4742 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4743 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4746 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4748 if (!isConcatMask(Mask, VT, SplitV0))
4751 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4752 VT.getVectorNumElements() / 2);
4754 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4755 DAG.getConstant(0, MVT::i64));
4757 if (V1.getValueType().getSizeInBits() == 128) {
4758 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4759 DAG.getConstant(0, MVT::i64));
4761 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4764 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4765 /// the specified operations to build the shuffle.
4766 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4767 SDValue RHS, SelectionDAG &DAG,
4769 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4770 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4771 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4774 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4783 OP_VUZPL, // VUZP, left result
4784 OP_VUZPR, // VUZP, right result
4785 OP_VZIPL, // VZIP, left result
4786 OP_VZIPR, // VZIP, right result
4787 OP_VTRNL, // VTRN, left result
4788 OP_VTRNR // VTRN, right result
4791 if (OpNum == OP_COPY) {
4792 if (LHSID == (1 * 9 + 2) * 9 + 3)
4794 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4798 SDValue OpLHS, OpRHS;
4799 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4800 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4801 EVT VT = OpLHS.getValueType();
4805 llvm_unreachable("Unknown shuffle opcode!");
4807 // VREV divides the vector in half and swaps within the half.
4808 if (VT.getVectorElementType() == MVT::i32 ||
4809 VT.getVectorElementType() == MVT::f32)
4810 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4811 // vrev <4 x i16> -> REV32
4812 if (VT.getVectorElementType() == MVT::i16 ||
4813 VT.getVectorElementType() == MVT::f16)
4814 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4815 // vrev <4 x i8> -> REV16
4816 assert(VT.getVectorElementType() == MVT::i8);
4817 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4822 EVT EltTy = VT.getVectorElementType();
4824 if (EltTy == MVT::i8)
4825 Opcode = AArch64ISD::DUPLANE8;
4826 else if (EltTy == MVT::i16)
4827 Opcode = AArch64ISD::DUPLANE16;
4828 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4829 Opcode = AArch64ISD::DUPLANE32;
4830 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4831 Opcode = AArch64ISD::DUPLANE64;
4833 llvm_unreachable("Invalid vector element type?");
4835 if (VT.getSizeInBits() == 64)
4836 OpLHS = WidenVector(OpLHS, DAG);
4837 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4838 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4843 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4844 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4845 DAG.getConstant(Imm, MVT::i32));
4848 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4851 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4854 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4857 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4860 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4863 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4868 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4869 SelectionDAG &DAG) {
4870 // Check to see if we can use the TBL instruction.
4871 SDValue V1 = Op.getOperand(0);
4872 SDValue V2 = Op.getOperand(1);
4875 EVT EltVT = Op.getValueType().getVectorElementType();
4876 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4878 SmallVector<SDValue, 8> TBLMask;
4879 for (int Val : ShuffleMask) {
4880 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4881 unsigned Offset = Byte + Val * BytesPerElt;
4882 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4886 MVT IndexVT = MVT::v8i8;
4887 unsigned IndexLen = 8;
4888 if (Op.getValueType().getSizeInBits() == 128) {
4889 IndexVT = MVT::v16i8;
4893 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4894 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4897 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4899 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4900 Shuffle = DAG.getNode(
4901 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4902 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4903 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4904 makeArrayRef(TBLMask.data(), IndexLen)));
4906 if (IndexLen == 8) {
4907 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4908 Shuffle = DAG.getNode(
4909 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4910 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4911 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4912 makeArrayRef(TBLMask.data(), IndexLen)));
4914 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4915 // cannot currently represent the register constraints on the input
4917 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4918 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4919 // &TBLMask[0], IndexLen));
4920 Shuffle = DAG.getNode(
4921 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4922 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4923 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4924 makeArrayRef(TBLMask.data(), IndexLen)));
4927 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4930 static unsigned getDUPLANEOp(EVT EltType) {
4931 if (EltType == MVT::i8)
4932 return AArch64ISD::DUPLANE8;
4933 if (EltType == MVT::i16 || EltType == MVT::f16)
4934 return AArch64ISD::DUPLANE16;
4935 if (EltType == MVT::i32 || EltType == MVT::f32)
4936 return AArch64ISD::DUPLANE32;
4937 if (EltType == MVT::i64 || EltType == MVT::f64)
4938 return AArch64ISD::DUPLANE64;
4940 llvm_unreachable("Invalid vector element type?");
4943 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4944 SelectionDAG &DAG) const {
4946 EVT VT = Op.getValueType();
4948 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4950 // Convert shuffles that are directly supported on NEON to target-specific
4951 // DAG nodes, instead of keeping them as shuffles and matching them again
4952 // during code selection. This is more efficient and avoids the possibility
4953 // of inconsistencies between legalization and selection.
4954 ArrayRef<int> ShuffleMask = SVN->getMask();
4956 SDValue V1 = Op.getOperand(0);
4957 SDValue V2 = Op.getOperand(1);
4959 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4960 V1.getValueType().getSimpleVT())) {
4961 int Lane = SVN->getSplatIndex();
4962 // If this is undef splat, generate it via "just" vdup, if possible.
4966 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4967 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4969 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4970 // constant. If so, we can just reference the lane's definition directly.
4971 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4972 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4973 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4975 // Otherwise, duplicate from the lane of the input vector.
4976 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4978 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4979 // to make a vector of the same size as this SHUFFLE. We can ignore the
4980 // extract entirely, and canonicalise the concat using WidenVector.
4981 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4982 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4983 V1 = V1.getOperand(0);
4984 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4985 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4986 Lane -= Idx * VT.getVectorNumElements() / 2;
4987 V1 = WidenVector(V1.getOperand(Idx), DAG);
4988 } else if (VT.getSizeInBits() == 64)
4989 V1 = WidenVector(V1, DAG);
4991 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4994 if (isREVMask(ShuffleMask, VT, 64))
4995 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4996 if (isREVMask(ShuffleMask, VT, 32))
4997 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4998 if (isREVMask(ShuffleMask, VT, 16))
4999 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5001 bool ReverseEXT = false;
5003 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5006 Imm *= getExtFactor(V1);
5007 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5008 DAG.getConstant(Imm, MVT::i32));
5009 } else if (V2->getOpcode() == ISD::UNDEF &&
5010 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5011 Imm *= getExtFactor(V1);
5012 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5013 DAG.getConstant(Imm, MVT::i32));
5016 unsigned WhichResult;
5017 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5018 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5019 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5021 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5022 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5023 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5025 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5026 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5027 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5030 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5031 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5032 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5034 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5035 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5036 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5038 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5039 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5040 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5043 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5044 if (Concat.getNode())
5049 int NumInputElements = V1.getValueType().getVectorNumElements();
5050 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5051 SDValue DstVec = DstIsLeft ? V1 : V2;
5052 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5054 SDValue SrcVec = V1;
5055 int SrcLane = ShuffleMask[Anomaly];
5056 if (SrcLane >= NumInputElements) {
5058 SrcLane -= VT.getVectorNumElements();
5060 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5062 EVT ScalarVT = VT.getVectorElementType();
5064 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5065 ScalarVT = MVT::i32;
5068 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5069 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5073 // If the shuffle is not directly supported and it has 4 elements, use
5074 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5075 unsigned NumElts = VT.getVectorNumElements();
5077 unsigned PFIndexes[4];
5078 for (unsigned i = 0; i != 4; ++i) {
5079 if (ShuffleMask[i] < 0)
5082 PFIndexes[i] = ShuffleMask[i];
5085 // Compute the index in the perfect shuffle table.
5086 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5087 PFIndexes[2] * 9 + PFIndexes[3];
5088 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5089 unsigned Cost = (PFEntry >> 30);
5092 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5095 return GenerateTBL(Op, ShuffleMask, DAG);
5098 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5100 EVT VT = BVN->getValueType(0);
5101 APInt SplatBits, SplatUndef;
5102 unsigned SplatBitSize;
5104 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5105 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5107 for (unsigned i = 0; i < NumSplats; ++i) {
5108 CnstBits <<= SplatBitSize;
5109 UndefBits <<= SplatBitSize;
5110 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5111 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5120 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5121 SelectionDAG &DAG) const {
5122 BuildVectorSDNode *BVN =
5123 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5124 SDValue LHS = Op.getOperand(0);
5126 EVT VT = Op.getValueType();
5131 APInt CnstBits(VT.getSizeInBits(), 0);
5132 APInt UndefBits(VT.getSizeInBits(), 0);
5133 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5134 // We only have BIC vector immediate instruction, which is and-not.
5135 CnstBits = ~CnstBits;
5137 // We make use of a little bit of goto ickiness in order to avoid having to
5138 // duplicate the immediate matching logic for the undef toggled case.
5139 bool SecondTry = false;
5142 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5143 CnstBits = CnstBits.zextOrTrunc(64);
5144 uint64_t CnstVal = CnstBits.getZExtValue();
5146 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5147 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5148 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5149 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5150 DAG.getConstant(CnstVal, MVT::i32),
5151 DAG.getConstant(0, MVT::i32));
5152 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5155 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5156 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5157 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5158 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5159 DAG.getConstant(CnstVal, MVT::i32),
5160 DAG.getConstant(8, MVT::i32));
5161 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5164 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5165 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5166 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5167 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5168 DAG.getConstant(CnstVal, MVT::i32),
5169 DAG.getConstant(16, MVT::i32));
5170 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5173 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5174 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5175 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5176 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5177 DAG.getConstant(CnstVal, MVT::i32),
5178 DAG.getConstant(24, MVT::i32));
5179 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5182 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5183 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5184 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5185 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5186 DAG.getConstant(CnstVal, MVT::i32),
5187 DAG.getConstant(0, MVT::i32));
5188 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5191 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5192 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5193 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5194 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5195 DAG.getConstant(CnstVal, MVT::i32),
5196 DAG.getConstant(8, MVT::i32));
5197 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5204 CnstBits = ~UndefBits;
5208 // We can always fall back to a non-immediate AND.
5213 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5214 // consists of only the same constant int value, returned in reference arg
5216 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5217 uint64_t &ConstVal) {
5218 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5221 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5224 EVT VT = Bvec->getValueType(0);
5225 unsigned NumElts = VT.getVectorNumElements();
5226 for (unsigned i = 1; i < NumElts; ++i)
5227 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5229 ConstVal = FirstElt->getZExtValue();
5233 static unsigned getIntrinsicID(const SDNode *N) {
5234 unsigned Opcode = N->getOpcode();
5237 return Intrinsic::not_intrinsic;
5238 case ISD::INTRINSIC_WO_CHAIN: {
5239 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5240 if (IID < Intrinsic::num_intrinsics)
5242 return Intrinsic::not_intrinsic;
5247 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5248 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5249 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5250 // Also, logical shift right -> sri, with the same structure.
5251 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5252 EVT VT = N->getValueType(0);
5259 // Is the first op an AND?
5260 const SDValue And = N->getOperand(0);
5261 if (And.getOpcode() != ISD::AND)
5264 // Is the second op an shl or lshr?
5265 SDValue Shift = N->getOperand(1);
5266 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5267 // or AArch64ISD::VLSHR vector, #shift
5268 unsigned ShiftOpc = Shift.getOpcode();
5269 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5271 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5273 // Is the shift amount constant?
5274 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5278 // Is the and mask vector all constant?
5280 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5283 // Is C1 == ~C2, taking into account how much one can shift elements of a
5285 uint64_t C2 = C2node->getZExtValue();
5286 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5287 if (C2 > ElemSizeInBits)
5289 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5290 if ((C1 & ElemMask) != (~C2 & ElemMask))
5293 SDValue X = And.getOperand(0);
5294 SDValue Y = Shift.getOperand(0);
5297 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5299 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5300 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5302 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5303 DEBUG(N->dump(&DAG));
5304 DEBUG(dbgs() << "into: \n");
5305 DEBUG(ResultSLI->dump(&DAG));
5311 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5312 SelectionDAG &DAG) const {
5313 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5314 if (EnableAArch64SlrGeneration) {
5315 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5320 BuildVectorSDNode *BVN =
5321 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5322 SDValue LHS = Op.getOperand(1);
5324 EVT VT = Op.getValueType();
5326 // OR commutes, so try swapping the operands.
5328 LHS = Op.getOperand(0);
5329 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5334 APInt CnstBits(VT.getSizeInBits(), 0);
5335 APInt UndefBits(VT.getSizeInBits(), 0);
5336 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5337 // We make use of a little bit of goto ickiness in order to avoid having to
5338 // duplicate the immediate matching logic for the undef toggled case.
5339 bool SecondTry = false;
5342 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5343 CnstBits = CnstBits.zextOrTrunc(64);
5344 uint64_t CnstVal = CnstBits.getZExtValue();
5346 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5347 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5348 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5349 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5350 DAG.getConstant(CnstVal, MVT::i32),
5351 DAG.getConstant(0, MVT::i32));
5352 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5355 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5356 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5357 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5358 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5359 DAG.getConstant(CnstVal, MVT::i32),
5360 DAG.getConstant(8, MVT::i32));
5361 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5364 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5365 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5366 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5367 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5368 DAG.getConstant(CnstVal, MVT::i32),
5369 DAG.getConstant(16, MVT::i32));
5370 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5373 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5374 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5375 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5376 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5377 DAG.getConstant(CnstVal, MVT::i32),
5378 DAG.getConstant(24, MVT::i32));
5379 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5382 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5383 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5384 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5385 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5386 DAG.getConstant(CnstVal, MVT::i32),
5387 DAG.getConstant(0, MVT::i32));
5388 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5391 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5392 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5393 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5394 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5395 DAG.getConstant(CnstVal, MVT::i32),
5396 DAG.getConstant(8, MVT::i32));
5397 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5404 CnstBits = UndefBits;
5408 // We can always fall back to a non-immediate OR.
5413 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5414 // be truncated to fit element width.
5415 static SDValue NormalizeBuildVector(SDValue Op,
5416 SelectionDAG &DAG) {
5417 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5419 EVT VT = Op.getValueType();
5420 EVT EltTy= VT.getVectorElementType();
5422 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5425 SmallVector<SDValue, 16> Ops;
5426 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5427 SDValue Lane = Op.getOperand(I);
5428 if (Lane.getOpcode() == ISD::Constant) {
5429 APInt LowBits(EltTy.getSizeInBits(),
5430 cast<ConstantSDNode>(Lane)->getZExtValue());
5431 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5433 Ops.push_back(Lane);
5435 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5438 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5439 SelectionDAG &DAG) const {
5441 EVT VT = Op.getValueType();
5442 Op = NormalizeBuildVector(Op, DAG);
5443 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5445 APInt CnstBits(VT.getSizeInBits(), 0);
5446 APInt UndefBits(VT.getSizeInBits(), 0);
5447 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5448 // We make use of a little bit of goto ickiness in order to avoid having to
5449 // duplicate the immediate matching logic for the undef toggled case.
5450 bool SecondTry = false;
5453 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5454 CnstBits = CnstBits.zextOrTrunc(64);
5455 uint64_t CnstVal = CnstBits.getZExtValue();
5457 // Certain magic vector constants (used to express things like NOT
5458 // and NEG) are passed through unmodified. This allows codegen patterns
5459 // for these operations to match. Special-purpose patterns will lower
5460 // these immediates to MOVIs if it proves necessary.
5461 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5464 // The many faces of MOVI...
5465 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5466 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5467 if (VT.getSizeInBits() == 128) {
5468 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5469 DAG.getConstant(CnstVal, MVT::i32));
5470 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5473 // Support the V64 version via subregister insertion.
5474 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5475 DAG.getConstant(CnstVal, MVT::i32));
5476 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5479 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5480 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5481 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5482 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5483 DAG.getConstant(CnstVal, MVT::i32),
5484 DAG.getConstant(0, MVT::i32));
5485 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5488 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5489 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5490 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5491 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5492 DAG.getConstant(CnstVal, MVT::i32),
5493 DAG.getConstant(8, MVT::i32));
5494 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5497 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5498 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5499 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5500 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5501 DAG.getConstant(CnstVal, MVT::i32),
5502 DAG.getConstant(16, MVT::i32));
5503 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5506 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5507 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5508 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5509 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5510 DAG.getConstant(CnstVal, MVT::i32),
5511 DAG.getConstant(24, MVT::i32));
5512 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5515 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5516 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5517 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5518 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5519 DAG.getConstant(CnstVal, MVT::i32),
5520 DAG.getConstant(0, MVT::i32));
5521 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5524 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5525 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5526 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5527 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5528 DAG.getConstant(CnstVal, MVT::i32),
5529 DAG.getConstant(8, MVT::i32));
5530 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5533 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5534 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5535 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5536 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5537 DAG.getConstant(CnstVal, MVT::i32),
5538 DAG.getConstant(264, MVT::i32));
5539 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5542 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5543 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5544 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5545 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5546 DAG.getConstant(CnstVal, MVT::i32),
5547 DAG.getConstant(272, MVT::i32));
5548 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5551 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5552 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5553 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5554 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5555 DAG.getConstant(CnstVal, MVT::i32));
5556 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5559 // The few faces of FMOV...
5560 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5561 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5562 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5563 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5564 DAG.getConstant(CnstVal, MVT::i32));
5565 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5568 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5569 VT.getSizeInBits() == 128) {
5570 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5571 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5572 DAG.getConstant(CnstVal, MVT::i32));
5573 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5576 // The many faces of MVNI...
5578 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5579 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5580 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5581 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5582 DAG.getConstant(CnstVal, MVT::i32),
5583 DAG.getConstant(0, MVT::i32));
5584 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5587 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5588 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5589 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5590 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5591 DAG.getConstant(CnstVal, MVT::i32),
5592 DAG.getConstant(8, MVT::i32));
5593 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5596 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5597 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5598 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5599 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5600 DAG.getConstant(CnstVal, MVT::i32),
5601 DAG.getConstant(16, MVT::i32));
5602 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5605 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5606 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5607 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5608 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5609 DAG.getConstant(CnstVal, MVT::i32),
5610 DAG.getConstant(24, MVT::i32));
5611 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5614 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5615 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5616 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5617 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5618 DAG.getConstant(CnstVal, MVT::i32),
5619 DAG.getConstant(0, MVT::i32));
5620 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5623 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5624 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5625 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5626 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5627 DAG.getConstant(CnstVal, MVT::i32),
5628 DAG.getConstant(8, MVT::i32));
5629 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5632 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5633 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5634 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5635 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5636 DAG.getConstant(CnstVal, MVT::i32),
5637 DAG.getConstant(264, MVT::i32));
5638 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5641 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5642 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5643 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5644 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5645 DAG.getConstant(CnstVal, MVT::i32),
5646 DAG.getConstant(272, MVT::i32));
5647 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5654 CnstBits = UndefBits;
5659 // Scan through the operands to find some interesting properties we can
5661 // 1) If only one value is used, we can use a DUP, or
5662 // 2) if only the low element is not undef, we can just insert that, or
5663 // 3) if only one constant value is used (w/ some non-constant lanes),
5664 // we can splat the constant value into the whole vector then fill
5665 // in the non-constant lanes.
5666 // 4) FIXME: If different constant values are used, but we can intelligently
5667 // select the values we'll be overwriting for the non-constant
5668 // lanes such that we can directly materialize the vector
5669 // some other way (MOVI, e.g.), we can be sneaky.
5670 unsigned NumElts = VT.getVectorNumElements();
5671 bool isOnlyLowElement = true;
5672 bool usesOnlyOneValue = true;
5673 bool usesOnlyOneConstantValue = true;
5674 bool isConstant = true;
5675 unsigned NumConstantLanes = 0;
5677 SDValue ConstantValue;
5678 for (unsigned i = 0; i < NumElts; ++i) {
5679 SDValue V = Op.getOperand(i);
5680 if (V.getOpcode() == ISD::UNDEF)
5683 isOnlyLowElement = false;
5684 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5687 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5689 if (!ConstantValue.getNode())
5691 else if (ConstantValue != V)
5692 usesOnlyOneConstantValue = false;
5695 if (!Value.getNode())
5697 else if (V != Value)
5698 usesOnlyOneValue = false;
5701 if (!Value.getNode())
5702 return DAG.getUNDEF(VT);
5704 if (isOnlyLowElement)
5705 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5707 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5708 // i32 and try again.
5709 if (usesOnlyOneValue) {
5711 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5712 Value.getValueType() != VT)
5713 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5715 // This is actually a DUPLANExx operation, which keeps everything vectory.
5717 // DUPLANE works on 128-bit vectors, widen it if necessary.
5718 SDValue Lane = Value.getOperand(1);
5719 Value = Value.getOperand(0);
5720 if (Value.getValueType().getSizeInBits() == 64)
5721 Value = WidenVector(Value, DAG);
5723 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5724 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5727 if (VT.getVectorElementType().isFloatingPoint()) {
5728 SmallVector<SDValue, 8> Ops;
5730 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5731 for (unsigned i = 0; i < NumElts; ++i)
5732 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5733 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5734 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5735 Val = LowerBUILD_VECTOR(Val, DAG);
5737 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5741 // If there was only one constant value used and for more than one lane,
5742 // start by splatting that value, then replace the non-constant lanes. This
5743 // is better than the default, which will perform a separate initialization
5745 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5746 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5747 // Now insert the non-constant lanes.
5748 for (unsigned i = 0; i < NumElts; ++i) {
5749 SDValue V = Op.getOperand(i);
5750 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5751 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5752 // Note that type legalization likely mucked about with the VT of the
5753 // source operand, so we may have to convert it here before inserting.
5754 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5760 // If all elements are constants and the case above didn't get hit, fall back
5761 // to the default expansion, which will generate a load from the constant
5766 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5768 SDValue shuffle = ReconstructShuffle(Op, DAG);
5769 if (shuffle != SDValue())
5773 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5774 // know the default expansion would otherwise fall back on something even
5775 // worse. For a vector with one or two non-undef values, that's
5776 // scalar_to_vector for the elements followed by a shuffle (provided the
5777 // shuffle is valid for the target) and materialization element by element
5778 // on the stack followed by a load for everything else.
5779 if (!isConstant && !usesOnlyOneValue) {
5780 SDValue Vec = DAG.getUNDEF(VT);
5781 SDValue Op0 = Op.getOperand(0);
5782 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5784 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5785 // a) Avoid a RMW dependency on the full vector register, and
5786 // b) Allow the register coalescer to fold away the copy if the
5787 // value is already in an S or D register.
5788 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5789 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5791 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5792 DAG.getTargetConstant(SubIdx, MVT::i32));
5793 Vec = SDValue(N, 0);
5796 for (; i < NumElts; ++i) {
5797 SDValue V = Op.getOperand(i);
5798 if (V.getOpcode() == ISD::UNDEF)
5800 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5801 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5806 // Just use the default expansion. We failed to find a better alternative.
5810 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5811 SelectionDAG &DAG) const {
5812 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5814 // Check for non-constant or out of range lane.
5815 EVT VT = Op.getOperand(0).getValueType();
5816 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5817 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5821 // Insertion/extraction are legal for V128 types.
5822 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5823 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5827 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5828 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5831 // For V64 types, we perform insertion by expanding the value
5832 // to a V128 type and perform the insertion on that.
5834 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5835 EVT WideTy = WideVec.getValueType();
5837 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5838 Op.getOperand(1), Op.getOperand(2));
5839 // Re-narrow the resultant vector.
5840 return NarrowVector(Node, DAG);
5844 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5845 SelectionDAG &DAG) const {
5846 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5848 // Check for non-constant or out of range lane.
5849 EVT VT = Op.getOperand(0).getValueType();
5850 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5851 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5855 // Insertion/extraction are legal for V128 types.
5856 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5857 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5861 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5862 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5865 // For V64 types, we perform extraction by expanding the value
5866 // to a V128 type and perform the extraction on that.
5868 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5869 EVT WideTy = WideVec.getValueType();
5871 EVT ExtrTy = WideTy.getVectorElementType();
5872 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5875 // For extractions, we just return the result directly.
5876 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5880 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5881 SelectionDAG &DAG) const {
5882 EVT VT = Op.getOperand(0).getValueType();
5888 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5891 unsigned Val = Cst->getZExtValue();
5893 unsigned Size = Op.getValueType().getSizeInBits();
5897 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5900 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5903 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5906 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5909 llvm_unreachable("Unexpected vector type in extract_subvector!");
5912 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5914 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5920 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5922 if (VT.getVectorNumElements() == 4 &&
5923 (VT.is128BitVector() || VT.is64BitVector())) {
5924 unsigned PFIndexes[4];
5925 for (unsigned i = 0; i != 4; ++i) {
5929 PFIndexes[i] = M[i];
5932 // Compute the index in the perfect shuffle table.
5933 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5934 PFIndexes[2] * 9 + PFIndexes[3];
5935 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5936 unsigned Cost = (PFEntry >> 30);
5944 unsigned DummyUnsigned;
5946 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5947 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5948 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5949 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5950 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5951 isZIPMask(M, VT, DummyUnsigned) ||
5952 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5953 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5954 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5955 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5956 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5959 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5960 /// operand of a vector shift operation, where all the elements of the
5961 /// build_vector must have the same constant integer value.
5962 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5963 // Ignore bit_converts.
5964 while (Op.getOpcode() == ISD::BITCAST)
5965 Op = Op.getOperand(0);
5966 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5967 APInt SplatBits, SplatUndef;
5968 unsigned SplatBitSize;
5970 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5971 HasAnyUndefs, ElementBits) ||
5972 SplatBitSize > ElementBits)
5974 Cnt = SplatBits.getSExtValue();
5978 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5979 /// operand of a vector shift left operation. That value must be in the range:
5980 /// 0 <= Value < ElementBits for a left shift; or
5981 /// 0 <= Value <= ElementBits for a long left shift.
5982 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5983 assert(VT.isVector() && "vector shift count is not a vector type");
5984 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5985 if (!getVShiftImm(Op, ElementBits, Cnt))
5987 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5990 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5991 /// operand of a vector shift right operation. For a shift opcode, the value
5992 /// is positive, but for an intrinsic the value count must be negative. The
5993 /// absolute value must be in the range:
5994 /// 1 <= |Value| <= ElementBits for a right shift; or
5995 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5996 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5998 assert(VT.isVector() && "vector shift count is not a vector type");
5999 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6000 if (!getVShiftImm(Op, ElementBits, Cnt))
6004 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6007 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6008 SelectionDAG &DAG) const {
6009 EVT VT = Op.getValueType();
6013 if (!Op.getOperand(1).getValueType().isVector())
6015 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6017 switch (Op.getOpcode()) {
6019 llvm_unreachable("unexpected shift opcode");
6022 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6023 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6024 DAG.getConstant(Cnt, MVT::i32));
6025 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6026 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6027 Op.getOperand(0), Op.getOperand(1));
6030 // Right shift immediate
6031 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6034 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6035 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6036 DAG.getConstant(Cnt, MVT::i32));
6039 // Right shift register. Note, there is not a shift right register
6040 // instruction, but the shift left register instruction takes a signed
6041 // value, where negative numbers specify a right shift.
6042 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6043 : Intrinsic::aarch64_neon_ushl;
6044 // negate the shift amount
6045 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6046 SDValue NegShiftLeft =
6047 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6048 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6049 return NegShiftLeft;
6055 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6056 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6057 SDLoc dl, SelectionDAG &DAG) {
6058 EVT SrcVT = LHS.getValueType();
6060 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6061 APInt CnstBits(VT.getSizeInBits(), 0);
6062 APInt UndefBits(VT.getSizeInBits(), 0);
6063 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6064 bool IsZero = IsCnst && (CnstBits == 0);
6066 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6070 case AArch64CC::NE: {
6073 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6075 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6076 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6080 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6081 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6084 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6085 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6088 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6089 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6092 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6093 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6097 // If we ignore NaNs then we can use to the MI implementation.
6101 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6102 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6109 case AArch64CC::NE: {
6112 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6114 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6115 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6119 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6120 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6123 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6124 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6127 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6128 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6131 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6132 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6134 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6136 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6139 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6140 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6142 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6144 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6148 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6149 SelectionDAG &DAG) const {
6150 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6151 SDValue LHS = Op.getOperand(0);
6152 SDValue RHS = Op.getOperand(1);
6155 if (LHS.getValueType().getVectorElementType().isInteger()) {
6156 assert(LHS.getValueType() == RHS.getValueType());
6157 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6158 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
6162 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6163 LHS.getValueType().getVectorElementType() == MVT::f64);
6165 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6166 // clean. Some of them require two branches to implement.
6167 AArch64CC::CondCode CC1, CC2;
6169 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6171 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6173 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
6177 if (CC2 != AArch64CC::AL) {
6179 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
6180 if (!Cmp2.getNode())
6183 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
6187 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6192 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6193 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6194 /// specified in the intrinsic calls.
6195 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6197 unsigned Intrinsic) const {
6198 switch (Intrinsic) {
6199 case Intrinsic::aarch64_neon_ld2:
6200 case Intrinsic::aarch64_neon_ld3:
6201 case Intrinsic::aarch64_neon_ld4:
6202 case Intrinsic::aarch64_neon_ld1x2:
6203 case Intrinsic::aarch64_neon_ld1x3:
6204 case Intrinsic::aarch64_neon_ld1x4:
6205 case Intrinsic::aarch64_neon_ld2lane:
6206 case Intrinsic::aarch64_neon_ld3lane:
6207 case Intrinsic::aarch64_neon_ld4lane:
6208 case Intrinsic::aarch64_neon_ld2r:
6209 case Intrinsic::aarch64_neon_ld3r:
6210 case Intrinsic::aarch64_neon_ld4r: {
6211 Info.opc = ISD::INTRINSIC_W_CHAIN;
6212 // Conservatively set memVT to the entire set of vectors loaded.
6213 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6214 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6215 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6218 Info.vol = false; // volatile loads with NEON intrinsics not supported
6219 Info.readMem = true;
6220 Info.writeMem = false;
6223 case Intrinsic::aarch64_neon_st2:
6224 case Intrinsic::aarch64_neon_st3:
6225 case Intrinsic::aarch64_neon_st4:
6226 case Intrinsic::aarch64_neon_st1x2:
6227 case Intrinsic::aarch64_neon_st1x3:
6228 case Intrinsic::aarch64_neon_st1x4:
6229 case Intrinsic::aarch64_neon_st2lane:
6230 case Intrinsic::aarch64_neon_st3lane:
6231 case Intrinsic::aarch64_neon_st4lane: {
6232 Info.opc = ISD::INTRINSIC_VOID;
6233 // Conservatively set memVT to the entire set of vectors stored.
6234 unsigned NumElts = 0;
6235 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6236 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6237 if (!ArgTy->isVectorTy())
6239 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6241 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6242 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6245 Info.vol = false; // volatile stores with NEON intrinsics not supported
6246 Info.readMem = false;
6247 Info.writeMem = true;
6250 case Intrinsic::aarch64_ldaxr:
6251 case Intrinsic::aarch64_ldxr: {
6252 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6253 Info.opc = ISD::INTRINSIC_W_CHAIN;
6254 Info.memVT = MVT::getVT(PtrTy->getElementType());
6255 Info.ptrVal = I.getArgOperand(0);
6257 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6259 Info.readMem = true;
6260 Info.writeMem = false;
6263 case Intrinsic::aarch64_stlxr:
6264 case Intrinsic::aarch64_stxr: {
6265 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6266 Info.opc = ISD::INTRINSIC_W_CHAIN;
6267 Info.memVT = MVT::getVT(PtrTy->getElementType());
6268 Info.ptrVal = I.getArgOperand(1);
6270 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6272 Info.readMem = false;
6273 Info.writeMem = true;
6276 case Intrinsic::aarch64_ldaxp:
6277 case Intrinsic::aarch64_ldxp: {
6278 Info.opc = ISD::INTRINSIC_W_CHAIN;
6279 Info.memVT = MVT::i128;
6280 Info.ptrVal = I.getArgOperand(0);
6284 Info.readMem = true;
6285 Info.writeMem = false;
6288 case Intrinsic::aarch64_stlxp:
6289 case Intrinsic::aarch64_stxp: {
6290 Info.opc = ISD::INTRINSIC_W_CHAIN;
6291 Info.memVT = MVT::i128;
6292 Info.ptrVal = I.getArgOperand(2);
6296 Info.readMem = false;
6297 Info.writeMem = true;
6307 // Truncations from 64-bit GPR to 32-bit GPR is free.
6308 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6309 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6311 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6312 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6313 return NumBits1 > NumBits2;
6315 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6316 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6318 unsigned NumBits1 = VT1.getSizeInBits();
6319 unsigned NumBits2 = VT2.getSizeInBits();
6320 return NumBits1 > NumBits2;
6323 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6325 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6326 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6328 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6329 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6330 return NumBits1 == 32 && NumBits2 == 64;
6332 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6333 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6335 unsigned NumBits1 = VT1.getSizeInBits();
6336 unsigned NumBits2 = VT2.getSizeInBits();
6337 return NumBits1 == 32 && NumBits2 == 64;
6340 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6341 EVT VT1 = Val.getValueType();
6342 if (isZExtFree(VT1, VT2)) {
6346 if (Val.getOpcode() != ISD::LOAD)
6349 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6350 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6351 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6352 VT1.getSizeInBits() <= 32);
6355 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6356 unsigned &RequiredAligment) const {
6357 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6359 // Cyclone supports unaligned accesses.
6360 RequiredAligment = 0;
6361 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6362 return NumBits == 32 || NumBits == 64;
6365 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6366 unsigned &RequiredAligment) const {
6367 if (!LoadedType.isSimple() ||
6368 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6370 // Cyclone supports unaligned accesses.
6371 RequiredAligment = 0;
6372 unsigned NumBits = LoadedType.getSizeInBits();
6373 return NumBits == 32 || NumBits == 64;
6376 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6377 unsigned AlignCheck) {
6378 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6379 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6382 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6383 unsigned SrcAlign, bool IsMemset,
6386 MachineFunction &MF) const {
6387 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6388 // instruction to materialize the v2i64 zero and one store (with restrictive
6389 // addressing mode). Just do two i64 store of zero-registers.
6391 const Function *F = MF.getFunction();
6392 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6393 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6394 Attribute::NoImplicitFloat) &&
6395 (memOpAlign(SrcAlign, DstAlign, 16) ||
6396 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6399 return Size >= 8 ? MVT::i64 : MVT::i32;
6402 // 12-bit optionally shifted immediates are legal for adds.
6403 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6404 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6409 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6410 // immediates is the same as for an add or a sub.
6411 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6414 return isLegalAddImmediate(Immed);
6417 /// isLegalAddressingMode - Return true if the addressing mode represented
6418 /// by AM is legal for this target, for a load/store of the specified type.
6419 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6421 // AArch64 has five basic addressing modes:
6423 // reg + 9-bit signed offset
6424 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6426 // reg + SIZE_IN_BYTES * reg
6428 // No global is ever allowed as a base.
6432 // No reg+reg+imm addressing.
6433 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6436 // check reg + imm case:
6437 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6438 uint64_t NumBytes = 0;
6439 if (Ty->isSized()) {
6440 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6441 NumBytes = NumBits / 8;
6442 if (!isPowerOf2_64(NumBits))
6447 int64_t Offset = AM.BaseOffs;
6449 // 9-bit signed offset
6450 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6453 // 12-bit unsigned offset
6454 unsigned shift = Log2_64(NumBytes);
6455 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6456 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6457 (Offset >> shift) << shift == Offset)
6462 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6464 if (!AM.Scale || AM.Scale == 1 ||
6465 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6470 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6472 // Scaling factors are not free at all.
6473 // Operands | Rt Latency
6474 // -------------------------------------------
6476 // -------------------------------------------
6477 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6478 // Rt, [Xn, Wm, <extend> #imm] |
6479 if (isLegalAddressingMode(AM, Ty))
6480 // Scale represents reg2 * scale, thus account for 1 if
6481 // it is not equal to 0 or 1.
6482 return AM.Scale != 0 && AM.Scale != 1;
6486 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6487 VT = VT.getScalarType();
6492 switch (VT.getSimpleVT().SimpleTy) {
6504 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6505 // LR is a callee-save register, but we must treat it as clobbered by any call
6506 // site. Hence we include LR in the scratch registers, which are in turn added
6507 // as implicit-defs for stackmaps and patchpoints.
6508 static const MCPhysReg ScratchRegs[] = {
6509 AArch64::X16, AArch64::X17, AArch64::LR, 0
6515 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6516 EVT VT = N->getValueType(0);
6517 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6518 // it with shift to let it be lowered to UBFX.
6519 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6520 isa<ConstantSDNode>(N->getOperand(1))) {
6521 uint64_t TruncMask = N->getConstantOperandVal(1);
6522 if (isMask_64(TruncMask) &&
6523 N->getOperand(0).getOpcode() == ISD::SRL &&
6524 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6530 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6532 assert(Ty->isIntegerTy());
6534 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6538 int64_t Val = Imm.getSExtValue();
6539 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6542 if ((int64_t)Val < 0)
6545 Val &= (1LL << 32) - 1;
6547 unsigned LZ = countLeadingZeros((uint64_t)Val);
6548 unsigned Shift = (63 - LZ) / 16;
6549 // MOVZ is free so return true for one or fewer MOVK.
6550 return (Shift < 3) ? true : false;
6553 // Generate SUBS and CSEL for integer abs.
6554 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6555 EVT VT = N->getValueType(0);
6557 SDValue N0 = N->getOperand(0);
6558 SDValue N1 = N->getOperand(1);
6561 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6562 // and change it to SUB and CSEL.
6563 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6564 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6565 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6566 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6567 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6568 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6570 // Generate SUBS & CSEL.
6572 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6573 N0.getOperand(0), DAG.getConstant(0, VT));
6574 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6575 DAG.getConstant(AArch64CC::PL, MVT::i32),
6576 SDValue(Cmp.getNode(), 1));
6581 // performXorCombine - Attempts to handle integer ABS.
6582 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6583 TargetLowering::DAGCombinerInfo &DCI,
6584 const AArch64Subtarget *Subtarget) {
6585 if (DCI.isBeforeLegalizeOps())
6588 return performIntegerAbsCombine(N, DAG);
6592 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6594 std::vector<SDNode *> *Created) const {
6595 // fold (sdiv X, pow2)
6596 EVT VT = N->getValueType(0);
6597 if ((VT != MVT::i32 && VT != MVT::i64) ||
6598 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6602 SDValue N0 = N->getOperand(0);
6603 unsigned Lg2 = Divisor.countTrailingZeros();
6604 SDValue Zero = DAG.getConstant(0, VT);
6605 SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT);
6607 // Add (N0 < 0) ? Pow2 - 1 : 0;
6609 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6610 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6611 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6614 Created->push_back(Cmp.getNode());
6615 Created->push_back(Add.getNode());
6616 Created->push_back(CSel.getNode());
6621 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6623 // If we're dividing by a positive value, we're done. Otherwise, we must
6624 // negate the result.
6625 if (Divisor.isNonNegative())
6629 Created->push_back(SRA.getNode());
6630 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6633 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6634 TargetLowering::DAGCombinerInfo &DCI,
6635 const AArch64Subtarget *Subtarget) {
6636 if (DCI.isBeforeLegalizeOps())
6639 // Multiplication of a power of two plus/minus one can be done more
6640 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6641 // future CPUs have a cheaper MADD instruction, this may need to be
6642 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6643 // 64-bit is 5 cycles, so this is always a win.
6644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6645 APInt Value = C->getAPIntValue();
6646 EVT VT = N->getValueType(0);
6647 if (Value.isNonNegative()) {
6648 // (mul x, 2^N + 1) => (add (shl x, N), x)
6649 APInt VM1 = Value - 1;
6650 if (VM1.isPowerOf2()) {
6651 SDValue ShiftedVal =
6652 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6653 DAG.getConstant(VM1.logBase2(), MVT::i64));
6654 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6657 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6658 APInt VP1 = Value + 1;
6659 if (VP1.isPowerOf2()) {
6660 SDValue ShiftedVal =
6661 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6662 DAG.getConstant(VP1.logBase2(), MVT::i64));
6663 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6667 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6668 APInt VNM1 = -Value - 1;
6669 if (VNM1.isPowerOf2()) {
6670 SDValue ShiftedVal =
6671 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6672 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6674 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6675 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6677 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6678 APInt VNP1 = -Value + 1;
6679 if (VNP1.isPowerOf2()) {
6680 SDValue ShiftedVal =
6681 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6682 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6683 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6691 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6692 SelectionDAG &DAG) {
6693 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6694 // optimize away operation when it's from a constant.
6696 // The general transformation is:
6697 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6698 // AND(VECTOR_CMP(x,y), constant2)
6699 // constant2 = UNARYOP(constant)
6701 // Early exit if this isn't a vector operation, the operand of the
6702 // unary operation isn't a bitwise AND, or if the sizes of the operations
6704 EVT VT = N->getValueType(0);
6705 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6706 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6707 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6710 // Now check that the other operand of the AND is a constant. We could
6711 // make the transformation for non-constant splats as well, but it's unclear
6712 // that would be a benefit as it would not eliminate any operations, just
6713 // perform one more step in scalar code before moving to the vector unit.
6714 if (BuildVectorSDNode *BV =
6715 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6716 // Bail out if the vector isn't a constant.
6717 if (!BV->isConstant())
6720 // Everything checks out. Build up the new and improved node.
6722 EVT IntVT = BV->getValueType(0);
6723 // Create a new constant of the appropriate type for the transformed
6725 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6726 // The AND node needs bitcasts to/from an integer vector type around it.
6727 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6728 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6729 N->getOperand(0)->getOperand(0), MaskConst);
6730 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6737 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6738 // First try to optimize away the conversion when it's conditionally from
6739 // a constant. Vectors only.
6740 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6741 if (Res != SDValue())
6744 EVT VT = N->getValueType(0);
6745 if (VT != MVT::f32 && VT != MVT::f64)
6748 // Only optimize when the source and destination types have the same width.
6749 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6752 // If the result of an integer load is only used by an integer-to-float
6753 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6754 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6755 SDValue N0 = N->getOperand(0);
6756 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6757 // Do not change the width of a volatile load.
6758 !cast<LoadSDNode>(N0)->isVolatile()) {
6759 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6760 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6761 LN0->getPointerInfo(), LN0->isVolatile(),
6762 LN0->isNonTemporal(), LN0->isInvariant(),
6763 LN0->getAlignment());
6765 // Make sure successors of the original load stay after it by updating them
6766 // to use the new Chain.
6767 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6770 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6771 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6777 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6778 /// searches for and classifies those shifts.
6779 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6781 if (N.getOpcode() == ISD::SHL)
6783 else if (N.getOpcode() == ISD::SRL)
6788 if (!isa<ConstantSDNode>(N.getOperand(1)))
6791 ShiftAmount = N->getConstantOperandVal(1);
6792 Src = N->getOperand(0);
6796 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6797 /// registers viewed as a high/low pair. This function looks for the pattern:
6798 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6799 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6801 static SDValue tryCombineToEXTR(SDNode *N,
6802 TargetLowering::DAGCombinerInfo &DCI) {
6803 SelectionDAG &DAG = DCI.DAG;
6805 EVT VT = N->getValueType(0);
6807 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6809 if (VT != MVT::i32 && VT != MVT::i64)
6813 uint32_t ShiftLHS = 0;
6815 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6819 uint32_t ShiftRHS = 0;
6821 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6824 // If they're both trying to come from the high part of the register, they're
6825 // not really an EXTR.
6826 if (LHSFromHi == RHSFromHi)
6829 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6833 std::swap(LHS, RHS);
6834 std::swap(ShiftLHS, ShiftRHS);
6837 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6838 DAG.getConstant(ShiftRHS, MVT::i64));
6841 static SDValue tryCombineToBSL(SDNode *N,
6842 TargetLowering::DAGCombinerInfo &DCI) {
6843 EVT VT = N->getValueType(0);
6844 SelectionDAG &DAG = DCI.DAG;
6850 SDValue N0 = N->getOperand(0);
6851 if (N0.getOpcode() != ISD::AND)
6854 SDValue N1 = N->getOperand(1);
6855 if (N1.getOpcode() != ISD::AND)
6858 // We only have to look for constant vectors here since the general, variable
6859 // case can be handled in TableGen.
6860 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6861 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6862 for (int i = 1; i >= 0; --i)
6863 for (int j = 1; j >= 0; --j) {
6864 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6865 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6869 bool FoundMatch = true;
6870 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6871 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6872 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6874 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6881 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6882 N0->getOperand(1 - i), N1->getOperand(1 - j));
6888 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6889 const AArch64Subtarget *Subtarget) {
6890 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6891 if (!EnableAArch64ExtrGeneration)
6893 SelectionDAG &DAG = DCI.DAG;
6894 EVT VT = N->getValueType(0);
6896 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6899 SDValue Res = tryCombineToEXTR(N, DCI);
6903 Res = tryCombineToBSL(N, DCI);
6910 static SDValue performBitcastCombine(SDNode *N,
6911 TargetLowering::DAGCombinerInfo &DCI,
6912 SelectionDAG &DAG) {
6913 // Wait 'til after everything is legalized to try this. That way we have
6914 // legal vector types and such.
6915 if (DCI.isBeforeLegalizeOps())
6918 // Remove extraneous bitcasts around an extract_subvector.
6920 // (v4i16 (bitconvert
6921 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6923 // (extract_subvector ((v8i16 ...), (i64 4)))
6925 // Only interested in 64-bit vectors as the ultimate result.
6926 EVT VT = N->getValueType(0);
6929 if (VT.getSimpleVT().getSizeInBits() != 64)
6931 // Is the operand an extract_subvector starting at the beginning or halfway
6932 // point of the vector? A low half may also come through as an
6933 // EXTRACT_SUBREG, so look for that, too.
6934 SDValue Op0 = N->getOperand(0);
6935 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6936 !(Op0->isMachineOpcode() &&
6937 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6939 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6940 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6941 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6943 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6944 if (idx != AArch64::dsub)
6946 // The dsub reference is equivalent to a lane zero subvector reference.
6949 // Look through the bitcast of the input to the extract.
6950 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6952 SDValue Source = Op0->getOperand(0)->getOperand(0);
6953 // If the source type has twice the number of elements as our destination
6954 // type, we know this is an extract of the high or low half of the vector.
6955 EVT SVT = Source->getValueType(0);
6956 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6959 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6961 // Create the simplified form to just extract the low or high half of the
6962 // vector directly rather than bothering with the bitcasts.
6964 unsigned NumElements = VT.getVectorNumElements();
6966 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6967 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6969 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6970 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6976 static SDValue performConcatVectorsCombine(SDNode *N,
6977 TargetLowering::DAGCombinerInfo &DCI,
6978 SelectionDAG &DAG) {
6979 // Wait 'til after everything is legalized to try this. That way we have
6980 // legal vector types and such.
6981 if (DCI.isBeforeLegalizeOps())
6985 EVT VT = N->getValueType(0);
6987 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6988 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6989 // canonicalise to that.
6990 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6991 assert(VT.getVectorElementType().getSizeInBits() == 64);
6992 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6993 WidenVector(N->getOperand(0), DAG),
6994 DAG.getConstant(0, MVT::i64));
6997 // Canonicalise concat_vectors so that the right-hand vector has as few
6998 // bit-casts as possible before its real operation. The primary matching
6999 // destination for these operations will be the narrowing "2" instructions,
7000 // which depend on the operation being performed on this right-hand vector.
7002 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7004 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7006 SDValue Op1 = N->getOperand(1);
7007 if (Op1->getOpcode() != ISD::BITCAST)
7009 SDValue RHS = Op1->getOperand(0);
7010 MVT RHSTy = RHS.getValueType().getSimpleVT();
7011 // If the RHS is not a vector, this is not the pattern we're looking for.
7012 if (!RHSTy.isVector())
7015 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7017 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7018 RHSTy.getVectorNumElements() * 2);
7020 ISD::BITCAST, dl, VT,
7021 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7022 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
7025 static SDValue tryCombineFixedPointConvert(SDNode *N,
7026 TargetLowering::DAGCombinerInfo &DCI,
7027 SelectionDAG &DAG) {
7028 // Wait 'til after everything is legalized to try this. That way we have
7029 // legal vector types and such.
7030 if (DCI.isBeforeLegalizeOps())
7032 // Transform a scalar conversion of a value from a lane extract into a
7033 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7034 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7035 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7037 // The second form interacts better with instruction selection and the
7038 // register allocator to avoid cross-class register copies that aren't
7039 // coalescable due to a lane reference.
7041 // Check the operand and see if it originates from a lane extract.
7042 SDValue Op1 = N->getOperand(1);
7043 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7044 // Yep, no additional predication needed. Perform the transform.
7045 SDValue IID = N->getOperand(0);
7046 SDValue Shift = N->getOperand(2);
7047 SDValue Vec = Op1.getOperand(0);
7048 SDValue Lane = Op1.getOperand(1);
7049 EVT ResTy = N->getValueType(0);
7053 // The vector width should be 128 bits by the time we get here, even
7054 // if it started as 64 bits (the extract_vector handling will have
7056 assert(Vec.getValueType().getSizeInBits() == 128 &&
7057 "unexpected vector size on extract_vector_elt!");
7058 if (Vec.getValueType() == MVT::v4i32)
7059 VecResTy = MVT::v4f32;
7060 else if (Vec.getValueType() == MVT::v2i64)
7061 VecResTy = MVT::v2f64;
7063 llvm_unreachable("unexpected vector type!");
7066 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7067 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7072 // AArch64 high-vector "long" operations are formed by performing the non-high
7073 // version on an extract_subvector of each operand which gets the high half:
7075 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7077 // However, there are cases which don't have an extract_high explicitly, but
7078 // have another operation that can be made compatible with one for free. For
7081 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7083 // This routine does the actual conversion of such DUPs, once outer routines
7084 // have determined that everything else is in order.
7085 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7086 // We can handle most types of duplicate, but the lane ones have an extra
7087 // operand saying *which* lane, so we need to know.
7089 switch (N.getOpcode()) {
7090 case AArch64ISD::DUP:
7093 case AArch64ISD::DUPLANE8:
7094 case AArch64ISD::DUPLANE16:
7095 case AArch64ISD::DUPLANE32:
7096 case AArch64ISD::DUPLANE64:
7103 MVT NarrowTy = N.getSimpleValueType();
7104 if (!NarrowTy.is64BitVector())
7107 MVT ElementTy = NarrowTy.getVectorElementType();
7108 unsigned NumElems = NarrowTy.getVectorNumElements();
7109 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7113 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7116 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7118 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7119 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7122 static bool isEssentiallyExtractSubvector(SDValue N) {
7123 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7126 return N.getOpcode() == ISD::BITCAST &&
7127 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7130 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7131 struct GenericSetCCInfo {
7132 const SDValue *Opnd0;
7133 const SDValue *Opnd1;
7137 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7138 struct AArch64SetCCInfo {
7140 AArch64CC::CondCode CC;
7143 /// \brief Helper structure to keep track of SetCC information.
7145 GenericSetCCInfo Generic;
7146 AArch64SetCCInfo AArch64;
7149 /// \brief Helper structure to be able to read SetCC information. If set to
7150 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7151 /// GenericSetCCInfo.
7152 struct SetCCInfoAndKind {
7157 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7159 /// AArch64 lowered one.
7160 /// \p SetCCInfo is filled accordingly.
7161 /// \post SetCCInfo is meanginfull only when this function returns true.
7162 /// \return True when Op is a kind of SET_CC operation.
7163 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7164 // If this is a setcc, this is straight forward.
7165 if (Op.getOpcode() == ISD::SETCC) {
7166 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7167 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7168 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7169 SetCCInfo.IsAArch64 = false;
7172 // Otherwise, check if this is a matching csel instruction.
7176 if (Op.getOpcode() != AArch64ISD::CSEL)
7178 // Set the information about the operands.
7179 // TODO: we want the operands of the Cmp not the csel
7180 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7181 SetCCInfo.IsAArch64 = true;
7182 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7183 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7185 // Check that the operands matches the constraints:
7186 // (1) Both operands must be constants.
7187 // (2) One must be 1 and the other must be 0.
7188 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7189 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7192 if (!TValue || !FValue)
7196 if (!TValue->isOne()) {
7197 // Update the comparison when we are interested in !cc.
7198 std::swap(TValue, FValue);
7199 SetCCInfo.Info.AArch64.CC =
7200 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7202 return TValue->isOne() && FValue->isNullValue();
7205 // Returns true if Op is setcc or zext of setcc.
7206 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7207 if (isSetCC(Op, Info))
7209 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7210 isSetCC(Op->getOperand(0), Info));
7213 // The folding we want to perform is:
7214 // (add x, [zext] (setcc cc ...) )
7216 // (csel x, (add x, 1), !cc ...)
7218 // The latter will get matched to a CSINC instruction.
7219 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7220 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7221 SDValue LHS = Op->getOperand(0);
7222 SDValue RHS = Op->getOperand(1);
7223 SetCCInfoAndKind InfoAndKind;
7225 // If neither operand is a SET_CC, give up.
7226 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7227 std::swap(LHS, RHS);
7228 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7232 // FIXME: This could be generatized to work for FP comparisons.
7233 EVT CmpVT = InfoAndKind.IsAArch64
7234 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7235 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7236 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7242 if (InfoAndKind.IsAArch64) {
7243 CCVal = DAG.getConstant(
7244 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7245 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7247 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7248 *InfoAndKind.Info.Generic.Opnd1,
7249 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7252 EVT VT = Op->getValueType(0);
7253 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7254 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7257 // The basic add/sub long vector instructions have variants with "2" on the end
7258 // which act on the high-half of their inputs. They are normally matched by
7261 // (add (zeroext (extract_high LHS)),
7262 // (zeroext (extract_high RHS)))
7263 // -> uaddl2 vD, vN, vM
7265 // However, if one of the extracts is something like a duplicate, this
7266 // instruction can still be used profitably. This function puts the DAG into a
7267 // more appropriate form for those patterns to trigger.
7268 static SDValue performAddSubLongCombine(SDNode *N,
7269 TargetLowering::DAGCombinerInfo &DCI,
7270 SelectionDAG &DAG) {
7271 if (DCI.isBeforeLegalizeOps())
7274 MVT VT = N->getSimpleValueType(0);
7275 if (!VT.is128BitVector()) {
7276 if (N->getOpcode() == ISD::ADD)
7277 return performSetccAddFolding(N, DAG);
7281 // Make sure both branches are extended in the same way.
7282 SDValue LHS = N->getOperand(0);
7283 SDValue RHS = N->getOperand(1);
7284 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7285 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7286 LHS.getOpcode() != RHS.getOpcode())
7289 unsigned ExtType = LHS.getOpcode();
7291 // It's not worth doing if at least one of the inputs isn't already an
7292 // extract, but we don't know which it'll be so we have to try both.
7293 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7294 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7298 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7299 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7300 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7304 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7307 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7310 // Massage DAGs which we can use the high-half "long" operations on into
7311 // something isel will recognize better. E.g.
7313 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7314 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7315 // (extract_high (v2i64 (dup128 scalar)))))
7317 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7318 TargetLowering::DAGCombinerInfo &DCI,
7319 SelectionDAG &DAG) {
7320 if (DCI.isBeforeLegalizeOps())
7323 SDValue LHS = N->getOperand(1);
7324 SDValue RHS = N->getOperand(2);
7325 assert(LHS.getValueType().is64BitVector() &&
7326 RHS.getValueType().is64BitVector() &&
7327 "unexpected shape for long operation");
7329 // Either node could be a DUP, but it's not worth doing both of them (you'd
7330 // just as well use the non-high version) so look for a corresponding extract
7331 // operation on the other "wing".
7332 if (isEssentiallyExtractSubvector(LHS)) {
7333 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7336 } else if (isEssentiallyExtractSubvector(RHS)) {
7337 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7342 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7343 N->getOperand(0), LHS, RHS);
7346 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7347 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7348 unsigned ElemBits = ElemTy.getSizeInBits();
7350 int64_t ShiftAmount;
7351 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7352 APInt SplatValue, SplatUndef;
7353 unsigned SplatBitSize;
7355 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7356 HasAnyUndefs, ElemBits) ||
7357 SplatBitSize != ElemBits)
7360 ShiftAmount = SplatValue.getSExtValue();
7361 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7362 ShiftAmount = CVN->getSExtValue();
7370 llvm_unreachable("Unknown shift intrinsic");
7371 case Intrinsic::aarch64_neon_sqshl:
7372 Opcode = AArch64ISD::SQSHL_I;
7373 IsRightShift = false;
7375 case Intrinsic::aarch64_neon_uqshl:
7376 Opcode = AArch64ISD::UQSHL_I;
7377 IsRightShift = false;
7379 case Intrinsic::aarch64_neon_srshl:
7380 Opcode = AArch64ISD::SRSHR_I;
7381 IsRightShift = true;
7383 case Intrinsic::aarch64_neon_urshl:
7384 Opcode = AArch64ISD::URSHR_I;
7385 IsRightShift = true;
7387 case Intrinsic::aarch64_neon_sqshlu:
7388 Opcode = AArch64ISD::SQSHLU_I;
7389 IsRightShift = false;
7393 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7394 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7395 DAG.getConstant(-ShiftAmount, MVT::i32));
7396 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7397 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7398 DAG.getConstant(ShiftAmount, MVT::i32));
7403 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7404 // the intrinsics must be legal and take an i32, this means there's almost
7405 // certainly going to be a zext in the DAG which we can eliminate.
7406 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7407 SDValue AndN = N->getOperand(2);
7408 if (AndN.getOpcode() != ISD::AND)
7411 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7412 if (!CMask || CMask->getZExtValue() != Mask)
7415 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7416 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7419 static SDValue performIntrinsicCombine(SDNode *N,
7420 TargetLowering::DAGCombinerInfo &DCI,
7421 const AArch64Subtarget *Subtarget) {
7422 SelectionDAG &DAG = DCI.DAG;
7423 unsigned IID = getIntrinsicID(N);
7427 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7428 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7429 return tryCombineFixedPointConvert(N, DCI, DAG);
7431 case Intrinsic::aarch64_neon_fmax:
7432 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7433 N->getOperand(1), N->getOperand(2));
7434 case Intrinsic::aarch64_neon_fmin:
7435 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7436 N->getOperand(1), N->getOperand(2));
7437 case Intrinsic::aarch64_neon_smull:
7438 case Intrinsic::aarch64_neon_umull:
7439 case Intrinsic::aarch64_neon_pmull:
7440 case Intrinsic::aarch64_neon_sqdmull:
7441 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7442 case Intrinsic::aarch64_neon_sqshl:
7443 case Intrinsic::aarch64_neon_uqshl:
7444 case Intrinsic::aarch64_neon_sqshlu:
7445 case Intrinsic::aarch64_neon_srshl:
7446 case Intrinsic::aarch64_neon_urshl:
7447 return tryCombineShiftImm(IID, N, DAG);
7448 case Intrinsic::aarch64_crc32b:
7449 case Intrinsic::aarch64_crc32cb:
7450 return tryCombineCRC32(0xff, N, DAG);
7451 case Intrinsic::aarch64_crc32h:
7452 case Intrinsic::aarch64_crc32ch:
7453 return tryCombineCRC32(0xffff, N, DAG);
7458 static SDValue performExtendCombine(SDNode *N,
7459 TargetLowering::DAGCombinerInfo &DCI,
7460 SelectionDAG &DAG) {
7461 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7462 // we can convert that DUP into another extract_high (of a bigger DUP), which
7463 // helps the backend to decide that an sabdl2 would be useful, saving a real
7464 // extract_high operation.
7465 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7466 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7467 SDNode *ABDNode = N->getOperand(0).getNode();
7468 unsigned IID = getIntrinsicID(ABDNode);
7469 if (IID == Intrinsic::aarch64_neon_sabd ||
7470 IID == Intrinsic::aarch64_neon_uabd) {
7471 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7472 if (!NewABD.getNode())
7475 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7480 // This is effectively a custom type legalization for AArch64.
7482 // Type legalization will split an extend of a small, legal, type to a larger
7483 // illegal type by first splitting the destination type, often creating
7484 // illegal source types, which then get legalized in isel-confusing ways,
7485 // leading to really terrible codegen. E.g.,
7486 // %result = v8i32 sext v8i8 %value
7488 // %losrc = extract_subreg %value, ...
7489 // %hisrc = extract_subreg %value, ...
7490 // %lo = v4i32 sext v4i8 %losrc
7491 // %hi = v4i32 sext v4i8 %hisrc
7492 // Things go rapidly downhill from there.
7494 // For AArch64, the [sz]ext vector instructions can only go up one element
7495 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7496 // take two instructions.
7498 // This implies that the most efficient way to do the extend from v8i8
7499 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7500 // the normal splitting to happen for the v8i16->v8i32.
7502 // This is pre-legalization to catch some cases where the default
7503 // type legalization will create ill-tempered code.
7504 if (!DCI.isBeforeLegalizeOps())
7507 // We're only interested in cleaning things up for non-legal vector types
7508 // here. If both the source and destination are legal, things will just
7509 // work naturally without any fiddling.
7510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7511 EVT ResVT = N->getValueType(0);
7512 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7514 // If the vector type isn't a simple VT, it's beyond the scope of what
7515 // we're worried about here. Let legalization do its thing and hope for
7517 SDValue Src = N->getOperand(0);
7518 EVT SrcVT = Src->getValueType(0);
7519 if (!ResVT.isSimple() || !SrcVT.isSimple())
7522 // If the source VT is a 64-bit vector, we can play games and get the
7523 // better results we want.
7524 if (SrcVT.getSizeInBits() != 64)
7527 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7528 unsigned ElementCount = SrcVT.getVectorNumElements();
7529 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7531 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7533 // Now split the rest of the operation into two halves, each with a 64
7537 unsigned NumElements = ResVT.getVectorNumElements();
7538 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7539 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7540 ResVT.getVectorElementType(), NumElements / 2);
7542 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7543 LoVT.getVectorNumElements());
7544 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7545 DAG.getIntPtrConstant(0));
7546 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7547 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7548 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7549 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7551 // Now combine the parts back together so we still have a single result
7552 // like the combiner expects.
7553 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7556 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7557 /// value. The load store optimizer pass will merge them to store pair stores.
7558 /// This has better performance than a splat of the scalar followed by a split
7559 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7560 /// followed by an ext.b and two stores.
7561 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7562 SDValue StVal = St->getValue();
7563 EVT VT = StVal.getValueType();
7565 // Don't replace floating point stores, they possibly won't be transformed to
7566 // stp because of the store pair suppress pass.
7567 if (VT.isFloatingPoint())
7570 // Check for insert vector elements.
7571 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7574 // We can express a splat as store pair(s) for 2 or 4 elements.
7575 unsigned NumVecElts = VT.getVectorNumElements();
7576 if (NumVecElts != 4 && NumVecElts != 2)
7578 SDValue SplatVal = StVal.getOperand(1);
7579 unsigned RemainInsertElts = NumVecElts - 1;
7581 // Check that this is a splat.
7582 while (--RemainInsertElts) {
7583 SDValue NextInsertElt = StVal.getOperand(0);
7584 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7586 if (NextInsertElt.getOperand(1) != SplatVal)
7588 StVal = NextInsertElt;
7590 unsigned OrigAlignment = St->getAlignment();
7591 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7592 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7594 // Create scalar stores. This is at least as good as the code sequence for a
7595 // split unaligned store wich is a dup.s, ext.b, and two stores.
7596 // Most of the time the three stores should be replaced by store pair
7597 // instructions (stp).
7599 SDValue BasePtr = St->getBasePtr();
7601 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7602 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7604 unsigned Offset = EltOffset;
7605 while (--NumVecElts) {
7606 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7607 DAG.getConstant(Offset, MVT::i64));
7608 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7609 St->getPointerInfo(), St->isVolatile(),
7610 St->isNonTemporal(), Alignment);
7611 Offset += EltOffset;
7616 static SDValue performSTORECombine(SDNode *N,
7617 TargetLowering::DAGCombinerInfo &DCI,
7619 const AArch64Subtarget *Subtarget) {
7620 if (!DCI.isBeforeLegalize())
7623 StoreSDNode *S = cast<StoreSDNode>(N);
7624 if (S->isVolatile())
7627 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7628 // page boundries. We want to split such stores.
7629 if (!Subtarget->isCyclone())
7632 // Don't split at Oz.
7633 MachineFunction &MF = DAG.getMachineFunction();
7634 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7635 AttributeSet::FunctionIndex, Attribute::MinSize);
7639 SDValue StVal = S->getValue();
7640 EVT VT = StVal.getValueType();
7642 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7643 // those up regresses performance on micro-benchmarks and olden/bh.
7644 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7647 // Split unaligned 16B stores. They are terrible for performance.
7648 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7649 // extensions can use this to mark that it does not want splitting to happen
7650 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7651 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7652 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7653 S->getAlignment() <= 2)
7656 // If we get a splat of a scalar convert this vector store to a store of
7657 // scalars. They will be merged into store pairs thereby removing two
7659 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7660 if (ReplacedSplat != SDValue())
7661 return ReplacedSplat;
7664 unsigned NumElts = VT.getVectorNumElements() / 2;
7665 // Split VT into two.
7667 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7668 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7669 DAG.getIntPtrConstant(0));
7670 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7671 DAG.getIntPtrConstant(NumElts));
7672 SDValue BasePtr = S->getBasePtr();
7674 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7675 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7676 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7677 DAG.getConstant(8, MVT::i64));
7678 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7679 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7683 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7684 /// post-increment LD1R.
7685 static SDValue performPostLD1Combine(SDNode *N,
7686 TargetLowering::DAGCombinerInfo &DCI,
7688 if (DCI.isBeforeLegalizeOps())
7691 SelectionDAG &DAG = DCI.DAG;
7692 EVT VT = N->getValueType(0);
7694 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7695 SDNode *LD = N->getOperand(LoadIdx).getNode();
7696 // If it is not LOAD, can not do such combine.
7697 if (LD->getOpcode() != ISD::LOAD)
7700 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7701 EVT MemVT = LoadSDN->getMemoryVT();
7702 // Check if memory operand is the same type as the vector element.
7703 if (MemVT != VT.getVectorElementType())
7706 // Check if there are other uses. If so, do not combine as it will introduce
7708 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7710 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7716 SDValue Addr = LD->getOperand(1);
7717 SDValue Vector = N->getOperand(0);
7718 // Search for a use of the address operand that is an increment.
7719 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7720 Addr.getNode()->use_end(); UI != UE; ++UI) {
7722 if (User->getOpcode() != ISD::ADD
7723 || UI.getUse().getResNo() != Addr.getResNo())
7726 // Check that the add is independent of the load. Otherwise, folding it
7727 // would create a cycle.
7728 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7730 // Also check that add is not used in the vector operand. This would also
7732 if (User->isPredecessorOf(Vector.getNode()))
7735 // If the increment is a constant, it must match the memory ref size.
7736 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7737 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7738 uint32_t IncVal = CInc->getZExtValue();
7739 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7740 if (IncVal != NumBytes)
7742 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7745 SmallVector<SDValue, 8> Ops;
7746 Ops.push_back(LD->getOperand(0)); // Chain
7748 Ops.push_back(Vector); // The vector to be inserted
7749 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7751 Ops.push_back(Addr);
7754 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7755 SDVTList SDTys = DAG.getVTList(Tys);
7756 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7757 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7759 LoadSDN->getMemOperand());
7762 std::vector<SDValue> NewResults;
7763 NewResults.push_back(SDValue(LD, 0)); // The result of load
7764 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7765 DCI.CombineTo(LD, NewResults);
7766 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7767 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7774 /// Target-specific DAG combine function for NEON load/store intrinsics
7775 /// to merge base address updates.
7776 static SDValue performNEONPostLDSTCombine(SDNode *N,
7777 TargetLowering::DAGCombinerInfo &DCI,
7778 SelectionDAG &DAG) {
7779 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7782 unsigned AddrOpIdx = N->getNumOperands() - 1;
7783 SDValue Addr = N->getOperand(AddrOpIdx);
7785 // Search for a use of the address operand that is an increment.
7786 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7787 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7789 if (User->getOpcode() != ISD::ADD ||
7790 UI.getUse().getResNo() != Addr.getResNo())
7793 // Check that the add is independent of the load/store. Otherwise, folding
7794 // it would create a cycle.
7795 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7798 // Find the new opcode for the updating load/store.
7799 bool IsStore = false;
7800 bool IsLaneOp = false;
7801 bool IsDupOp = false;
7802 unsigned NewOpc = 0;
7803 unsigned NumVecs = 0;
7804 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7806 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7807 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7809 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7811 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7813 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7814 NumVecs = 2; IsStore = true; break;
7815 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7816 NumVecs = 3; IsStore = true; break;
7817 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7818 NumVecs = 4; IsStore = true; break;
7819 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7821 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7823 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7825 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7826 NumVecs = 2; IsStore = true; break;
7827 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7828 NumVecs = 3; IsStore = true; break;
7829 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7830 NumVecs = 4; IsStore = true; break;
7831 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7832 NumVecs = 2; IsDupOp = true; break;
7833 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7834 NumVecs = 3; IsDupOp = true; break;
7835 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7836 NumVecs = 4; IsDupOp = true; break;
7837 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7838 NumVecs = 2; IsLaneOp = true; break;
7839 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7840 NumVecs = 3; IsLaneOp = true; break;
7841 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7842 NumVecs = 4; IsLaneOp = true; break;
7843 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7844 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7845 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7846 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7847 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7848 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7853 VecTy = N->getOperand(2).getValueType();
7855 VecTy = N->getValueType(0);
7857 // If the increment is a constant, it must match the memory ref size.
7858 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7859 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7860 uint32_t IncVal = CInc->getZExtValue();
7861 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7862 if (IsLaneOp || IsDupOp)
7863 NumBytes /= VecTy.getVectorNumElements();
7864 if (IncVal != NumBytes)
7866 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7868 SmallVector<SDValue, 8> Ops;
7869 Ops.push_back(N->getOperand(0)); // Incoming chain
7870 // Load lane and store have vector list as input.
7871 if (IsLaneOp || IsStore)
7872 for (unsigned i = 2; i < AddrOpIdx; ++i)
7873 Ops.push_back(N->getOperand(i));
7874 Ops.push_back(Addr); // Base register
7879 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7881 for (n = 0; n < NumResultVecs; ++n)
7883 Tys[n++] = MVT::i64; // Type of write back register
7884 Tys[n] = MVT::Other; // Type of the chain
7885 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
7887 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7888 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7889 MemInt->getMemoryVT(),
7890 MemInt->getMemOperand());
7893 std::vector<SDValue> NewResults;
7894 for (unsigned i = 0; i < NumResultVecs; ++i) {
7895 NewResults.push_back(SDValue(UpdN.getNode(), i));
7897 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7898 DCI.CombineTo(N, NewResults);
7899 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7906 // Optimize compare with zero and branch.
7907 static SDValue performBRCONDCombine(SDNode *N,
7908 TargetLowering::DAGCombinerInfo &DCI,
7909 SelectionDAG &DAG) {
7910 SDValue Chain = N->getOperand(0);
7911 SDValue Dest = N->getOperand(1);
7912 SDValue CCVal = N->getOperand(2);
7913 SDValue Cmp = N->getOperand(3);
7915 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7916 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7917 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7920 unsigned CmpOpc = Cmp.getOpcode();
7921 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7924 // Only attempt folding if there is only one use of the flag and no use of the
7926 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7929 SDValue LHS = Cmp.getOperand(0);
7930 SDValue RHS = Cmp.getOperand(1);
7932 assert(LHS.getValueType() == RHS.getValueType() &&
7933 "Expected the value type to be the same for both operands!");
7934 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7937 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7938 std::swap(LHS, RHS);
7940 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7943 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7944 LHS.getOpcode() == ISD::SRL)
7947 // Fold the compare into the branch instruction.
7949 if (CC == AArch64CC::EQ)
7950 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7952 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7954 // Do not add new nodes to DAG combiner worklist.
7955 DCI.CombineTo(N, BR, false);
7960 // vselect (v1i1 setcc) ->
7961 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7962 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7963 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7965 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7966 SDValue N0 = N->getOperand(0);
7967 EVT CCVT = N0.getValueType();
7969 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7970 CCVT.getVectorElementType() != MVT::i1)
7973 EVT ResVT = N->getValueType(0);
7974 EVT CmpVT = N0.getOperand(0).getValueType();
7975 // Only combine when the result type is of the same size as the compared
7977 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7980 SDValue IfTrue = N->getOperand(1);
7981 SDValue IfFalse = N->getOperand(2);
7983 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7984 N0.getOperand(0), N0.getOperand(1),
7985 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7986 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7990 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7991 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7992 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7993 /// with a vector one followed by a DUP shuffle on the result.
7994 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7995 SDValue N0 = N->getOperand(0);
7996 EVT ResVT = N->getValueType(0);
7997 EVT SrcVT = N0.getOperand(0).getValueType();
7998 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8000 // If NumMaskElts == 0, the comparison is larger than select result. The
8001 // largest real NEON comparison is 64-bits per lane, which means the result is
8002 // at most 32-bits and an illegal vector. Just bail out for now.
8003 if (!ResVT.isVector() || NumMaskElts == 0)
8006 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8009 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8010 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8012 // First perform a vector comparison, where lane 0 is the one we're interested
8016 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8018 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8019 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8021 // Now duplicate the comparison mask we want across all other lanes.
8022 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8023 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8024 Mask = DAG.getNode(ISD::BITCAST, DL,
8025 ResVT.changeVectorElementTypeToInteger(), Mask);
8027 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8030 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8031 DAGCombinerInfo &DCI) const {
8032 SelectionDAG &DAG = DCI.DAG;
8033 switch (N->getOpcode()) {
8038 return performAddSubLongCombine(N, DCI, DAG);
8040 return performXorCombine(N, DAG, DCI, Subtarget);
8042 return performMulCombine(N, DAG, DCI, Subtarget);
8043 case ISD::SINT_TO_FP:
8044 case ISD::UINT_TO_FP:
8045 return performIntToFpCombine(N, DAG);
8047 return performORCombine(N, DCI, Subtarget);
8048 case ISD::INTRINSIC_WO_CHAIN:
8049 return performIntrinsicCombine(N, DCI, Subtarget);
8050 case ISD::ANY_EXTEND:
8051 case ISD::ZERO_EXTEND:
8052 case ISD::SIGN_EXTEND:
8053 return performExtendCombine(N, DCI, DAG);
8055 return performBitcastCombine(N, DCI, DAG);
8056 case ISD::CONCAT_VECTORS:
8057 return performConcatVectorsCombine(N, DCI, DAG);
8059 return performSelectCombine(N, DAG);
8061 return performVSelectCombine(N, DCI.DAG);
8063 return performSTORECombine(N, DCI, DAG, Subtarget);
8064 case AArch64ISD::BRCOND:
8065 return performBRCONDCombine(N, DCI, DAG);
8066 case AArch64ISD::DUP:
8067 return performPostLD1Combine(N, DCI, false);
8068 case ISD::INSERT_VECTOR_ELT:
8069 return performPostLD1Combine(N, DCI, true);
8070 case ISD::INTRINSIC_VOID:
8071 case ISD::INTRINSIC_W_CHAIN:
8072 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8073 case Intrinsic::aarch64_neon_ld2:
8074 case Intrinsic::aarch64_neon_ld3:
8075 case Intrinsic::aarch64_neon_ld4:
8076 case Intrinsic::aarch64_neon_ld1x2:
8077 case Intrinsic::aarch64_neon_ld1x3:
8078 case Intrinsic::aarch64_neon_ld1x4:
8079 case Intrinsic::aarch64_neon_ld2lane:
8080 case Intrinsic::aarch64_neon_ld3lane:
8081 case Intrinsic::aarch64_neon_ld4lane:
8082 case Intrinsic::aarch64_neon_ld2r:
8083 case Intrinsic::aarch64_neon_ld3r:
8084 case Intrinsic::aarch64_neon_ld4r:
8085 case Intrinsic::aarch64_neon_st2:
8086 case Intrinsic::aarch64_neon_st3:
8087 case Intrinsic::aarch64_neon_st4:
8088 case Intrinsic::aarch64_neon_st1x2:
8089 case Intrinsic::aarch64_neon_st1x3:
8090 case Intrinsic::aarch64_neon_st1x4:
8091 case Intrinsic::aarch64_neon_st2lane:
8092 case Intrinsic::aarch64_neon_st3lane:
8093 case Intrinsic::aarch64_neon_st4lane:
8094 return performNEONPostLDSTCombine(N, DCI, DAG);
8102 // Check if the return value is used as only a return value, as otherwise
8103 // we can't perform a tail-call. In particular, we need to check for
8104 // target ISD nodes that are returns and any other "odd" constructs
8105 // that the generic analysis code won't necessarily catch.
8106 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8107 SDValue &Chain) const {
8108 if (N->getNumValues() != 1)
8110 if (!N->hasNUsesOfValue(1, 0))
8113 SDValue TCChain = Chain;
8114 SDNode *Copy = *N->use_begin();
8115 if (Copy->getOpcode() == ISD::CopyToReg) {
8116 // If the copy has a glue operand, we conservatively assume it isn't safe to
8117 // perform a tail call.
8118 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8121 TCChain = Copy->getOperand(0);
8122 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8125 bool HasRet = false;
8126 for (SDNode *Node : Copy->uses()) {
8127 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8139 // Return whether the an instruction can potentially be optimized to a tail
8140 // call. This will cause the optimizers to attempt to move, or duplicate,
8141 // return instructions to help enable tail call optimizations for this
8143 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8144 if (!CI->isTailCall())
8150 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8152 ISD::MemIndexedMode &AM,
8154 SelectionDAG &DAG) const {
8155 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8158 Base = Op->getOperand(0);
8159 // All of the indexed addressing mode instructions take a signed
8160 // 9 bit immediate offset.
8161 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8162 int64_t RHSC = (int64_t)RHS->getZExtValue();
8163 if (RHSC >= 256 || RHSC <= -256)
8165 IsInc = (Op->getOpcode() == ISD::ADD);
8166 Offset = Op->getOperand(1);
8172 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8174 ISD::MemIndexedMode &AM,
8175 SelectionDAG &DAG) const {
8178 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8179 VT = LD->getMemoryVT();
8180 Ptr = LD->getBasePtr();
8181 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8182 VT = ST->getMemoryVT();
8183 Ptr = ST->getBasePtr();
8188 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8190 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8194 bool AArch64TargetLowering::getPostIndexedAddressParts(
8195 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8196 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8199 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8200 VT = LD->getMemoryVT();
8201 Ptr = LD->getBasePtr();
8202 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8203 VT = ST->getMemoryVT();
8204 Ptr = ST->getBasePtr();
8209 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8211 // Post-indexing updates the base, so it's not a valid transform
8212 // if that's not the same as the load's pointer.
8215 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8219 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8220 SelectionDAG &DAG) {
8221 if (N->getValueType(0) != MVT::i16)
8225 SDValue Op = N->getOperand(0);
8226 assert(Op.getValueType() == MVT::f16 &&
8227 "Inconsistent bitcast? Only 16-bit types should be i16 or f16");
8229 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8230 DAG.getUNDEF(MVT::i32), Op,
8231 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8233 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8234 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8237 void AArch64TargetLowering::ReplaceNodeResults(
8238 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8239 switch (N->getOpcode()) {
8241 llvm_unreachable("Don't know how to custom expand this");
8243 ReplaceBITCASTResults(N, Results, DAG);
8245 case ISD::FP_TO_UINT:
8246 case ISD::FP_TO_SINT:
8247 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8248 // Let normal code take care of it by not adding anything to Results.
8253 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
8254 // Loads and stores less than 128-bits are already atomic; ones above that
8255 // are doomed anyway, so defer to the default libcall and blame the OS when
8257 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
8258 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
8259 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
8260 return LI->getType()->getPrimitiveSizeInBits() == 128;
8262 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
8263 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
8266 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8270 TargetLoweringBase::LegalizeTypeAction
8271 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8272 MVT SVT = VT.getSimpleVT();
8273 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8274 // v4i16, v2i32 instead of to promote.
8275 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8276 || SVT == MVT::v1f32)
8277 return TypeWidenVector;
8279 return TargetLoweringBase::getPreferredVectorAction(VT);
8282 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8283 AtomicOrdering Ord) const {
8284 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8285 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8286 bool IsAcquire = isAtLeastAcquire(Ord);
8288 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8289 // intrinsic must return {i64, i64} and we have to recombine them into a
8290 // single i128 here.
8291 if (ValTy->getPrimitiveSizeInBits() == 128) {
8293 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8294 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8296 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8297 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8299 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8300 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8301 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8302 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8303 return Builder.CreateOr(
8304 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8307 Type *Tys[] = { Addr->getType() };
8309 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8310 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8312 return Builder.CreateTruncOrBitCast(
8313 Builder.CreateCall(Ldxr, Addr),
8314 cast<PointerType>(Addr->getType())->getElementType());
8317 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8318 Value *Val, Value *Addr,
8319 AtomicOrdering Ord) const {
8320 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8321 bool IsRelease = isAtLeastRelease(Ord);
8323 // Since the intrinsics must have legal type, the i128 intrinsics take two
8324 // parameters: "i64, i64". We must marshal Val into the appropriate form
8326 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8328 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8329 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8330 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8332 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8333 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8334 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8335 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8339 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8340 Type *Tys[] = { Addr->getType() };
8341 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8343 return Builder.CreateCall2(
8344 Stxr, Builder.CreateZExtOrBitCast(
8345 Val, Stxr->getFunctionType()->getParamType(0)),