1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
71 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
72 : TargetLowering(TM) {
73 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
75 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
76 // we have to make something up. Arbitrarily, choose ZeroOrOne.
77 setBooleanContents(ZeroOrOneBooleanContent);
78 // When comparing vectors the result sets the different elements in the
79 // vector to all-one or all-zero.
80 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
82 // Set up the register classes.
83 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
84 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
86 if (Subtarget->hasFPARMv8()) {
87 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
88 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
89 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
90 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
93 if (Subtarget->hasNEON()) {
94 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
95 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
96 // Someone set us up the NEON.
97 addDRTypeForNEON(MVT::v2f32);
98 addDRTypeForNEON(MVT::v8i8);
99 addDRTypeForNEON(MVT::v4i16);
100 addDRTypeForNEON(MVT::v2i32);
101 addDRTypeForNEON(MVT::v1i64);
102 addDRTypeForNEON(MVT::v1f64);
103 addDRTypeForNEON(MVT::v4f16);
105 addQRTypeForNEON(MVT::v4f32);
106 addQRTypeForNEON(MVT::v2f64);
107 addQRTypeForNEON(MVT::v16i8);
108 addQRTypeForNEON(MVT::v8i16);
109 addQRTypeForNEON(MVT::v4i32);
110 addQRTypeForNEON(MVT::v2i64);
111 addQRTypeForNEON(MVT::v8f16);
114 // Compute derived properties from the register classes
115 computeRegisterProperties();
117 // Provide all sorts of operation actions
118 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
119 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
120 setOperationAction(ISD::SETCC, MVT::i32, Custom);
121 setOperationAction(ISD::SETCC, MVT::i64, Custom);
122 setOperationAction(ISD::SETCC, MVT::f32, Custom);
123 setOperationAction(ISD::SETCC, MVT::f64, Custom);
124 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
125 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
126 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
127 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
128 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
129 setOperationAction(ISD::SELECT, MVT::i32, Custom);
130 setOperationAction(ISD::SELECT, MVT::i64, Custom);
131 setOperationAction(ISD::SELECT, MVT::f32, Custom);
132 setOperationAction(ISD::SELECT, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
137 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
138 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
140 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
141 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
142 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
144 setOperationAction(ISD::FREM, MVT::f32, Expand);
145 setOperationAction(ISD::FREM, MVT::f64, Expand);
146 setOperationAction(ISD::FREM, MVT::f80, Expand);
148 // Custom lowering hooks are needed for XOR
149 // to fold it into CSINC/CSINV.
150 setOperationAction(ISD::XOR, MVT::i32, Custom);
151 setOperationAction(ISD::XOR, MVT::i64, Custom);
153 // Virtually no operation on f128 is legal, but LLVM can't expand them when
154 // there's a valid register class, so we need custom operations in most cases.
155 setOperationAction(ISD::FABS, MVT::f128, Expand);
156 setOperationAction(ISD::FADD, MVT::f128, Custom);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
158 setOperationAction(ISD::FCOS, MVT::f128, Expand);
159 setOperationAction(ISD::FDIV, MVT::f128, Custom);
160 setOperationAction(ISD::FMA, MVT::f128, Expand);
161 setOperationAction(ISD::FMUL, MVT::f128, Custom);
162 setOperationAction(ISD::FNEG, MVT::f128, Expand);
163 setOperationAction(ISD::FPOW, MVT::f128, Expand);
164 setOperationAction(ISD::FREM, MVT::f128, Expand);
165 setOperationAction(ISD::FRINT, MVT::f128, Expand);
166 setOperationAction(ISD::FSIN, MVT::f128, Expand);
167 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
168 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
169 setOperationAction(ISD::FSUB, MVT::f128, Custom);
170 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
171 setOperationAction(ISD::SETCC, MVT::f128, Custom);
172 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
173 setOperationAction(ISD::SELECT, MVT::f128, Custom);
174 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
175 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
177 // Lowering for many of the conversions is actually specified by the non-f128
178 // type. The LowerXXX function will be trivial when f128 isn't involved.
179 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
180 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
181 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
182 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
183 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
184 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
185 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
186 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
187 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
188 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
189 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
190 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
191 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
192 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
194 // Variable arguments.
195 setOperationAction(ISD::VASTART, MVT::Other, Custom);
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
197 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
198 setOperationAction(ISD::VAEND, MVT::Other, Expand);
200 // Variable-sized objects.
201 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
202 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
203 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
205 // Exception handling.
206 // FIXME: These are guesses. Has this been defined yet?
207 setExceptionPointerRegister(AArch64::X0);
208 setExceptionSelectorRegister(AArch64::X1);
210 // Constant pool entries
211 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
214 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
216 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
217 setOperationAction(ISD::ADDC, MVT::i32, Custom);
218 setOperationAction(ISD::ADDE, MVT::i32, Custom);
219 setOperationAction(ISD::SUBC, MVT::i32, Custom);
220 setOperationAction(ISD::SUBE, MVT::i32, Custom);
221 setOperationAction(ISD::ADDC, MVT::i64, Custom);
222 setOperationAction(ISD::ADDE, MVT::i64, Custom);
223 setOperationAction(ISD::SUBC, MVT::i64, Custom);
224 setOperationAction(ISD::SUBE, MVT::i64, Custom);
226 // AArch64 lacks both left-rotate and popcount instructions.
227 setOperationAction(ISD::ROTL, MVT::i32, Expand);
228 setOperationAction(ISD::ROTL, MVT::i64, Expand);
230 // AArch64 doesn't have {U|S}MUL_LOHI.
231 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
232 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
235 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
236 // counterparts, which AArch64 supports directly.
237 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
238 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
239 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
240 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
242 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
243 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
245 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
246 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
247 setOperationAction(ISD::SREM, MVT::i32, Expand);
248 setOperationAction(ISD::SREM, MVT::i64, Expand);
249 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::UREM, MVT::i32, Expand);
252 setOperationAction(ISD::UREM, MVT::i64, Expand);
254 // Custom lower Add/Sub/Mul with overflow.
255 setOperationAction(ISD::SADDO, MVT::i32, Custom);
256 setOperationAction(ISD::SADDO, MVT::i64, Custom);
257 setOperationAction(ISD::UADDO, MVT::i32, Custom);
258 setOperationAction(ISD::UADDO, MVT::i64, Custom);
259 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
260 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
261 setOperationAction(ISD::USUBO, MVT::i32, Custom);
262 setOperationAction(ISD::USUBO, MVT::i64, Custom);
263 setOperationAction(ISD::SMULO, MVT::i32, Custom);
264 setOperationAction(ISD::SMULO, MVT::i64, Custom);
265 setOperationAction(ISD::UMULO, MVT::i32, Custom);
266 setOperationAction(ISD::UMULO, MVT::i64, Custom);
268 setOperationAction(ISD::FSIN, MVT::f32, Expand);
269 setOperationAction(ISD::FSIN, MVT::f64, Expand);
270 setOperationAction(ISD::FCOS, MVT::f32, Expand);
271 setOperationAction(ISD::FCOS, MVT::f64, Expand);
272 setOperationAction(ISD::FPOW, MVT::f32, Expand);
273 setOperationAction(ISD::FPOW, MVT::f64, Expand);
274 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
275 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
277 // f16 is storage-only, so we promote operations to f32 if we know this is
278 // valid, and ignore them otherwise. The operations not mentioned here will
279 // fail to select, but this is not a major problem as no source language
280 // should be emitting native f16 operations yet.
281 setOperationAction(ISD::FADD, MVT::f16, Promote);
282 setOperationAction(ISD::FDIV, MVT::f16, Promote);
283 setOperationAction(ISD::FMUL, MVT::f16, Promote);
284 setOperationAction(ISD::FSUB, MVT::f16, Promote);
286 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
288 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
289 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
290 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
291 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
292 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
293 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
294 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
295 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
296 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
297 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
298 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
299 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
301 // Expand all other v4f16 operations.
302 // FIXME: We could generate better code by promoting some operations to
304 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
305 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
306 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
307 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
308 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
309 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
311 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
312 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
313 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
314 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
315 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
316 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
317 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
318 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
319 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
320 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
321 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
322 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
323 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
324 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
325 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
326 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
327 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
328 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
329 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
332 // v8f16 is also a storage-only type, so expand it.
333 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
334 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
335 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
336 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
337 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
338 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
339 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
340 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
341 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
342 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
343 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
344 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
345 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
346 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
347 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
348 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
349 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
350 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
351 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
352 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
353 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
354 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
355 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
356 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
357 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
358 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
359 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
360 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
361 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
362 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
363 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
365 // AArch64 has implementations of a lot of rounding-like FP operations.
366 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
367 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
368 MVT Ty = RoundingTypes[I];
369 setOperationAction(ISD::FFLOOR, Ty, Legal);
370 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
371 setOperationAction(ISD::FCEIL, Ty, Legal);
372 setOperationAction(ISD::FRINT, Ty, Legal);
373 setOperationAction(ISD::FTRUNC, Ty, Legal);
374 setOperationAction(ISD::FROUND, Ty, Legal);
377 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
379 if (Subtarget->isTargetMachO()) {
380 // For iOS, we don't want to the normal expansion of a libcall to
381 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
383 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
384 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
386 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
387 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
390 // AArch64 does not have floating-point extending loads, i1 sign-extending
391 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
392 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
393 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
394 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
395 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
396 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
397 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
398 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
399 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
400 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
401 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
402 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
403 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
405 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
406 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
408 // Indexed loads and stores are supported.
409 for (unsigned im = (unsigned)ISD::PRE_INC;
410 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
411 setIndexedLoadAction(im, MVT::i8, Legal);
412 setIndexedLoadAction(im, MVT::i16, Legal);
413 setIndexedLoadAction(im, MVT::i32, Legal);
414 setIndexedLoadAction(im, MVT::i64, Legal);
415 setIndexedLoadAction(im, MVT::f64, Legal);
416 setIndexedLoadAction(im, MVT::f32, Legal);
417 setIndexedStoreAction(im, MVT::i8, Legal);
418 setIndexedStoreAction(im, MVT::i16, Legal);
419 setIndexedStoreAction(im, MVT::i32, Legal);
420 setIndexedStoreAction(im, MVT::i64, Legal);
421 setIndexedStoreAction(im, MVT::f64, Legal);
422 setIndexedStoreAction(im, MVT::f32, Legal);
426 setOperationAction(ISD::TRAP, MVT::Other, Legal);
428 // We combine OR nodes for bitfield operations.
429 setTargetDAGCombine(ISD::OR);
431 // Vector add and sub nodes may conceal a high-half opportunity.
432 // Also, try to fold ADD into CSINC/CSINV..
433 setTargetDAGCombine(ISD::ADD);
434 setTargetDAGCombine(ISD::SUB);
436 setTargetDAGCombine(ISD::XOR);
437 setTargetDAGCombine(ISD::SINT_TO_FP);
438 setTargetDAGCombine(ISD::UINT_TO_FP);
440 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
442 setTargetDAGCombine(ISD::ANY_EXTEND);
443 setTargetDAGCombine(ISD::ZERO_EXTEND);
444 setTargetDAGCombine(ISD::SIGN_EXTEND);
445 setTargetDAGCombine(ISD::BITCAST);
446 setTargetDAGCombine(ISD::CONCAT_VECTORS);
447 setTargetDAGCombine(ISD::STORE);
449 setTargetDAGCombine(ISD::MUL);
451 setTargetDAGCombine(ISD::SELECT);
452 setTargetDAGCombine(ISD::VSELECT);
454 setTargetDAGCombine(ISD::INTRINSIC_VOID);
455 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
456 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
458 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
459 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
460 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
462 setStackPointerRegisterToSaveRestore(AArch64::SP);
464 setSchedulingPreference(Sched::Hybrid);
467 MaskAndBranchFoldingIsLegal = true;
469 setMinFunctionAlignment(2);
471 RequireStrictAlign = (Align == StrictAlign);
473 setHasExtractBitsInsn(true);
475 if (Subtarget->hasNEON()) {
476 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
477 // silliness like this:
478 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
479 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
480 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
481 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
482 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
483 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
484 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
485 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
486 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
487 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
488 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
489 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
490 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
491 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
492 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
493 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
494 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
495 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
496 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
497 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
498 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
499 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
500 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
501 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
502 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
504 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
505 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
506 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
507 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
508 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
510 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
512 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
513 // elements smaller than i32, so promote the input to i32 first.
514 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
515 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
516 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
517 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
518 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
519 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
520 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
521 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
522 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
524 // AArch64 doesn't have MUL.2d:
525 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
526 // Custom handling for some quad-vector types to detect MULL.
527 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
528 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
529 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
531 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
532 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
533 // Likewise, narrowing and extending vector loads/stores aren't handled
535 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
536 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
538 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
541 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
548 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
550 setTruncStoreAction((MVT::SimpleValueType)VT,
551 (MVT::SimpleValueType)InnerVT, Expand);
552 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
553 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
554 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
557 // AArch64 has implementations of a lot of rounding-like FP operations.
558 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
559 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
560 MVT Ty = RoundingVecTypes[I];
561 setOperationAction(ISD::FFLOOR, Ty, Legal);
562 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
563 setOperationAction(ISD::FCEIL, Ty, Legal);
564 setOperationAction(ISD::FRINT, Ty, Legal);
565 setOperationAction(ISD::FTRUNC, Ty, Legal);
566 setOperationAction(ISD::FROUND, Ty, Legal);
570 // Prefer likely predicted branches to selects on out-of-order cores.
571 if (Subtarget->isCortexA57())
572 PredictableSelectIsExpensive = true;
575 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
576 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
577 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
578 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
580 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
581 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
582 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
583 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
584 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
586 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
587 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
590 // Mark vector float intrinsics as expand.
591 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
592 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
593 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
594 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
595 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
596 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
597 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
598 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
599 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
600 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
603 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
604 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
605 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
606 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
607 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
608 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
609 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
610 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
611 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
612 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
613 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
614 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
616 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
617 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
618 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
619 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
621 // CNT supports only B element sizes.
622 if (VT != MVT::v8i8 && VT != MVT::v16i8)
623 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
625 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
626 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
627 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
632 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
634 if (Subtarget->isLittleEndian()) {
635 for (unsigned im = (unsigned)ISD::PRE_INC;
636 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
637 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
638 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
643 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
644 addRegisterClass(VT, &AArch64::FPR64RegClass);
645 addTypeForNEON(VT, MVT::v2i32);
648 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
649 addRegisterClass(VT, &AArch64::FPR128RegClass);
650 addTypeForNEON(VT, MVT::v4i32);
653 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
656 return VT.changeVectorElementTypeToInteger();
659 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
660 /// Mask are known to be either zero or one and return them in the
661 /// KnownZero/KnownOne bitsets.
662 void AArch64TargetLowering::computeKnownBitsForTargetNode(
663 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
664 const SelectionDAG &DAG, unsigned Depth) const {
665 switch (Op.getOpcode()) {
668 case AArch64ISD::CSEL: {
669 APInt KnownZero2, KnownOne2;
670 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
671 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
672 KnownZero &= KnownZero2;
673 KnownOne &= KnownOne2;
676 case ISD::INTRINSIC_W_CHAIN: {
677 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
678 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
681 case Intrinsic::aarch64_ldaxr:
682 case Intrinsic::aarch64_ldxr: {
683 unsigned BitWidth = KnownOne.getBitWidth();
684 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
685 unsigned MemBits = VT.getScalarType().getSizeInBits();
686 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
692 case ISD::INTRINSIC_WO_CHAIN:
693 case ISD::INTRINSIC_VOID: {
694 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
698 case Intrinsic::aarch64_neon_umaxv:
699 case Intrinsic::aarch64_neon_uminv: {
700 // Figure out the datatype of the vector operand. The UMINV instruction
701 // will zero extend the result, so we can mark as known zero all the
702 // bits larger than the element datatype. 32-bit or larget doesn't need
703 // this as those are legal types and will be handled by isel directly.
704 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
705 unsigned BitWidth = KnownZero.getBitWidth();
706 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
707 assert(BitWidth >= 8 && "Unexpected width!");
708 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
710 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
711 assert(BitWidth >= 16 && "Unexpected width!");
712 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
722 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
726 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
727 // FIXME: On AArch64, this depends on the type.
728 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
729 // and the offset has to be a multiple of the related size in bytes.
734 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
735 const TargetLibraryInfo *libInfo) const {
736 return AArch64::createFastISel(funcInfo, libInfo);
739 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
743 case AArch64ISD::CALL: return "AArch64ISD::CALL";
744 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
745 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
746 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
747 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
748 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
749 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
750 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
751 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
752 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
753 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
754 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
755 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
756 case AArch64ISD::ADC: return "AArch64ISD::ADC";
757 case AArch64ISD::SBC: return "AArch64ISD::SBC";
758 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
759 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
760 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
761 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
762 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
763 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
764 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
765 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
766 case AArch64ISD::DUP: return "AArch64ISD::DUP";
767 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
768 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
769 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
770 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
771 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
772 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
773 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
774 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
775 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
776 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
777 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
778 case AArch64ISD::BICi: return "AArch64ISD::BICi";
779 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
780 case AArch64ISD::BSL: return "AArch64ISD::BSL";
781 case AArch64ISD::NEG: return "AArch64ISD::NEG";
782 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
783 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
784 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
785 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
786 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
787 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
788 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
789 case AArch64ISD::REV16: return "AArch64ISD::REV16";
790 case AArch64ISD::REV32: return "AArch64ISD::REV32";
791 case AArch64ISD::REV64: return "AArch64ISD::REV64";
792 case AArch64ISD::EXT: return "AArch64ISD::EXT";
793 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
794 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
795 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
796 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
797 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
798 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
799 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
800 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
801 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
802 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
803 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
804 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
805 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
806 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
807 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
808 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
809 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
810 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
811 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
812 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
813 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
814 case AArch64ISD::NOT: return "AArch64ISD::NOT";
815 case AArch64ISD::BIT: return "AArch64ISD::BIT";
816 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
817 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
818 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
819 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
820 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
821 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
822 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
823 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
824 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
825 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
826 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
827 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
828 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
829 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
830 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
831 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
832 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
833 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
834 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
835 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
836 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
837 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
838 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
839 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
840 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
841 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
842 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
843 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
844 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
845 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
846 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
847 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
848 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
849 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
850 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
851 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
852 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
853 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
854 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
859 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
860 MachineBasicBlock *MBB) const {
861 // We materialise the F128CSEL pseudo-instruction as some control flow and a
865 // [... previous instrs leading to comparison ...]
871 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
873 const TargetInstrInfo *TII =
874 getTargetMachine().getSubtargetImpl()->getInstrInfo();
875 MachineFunction *MF = MBB->getParent();
876 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
877 DebugLoc DL = MI->getDebugLoc();
878 MachineFunction::iterator It = MBB;
881 unsigned DestReg = MI->getOperand(0).getReg();
882 unsigned IfTrueReg = MI->getOperand(1).getReg();
883 unsigned IfFalseReg = MI->getOperand(2).getReg();
884 unsigned CondCode = MI->getOperand(3).getImm();
885 bool NZCVKilled = MI->getOperand(4).isKill();
887 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
888 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
889 MF->insert(It, TrueBB);
890 MF->insert(It, EndBB);
892 // Transfer rest of current basic-block to EndBB
893 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
895 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
897 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
898 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
899 MBB->addSuccessor(TrueBB);
900 MBB->addSuccessor(EndBB);
902 // TrueBB falls through to the end.
903 TrueBB->addSuccessor(EndBB);
906 TrueBB->addLiveIn(AArch64::NZCV);
907 EndBB->addLiveIn(AArch64::NZCV);
910 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
916 MI->eraseFromParent();
921 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
922 MachineBasicBlock *BB) const {
923 switch (MI->getOpcode()) {
928 llvm_unreachable("Unexpected instruction for custom inserter!");
930 case AArch64::F128CSEL:
931 return EmitF128CSEL(MI, BB);
933 case TargetOpcode::STACKMAP:
934 case TargetOpcode::PATCHPOINT:
935 return emitPatchPoint(MI, BB);
939 //===----------------------------------------------------------------------===//
940 // AArch64 Lowering private implementation.
941 //===----------------------------------------------------------------------===//
943 //===----------------------------------------------------------------------===//
945 //===----------------------------------------------------------------------===//
947 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
949 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
952 llvm_unreachable("Unknown condition code!");
954 return AArch64CC::NE;
956 return AArch64CC::EQ;
958 return AArch64CC::GT;
960 return AArch64CC::GE;
962 return AArch64CC::LT;
964 return AArch64CC::LE;
966 return AArch64CC::HI;
968 return AArch64CC::HS;
970 return AArch64CC::LO;
972 return AArch64CC::LS;
976 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
977 static void changeFPCCToAArch64CC(ISD::CondCode CC,
978 AArch64CC::CondCode &CondCode,
979 AArch64CC::CondCode &CondCode2) {
980 CondCode2 = AArch64CC::AL;
983 llvm_unreachable("Unknown FP condition!");
986 CondCode = AArch64CC::EQ;
990 CondCode = AArch64CC::GT;
994 CondCode = AArch64CC::GE;
997 CondCode = AArch64CC::MI;
1000 CondCode = AArch64CC::LS;
1003 CondCode = AArch64CC::MI;
1004 CondCode2 = AArch64CC::GT;
1007 CondCode = AArch64CC::VC;
1010 CondCode = AArch64CC::VS;
1013 CondCode = AArch64CC::EQ;
1014 CondCode2 = AArch64CC::VS;
1017 CondCode = AArch64CC::HI;
1020 CondCode = AArch64CC::PL;
1024 CondCode = AArch64CC::LT;
1028 CondCode = AArch64CC::LE;
1032 CondCode = AArch64CC::NE;
1037 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1038 /// CC usable with the vector instructions. Fewer operations are available
1039 /// without a real NZCV register, so we have to use less efficient combinations
1040 /// to get the same effect.
1041 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1042 AArch64CC::CondCode &CondCode,
1043 AArch64CC::CondCode &CondCode2,
1048 // Mostly the scalar mappings work fine.
1049 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1052 Invert = true; // Fallthrough
1054 CondCode = AArch64CC::MI;
1055 CondCode2 = AArch64CC::GE;
1062 // All of the compare-mask comparisons are ordered, but we can switch
1063 // between the two by a double inversion. E.g. ULE == !OGT.
1065 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1070 static bool isLegalArithImmed(uint64_t C) {
1071 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1072 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1075 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1076 SDLoc dl, SelectionDAG &DAG) {
1077 EVT VT = LHS.getValueType();
1079 if (VT.isFloatingPoint())
1080 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1082 // The CMP instruction is just an alias for SUBS, and representing it as
1083 // SUBS means that it's possible to get CSE with subtract operations.
1084 // A later phase can perform the optimization of setting the destination
1085 // register to WZR/XZR if it ends up being unused.
1086 unsigned Opcode = AArch64ISD::SUBS;
1088 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1089 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1090 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1091 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1092 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1093 // can be set differently by this operation. It comes down to whether
1094 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1095 // everything is fine. If not then the optimization is wrong. Thus general
1096 // comparisons are only valid if op2 != 0.
1098 // So, finally, the only LLVM-native comparisons that don't mention C and V
1099 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1100 // the absence of information about op2.
1101 Opcode = AArch64ISD::ADDS;
1102 RHS = RHS.getOperand(1);
1103 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1104 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1105 !isUnsignedIntSetCC(CC)) {
1106 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1107 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1108 // of the signed comparisons.
1109 Opcode = AArch64ISD::ANDS;
1110 RHS = LHS.getOperand(1);
1111 LHS = LHS.getOperand(0);
1114 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1118 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1119 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1121 AArch64CC::CondCode AArch64CC;
1122 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1123 EVT VT = RHS.getValueType();
1124 uint64_t C = RHSC->getZExtValue();
1125 if (!isLegalArithImmed(C)) {
1126 // Constant does not fit, try adjusting it by one?
1132 if ((VT == MVT::i32 && C != 0x80000000 &&
1133 isLegalArithImmed((uint32_t)(C - 1))) ||
1134 (VT == MVT::i64 && C != 0x80000000ULL &&
1135 isLegalArithImmed(C - 1ULL))) {
1136 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1137 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1138 RHS = DAG.getConstant(C, VT);
1143 if ((VT == MVT::i32 && C != 0 &&
1144 isLegalArithImmed((uint32_t)(C - 1))) ||
1145 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1146 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1147 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1148 RHS = DAG.getConstant(C, VT);
1153 if ((VT == MVT::i32 && C != INT32_MAX &&
1154 isLegalArithImmed((uint32_t)(C + 1))) ||
1155 (VT == MVT::i64 && C != INT64_MAX &&
1156 isLegalArithImmed(C + 1ULL))) {
1157 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1158 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1159 RHS = DAG.getConstant(C, VT);
1164 if ((VT == MVT::i32 && C != UINT32_MAX &&
1165 isLegalArithImmed((uint32_t)(C + 1))) ||
1166 (VT == MVT::i64 && C != UINT64_MAX &&
1167 isLegalArithImmed(C + 1ULL))) {
1168 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1169 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1170 RHS = DAG.getConstant(C, VT);
1176 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1177 // For the i8 operand, the largest immediate is 255, so this can be easily
1178 // encoded in the compare instruction. For the i16 operand, however, the
1179 // largest immediate cannot be encoded in the compare.
1180 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1181 // constant. For example,
1183 // ldrh w0, [x0, #0]
1186 // ldrsh w0, [x0, #0]
1188 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1189 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1190 // both the LHS and RHS are truely zero extended and to make sure the
1191 // transformation is profitable.
1192 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1193 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1194 isa<LoadSDNode>(LHS)) {
1195 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1196 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1197 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1198 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1199 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1201 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1202 DAG.getValueType(MVT::i16));
1203 Cmp = emitComparison(SExt,
1204 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1206 AArch64CC = changeIntCCToAArch64CC(CC);
1207 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1213 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1214 AArch64CC = changeIntCCToAArch64CC(CC);
1215 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1219 static std::pair<SDValue, SDValue>
1220 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1221 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1222 "Unsupported value type");
1223 SDValue Value, Overflow;
1225 SDValue LHS = Op.getOperand(0);
1226 SDValue RHS = Op.getOperand(1);
1228 switch (Op.getOpcode()) {
1230 llvm_unreachable("Unknown overflow instruction!");
1232 Opc = AArch64ISD::ADDS;
1236 Opc = AArch64ISD::ADDS;
1240 Opc = AArch64ISD::SUBS;
1244 Opc = AArch64ISD::SUBS;
1247 // Multiply needs a little bit extra work.
1251 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1252 if (Op.getValueType() == MVT::i32) {
1253 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1254 // For a 32 bit multiply with overflow check we want the instruction
1255 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1256 // need to generate the following pattern:
1257 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1258 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1259 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1260 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1261 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1262 DAG.getConstant(0, MVT::i64));
1263 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1264 // operation. We need to clear out the upper 32 bits, because we used a
1265 // widening multiply that wrote all 64 bits. In the end this should be a
1267 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1269 // The signed overflow check requires more than just a simple check for
1270 // any bit set in the upper 32 bits of the result. These bits could be
1271 // just the sign bits of a negative number. To perform the overflow
1272 // check we have to arithmetic shift right the 32nd bit of the result by
1273 // 31 bits. Then we compare the result to the upper 32 bits.
1274 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1275 DAG.getConstant(32, MVT::i64));
1276 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1277 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1278 DAG.getConstant(31, MVT::i64));
1279 // It is important that LowerBits is last, otherwise the arithmetic
1280 // shift will not be folded into the compare (SUBS).
1281 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1282 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1285 // The overflow check for unsigned multiply is easy. We only need to
1286 // check if any of the upper 32 bits are set. This can be done with a
1287 // CMP (shifted register). For that we need to generate the following
1289 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1290 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1291 DAG.getConstant(32, MVT::i64));
1292 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1294 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1295 UpperBits).getValue(1);
1299 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1300 // For the 64 bit multiply
1301 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1303 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1304 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1305 DAG.getConstant(63, MVT::i64));
1306 // It is important that LowerBits is last, otherwise the arithmetic
1307 // shift will not be folded into the compare (SUBS).
1308 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1309 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1312 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1313 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1315 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1316 UpperBits).getValue(1);
1323 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1325 // Emit the AArch64 operation with overflow check.
1326 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1327 Overflow = Value.getValue(1);
1329 return std::make_pair(Value, Overflow);
1332 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1333 RTLIB::Libcall Call) const {
1334 SmallVector<SDValue, 2> Ops;
1335 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1336 Ops.push_back(Op.getOperand(i));
1338 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1342 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1343 SDValue Sel = Op.getOperand(0);
1344 SDValue Other = Op.getOperand(1);
1346 // If neither operand is a SELECT_CC, give up.
1347 if (Sel.getOpcode() != ISD::SELECT_CC)
1348 std::swap(Sel, Other);
1349 if (Sel.getOpcode() != ISD::SELECT_CC)
1352 // The folding we want to perform is:
1353 // (xor x, (select_cc a, b, cc, 0, -1) )
1355 // (csel x, (xor x, -1), cc ...)
1357 // The latter will get matched to a CSINV instruction.
1359 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1360 SDValue LHS = Sel.getOperand(0);
1361 SDValue RHS = Sel.getOperand(1);
1362 SDValue TVal = Sel.getOperand(2);
1363 SDValue FVal = Sel.getOperand(3);
1366 // FIXME: This could be generalized to non-integer comparisons.
1367 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1370 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1371 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1373 // The the values aren't constants, this isn't the pattern we're looking for.
1374 if (!CFVal || !CTVal)
1377 // We can commute the SELECT_CC by inverting the condition. This
1378 // might be needed to make this fit into a CSINV pattern.
1379 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1380 std::swap(TVal, FVal);
1381 std::swap(CTVal, CFVal);
1382 CC = ISD::getSetCCInverse(CC, true);
1385 // If the constants line up, perform the transform!
1386 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1388 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1391 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1392 DAG.getConstant(-1ULL, Other.getValueType()));
1394 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1401 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1402 EVT VT = Op.getValueType();
1404 // Let legalize expand this if it isn't a legal type yet.
1405 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1408 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1411 bool ExtraOp = false;
1412 switch (Op.getOpcode()) {
1414 llvm_unreachable("Invalid code");
1416 Opc = AArch64ISD::ADDS;
1419 Opc = AArch64ISD::SUBS;
1422 Opc = AArch64ISD::ADCS;
1426 Opc = AArch64ISD::SBCS;
1432 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1433 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1437 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1438 // Let legalize expand this if it isn't a legal type yet.
1439 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1442 AArch64CC::CondCode CC;
1443 // The actual operation that sets the overflow or carry flag.
1444 SDValue Value, Overflow;
1445 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1447 // We use 0 and 1 as false and true values.
1448 SDValue TVal = DAG.getConstant(1, MVT::i32);
1449 SDValue FVal = DAG.getConstant(0, MVT::i32);
1451 // We use an inverted condition, because the conditional select is inverted
1452 // too. This will allow it to be selected to a single instruction:
1453 // CSINC Wd, WZR, WZR, invert(cond).
1454 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1455 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1458 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1459 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1462 // Prefetch operands are:
1463 // 1: Address to prefetch
1465 // 3: int locality (0 = no locality ... 3 = extreme locality)
1466 // 4: bool isDataCache
1467 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1469 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1470 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1471 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1473 bool IsStream = !Locality;
1474 // When the locality number is set
1476 // The front-end should have filtered out the out-of-range values
1477 assert(Locality <= 3 && "Prefetch locality out-of-range");
1478 // The locality degree is the opposite of the cache speed.
1479 // Put the number the other way around.
1480 // The encoding starts at 0 for level 1
1481 Locality = 3 - Locality;
1484 // built the mask value encoding the expected behavior.
1485 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1486 (!IsData << 3) | // IsDataCache bit
1487 (Locality << 1) | // Cache level bits
1488 (unsigned)IsStream; // Stream bit
1489 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1490 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1493 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1494 SelectionDAG &DAG) const {
1495 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1498 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1500 return LowerF128Call(Op, DAG, LC);
1503 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1504 SelectionDAG &DAG) const {
1505 if (Op.getOperand(0).getValueType() != MVT::f128) {
1506 // It's legal except when f128 is involved
1511 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1513 // FP_ROUND node has a second operand indicating whether it is known to be
1514 // precise. That doesn't take part in the LibCall so we can't directly use
1516 SDValue SrcVal = Op.getOperand(0);
1517 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1518 /*isSigned*/ false, SDLoc(Op)).first;
1521 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1522 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1523 // Any additional optimization in this function should be recorded
1524 // in the cost tables.
1525 EVT InVT = Op.getOperand(0).getValueType();
1526 EVT VT = Op.getValueType();
1528 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1531 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1533 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1536 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1539 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1540 VT.getVectorNumElements());
1541 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1542 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1545 // Type changing conversions are illegal.
1549 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1550 SelectionDAG &DAG) const {
1551 if (Op.getOperand(0).getValueType().isVector())
1552 return LowerVectorFP_TO_INT(Op, DAG);
1554 if (Op.getOperand(0).getValueType() != MVT::f128) {
1555 // It's legal except when f128 is involved
1560 if (Op.getOpcode() == ISD::FP_TO_SINT)
1561 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1563 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1565 SmallVector<SDValue, 2> Ops;
1566 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1567 Ops.push_back(Op.getOperand(i));
1569 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1573 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1574 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1575 // Any additional optimization in this function should be recorded
1576 // in the cost tables.
1577 EVT VT = Op.getValueType();
1579 SDValue In = Op.getOperand(0);
1580 EVT InVT = In.getValueType();
1582 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1584 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1585 InVT.getVectorNumElements());
1586 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1587 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1590 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1592 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1593 EVT CastVT = VT.changeVectorElementTypeToInteger();
1594 In = DAG.getNode(CastOpc, dl, CastVT, In);
1595 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1601 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1602 SelectionDAG &DAG) const {
1603 if (Op.getValueType().isVector())
1604 return LowerVectorINT_TO_FP(Op, DAG);
1606 // i128 conversions are libcalls.
1607 if (Op.getOperand(0).getValueType() == MVT::i128)
1610 // Other conversions are legal, unless it's to the completely software-based
1612 if (Op.getValueType() != MVT::f128)
1616 if (Op.getOpcode() == ISD::SINT_TO_FP)
1617 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1619 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1621 return LowerF128Call(Op, DAG, LC);
1624 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1625 SelectionDAG &DAG) const {
1626 // For iOS, we want to call an alternative entry point: __sincos_stret,
1627 // which returns the values in two S / D registers.
1629 SDValue Arg = Op.getOperand(0);
1630 EVT ArgVT = Arg.getValueType();
1631 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1638 Entry.isSExt = false;
1639 Entry.isZExt = false;
1640 Args.push_back(Entry);
1642 const char *LibcallName =
1643 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1644 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1646 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1647 TargetLowering::CallLoweringInfo CLI(DAG);
1648 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1649 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1651 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1652 return CallResult.first;
1655 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1656 if (Op.getValueType() != MVT::f16)
1659 assert(Op.getOperand(0).getValueType() == MVT::i16);
1662 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1663 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1665 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1666 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1670 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1671 if (OrigVT.getSizeInBits() >= 64)
1674 assert(OrigVT.isSimple() && "Expecting a simple value type");
1676 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1677 switch (OrigSimpleTy) {
1678 default: llvm_unreachable("Unexpected Vector Type");
1687 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1690 unsigned ExtOpcode) {
1691 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1692 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1693 // 64-bits we need to insert a new extension so that it will be 64-bits.
1694 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1695 if (OrigTy.getSizeInBits() >= 64)
1698 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1699 EVT NewVT = getExtensionTo64Bits(OrigTy);
1701 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1704 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1706 EVT VT = N->getValueType(0);
1708 if (N->getOpcode() != ISD::BUILD_VECTOR)
1711 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1712 SDNode *Elt = N->getOperand(i).getNode();
1713 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1714 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1715 unsigned HalfSize = EltSize / 2;
1717 if (!isIntN(HalfSize, C->getSExtValue()))
1720 if (!isUIntN(HalfSize, C->getZExtValue()))
1731 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1732 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1733 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1734 N->getOperand(0)->getValueType(0),
1738 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1739 EVT VT = N->getValueType(0);
1740 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1741 unsigned NumElts = VT.getVectorNumElements();
1742 MVT TruncVT = MVT::getIntegerVT(EltSize);
1743 SmallVector<SDValue, 8> Ops;
1744 for (unsigned i = 0; i != NumElts; ++i) {
1745 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1746 const APInt &CInt = C->getAPIntValue();
1747 // Element types smaller than 32 bits are not legal, so use i32 elements.
1748 // The values are implicitly truncated so sext vs. zext doesn't matter.
1749 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1751 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1752 MVT::getVectorVT(TruncVT, NumElts), Ops);
1755 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1756 if (N->getOpcode() == ISD::SIGN_EXTEND)
1758 if (isExtendedBUILD_VECTOR(N, DAG, true))
1763 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1764 if (N->getOpcode() == ISD::ZERO_EXTEND)
1766 if (isExtendedBUILD_VECTOR(N, DAG, false))
1771 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1772 unsigned Opcode = N->getOpcode();
1773 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1774 SDNode *N0 = N->getOperand(0).getNode();
1775 SDNode *N1 = N->getOperand(1).getNode();
1776 return N0->hasOneUse() && N1->hasOneUse() &&
1777 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1782 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1783 unsigned Opcode = N->getOpcode();
1784 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1785 SDNode *N0 = N->getOperand(0).getNode();
1786 SDNode *N1 = N->getOperand(1).getNode();
1787 return N0->hasOneUse() && N1->hasOneUse() &&
1788 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1793 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1794 // Multiplications are only custom-lowered for 128-bit vectors so that
1795 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1796 EVT VT = Op.getValueType();
1797 assert(VT.is128BitVector() && VT.isInteger() &&
1798 "unexpected type for custom-lowering ISD::MUL");
1799 SDNode *N0 = Op.getOperand(0).getNode();
1800 SDNode *N1 = Op.getOperand(1).getNode();
1801 unsigned NewOpc = 0;
1803 bool isN0SExt = isSignExtended(N0, DAG);
1804 bool isN1SExt = isSignExtended(N1, DAG);
1805 if (isN0SExt && isN1SExt)
1806 NewOpc = AArch64ISD::SMULL;
1808 bool isN0ZExt = isZeroExtended(N0, DAG);
1809 bool isN1ZExt = isZeroExtended(N1, DAG);
1810 if (isN0ZExt && isN1ZExt)
1811 NewOpc = AArch64ISD::UMULL;
1812 else if (isN1SExt || isN1ZExt) {
1813 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1814 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1815 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1816 NewOpc = AArch64ISD::SMULL;
1818 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1819 NewOpc = AArch64ISD::UMULL;
1821 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1823 NewOpc = AArch64ISD::UMULL;
1829 if (VT == MVT::v2i64)
1830 // Fall through to expand this. It is not legal.
1833 // Other vector multiplications are legal.
1838 // Legalize to a S/UMULL instruction
1841 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1843 Op0 = skipExtensionForVectorMULL(N0, DAG);
1844 assert(Op0.getValueType().is64BitVector() &&
1845 Op1.getValueType().is64BitVector() &&
1846 "unexpected types for extended operands to VMULL");
1847 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1849 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1850 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1851 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1852 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1853 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1854 EVT Op1VT = Op1.getValueType();
1855 return DAG.getNode(N0->getOpcode(), DL, VT,
1856 DAG.getNode(NewOpc, DL, VT,
1857 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1858 DAG.getNode(NewOpc, DL, VT,
1859 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1862 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1863 SelectionDAG &DAG) const {
1864 switch (Op.getOpcode()) {
1866 llvm_unreachable("unimplemented operand");
1869 return LowerBITCAST(Op, DAG);
1870 case ISD::GlobalAddress:
1871 return LowerGlobalAddress(Op, DAG);
1872 case ISD::GlobalTLSAddress:
1873 return LowerGlobalTLSAddress(Op, DAG);
1875 return LowerSETCC(Op, DAG);
1877 return LowerBR_CC(Op, DAG);
1879 return LowerSELECT(Op, DAG);
1880 case ISD::SELECT_CC:
1881 return LowerSELECT_CC(Op, DAG);
1882 case ISD::JumpTable:
1883 return LowerJumpTable(Op, DAG);
1884 case ISD::ConstantPool:
1885 return LowerConstantPool(Op, DAG);
1886 case ISD::BlockAddress:
1887 return LowerBlockAddress(Op, DAG);
1889 return LowerVASTART(Op, DAG);
1891 return LowerVACOPY(Op, DAG);
1893 return LowerVAARG(Op, DAG);
1898 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1905 return LowerXALUO(Op, DAG);
1907 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1909 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1911 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1913 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1915 return LowerFP_ROUND(Op, DAG);
1916 case ISD::FP_EXTEND:
1917 return LowerFP_EXTEND(Op, DAG);
1918 case ISD::FRAMEADDR:
1919 return LowerFRAMEADDR(Op, DAG);
1920 case ISD::RETURNADDR:
1921 return LowerRETURNADDR(Op, DAG);
1922 case ISD::INSERT_VECTOR_ELT:
1923 return LowerINSERT_VECTOR_ELT(Op, DAG);
1924 case ISD::EXTRACT_VECTOR_ELT:
1925 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1926 case ISD::BUILD_VECTOR:
1927 return LowerBUILD_VECTOR(Op, DAG);
1928 case ISD::VECTOR_SHUFFLE:
1929 return LowerVECTOR_SHUFFLE(Op, DAG);
1930 case ISD::EXTRACT_SUBVECTOR:
1931 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1935 return LowerVectorSRA_SRL_SHL(Op, DAG);
1936 case ISD::SHL_PARTS:
1937 return LowerShiftLeftParts(Op, DAG);
1938 case ISD::SRL_PARTS:
1939 case ISD::SRA_PARTS:
1940 return LowerShiftRightParts(Op, DAG);
1942 return LowerCTPOP(Op, DAG);
1943 case ISD::FCOPYSIGN:
1944 return LowerFCOPYSIGN(Op, DAG);
1946 return LowerVectorAND(Op, DAG);
1948 return LowerVectorOR(Op, DAG);
1950 return LowerXOR(Op, DAG);
1952 return LowerPREFETCH(Op, DAG);
1953 case ISD::SINT_TO_FP:
1954 case ISD::UINT_TO_FP:
1955 return LowerINT_TO_FP(Op, DAG);
1956 case ISD::FP_TO_SINT:
1957 case ISD::FP_TO_UINT:
1958 return LowerFP_TO_INT(Op, DAG);
1960 return LowerFSINCOS(Op, DAG);
1962 return LowerMUL(Op, DAG);
1966 /// getFunctionAlignment - Return the Log2 alignment of this function.
1967 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1971 //===----------------------------------------------------------------------===//
1972 // Calling Convention Implementation
1973 //===----------------------------------------------------------------------===//
1975 #include "AArch64GenCallingConv.inc"
1977 /// Selects the correct CCAssignFn for a given CallingConvention value.
1978 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1979 bool IsVarArg) const {
1982 llvm_unreachable("Unsupported calling convention.");
1983 case CallingConv::WebKit_JS:
1984 return CC_AArch64_WebKit_JS;
1985 case CallingConv::C:
1986 case CallingConv::Fast:
1987 if (!Subtarget->isTargetDarwin())
1988 return CC_AArch64_AAPCS;
1989 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1993 SDValue AArch64TargetLowering::LowerFormalArguments(
1994 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1995 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1996 SmallVectorImpl<SDValue> &InVals) const {
1997 MachineFunction &MF = DAG.getMachineFunction();
1998 MachineFrameInfo *MFI = MF.getFrameInfo();
2000 // Assign locations to all of the incoming arguments.
2001 SmallVector<CCValAssign, 16> ArgLocs;
2002 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2005 // At this point, Ins[].VT may already be promoted to i32. To correctly
2006 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2007 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2008 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2009 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2011 unsigned NumArgs = Ins.size();
2012 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2013 unsigned CurArgIdx = 0;
2014 for (unsigned i = 0; i != NumArgs; ++i) {
2015 MVT ValVT = Ins[i].VT;
2016 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
2017 CurArgIdx = Ins[i].OrigArgIndex;
2019 // Get type of the original argument.
2020 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2021 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2022 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2023 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2025 else if (ActualMVT == MVT::i16)
2028 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2030 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2031 assert(!Res && "Call operand has unhandled type");
2034 assert(ArgLocs.size() == Ins.size());
2035 SmallVector<SDValue, 16> ArgValues;
2036 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2037 CCValAssign &VA = ArgLocs[i];
2039 if (Ins[i].Flags.isByVal()) {
2040 // Byval is used for HFAs in the PCS, but the system should work in a
2041 // non-compliant manner for larger structs.
2042 EVT PtrTy = getPointerTy();
2043 int Size = Ins[i].Flags.getByValSize();
2044 unsigned NumRegs = (Size + 7) / 8;
2046 // FIXME: This works on big-endian for composite byvals, which are the common
2047 // case. It should also work for fundamental types too.
2049 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2050 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2051 InVals.push_back(FrameIdxN);
2056 if (VA.isRegLoc()) {
2057 // Arguments stored in registers.
2058 EVT RegVT = VA.getLocVT();
2061 const TargetRegisterClass *RC;
2063 if (RegVT == MVT::i32)
2064 RC = &AArch64::GPR32RegClass;
2065 else if (RegVT == MVT::i64)
2066 RC = &AArch64::GPR64RegClass;
2067 else if (RegVT == MVT::f16)
2068 RC = &AArch64::FPR16RegClass;
2069 else if (RegVT == MVT::f32)
2070 RC = &AArch64::FPR32RegClass;
2071 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2072 RC = &AArch64::FPR64RegClass;
2073 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2074 RC = &AArch64::FPR128RegClass;
2076 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2078 // Transform the arguments in physical registers into virtual ones.
2079 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2080 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2082 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2083 // to 64 bits. Insert an assert[sz]ext to capture this, then
2084 // truncate to the right size.
2085 switch (VA.getLocInfo()) {
2087 llvm_unreachable("Unknown loc info!");
2088 case CCValAssign::Full:
2090 case CCValAssign::BCvt:
2091 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2093 case CCValAssign::AExt:
2094 case CCValAssign::SExt:
2095 case CCValAssign::ZExt:
2096 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2097 // nodes after our lowering.
2098 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2102 InVals.push_back(ArgValue);
2104 } else { // VA.isRegLoc()
2105 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2106 unsigned ArgOffset = VA.getLocMemOffset();
2107 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2109 uint32_t BEAlign = 0;
2110 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2111 BEAlign = 8 - ArgSize;
2113 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2115 // Create load nodes to retrieve arguments from the stack.
2116 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2119 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2120 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2121 MVT MemVT = VA.getValVT();
2123 switch (VA.getLocInfo()) {
2126 case CCValAssign::BCvt:
2127 MemVT = VA.getLocVT();
2129 case CCValAssign::SExt:
2130 ExtType = ISD::SEXTLOAD;
2132 case CCValAssign::ZExt:
2133 ExtType = ISD::ZEXTLOAD;
2135 case CCValAssign::AExt:
2136 ExtType = ISD::EXTLOAD;
2140 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2141 MachinePointerInfo::getFixedStack(FI),
2142 MemVT, false, false, false, 0);
2144 InVals.push_back(ArgValue);
2150 if (!Subtarget->isTargetDarwin()) {
2151 // The AAPCS variadic function ABI is identical to the non-variadic
2152 // one. As a result there may be more arguments in registers and we should
2153 // save them for future reference.
2154 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2157 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2158 // This will point to the next argument passed via stack.
2159 unsigned StackOffset = CCInfo.getNextStackOffset();
2160 // We currently pass all varargs at 8-byte alignment.
2161 StackOffset = ((StackOffset + 7) & ~7);
2162 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2165 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2166 unsigned StackArgSize = CCInfo.getNextStackOffset();
2167 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2168 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2169 // This is a non-standard ABI so by fiat I say we're allowed to make full
2170 // use of the stack area to be popped, which must be aligned to 16 bytes in
2172 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2174 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2175 // a multiple of 16.
2176 FuncInfo->setArgumentStackToRestore(StackArgSize);
2178 // This realignment carries over to the available bytes below. Our own
2179 // callers will guarantee the space is free by giving an aligned value to
2182 // Even if we're not expected to free up the space, it's useful to know how
2183 // much is there while considering tail calls (because we can reuse it).
2184 FuncInfo->setBytesInStackArgArea(StackArgSize);
2189 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2190 SelectionDAG &DAG, SDLoc DL,
2191 SDValue &Chain) const {
2192 MachineFunction &MF = DAG.getMachineFunction();
2193 MachineFrameInfo *MFI = MF.getFrameInfo();
2194 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2196 SmallVector<SDValue, 8> MemOps;
2198 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2199 AArch64::X3, AArch64::X4, AArch64::X5,
2200 AArch64::X6, AArch64::X7 };
2201 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2202 unsigned FirstVariadicGPR =
2203 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
2205 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2207 if (GPRSaveSize != 0) {
2208 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2210 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2212 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2213 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2214 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2216 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2217 MachinePointerInfo::getStack(i * 8), false, false, 0);
2218 MemOps.push_back(Store);
2219 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2220 DAG.getConstant(8, getPointerTy()));
2223 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2224 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2226 if (Subtarget->hasFPARMv8()) {
2227 static const MCPhysReg FPRArgRegs[] = {
2228 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2229 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2230 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2231 unsigned FirstVariadicFPR =
2232 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
2234 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2236 if (FPRSaveSize != 0) {
2237 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2239 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2241 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2242 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2243 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2246 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2247 MachinePointerInfo::getStack(i * 16), false, false, 0);
2248 MemOps.push_back(Store);
2249 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2250 DAG.getConstant(16, getPointerTy()));
2253 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2254 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2257 if (!MemOps.empty()) {
2258 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2262 /// LowerCallResult - Lower the result values of a call into the
2263 /// appropriate copies out of appropriate physical registers.
2264 SDValue AArch64TargetLowering::LowerCallResult(
2265 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2266 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2267 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2268 SDValue ThisVal) const {
2269 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2270 ? RetCC_AArch64_WebKit_JS
2271 : RetCC_AArch64_AAPCS;
2272 // Assign locations to each value returned by this call.
2273 SmallVector<CCValAssign, 16> RVLocs;
2274 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2276 CCInfo.AnalyzeCallResult(Ins, RetCC);
2278 // Copy all of the result registers out of their specified physreg.
2279 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2280 CCValAssign VA = RVLocs[i];
2282 // Pass 'this' value directly from the argument to return value, to avoid
2283 // reg unit interference
2284 if (i == 0 && isThisReturn) {
2285 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2286 "unexpected return calling convention register assignment");
2287 InVals.push_back(ThisVal);
2292 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2293 Chain = Val.getValue(1);
2294 InFlag = Val.getValue(2);
2296 switch (VA.getLocInfo()) {
2298 llvm_unreachable("Unknown loc info!");
2299 case CCValAssign::Full:
2301 case CCValAssign::BCvt:
2302 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2306 InVals.push_back(Val);
2312 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2313 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2314 bool isCalleeStructRet, bool isCallerStructRet,
2315 const SmallVectorImpl<ISD::OutputArg> &Outs,
2316 const SmallVectorImpl<SDValue> &OutVals,
2317 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2318 // For CallingConv::C this function knows whether the ABI needs
2319 // changing. That's not true for other conventions so they will have to opt in
2321 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2324 const MachineFunction &MF = DAG.getMachineFunction();
2325 const Function *CallerF = MF.getFunction();
2326 CallingConv::ID CallerCC = CallerF->getCallingConv();
2327 bool CCMatch = CallerCC == CalleeCC;
2329 // Byval parameters hand the function a pointer directly into the stack area
2330 // we want to reuse during a tail call. Working around this *is* possible (see
2331 // X86) but less efficient and uglier in LowerCall.
2332 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2333 e = CallerF->arg_end();
2335 if (i->hasByValAttr())
2338 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2339 if (IsTailCallConvention(CalleeCC) && CCMatch)
2344 // Externally-defined functions with weak linkage should not be
2345 // tail-called on AArch64 when the OS does not support dynamic
2346 // pre-emption of symbols, as the AAELF spec requires normal calls
2347 // to undefined weak functions to be replaced with a NOP or jump to the
2348 // next instruction. The behaviour of branch instructions in this
2349 // situation (as used for tail calls) is implementation-defined, so we
2350 // cannot rely on the linker replacing the tail call with a return.
2351 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2352 const GlobalValue *GV = G->getGlobal();
2353 if (GV->hasExternalWeakLinkage())
2357 // Now we search for cases where we can use a tail call without changing the
2358 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2361 // I want anyone implementing a new calling convention to think long and hard
2362 // about this assert.
2363 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2364 "Unexpected variadic calling convention");
2366 if (isVarArg && !Outs.empty()) {
2367 // At least two cases here: if caller is fastcc then we can't have any
2368 // memory arguments (we'd be expected to clean up the stack afterwards). If
2369 // caller is C then we could potentially use its argument area.
2371 // FIXME: for now we take the most conservative of these in both cases:
2372 // disallow all variadic memory operands.
2373 SmallVector<CCValAssign, 16> ArgLocs;
2374 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2377 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2378 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2379 if (!ArgLocs[i].isRegLoc())
2383 // If the calling conventions do not match, then we'd better make sure the
2384 // results are returned in the same way as what the caller expects.
2386 SmallVector<CCValAssign, 16> RVLocs1;
2387 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2389 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2391 SmallVector<CCValAssign, 16> RVLocs2;
2392 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2394 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2396 if (RVLocs1.size() != RVLocs2.size())
2398 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2399 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2401 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2403 if (RVLocs1[i].isRegLoc()) {
2404 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2407 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2413 // Nothing more to check if the callee is taking no arguments
2417 SmallVector<CCValAssign, 16> ArgLocs;
2418 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2421 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2423 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2425 // If the stack arguments for this call would fit into our own save area then
2426 // the call can be made tail.
2427 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2430 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2432 MachineFrameInfo *MFI,
2433 int ClobberedFI) const {
2434 SmallVector<SDValue, 8> ArgChains;
2435 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2436 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2438 // Include the original chain at the beginning of the list. When this is
2439 // used by target LowerCall hooks, this helps legalize find the
2440 // CALLSEQ_BEGIN node.
2441 ArgChains.push_back(Chain);
2443 // Add a chain value for each stack argument corresponding
2444 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2445 UE = DAG.getEntryNode().getNode()->use_end();
2447 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2448 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2449 if (FI->getIndex() < 0) {
2450 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2451 int64_t InLastByte = InFirstByte;
2452 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2454 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2455 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2456 ArgChains.push_back(SDValue(L, 1));
2459 // Build a tokenfactor for all the chains.
2460 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2463 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2464 bool TailCallOpt) const {
2465 return CallCC == CallingConv::Fast && TailCallOpt;
2468 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2469 return CallCC == CallingConv::Fast;
2472 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2473 /// and add input and output parameter nodes.
2475 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2476 SmallVectorImpl<SDValue> &InVals) const {
2477 SelectionDAG &DAG = CLI.DAG;
2479 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2480 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2481 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2482 SDValue Chain = CLI.Chain;
2483 SDValue Callee = CLI.Callee;
2484 bool &IsTailCall = CLI.IsTailCall;
2485 CallingConv::ID CallConv = CLI.CallConv;
2486 bool IsVarArg = CLI.IsVarArg;
2488 MachineFunction &MF = DAG.getMachineFunction();
2489 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2490 bool IsThisReturn = false;
2492 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2493 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2494 bool IsSibCall = false;
2497 // Check if it's really possible to do a tail call.
2498 IsTailCall = isEligibleForTailCallOptimization(
2499 Callee, CallConv, IsVarArg, IsStructRet,
2500 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2501 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2502 report_fatal_error("failed to perform tail call elimination on a call "
2503 "site marked musttail");
2505 // A sibling call is one where we're under the usual C ABI and not planning
2506 // to change that but can still do a tail call:
2507 if (!TailCallOpt && IsTailCall)
2514 // Analyze operands of the call, assigning locations to each operand.
2515 SmallVector<CCValAssign, 16> ArgLocs;
2516 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2520 // Handle fixed and variable vector arguments differently.
2521 // Variable vector arguments always go into memory.
2522 unsigned NumArgs = Outs.size();
2524 for (unsigned i = 0; i != NumArgs; ++i) {
2525 MVT ArgVT = Outs[i].VT;
2526 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2527 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2528 /*IsVarArg=*/ !Outs[i].IsFixed);
2529 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2530 assert(!Res && "Call operand has unhandled type");
2534 // At this point, Outs[].VT may already be promoted to i32. To correctly
2535 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2536 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2537 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2538 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2540 unsigned NumArgs = Outs.size();
2541 for (unsigned i = 0; i != NumArgs; ++i) {
2542 MVT ValVT = Outs[i].VT;
2543 // Get type of the original argument.
2544 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2545 /*AllowUnknown*/ true);
2546 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2547 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2548 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2549 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2551 else if (ActualMVT == MVT::i16)
2554 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2555 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2556 assert(!Res && "Call operand has unhandled type");
2561 // Get a count of how many bytes are to be pushed on the stack.
2562 unsigned NumBytes = CCInfo.getNextStackOffset();
2565 // Since we're not changing the ABI to make this a tail call, the memory
2566 // operands are already available in the caller's incoming argument space.
2570 // FPDiff is the byte offset of the call's argument area from the callee's.
2571 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2572 // by this amount for a tail call. In a sibling call it must be 0 because the
2573 // caller will deallocate the entire stack and the callee still expects its
2574 // arguments to begin at SP+0. Completely unused for non-tail calls.
2577 if (IsTailCall && !IsSibCall) {
2578 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2580 // Since callee will pop argument stack as a tail call, we must keep the
2581 // popped size 16-byte aligned.
2582 NumBytes = RoundUpToAlignment(NumBytes, 16);
2584 // FPDiff will be negative if this tail call requires more space than we
2585 // would automatically have in our incoming argument space. Positive if we
2586 // can actually shrink the stack.
2587 FPDiff = NumReusableBytes - NumBytes;
2589 // The stack pointer must be 16-byte aligned at all times it's used for a
2590 // memory operation, which in practice means at *all* times and in
2591 // particular across call boundaries. Therefore our own arguments started at
2592 // a 16-byte aligned SP and the delta applied for the tail call should
2593 // satisfy the same constraint.
2594 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2597 // Adjust the stack pointer for the new arguments...
2598 // These operations are automatically eliminated by the prolog/epilog pass
2601 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2603 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2605 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2606 SmallVector<SDValue, 8> MemOpChains;
2608 // Walk the register/memloc assignments, inserting copies/loads.
2609 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2610 ++i, ++realArgIdx) {
2611 CCValAssign &VA = ArgLocs[i];
2612 SDValue Arg = OutVals[realArgIdx];
2613 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2615 // Promote the value if needed.
2616 switch (VA.getLocInfo()) {
2618 llvm_unreachable("Unknown loc info!");
2619 case CCValAssign::Full:
2621 case CCValAssign::SExt:
2622 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2624 case CCValAssign::ZExt:
2625 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2627 case CCValAssign::AExt:
2628 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2629 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2630 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2631 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2633 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2635 case CCValAssign::BCvt:
2636 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2638 case CCValAssign::FPExt:
2639 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2643 if (VA.isRegLoc()) {
2644 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2645 assert(VA.getLocVT() == MVT::i64 &&
2646 "unexpected calling convention register assignment");
2647 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2648 "unexpected use of 'returned'");
2649 IsThisReturn = true;
2651 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2653 assert(VA.isMemLoc());
2656 MachinePointerInfo DstInfo;
2658 // FIXME: This works on big-endian for composite byvals, which are the
2659 // common case. It should also work for fundamental types too.
2660 uint32_t BEAlign = 0;
2661 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2662 : VA.getValVT().getSizeInBits();
2663 OpSize = (OpSize + 7) / 8;
2664 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2666 BEAlign = 8 - OpSize;
2668 unsigned LocMemOffset = VA.getLocMemOffset();
2669 int32_t Offset = LocMemOffset + BEAlign;
2670 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2671 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2674 Offset = Offset + FPDiff;
2675 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2677 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2678 DstInfo = MachinePointerInfo::getFixedStack(FI);
2680 // Make sure any stack arguments overlapping with where we're storing
2681 // are loaded before this eventual operation. Otherwise they'll be
2683 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2685 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2687 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2688 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2691 if (Outs[i].Flags.isByVal()) {
2693 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2694 SDValue Cpy = DAG.getMemcpy(
2695 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2697 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2699 MemOpChains.push_back(Cpy);
2701 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2702 // promoted to a legal register type i32, we should truncate Arg back to
2704 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2705 VA.getValVT() == MVT::i16)
2706 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2709 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2710 MemOpChains.push_back(Store);
2715 if (!MemOpChains.empty())
2716 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2718 // Build a sequence of copy-to-reg nodes chained together with token chain
2719 // and flag operands which copy the outgoing args into the appropriate regs.
2721 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2722 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2723 RegsToPass[i].second, InFlag);
2724 InFlag = Chain.getValue(1);
2727 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2728 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2729 // node so that legalize doesn't hack it.
2730 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2731 Subtarget->isTargetMachO()) {
2732 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2733 const GlobalValue *GV = G->getGlobal();
2734 bool InternalLinkage = GV->hasInternalLinkage();
2735 if (InternalLinkage)
2736 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2738 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2740 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2742 } else if (ExternalSymbolSDNode *S =
2743 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2744 const char *Sym = S->getSymbol();
2746 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2747 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2749 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2750 const GlobalValue *GV = G->getGlobal();
2751 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2752 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2753 const char *Sym = S->getSymbol();
2754 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2757 // We don't usually want to end the call-sequence here because we would tidy
2758 // the frame up *after* the call, however in the ABI-changing tail-call case
2759 // we've carefully laid out the parameters so that when sp is reset they'll be
2760 // in the correct location.
2761 if (IsTailCall && !IsSibCall) {
2762 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2763 DAG.getIntPtrConstant(0, true), InFlag, DL);
2764 InFlag = Chain.getValue(1);
2767 std::vector<SDValue> Ops;
2768 Ops.push_back(Chain);
2769 Ops.push_back(Callee);
2772 // Each tail call may have to adjust the stack by a different amount, so
2773 // this information must travel along with the operation for eventual
2774 // consumption by emitEpilogue.
2775 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2778 // Add argument registers to the end of the list so that they are known live
2780 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2781 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2782 RegsToPass[i].second.getValueType()));
2784 // Add a register mask operand representing the call-preserved registers.
2785 const uint32_t *Mask;
2786 const TargetRegisterInfo *TRI =
2787 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2788 const AArch64RegisterInfo *ARI =
2789 static_cast<const AArch64RegisterInfo *>(TRI);
2791 // For 'this' returns, use the X0-preserving mask if applicable
2792 Mask = ARI->getThisReturnPreservedMask(CallConv);
2794 IsThisReturn = false;
2795 Mask = ARI->getCallPreservedMask(CallConv);
2798 Mask = ARI->getCallPreservedMask(CallConv);
2800 assert(Mask && "Missing call preserved mask for calling convention");
2801 Ops.push_back(DAG.getRegisterMask(Mask));
2803 if (InFlag.getNode())
2804 Ops.push_back(InFlag);
2806 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2808 // If we're doing a tall call, use a TC_RETURN here rather than an
2809 // actual call instruction.
2811 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2813 // Returns a chain and a flag for retval copy to use.
2814 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2815 InFlag = Chain.getValue(1);
2817 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2818 ? RoundUpToAlignment(NumBytes, 16)
2821 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2822 DAG.getIntPtrConstant(CalleePopBytes, true),
2825 InFlag = Chain.getValue(1);
2827 // Handle result values, copying them out of physregs into vregs that we
2829 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2830 InVals, IsThisReturn,
2831 IsThisReturn ? OutVals[0] : SDValue());
2834 bool AArch64TargetLowering::CanLowerReturn(
2835 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2836 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2837 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2838 ? RetCC_AArch64_WebKit_JS
2839 : RetCC_AArch64_AAPCS;
2840 SmallVector<CCValAssign, 16> RVLocs;
2841 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2842 return CCInfo.CheckReturn(Outs, RetCC);
2846 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2848 const SmallVectorImpl<ISD::OutputArg> &Outs,
2849 const SmallVectorImpl<SDValue> &OutVals,
2850 SDLoc DL, SelectionDAG &DAG) const {
2851 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2852 ? RetCC_AArch64_WebKit_JS
2853 : RetCC_AArch64_AAPCS;
2854 SmallVector<CCValAssign, 16> RVLocs;
2855 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2857 CCInfo.AnalyzeReturn(Outs, RetCC);
2859 // Copy the result values into the output registers.
2861 SmallVector<SDValue, 4> RetOps(1, Chain);
2862 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2863 ++i, ++realRVLocIdx) {
2864 CCValAssign &VA = RVLocs[i];
2865 assert(VA.isRegLoc() && "Can only return in registers!");
2866 SDValue Arg = OutVals[realRVLocIdx];
2868 switch (VA.getLocInfo()) {
2870 llvm_unreachable("Unknown loc info!");
2871 case CCValAssign::Full:
2872 if (Outs[i].ArgVT == MVT::i1) {
2873 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2874 // value. This is strictly redundant on Darwin (which uses "zeroext
2875 // i1"), but will be optimised out before ISel.
2876 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2877 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2880 case CCValAssign::BCvt:
2881 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2885 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2886 Flag = Chain.getValue(1);
2887 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2890 RetOps[0] = Chain; // Update chain.
2892 // Add the flag if we have it.
2894 RetOps.push_back(Flag);
2896 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2899 //===----------------------------------------------------------------------===//
2900 // Other Lowering Code
2901 //===----------------------------------------------------------------------===//
2903 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2904 SelectionDAG &DAG) const {
2905 EVT PtrVT = getPointerTy();
2907 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2908 const GlobalValue *GV = GN->getGlobal();
2909 unsigned char OpFlags =
2910 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2912 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2913 "unexpected offset in global node");
2915 // This also catched the large code model case for Darwin.
2916 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2917 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2918 // FIXME: Once remat is capable of dealing with instructions with register
2919 // operands, expand this into two nodes instead of using a wrapper node.
2920 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2923 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2924 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2925 "use of MO_CONSTPOOL only supported on small model");
2926 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2927 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2928 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2929 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2930 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2931 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2932 MachinePointerInfo::getConstantPool(),
2933 /*isVolatile=*/ false,
2934 /*isNonTemporal=*/ true,
2935 /*isInvariant=*/ true, 8);
2936 if (GN->getOffset() != 0)
2937 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2938 DAG.getConstant(GN->getOffset(), PtrVT));
2942 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2943 const unsigned char MO_NC = AArch64II::MO_NC;
2945 AArch64ISD::WrapperLarge, DL, PtrVT,
2946 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2947 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2948 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2949 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2951 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2952 // the only correct model on Darwin.
2953 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2954 OpFlags | AArch64II::MO_PAGE);
2955 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2956 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2958 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2959 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2963 /// \brief Convert a TLS address reference into the correct sequence of loads
2964 /// and calls to compute the variable's address (for Darwin, currently) and
2965 /// return an SDValue containing the final node.
2967 /// Darwin only has one TLS scheme which must be capable of dealing with the
2968 /// fully general situation, in the worst case. This means:
2969 /// + "extern __thread" declaration.
2970 /// + Defined in a possibly unknown dynamic library.
2972 /// The general system is that each __thread variable has a [3 x i64] descriptor
2973 /// which contains information used by the runtime to calculate the address. The
2974 /// only part of this the compiler needs to know about is the first xword, which
2975 /// contains a function pointer that must be called with the address of the
2976 /// entire descriptor in "x0".
2978 /// Since this descriptor may be in a different unit, in general even the
2979 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2981 /// adrp x0, _var@TLVPPAGE
2982 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2983 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2984 /// ; the function pointer
2985 /// blr x1 ; Uses descriptor address in x0
2986 /// ; Address of _var is now in x0.
2988 /// If the address of _var's descriptor *is* known to the linker, then it can
2989 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2990 /// a slight efficiency gain.
2992 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2993 SelectionDAG &DAG) const {
2994 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2997 MVT PtrVT = getPointerTy();
2998 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3001 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3002 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3004 // The first entry in the descriptor is a function pointer that we must call
3005 // to obtain the address of the variable.
3006 SDValue Chain = DAG.getEntryNode();
3007 SDValue FuncTLVGet =
3008 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3009 false, true, true, 8);
3010 Chain = FuncTLVGet.getValue(1);
3012 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3013 MFI->setAdjustsStack(true);
3015 // TLS calls preserve all registers except those that absolutely must be
3016 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3018 const TargetRegisterInfo *TRI =
3019 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3020 const AArch64RegisterInfo *ARI =
3021 static_cast<const AArch64RegisterInfo *>(TRI);
3022 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
3024 // Finally, we can make the call. This is just a degenerate version of a
3025 // normal AArch64 call node: x0 takes the address of the descriptor, and
3026 // returns the address of the variable in this thread.
3027 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3029 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3030 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3031 DAG.getRegisterMask(Mask), Chain.getValue(1));
3032 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3035 /// When accessing thread-local variables under either the general-dynamic or
3036 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3037 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3038 /// is a function pointer to carry out the resolution. This function takes the
3039 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
3040 /// other registers (except LR, NZCV) are preserved.
3042 /// Thus, the ideal call sequence on AArch64 is:
3044 /// adrp x0, :tlsdesc:thread_var
3045 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
3046 /// add x0, x0, :tlsdesc_lo12:thread_var
3047 /// .tlsdesccall thread_var
3049 /// (TPIDR_EL0 offset now in x0).
3051 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
3052 /// relocation to help the linker relax this sequence if it turns out to be too
3055 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
3057 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
3058 SDValue DescAddr, SDLoc DL,
3059 SelectionDAG &DAG) const {
3060 EVT PtrVT = getPointerTy();
3062 // The function we need to call is simply the first entry in the GOT for this
3063 // descriptor, load it in preparation.
3064 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
3066 // TLS calls preserve all registers except those that absolutely must be
3067 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3069 const TargetRegisterInfo *TRI =
3070 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3071 const AArch64RegisterInfo *ARI =
3072 static_cast<const AArch64RegisterInfo *>(TRI);
3073 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
3075 // The function takes only one argument: the address of the descriptor itself
3077 SDValue Glue, Chain;
3078 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
3079 Glue = Chain.getValue(1);
3081 // We're now ready to populate the argument list, as with a normal call:
3082 SmallVector<SDValue, 6> Ops;
3083 Ops.push_back(Chain);
3084 Ops.push_back(Func);
3085 Ops.push_back(SymAddr);
3086 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
3087 Ops.push_back(DAG.getRegisterMask(Mask));
3088 Ops.push_back(Glue);
3090 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3091 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
3092 Glue = Chain.getValue(1);
3094 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3098 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3099 SelectionDAG &DAG) const {
3100 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3101 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3102 "ELF TLS only supported in small memory model");
3103 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3105 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3108 EVT PtrVT = getPointerTy();
3110 const GlobalValue *GV = GA->getGlobal();
3112 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3114 if (Model == TLSModel::LocalExec) {
3115 SDValue HiVar = DAG.getTargetGlobalAddress(
3116 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
3117 SDValue LoVar = DAG.getTargetGlobalAddress(
3119 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
3121 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
3122 DAG.getTargetConstant(16, MVT::i32)),
3124 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
3125 DAG.getTargetConstant(0, MVT::i32)),
3127 } else if (Model == TLSModel::InitialExec) {
3128 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3129 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3130 } else if (Model == TLSModel::LocalDynamic) {
3131 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3132 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3133 // the beginning of the module's TLS region, followed by a DTPREL offset
3136 // These accesses will need deduplicating if there's more than one.
3137 AArch64FunctionInfo *MFI =
3138 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3139 MFI->incNumLocalDynamicTLSAccesses();
3141 // Accesses used in this sequence go via the TLS descriptor which lives in
3142 // the GOT. Prepare an address we can use to handle this.
3143 SDValue HiDesc = DAG.getTargetExternalSymbol(
3144 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
3145 SDValue LoDesc = DAG.getTargetExternalSymbol(
3146 "_TLS_MODULE_BASE_", PtrVT,
3147 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3149 // First argument to the descriptor call is the address of the descriptor
3151 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
3152 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
3154 // The call needs a relocation too for linker relaxation. It doesn't make
3155 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3157 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3160 // Now we can calculate the offset from TPIDR_EL0 to this module's
3161 // thread-local area.
3162 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
3164 // Now use :dtprel_whatever: operations to calculate this variable's offset
3165 // in its thread-storage area.
3166 SDValue HiVar = DAG.getTargetGlobalAddress(
3167 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
3168 SDValue LoVar = DAG.getTargetGlobalAddress(
3169 GV, DL, MVT::i64, 0,
3170 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
3173 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
3174 DAG.getTargetConstant(16, MVT::i32)),
3177 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
3178 DAG.getTargetConstant(0, MVT::i32)),
3181 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
3182 } else if (Model == TLSModel::GeneralDynamic) {
3183 // Accesses used in this sequence go via the TLS descriptor which lives in
3184 // the GOT. Prepare an address we can use to handle this.
3185 SDValue HiDesc = DAG.getTargetGlobalAddress(
3186 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
3187 SDValue LoDesc = DAG.getTargetGlobalAddress(
3189 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3191 // First argument to the descriptor call is the address of the descriptor
3193 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
3194 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
3196 // The call needs a relocation too for linker relaxation. It doesn't make
3197 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3200 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3202 // Finally we can make a call to calculate the offset from tpidr_el0.
3203 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
3205 llvm_unreachable("Unsupported ELF TLS access model");
3207 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3210 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3211 SelectionDAG &DAG) const {
3212 if (Subtarget->isTargetDarwin())
3213 return LowerDarwinGlobalTLSAddress(Op, DAG);
3214 else if (Subtarget->isTargetELF())
3215 return LowerELFGlobalTLSAddress(Op, DAG);
3217 llvm_unreachable("Unexpected platform trying to use TLS");
3219 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3220 SDValue Chain = Op.getOperand(0);
3221 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3222 SDValue LHS = Op.getOperand(2);
3223 SDValue RHS = Op.getOperand(3);
3224 SDValue Dest = Op.getOperand(4);
3227 // Handle f128 first, since lowering it will result in comparing the return
3228 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3229 // is expecting to deal with.
3230 if (LHS.getValueType() == MVT::f128) {
3231 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3233 // If softenSetCCOperands returned a scalar, we need to compare the result
3234 // against zero to select between true and false values.
3235 if (!RHS.getNode()) {
3236 RHS = DAG.getConstant(0, LHS.getValueType());
3241 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3243 unsigned Opc = LHS.getOpcode();
3244 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3245 cast<ConstantSDNode>(RHS)->isOne() &&
3246 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3247 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3248 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3249 "Unexpected condition code.");
3250 // Only lower legal XALUO ops.
3251 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3254 // The actual operation with overflow check.
3255 AArch64CC::CondCode OFCC;
3256 SDValue Value, Overflow;
3257 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3259 if (CC == ISD::SETNE)
3260 OFCC = getInvertedCondCode(OFCC);
3261 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3263 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
3267 if (LHS.getValueType().isInteger()) {
3268 assert((LHS.getValueType() == RHS.getValueType()) &&
3269 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3271 // If the RHS of the comparison is zero, we can potentially fold this
3272 // to a specialized branch.
3273 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3274 if (RHSC && RHSC->getZExtValue() == 0) {
3275 if (CC == ISD::SETEQ) {
3276 // See if we can use a TBZ to fold in an AND as well.
3277 // TBZ has a smaller branch displacement than CBZ. If the offset is
3278 // out of bounds, a late MI-layer pass rewrites branches.
3279 // 403.gcc is an example that hits this case.
3280 if (LHS.getOpcode() == ISD::AND &&
3281 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3282 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3283 SDValue Test = LHS.getOperand(0);
3284 uint64_t Mask = LHS.getConstantOperandVal(1);
3285 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3286 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3289 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3290 } else if (CC == ISD::SETNE) {
3291 // See if we can use a TBZ to fold in an AND as well.
3292 // TBZ has a smaller branch displacement than CBZ. If the offset is
3293 // out of bounds, a late MI-layer pass rewrites branches.
3294 // 403.gcc is an example that hits this case.
3295 if (LHS.getOpcode() == ISD::AND &&
3296 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3297 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3298 SDValue Test = LHS.getOperand(0);
3299 uint64_t Mask = LHS.getConstantOperandVal(1);
3300 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3301 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3304 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3305 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3306 // Don't combine AND since emitComparison converts the AND to an ANDS
3307 // (a.k.a. TST) and the test in the test bit and branch instruction
3308 // becomes redundant. This would also increase register pressure.
3309 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3310 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3311 DAG.getConstant(Mask, MVT::i64), Dest);
3314 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3315 LHS.getOpcode() != ISD::AND) {
3316 // Don't combine AND since emitComparison converts the AND to an ANDS
3317 // (a.k.a. TST) and the test in the test bit and branch instruction
3318 // becomes redundant. This would also increase register pressure.
3319 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3320 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3321 DAG.getConstant(Mask, MVT::i64), Dest);
3325 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3326 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3330 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3332 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3333 // clean. Some of them require two branches to implement.
3334 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3335 AArch64CC::CondCode CC1, CC2;
3336 changeFPCCToAArch64CC(CC, CC1, CC2);
3337 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3339 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3340 if (CC2 != AArch64CC::AL) {
3341 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3342 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3349 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3350 SelectionDAG &DAG) const {
3351 EVT VT = Op.getValueType();
3354 SDValue In1 = Op.getOperand(0);
3355 SDValue In2 = Op.getOperand(1);
3356 EVT SrcVT = In2.getValueType();
3358 if (SrcVT == MVT::f32 && VT == MVT::f64)
3359 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3360 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3361 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3363 // FIXME: Src type is different, bail out for now. Can VT really be a
3370 SDValue EltMask, VecVal1, VecVal2;
3371 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3374 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3376 if (!VT.isVector()) {
3377 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3378 DAG.getUNDEF(VecVT), In1);
3379 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3380 DAG.getUNDEF(VecVT), In2);
3382 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3383 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3385 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3389 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3390 // immediate moves cannot materialize that in a single instruction for
3391 // 64-bit elements. Instead, materialize zero and then negate it.
3392 EltMask = DAG.getConstant(0, EltVT);
3394 if (!VT.isVector()) {
3395 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3396 DAG.getUNDEF(VecVT), In1);
3397 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3398 DAG.getUNDEF(VecVT), In2);
3400 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3401 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3404 llvm_unreachable("Invalid type for copysign!");
3407 std::vector<SDValue> BuildVectorOps;
3408 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3409 BuildVectorOps.push_back(EltMask);
3411 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3413 // If we couldn't materialize the mask above, then the mask vector will be
3414 // the zero vector, and we need to negate it here.
3415 if (VT == MVT::f64 || VT == MVT::v2f64) {
3416 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3417 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3418 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3422 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3425 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3426 else if (VT == MVT::f64)
3427 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3429 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3432 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3433 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3434 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3437 if (!Subtarget->hasNEON())
3440 // While there is no integer popcount instruction, it can
3441 // be more efficiently lowered to the following sequence that uses
3442 // AdvSIMD registers/instructions as long as the copies to/from
3443 // the AdvSIMD registers are cheap.
3444 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3445 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3446 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3447 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3448 SDValue Val = Op.getOperand(0);
3450 EVT VT = Op.getValueType();
3451 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3454 if (VT == MVT::i32) {
3455 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3456 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3459 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3462 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3463 SDValue UaddLV = DAG.getNode(
3464 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3465 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3468 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3472 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3474 if (Op.getValueType().isVector())
3475 return LowerVSETCC(Op, DAG);
3477 SDValue LHS = Op.getOperand(0);
3478 SDValue RHS = Op.getOperand(1);
3479 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3482 // We chose ZeroOrOneBooleanContents, so use zero and one.
3483 EVT VT = Op.getValueType();
3484 SDValue TVal = DAG.getConstant(1, VT);
3485 SDValue FVal = DAG.getConstant(0, VT);
3487 // Handle f128 first, since one possible outcome is a normal integer
3488 // comparison which gets picked up by the next if statement.
3489 if (LHS.getValueType() == MVT::f128) {
3490 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3492 // If softenSetCCOperands returned a scalar, use it.
3493 if (!RHS.getNode()) {
3494 assert(LHS.getValueType() == Op.getValueType() &&
3495 "Unexpected setcc expansion!");
3500 if (LHS.getValueType().isInteger()) {
3503 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3505 // Note that we inverted the condition above, so we reverse the order of
3506 // the true and false operands here. This will allow the setcc to be
3507 // matched to a single CSINC instruction.
3508 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3511 // Now we know we're dealing with FP values.
3512 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3514 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3515 // and do the comparison.
3516 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3518 AArch64CC::CondCode CC1, CC2;
3519 changeFPCCToAArch64CC(CC, CC1, CC2);
3520 if (CC2 == AArch64CC::AL) {
3521 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3522 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3524 // Note that we inverted the condition above, so we reverse the order of
3525 // the true and false operands here. This will allow the setcc to be
3526 // matched to a single CSINC instruction.
3527 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3529 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3530 // totally clean. Some of them require two CSELs to implement. As is in
3531 // this case, we emit the first CSEL and then emit a second using the output
3532 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3534 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3535 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3537 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3539 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3540 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3544 /// A SELECT_CC operation is really some kind of max or min if both values being
3545 /// compared are, in some sense, equal to the results in either case. However,
3546 /// it is permissible to compare f32 values and produce directly extended f64
3549 /// Extending the comparison operands would also be allowed, but is less likely
3550 /// to happen in practice since their use is right here. Note that truncate
3551 /// operations would *not* be semantically equivalent.
3552 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3556 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3557 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3558 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3559 Result.getValueType() == MVT::f64) {
3561 APFloat CmpVal = CCmp->getValueAPF();
3562 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3563 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3566 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3569 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3570 SelectionDAG &DAG) const {
3571 SDValue CC = Op->getOperand(0);
3572 SDValue TVal = Op->getOperand(1);
3573 SDValue FVal = Op->getOperand(2);
3576 unsigned Opc = CC.getOpcode();
3577 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3579 if (CC.getResNo() == 1 &&
3580 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3581 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3582 // Only lower legal XALUO ops.
3583 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3586 AArch64CC::CondCode OFCC;
3587 SDValue Value, Overflow;
3588 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3589 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3591 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3595 if (CC.getOpcode() == ISD::SETCC)
3596 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3597 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3599 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3603 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3604 SelectionDAG &DAG) const {
3605 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3606 SDValue LHS = Op.getOperand(0);
3607 SDValue RHS = Op.getOperand(1);
3608 SDValue TVal = Op.getOperand(2);
3609 SDValue FVal = Op.getOperand(3);
3612 // Handle f128 first, because it will result in a comparison of some RTLIB
3613 // call result against zero.
3614 if (LHS.getValueType() == MVT::f128) {
3615 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3617 // If softenSetCCOperands returned a scalar, we need to compare the result
3618 // against zero to select between true and false values.
3619 if (!RHS.getNode()) {
3620 RHS = DAG.getConstant(0, LHS.getValueType());
3625 // Handle integers first.
3626 if (LHS.getValueType().isInteger()) {
3627 assert((LHS.getValueType() == RHS.getValueType()) &&
3628 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3630 unsigned Opcode = AArch64ISD::CSEL;
3632 // If both the TVal and the FVal are constants, see if we can swap them in
3633 // order to for a CSINV or CSINC out of them.
3634 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3635 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3637 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3638 std::swap(TVal, FVal);
3639 std::swap(CTVal, CFVal);
3640 CC = ISD::getSetCCInverse(CC, true);
3641 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3642 std::swap(TVal, FVal);
3643 std::swap(CTVal, CFVal);
3644 CC = ISD::getSetCCInverse(CC, true);
3645 } else if (TVal.getOpcode() == ISD::XOR) {
3646 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3647 // with a CSINV rather than a CSEL.
3648 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3650 if (CVal && CVal->isAllOnesValue()) {
3651 std::swap(TVal, FVal);
3652 std::swap(CTVal, CFVal);
3653 CC = ISD::getSetCCInverse(CC, true);
3655 } else if (TVal.getOpcode() == ISD::SUB) {
3656 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3657 // that we can match with a CSNEG rather than a CSEL.
3658 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3660 if (CVal && CVal->isNullValue()) {
3661 std::swap(TVal, FVal);
3662 std::swap(CTVal, CFVal);
3663 CC = ISD::getSetCCInverse(CC, true);
3665 } else if (CTVal && CFVal) {
3666 const int64_t TrueVal = CTVal->getSExtValue();
3667 const int64_t FalseVal = CFVal->getSExtValue();
3670 // If both TVal and FVal are constants, see if FVal is the
3671 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3672 // instead of a CSEL in that case.
3673 if (TrueVal == ~FalseVal) {
3674 Opcode = AArch64ISD::CSINV;
3675 } else if (TrueVal == -FalseVal) {
3676 Opcode = AArch64ISD::CSNEG;
3677 } else if (TVal.getValueType() == MVT::i32) {
3678 // If our operands are only 32-bit wide, make sure we use 32-bit
3679 // arithmetic for the check whether we can use CSINC. This ensures that
3680 // the addition in the check will wrap around properly in case there is
3681 // an overflow (which would not be the case if we do the check with
3682 // 64-bit arithmetic).
3683 const uint32_t TrueVal32 = CTVal->getZExtValue();
3684 const uint32_t FalseVal32 = CFVal->getZExtValue();
3686 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3687 Opcode = AArch64ISD::CSINC;
3689 if (TrueVal32 > FalseVal32) {
3693 // 64-bit check whether we can use CSINC.
3694 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3695 Opcode = AArch64ISD::CSINC;
3697 if (TrueVal > FalseVal) {
3702 // Swap TVal and FVal if necessary.
3704 std::swap(TVal, FVal);
3705 std::swap(CTVal, CFVal);
3706 CC = ISD::getSetCCInverse(CC, true);
3709 if (Opcode != AArch64ISD::CSEL) {
3710 // Drop FVal since we can get its value by simply inverting/negating
3717 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3719 EVT VT = Op.getValueType();
3720 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3723 // Now we know we're dealing with FP values.
3724 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3725 assert(LHS.getValueType() == RHS.getValueType());
3726 EVT VT = Op.getValueType();
3728 // Try to match this select into a max/min operation, which have dedicated
3729 // opcode in the instruction set.
3730 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3732 if (getTargetMachine().Options.NoNaNsFPMath) {
3733 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3734 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3735 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3736 CC = ISD::getSetCCSwappedOperands(CC);
3737 std::swap(MinMaxLHS, MinMaxRHS);
3740 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3741 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3751 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3759 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3765 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3766 // and do the comparison.
3767 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3769 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3770 // clean. Some of them require two CSELs to implement.
3771 AArch64CC::CondCode CC1, CC2;
3772 changeFPCCToAArch64CC(CC, CC1, CC2);
3773 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3774 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3776 // If we need a second CSEL, emit it, using the output of the first as the
3777 // RHS. We're effectively OR'ing the two CC's together.
3778 if (CC2 != AArch64CC::AL) {
3779 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3780 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3783 // Otherwise, return the output of the first CSEL.
3787 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3788 SelectionDAG &DAG) const {
3789 // Jump table entries as PC relative offsets. No additional tweaking
3790 // is necessary here. Just get the address of the jump table.
3791 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3792 EVT PtrVT = getPointerTy();
3795 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3796 !Subtarget->isTargetMachO()) {
3797 const unsigned char MO_NC = AArch64II::MO_NC;
3799 AArch64ISD::WrapperLarge, DL, PtrVT,
3800 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3801 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3802 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3803 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3804 AArch64II::MO_G0 | MO_NC));
3808 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3809 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3810 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3811 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3812 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3815 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3816 SelectionDAG &DAG) const {
3817 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3818 EVT PtrVT = getPointerTy();
3821 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3822 // Use the GOT for the large code model on iOS.
3823 if (Subtarget->isTargetMachO()) {
3824 SDValue GotAddr = DAG.getTargetConstantPool(
3825 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3827 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3830 const unsigned char MO_NC = AArch64II::MO_NC;
3832 AArch64ISD::WrapperLarge, DL, PtrVT,
3833 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3834 CP->getOffset(), AArch64II::MO_G3),
3835 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3836 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3837 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3838 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3839 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3840 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3842 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3843 // ELF, the only valid one on Darwin.
3845 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3846 CP->getOffset(), AArch64II::MO_PAGE);
3847 SDValue Lo = DAG.getTargetConstantPool(
3848 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3849 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3851 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3852 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3856 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3857 SelectionDAG &DAG) const {
3858 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3859 EVT PtrVT = getPointerTy();
3861 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3862 !Subtarget->isTargetMachO()) {
3863 const unsigned char MO_NC = AArch64II::MO_NC;
3865 AArch64ISD::WrapperLarge, DL, PtrVT,
3866 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3867 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3868 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3869 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3871 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3872 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3874 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3875 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3879 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3880 SelectionDAG &DAG) const {
3881 AArch64FunctionInfo *FuncInfo =
3882 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3886 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3887 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3888 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3889 MachinePointerInfo(SV), false, false, 0);
3892 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3893 SelectionDAG &DAG) const {
3894 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3895 // Standard, section B.3.
3896 MachineFunction &MF = DAG.getMachineFunction();
3897 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3900 SDValue Chain = Op.getOperand(0);
3901 SDValue VAList = Op.getOperand(1);
3902 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3903 SmallVector<SDValue, 4> MemOps;
3905 // void *__stack at offset 0
3907 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3908 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3909 MachinePointerInfo(SV), false, false, 8));
3911 // void *__gr_top at offset 8
3912 int GPRSize = FuncInfo->getVarArgsGPRSize();
3914 SDValue GRTop, GRTopAddr;
3916 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3917 DAG.getConstant(8, getPointerTy()));
3919 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3920 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3921 DAG.getConstant(GPRSize, getPointerTy()));
3923 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3924 MachinePointerInfo(SV, 8), false, false, 8));
3927 // void *__vr_top at offset 16
3928 int FPRSize = FuncInfo->getVarArgsFPRSize();
3930 SDValue VRTop, VRTopAddr;
3931 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3932 DAG.getConstant(16, getPointerTy()));
3934 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3935 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3936 DAG.getConstant(FPRSize, getPointerTy()));
3938 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3939 MachinePointerInfo(SV, 16), false, false, 8));
3942 // int __gr_offs at offset 24
3943 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3944 DAG.getConstant(24, getPointerTy()));
3945 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3946 GROffsAddr, MachinePointerInfo(SV, 24), false,
3949 // int __vr_offs at offset 28
3950 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3951 DAG.getConstant(28, getPointerTy()));
3952 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3953 VROffsAddr, MachinePointerInfo(SV, 28), false,
3956 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3959 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3960 SelectionDAG &DAG) const {
3961 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3962 : LowerAAPCS_VASTART(Op, DAG);
3965 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3966 SelectionDAG &DAG) const {
3967 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3969 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3970 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3971 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3973 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3974 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3975 8, false, false, MachinePointerInfo(DestSV),
3976 MachinePointerInfo(SrcSV));
3979 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3980 assert(Subtarget->isTargetDarwin() &&
3981 "automatic va_arg instruction only works on Darwin");
3983 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3984 EVT VT = Op.getValueType();
3986 SDValue Chain = Op.getOperand(0);
3987 SDValue Addr = Op.getOperand(1);
3988 unsigned Align = Op.getConstantOperandVal(3);
3990 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3991 MachinePointerInfo(V), false, false, false, 0);
3992 Chain = VAList.getValue(1);
3995 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3996 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3997 DAG.getConstant(Align - 1, getPointerTy()));
3998 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3999 DAG.getConstant(-(int64_t)Align, getPointerTy()));
4002 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4003 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4005 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4006 // up to 64 bits. At the very least, we have to increase the striding of the
4007 // vaargs list to match this, and for FP values we need to introduce
4008 // FP_ROUND nodes as well.
4009 if (VT.isInteger() && !VT.isVector())
4011 bool NeedFPTrunc = false;
4012 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4017 // Increment the pointer, VAList, to the next vaarg
4018 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4019 DAG.getConstant(ArgSize, getPointerTy()));
4020 // Store the incremented VAList to the legalized pointer
4021 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4024 // Load the actual argument out of the pointer VAList
4026 // Load the value as an f64.
4027 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4028 MachinePointerInfo(), false, false, false, 0);
4029 // Round the value down to an f32.
4030 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4031 DAG.getIntPtrConstant(1));
4032 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4033 // Merge the rounded value with the chain output of the load.
4034 return DAG.getMergeValues(Ops, DL);
4037 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4041 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4042 SelectionDAG &DAG) const {
4043 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4044 MFI->setFrameAddressIsTaken(true);
4046 EVT VT = Op.getValueType();
4048 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4050 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4052 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4053 MachinePointerInfo(), false, false, false, 0);
4057 // FIXME? Maybe this could be a TableGen attribute on some registers and
4058 // this table could be generated automatically from RegInfo.
4059 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4061 unsigned Reg = StringSwitch<unsigned>(RegName)
4062 .Case("sp", AArch64::SP)
4066 report_fatal_error("Invalid register name global variable");
4069 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4070 SelectionDAG &DAG) const {
4071 MachineFunction &MF = DAG.getMachineFunction();
4072 MachineFrameInfo *MFI = MF.getFrameInfo();
4073 MFI->setReturnAddressIsTaken(true);
4075 EVT VT = Op.getValueType();
4077 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4079 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4080 SDValue Offset = DAG.getConstant(8, getPointerTy());
4081 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4082 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4083 MachinePointerInfo(), false, false, false, 0);
4086 // Return LR, which contains the return address. Mark it an implicit live-in.
4087 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4088 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4091 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4092 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4093 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4094 SelectionDAG &DAG) const {
4095 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4096 EVT VT = Op.getValueType();
4097 unsigned VTBits = VT.getSizeInBits();
4099 SDValue ShOpLo = Op.getOperand(0);
4100 SDValue ShOpHi = Op.getOperand(1);
4101 SDValue ShAmt = Op.getOperand(2);
4103 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4105 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4107 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4108 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4109 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4110 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4111 DAG.getConstant(VTBits, MVT::i64));
4112 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4114 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4115 ISD::SETGE, dl, DAG);
4116 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4118 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4119 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4121 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4123 // AArch64 shifts larger than the register width are wrapped rather than
4124 // clamped, so we can't just emit "hi >> x".
4125 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4126 SDValue TrueValHi = Opc == ISD::SRA
4127 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4128 DAG.getConstant(VTBits - 1, MVT::i64))
4129 : DAG.getConstant(0, VT);
4131 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4133 SDValue Ops[2] = { Lo, Hi };
4134 return DAG.getMergeValues(Ops, dl);
4137 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4138 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4139 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4140 SelectionDAG &DAG) const {
4141 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4142 EVT VT = Op.getValueType();
4143 unsigned VTBits = VT.getSizeInBits();
4145 SDValue ShOpLo = Op.getOperand(0);
4146 SDValue ShOpHi = Op.getOperand(1);
4147 SDValue ShAmt = Op.getOperand(2);
4150 assert(Op.getOpcode() == ISD::SHL_PARTS);
4151 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4152 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4153 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4154 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4155 DAG.getConstant(VTBits, MVT::i64));
4156 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4157 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4159 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4161 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4162 ISD::SETGE, dl, DAG);
4163 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4165 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4167 // AArch64 shifts of larger than register sizes are wrapped rather than
4168 // clamped, so we can't just emit "lo << a" if a is too big.
4169 SDValue TrueValLo = DAG.getConstant(0, VT);
4170 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4172 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4174 SDValue Ops[2] = { Lo, Hi };
4175 return DAG.getMergeValues(Ops, dl);
4178 bool AArch64TargetLowering::isOffsetFoldingLegal(
4179 const GlobalAddressSDNode *GA) const {
4180 // The AArch64 target doesn't support folding offsets into global addresses.
4184 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4185 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4186 // FIXME: We should be able to handle f128 as well with a clever lowering.
4187 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4191 return AArch64_AM::getFP64Imm(Imm) != -1;
4192 else if (VT == MVT::f32)
4193 return AArch64_AM::getFP32Imm(Imm) != -1;
4197 //===----------------------------------------------------------------------===//
4198 // AArch64 Optimization Hooks
4199 //===----------------------------------------------------------------------===//
4201 //===----------------------------------------------------------------------===//
4202 // AArch64 Inline Assembly Support
4203 //===----------------------------------------------------------------------===//
4205 // Table of Constraints
4206 // TODO: This is the current set of constraints supported by ARM for the
4207 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4209 // r - A general register
4210 // w - An FP/SIMD register of some size in the range v0-v31
4211 // x - An FP/SIMD register of some size in the range v0-v15
4212 // I - Constant that can be used with an ADD instruction
4213 // J - Constant that can be used with a SUB instruction
4214 // K - Constant that can be used with a 32-bit logical instruction
4215 // L - Constant that can be used with a 64-bit logical instruction
4216 // M - Constant that can be used as a 32-bit MOV immediate
4217 // N - Constant that can be used as a 64-bit MOV immediate
4218 // Q - A memory reference with base register and no offset
4219 // S - A symbolic address
4220 // Y - Floating point constant zero
4221 // Z - Integer constant zero
4223 // Note that general register operands will be output using their 64-bit x
4224 // register name, whatever the size of the variable, unless the asm operand
4225 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4226 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4229 /// getConstraintType - Given a constraint letter, return the type of
4230 /// constraint it is for this target.
4231 AArch64TargetLowering::ConstraintType
4232 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4233 if (Constraint.size() == 1) {
4234 switch (Constraint[0]) {
4241 return C_RegisterClass;
4242 // An address with a single base register. Due to the way we
4243 // currently handle addresses it is the same as 'r'.
4248 return TargetLowering::getConstraintType(Constraint);
4251 /// Examine constraint type and operand type and determine a weight value.
4252 /// This object must already have been set up with the operand type
4253 /// and the current alternative constraint selected.
4254 TargetLowering::ConstraintWeight
4255 AArch64TargetLowering::getSingleConstraintMatchWeight(
4256 AsmOperandInfo &info, const char *constraint) const {
4257 ConstraintWeight weight = CW_Invalid;
4258 Value *CallOperandVal = info.CallOperandVal;
4259 // If we don't have a value, we can't do a match,
4260 // but allow it at the lowest weight.
4261 if (!CallOperandVal)
4263 Type *type = CallOperandVal->getType();
4264 // Look at the constraint type.
4265 switch (*constraint) {
4267 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4271 if (type->isFloatingPointTy() || type->isVectorTy())
4272 weight = CW_Register;
4275 weight = CW_Constant;
4281 std::pair<unsigned, const TargetRegisterClass *>
4282 AArch64TargetLowering::getRegForInlineAsmConstraint(
4283 const std::string &Constraint, MVT VT) const {
4284 if (Constraint.size() == 1) {
4285 switch (Constraint[0]) {
4287 if (VT.getSizeInBits() == 64)
4288 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4289 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4292 return std::make_pair(0U, &AArch64::FPR32RegClass);
4293 if (VT.getSizeInBits() == 64)
4294 return std::make_pair(0U, &AArch64::FPR64RegClass);
4295 if (VT.getSizeInBits() == 128)
4296 return std::make_pair(0U, &AArch64::FPR128RegClass);
4298 // The instructions that this constraint is designed for can
4299 // only take 128-bit registers so just use that regclass.
4301 if (VT.getSizeInBits() == 128)
4302 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4306 if (StringRef("{cc}").equals_lower(Constraint))
4307 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4309 // Use the default implementation in TargetLowering to convert the register
4310 // constraint into a member of a register class.
4311 std::pair<unsigned, const TargetRegisterClass *> Res;
4312 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4314 // Not found as a standard register?
4316 unsigned Size = Constraint.size();
4317 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4318 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4319 const std::string Reg =
4320 std::string(&Constraint[2], &Constraint[Size - 1]);
4321 int RegNo = atoi(Reg.c_str());
4322 if (RegNo >= 0 && RegNo <= 31) {
4323 // v0 - v31 are aliases of q0 - q31.
4324 // By default we'll emit v0-v31 for this unless there's a modifier where
4325 // we'll emit the correct register as well.
4326 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4327 Res.second = &AArch64::FPR128RegClass;
4335 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4336 /// vector. If it is invalid, don't add anything to Ops.
4337 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4338 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4339 SelectionDAG &DAG) const {
4342 // Currently only support length 1 constraints.
4343 if (Constraint.length() != 1)
4346 char ConstraintLetter = Constraint[0];
4347 switch (ConstraintLetter) {
4351 // This set of constraints deal with valid constants for various instructions.
4352 // Validate and return a target constant for them if we can.
4354 // 'z' maps to xzr or wzr so it needs an input of 0.
4355 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4356 if (!C || C->getZExtValue() != 0)
4359 if (Op.getValueType() == MVT::i64)
4360 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4362 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4372 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4376 // Grab the value and do some validation.
4377 uint64_t CVal = C->getZExtValue();
4378 switch (ConstraintLetter) {
4379 // The I constraint applies only to simple ADD or SUB immediate operands:
4380 // i.e. 0 to 4095 with optional shift by 12
4381 // The J constraint applies only to ADD or SUB immediates that would be
4382 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4383 // instruction [or vice versa], in other words -1 to -4095 with optional
4384 // left shift by 12.
4386 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4390 uint64_t NVal = -C->getSExtValue();
4391 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4392 CVal = C->getSExtValue();
4397 // The K and L constraints apply *only* to logical immediates, including
4398 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4399 // been removed and MOV should be used). So these constraints have to
4400 // distinguish between bit patterns that are valid 32-bit or 64-bit
4401 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4402 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4405 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4409 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4412 // The M and N constraints are a superset of K and L respectively, for use
4413 // with the MOV (immediate) alias. As well as the logical immediates they
4414 // also match 32 or 64-bit immediates that can be loaded either using a
4415 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4416 // (M) or 64-bit 0x1234000000000000 (N) etc.
4417 // As a note some of this code is liberally stolen from the asm parser.
4419 if (!isUInt<32>(CVal))
4421 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4423 if ((CVal & 0xFFFF) == CVal)
4425 if ((CVal & 0xFFFF0000ULL) == CVal)
4427 uint64_t NCVal = ~(uint32_t)CVal;
4428 if ((NCVal & 0xFFFFULL) == NCVal)
4430 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4435 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4437 if ((CVal & 0xFFFFULL) == CVal)
4439 if ((CVal & 0xFFFF0000ULL) == CVal)
4441 if ((CVal & 0xFFFF00000000ULL) == CVal)
4443 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4445 uint64_t NCVal = ~CVal;
4446 if ((NCVal & 0xFFFFULL) == NCVal)
4448 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4450 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4452 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4460 // All assembler immediates are 64-bit integers.
4461 Result = DAG.getTargetConstant(CVal, MVT::i64);
4465 if (Result.getNode()) {
4466 Ops.push_back(Result);
4470 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4473 //===----------------------------------------------------------------------===//
4474 // AArch64 Advanced SIMD Support
4475 //===----------------------------------------------------------------------===//
4477 /// WidenVector - Given a value in the V64 register class, produce the
4478 /// equivalent value in the V128 register class.
4479 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4480 EVT VT = V64Reg.getValueType();
4481 unsigned NarrowSize = VT.getVectorNumElements();
4482 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4483 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4486 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4487 V64Reg, DAG.getConstant(0, MVT::i32));
4490 /// getExtFactor - Determine the adjustment factor for the position when
4491 /// generating an "extract from vector registers" instruction.
4492 static unsigned getExtFactor(SDValue &V) {
4493 EVT EltType = V.getValueType().getVectorElementType();
4494 return EltType.getSizeInBits() / 8;
4497 /// NarrowVector - Given a value in the V128 register class, produce the
4498 /// equivalent value in the V64 register class.
4499 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4500 EVT VT = V128Reg.getValueType();
4501 unsigned WideSize = VT.getVectorNumElements();
4502 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4503 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4506 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4509 // Gather data to see if the operation can be modelled as a
4510 // shuffle in combination with VEXTs.
4511 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4512 SelectionDAG &DAG) const {
4513 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4515 EVT VT = Op.getValueType();
4516 unsigned NumElts = VT.getVectorNumElements();
4518 struct ShuffleSourceInfo {
4523 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4524 // be compatible with the shuffle we intend to construct. As a result
4525 // ShuffleVec will be some sliding window into the original Vec.
4528 // Code should guarantee that element i in Vec starts at element "WindowBase
4529 // + i * WindowScale in ShuffleVec".
4533 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4534 ShuffleSourceInfo(SDValue Vec)
4535 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4539 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4541 SmallVector<ShuffleSourceInfo, 2> Sources;
4542 for (unsigned i = 0; i < NumElts; ++i) {
4543 SDValue V = Op.getOperand(i);
4544 if (V.getOpcode() == ISD::UNDEF)
4546 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4547 // A shuffle can only come from building a vector from various
4548 // elements of other vectors.
4552 // Add this element source to the list if it's not already there.
4553 SDValue SourceVec = V.getOperand(0);
4554 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4555 if (Source == Sources.end())
4556 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4558 // Update the minimum and maximum lane number seen.
4559 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4560 Source->MinElt = std::min(Source->MinElt, EltNo);
4561 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4564 // Currently only do something sane when at most two source vectors
4566 if (Sources.size() > 2)
4569 // Find out the smallest element size among result and two sources, and use
4570 // it as element size to build the shuffle_vector.
4571 EVT SmallestEltTy = VT.getVectorElementType();
4572 for (auto &Source : Sources) {
4573 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4574 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4575 SmallestEltTy = SrcEltTy;
4578 unsigned ResMultiplier =
4579 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4580 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4581 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4583 // If the source vector is too wide or too narrow, we may nevertheless be able
4584 // to construct a compatible shuffle either by concatenating it with UNDEF or
4585 // extracting a suitable range of elements.
4586 for (auto &Src : Sources) {
4587 EVT SrcVT = Src.ShuffleVec.getValueType();
4589 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4592 // This stage of the search produces a source with the same element type as
4593 // the original, but with a total width matching the BUILD_VECTOR output.
4594 EVT EltVT = SrcVT.getVectorElementType();
4595 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4596 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4598 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4599 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4600 // We can pad out the smaller vector for free, so if it's part of a
4603 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4604 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4608 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4610 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4611 // Span too large for a VEXT to cope
4615 if (Src.MinElt >= NumSrcElts) {
4616 // The extraction can just take the second half
4618 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4619 DAG.getIntPtrConstant(NumSrcElts));
4620 Src.WindowBase = -NumSrcElts;
4621 } else if (Src.MaxElt < NumSrcElts) {
4622 // The extraction can just take the first half
4623 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4624 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4626 // An actual VEXT is needed
4627 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4628 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4630 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4631 DAG.getIntPtrConstant(NumSrcElts));
4632 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4634 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4635 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4636 Src.WindowBase = -Src.MinElt;
4640 // Another possible incompatibility occurs from the vector element types. We
4641 // can fix this by bitcasting the source vectors to the same type we intend
4643 for (auto &Src : Sources) {
4644 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4645 if (SrcEltTy == SmallestEltTy)
4647 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4648 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4649 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4650 Src.WindowBase *= Src.WindowScale;
4653 // Final sanity check before we try to actually produce a shuffle.
4655 for (auto Src : Sources)
4656 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4659 // The stars all align, our next step is to produce the mask for the shuffle.
4660 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4661 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4662 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4663 SDValue Entry = Op.getOperand(i);
4664 if (Entry.getOpcode() == ISD::UNDEF)
4667 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4668 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4670 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4671 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4673 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4674 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4675 VT.getVectorElementType().getSizeInBits());
4676 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4678 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4679 // starting at the appropriate offset.
4680 int *LaneMask = &Mask[i * ResMultiplier];
4682 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4683 ExtractBase += NumElts * (Src - Sources.begin());
4684 for (int j = 0; j < LanesDefined; ++j)
4685 LaneMask[j] = ExtractBase + j;
4688 // Final check before we try to produce nonsense...
4689 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4692 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4693 for (unsigned i = 0; i < Sources.size(); ++i)
4694 ShuffleOps[i] = Sources[i].ShuffleVec;
4696 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4697 ShuffleOps[1], &Mask[0]);
4698 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4701 // check if an EXT instruction can handle the shuffle mask when the
4702 // vector sources of the shuffle are the same.
4703 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4704 unsigned NumElts = VT.getVectorNumElements();
4706 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4712 // If this is a VEXT shuffle, the immediate value is the index of the first
4713 // element. The other shuffle indices must be the successive elements after
4715 unsigned ExpectedElt = Imm;
4716 for (unsigned i = 1; i < NumElts; ++i) {
4717 // Increment the expected index. If it wraps around, just follow it
4718 // back to index zero and keep going.
4720 if (ExpectedElt == NumElts)
4724 continue; // ignore UNDEF indices
4725 if (ExpectedElt != static_cast<unsigned>(M[i]))
4732 // check if an EXT instruction can handle the shuffle mask when the
4733 // vector sources of the shuffle are different.
4734 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4736 // Look for the first non-undef element.
4737 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4738 [](int Elt) {return Elt >= 0;});
4740 // Benefit form APInt to handle overflow when calculating expected element.
4741 unsigned NumElts = VT.getVectorNumElements();
4742 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4743 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4744 // The following shuffle indices must be the successive elements after the
4745 // first real element.
4746 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4747 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4748 if (FirstWrongElt != M.end())
4751 // The index of an EXT is the first element if it is not UNDEF.
4752 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4753 // value of the first element. E.g.
4754 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4755 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4756 // ExpectedElt is the last mask index plus 1.
4757 Imm = ExpectedElt.getZExtValue();
4759 // There are two difference cases requiring to reverse input vectors.
4760 // For example, for vector <4 x i32> we have the following cases,
4761 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4762 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4763 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4764 // to reverse two input vectors.
4773 /// isREVMask - Check if a vector shuffle corresponds to a REV
4774 /// instruction with the specified blocksize. (The order of the elements
4775 /// within each block of the vector is reversed.)
4776 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4777 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4778 "Only possible block sizes for REV are: 16, 32, 64");
4780 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4784 unsigned NumElts = VT.getVectorNumElements();
4785 unsigned BlockElts = M[0] + 1;
4786 // If the first shuffle index is UNDEF, be optimistic.
4788 BlockElts = BlockSize / EltSz;
4790 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4793 for (unsigned i = 0; i < NumElts; ++i) {
4795 continue; // ignore UNDEF indices
4796 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4803 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4804 unsigned NumElts = VT.getVectorNumElements();
4805 WhichResult = (M[0] == 0 ? 0 : 1);
4806 unsigned Idx = WhichResult * NumElts / 2;
4807 for (unsigned i = 0; i != NumElts; i += 2) {
4808 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4809 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4817 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4818 unsigned NumElts = VT.getVectorNumElements();
4819 WhichResult = (M[0] == 0 ? 0 : 1);
4820 for (unsigned i = 0; i != NumElts; ++i) {
4822 continue; // ignore UNDEF indices
4823 if ((unsigned)M[i] != 2 * i + WhichResult)
4830 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4831 unsigned NumElts = VT.getVectorNumElements();
4832 WhichResult = (M[0] == 0 ? 0 : 1);
4833 for (unsigned i = 0; i < NumElts; i += 2) {
4834 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4835 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4841 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4842 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4843 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4844 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4845 unsigned NumElts = VT.getVectorNumElements();
4846 WhichResult = (M[0] == 0 ? 0 : 1);
4847 unsigned Idx = WhichResult * NumElts / 2;
4848 for (unsigned i = 0; i != NumElts; i += 2) {
4849 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4850 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4858 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4859 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4860 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4861 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4862 unsigned Half = VT.getVectorNumElements() / 2;
4863 WhichResult = (M[0] == 0 ? 0 : 1);
4864 for (unsigned j = 0; j != 2; ++j) {
4865 unsigned Idx = WhichResult;
4866 for (unsigned i = 0; i != Half; ++i) {
4867 int MIdx = M[i + j * Half];
4868 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4877 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4878 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4879 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4880 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4881 unsigned NumElts = VT.getVectorNumElements();
4882 WhichResult = (M[0] == 0 ? 0 : 1);
4883 for (unsigned i = 0; i < NumElts; i += 2) {
4884 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4885 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4891 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4892 bool &DstIsLeft, int &Anomaly) {
4893 if (M.size() != static_cast<size_t>(NumInputElements))
4896 int NumLHSMatch = 0, NumRHSMatch = 0;
4897 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4899 for (int i = 0; i < NumInputElements; ++i) {
4909 LastLHSMismatch = i;
4911 if (M[i] == i + NumInputElements)
4914 LastRHSMismatch = i;
4917 if (NumLHSMatch == NumInputElements - 1) {
4919 Anomaly = LastLHSMismatch;
4921 } else if (NumRHSMatch == NumInputElements - 1) {
4923 Anomaly = LastRHSMismatch;
4930 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4931 if (VT.getSizeInBits() != 128)
4934 unsigned NumElts = VT.getVectorNumElements();
4936 for (int I = 0, E = NumElts / 2; I != E; I++) {
4941 int Offset = NumElts / 2;
4942 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4943 if (Mask[I] != I + SplitLHS * Offset)
4950 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4952 EVT VT = Op.getValueType();
4953 SDValue V0 = Op.getOperand(0);
4954 SDValue V1 = Op.getOperand(1);
4955 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4957 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4958 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4961 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4963 if (!isConcatMask(Mask, VT, SplitV0))
4966 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4967 VT.getVectorNumElements() / 2);
4969 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4970 DAG.getConstant(0, MVT::i64));
4972 if (V1.getValueType().getSizeInBits() == 128) {
4973 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4974 DAG.getConstant(0, MVT::i64));
4976 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4979 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4980 /// the specified operations to build the shuffle.
4981 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4982 SDValue RHS, SelectionDAG &DAG,
4984 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4985 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4986 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4989 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4998 OP_VUZPL, // VUZP, left result
4999 OP_VUZPR, // VUZP, right result
5000 OP_VZIPL, // VZIP, left result
5001 OP_VZIPR, // VZIP, right result
5002 OP_VTRNL, // VTRN, left result
5003 OP_VTRNR // VTRN, right result
5006 if (OpNum == OP_COPY) {
5007 if (LHSID == (1 * 9 + 2) * 9 + 3)
5009 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5013 SDValue OpLHS, OpRHS;
5014 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5015 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5016 EVT VT = OpLHS.getValueType();
5020 llvm_unreachable("Unknown shuffle opcode!");
5022 // VREV divides the vector in half and swaps within the half.
5023 if (VT.getVectorElementType() == MVT::i32 ||
5024 VT.getVectorElementType() == MVT::f32)
5025 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5026 // vrev <4 x i16> -> REV32
5027 if (VT.getVectorElementType() == MVT::i16 ||
5028 VT.getVectorElementType() == MVT::f16)
5029 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5030 // vrev <4 x i8> -> REV16
5031 assert(VT.getVectorElementType() == MVT::i8);
5032 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5037 EVT EltTy = VT.getVectorElementType();
5039 if (EltTy == MVT::i8)
5040 Opcode = AArch64ISD::DUPLANE8;
5041 else if (EltTy == MVT::i16)
5042 Opcode = AArch64ISD::DUPLANE16;
5043 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5044 Opcode = AArch64ISD::DUPLANE32;
5045 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5046 Opcode = AArch64ISD::DUPLANE64;
5048 llvm_unreachable("Invalid vector element type?");
5050 if (VT.getSizeInBits() == 64)
5051 OpLHS = WidenVector(OpLHS, DAG);
5052 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5053 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5058 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5059 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5060 DAG.getConstant(Imm, MVT::i32));
5063 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5066 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5069 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5072 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5075 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5078 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5083 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5084 SelectionDAG &DAG) {
5085 // Check to see if we can use the TBL instruction.
5086 SDValue V1 = Op.getOperand(0);
5087 SDValue V2 = Op.getOperand(1);
5090 EVT EltVT = Op.getValueType().getVectorElementType();
5091 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5093 SmallVector<SDValue, 8> TBLMask;
5094 for (int Val : ShuffleMask) {
5095 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5096 unsigned Offset = Byte + Val * BytesPerElt;
5097 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5101 MVT IndexVT = MVT::v8i8;
5102 unsigned IndexLen = 8;
5103 if (Op.getValueType().getSizeInBits() == 128) {
5104 IndexVT = MVT::v16i8;
5108 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5109 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5112 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5114 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5115 Shuffle = DAG.getNode(
5116 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5117 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5118 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5119 makeArrayRef(TBLMask.data(), IndexLen)));
5121 if (IndexLen == 8) {
5122 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5123 Shuffle = DAG.getNode(
5124 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5125 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5126 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5127 makeArrayRef(TBLMask.data(), IndexLen)));
5129 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5130 // cannot currently represent the register constraints on the input
5132 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5133 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5134 // &TBLMask[0], IndexLen));
5135 Shuffle = DAG.getNode(
5136 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5137 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5138 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5139 makeArrayRef(TBLMask.data(), IndexLen)));
5142 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5145 static unsigned getDUPLANEOp(EVT EltType) {
5146 if (EltType == MVT::i8)
5147 return AArch64ISD::DUPLANE8;
5148 if (EltType == MVT::i16 || EltType == MVT::f16)
5149 return AArch64ISD::DUPLANE16;
5150 if (EltType == MVT::i32 || EltType == MVT::f32)
5151 return AArch64ISD::DUPLANE32;
5152 if (EltType == MVT::i64 || EltType == MVT::f64)
5153 return AArch64ISD::DUPLANE64;
5155 llvm_unreachable("Invalid vector element type?");
5158 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5159 SelectionDAG &DAG) const {
5161 EVT VT = Op.getValueType();
5163 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5165 // Convert shuffles that are directly supported on NEON to target-specific
5166 // DAG nodes, instead of keeping them as shuffles and matching them again
5167 // during code selection. This is more efficient and avoids the possibility
5168 // of inconsistencies between legalization and selection.
5169 ArrayRef<int> ShuffleMask = SVN->getMask();
5171 SDValue V1 = Op.getOperand(0);
5172 SDValue V2 = Op.getOperand(1);
5174 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5175 V1.getValueType().getSimpleVT())) {
5176 int Lane = SVN->getSplatIndex();
5177 // If this is undef splat, generate it via "just" vdup, if possible.
5181 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5182 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5184 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5185 // constant. If so, we can just reference the lane's definition directly.
5186 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5187 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5188 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5190 // Otherwise, duplicate from the lane of the input vector.
5191 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5193 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5194 // to make a vector of the same size as this SHUFFLE. We can ignore the
5195 // extract entirely, and canonicalise the concat using WidenVector.
5196 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5197 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5198 V1 = V1.getOperand(0);
5199 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5200 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5201 Lane -= Idx * VT.getVectorNumElements() / 2;
5202 V1 = WidenVector(V1.getOperand(Idx), DAG);
5203 } else if (VT.getSizeInBits() == 64)
5204 V1 = WidenVector(V1, DAG);
5206 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5209 if (isREVMask(ShuffleMask, VT, 64))
5210 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5211 if (isREVMask(ShuffleMask, VT, 32))
5212 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5213 if (isREVMask(ShuffleMask, VT, 16))
5214 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5216 bool ReverseEXT = false;
5218 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5221 Imm *= getExtFactor(V1);
5222 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5223 DAG.getConstant(Imm, MVT::i32));
5224 } else if (V2->getOpcode() == ISD::UNDEF &&
5225 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5226 Imm *= getExtFactor(V1);
5227 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5228 DAG.getConstant(Imm, MVT::i32));
5231 unsigned WhichResult;
5232 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5233 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5234 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5236 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5237 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5238 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5240 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5241 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5242 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5245 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5246 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5247 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5249 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5250 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5251 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5253 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5254 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5255 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5258 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5259 if (Concat.getNode())
5264 int NumInputElements = V1.getValueType().getVectorNumElements();
5265 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5266 SDValue DstVec = DstIsLeft ? V1 : V2;
5267 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5269 SDValue SrcVec = V1;
5270 int SrcLane = ShuffleMask[Anomaly];
5271 if (SrcLane >= NumInputElements) {
5273 SrcLane -= VT.getVectorNumElements();
5275 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5277 EVT ScalarVT = VT.getVectorElementType();
5279 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5280 ScalarVT = MVT::i32;
5283 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5284 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5288 // If the shuffle is not directly supported and it has 4 elements, use
5289 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5290 unsigned NumElts = VT.getVectorNumElements();
5292 unsigned PFIndexes[4];
5293 for (unsigned i = 0; i != 4; ++i) {
5294 if (ShuffleMask[i] < 0)
5297 PFIndexes[i] = ShuffleMask[i];
5300 // Compute the index in the perfect shuffle table.
5301 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5302 PFIndexes[2] * 9 + PFIndexes[3];
5303 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5304 unsigned Cost = (PFEntry >> 30);
5307 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5310 return GenerateTBL(Op, ShuffleMask, DAG);
5313 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5315 EVT VT = BVN->getValueType(0);
5316 APInt SplatBits, SplatUndef;
5317 unsigned SplatBitSize;
5319 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5320 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5322 for (unsigned i = 0; i < NumSplats; ++i) {
5323 CnstBits <<= SplatBitSize;
5324 UndefBits <<= SplatBitSize;
5325 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5326 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5335 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5336 SelectionDAG &DAG) const {
5337 BuildVectorSDNode *BVN =
5338 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5339 SDValue LHS = Op.getOperand(0);
5341 EVT VT = Op.getValueType();
5346 APInt CnstBits(VT.getSizeInBits(), 0);
5347 APInt UndefBits(VT.getSizeInBits(), 0);
5348 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5349 // We only have BIC vector immediate instruction, which is and-not.
5350 CnstBits = ~CnstBits;
5352 // We make use of a little bit of goto ickiness in order to avoid having to
5353 // duplicate the immediate matching logic for the undef toggled case.
5354 bool SecondTry = false;
5357 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5358 CnstBits = CnstBits.zextOrTrunc(64);
5359 uint64_t CnstVal = CnstBits.getZExtValue();
5361 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5362 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5363 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5364 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5365 DAG.getConstant(CnstVal, MVT::i32),
5366 DAG.getConstant(0, MVT::i32));
5367 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5370 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5371 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5372 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5373 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5374 DAG.getConstant(CnstVal, MVT::i32),
5375 DAG.getConstant(8, MVT::i32));
5376 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5379 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5380 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5381 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5382 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5383 DAG.getConstant(CnstVal, MVT::i32),
5384 DAG.getConstant(16, MVT::i32));
5385 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5388 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5389 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5391 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5392 DAG.getConstant(CnstVal, MVT::i32),
5393 DAG.getConstant(24, MVT::i32));
5394 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5397 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5400 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5401 DAG.getConstant(CnstVal, MVT::i32),
5402 DAG.getConstant(0, MVT::i32));
5403 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5406 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5409 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5410 DAG.getConstant(CnstVal, MVT::i32),
5411 DAG.getConstant(8, MVT::i32));
5412 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5419 CnstBits = ~UndefBits;
5423 // We can always fall back to a non-immediate AND.
5428 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5429 // consists of only the same constant int value, returned in reference arg
5431 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5432 uint64_t &ConstVal) {
5433 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5436 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5439 EVT VT = Bvec->getValueType(0);
5440 unsigned NumElts = VT.getVectorNumElements();
5441 for (unsigned i = 1; i < NumElts; ++i)
5442 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5444 ConstVal = FirstElt->getZExtValue();
5448 static unsigned getIntrinsicID(const SDNode *N) {
5449 unsigned Opcode = N->getOpcode();
5452 return Intrinsic::not_intrinsic;
5453 case ISD::INTRINSIC_WO_CHAIN: {
5454 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5455 if (IID < Intrinsic::num_intrinsics)
5457 return Intrinsic::not_intrinsic;
5462 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5463 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5464 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5465 // Also, logical shift right -> sri, with the same structure.
5466 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5467 EVT VT = N->getValueType(0);
5474 // Is the first op an AND?
5475 const SDValue And = N->getOperand(0);
5476 if (And.getOpcode() != ISD::AND)
5479 // Is the second op an shl or lshr?
5480 SDValue Shift = N->getOperand(1);
5481 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5482 // or AArch64ISD::VLSHR vector, #shift
5483 unsigned ShiftOpc = Shift.getOpcode();
5484 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5486 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5488 // Is the shift amount constant?
5489 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5493 // Is the and mask vector all constant?
5495 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5498 // Is C1 == ~C2, taking into account how much one can shift elements of a
5500 uint64_t C2 = C2node->getZExtValue();
5501 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5502 if (C2 > ElemSizeInBits)
5504 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5505 if ((C1 & ElemMask) != (~C2 & ElemMask))
5508 SDValue X = And.getOperand(0);
5509 SDValue Y = Shift.getOperand(0);
5512 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5514 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5515 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5517 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5518 DEBUG(N->dump(&DAG));
5519 DEBUG(dbgs() << "into: \n");
5520 DEBUG(ResultSLI->dump(&DAG));
5526 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5527 SelectionDAG &DAG) const {
5528 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5529 if (EnableAArch64SlrGeneration) {
5530 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5535 BuildVectorSDNode *BVN =
5536 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5537 SDValue LHS = Op.getOperand(1);
5539 EVT VT = Op.getValueType();
5541 // OR commutes, so try swapping the operands.
5543 LHS = Op.getOperand(0);
5544 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5549 APInt CnstBits(VT.getSizeInBits(), 0);
5550 APInt UndefBits(VT.getSizeInBits(), 0);
5551 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5552 // We make use of a little bit of goto ickiness in order to avoid having to
5553 // duplicate the immediate matching logic for the undef toggled case.
5554 bool SecondTry = false;
5557 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5558 CnstBits = CnstBits.zextOrTrunc(64);
5559 uint64_t CnstVal = CnstBits.getZExtValue();
5561 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5562 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5563 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5564 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5565 DAG.getConstant(CnstVal, MVT::i32),
5566 DAG.getConstant(0, MVT::i32));
5567 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5570 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5571 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5572 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5573 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5574 DAG.getConstant(CnstVal, MVT::i32),
5575 DAG.getConstant(8, MVT::i32));
5576 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5579 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5580 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5581 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5582 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5583 DAG.getConstant(CnstVal, MVT::i32),
5584 DAG.getConstant(16, MVT::i32));
5585 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5588 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5589 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5590 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5591 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5592 DAG.getConstant(CnstVal, MVT::i32),
5593 DAG.getConstant(24, MVT::i32));
5594 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5597 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5598 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5599 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5600 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5601 DAG.getConstant(CnstVal, MVT::i32),
5602 DAG.getConstant(0, MVT::i32));
5603 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5606 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5607 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5608 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5609 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5610 DAG.getConstant(CnstVal, MVT::i32),
5611 DAG.getConstant(8, MVT::i32));
5612 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5619 CnstBits = UndefBits;
5623 // We can always fall back to a non-immediate OR.
5628 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5629 // be truncated to fit element width.
5630 static SDValue NormalizeBuildVector(SDValue Op,
5631 SelectionDAG &DAG) {
5632 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5634 EVT VT = Op.getValueType();
5635 EVT EltTy= VT.getVectorElementType();
5637 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5640 SmallVector<SDValue, 16> Ops;
5641 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5642 SDValue Lane = Op.getOperand(I);
5643 if (Lane.getOpcode() == ISD::Constant) {
5644 APInt LowBits(EltTy.getSizeInBits(),
5645 cast<ConstantSDNode>(Lane)->getZExtValue());
5646 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5648 Ops.push_back(Lane);
5650 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5653 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5654 SelectionDAG &DAG) const {
5656 EVT VT = Op.getValueType();
5657 Op = NormalizeBuildVector(Op, DAG);
5658 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5660 APInt CnstBits(VT.getSizeInBits(), 0);
5661 APInt UndefBits(VT.getSizeInBits(), 0);
5662 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5663 // We make use of a little bit of goto ickiness in order to avoid having to
5664 // duplicate the immediate matching logic for the undef toggled case.
5665 bool SecondTry = false;
5668 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5669 CnstBits = CnstBits.zextOrTrunc(64);
5670 uint64_t CnstVal = CnstBits.getZExtValue();
5672 // Certain magic vector constants (used to express things like NOT
5673 // and NEG) are passed through unmodified. This allows codegen patterns
5674 // for these operations to match. Special-purpose patterns will lower
5675 // these immediates to MOVIs if it proves necessary.
5676 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5679 // The many faces of MOVI...
5680 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5681 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5682 if (VT.getSizeInBits() == 128) {
5683 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5684 DAG.getConstant(CnstVal, MVT::i32));
5685 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5688 // Support the V64 version via subregister insertion.
5689 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5690 DAG.getConstant(CnstVal, MVT::i32));
5691 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5694 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5695 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5696 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5697 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5698 DAG.getConstant(CnstVal, MVT::i32),
5699 DAG.getConstant(0, MVT::i32));
5700 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5703 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5704 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5705 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5706 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5707 DAG.getConstant(CnstVal, MVT::i32),
5708 DAG.getConstant(8, MVT::i32));
5709 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5712 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5713 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5714 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5715 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5716 DAG.getConstant(CnstVal, MVT::i32),
5717 DAG.getConstant(16, MVT::i32));
5718 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5721 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5722 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5723 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5724 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5725 DAG.getConstant(CnstVal, MVT::i32),
5726 DAG.getConstant(24, MVT::i32));
5727 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5730 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5731 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5732 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5733 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5734 DAG.getConstant(CnstVal, MVT::i32),
5735 DAG.getConstant(0, MVT::i32));
5736 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5739 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5740 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5741 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5742 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5743 DAG.getConstant(CnstVal, MVT::i32),
5744 DAG.getConstant(8, MVT::i32));
5745 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5748 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5749 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5750 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5751 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5752 DAG.getConstant(CnstVal, MVT::i32),
5753 DAG.getConstant(264, MVT::i32));
5754 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5757 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5758 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5759 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5760 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5761 DAG.getConstant(CnstVal, MVT::i32),
5762 DAG.getConstant(272, MVT::i32));
5763 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5766 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5767 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5768 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5769 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5770 DAG.getConstant(CnstVal, MVT::i32));
5771 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5774 // The few faces of FMOV...
5775 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5776 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5777 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5778 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5779 DAG.getConstant(CnstVal, MVT::i32));
5780 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5783 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5784 VT.getSizeInBits() == 128) {
5785 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5786 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5787 DAG.getConstant(CnstVal, MVT::i32));
5788 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5791 // The many faces of MVNI...
5793 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5794 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5795 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5796 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5797 DAG.getConstant(CnstVal, MVT::i32),
5798 DAG.getConstant(0, MVT::i32));
5799 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5802 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5803 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5804 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5805 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5806 DAG.getConstant(CnstVal, MVT::i32),
5807 DAG.getConstant(8, MVT::i32));
5808 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5811 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5812 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5813 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5814 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5815 DAG.getConstant(CnstVal, MVT::i32),
5816 DAG.getConstant(16, MVT::i32));
5817 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5820 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5821 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5822 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5823 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5824 DAG.getConstant(CnstVal, MVT::i32),
5825 DAG.getConstant(24, MVT::i32));
5826 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5829 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5830 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5831 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5832 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5833 DAG.getConstant(CnstVal, MVT::i32),
5834 DAG.getConstant(0, MVT::i32));
5835 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5838 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5839 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5840 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5841 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5842 DAG.getConstant(CnstVal, MVT::i32),
5843 DAG.getConstant(8, MVT::i32));
5844 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5847 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5848 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5849 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5850 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5851 DAG.getConstant(CnstVal, MVT::i32),
5852 DAG.getConstant(264, MVT::i32));
5853 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5856 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5857 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5858 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5859 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5860 DAG.getConstant(CnstVal, MVT::i32),
5861 DAG.getConstant(272, MVT::i32));
5862 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5869 CnstBits = UndefBits;
5874 // Scan through the operands to find some interesting properties we can
5876 // 1) If only one value is used, we can use a DUP, or
5877 // 2) if only the low element is not undef, we can just insert that, or
5878 // 3) if only one constant value is used (w/ some non-constant lanes),
5879 // we can splat the constant value into the whole vector then fill
5880 // in the non-constant lanes.
5881 // 4) FIXME: If different constant values are used, but we can intelligently
5882 // select the values we'll be overwriting for the non-constant
5883 // lanes such that we can directly materialize the vector
5884 // some other way (MOVI, e.g.), we can be sneaky.
5885 unsigned NumElts = VT.getVectorNumElements();
5886 bool isOnlyLowElement = true;
5887 bool usesOnlyOneValue = true;
5888 bool usesOnlyOneConstantValue = true;
5889 bool isConstant = true;
5890 unsigned NumConstantLanes = 0;
5892 SDValue ConstantValue;
5893 for (unsigned i = 0; i < NumElts; ++i) {
5894 SDValue V = Op.getOperand(i);
5895 if (V.getOpcode() == ISD::UNDEF)
5898 isOnlyLowElement = false;
5899 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5902 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5904 if (!ConstantValue.getNode())
5906 else if (ConstantValue != V)
5907 usesOnlyOneConstantValue = false;
5910 if (!Value.getNode())
5912 else if (V != Value)
5913 usesOnlyOneValue = false;
5916 if (!Value.getNode())
5917 return DAG.getUNDEF(VT);
5919 if (isOnlyLowElement)
5920 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5922 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5923 // i32 and try again.
5924 if (usesOnlyOneValue) {
5926 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5927 Value.getValueType() != VT)
5928 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5930 // This is actually a DUPLANExx operation, which keeps everything vectory.
5932 // DUPLANE works on 128-bit vectors, widen it if necessary.
5933 SDValue Lane = Value.getOperand(1);
5934 Value = Value.getOperand(0);
5935 if (Value.getValueType().getSizeInBits() == 64)
5936 Value = WidenVector(Value, DAG);
5938 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5939 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5942 if (VT.getVectorElementType().isFloatingPoint()) {
5943 SmallVector<SDValue, 8> Ops;
5945 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5946 for (unsigned i = 0; i < NumElts; ++i)
5947 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5948 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5949 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5950 Val = LowerBUILD_VECTOR(Val, DAG);
5952 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5956 // If there was only one constant value used and for more than one lane,
5957 // start by splatting that value, then replace the non-constant lanes. This
5958 // is better than the default, which will perform a separate initialization
5960 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5961 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5962 // Now insert the non-constant lanes.
5963 for (unsigned i = 0; i < NumElts; ++i) {
5964 SDValue V = Op.getOperand(i);
5965 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5966 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5967 // Note that type legalization likely mucked about with the VT of the
5968 // source operand, so we may have to convert it here before inserting.
5969 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5975 // If all elements are constants and the case above didn't get hit, fall back
5976 // to the default expansion, which will generate a load from the constant
5981 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5983 SDValue shuffle = ReconstructShuffle(Op, DAG);
5984 if (shuffle != SDValue())
5988 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5989 // know the default expansion would otherwise fall back on something even
5990 // worse. For a vector with one or two non-undef values, that's
5991 // scalar_to_vector for the elements followed by a shuffle (provided the
5992 // shuffle is valid for the target) and materialization element by element
5993 // on the stack followed by a load for everything else.
5994 if (!isConstant && !usesOnlyOneValue) {
5995 SDValue Vec = DAG.getUNDEF(VT);
5996 SDValue Op0 = Op.getOperand(0);
5997 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5999 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6000 // a) Avoid a RMW dependency on the full vector register, and
6001 // b) Allow the register coalescer to fold away the copy if the
6002 // value is already in an S or D register.
6003 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6004 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6006 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6007 DAG.getTargetConstant(SubIdx, MVT::i32));
6008 Vec = SDValue(N, 0);
6011 for (; i < NumElts; ++i) {
6012 SDValue V = Op.getOperand(i);
6013 if (V.getOpcode() == ISD::UNDEF)
6015 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
6016 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6021 // Just use the default expansion. We failed to find a better alternative.
6025 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6026 SelectionDAG &DAG) const {
6027 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6029 // Check for non-constant or out of range lane.
6030 EVT VT = Op.getOperand(0).getValueType();
6031 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6032 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6036 // Insertion/extraction are legal for V128 types.
6037 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6038 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6042 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6043 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6046 // For V64 types, we perform insertion by expanding the value
6047 // to a V128 type and perform the insertion on that.
6049 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6050 EVT WideTy = WideVec.getValueType();
6052 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6053 Op.getOperand(1), Op.getOperand(2));
6054 // Re-narrow the resultant vector.
6055 return NarrowVector(Node, DAG);
6059 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6060 SelectionDAG &DAG) const {
6061 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6063 // Check for non-constant or out of range lane.
6064 EVT VT = Op.getOperand(0).getValueType();
6065 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6066 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6070 // Insertion/extraction are legal for V128 types.
6071 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6072 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6076 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6077 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6080 // For V64 types, we perform extraction by expanding the value
6081 // to a V128 type and perform the extraction on that.
6083 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6084 EVT WideTy = WideVec.getValueType();
6086 EVT ExtrTy = WideTy.getVectorElementType();
6087 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6090 // For extractions, we just return the result directly.
6091 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6095 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6096 SelectionDAG &DAG) const {
6097 EVT VT = Op.getOperand(0).getValueType();
6103 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6106 unsigned Val = Cst->getZExtValue();
6108 unsigned Size = Op.getValueType().getSizeInBits();
6112 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6115 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6118 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6121 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6124 llvm_unreachable("Unexpected vector type in extract_subvector!");
6127 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6129 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6135 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6137 if (VT.getVectorNumElements() == 4 &&
6138 (VT.is128BitVector() || VT.is64BitVector())) {
6139 unsigned PFIndexes[4];
6140 for (unsigned i = 0; i != 4; ++i) {
6144 PFIndexes[i] = M[i];
6147 // Compute the index in the perfect shuffle table.
6148 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6149 PFIndexes[2] * 9 + PFIndexes[3];
6150 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6151 unsigned Cost = (PFEntry >> 30);
6159 unsigned DummyUnsigned;
6161 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6162 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6163 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6164 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6165 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6166 isZIPMask(M, VT, DummyUnsigned) ||
6167 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6168 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6169 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6170 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6171 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6174 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6175 /// operand of a vector shift operation, where all the elements of the
6176 /// build_vector must have the same constant integer value.
6177 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6178 // Ignore bit_converts.
6179 while (Op.getOpcode() == ISD::BITCAST)
6180 Op = Op.getOperand(0);
6181 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6182 APInt SplatBits, SplatUndef;
6183 unsigned SplatBitSize;
6185 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6186 HasAnyUndefs, ElementBits) ||
6187 SplatBitSize > ElementBits)
6189 Cnt = SplatBits.getSExtValue();
6193 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6194 /// operand of a vector shift left operation. That value must be in the range:
6195 /// 0 <= Value < ElementBits for a left shift; or
6196 /// 0 <= Value <= ElementBits for a long left shift.
6197 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6198 assert(VT.isVector() && "vector shift count is not a vector type");
6199 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6200 if (!getVShiftImm(Op, ElementBits, Cnt))
6202 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6205 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6206 /// operand of a vector shift right operation. For a shift opcode, the value
6207 /// is positive, but for an intrinsic the value count must be negative. The
6208 /// absolute value must be in the range:
6209 /// 1 <= |Value| <= ElementBits for a right shift; or
6210 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6211 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6213 assert(VT.isVector() && "vector shift count is not a vector type");
6214 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6215 if (!getVShiftImm(Op, ElementBits, Cnt))
6219 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6222 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6223 SelectionDAG &DAG) const {
6224 EVT VT = Op.getValueType();
6228 if (!Op.getOperand(1).getValueType().isVector())
6230 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6232 switch (Op.getOpcode()) {
6234 llvm_unreachable("unexpected shift opcode");
6237 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6238 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6239 DAG.getConstant(Cnt, MVT::i32));
6240 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6241 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6242 Op.getOperand(0), Op.getOperand(1));
6245 // Right shift immediate
6246 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6249 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6250 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6251 DAG.getConstant(Cnt, MVT::i32));
6254 // Right shift register. Note, there is not a shift right register
6255 // instruction, but the shift left register instruction takes a signed
6256 // value, where negative numbers specify a right shift.
6257 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6258 : Intrinsic::aarch64_neon_ushl;
6259 // negate the shift amount
6260 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6261 SDValue NegShiftLeft =
6262 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6263 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6264 return NegShiftLeft;
6270 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6271 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6272 SDLoc dl, SelectionDAG &DAG) {
6273 EVT SrcVT = LHS.getValueType();
6275 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6276 APInt CnstBits(VT.getSizeInBits(), 0);
6277 APInt UndefBits(VT.getSizeInBits(), 0);
6278 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6279 bool IsZero = IsCnst && (CnstBits == 0);
6281 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6285 case AArch64CC::NE: {
6288 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6290 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6291 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6295 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6296 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6299 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6300 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6303 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6304 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6307 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6308 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6312 // If we ignore NaNs then we can use to the MI implementation.
6316 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6317 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6324 case AArch64CC::NE: {
6327 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6329 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6330 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6334 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6335 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6338 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6339 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6342 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6343 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6346 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6347 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6349 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6351 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6354 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6355 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6357 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6359 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6363 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6364 SelectionDAG &DAG) const {
6365 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6366 SDValue LHS = Op.getOperand(0);
6367 SDValue RHS = Op.getOperand(1);
6370 if (LHS.getValueType().getVectorElementType().isInteger()) {
6371 assert(LHS.getValueType() == RHS.getValueType());
6372 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6373 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
6377 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6378 LHS.getValueType().getVectorElementType() == MVT::f64);
6380 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6381 // clean. Some of them require two branches to implement.
6382 AArch64CC::CondCode CC1, CC2;
6384 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6386 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6388 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
6392 if (CC2 != AArch64CC::AL) {
6394 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
6395 if (!Cmp2.getNode())
6398 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
6402 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6407 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6408 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6409 /// specified in the intrinsic calls.
6410 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6412 unsigned Intrinsic) const {
6413 switch (Intrinsic) {
6414 case Intrinsic::aarch64_neon_ld2:
6415 case Intrinsic::aarch64_neon_ld3:
6416 case Intrinsic::aarch64_neon_ld4:
6417 case Intrinsic::aarch64_neon_ld1x2:
6418 case Intrinsic::aarch64_neon_ld1x3:
6419 case Intrinsic::aarch64_neon_ld1x4:
6420 case Intrinsic::aarch64_neon_ld2lane:
6421 case Intrinsic::aarch64_neon_ld3lane:
6422 case Intrinsic::aarch64_neon_ld4lane:
6423 case Intrinsic::aarch64_neon_ld2r:
6424 case Intrinsic::aarch64_neon_ld3r:
6425 case Intrinsic::aarch64_neon_ld4r: {
6426 Info.opc = ISD::INTRINSIC_W_CHAIN;
6427 // Conservatively set memVT to the entire set of vectors loaded.
6428 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6429 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6430 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6433 Info.vol = false; // volatile loads with NEON intrinsics not supported
6434 Info.readMem = true;
6435 Info.writeMem = false;
6438 case Intrinsic::aarch64_neon_st2:
6439 case Intrinsic::aarch64_neon_st3:
6440 case Intrinsic::aarch64_neon_st4:
6441 case Intrinsic::aarch64_neon_st1x2:
6442 case Intrinsic::aarch64_neon_st1x3:
6443 case Intrinsic::aarch64_neon_st1x4:
6444 case Intrinsic::aarch64_neon_st2lane:
6445 case Intrinsic::aarch64_neon_st3lane:
6446 case Intrinsic::aarch64_neon_st4lane: {
6447 Info.opc = ISD::INTRINSIC_VOID;
6448 // Conservatively set memVT to the entire set of vectors stored.
6449 unsigned NumElts = 0;
6450 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6451 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6452 if (!ArgTy->isVectorTy())
6454 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6456 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6457 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6460 Info.vol = false; // volatile stores with NEON intrinsics not supported
6461 Info.readMem = false;
6462 Info.writeMem = true;
6465 case Intrinsic::aarch64_ldaxr:
6466 case Intrinsic::aarch64_ldxr: {
6467 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6468 Info.opc = ISD::INTRINSIC_W_CHAIN;
6469 Info.memVT = MVT::getVT(PtrTy->getElementType());
6470 Info.ptrVal = I.getArgOperand(0);
6472 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6474 Info.readMem = true;
6475 Info.writeMem = false;
6478 case Intrinsic::aarch64_stlxr:
6479 case Intrinsic::aarch64_stxr: {
6480 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6481 Info.opc = ISD::INTRINSIC_W_CHAIN;
6482 Info.memVT = MVT::getVT(PtrTy->getElementType());
6483 Info.ptrVal = I.getArgOperand(1);
6485 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6487 Info.readMem = false;
6488 Info.writeMem = true;
6491 case Intrinsic::aarch64_ldaxp:
6492 case Intrinsic::aarch64_ldxp: {
6493 Info.opc = ISD::INTRINSIC_W_CHAIN;
6494 Info.memVT = MVT::i128;
6495 Info.ptrVal = I.getArgOperand(0);
6499 Info.readMem = true;
6500 Info.writeMem = false;
6503 case Intrinsic::aarch64_stlxp:
6504 case Intrinsic::aarch64_stxp: {
6505 Info.opc = ISD::INTRINSIC_W_CHAIN;
6506 Info.memVT = MVT::i128;
6507 Info.ptrVal = I.getArgOperand(2);
6511 Info.readMem = false;
6512 Info.writeMem = true;
6522 // Truncations from 64-bit GPR to 32-bit GPR is free.
6523 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6524 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6526 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6527 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6528 return NumBits1 > NumBits2;
6530 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6531 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6533 unsigned NumBits1 = VT1.getSizeInBits();
6534 unsigned NumBits2 = VT2.getSizeInBits();
6535 return NumBits1 > NumBits2;
6538 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6540 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6541 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6543 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6544 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6545 return NumBits1 == 32 && NumBits2 == 64;
6547 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6548 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6550 unsigned NumBits1 = VT1.getSizeInBits();
6551 unsigned NumBits2 = VT2.getSizeInBits();
6552 return NumBits1 == 32 && NumBits2 == 64;
6555 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6556 EVT VT1 = Val.getValueType();
6557 if (isZExtFree(VT1, VT2)) {
6561 if (Val.getOpcode() != ISD::LOAD)
6564 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6565 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6566 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6567 VT1.getSizeInBits() <= 32);
6570 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6571 unsigned &RequiredAligment) const {
6572 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6574 // Cyclone supports unaligned accesses.
6575 RequiredAligment = 0;
6576 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6577 return NumBits == 32 || NumBits == 64;
6580 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6581 unsigned &RequiredAligment) const {
6582 if (!LoadedType.isSimple() ||
6583 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6585 // Cyclone supports unaligned accesses.
6586 RequiredAligment = 0;
6587 unsigned NumBits = LoadedType.getSizeInBits();
6588 return NumBits == 32 || NumBits == 64;
6591 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6592 unsigned AlignCheck) {
6593 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6594 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6597 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6598 unsigned SrcAlign, bool IsMemset,
6601 MachineFunction &MF) const {
6602 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6603 // instruction to materialize the v2i64 zero and one store (with restrictive
6604 // addressing mode). Just do two i64 store of zero-registers.
6606 const Function *F = MF.getFunction();
6607 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6608 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6609 Attribute::NoImplicitFloat) &&
6610 (memOpAlign(SrcAlign, DstAlign, 16) ||
6611 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6614 return Size >= 8 ? MVT::i64 : MVT::i32;
6617 // 12-bit optionally shifted immediates are legal for adds.
6618 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6619 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6624 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6625 // immediates is the same as for an add or a sub.
6626 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6629 return isLegalAddImmediate(Immed);
6632 /// isLegalAddressingMode - Return true if the addressing mode represented
6633 /// by AM is legal for this target, for a load/store of the specified type.
6634 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6636 // AArch64 has five basic addressing modes:
6638 // reg + 9-bit signed offset
6639 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6641 // reg + SIZE_IN_BYTES * reg
6643 // No global is ever allowed as a base.
6647 // No reg+reg+imm addressing.
6648 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6651 // check reg + imm case:
6652 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6653 uint64_t NumBytes = 0;
6654 if (Ty->isSized()) {
6655 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6656 NumBytes = NumBits / 8;
6657 if (!isPowerOf2_64(NumBits))
6662 int64_t Offset = AM.BaseOffs;
6664 // 9-bit signed offset
6665 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6668 // 12-bit unsigned offset
6669 unsigned shift = Log2_64(NumBytes);
6670 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6671 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6672 (Offset >> shift) << shift == Offset)
6677 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6679 if (!AM.Scale || AM.Scale == 1 ||
6680 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6685 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6687 // Scaling factors are not free at all.
6688 // Operands | Rt Latency
6689 // -------------------------------------------
6691 // -------------------------------------------
6692 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6693 // Rt, [Xn, Wm, <extend> #imm] |
6694 if (isLegalAddressingMode(AM, Ty))
6695 // Scale represents reg2 * scale, thus account for 1 if
6696 // it is not equal to 0 or 1.
6697 return AM.Scale != 0 && AM.Scale != 1;
6701 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6702 VT = VT.getScalarType();
6707 switch (VT.getSimpleVT().SimpleTy) {
6719 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6720 // LR is a callee-save register, but we must treat it as clobbered by any call
6721 // site. Hence we include LR in the scratch registers, which are in turn added
6722 // as implicit-defs for stackmaps and patchpoints.
6723 static const MCPhysReg ScratchRegs[] = {
6724 AArch64::X16, AArch64::X17, AArch64::LR, 0
6730 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6731 EVT VT = N->getValueType(0);
6732 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6733 // it with shift to let it be lowered to UBFX.
6734 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6735 isa<ConstantSDNode>(N->getOperand(1))) {
6736 uint64_t TruncMask = N->getConstantOperandVal(1);
6737 if (isMask_64(TruncMask) &&
6738 N->getOperand(0).getOpcode() == ISD::SRL &&
6739 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6745 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6747 assert(Ty->isIntegerTy());
6749 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6753 int64_t Val = Imm.getSExtValue();
6754 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6757 if ((int64_t)Val < 0)
6760 Val &= (1LL << 32) - 1;
6762 unsigned LZ = countLeadingZeros((uint64_t)Val);
6763 unsigned Shift = (63 - LZ) / 16;
6764 // MOVZ is free so return true for one or fewer MOVK.
6765 return (Shift < 3) ? true : false;
6768 // Generate SUBS and CSEL for integer abs.
6769 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6770 EVT VT = N->getValueType(0);
6772 SDValue N0 = N->getOperand(0);
6773 SDValue N1 = N->getOperand(1);
6776 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6777 // and change it to SUB and CSEL.
6778 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6779 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6780 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6781 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6782 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6783 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6785 // Generate SUBS & CSEL.
6787 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6788 N0.getOperand(0), DAG.getConstant(0, VT));
6789 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6790 DAG.getConstant(AArch64CC::PL, MVT::i32),
6791 SDValue(Cmp.getNode(), 1));
6796 // performXorCombine - Attempts to handle integer ABS.
6797 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6798 TargetLowering::DAGCombinerInfo &DCI,
6799 const AArch64Subtarget *Subtarget) {
6800 if (DCI.isBeforeLegalizeOps())
6803 return performIntegerAbsCombine(N, DAG);
6807 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6809 std::vector<SDNode *> *Created) const {
6810 // fold (sdiv X, pow2)
6811 EVT VT = N->getValueType(0);
6812 if ((VT != MVT::i32 && VT != MVT::i64) ||
6813 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6817 SDValue N0 = N->getOperand(0);
6818 unsigned Lg2 = Divisor.countTrailingZeros();
6819 SDValue Zero = DAG.getConstant(0, VT);
6820 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6822 // Add (N0 < 0) ? Pow2 - 1 : 0;
6824 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6825 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6826 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6829 Created->push_back(Cmp.getNode());
6830 Created->push_back(Add.getNode());
6831 Created->push_back(CSel.getNode());
6836 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6838 // If we're dividing by a positive value, we're done. Otherwise, we must
6839 // negate the result.
6840 if (Divisor.isNonNegative())
6844 Created->push_back(SRA.getNode());
6845 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6848 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6849 TargetLowering::DAGCombinerInfo &DCI,
6850 const AArch64Subtarget *Subtarget) {
6851 if (DCI.isBeforeLegalizeOps())
6854 // Multiplication of a power of two plus/minus one can be done more
6855 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6856 // future CPUs have a cheaper MADD instruction, this may need to be
6857 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6858 // 64-bit is 5 cycles, so this is always a win.
6859 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6860 APInt Value = C->getAPIntValue();
6861 EVT VT = N->getValueType(0);
6862 if (Value.isNonNegative()) {
6863 // (mul x, 2^N + 1) => (add (shl x, N), x)
6864 APInt VM1 = Value - 1;
6865 if (VM1.isPowerOf2()) {
6866 SDValue ShiftedVal =
6867 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6868 DAG.getConstant(VM1.logBase2(), MVT::i64));
6869 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6872 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6873 APInt VP1 = Value + 1;
6874 if (VP1.isPowerOf2()) {
6875 SDValue ShiftedVal =
6876 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6877 DAG.getConstant(VP1.logBase2(), MVT::i64));
6878 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6882 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6883 APInt VNM1 = -Value - 1;
6884 if (VNM1.isPowerOf2()) {
6885 SDValue ShiftedVal =
6886 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6887 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6889 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6890 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6892 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6893 APInt VNP1 = -Value + 1;
6894 if (VNP1.isPowerOf2()) {
6895 SDValue ShiftedVal =
6896 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6897 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6898 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6906 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6907 SelectionDAG &DAG) {
6908 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6909 // optimize away operation when it's from a constant.
6911 // The general transformation is:
6912 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6913 // AND(VECTOR_CMP(x,y), constant2)
6914 // constant2 = UNARYOP(constant)
6916 // Early exit if this isn't a vector operation, the operand of the
6917 // unary operation isn't a bitwise AND, or if the sizes of the operations
6919 EVT VT = N->getValueType(0);
6920 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6921 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6922 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6925 // Now check that the other operand of the AND is a constant. We could
6926 // make the transformation for non-constant splats as well, but it's unclear
6927 // that would be a benefit as it would not eliminate any operations, just
6928 // perform one more step in scalar code before moving to the vector unit.
6929 if (BuildVectorSDNode *BV =
6930 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6931 // Bail out if the vector isn't a constant.
6932 if (!BV->isConstant())
6935 // Everything checks out. Build up the new and improved node.
6937 EVT IntVT = BV->getValueType(0);
6938 // Create a new constant of the appropriate type for the transformed
6940 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6941 // The AND node needs bitcasts to/from an integer vector type around it.
6942 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6943 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6944 N->getOperand(0)->getOperand(0), MaskConst);
6945 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6952 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6953 // First try to optimize away the conversion when it's conditionally from
6954 // a constant. Vectors only.
6955 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6956 if (Res != SDValue())
6959 EVT VT = N->getValueType(0);
6960 if (VT != MVT::f32 && VT != MVT::f64)
6963 // Only optimize when the source and destination types have the same width.
6964 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6967 // If the result of an integer load is only used by an integer-to-float
6968 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6969 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6970 SDValue N0 = N->getOperand(0);
6971 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6972 // Do not change the width of a volatile load.
6973 !cast<LoadSDNode>(N0)->isVolatile()) {
6974 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6975 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6976 LN0->getPointerInfo(), LN0->isVolatile(),
6977 LN0->isNonTemporal(), LN0->isInvariant(),
6978 LN0->getAlignment());
6980 // Make sure successors of the original load stay after it by updating them
6981 // to use the new Chain.
6982 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6985 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6986 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6992 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6993 /// searches for and classifies those shifts.
6994 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6996 if (N.getOpcode() == ISD::SHL)
6998 else if (N.getOpcode() == ISD::SRL)
7003 if (!isa<ConstantSDNode>(N.getOperand(1)))
7006 ShiftAmount = N->getConstantOperandVal(1);
7007 Src = N->getOperand(0);
7011 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7012 /// registers viewed as a high/low pair. This function looks for the pattern:
7013 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7014 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7016 static SDValue tryCombineToEXTR(SDNode *N,
7017 TargetLowering::DAGCombinerInfo &DCI) {
7018 SelectionDAG &DAG = DCI.DAG;
7020 EVT VT = N->getValueType(0);
7022 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7024 if (VT != MVT::i32 && VT != MVT::i64)
7028 uint32_t ShiftLHS = 0;
7030 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7034 uint32_t ShiftRHS = 0;
7036 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7039 // If they're both trying to come from the high part of the register, they're
7040 // not really an EXTR.
7041 if (LHSFromHi == RHSFromHi)
7044 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7048 std::swap(LHS, RHS);
7049 std::swap(ShiftLHS, ShiftRHS);
7052 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7053 DAG.getConstant(ShiftRHS, MVT::i64));
7056 static SDValue tryCombineToBSL(SDNode *N,
7057 TargetLowering::DAGCombinerInfo &DCI) {
7058 EVT VT = N->getValueType(0);
7059 SelectionDAG &DAG = DCI.DAG;
7065 SDValue N0 = N->getOperand(0);
7066 if (N0.getOpcode() != ISD::AND)
7069 SDValue N1 = N->getOperand(1);
7070 if (N1.getOpcode() != ISD::AND)
7073 // We only have to look for constant vectors here since the general, variable
7074 // case can be handled in TableGen.
7075 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7076 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7077 for (int i = 1; i >= 0; --i)
7078 for (int j = 1; j >= 0; --j) {
7079 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7080 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7084 bool FoundMatch = true;
7085 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7086 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7087 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7089 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7096 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7097 N0->getOperand(1 - i), N1->getOperand(1 - j));
7103 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7104 const AArch64Subtarget *Subtarget) {
7105 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7106 if (!EnableAArch64ExtrGeneration)
7108 SelectionDAG &DAG = DCI.DAG;
7109 EVT VT = N->getValueType(0);
7111 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7114 SDValue Res = tryCombineToEXTR(N, DCI);
7118 Res = tryCombineToBSL(N, DCI);
7125 static SDValue performBitcastCombine(SDNode *N,
7126 TargetLowering::DAGCombinerInfo &DCI,
7127 SelectionDAG &DAG) {
7128 // Wait 'til after everything is legalized to try this. That way we have
7129 // legal vector types and such.
7130 if (DCI.isBeforeLegalizeOps())
7133 // Remove extraneous bitcasts around an extract_subvector.
7135 // (v4i16 (bitconvert
7136 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7138 // (extract_subvector ((v8i16 ...), (i64 4)))
7140 // Only interested in 64-bit vectors as the ultimate result.
7141 EVT VT = N->getValueType(0);
7144 if (VT.getSimpleVT().getSizeInBits() != 64)
7146 // Is the operand an extract_subvector starting at the beginning or halfway
7147 // point of the vector? A low half may also come through as an
7148 // EXTRACT_SUBREG, so look for that, too.
7149 SDValue Op0 = N->getOperand(0);
7150 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7151 !(Op0->isMachineOpcode() &&
7152 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7154 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7155 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7156 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7158 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7159 if (idx != AArch64::dsub)
7161 // The dsub reference is equivalent to a lane zero subvector reference.
7164 // Look through the bitcast of the input to the extract.
7165 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7167 SDValue Source = Op0->getOperand(0)->getOperand(0);
7168 // If the source type has twice the number of elements as our destination
7169 // type, we know this is an extract of the high or low half of the vector.
7170 EVT SVT = Source->getValueType(0);
7171 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7174 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7176 // Create the simplified form to just extract the low or high half of the
7177 // vector directly rather than bothering with the bitcasts.
7179 unsigned NumElements = VT.getVectorNumElements();
7181 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7182 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7184 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7185 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7191 static SDValue performConcatVectorsCombine(SDNode *N,
7192 TargetLowering::DAGCombinerInfo &DCI,
7193 SelectionDAG &DAG) {
7194 // Wait 'til after everything is legalized to try this. That way we have
7195 // legal vector types and such.
7196 if (DCI.isBeforeLegalizeOps())
7200 EVT VT = N->getValueType(0);
7202 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7203 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7204 // canonicalise to that.
7205 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
7206 assert(VT.getVectorElementType().getSizeInBits() == 64);
7207 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
7208 WidenVector(N->getOperand(0), DAG),
7209 DAG.getConstant(0, MVT::i64));
7212 // Canonicalise concat_vectors so that the right-hand vector has as few
7213 // bit-casts as possible before its real operation. The primary matching
7214 // destination for these operations will be the narrowing "2" instructions,
7215 // which depend on the operation being performed on this right-hand vector.
7217 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7219 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7221 SDValue Op1 = N->getOperand(1);
7222 if (Op1->getOpcode() != ISD::BITCAST)
7224 SDValue RHS = Op1->getOperand(0);
7225 MVT RHSTy = RHS.getValueType().getSimpleVT();
7226 // If the RHS is not a vector, this is not the pattern we're looking for.
7227 if (!RHSTy.isVector())
7230 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7232 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7233 RHSTy.getVectorNumElements() * 2);
7235 ISD::BITCAST, dl, VT,
7236 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7237 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
7240 static SDValue tryCombineFixedPointConvert(SDNode *N,
7241 TargetLowering::DAGCombinerInfo &DCI,
7242 SelectionDAG &DAG) {
7243 // Wait 'til after everything is legalized to try this. That way we have
7244 // legal vector types and such.
7245 if (DCI.isBeforeLegalizeOps())
7247 // Transform a scalar conversion of a value from a lane extract into a
7248 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7249 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7250 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7252 // The second form interacts better with instruction selection and the
7253 // register allocator to avoid cross-class register copies that aren't
7254 // coalescable due to a lane reference.
7256 // Check the operand and see if it originates from a lane extract.
7257 SDValue Op1 = N->getOperand(1);
7258 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7259 // Yep, no additional predication needed. Perform the transform.
7260 SDValue IID = N->getOperand(0);
7261 SDValue Shift = N->getOperand(2);
7262 SDValue Vec = Op1.getOperand(0);
7263 SDValue Lane = Op1.getOperand(1);
7264 EVT ResTy = N->getValueType(0);
7268 // The vector width should be 128 bits by the time we get here, even
7269 // if it started as 64 bits (the extract_vector handling will have
7271 assert(Vec.getValueType().getSizeInBits() == 128 &&
7272 "unexpected vector size on extract_vector_elt!");
7273 if (Vec.getValueType() == MVT::v4i32)
7274 VecResTy = MVT::v4f32;
7275 else if (Vec.getValueType() == MVT::v2i64)
7276 VecResTy = MVT::v2f64;
7278 llvm_unreachable("unexpected vector type!");
7281 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7282 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7287 // AArch64 high-vector "long" operations are formed by performing the non-high
7288 // version on an extract_subvector of each operand which gets the high half:
7290 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7292 // However, there are cases which don't have an extract_high explicitly, but
7293 // have another operation that can be made compatible with one for free. For
7296 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7298 // This routine does the actual conversion of such DUPs, once outer routines
7299 // have determined that everything else is in order.
7300 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7301 // We can handle most types of duplicate, but the lane ones have an extra
7302 // operand saying *which* lane, so we need to know.
7304 switch (N.getOpcode()) {
7305 case AArch64ISD::DUP:
7308 case AArch64ISD::DUPLANE8:
7309 case AArch64ISD::DUPLANE16:
7310 case AArch64ISD::DUPLANE32:
7311 case AArch64ISD::DUPLANE64:
7318 MVT NarrowTy = N.getSimpleValueType();
7319 if (!NarrowTy.is64BitVector())
7322 MVT ElementTy = NarrowTy.getVectorElementType();
7323 unsigned NumElems = NarrowTy.getVectorNumElements();
7324 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7328 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7331 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7333 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7334 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7337 static bool isEssentiallyExtractSubvector(SDValue N) {
7338 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7341 return N.getOpcode() == ISD::BITCAST &&
7342 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7345 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7346 struct GenericSetCCInfo {
7347 const SDValue *Opnd0;
7348 const SDValue *Opnd1;
7352 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7353 struct AArch64SetCCInfo {
7355 AArch64CC::CondCode CC;
7358 /// \brief Helper structure to keep track of SetCC information.
7360 GenericSetCCInfo Generic;
7361 AArch64SetCCInfo AArch64;
7364 /// \brief Helper structure to be able to read SetCC information. If set to
7365 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7366 /// GenericSetCCInfo.
7367 struct SetCCInfoAndKind {
7372 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7374 /// AArch64 lowered one.
7375 /// \p SetCCInfo is filled accordingly.
7376 /// \post SetCCInfo is meanginfull only when this function returns true.
7377 /// \return True when Op is a kind of SET_CC operation.
7378 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7379 // If this is a setcc, this is straight forward.
7380 if (Op.getOpcode() == ISD::SETCC) {
7381 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7382 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7383 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7384 SetCCInfo.IsAArch64 = false;
7387 // Otherwise, check if this is a matching csel instruction.
7391 if (Op.getOpcode() != AArch64ISD::CSEL)
7393 // Set the information about the operands.
7394 // TODO: we want the operands of the Cmp not the csel
7395 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7396 SetCCInfo.IsAArch64 = true;
7397 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7398 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7400 // Check that the operands matches the constraints:
7401 // (1) Both operands must be constants.
7402 // (2) One must be 1 and the other must be 0.
7403 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7404 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7407 if (!TValue || !FValue)
7411 if (!TValue->isOne()) {
7412 // Update the comparison when we are interested in !cc.
7413 std::swap(TValue, FValue);
7414 SetCCInfo.Info.AArch64.CC =
7415 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7417 return TValue->isOne() && FValue->isNullValue();
7420 // Returns true if Op is setcc or zext of setcc.
7421 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7422 if (isSetCC(Op, Info))
7424 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7425 isSetCC(Op->getOperand(0), Info));
7428 // The folding we want to perform is:
7429 // (add x, [zext] (setcc cc ...) )
7431 // (csel x, (add x, 1), !cc ...)
7433 // The latter will get matched to a CSINC instruction.
7434 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7435 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7436 SDValue LHS = Op->getOperand(0);
7437 SDValue RHS = Op->getOperand(1);
7438 SetCCInfoAndKind InfoAndKind;
7440 // If neither operand is a SET_CC, give up.
7441 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7442 std::swap(LHS, RHS);
7443 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7447 // FIXME: This could be generatized to work for FP comparisons.
7448 EVT CmpVT = InfoAndKind.IsAArch64
7449 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7450 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7451 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7457 if (InfoAndKind.IsAArch64) {
7458 CCVal = DAG.getConstant(
7459 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7460 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7462 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7463 *InfoAndKind.Info.Generic.Opnd1,
7464 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7467 EVT VT = Op->getValueType(0);
7468 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7469 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7472 // The basic add/sub long vector instructions have variants with "2" on the end
7473 // which act on the high-half of their inputs. They are normally matched by
7476 // (add (zeroext (extract_high LHS)),
7477 // (zeroext (extract_high RHS)))
7478 // -> uaddl2 vD, vN, vM
7480 // However, if one of the extracts is something like a duplicate, this
7481 // instruction can still be used profitably. This function puts the DAG into a
7482 // more appropriate form for those patterns to trigger.
7483 static SDValue performAddSubLongCombine(SDNode *N,
7484 TargetLowering::DAGCombinerInfo &DCI,
7485 SelectionDAG &DAG) {
7486 if (DCI.isBeforeLegalizeOps())
7489 MVT VT = N->getSimpleValueType(0);
7490 if (!VT.is128BitVector()) {
7491 if (N->getOpcode() == ISD::ADD)
7492 return performSetccAddFolding(N, DAG);
7496 // Make sure both branches are extended in the same way.
7497 SDValue LHS = N->getOperand(0);
7498 SDValue RHS = N->getOperand(1);
7499 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7500 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7501 LHS.getOpcode() != RHS.getOpcode())
7504 unsigned ExtType = LHS.getOpcode();
7506 // It's not worth doing if at least one of the inputs isn't already an
7507 // extract, but we don't know which it'll be so we have to try both.
7508 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7509 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7513 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7514 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7515 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7519 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7522 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7525 // Massage DAGs which we can use the high-half "long" operations on into
7526 // something isel will recognize better. E.g.
7528 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7529 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7530 // (extract_high (v2i64 (dup128 scalar)))))
7532 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7533 TargetLowering::DAGCombinerInfo &DCI,
7534 SelectionDAG &DAG) {
7535 if (DCI.isBeforeLegalizeOps())
7538 SDValue LHS = N->getOperand(1);
7539 SDValue RHS = N->getOperand(2);
7540 assert(LHS.getValueType().is64BitVector() &&
7541 RHS.getValueType().is64BitVector() &&
7542 "unexpected shape for long operation");
7544 // Either node could be a DUP, but it's not worth doing both of them (you'd
7545 // just as well use the non-high version) so look for a corresponding extract
7546 // operation on the other "wing".
7547 if (isEssentiallyExtractSubvector(LHS)) {
7548 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7551 } else if (isEssentiallyExtractSubvector(RHS)) {
7552 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7557 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7558 N->getOperand(0), LHS, RHS);
7561 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7562 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7563 unsigned ElemBits = ElemTy.getSizeInBits();
7565 int64_t ShiftAmount;
7566 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7567 APInt SplatValue, SplatUndef;
7568 unsigned SplatBitSize;
7570 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7571 HasAnyUndefs, ElemBits) ||
7572 SplatBitSize != ElemBits)
7575 ShiftAmount = SplatValue.getSExtValue();
7576 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7577 ShiftAmount = CVN->getSExtValue();
7585 llvm_unreachable("Unknown shift intrinsic");
7586 case Intrinsic::aarch64_neon_sqshl:
7587 Opcode = AArch64ISD::SQSHL_I;
7588 IsRightShift = false;
7590 case Intrinsic::aarch64_neon_uqshl:
7591 Opcode = AArch64ISD::UQSHL_I;
7592 IsRightShift = false;
7594 case Intrinsic::aarch64_neon_srshl:
7595 Opcode = AArch64ISD::SRSHR_I;
7596 IsRightShift = true;
7598 case Intrinsic::aarch64_neon_urshl:
7599 Opcode = AArch64ISD::URSHR_I;
7600 IsRightShift = true;
7602 case Intrinsic::aarch64_neon_sqshlu:
7603 Opcode = AArch64ISD::SQSHLU_I;
7604 IsRightShift = false;
7608 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7609 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7610 DAG.getConstant(-ShiftAmount, MVT::i32));
7611 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7612 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7613 DAG.getConstant(ShiftAmount, MVT::i32));
7618 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7619 // the intrinsics must be legal and take an i32, this means there's almost
7620 // certainly going to be a zext in the DAG which we can eliminate.
7621 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7622 SDValue AndN = N->getOperand(2);
7623 if (AndN.getOpcode() != ISD::AND)
7626 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7627 if (!CMask || CMask->getZExtValue() != Mask)
7630 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7631 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7634 static SDValue performIntrinsicCombine(SDNode *N,
7635 TargetLowering::DAGCombinerInfo &DCI,
7636 const AArch64Subtarget *Subtarget) {
7637 SelectionDAG &DAG = DCI.DAG;
7638 unsigned IID = getIntrinsicID(N);
7642 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7643 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7644 return tryCombineFixedPointConvert(N, DCI, DAG);
7646 case Intrinsic::aarch64_neon_fmax:
7647 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7648 N->getOperand(1), N->getOperand(2));
7649 case Intrinsic::aarch64_neon_fmin:
7650 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7651 N->getOperand(1), N->getOperand(2));
7652 case Intrinsic::aarch64_neon_smull:
7653 case Intrinsic::aarch64_neon_umull:
7654 case Intrinsic::aarch64_neon_pmull:
7655 case Intrinsic::aarch64_neon_sqdmull:
7656 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7657 case Intrinsic::aarch64_neon_sqshl:
7658 case Intrinsic::aarch64_neon_uqshl:
7659 case Intrinsic::aarch64_neon_sqshlu:
7660 case Intrinsic::aarch64_neon_srshl:
7661 case Intrinsic::aarch64_neon_urshl:
7662 return tryCombineShiftImm(IID, N, DAG);
7663 case Intrinsic::aarch64_crc32b:
7664 case Intrinsic::aarch64_crc32cb:
7665 return tryCombineCRC32(0xff, N, DAG);
7666 case Intrinsic::aarch64_crc32h:
7667 case Intrinsic::aarch64_crc32ch:
7668 return tryCombineCRC32(0xffff, N, DAG);
7673 static SDValue performExtendCombine(SDNode *N,
7674 TargetLowering::DAGCombinerInfo &DCI,
7675 SelectionDAG &DAG) {
7676 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7677 // we can convert that DUP into another extract_high (of a bigger DUP), which
7678 // helps the backend to decide that an sabdl2 would be useful, saving a real
7679 // extract_high operation.
7680 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7681 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7682 SDNode *ABDNode = N->getOperand(0).getNode();
7683 unsigned IID = getIntrinsicID(ABDNode);
7684 if (IID == Intrinsic::aarch64_neon_sabd ||
7685 IID == Intrinsic::aarch64_neon_uabd) {
7686 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7687 if (!NewABD.getNode())
7690 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7695 // This is effectively a custom type legalization for AArch64.
7697 // Type legalization will split an extend of a small, legal, type to a larger
7698 // illegal type by first splitting the destination type, often creating
7699 // illegal source types, which then get legalized in isel-confusing ways,
7700 // leading to really terrible codegen. E.g.,
7701 // %result = v8i32 sext v8i8 %value
7703 // %losrc = extract_subreg %value, ...
7704 // %hisrc = extract_subreg %value, ...
7705 // %lo = v4i32 sext v4i8 %losrc
7706 // %hi = v4i32 sext v4i8 %hisrc
7707 // Things go rapidly downhill from there.
7709 // For AArch64, the [sz]ext vector instructions can only go up one element
7710 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7711 // take two instructions.
7713 // This implies that the most efficient way to do the extend from v8i8
7714 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7715 // the normal splitting to happen for the v8i16->v8i32.
7717 // This is pre-legalization to catch some cases where the default
7718 // type legalization will create ill-tempered code.
7719 if (!DCI.isBeforeLegalizeOps())
7722 // We're only interested in cleaning things up for non-legal vector types
7723 // here. If both the source and destination are legal, things will just
7724 // work naturally without any fiddling.
7725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7726 EVT ResVT = N->getValueType(0);
7727 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7729 // If the vector type isn't a simple VT, it's beyond the scope of what
7730 // we're worried about here. Let legalization do its thing and hope for
7732 SDValue Src = N->getOperand(0);
7733 EVT SrcVT = Src->getValueType(0);
7734 if (!ResVT.isSimple() || !SrcVT.isSimple())
7737 // If the source VT is a 64-bit vector, we can play games and get the
7738 // better results we want.
7739 if (SrcVT.getSizeInBits() != 64)
7742 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7743 unsigned ElementCount = SrcVT.getVectorNumElements();
7744 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7746 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7748 // Now split the rest of the operation into two halves, each with a 64
7752 unsigned NumElements = ResVT.getVectorNumElements();
7753 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7754 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7755 ResVT.getVectorElementType(), NumElements / 2);
7757 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7758 LoVT.getVectorNumElements());
7759 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7760 DAG.getIntPtrConstant(0));
7761 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7762 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7763 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7764 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7766 // Now combine the parts back together so we still have a single result
7767 // like the combiner expects.
7768 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7771 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7772 /// value. The load store optimizer pass will merge them to store pair stores.
7773 /// This has better performance than a splat of the scalar followed by a split
7774 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7775 /// followed by an ext.b and two stores.
7776 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7777 SDValue StVal = St->getValue();
7778 EVT VT = StVal.getValueType();
7780 // Don't replace floating point stores, they possibly won't be transformed to
7781 // stp because of the store pair suppress pass.
7782 if (VT.isFloatingPoint())
7785 // Check for insert vector elements.
7786 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7789 // We can express a splat as store pair(s) for 2 or 4 elements.
7790 unsigned NumVecElts = VT.getVectorNumElements();
7791 if (NumVecElts != 4 && NumVecElts != 2)
7793 SDValue SplatVal = StVal.getOperand(1);
7794 unsigned RemainInsertElts = NumVecElts - 1;
7796 // Check that this is a splat.
7797 while (--RemainInsertElts) {
7798 SDValue NextInsertElt = StVal.getOperand(0);
7799 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7801 if (NextInsertElt.getOperand(1) != SplatVal)
7803 StVal = NextInsertElt;
7805 unsigned OrigAlignment = St->getAlignment();
7806 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7807 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7809 // Create scalar stores. This is at least as good as the code sequence for a
7810 // split unaligned store wich is a dup.s, ext.b, and two stores.
7811 // Most of the time the three stores should be replaced by store pair
7812 // instructions (stp).
7814 SDValue BasePtr = St->getBasePtr();
7816 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7817 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7819 unsigned Offset = EltOffset;
7820 while (--NumVecElts) {
7821 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7822 DAG.getConstant(Offset, MVT::i64));
7823 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7824 St->getPointerInfo(), St->isVolatile(),
7825 St->isNonTemporal(), Alignment);
7826 Offset += EltOffset;
7831 static SDValue performSTORECombine(SDNode *N,
7832 TargetLowering::DAGCombinerInfo &DCI,
7834 const AArch64Subtarget *Subtarget) {
7835 if (!DCI.isBeforeLegalize())
7838 StoreSDNode *S = cast<StoreSDNode>(N);
7839 if (S->isVolatile())
7842 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7843 // page boundries. We want to split such stores.
7844 if (!Subtarget->isCyclone())
7847 // Don't split at Oz.
7848 MachineFunction &MF = DAG.getMachineFunction();
7849 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7850 AttributeSet::FunctionIndex, Attribute::MinSize);
7854 SDValue StVal = S->getValue();
7855 EVT VT = StVal.getValueType();
7857 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7858 // those up regresses performance on micro-benchmarks and olden/bh.
7859 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7862 // Split unaligned 16B stores. They are terrible for performance.
7863 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7864 // extensions can use this to mark that it does not want splitting to happen
7865 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7866 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7867 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7868 S->getAlignment() <= 2)
7871 // If we get a splat of a scalar convert this vector store to a store of
7872 // scalars. They will be merged into store pairs thereby removing two
7874 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7875 if (ReplacedSplat != SDValue())
7876 return ReplacedSplat;
7879 unsigned NumElts = VT.getVectorNumElements() / 2;
7880 // Split VT into two.
7882 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7883 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7884 DAG.getIntPtrConstant(0));
7885 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7886 DAG.getIntPtrConstant(NumElts));
7887 SDValue BasePtr = S->getBasePtr();
7889 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7890 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7891 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7892 DAG.getConstant(8, MVT::i64));
7893 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7894 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7898 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7899 /// post-increment LD1R.
7900 static SDValue performPostLD1Combine(SDNode *N,
7901 TargetLowering::DAGCombinerInfo &DCI,
7903 if (DCI.isBeforeLegalizeOps())
7906 SelectionDAG &DAG = DCI.DAG;
7907 EVT VT = N->getValueType(0);
7909 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7910 SDNode *LD = N->getOperand(LoadIdx).getNode();
7911 // If it is not LOAD, can not do such combine.
7912 if (LD->getOpcode() != ISD::LOAD)
7915 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7916 EVT MemVT = LoadSDN->getMemoryVT();
7917 // Check if memory operand is the same type as the vector element.
7918 if (MemVT != VT.getVectorElementType())
7921 // Check if there are other uses. If so, do not combine as it will introduce
7923 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7925 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7931 SDValue Addr = LD->getOperand(1);
7932 SDValue Vector = N->getOperand(0);
7933 // Search for a use of the address operand that is an increment.
7934 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7935 Addr.getNode()->use_end(); UI != UE; ++UI) {
7937 if (User->getOpcode() != ISD::ADD
7938 || UI.getUse().getResNo() != Addr.getResNo())
7941 // Check that the add is independent of the load. Otherwise, folding it
7942 // would create a cycle.
7943 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7945 // Also check that add is not used in the vector operand. This would also
7947 if (User->isPredecessorOf(Vector.getNode()))
7950 // If the increment is a constant, it must match the memory ref size.
7951 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7952 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7953 uint32_t IncVal = CInc->getZExtValue();
7954 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7955 if (IncVal != NumBytes)
7957 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7960 SmallVector<SDValue, 8> Ops;
7961 Ops.push_back(LD->getOperand(0)); // Chain
7963 Ops.push_back(Vector); // The vector to be inserted
7964 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7966 Ops.push_back(Addr);
7969 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7970 SDVTList SDTys = DAG.getVTList(Tys);
7971 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7972 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7974 LoadSDN->getMemOperand());
7977 std::vector<SDValue> NewResults;
7978 NewResults.push_back(SDValue(LD, 0)); // The result of load
7979 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7980 DCI.CombineTo(LD, NewResults);
7981 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7982 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7989 /// Target-specific DAG combine function for NEON load/store intrinsics
7990 /// to merge base address updates.
7991 static SDValue performNEONPostLDSTCombine(SDNode *N,
7992 TargetLowering::DAGCombinerInfo &DCI,
7993 SelectionDAG &DAG) {
7994 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7997 unsigned AddrOpIdx = N->getNumOperands() - 1;
7998 SDValue Addr = N->getOperand(AddrOpIdx);
8000 // Search for a use of the address operand that is an increment.
8001 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8002 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8004 if (User->getOpcode() != ISD::ADD ||
8005 UI.getUse().getResNo() != Addr.getResNo())
8008 // Check that the add is independent of the load/store. Otherwise, folding
8009 // it would create a cycle.
8010 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8013 // Find the new opcode for the updating load/store.
8014 bool IsStore = false;
8015 bool IsLaneOp = false;
8016 bool IsDupOp = false;
8017 unsigned NewOpc = 0;
8018 unsigned NumVecs = 0;
8019 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8021 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8022 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8024 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8026 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8028 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8029 NumVecs = 2; IsStore = true; break;
8030 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8031 NumVecs = 3; IsStore = true; break;
8032 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8033 NumVecs = 4; IsStore = true; break;
8034 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8036 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8038 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8040 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8041 NumVecs = 2; IsStore = true; break;
8042 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8043 NumVecs = 3; IsStore = true; break;
8044 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8045 NumVecs = 4; IsStore = true; break;
8046 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8047 NumVecs = 2; IsDupOp = true; break;
8048 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8049 NumVecs = 3; IsDupOp = true; break;
8050 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8051 NumVecs = 4; IsDupOp = true; break;
8052 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8053 NumVecs = 2; IsLaneOp = true; break;
8054 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8055 NumVecs = 3; IsLaneOp = true; break;
8056 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8057 NumVecs = 4; IsLaneOp = true; break;
8058 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8059 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8060 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8061 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8062 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8063 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8068 VecTy = N->getOperand(2).getValueType();
8070 VecTy = N->getValueType(0);
8072 // If the increment is a constant, it must match the memory ref size.
8073 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8074 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8075 uint32_t IncVal = CInc->getZExtValue();
8076 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8077 if (IsLaneOp || IsDupOp)
8078 NumBytes /= VecTy.getVectorNumElements();
8079 if (IncVal != NumBytes)
8081 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8083 SmallVector<SDValue, 8> Ops;
8084 Ops.push_back(N->getOperand(0)); // Incoming chain
8085 // Load lane and store have vector list as input.
8086 if (IsLaneOp || IsStore)
8087 for (unsigned i = 2; i < AddrOpIdx; ++i)
8088 Ops.push_back(N->getOperand(i));
8089 Ops.push_back(Addr); // Base register
8094 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8096 for (n = 0; n < NumResultVecs; ++n)
8098 Tys[n++] = MVT::i64; // Type of write back register
8099 Tys[n] = MVT::Other; // Type of the chain
8100 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8102 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8103 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8104 MemInt->getMemoryVT(),
8105 MemInt->getMemOperand());
8108 std::vector<SDValue> NewResults;
8109 for (unsigned i = 0; i < NumResultVecs; ++i) {
8110 NewResults.push_back(SDValue(UpdN.getNode(), i));
8112 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8113 DCI.CombineTo(N, NewResults);
8114 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8121 // Checks to see if the value is the prescribed width and returns information
8122 // about its extension mode.
8124 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8125 ExtType = ISD::NON_EXTLOAD;
8126 switch(V.getNode()->getOpcode()) {
8130 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8131 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8132 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8133 ExtType = LoadNode->getExtensionType();
8138 case ISD::AssertSext: {
8139 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8140 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8141 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8142 ExtType = ISD::SEXTLOAD;
8147 case ISD::AssertZext: {
8148 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8149 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8150 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8151 ExtType = ISD::ZEXTLOAD;
8157 case ISD::TargetConstant: {
8158 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8168 // This function does a whole lot of voodoo to determine if the tests are
8169 // equivalent without and with a mask. Essentially what happens is that given a
8172 // +-------------+ +-------------+ +-------------+ +-------------+
8173 // | Input | | AddConstant | | CompConstant| | CC |
8174 // +-------------+ +-------------+ +-------------+ +-------------+
8176 // V V | +----------+
8177 // +-------------+ +----+ | |
8178 // | ADD | |0xff| | |
8179 // +-------------+ +----+ | |
8182 // +-------------+ | |
8184 // +-------------+ | |
8193 // The AND node may be safely removed for some combinations of inputs. In
8194 // particular we need to take into account the extension type of the Input,
8195 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8196 // width of the input (this can work for any width inputs, the above graph is
8197 // specific to 8 bits.
8199 // The specific equations were worked out by generating output tables for each
8200 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8201 // problem was simplified by working with 4 bit inputs, which means we only
8202 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8203 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8204 // patterns present in both extensions (0,7). For every distinct set of
8205 // AddConstant and CompConstants bit patterns we can consider the masked and
8206 // unmasked versions to be equivalent if the result of this function is true for
8207 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8210 // and w10, w8, #0x0f
8212 // cset w9, AArch64CC
8214 // cset w11, AArch64CC
8219 // Since the above function shows when the outputs are equivalent it defines
8220 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8221 // would be expensive to run during compiles. The equations below were written
8222 // in a test harness that confirmed they gave equivalent outputs to the above
8223 // for all inputs function, so they can be used determine if the removal is
8226 // isEquivalentMaskless() is the code for testing if the AND can be removed
8227 // factored out of the DAG recognition as the DAG can take several forms.
8230 bool isEquivalentMaskless(unsigned CC, unsigned width,
8231 ISD::LoadExtType ExtType, signed AddConstant,
8232 signed CompConstant) {
8233 // By being careful about our equations and only writing the in term
8234 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8235 // make them generally applicable to all bit widths.
8236 signed MaxUInt = (1 << width);
8238 // For the purposes of these comparisons sign extending the type is
8239 // equivalent to zero extending the add and displacing it by half the integer
8240 // width. Provided we are careful and make sure our equations are valid over
8241 // the whole range we can just adjust the input and avoid writing equations
8242 // for sign extended inputs.
8243 if (ExtType == ISD::SEXTLOAD)
8244 AddConstant -= (1 << (width-1));
8248 case AArch64CC::GT: {
8249 if ((AddConstant == 0) ||
8250 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8251 (AddConstant >= 0 && CompConstant < 0) ||
8252 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8256 case AArch64CC::GE: {
8257 if ((AddConstant == 0) ||
8258 (AddConstant >= 0 && CompConstant <= 0) ||
8259 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8263 case AArch64CC::LS: {
8264 if ((AddConstant >= 0 && CompConstant < 0) ||
8265 (AddConstant <= 0 && CompConstant >= -1 &&
8266 CompConstant < AddConstant + MaxUInt))
8270 case AArch64CC::MI: {
8271 if ((AddConstant == 0) ||
8272 (AddConstant > 0 && CompConstant <= 0) ||
8273 (AddConstant < 0 && CompConstant <= AddConstant))
8277 case AArch64CC::HS: {
8278 if ((AddConstant >= 0 && CompConstant <= 0) ||
8279 (AddConstant <= 0 && CompConstant >= 0 &&
8280 CompConstant <= AddConstant + MaxUInt))
8284 case AArch64CC::NE: {
8285 if ((AddConstant > 0 && CompConstant < 0) ||
8286 (AddConstant < 0 && CompConstant >= 0 &&
8287 CompConstant < AddConstant + MaxUInt) ||
8288 (AddConstant >= 0 && CompConstant >= 0 &&
8289 CompConstant >= AddConstant) ||
8290 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8299 case AArch64CC::Invalid:
8307 SDValue performCONDCombine(SDNode *N,
8308 TargetLowering::DAGCombinerInfo &DCI,
8309 SelectionDAG &DAG, unsigned CCIndex,
8310 unsigned CmpIndex) {
8311 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8312 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8313 unsigned CondOpcode = SubsNode->getOpcode();
8315 if (CondOpcode != AArch64ISD::SUBS)
8318 // There is a SUBS feeding this condition. Is it fed by a mask we can
8321 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8322 unsigned MaskBits = 0;
8324 if (AndNode->getOpcode() != ISD::AND)
8327 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8328 uint32_t CNV = CN->getZExtValue();
8331 else if (CNV == 65535)
8338 SDValue AddValue = AndNode->getOperand(0);
8340 if (AddValue.getOpcode() != ISD::ADD)
8343 // The basic dag structure is correct, grab the inputs and validate them.
8345 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8346 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8347 SDValue SubsInputValue = SubsNode->getOperand(1);
8349 // The mask is present and the provenance of all the values is a smaller type,
8350 // lets see if the mask is superfluous.
8352 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8353 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8356 ISD::LoadExtType ExtType;
8358 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8359 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8360 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8363 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8364 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8365 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8368 // The AND is not necessary, remove it.
8370 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8371 SubsNode->getValueType(1));
8372 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8374 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8375 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8377 return SDValue(N, 0);
8380 // Optimize compare with zero and branch.
8381 static SDValue performBRCONDCombine(SDNode *N,
8382 TargetLowering::DAGCombinerInfo &DCI,
8383 SelectionDAG &DAG) {
8384 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8387 SDValue Chain = N->getOperand(0);
8388 SDValue Dest = N->getOperand(1);
8389 SDValue CCVal = N->getOperand(2);
8390 SDValue Cmp = N->getOperand(3);
8392 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8393 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8394 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8397 unsigned CmpOpc = Cmp.getOpcode();
8398 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8401 // Only attempt folding if there is only one use of the flag and no use of the
8403 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8406 SDValue LHS = Cmp.getOperand(0);
8407 SDValue RHS = Cmp.getOperand(1);
8409 assert(LHS.getValueType() == RHS.getValueType() &&
8410 "Expected the value type to be the same for both operands!");
8411 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8414 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8415 std::swap(LHS, RHS);
8417 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8420 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8421 LHS.getOpcode() == ISD::SRL)
8424 // Fold the compare into the branch instruction.
8426 if (CC == AArch64CC::EQ)
8427 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8429 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8431 // Do not add new nodes to DAG combiner worklist.
8432 DCI.CombineTo(N, BR, false);
8437 // vselect (v1i1 setcc) ->
8438 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8439 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8440 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8442 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8443 SDValue N0 = N->getOperand(0);
8444 EVT CCVT = N0.getValueType();
8446 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8447 CCVT.getVectorElementType() != MVT::i1)
8450 EVT ResVT = N->getValueType(0);
8451 EVT CmpVT = N0.getOperand(0).getValueType();
8452 // Only combine when the result type is of the same size as the compared
8454 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8457 SDValue IfTrue = N->getOperand(1);
8458 SDValue IfFalse = N->getOperand(2);
8460 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8461 N0.getOperand(0), N0.getOperand(1),
8462 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8463 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8467 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8468 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8469 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8470 /// with a vector one followed by a DUP shuffle on the result.
8471 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8472 SDValue N0 = N->getOperand(0);
8473 EVT ResVT = N->getValueType(0);
8475 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8478 // If NumMaskElts == 0, the comparison is larger than select result. The
8479 // largest real NEON comparison is 64-bits per lane, which means the result is
8480 // at most 32-bits and an illegal vector. Just bail out for now.
8481 EVT SrcVT = N0.getOperand(0).getValueType();
8482 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8483 if (!ResVT.isVector() || NumMaskElts == 0)
8486 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8487 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8489 // First perform a vector comparison, where lane 0 is the one we're interested
8493 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8495 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8496 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8498 // Now duplicate the comparison mask we want across all other lanes.
8499 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8500 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8501 Mask = DAG.getNode(ISD::BITCAST, DL,
8502 ResVT.changeVectorElementTypeToInteger(), Mask);
8504 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8507 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8508 DAGCombinerInfo &DCI) const {
8509 SelectionDAG &DAG = DCI.DAG;
8510 switch (N->getOpcode()) {
8515 return performAddSubLongCombine(N, DCI, DAG);
8517 return performXorCombine(N, DAG, DCI, Subtarget);
8519 return performMulCombine(N, DAG, DCI, Subtarget);
8520 case ISD::SINT_TO_FP:
8521 case ISD::UINT_TO_FP:
8522 return performIntToFpCombine(N, DAG);
8524 return performORCombine(N, DCI, Subtarget);
8525 case ISD::INTRINSIC_WO_CHAIN:
8526 return performIntrinsicCombine(N, DCI, Subtarget);
8527 case ISD::ANY_EXTEND:
8528 case ISD::ZERO_EXTEND:
8529 case ISD::SIGN_EXTEND:
8530 return performExtendCombine(N, DCI, DAG);
8532 return performBitcastCombine(N, DCI, DAG);
8533 case ISD::CONCAT_VECTORS:
8534 return performConcatVectorsCombine(N, DCI, DAG);
8536 return performSelectCombine(N, DAG);
8538 return performVSelectCombine(N, DCI.DAG);
8540 return performSTORECombine(N, DCI, DAG, Subtarget);
8541 case AArch64ISD::BRCOND:
8542 return performBRCONDCombine(N, DCI, DAG);
8543 case AArch64ISD::CSEL:
8544 return performCONDCombine(N, DCI, DAG, 2, 3);
8545 case AArch64ISD::DUP:
8546 return performPostLD1Combine(N, DCI, false);
8547 case ISD::INSERT_VECTOR_ELT:
8548 return performPostLD1Combine(N, DCI, true);
8549 case ISD::INTRINSIC_VOID:
8550 case ISD::INTRINSIC_W_CHAIN:
8551 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8552 case Intrinsic::aarch64_neon_ld2:
8553 case Intrinsic::aarch64_neon_ld3:
8554 case Intrinsic::aarch64_neon_ld4:
8555 case Intrinsic::aarch64_neon_ld1x2:
8556 case Intrinsic::aarch64_neon_ld1x3:
8557 case Intrinsic::aarch64_neon_ld1x4:
8558 case Intrinsic::aarch64_neon_ld2lane:
8559 case Intrinsic::aarch64_neon_ld3lane:
8560 case Intrinsic::aarch64_neon_ld4lane:
8561 case Intrinsic::aarch64_neon_ld2r:
8562 case Intrinsic::aarch64_neon_ld3r:
8563 case Intrinsic::aarch64_neon_ld4r:
8564 case Intrinsic::aarch64_neon_st2:
8565 case Intrinsic::aarch64_neon_st3:
8566 case Intrinsic::aarch64_neon_st4:
8567 case Intrinsic::aarch64_neon_st1x2:
8568 case Intrinsic::aarch64_neon_st1x3:
8569 case Intrinsic::aarch64_neon_st1x4:
8570 case Intrinsic::aarch64_neon_st2lane:
8571 case Intrinsic::aarch64_neon_st3lane:
8572 case Intrinsic::aarch64_neon_st4lane:
8573 return performNEONPostLDSTCombine(N, DCI, DAG);
8581 // Check if the return value is used as only a return value, as otherwise
8582 // we can't perform a tail-call. In particular, we need to check for
8583 // target ISD nodes that are returns and any other "odd" constructs
8584 // that the generic analysis code won't necessarily catch.
8585 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8586 SDValue &Chain) const {
8587 if (N->getNumValues() != 1)
8589 if (!N->hasNUsesOfValue(1, 0))
8592 SDValue TCChain = Chain;
8593 SDNode *Copy = *N->use_begin();
8594 if (Copy->getOpcode() == ISD::CopyToReg) {
8595 // If the copy has a glue operand, we conservatively assume it isn't safe to
8596 // perform a tail call.
8597 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8600 TCChain = Copy->getOperand(0);
8601 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8604 bool HasRet = false;
8605 for (SDNode *Node : Copy->uses()) {
8606 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8618 // Return whether the an instruction can potentially be optimized to a tail
8619 // call. This will cause the optimizers to attempt to move, or duplicate,
8620 // return instructions to help enable tail call optimizations for this
8622 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8623 if (!CI->isTailCall())
8629 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8631 ISD::MemIndexedMode &AM,
8633 SelectionDAG &DAG) const {
8634 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8637 Base = Op->getOperand(0);
8638 // All of the indexed addressing mode instructions take a signed
8639 // 9 bit immediate offset.
8640 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8641 int64_t RHSC = (int64_t)RHS->getZExtValue();
8642 if (RHSC >= 256 || RHSC <= -256)
8644 IsInc = (Op->getOpcode() == ISD::ADD);
8645 Offset = Op->getOperand(1);
8651 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8653 ISD::MemIndexedMode &AM,
8654 SelectionDAG &DAG) const {
8657 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8658 VT = LD->getMemoryVT();
8659 Ptr = LD->getBasePtr();
8660 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8661 VT = ST->getMemoryVT();
8662 Ptr = ST->getBasePtr();
8667 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8669 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8673 bool AArch64TargetLowering::getPostIndexedAddressParts(
8674 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8675 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8678 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8679 VT = LD->getMemoryVT();
8680 Ptr = LD->getBasePtr();
8681 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8682 VT = ST->getMemoryVT();
8683 Ptr = ST->getBasePtr();
8688 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8690 // Post-indexing updates the base, so it's not a valid transform
8691 // if that's not the same as the load's pointer.
8694 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8698 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8699 SelectionDAG &DAG) {
8701 SDValue Op = N->getOperand(0);
8703 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8707 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8708 DAG.getUNDEF(MVT::i32), Op,
8709 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8711 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8712 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8715 void AArch64TargetLowering::ReplaceNodeResults(
8716 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8717 switch (N->getOpcode()) {
8719 llvm_unreachable("Don't know how to custom expand this");
8721 ReplaceBITCASTResults(N, Results, DAG);
8723 case ISD::FP_TO_UINT:
8724 case ISD::FP_TO_SINT:
8725 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8726 // Let normal code take care of it by not adding anything to Results.
8731 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8735 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8736 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8737 // reciprocal if there are three or more FDIVs.
8738 return NumUsers > 2;
8741 TargetLoweringBase::LegalizeTypeAction
8742 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8743 MVT SVT = VT.getSimpleVT();
8744 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8745 // v4i16, v2i32 instead of to promote.
8746 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8747 || SVT == MVT::v1f32)
8748 return TypeWidenVector;
8750 return TargetLoweringBase::getPreferredVectorAction(VT);
8753 // Loads and stores less than 128-bits are already atomic; ones above that
8754 // are doomed anyway, so defer to the default libcall and blame the OS when
8756 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8757 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8761 // Loads and stores less than 128-bits are already atomic; ones above that
8762 // are doomed anyway, so defer to the default libcall and blame the OS when
8764 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8765 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8769 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8770 bool AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8771 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8775 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8779 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8780 AtomicOrdering Ord) const {
8781 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8782 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8783 bool IsAcquire = isAtLeastAcquire(Ord);
8785 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8786 // intrinsic must return {i64, i64} and we have to recombine them into a
8787 // single i128 here.
8788 if (ValTy->getPrimitiveSizeInBits() == 128) {
8790 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8791 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8793 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8794 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8796 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8797 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8798 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8799 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8800 return Builder.CreateOr(
8801 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8804 Type *Tys[] = { Addr->getType() };
8806 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8807 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8809 return Builder.CreateTruncOrBitCast(
8810 Builder.CreateCall(Ldxr, Addr),
8811 cast<PointerType>(Addr->getType())->getElementType());
8814 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8815 Value *Val, Value *Addr,
8816 AtomicOrdering Ord) const {
8817 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8818 bool IsRelease = isAtLeastRelease(Ord);
8820 // Since the intrinsics must have legal type, the i128 intrinsics take two
8821 // parameters: "i64, i64". We must marshal Val into the appropriate form
8823 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8825 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8826 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8827 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8829 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8830 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8831 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8832 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8836 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8837 Type *Tys[] = { Addr->getType() };
8838 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8840 return Builder.CreateCall2(
8841 Stxr, Builder.CreateZExtOrBitCast(
8842 Val, Stxr->getFunctionType()->getParamType(0)),
8846 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
8847 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
8848 return Ty->isArrayTy();