1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64CallingConv.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
47 static cl::opt<AlignMode>
48 Align(cl::desc("Load/store alignment support"),
49 cl::Hidden, cl::init(NoStrictAlign),
51 clEnumValN(StrictAlign, "aarch64-strict-align",
52 "Disallow all unaligned memory accesses"),
53 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
54 "Allow unaligned memory accesses"),
57 // Place holder until extr generation is tested fully.
59 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
60 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
64 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
65 cl::desc("Allow AArch64 SLI/SRI formation"),
68 //===----------------------------------------------------------------------===//
69 // AArch64 Lowering public interface.
70 //===----------------------------------------------------------------------===//
71 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
72 if (TM.getSubtarget<AArch64Subtarget>().isTargetDarwin())
73 return new AArch64_MachoTargetObjectFile();
75 return new AArch64_ELFTargetObjectFile();
78 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
79 : TargetLowering(TM, createTLOF(TM)) {
80 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
111 addQRTypeForNEON(MVT::v4f32);
112 addQRTypeForNEON(MVT::v2f64);
113 addQRTypeForNEON(MVT::v16i8);
114 addQRTypeForNEON(MVT::v8i16);
115 addQRTypeForNEON(MVT::v4i32);
116 addQRTypeForNEON(MVT::v2i64);
119 // Compute derived properties from the register classes
120 computeRegisterProperties();
122 // Provide all sorts of operation actions
123 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
124 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
125 setOperationAction(ISD::SETCC, MVT::i32, Custom);
126 setOperationAction(ISD::SETCC, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::f32, Custom);
128 setOperationAction(ISD::SETCC, MVT::f64, Custom);
129 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
130 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
131 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
134 setOperationAction(ISD::SELECT, MVT::i32, Custom);
135 setOperationAction(ISD::SELECT, MVT::i64, Custom);
136 setOperationAction(ISD::SELECT, MVT::f32, Custom);
137 setOperationAction(ISD::SELECT, MVT::f64, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
142 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
143 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
145 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
147 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::FREM, MVT::f32, Expand);
150 setOperationAction(ISD::FREM, MVT::f64, Expand);
151 setOperationAction(ISD::FREM, MVT::f80, Expand);
153 // Custom lowering hooks are needed for XOR
154 // to fold it into CSINC/CSINV.
155 setOperationAction(ISD::XOR, MVT::i32, Custom);
156 setOperationAction(ISD::XOR, MVT::i64, Custom);
158 // Virtually no operation on f128 is legal, but LLVM can't expand them when
159 // there's a valid register class, so we need custom operations in most cases.
160 setOperationAction(ISD::FABS, MVT::f128, Expand);
161 setOperationAction(ISD::FADD, MVT::f128, Custom);
162 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
163 setOperationAction(ISD::FCOS, MVT::f128, Expand);
164 setOperationAction(ISD::FDIV, MVT::f128, Custom);
165 setOperationAction(ISD::FMA, MVT::f128, Expand);
166 setOperationAction(ISD::FMUL, MVT::f128, Custom);
167 setOperationAction(ISD::FNEG, MVT::f128, Expand);
168 setOperationAction(ISD::FPOW, MVT::f128, Expand);
169 setOperationAction(ISD::FREM, MVT::f128, Expand);
170 setOperationAction(ISD::FRINT, MVT::f128, Expand);
171 setOperationAction(ISD::FSIN, MVT::f128, Expand);
172 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
173 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
174 setOperationAction(ISD::FSUB, MVT::f128, Custom);
175 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
176 setOperationAction(ISD::SETCC, MVT::f128, Custom);
177 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT, MVT::f128, Custom);
179 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
180 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
182 // Lowering for many of the conversions is actually specified by the non-f128
183 // type. The LowerXXX function will be trivial when f128 isn't involved.
184 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
186 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
197 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
199 // Variable arguments.
200 setOperationAction(ISD::VASTART, MVT::Other, Custom);
201 setOperationAction(ISD::VAARG, MVT::Other, Custom);
202 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
203 setOperationAction(ISD::VAEND, MVT::Other, Expand);
205 // Variable-sized objects.
206 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
207 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
208 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
210 // Exception handling.
211 // FIXME: These are guesses. Has this been defined yet?
212 setExceptionPointerRegister(AArch64::X0);
213 setExceptionSelectorRegister(AArch64::X1);
215 // Constant pool entries
216 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
221 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
222 setOperationAction(ISD::ADDC, MVT::i32, Custom);
223 setOperationAction(ISD::ADDE, MVT::i32, Custom);
224 setOperationAction(ISD::SUBC, MVT::i32, Custom);
225 setOperationAction(ISD::SUBE, MVT::i32, Custom);
226 setOperationAction(ISD::ADDC, MVT::i64, Custom);
227 setOperationAction(ISD::ADDE, MVT::i64, Custom);
228 setOperationAction(ISD::SUBC, MVT::i64, Custom);
229 setOperationAction(ISD::SUBE, MVT::i64, Custom);
231 // AArch64 lacks both left-rotate and popcount instructions.
232 setOperationAction(ISD::ROTL, MVT::i32, Expand);
233 setOperationAction(ISD::ROTL, MVT::i64, Expand);
235 // AArch64 doesn't have {U|S}MUL_LOHI.
236 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
237 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
240 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
241 // counterparts, which AArch64 supports directly.
242 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
248 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
250 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
251 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
252 setOperationAction(ISD::SREM, MVT::i32, Expand);
253 setOperationAction(ISD::SREM, MVT::i64, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
255 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
256 setOperationAction(ISD::UREM, MVT::i32, Expand);
257 setOperationAction(ISD::UREM, MVT::i64, Expand);
259 // Custom lower Add/Sub/Mul with overflow.
260 setOperationAction(ISD::SADDO, MVT::i32, Custom);
261 setOperationAction(ISD::SADDO, MVT::i64, Custom);
262 setOperationAction(ISD::UADDO, MVT::i32, Custom);
263 setOperationAction(ISD::UADDO, MVT::i64, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
265 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
266 setOperationAction(ISD::USUBO, MVT::i32, Custom);
267 setOperationAction(ISD::USUBO, MVT::i64, Custom);
268 setOperationAction(ISD::SMULO, MVT::i32, Custom);
269 setOperationAction(ISD::SMULO, MVT::i64, Custom);
270 setOperationAction(ISD::UMULO, MVT::i32, Custom);
271 setOperationAction(ISD::UMULO, MVT::i64, Custom);
273 setOperationAction(ISD::FSIN, MVT::f32, Expand);
274 setOperationAction(ISD::FSIN, MVT::f64, Expand);
275 setOperationAction(ISD::FCOS, MVT::f32, Expand);
276 setOperationAction(ISD::FCOS, MVT::f64, Expand);
277 setOperationAction(ISD::FPOW, MVT::f32, Expand);
278 setOperationAction(ISD::FPOW, MVT::f64, Expand);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
280 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
282 // AArch64 has implementations of a lot of rounding-like FP operations.
283 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
284 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
285 MVT Ty = RoundingTypes[I];
286 setOperationAction(ISD::FFLOOR, Ty, Legal);
287 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
288 setOperationAction(ISD::FCEIL, Ty, Legal);
289 setOperationAction(ISD::FRINT, Ty, Legal);
290 setOperationAction(ISD::FTRUNC, Ty, Legal);
291 setOperationAction(ISD::FROUND, Ty, Legal);
294 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
296 if (Subtarget->isTargetMachO()) {
297 // For iOS, we don't want to the normal expansion of a libcall to
298 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
300 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
301 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
303 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
304 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
307 // AArch64 does not have floating-point extending loads, i1 sign-extending
308 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
309 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
311 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
312 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
313 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
319 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
320 // Indexed loads and stores are supported.
321 for (unsigned im = (unsigned)ISD::PRE_INC;
322 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
323 setIndexedLoadAction(im, MVT::i8, Legal);
324 setIndexedLoadAction(im, MVT::i16, Legal);
325 setIndexedLoadAction(im, MVT::i32, Legal);
326 setIndexedLoadAction(im, MVT::i64, Legal);
327 setIndexedLoadAction(im, MVT::f64, Legal);
328 setIndexedLoadAction(im, MVT::f32, Legal);
329 setIndexedStoreAction(im, MVT::i8, Legal);
330 setIndexedStoreAction(im, MVT::i16, Legal);
331 setIndexedStoreAction(im, MVT::i32, Legal);
332 setIndexedStoreAction(im, MVT::i64, Legal);
333 setIndexedStoreAction(im, MVT::f64, Legal);
334 setIndexedStoreAction(im, MVT::f32, Legal);
338 setOperationAction(ISD::TRAP, MVT::Other, Legal);
340 // We combine OR nodes for bitfield operations.
341 setTargetDAGCombine(ISD::OR);
343 // Vector add and sub nodes may conceal a high-half opportunity.
344 // Also, try to fold ADD into CSINC/CSINV..
345 setTargetDAGCombine(ISD::ADD);
346 setTargetDAGCombine(ISD::SUB);
348 setTargetDAGCombine(ISD::XOR);
349 setTargetDAGCombine(ISD::SINT_TO_FP);
350 setTargetDAGCombine(ISD::UINT_TO_FP);
352 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
354 setTargetDAGCombine(ISD::ANY_EXTEND);
355 setTargetDAGCombine(ISD::ZERO_EXTEND);
356 setTargetDAGCombine(ISD::SIGN_EXTEND);
357 setTargetDAGCombine(ISD::BITCAST);
358 setTargetDAGCombine(ISD::CONCAT_VECTORS);
359 setTargetDAGCombine(ISD::STORE);
361 setTargetDAGCombine(ISD::MUL);
363 setTargetDAGCombine(ISD::SELECT);
364 setTargetDAGCombine(ISD::VSELECT);
366 setTargetDAGCombine(ISD::INTRINSIC_VOID);
367 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
368 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
370 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
371 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
372 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
374 setStackPointerRegisterToSaveRestore(AArch64::SP);
376 setSchedulingPreference(Sched::Hybrid);
379 MaskAndBranchFoldingIsLegal = true;
381 setMinFunctionAlignment(2);
383 RequireStrictAlign = (Align == StrictAlign);
385 setHasExtractBitsInsn(true);
387 if (Subtarget->hasNEON()) {
388 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
389 // silliness like this:
390 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
391 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
394 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
395 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
396 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
398 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
400 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
401 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
402 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
403 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
404 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
408 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
409 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
410 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
411 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
413 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
414 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
416 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
418 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
420 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
422 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
424 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
425 // elements smaller than i32, so promote the input to i32 first.
426 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
428 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
429 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
430 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
431 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
433 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
434 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
436 // AArch64 doesn't have MUL.2d:
437 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
438 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
439 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
440 // Likewise, narrowing and extending vector loads/stores aren't handled
442 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
443 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
445 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
448 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
453 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
455 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
456 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
457 setTruncStoreAction((MVT::SimpleValueType)VT,
458 (MVT::SimpleValueType)InnerVT, Expand);
459 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
461 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
464 // AArch64 has implementations of a lot of rounding-like FP operations.
465 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
466 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
467 MVT Ty = RoundingVecTypes[I];
468 setOperationAction(ISD::FFLOOR, Ty, Legal);
469 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
470 setOperationAction(ISD::FCEIL, Ty, Legal);
471 setOperationAction(ISD::FRINT, Ty, Legal);
472 setOperationAction(ISD::FTRUNC, Ty, Legal);
473 setOperationAction(ISD::FROUND, Ty, Legal);
478 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
479 if (VT == MVT::v2f32) {
480 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
481 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
483 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
484 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
485 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
486 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
487 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
489 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
490 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
493 // Mark vector float intrinsics as expand.
494 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
495 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
503 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
506 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
517 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
519 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
521 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
522 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
524 // CNT supports only B element sizes.
525 if (VT != MVT::v8i8 && VT != MVT::v16i8)
526 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
532 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
534 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
535 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
537 if (Subtarget->isLittleEndian()) {
538 for (unsigned im = (unsigned)ISD::PRE_INC;
539 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
540 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
541 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
546 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
547 addRegisterClass(VT, &AArch64::FPR64RegClass);
548 addTypeForNEON(VT, MVT::v2i32);
551 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
552 addRegisterClass(VT, &AArch64::FPR128RegClass);
553 addTypeForNEON(VT, MVT::v4i32);
556 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
559 return VT.changeVectorElementTypeToInteger();
562 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
563 /// Mask are known to be either zero or one and return them in the
564 /// KnownZero/KnownOne bitsets.
565 void AArch64TargetLowering::computeKnownBitsForTargetNode(
566 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
567 const SelectionDAG &DAG, unsigned Depth) const {
568 switch (Op.getOpcode()) {
571 case AArch64ISD::CSEL: {
572 APInt KnownZero2, KnownOne2;
573 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
574 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
575 KnownZero &= KnownZero2;
576 KnownOne &= KnownOne2;
579 case ISD::INTRINSIC_W_CHAIN: {
580 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
581 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
584 case Intrinsic::aarch64_ldaxr:
585 case Intrinsic::aarch64_ldxr: {
586 unsigned BitWidth = KnownOne.getBitWidth();
587 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
588 unsigned MemBits = VT.getScalarType().getSizeInBits();
589 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
595 case ISD::INTRINSIC_WO_CHAIN:
596 case ISD::INTRINSIC_VOID: {
597 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
601 case Intrinsic::aarch64_neon_umaxv:
602 case Intrinsic::aarch64_neon_uminv: {
603 // Figure out the datatype of the vector operand. The UMINV instruction
604 // will zero extend the result, so we can mark as known zero all the
605 // bits larger than the element datatype. 32-bit or larget doesn't need
606 // this as those are legal types and will be handled by isel directly.
607 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
608 unsigned BitWidth = KnownZero.getBitWidth();
609 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
610 assert(BitWidth >= 8 && "Unexpected width!");
611 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
613 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
614 assert(BitWidth >= 16 && "Unexpected width!");
615 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
625 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
629 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
630 // FIXME: On AArch64, this depends on the type.
631 // Basically, the addressable offsets are o to 4095 * Ty.getSizeInBytes().
632 // and the offset has to be a multiple of the related size in bytes.
637 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
638 const TargetLibraryInfo *libInfo) const {
639 return AArch64::createFastISel(funcInfo, libInfo);
642 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
646 case AArch64ISD::CALL: return "AArch64ISD::CALL";
647 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
648 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
649 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
650 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
651 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
652 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
653 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
654 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
655 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
656 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
657 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
658 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
659 case AArch64ISD::ADC: return "AArch64ISD::ADC";
660 case AArch64ISD::SBC: return "AArch64ISD::SBC";
661 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
662 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
663 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
664 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
665 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
666 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
667 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
668 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
669 case AArch64ISD::DUP: return "AArch64ISD::DUP";
670 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
671 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
672 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
673 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
674 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
675 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
676 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
677 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
678 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
679 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
680 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
681 case AArch64ISD::BICi: return "AArch64ISD::BICi";
682 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
683 case AArch64ISD::BSL: return "AArch64ISD::BSL";
684 case AArch64ISD::NEG: return "AArch64ISD::NEG";
685 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
686 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
687 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
688 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
689 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
690 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
691 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
692 case AArch64ISD::REV16: return "AArch64ISD::REV16";
693 case AArch64ISD::REV32: return "AArch64ISD::REV32";
694 case AArch64ISD::REV64: return "AArch64ISD::REV64";
695 case AArch64ISD::EXT: return "AArch64ISD::EXT";
696 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
697 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
698 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
699 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
700 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
701 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
702 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
703 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
704 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
705 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
706 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
707 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
708 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
709 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
710 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
711 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
712 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
713 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
714 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
715 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
716 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
717 case AArch64ISD::NOT: return "AArch64ISD::NOT";
718 case AArch64ISD::BIT: return "AArch64ISD::BIT";
719 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
720 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
721 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
722 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
723 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
724 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
725 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
726 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
727 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
728 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
729 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
730 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
731 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
732 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
733 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
734 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
735 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
736 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
737 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
738 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
739 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
740 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
741 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
742 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
743 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
744 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
745 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
746 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
747 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
748 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
749 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
750 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
751 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
752 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
753 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
754 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
759 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
760 MachineBasicBlock *MBB) const {
761 // We materialise the F128CSEL pseudo-instruction as some control flow and a
765 // [... previous instrs leading to comparison ...]
771 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
773 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
774 MachineFunction *MF = MBB->getParent();
775 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
776 DebugLoc DL = MI->getDebugLoc();
777 MachineFunction::iterator It = MBB;
780 unsigned DestReg = MI->getOperand(0).getReg();
781 unsigned IfTrueReg = MI->getOperand(1).getReg();
782 unsigned IfFalseReg = MI->getOperand(2).getReg();
783 unsigned CondCode = MI->getOperand(3).getImm();
784 bool NZCVKilled = MI->getOperand(4).isKill();
786 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
788 MF->insert(It, TrueBB);
789 MF->insert(It, EndBB);
791 // Transfer rest of current basic-block to EndBB
792 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
794 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
796 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
797 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
798 MBB->addSuccessor(TrueBB);
799 MBB->addSuccessor(EndBB);
801 // TrueBB falls through to the end.
802 TrueBB->addSuccessor(EndBB);
805 TrueBB->addLiveIn(AArch64::NZCV);
806 EndBB->addLiveIn(AArch64::NZCV);
809 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
815 MI->eraseFromParent();
820 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
821 MachineBasicBlock *BB) const {
822 switch (MI->getOpcode()) {
827 assert(0 && "Unexpected instruction for custom inserter!");
830 case AArch64::F128CSEL:
831 return EmitF128CSEL(MI, BB);
833 case TargetOpcode::STACKMAP:
834 case TargetOpcode::PATCHPOINT:
835 return emitPatchPoint(MI, BB);
837 llvm_unreachable("Unexpected instruction for custom inserter!");
840 //===----------------------------------------------------------------------===//
841 // AArch64 Lowering private implementation.
842 //===----------------------------------------------------------------------===//
844 //===----------------------------------------------------------------------===//
846 //===----------------------------------------------------------------------===//
848 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
850 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
853 llvm_unreachable("Unknown condition code!");
855 return AArch64CC::NE;
857 return AArch64CC::EQ;
859 return AArch64CC::GT;
861 return AArch64CC::GE;
863 return AArch64CC::LT;
865 return AArch64CC::LE;
867 return AArch64CC::HI;
869 return AArch64CC::HS;
871 return AArch64CC::LO;
873 return AArch64CC::LS;
877 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
878 static void changeFPCCToAArch64CC(ISD::CondCode CC,
879 AArch64CC::CondCode &CondCode,
880 AArch64CC::CondCode &CondCode2) {
881 CondCode2 = AArch64CC::AL;
884 llvm_unreachable("Unknown FP condition!");
887 CondCode = AArch64CC::EQ;
891 CondCode = AArch64CC::GT;
895 CondCode = AArch64CC::GE;
898 CondCode = AArch64CC::MI;
901 CondCode = AArch64CC::LS;
904 CondCode = AArch64CC::MI;
905 CondCode2 = AArch64CC::GT;
908 CondCode = AArch64CC::VC;
911 CondCode = AArch64CC::VS;
914 CondCode = AArch64CC::EQ;
915 CondCode2 = AArch64CC::VS;
918 CondCode = AArch64CC::HI;
921 CondCode = AArch64CC::PL;
925 CondCode = AArch64CC::LT;
929 CondCode = AArch64CC::LE;
933 CondCode = AArch64CC::NE;
938 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
939 /// CC usable with the vector instructions. Fewer operations are available
940 /// without a real NZCV register, so we have to use less efficient combinations
941 /// to get the same effect.
942 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
943 AArch64CC::CondCode &CondCode,
944 AArch64CC::CondCode &CondCode2,
949 // Mostly the scalar mappings work fine.
950 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
953 Invert = true; // Fallthrough
955 CondCode = AArch64CC::MI;
956 CondCode2 = AArch64CC::GE;
963 // All of the compare-mask comparisons are ordered, but we can switch
964 // between the two by a double inversion. E.g. ULE == !OGT.
966 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
971 static bool isLegalArithImmed(uint64_t C) {
972 // Matches AArch64DAGToDAGISel::SelectArithImmed().
973 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
976 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
977 SDLoc dl, SelectionDAG &DAG) {
978 EVT VT = LHS.getValueType();
980 if (VT.isFloatingPoint())
981 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
983 // The CMP instruction is just an alias for SUBS, and representing it as
984 // SUBS means that it's possible to get CSE with subtract operations.
985 // A later phase can perform the optimization of setting the destination
986 // register to WZR/XZR if it ends up being unused.
987 unsigned Opcode = AArch64ISD::SUBS;
989 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
990 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
991 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
992 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
993 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
994 // can be set differently by this operation. It comes down to whether
995 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
996 // everything is fine. If not then the optimization is wrong. Thus general
997 // comparisons are only valid if op2 != 0.
999 // So, finally, the only LLVM-native comparisons that don't mention C and V
1000 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1001 // the absence of information about op2.
1002 Opcode = AArch64ISD::ADDS;
1003 RHS = RHS.getOperand(1);
1004 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1005 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1006 !isUnsignedIntSetCC(CC)) {
1007 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1008 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1009 // of the signed comparisons.
1010 Opcode = AArch64ISD::ANDS;
1011 RHS = LHS.getOperand(1);
1012 LHS = LHS.getOperand(0);
1015 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1019 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1020 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1021 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1022 EVT VT = RHS.getValueType();
1023 uint64_t C = RHSC->getZExtValue();
1024 if (!isLegalArithImmed(C)) {
1025 // Constant does not fit, try adjusting it by one?
1031 if ((VT == MVT::i32 && C != 0x80000000 &&
1032 isLegalArithImmed((uint32_t)(C - 1))) ||
1033 (VT == MVT::i64 && C != 0x80000000ULL &&
1034 isLegalArithImmed(C - 1ULL))) {
1035 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1036 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1037 RHS = DAG.getConstant(C, VT);
1042 if ((VT == MVT::i32 && C != 0 &&
1043 isLegalArithImmed((uint32_t)(C - 1))) ||
1044 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1045 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1046 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1047 RHS = DAG.getConstant(C, VT);
1052 if ((VT == MVT::i32 && C != 0x7fffffff &&
1053 isLegalArithImmed((uint32_t)(C + 1))) ||
1054 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1055 isLegalArithImmed(C + 1ULL))) {
1056 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1057 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1058 RHS = DAG.getConstant(C, VT);
1063 if ((VT == MVT::i32 && C != 0xffffffff &&
1064 isLegalArithImmed((uint32_t)(C + 1))) ||
1065 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1066 isLegalArithImmed(C + 1ULL))) {
1067 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1068 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1069 RHS = DAG.getConstant(C, VT);
1076 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1077 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1078 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1082 static std::pair<SDValue, SDValue>
1083 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1084 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1085 "Unsupported value type");
1086 SDValue Value, Overflow;
1088 SDValue LHS = Op.getOperand(0);
1089 SDValue RHS = Op.getOperand(1);
1091 switch (Op.getOpcode()) {
1093 llvm_unreachable("Unknown overflow instruction!");
1095 Opc = AArch64ISD::ADDS;
1099 Opc = AArch64ISD::ADDS;
1103 Opc = AArch64ISD::SUBS;
1107 Opc = AArch64ISD::SUBS;
1110 // Multiply needs a little bit extra work.
1114 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1115 if (Op.getValueType() == MVT::i32) {
1116 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1117 // For a 32 bit multiply with overflow check we want the instruction
1118 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1119 // need to generate the following pattern:
1120 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1121 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1122 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1123 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1124 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1125 DAG.getConstant(0, MVT::i64));
1126 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1127 // operation. We need to clear out the upper 32 bits, because we used a
1128 // widening multiply that wrote all 64 bits. In the end this should be a
1130 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1132 // The signed overflow check requires more than just a simple check for
1133 // any bit set in the upper 32 bits of the result. These bits could be
1134 // just the sign bits of a negative number. To perform the overflow
1135 // check we have to arithmetic shift right the 32nd bit of the result by
1136 // 31 bits. Then we compare the result to the upper 32 bits.
1137 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1138 DAG.getConstant(32, MVT::i64));
1139 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1140 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1141 DAG.getConstant(31, MVT::i64));
1142 // It is important that LowerBits is last, otherwise the arithmetic
1143 // shift will not be folded into the compare (SUBS).
1144 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1145 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1148 // The overflow check for unsigned multiply is easy. We only need to
1149 // check if any of the upper 32 bits are set. This can be done with a
1150 // CMP (shifted register). For that we need to generate the following
1152 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1153 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1154 DAG.getConstant(32, MVT::i64));
1155 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1157 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1158 UpperBits).getValue(1);
1162 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1163 // For the 64 bit multiply
1164 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1166 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1167 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1168 DAG.getConstant(63, MVT::i64));
1169 // It is important that LowerBits is last, otherwise the arithmetic
1170 // shift will not be folded into the compare (SUBS).
1171 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1172 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1175 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1176 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1178 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1179 UpperBits).getValue(1);
1186 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1188 // Emit the AArch64 operation with overflow check.
1189 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1190 Overflow = Value.getValue(1);
1192 return std::make_pair(Value, Overflow);
1195 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1196 RTLIB::Libcall Call) const {
1197 SmallVector<SDValue, 2> Ops;
1198 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1199 Ops.push_back(Op.getOperand(i));
1201 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1205 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1206 SDValue Sel = Op.getOperand(0);
1207 SDValue Other = Op.getOperand(1);
1209 // If neither operand is a SELECT_CC, give up.
1210 if (Sel.getOpcode() != ISD::SELECT_CC)
1211 std::swap(Sel, Other);
1212 if (Sel.getOpcode() != ISD::SELECT_CC)
1215 // The folding we want to perform is:
1216 // (xor x, (select_cc a, b, cc, 0, -1) )
1218 // (csel x, (xor x, -1), cc ...)
1220 // The latter will get matched to a CSINV instruction.
1222 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1223 SDValue LHS = Sel.getOperand(0);
1224 SDValue RHS = Sel.getOperand(1);
1225 SDValue TVal = Sel.getOperand(2);
1226 SDValue FVal = Sel.getOperand(3);
1229 // FIXME: This could be generalized to non-integer comparisons.
1230 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1233 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1234 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1236 // The the values aren't constants, this isn't the pattern we're looking for.
1237 if (!CFVal || !CTVal)
1240 // We can commute the SELECT_CC by inverting the condition. This
1241 // might be needed to make this fit into a CSINV pattern.
1242 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1243 std::swap(TVal, FVal);
1244 std::swap(CTVal, CFVal);
1245 CC = ISD::getSetCCInverse(CC, true);
1248 // If the constants line up, perform the transform!
1249 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1251 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1254 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1255 DAG.getConstant(-1ULL, Other.getValueType()));
1257 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1264 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1265 EVT VT = Op.getValueType();
1267 // Let legalize expand this if it isn't a legal type yet.
1268 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1271 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1274 bool ExtraOp = false;
1275 switch (Op.getOpcode()) {
1277 assert(0 && "Invalid code");
1279 Opc = AArch64ISD::ADDS;
1282 Opc = AArch64ISD::SUBS;
1285 Opc = AArch64ISD::ADCS;
1289 Opc = AArch64ISD::SBCS;
1295 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1296 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1300 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1301 // Let legalize expand this if it isn't a legal type yet.
1302 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1305 AArch64CC::CondCode CC;
1306 // The actual operation that sets the overflow or carry flag.
1307 SDValue Value, Overflow;
1308 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1310 // We use 0 and 1 as false and true values.
1311 SDValue TVal = DAG.getConstant(1, MVT::i32);
1312 SDValue FVal = DAG.getConstant(0, MVT::i32);
1314 // We use an inverted condition, because the conditional select is inverted
1315 // too. This will allow it to be selected to a single instruction:
1316 // CSINC Wd, WZR, WZR, invert(cond).
1317 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1318 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1321 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1322 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1325 // Prefetch operands are:
1326 // 1: Address to prefetch
1328 // 3: int locality (0 = no locality ... 3 = extreme locality)
1329 // 4: bool isDataCache
1330 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1332 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1333 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1334 // The data thing is not used.
1335 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1337 bool IsStream = !Locality;
1338 // When the locality number is set
1340 // The front-end should have filtered out the out-of-range values
1341 assert(Locality <= 3 && "Prefetch locality out-of-range");
1342 // The locality degree is the opposite of the cache speed.
1343 // Put the number the other way around.
1344 // The encoding starts at 0 for level 1
1345 Locality = 3 - Locality;
1348 // built the mask value encoding the expected behavior.
1349 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1350 (Locality << 1) | // Cache level bits
1351 (unsigned)IsStream; // Stream bit
1352 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1353 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1356 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1357 SelectionDAG &DAG) const {
1358 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1361 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1363 return LowerF128Call(Op, DAG, LC);
1366 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1367 SelectionDAG &DAG) const {
1368 if (Op.getOperand(0).getValueType() != MVT::f128) {
1369 // It's legal except when f128 is involved
1374 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1376 // FP_ROUND node has a second operand indicating whether it is known to be
1377 // precise. That doesn't take part in the LibCall so we can't directly use
1379 SDValue SrcVal = Op.getOperand(0);
1380 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1381 /*isSigned*/ false, SDLoc(Op)).first;
1384 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1385 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1386 // Any additional optimization in this function should be recorded
1387 // in the cost tables.
1388 EVT InVT = Op.getOperand(0).getValueType();
1389 EVT VT = Op.getValueType();
1391 // FP_TO_XINT conversion from the same type are legal.
1392 if (VT.getSizeInBits() == InVT.getSizeInBits())
1395 if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
1398 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1400 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1401 } else if (InVT == MVT::v2f32) {
1403 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1404 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1407 // Type changing conversions are illegal.
1411 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1412 SelectionDAG &DAG) const {
1413 if (Op.getOperand(0).getValueType().isVector())
1414 return LowerVectorFP_TO_INT(Op, DAG);
1416 if (Op.getOperand(0).getValueType() != MVT::f128) {
1417 // It's legal except when f128 is involved
1422 if (Op.getOpcode() == ISD::FP_TO_SINT)
1423 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1425 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1427 SmallVector<SDValue, 2> Ops;
1428 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1429 Ops.push_back(Op.getOperand(i));
1431 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1435 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1436 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1437 // Any additional optimization in this function should be recorded
1438 // in the cost tables.
1439 EVT VT = Op.getValueType();
1441 SDValue In = Op.getOperand(0);
1442 EVT InVT = In.getValueType();
1444 // v2i32 to v2f32 is legal.
1445 if (VT == MVT::v2f32 && InVT == MVT::v2i32)
1448 // This function only handles v2f64 outputs.
1449 if (VT == MVT::v2f64) {
1450 // Extend the input argument to a v2i64 that we can feed into the
1451 // floating point conversion. Zero or sign extend based on whether
1452 // we're doing a signed or unsigned float conversion.
1454 Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
1455 assert(Op.getNumOperands() == 1 && "FP conversions take one argument");
1456 SDValue Promoted = DAG.getNode(Opc, dl, MVT::v2i64, Op.getOperand(0));
1457 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Promoted);
1460 // Scalarize v2i64 to v2f32 conversions.
1461 std::vector<SDValue> BuildVectorOps;
1462 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
1463 SDValue Sclr = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, In,
1464 DAG.getConstant(i, MVT::i64));
1465 Sclr = DAG.getNode(Op->getOpcode(), dl, MVT::f32, Sclr);
1466 BuildVectorOps.push_back(Sclr);
1469 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BuildVectorOps);
1472 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1473 SelectionDAG &DAG) const {
1474 if (Op.getValueType().isVector())
1475 return LowerVectorINT_TO_FP(Op, DAG);
1477 // i128 conversions are libcalls.
1478 if (Op.getOperand(0).getValueType() == MVT::i128)
1481 // Other conversions are legal, unless it's to the completely software-based
1483 if (Op.getValueType() != MVT::f128)
1487 if (Op.getOpcode() == ISD::SINT_TO_FP)
1488 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1490 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1492 return LowerF128Call(Op, DAG, LC);
1495 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1496 SelectionDAG &DAG) const {
1497 // For iOS, we want to call an alternative entry point: __sincos_stret,
1498 // which returns the values in two S / D registers.
1500 SDValue Arg = Op.getOperand(0);
1501 EVT ArgVT = Arg.getValueType();
1502 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1509 Entry.isSExt = false;
1510 Entry.isZExt = false;
1511 Args.push_back(Entry);
1513 const char *LibcallName =
1514 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1515 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1517 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1518 TargetLowering::CallLoweringInfo CLI(DAG);
1519 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1520 .setCallee(CallingConv::Fast, RetTy, Callee, &Args, 0);
1522 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1523 return CallResult.first;
1526 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1527 SelectionDAG &DAG) const {
1528 switch (Op.getOpcode()) {
1530 llvm_unreachable("unimplemented operand");
1532 case ISD::GlobalAddress:
1533 return LowerGlobalAddress(Op, DAG);
1534 case ISD::GlobalTLSAddress:
1535 return LowerGlobalTLSAddress(Op, DAG);
1537 return LowerSETCC(Op, DAG);
1539 return LowerBR_CC(Op, DAG);
1541 return LowerSELECT(Op, DAG);
1542 case ISD::SELECT_CC:
1543 return LowerSELECT_CC(Op, DAG);
1544 case ISD::JumpTable:
1545 return LowerJumpTable(Op, DAG);
1546 case ISD::ConstantPool:
1547 return LowerConstantPool(Op, DAG);
1548 case ISD::BlockAddress:
1549 return LowerBlockAddress(Op, DAG);
1551 return LowerVASTART(Op, DAG);
1553 return LowerVACOPY(Op, DAG);
1555 return LowerVAARG(Op, DAG);
1560 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1567 return LowerXALUO(Op, DAG);
1569 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1571 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1573 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1575 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1577 return LowerFP_ROUND(Op, DAG);
1578 case ISD::FP_EXTEND:
1579 return LowerFP_EXTEND(Op, DAG);
1580 case ISD::FRAMEADDR:
1581 return LowerFRAMEADDR(Op, DAG);
1582 case ISD::RETURNADDR:
1583 return LowerRETURNADDR(Op, DAG);
1584 case ISD::INSERT_VECTOR_ELT:
1585 return LowerINSERT_VECTOR_ELT(Op, DAG);
1586 case ISD::EXTRACT_VECTOR_ELT:
1587 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1588 case ISD::BUILD_VECTOR:
1589 return LowerBUILD_VECTOR(Op, DAG);
1590 case ISD::VECTOR_SHUFFLE:
1591 return LowerVECTOR_SHUFFLE(Op, DAG);
1592 case ISD::EXTRACT_SUBVECTOR:
1593 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1597 return LowerVectorSRA_SRL_SHL(Op, DAG);
1598 case ISD::SHL_PARTS:
1599 return LowerShiftLeftParts(Op, DAG);
1600 case ISD::SRL_PARTS:
1601 case ISD::SRA_PARTS:
1602 return LowerShiftRightParts(Op, DAG);
1604 return LowerCTPOP(Op, DAG);
1605 case ISD::FCOPYSIGN:
1606 return LowerFCOPYSIGN(Op, DAG);
1608 return LowerVectorAND(Op, DAG);
1610 return LowerVectorOR(Op, DAG);
1612 return LowerXOR(Op, DAG);
1614 return LowerPREFETCH(Op, DAG);
1615 case ISD::SINT_TO_FP:
1616 case ISD::UINT_TO_FP:
1617 return LowerINT_TO_FP(Op, DAG);
1618 case ISD::FP_TO_SINT:
1619 case ISD::FP_TO_UINT:
1620 return LowerFP_TO_INT(Op, DAG);
1622 return LowerFSINCOS(Op, DAG);
1626 /// getFunctionAlignment - Return the Log2 alignment of this function.
1627 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1631 //===----------------------------------------------------------------------===//
1632 // Calling Convention Implementation
1633 //===----------------------------------------------------------------------===//
1635 #include "AArch64GenCallingConv.inc"
1637 /// Selects the correct CCAssignFn for a the given CallingConvention
1639 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1640 bool IsVarArg) const {
1643 llvm_unreachable("Unsupported calling convention.");
1644 case CallingConv::WebKit_JS:
1645 return CC_AArch64_WebKit_JS;
1646 case CallingConv::C:
1647 case CallingConv::Fast:
1648 if (!Subtarget->isTargetDarwin())
1649 return CC_AArch64_AAPCS;
1650 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1654 SDValue AArch64TargetLowering::LowerFormalArguments(
1655 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1656 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1657 SmallVectorImpl<SDValue> &InVals) const {
1658 MachineFunction &MF = DAG.getMachineFunction();
1659 MachineFrameInfo *MFI = MF.getFrameInfo();
1661 // Assign locations to all of the incoming arguments.
1662 SmallVector<CCValAssign, 16> ArgLocs;
1663 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1664 getTargetMachine(), ArgLocs, *DAG.getContext());
1666 // At this point, Ins[].VT may already be promoted to i32. To correctly
1667 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1668 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1669 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1670 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1672 unsigned NumArgs = Ins.size();
1673 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1674 unsigned CurArgIdx = 0;
1675 for (unsigned i = 0; i != NumArgs; ++i) {
1676 MVT ValVT = Ins[i].VT;
1677 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1678 CurArgIdx = Ins[i].OrigArgIndex;
1680 // Get type of the original argument.
1681 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1682 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1683 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1685 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1687 else if (ActualMVT == MVT::i16)
1690 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1692 AssignFn(i, ValVT, LocVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1693 assert(!Res && "Call operand has unhandled type");
1696 assert(ArgLocs.size() == Ins.size());
1697 SmallVector<SDValue, 16> ArgValues;
1698 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1699 CCValAssign &VA = ArgLocs[i];
1701 if (Ins[i].Flags.isByVal()) {
1702 // Byval is used for HFAs in the PCS, but the system should work in a
1703 // non-compliant manner for larger structs.
1704 EVT PtrTy = getPointerTy();
1705 int Size = Ins[i].Flags.getByValSize();
1706 unsigned NumRegs = (Size + 7) / 8;
1708 // FIXME: This works on big-endian for composite byvals, which are the common
1709 // case. It should also work for fundamental types too.
1711 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1712 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1713 InVals.push_back(FrameIdxN);
1716 } if (VA.isRegLoc()) {
1717 // Arguments stored in registers.
1718 EVT RegVT = VA.getLocVT();
1721 const TargetRegisterClass *RC;
1723 if (RegVT == MVT::i32)
1724 RC = &AArch64::GPR32RegClass;
1725 else if (RegVT == MVT::i64)
1726 RC = &AArch64::GPR64RegClass;
1727 else if (RegVT == MVT::f32)
1728 RC = &AArch64::FPR32RegClass;
1729 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1730 RC = &AArch64::FPR64RegClass;
1731 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1732 RC = &AArch64::FPR128RegClass;
1734 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1736 // Transform the arguments in physical registers into virtual ones.
1737 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1738 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1740 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1741 // to 64 bits. Insert an assert[sz]ext to capture this, then
1742 // truncate to the right size.
1743 switch (VA.getLocInfo()) {
1745 llvm_unreachable("Unknown loc info!");
1746 case CCValAssign::Full:
1748 case CCValAssign::BCvt:
1749 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1751 case CCValAssign::SExt:
1752 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
1753 DAG.getValueType(VA.getValVT()));
1754 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
1756 case CCValAssign::ZExt:
1757 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
1758 DAG.getValueType(VA.getValVT()));
1759 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
1763 InVals.push_back(ArgValue);
1765 } else { // VA.isRegLoc()
1766 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1767 unsigned ArgOffset = VA.getLocMemOffset();
1768 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1770 uint32_t BEAlign = 0;
1771 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1772 BEAlign = 8 - ArgSize;
1774 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1776 // Create load nodes to retrieve arguments from the stack.
1777 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1780 // If the loc type and val type are not the same, create an anyext load.
1781 if (VA.getLocVT().getSizeInBits() != VA.getValVT().getSizeInBits()) {
1782 // We should only get here if this is a pure integer.
1783 assert(!VA.getValVT().isVector() && VA.getValVT().isInteger() &&
1784 "Only integer extension supported!");
1785 ArgValue = DAG.getExtLoad(ISD::EXTLOAD, DL, VA.getValVT(), Chain, FIN,
1786 MachinePointerInfo::getFixedStack(FI),
1788 false, false, false, 0);
1790 ArgValue = DAG.getLoad(VA.getValVT(), DL, Chain, FIN,
1791 MachinePointerInfo::getFixedStack(FI), false,
1795 InVals.push_back(ArgValue);
1801 if (!Subtarget->isTargetDarwin()) {
1802 // The AAPCS variadic function ABI is identical to the non-variadic
1803 // one. As a result there may be more arguments in registers and we should
1804 // save them for future reference.
1805 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1808 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1809 // This will point to the next argument passed via stack.
1810 unsigned StackOffset = CCInfo.getNextStackOffset();
1811 // We currently pass all varargs at 8-byte alignment.
1812 StackOffset = ((StackOffset + 7) & ~7);
1813 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1816 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1817 unsigned StackArgSize = CCInfo.getNextStackOffset();
1818 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1819 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1820 // This is a non-standard ABI so by fiat I say we're allowed to make full
1821 // use of the stack area to be popped, which must be aligned to 16 bytes in
1823 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1825 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1826 // a multiple of 16.
1827 FuncInfo->setArgumentStackToRestore(StackArgSize);
1829 // This realignment carries over to the available bytes below. Our own
1830 // callers will guarantee the space is free by giving an aligned value to
1833 // Even if we're not expected to free up the space, it's useful to know how
1834 // much is there while considering tail calls (because we can reuse it).
1835 FuncInfo->setBytesInStackArgArea(StackArgSize);
1840 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1841 SelectionDAG &DAG, SDLoc DL,
1842 SDValue &Chain) const {
1843 MachineFunction &MF = DAG.getMachineFunction();
1844 MachineFrameInfo *MFI = MF.getFrameInfo();
1845 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1847 SmallVector<SDValue, 8> MemOps;
1849 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1850 AArch64::X3, AArch64::X4, AArch64::X5,
1851 AArch64::X6, AArch64::X7 };
1852 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1853 unsigned FirstVariadicGPR =
1854 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1856 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1858 if (GPRSaveSize != 0) {
1859 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1861 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1863 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1864 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1865 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1867 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1868 MachinePointerInfo::getStack(i * 8), false, false, 0);
1869 MemOps.push_back(Store);
1870 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1871 DAG.getConstant(8, getPointerTy()));
1874 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1875 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1877 if (Subtarget->hasFPARMv8()) {
1878 static const MCPhysReg FPRArgRegs[] = {
1879 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1880 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1881 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1882 unsigned FirstVariadicFPR =
1883 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1885 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1887 if (FPRSaveSize != 0) {
1888 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1890 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1892 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1893 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1894 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1897 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1898 MachinePointerInfo::getStack(i * 16), false, false, 0);
1899 MemOps.push_back(Store);
1900 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1901 DAG.getConstant(16, getPointerTy()));
1904 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1905 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1908 if (!MemOps.empty()) {
1909 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1913 /// LowerCallResult - Lower the result values of a call into the
1914 /// appropriate copies out of appropriate physical registers.
1915 SDValue AArch64TargetLowering::LowerCallResult(
1916 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1917 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1918 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1919 SDValue ThisVal) const {
1920 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1921 ? RetCC_AArch64_WebKit_JS
1922 : RetCC_AArch64_AAPCS;
1923 // Assign locations to each value returned by this call.
1924 SmallVector<CCValAssign, 16> RVLocs;
1925 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1926 getTargetMachine(), RVLocs, *DAG.getContext());
1927 CCInfo.AnalyzeCallResult(Ins, RetCC);
1929 // Copy all of the result registers out of their specified physreg.
1930 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1931 CCValAssign VA = RVLocs[i];
1933 // Pass 'this' value directly from the argument to return value, to avoid
1934 // reg unit interference
1935 if (i == 0 && isThisReturn) {
1936 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1937 "unexpected return calling convention register assignment");
1938 InVals.push_back(ThisVal);
1943 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1944 Chain = Val.getValue(1);
1945 InFlag = Val.getValue(2);
1947 switch (VA.getLocInfo()) {
1949 llvm_unreachable("Unknown loc info!");
1950 case CCValAssign::Full:
1952 case CCValAssign::BCvt:
1953 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1957 InVals.push_back(Val);
1963 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1964 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1965 bool isCalleeStructRet, bool isCallerStructRet,
1966 const SmallVectorImpl<ISD::OutputArg> &Outs,
1967 const SmallVectorImpl<SDValue> &OutVals,
1968 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1969 // For CallingConv::C this function knows whether the ABI needs
1970 // changing. That's not true for other conventions so they will have to opt in
1972 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1975 const MachineFunction &MF = DAG.getMachineFunction();
1976 const Function *CallerF = MF.getFunction();
1977 CallingConv::ID CallerCC = CallerF->getCallingConv();
1978 bool CCMatch = CallerCC == CalleeCC;
1980 // Byval parameters hand the function a pointer directly into the stack area
1981 // we want to reuse during a tail call. Working around this *is* possible (see
1982 // X86) but less efficient and uglier in LowerCall.
1983 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1984 e = CallerF->arg_end();
1986 if (i->hasByValAttr())
1989 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1990 if (IsTailCallConvention(CalleeCC) && CCMatch)
1995 // Now we search for cases where we can use a tail call without changing the
1996 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1999 // I want anyone implementing a new calling convention to think long and hard
2000 // about this assert.
2001 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2002 "Unexpected variadic calling convention");
2004 if (isVarArg && !Outs.empty()) {
2005 // At least two cases here: if caller is fastcc then we can't have any
2006 // memory arguments (we'd be expected to clean up the stack afterwards). If
2007 // caller is C then we could potentially use its argument area.
2009 // FIXME: for now we take the most conservative of these in both cases:
2010 // disallow all variadic memory operands.
2011 SmallVector<CCValAssign, 16> ArgLocs;
2012 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2013 getTargetMachine(), ArgLocs, *DAG.getContext());
2015 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2016 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2017 if (!ArgLocs[i].isRegLoc())
2021 // If the calling conventions do not match, then we'd better make sure the
2022 // results are returned in the same way as what the caller expects.
2024 SmallVector<CCValAssign, 16> RVLocs1;
2025 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2026 getTargetMachine(), RVLocs1, *DAG.getContext());
2027 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2029 SmallVector<CCValAssign, 16> RVLocs2;
2030 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2031 getTargetMachine(), RVLocs2, *DAG.getContext());
2032 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2034 if (RVLocs1.size() != RVLocs2.size())
2036 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2037 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2039 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2041 if (RVLocs1[i].isRegLoc()) {
2042 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2045 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2051 // Nothing more to check if the callee is taking no arguments
2055 SmallVector<CCValAssign, 16> ArgLocs;
2056 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2057 getTargetMachine(), ArgLocs, *DAG.getContext());
2059 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2061 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2063 // If the stack arguments for this call would fit into our own save area then
2064 // the call can be made tail.
2065 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2068 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2070 MachineFrameInfo *MFI,
2071 int ClobberedFI) const {
2072 SmallVector<SDValue, 8> ArgChains;
2073 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2074 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2076 // Include the original chain at the beginning of the list. When this is
2077 // used by target LowerCall hooks, this helps legalize find the
2078 // CALLSEQ_BEGIN node.
2079 ArgChains.push_back(Chain);
2081 // Add a chain value for each stack argument corresponding
2082 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2083 UE = DAG.getEntryNode().getNode()->use_end();
2085 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2086 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2087 if (FI->getIndex() < 0) {
2088 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2089 int64_t InLastByte = InFirstByte;
2090 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2092 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2093 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2094 ArgChains.push_back(SDValue(L, 1));
2097 // Build a tokenfactor for all the chains.
2098 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2101 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2102 bool TailCallOpt) const {
2103 return CallCC == CallingConv::Fast && TailCallOpt;
2106 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2107 return CallCC == CallingConv::Fast;
2110 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2111 /// and add input and output parameter nodes.
2113 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2114 SmallVectorImpl<SDValue> &InVals) const {
2115 SelectionDAG &DAG = CLI.DAG;
2117 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2118 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2119 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2120 SDValue Chain = CLI.Chain;
2121 SDValue Callee = CLI.Callee;
2122 bool &IsTailCall = CLI.IsTailCall;
2123 CallingConv::ID CallConv = CLI.CallConv;
2124 bool IsVarArg = CLI.IsVarArg;
2126 MachineFunction &MF = DAG.getMachineFunction();
2127 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2128 bool IsThisReturn = false;
2130 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2131 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2132 bool IsSibCall = false;
2135 // Check if it's really possible to do a tail call.
2136 IsTailCall = isEligibleForTailCallOptimization(
2137 Callee, CallConv, IsVarArg, IsStructRet,
2138 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2139 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2140 report_fatal_error("failed to perform tail call elimination on a call "
2141 "site marked musttail");
2143 // A sibling call is one where we're under the usual C ABI and not planning
2144 // to change that but can still do a tail call:
2145 if (!TailCallOpt && IsTailCall)
2152 // Analyze operands of the call, assigning locations to each operand.
2153 SmallVector<CCValAssign, 16> ArgLocs;
2154 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2155 getTargetMachine(), ArgLocs, *DAG.getContext());
2158 // Handle fixed and variable vector arguments differently.
2159 // Variable vector arguments always go into memory.
2160 unsigned NumArgs = Outs.size();
2162 for (unsigned i = 0; i != NumArgs; ++i) {
2163 MVT ArgVT = Outs[i].VT;
2164 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2165 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2166 /*IsVarArg=*/ !Outs[i].IsFixed);
2167 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2168 assert(!Res && "Call operand has unhandled type");
2172 // At this point, Outs[].VT may already be promoted to i32. To correctly
2173 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2174 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2175 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2176 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2178 unsigned NumArgs = Outs.size();
2179 for (unsigned i = 0; i != NumArgs; ++i) {
2180 MVT ValVT = Outs[i].VT;
2181 // Get type of the original argument.
2182 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2183 /*AllowUnknown*/ true);
2184 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2185 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2186 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2188 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2190 else if (ActualMVT == MVT::i16)
2193 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2194 bool Res = AssignFn(i, ValVT, LocVT, CCValAssign::Full, ArgFlags, CCInfo);
2195 assert(!Res && "Call operand has unhandled type");
2200 // Get a count of how many bytes are to be pushed on the stack.
2201 unsigned NumBytes = CCInfo.getNextStackOffset();
2204 // Since we're not changing the ABI to make this a tail call, the memory
2205 // operands are already available in the caller's incoming argument space.
2209 // FPDiff is the byte offset of the call's argument area from the callee's.
2210 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2211 // by this amount for a tail call. In a sibling call it must be 0 because the
2212 // caller will deallocate the entire stack and the callee still expects its
2213 // arguments to begin at SP+0. Completely unused for non-tail calls.
2216 if (IsTailCall && !IsSibCall) {
2217 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2219 // Since callee will pop argument stack as a tail call, we must keep the
2220 // popped size 16-byte aligned.
2221 NumBytes = RoundUpToAlignment(NumBytes, 16);
2223 // FPDiff will be negative if this tail call requires more space than we
2224 // would automatically have in our incoming argument space. Positive if we
2225 // can actually shrink the stack.
2226 FPDiff = NumReusableBytes - NumBytes;
2228 // The stack pointer must be 16-byte aligned at all times it's used for a
2229 // memory operation, which in practice means at *all* times and in
2230 // particular across call boundaries. Therefore our own arguments started at
2231 // a 16-byte aligned SP and the delta applied for the tail call should
2232 // satisfy the same constraint.
2233 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2236 // Adjust the stack pointer for the new arguments...
2237 // These operations are automatically eliminated by the prolog/epilog pass
2240 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2242 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2244 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2245 SmallVector<SDValue, 8> MemOpChains;
2247 // Walk the register/memloc assignments, inserting copies/loads.
2248 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2249 ++i, ++realArgIdx) {
2250 CCValAssign &VA = ArgLocs[i];
2251 SDValue Arg = OutVals[realArgIdx];
2252 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2254 // Promote the value if needed.
2255 switch (VA.getLocInfo()) {
2257 llvm_unreachable("Unknown loc info!");
2258 case CCValAssign::Full:
2260 case CCValAssign::SExt:
2261 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2263 case CCValAssign::ZExt:
2264 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2266 case CCValAssign::AExt:
2267 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2269 case CCValAssign::BCvt:
2270 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2272 case CCValAssign::FPExt:
2273 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2277 if (VA.isRegLoc()) {
2278 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2279 assert(VA.getLocVT() == MVT::i64 &&
2280 "unexpected calling convention register assignment");
2281 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2282 "unexpected use of 'returned'");
2283 IsThisReturn = true;
2285 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2287 assert(VA.isMemLoc());
2290 MachinePointerInfo DstInfo;
2292 // FIXME: This works on big-endian for composite byvals, which are the
2293 // common case. It should also work for fundamental types too.
2294 uint32_t BEAlign = 0;
2295 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2296 : VA.getLocVT().getSizeInBits();
2297 OpSize = (OpSize + 7) / 8;
2298 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2300 BEAlign = 8 - OpSize;
2302 unsigned LocMemOffset = VA.getLocMemOffset();
2303 int32_t Offset = LocMemOffset + BEAlign;
2304 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2305 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2308 Offset = Offset + FPDiff;
2309 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2311 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2312 DstInfo = MachinePointerInfo::getFixedStack(FI);
2314 // Make sure any stack arguments overlapping with where we're storing
2315 // are loaded before this eventual operation. Otherwise they'll be
2317 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2319 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2321 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2322 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2325 if (Outs[i].Flags.isByVal()) {
2327 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2328 SDValue Cpy = DAG.getMemcpy(
2329 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2330 /*isVolatile = */ false,
2331 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2333 MemOpChains.push_back(Cpy);
2335 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2336 // promoted to a legal register type i32, we should truncate Arg back to
2338 if (Arg.getValueType().isSimple() &&
2339 Arg.getValueType().getSimpleVT() == MVT::i32 &&
2340 (VA.getLocVT() == MVT::i1 || VA.getLocVT() == MVT::i8 ||
2341 VA.getLocVT() == MVT::i16))
2342 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getLocVT(), Arg);
2345 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2346 MemOpChains.push_back(Store);
2351 if (!MemOpChains.empty())
2352 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2354 // Build a sequence of copy-to-reg nodes chained together with token chain
2355 // and flag operands which copy the outgoing args into the appropriate regs.
2357 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2358 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2359 RegsToPass[i].second, InFlag);
2360 InFlag = Chain.getValue(1);
2363 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2364 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2365 // node so that legalize doesn't hack it.
2366 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2367 Subtarget->isTargetMachO()) {
2368 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2369 const GlobalValue *GV = G->getGlobal();
2370 bool InternalLinkage = GV->hasInternalLinkage();
2371 if (InternalLinkage)
2372 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2374 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2376 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2378 } else if (ExternalSymbolSDNode *S =
2379 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2380 const char *Sym = S->getSymbol();
2382 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2383 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2385 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2386 const GlobalValue *GV = G->getGlobal();
2387 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2388 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2389 const char *Sym = S->getSymbol();
2390 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2393 // We don't usually want to end the call-sequence here because we would tidy
2394 // the frame up *after* the call, however in the ABI-changing tail-call case
2395 // we've carefully laid out the parameters so that when sp is reset they'll be
2396 // in the correct location.
2397 if (IsTailCall && !IsSibCall) {
2398 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2399 DAG.getIntPtrConstant(0, true), InFlag, DL);
2400 InFlag = Chain.getValue(1);
2403 std::vector<SDValue> Ops;
2404 Ops.push_back(Chain);
2405 Ops.push_back(Callee);
2408 // Each tail call may have to adjust the stack by a different amount, so
2409 // this information must travel along with the operation for eventual
2410 // consumption by emitEpilogue.
2411 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2414 // Add argument registers to the end of the list so that they are known live
2416 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2417 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2418 RegsToPass[i].second.getValueType()));
2420 // Add a register mask operand representing the call-preserved registers.
2421 const uint32_t *Mask;
2422 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2423 const AArch64RegisterInfo *ARI =
2424 static_cast<const AArch64RegisterInfo *>(TRI);
2426 // For 'this' returns, use the X0-preserving mask if applicable
2427 Mask = ARI->getThisReturnPreservedMask(CallConv);
2429 IsThisReturn = false;
2430 Mask = ARI->getCallPreservedMask(CallConv);
2433 Mask = ARI->getCallPreservedMask(CallConv);
2435 assert(Mask && "Missing call preserved mask for calling convention");
2436 Ops.push_back(DAG.getRegisterMask(Mask));
2438 if (InFlag.getNode())
2439 Ops.push_back(InFlag);
2441 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2443 // If we're doing a tall call, use a TC_RETURN here rather than an
2444 // actual call instruction.
2446 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2448 // Returns a chain and a flag for retval copy to use.
2449 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2450 InFlag = Chain.getValue(1);
2452 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2453 ? RoundUpToAlignment(NumBytes, 16)
2456 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2457 DAG.getIntPtrConstant(CalleePopBytes, true),
2460 InFlag = Chain.getValue(1);
2462 // Handle result values, copying them out of physregs into vregs that we
2464 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2465 InVals, IsThisReturn,
2466 IsThisReturn ? OutVals[0] : SDValue());
2469 bool AArch64TargetLowering::CanLowerReturn(
2470 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2471 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2472 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2473 ? RetCC_AArch64_WebKit_JS
2474 : RetCC_AArch64_AAPCS;
2475 SmallVector<CCValAssign, 16> RVLocs;
2476 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2477 return CCInfo.CheckReturn(Outs, RetCC);
2481 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2483 const SmallVectorImpl<ISD::OutputArg> &Outs,
2484 const SmallVectorImpl<SDValue> &OutVals,
2485 SDLoc DL, SelectionDAG &DAG) const {
2486 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2487 ? RetCC_AArch64_WebKit_JS
2488 : RetCC_AArch64_AAPCS;
2489 SmallVector<CCValAssign, 16> RVLocs;
2490 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2491 getTargetMachine(), RVLocs, *DAG.getContext());
2492 CCInfo.AnalyzeReturn(Outs, RetCC);
2494 // Copy the result values into the output registers.
2496 SmallVector<SDValue, 4> RetOps(1, Chain);
2497 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2498 ++i, ++realRVLocIdx) {
2499 CCValAssign &VA = RVLocs[i];
2500 assert(VA.isRegLoc() && "Can only return in registers!");
2501 SDValue Arg = OutVals[realRVLocIdx];
2503 switch (VA.getLocInfo()) {
2505 llvm_unreachable("Unknown loc info!");
2506 case CCValAssign::Full:
2508 case CCValAssign::BCvt:
2509 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2513 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2514 Flag = Chain.getValue(1);
2515 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2518 RetOps[0] = Chain; // Update chain.
2520 // Add the flag if we have it.
2522 RetOps.push_back(Flag);
2524 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2527 //===----------------------------------------------------------------------===//
2528 // Other Lowering Code
2529 //===----------------------------------------------------------------------===//
2531 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2532 SelectionDAG &DAG) const {
2533 EVT PtrVT = getPointerTy();
2535 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2536 unsigned char OpFlags =
2537 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2539 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2540 "unexpected offset in global node");
2542 // This also catched the large code model case for Darwin.
2543 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2544 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2545 // FIXME: Once remat is capable of dealing with instructions with register
2546 // operands, expand this into two nodes instead of using a wrapper node.
2547 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2550 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2551 const unsigned char MO_NC = AArch64II::MO_NC;
2553 AArch64ISD::WrapperLarge, DL, PtrVT,
2554 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2555 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2556 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2557 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2559 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2560 // the only correct model on Darwin.
2561 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2562 OpFlags | AArch64II::MO_PAGE);
2563 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2564 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2566 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2567 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2571 /// \brief Convert a TLS address reference into the correct sequence of loads
2572 /// and calls to compute the variable's address (for Darwin, currently) and
2573 /// return an SDValue containing the final node.
2575 /// Darwin only has one TLS scheme which must be capable of dealing with the
2576 /// fully general situation, in the worst case. This means:
2577 /// + "extern __thread" declaration.
2578 /// + Defined in a possibly unknown dynamic library.
2580 /// The general system is that each __thread variable has a [3 x i64] descriptor
2581 /// which contains information used by the runtime to calculate the address. The
2582 /// only part of this the compiler needs to know about is the first xword, which
2583 /// contains a function pointer that must be called with the address of the
2584 /// entire descriptor in "x0".
2586 /// Since this descriptor may be in a different unit, in general even the
2587 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2589 /// adrp x0, _var@TLVPPAGE
2590 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2591 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2592 /// ; the function pointer
2593 /// blr x1 ; Uses descriptor address in x0
2594 /// ; Address of _var is now in x0.
2596 /// If the address of _var's descriptor *is* known to the linker, then it can
2597 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2598 /// a slight efficiency gain.
2600 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2601 SelectionDAG &DAG) const {
2602 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2605 MVT PtrVT = getPointerTy();
2606 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2609 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2610 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2612 // The first entry in the descriptor is a function pointer that we must call
2613 // to obtain the address of the variable.
2614 SDValue Chain = DAG.getEntryNode();
2615 SDValue FuncTLVGet =
2616 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2617 false, true, true, 8);
2618 Chain = FuncTLVGet.getValue(1);
2620 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2621 MFI->setAdjustsStack(true);
2623 // TLS calls preserve all registers except those that absolutely must be
2624 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2626 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2627 const AArch64RegisterInfo *ARI =
2628 static_cast<const AArch64RegisterInfo *>(TRI);
2629 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2631 // Finally, we can make the call. This is just a degenerate version of a
2632 // normal AArch64 call node: x0 takes the address of the descriptor, and
2633 // returns the address of the variable in this thread.
2634 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2636 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2637 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2638 DAG.getRegisterMask(Mask), Chain.getValue(1));
2639 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2642 /// When accessing thread-local variables under either the general-dynamic or
2643 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2644 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2645 /// is a function pointer to carry out the resolution. This function takes the
2646 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2647 /// other registers (except LR, NZCV) are preserved.
2649 /// Thus, the ideal call sequence on AArch64 is:
2651 /// adrp x0, :tlsdesc:thread_var
2652 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2653 /// add x0, x0, :tlsdesc_lo12:thread_var
2654 /// .tlsdesccall thread_var
2656 /// (TPIDR_EL0 offset now in x0).
2658 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2659 /// relocation to help the linker relax this sequence if it turns out to be too
2662 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2664 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2665 SDValue DescAddr, SDLoc DL,
2666 SelectionDAG &DAG) const {
2667 EVT PtrVT = getPointerTy();
2669 // The function we need to call is simply the first entry in the GOT for this
2670 // descriptor, load it in preparation.
2671 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2673 // TLS calls preserve all registers except those that absolutely must be
2674 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2676 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2677 const AArch64RegisterInfo *ARI =
2678 static_cast<const AArch64RegisterInfo *>(TRI);
2679 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2681 // The function takes only one argument: the address of the descriptor itself
2683 SDValue Glue, Chain;
2684 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2685 Glue = Chain.getValue(1);
2687 // We're now ready to populate the argument list, as with a normal call:
2688 SmallVector<SDValue, 6> Ops;
2689 Ops.push_back(Chain);
2690 Ops.push_back(Func);
2691 Ops.push_back(SymAddr);
2692 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2693 Ops.push_back(DAG.getRegisterMask(Mask));
2694 Ops.push_back(Glue);
2696 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2697 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2698 Glue = Chain.getValue(1);
2700 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2704 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2705 SelectionDAG &DAG) const {
2706 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2707 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2708 "ELF TLS only supported in small memory model");
2709 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2711 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2714 EVT PtrVT = getPointerTy();
2716 const GlobalValue *GV = GA->getGlobal();
2718 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2720 if (Model == TLSModel::LocalExec) {
2721 SDValue HiVar = DAG.getTargetGlobalAddress(
2722 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2723 SDValue LoVar = DAG.getTargetGlobalAddress(
2725 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2727 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2728 DAG.getTargetConstant(16, MVT::i32)),
2730 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2731 DAG.getTargetConstant(0, MVT::i32)),
2733 } else if (Model == TLSModel::InitialExec) {
2734 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2735 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2736 } else if (Model == TLSModel::LocalDynamic) {
2737 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2738 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2739 // the beginning of the module's TLS region, followed by a DTPREL offset
2742 // These accesses will need deduplicating if there's more than one.
2743 AArch64FunctionInfo *MFI =
2744 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2745 MFI->incNumLocalDynamicTLSAccesses();
2747 // Accesses used in this sequence go via the TLS descriptor which lives in
2748 // the GOT. Prepare an address we can use to handle this.
2749 SDValue HiDesc = DAG.getTargetExternalSymbol(
2750 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2751 SDValue LoDesc = DAG.getTargetExternalSymbol(
2752 "_TLS_MODULE_BASE_", PtrVT,
2753 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2755 // First argument to the descriptor call is the address of the descriptor
2757 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2758 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2760 // The call needs a relocation too for linker relaxation. It doesn't make
2761 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2763 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2766 // Now we can calculate the offset from TPIDR_EL0 to this module's
2767 // thread-local area.
2768 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2770 // Now use :dtprel_whatever: operations to calculate this variable's offset
2771 // in its thread-storage area.
2772 SDValue HiVar = DAG.getTargetGlobalAddress(
2773 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2774 SDValue LoVar = DAG.getTargetGlobalAddress(
2775 GV, DL, MVT::i64, 0,
2776 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2779 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2780 DAG.getTargetConstant(16, MVT::i32)),
2783 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2784 DAG.getTargetConstant(0, MVT::i32)),
2787 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2788 } else if (Model == TLSModel::GeneralDynamic) {
2789 // Accesses used in this sequence go via the TLS descriptor which lives in
2790 // the GOT. Prepare an address we can use to handle this.
2791 SDValue HiDesc = DAG.getTargetGlobalAddress(
2792 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2793 SDValue LoDesc = DAG.getTargetGlobalAddress(
2795 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2797 // First argument to the descriptor call is the address of the descriptor
2799 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2800 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2802 // The call needs a relocation too for linker relaxation. It doesn't make
2803 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2806 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2808 // Finally we can make a call to calculate the offset from tpidr_el0.
2809 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2811 llvm_unreachable("Unsupported ELF TLS access model");
2813 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2816 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2817 SelectionDAG &DAG) const {
2818 if (Subtarget->isTargetDarwin())
2819 return LowerDarwinGlobalTLSAddress(Op, DAG);
2820 else if (Subtarget->isTargetELF())
2821 return LowerELFGlobalTLSAddress(Op, DAG);
2823 llvm_unreachable("Unexpected platform trying to use TLS");
2825 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2826 SDValue Chain = Op.getOperand(0);
2827 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2828 SDValue LHS = Op.getOperand(2);
2829 SDValue RHS = Op.getOperand(3);
2830 SDValue Dest = Op.getOperand(4);
2833 // Handle f128 first, since lowering it will result in comparing the return
2834 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2835 // is expecting to deal with.
2836 if (LHS.getValueType() == MVT::f128) {
2837 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2839 // If softenSetCCOperands returned a scalar, we need to compare the result
2840 // against zero to select between true and false values.
2841 if (!RHS.getNode()) {
2842 RHS = DAG.getConstant(0, LHS.getValueType());
2847 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2849 unsigned Opc = LHS.getOpcode();
2850 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2851 cast<ConstantSDNode>(RHS)->isOne() &&
2852 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2853 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2854 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2855 "Unexpected condition code.");
2856 // Only lower legal XALUO ops.
2857 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2860 // The actual operation with overflow check.
2861 AArch64CC::CondCode OFCC;
2862 SDValue Value, Overflow;
2863 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2865 if (CC == ISD::SETNE)
2866 OFCC = getInvertedCondCode(OFCC);
2867 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2869 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2873 if (LHS.getValueType().isInteger()) {
2874 assert((LHS.getValueType() == RHS.getValueType()) &&
2875 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2877 // If the RHS of the comparison is zero, we can potentially fold this
2878 // to a specialized branch.
2879 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2880 if (RHSC && RHSC->getZExtValue() == 0) {
2881 if (CC == ISD::SETEQ) {
2882 // See if we can use a TBZ to fold in an AND as well.
2883 // TBZ has a smaller branch displacement than CBZ. If the offset is
2884 // out of bounds, a late MI-layer pass rewrites branches.
2885 // 403.gcc is an example that hits this case.
2886 if (LHS.getOpcode() == ISD::AND &&
2887 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2888 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2889 SDValue Test = LHS.getOperand(0);
2890 uint64_t Mask = LHS.getConstantOperandVal(1);
2892 // TBZ only operates on i64's, but the ext should be free.
2893 if (Test.getValueType() == MVT::i32)
2894 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2896 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2897 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2900 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2901 } else if (CC == ISD::SETNE) {
2902 // See if we can use a TBZ to fold in an AND as well.
2903 // TBZ has a smaller branch displacement than CBZ. If the offset is
2904 // out of bounds, a late MI-layer pass rewrites branches.
2905 // 403.gcc is an example that hits this case.
2906 if (LHS.getOpcode() == ISD::AND &&
2907 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2908 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2909 SDValue Test = LHS.getOperand(0);
2910 uint64_t Mask = LHS.getConstantOperandVal(1);
2912 // TBNZ only operates on i64's, but the ext should be free.
2913 if (Test.getValueType() == MVT::i32)
2914 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2916 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2917 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2920 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2925 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2926 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2930 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2932 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2933 // clean. Some of them require two branches to implement.
2934 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2935 AArch64CC::CondCode CC1, CC2;
2936 changeFPCCToAArch64CC(CC, CC1, CC2);
2937 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2939 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2940 if (CC2 != AArch64CC::AL) {
2941 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2942 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2949 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2950 SelectionDAG &DAG) const {
2951 EVT VT = Op.getValueType();
2954 SDValue In1 = Op.getOperand(0);
2955 SDValue In2 = Op.getOperand(1);
2956 EVT SrcVT = In2.getValueType();
2958 if (SrcVT == MVT::f32 && VT == MVT::f64)
2959 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2960 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2961 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2963 // FIXME: Src type is different, bail out for now. Can VT really be a
2970 SDValue EltMask, VecVal1, VecVal2;
2971 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2974 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2976 if (!VT.isVector()) {
2977 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2978 DAG.getUNDEF(VecVT), In1);
2979 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2980 DAG.getUNDEF(VecVT), In2);
2982 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2983 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2985 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
2989 // We want to materialize a mask with the the high bit set, but the AdvSIMD
2990 // immediate moves cannot materialize that in a single instruction for
2991 // 64-bit elements. Instead, materialize zero and then negate it.
2992 EltMask = DAG.getConstant(0, EltVT);
2994 if (!VT.isVector()) {
2995 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
2996 DAG.getUNDEF(VecVT), In1);
2997 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
2998 DAG.getUNDEF(VecVT), In2);
3000 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3001 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3004 llvm_unreachable("Invalid type for copysign!");
3007 std::vector<SDValue> BuildVectorOps;
3008 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3009 BuildVectorOps.push_back(EltMask);
3011 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3013 // If we couldn't materialize the mask above, then the mask vector will be
3014 // the zero vector, and we need to negate it here.
3015 if (VT == MVT::f64 || VT == MVT::v2f64) {
3016 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3017 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3018 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3022 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3025 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3026 else if (VT == MVT::f64)
3027 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3029 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3032 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3033 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3034 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3037 // While there is no integer popcount instruction, it can
3038 // be more efficiently lowered to the following sequence that uses
3039 // AdvSIMD registers/instructions as long as the copies to/from
3040 // the AdvSIMD registers are cheap.
3041 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3042 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3043 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3044 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3045 SDValue Val = Op.getOperand(0);
3047 EVT VT = Op.getValueType();
3048 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3051 if (VT == MVT::i32) {
3052 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3053 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3056 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3059 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3060 SDValue UaddLV = DAG.getNode(
3061 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3062 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3065 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3069 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3071 if (Op.getValueType().isVector())
3072 return LowerVSETCC(Op, DAG);
3074 SDValue LHS = Op.getOperand(0);
3075 SDValue RHS = Op.getOperand(1);
3076 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3079 // We chose ZeroOrOneBooleanContents, so use zero and one.
3080 EVT VT = Op.getValueType();
3081 SDValue TVal = DAG.getConstant(1, VT);
3082 SDValue FVal = DAG.getConstant(0, VT);
3084 // Handle f128 first, since one possible outcome is a normal integer
3085 // comparison which gets picked up by the next if statement.
3086 if (LHS.getValueType() == MVT::f128) {
3087 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3089 // If softenSetCCOperands returned a scalar, use it.
3090 if (!RHS.getNode()) {
3091 assert(LHS.getValueType() == Op.getValueType() &&
3092 "Unexpected setcc expansion!");
3097 if (LHS.getValueType().isInteger()) {
3100 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3102 // Note that we inverted the condition above, so we reverse the order of
3103 // the true and false operands here. This will allow the setcc to be
3104 // matched to a single CSINC instruction.
3105 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3108 // Now we know we're dealing with FP values.
3109 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3111 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3112 // and do the comparison.
3113 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3115 AArch64CC::CondCode CC1, CC2;
3116 changeFPCCToAArch64CC(CC, CC1, CC2);
3117 if (CC2 == AArch64CC::AL) {
3118 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3119 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3121 // Note that we inverted the condition above, so we reverse the order of
3122 // the true and false operands here. This will allow the setcc to be
3123 // matched to a single CSINC instruction.
3124 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3126 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3127 // totally clean. Some of them require two CSELs to implement. As is in
3128 // this case, we emit the first CSEL and then emit a second using the output
3129 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3131 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3132 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3134 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3136 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3137 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3141 /// A SELECT_CC operation is really some kind of max or min if both values being
3142 /// compared are, in some sense, equal to the results in either case. However,
3143 /// it is permissible to compare f32 values and produce directly extended f64
3146 /// Extending the comparison operands would also be allowed, but is less likely
3147 /// to happen in practice since their use is right here. Note that truncate
3148 /// operations would *not* be semantically equivalent.
3149 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3153 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3154 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3155 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3156 Result.getValueType() == MVT::f64) {
3158 APFloat CmpVal = CCmp->getValueAPF();
3159 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3160 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3163 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3166 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3167 SelectionDAG &DAG) const {
3168 SDValue CC = Op->getOperand(0);
3169 SDValue TVal = Op->getOperand(1);
3170 SDValue FVal = Op->getOperand(2);
3173 unsigned Opc = CC.getOpcode();
3174 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3176 if (CC.getResNo() == 1 &&
3177 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3178 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3179 // Only lower legal XALUO ops.
3180 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3183 AArch64CC::CondCode OFCC;
3184 SDValue Value, Overflow;
3185 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3186 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3188 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3192 if (CC.getOpcode() == ISD::SETCC)
3193 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3194 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3196 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3200 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3201 SelectionDAG &DAG) const {
3202 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3203 SDValue LHS = Op.getOperand(0);
3204 SDValue RHS = Op.getOperand(1);
3205 SDValue TVal = Op.getOperand(2);
3206 SDValue FVal = Op.getOperand(3);
3209 // Handle f128 first, because it will result in a comparison of some RTLIB
3210 // call result against zero.
3211 if (LHS.getValueType() == MVT::f128) {
3212 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3214 // If softenSetCCOperands returned a scalar, we need to compare the result
3215 // against zero to select between true and false values.
3216 if (!RHS.getNode()) {
3217 RHS = DAG.getConstant(0, LHS.getValueType());
3222 // Handle integers first.
3223 if (LHS.getValueType().isInteger()) {
3224 assert((LHS.getValueType() == RHS.getValueType()) &&
3225 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3227 unsigned Opcode = AArch64ISD::CSEL;
3229 // If both the TVal and the FVal are constants, see if we can swap them in
3230 // order to for a CSINV or CSINC out of them.
3231 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3232 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3234 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3235 std::swap(TVal, FVal);
3236 std::swap(CTVal, CFVal);
3237 CC = ISD::getSetCCInverse(CC, true);
3238 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3239 std::swap(TVal, FVal);
3240 std::swap(CTVal, CFVal);
3241 CC = ISD::getSetCCInverse(CC, true);
3242 } else if (TVal.getOpcode() == ISD::XOR) {
3243 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3244 // with a CSINV rather than a CSEL.
3245 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3247 if (CVal && CVal->isAllOnesValue()) {
3248 std::swap(TVal, FVal);
3249 std::swap(CTVal, CFVal);
3250 CC = ISD::getSetCCInverse(CC, true);
3252 } else if (TVal.getOpcode() == ISD::SUB) {
3253 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3254 // that we can match with a CSNEG rather than a CSEL.
3255 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3257 if (CVal && CVal->isNullValue()) {
3258 std::swap(TVal, FVal);
3259 std::swap(CTVal, CFVal);
3260 CC = ISD::getSetCCInverse(CC, true);
3262 } else if (CTVal && CFVal) {
3263 const int64_t TrueVal = CTVal->getSExtValue();
3264 const int64_t FalseVal = CFVal->getSExtValue();
3267 // If both TVal and FVal are constants, see if FVal is the
3268 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3269 // instead of a CSEL in that case.
3270 if (TrueVal == ~FalseVal) {
3271 Opcode = AArch64ISD::CSINV;
3272 } else if (TrueVal == -FalseVal) {
3273 Opcode = AArch64ISD::CSNEG;
3274 } else if (TVal.getValueType() == MVT::i32) {
3275 // If our operands are only 32-bit wide, make sure we use 32-bit
3276 // arithmetic for the check whether we can use CSINC. This ensures that
3277 // the addition in the check will wrap around properly in case there is
3278 // an overflow (which would not be the case if we do the check with
3279 // 64-bit arithmetic).
3280 const uint32_t TrueVal32 = CTVal->getZExtValue();
3281 const uint32_t FalseVal32 = CFVal->getZExtValue();
3283 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3284 Opcode = AArch64ISD::CSINC;
3286 if (TrueVal32 > FalseVal32) {
3290 // 64-bit check whether we can use CSINC.
3291 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3292 Opcode = AArch64ISD::CSINC;
3294 if (TrueVal > FalseVal) {
3299 // Swap TVal and FVal if necessary.
3301 std::swap(TVal, FVal);
3302 std::swap(CTVal, CFVal);
3303 CC = ISD::getSetCCInverse(CC, true);
3306 if (Opcode != AArch64ISD::CSEL) {
3307 // Drop FVal since we can get its value by simply inverting/negating
3314 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3316 EVT VT = Op.getValueType();
3317 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3320 // Now we know we're dealing with FP values.
3321 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3322 assert(LHS.getValueType() == RHS.getValueType());
3323 EVT VT = Op.getValueType();
3325 // Try to match this select into a max/min operation, which have dedicated
3326 // opcode in the instruction set.
3327 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3329 if (getTargetMachine().Options.NoNaNsFPMath) {
3330 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3331 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3332 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3333 CC = ISD::getSetCCSwappedOperands(CC);
3334 std::swap(MinMaxLHS, MinMaxRHS);
3337 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3338 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3348 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3356 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3362 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3363 // and do the comparison.
3364 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3366 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3367 // clean. Some of them require two CSELs to implement.
3368 AArch64CC::CondCode CC1, CC2;
3369 changeFPCCToAArch64CC(CC, CC1, CC2);
3370 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3371 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3373 // If we need a second CSEL, emit it, using the output of the first as the
3374 // RHS. We're effectively OR'ing the two CC's together.
3375 if (CC2 != AArch64CC::AL) {
3376 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3377 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3380 // Otherwise, return the output of the first CSEL.
3384 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3385 SelectionDAG &DAG) const {
3386 // Jump table entries as PC relative offsets. No additional tweaking
3387 // is necessary here. Just get the address of the jump table.
3388 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3389 EVT PtrVT = getPointerTy();
3392 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3393 !Subtarget->isTargetMachO()) {
3394 const unsigned char MO_NC = AArch64II::MO_NC;
3396 AArch64ISD::WrapperLarge, DL, PtrVT,
3397 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3398 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3399 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3400 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3401 AArch64II::MO_G0 | MO_NC));
3405 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3406 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3407 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3408 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3409 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3412 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3413 SelectionDAG &DAG) const {
3414 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3415 EVT PtrVT = getPointerTy();
3418 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3419 // Use the GOT for the large code model on iOS.
3420 if (Subtarget->isTargetMachO()) {
3421 SDValue GotAddr = DAG.getTargetConstantPool(
3422 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3424 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3427 const unsigned char MO_NC = AArch64II::MO_NC;
3429 AArch64ISD::WrapperLarge, DL, PtrVT,
3430 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3431 CP->getOffset(), AArch64II::MO_G3),
3432 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3433 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3434 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3435 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3436 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3437 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3439 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3440 // ELF, the only valid one on Darwin.
3442 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3443 CP->getOffset(), AArch64II::MO_PAGE);
3444 SDValue Lo = DAG.getTargetConstantPool(
3445 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3446 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3448 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3449 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3453 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3454 SelectionDAG &DAG) const {
3455 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3456 EVT PtrVT = getPointerTy();
3458 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3459 !Subtarget->isTargetMachO()) {
3460 const unsigned char MO_NC = AArch64II::MO_NC;
3462 AArch64ISD::WrapperLarge, DL, PtrVT,
3463 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3464 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3465 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3466 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3468 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3469 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3471 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3472 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3476 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3477 SelectionDAG &DAG) const {
3478 AArch64FunctionInfo *FuncInfo =
3479 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3483 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3484 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3485 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3486 MachinePointerInfo(SV), false, false, 0);
3489 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3490 SelectionDAG &DAG) const {
3491 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3492 // Standard, section B.3.
3493 MachineFunction &MF = DAG.getMachineFunction();
3494 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3497 SDValue Chain = Op.getOperand(0);
3498 SDValue VAList = Op.getOperand(1);
3499 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3500 SmallVector<SDValue, 4> MemOps;
3502 // void *__stack at offset 0
3504 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3505 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3506 MachinePointerInfo(SV), false, false, 8));
3508 // void *__gr_top at offset 8
3509 int GPRSize = FuncInfo->getVarArgsGPRSize();
3511 SDValue GRTop, GRTopAddr;
3513 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3514 DAG.getConstant(8, getPointerTy()));
3516 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3517 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3518 DAG.getConstant(GPRSize, getPointerTy()));
3520 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3521 MachinePointerInfo(SV, 8), false, false, 8));
3524 // void *__vr_top at offset 16
3525 int FPRSize = FuncInfo->getVarArgsFPRSize();
3527 SDValue VRTop, VRTopAddr;
3528 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3529 DAG.getConstant(16, getPointerTy()));
3531 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3532 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3533 DAG.getConstant(FPRSize, getPointerTy()));
3535 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3536 MachinePointerInfo(SV, 16), false, false, 8));
3539 // int __gr_offs at offset 24
3540 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3541 DAG.getConstant(24, getPointerTy()));
3542 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3543 GROffsAddr, MachinePointerInfo(SV, 24), false,
3546 // int __vr_offs at offset 28
3547 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3548 DAG.getConstant(28, getPointerTy()));
3549 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3550 VROffsAddr, MachinePointerInfo(SV, 28), false,
3553 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3556 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3557 SelectionDAG &DAG) const {
3558 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3559 : LowerAAPCS_VASTART(Op, DAG);
3562 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3563 SelectionDAG &DAG) const {
3564 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3566 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3567 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3568 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3570 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3571 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3572 8, false, false, MachinePointerInfo(DestSV),
3573 MachinePointerInfo(SrcSV));
3576 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3577 assert(Subtarget->isTargetDarwin() &&
3578 "automatic va_arg instruction only works on Darwin");
3580 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3581 EVT VT = Op.getValueType();
3583 SDValue Chain = Op.getOperand(0);
3584 SDValue Addr = Op.getOperand(1);
3585 unsigned Align = Op.getConstantOperandVal(3);
3587 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3588 MachinePointerInfo(V), false, false, false, 0);
3589 Chain = VAList.getValue(1);
3592 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3593 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3594 DAG.getConstant(Align - 1, getPointerTy()));
3595 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3596 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3599 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3600 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3602 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3603 // up to 64 bits. At the very least, we have to increase the striding of the
3604 // vaargs list to match this, and for FP values we need to introduce
3605 // FP_ROUND nodes as well.
3606 if (VT.isInteger() && !VT.isVector())
3608 bool NeedFPTrunc = false;
3609 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3614 // Increment the pointer, VAList, to the next vaarg
3615 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3616 DAG.getConstant(ArgSize, getPointerTy()));
3617 // Store the incremented VAList to the legalized pointer
3618 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3621 // Load the actual argument out of the pointer VAList
3623 // Load the value as an f64.
3624 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3625 MachinePointerInfo(), false, false, false, 0);
3626 // Round the value down to an f32.
3627 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3628 DAG.getIntPtrConstant(1));
3629 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3630 // Merge the rounded value with the chain output of the load.
3631 return DAG.getMergeValues(Ops, DL);
3634 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3638 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3639 SelectionDAG &DAG) const {
3640 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3641 MFI->setFrameAddressIsTaken(true);
3643 EVT VT = Op.getValueType();
3645 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3647 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3649 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3650 MachinePointerInfo(), false, false, false, 0);
3654 // FIXME? Maybe this could be a TableGen attribute on some registers and
3655 // this table could be generated automatically from RegInfo.
3656 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3658 unsigned Reg = StringSwitch<unsigned>(RegName)
3659 .Case("sp", AArch64::SP)
3663 report_fatal_error("Invalid register name global variable");
3666 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3667 SelectionDAG &DAG) const {
3668 MachineFunction &MF = DAG.getMachineFunction();
3669 MachineFrameInfo *MFI = MF.getFrameInfo();
3670 MFI->setReturnAddressIsTaken(true);
3672 EVT VT = Op.getValueType();
3674 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3676 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3677 SDValue Offset = DAG.getConstant(8, getPointerTy());
3678 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3679 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3680 MachinePointerInfo(), false, false, false, 0);
3683 // Return LR, which contains the return address. Mark it an implicit live-in.
3684 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3685 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3688 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3689 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3690 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3691 SelectionDAG &DAG) const {
3692 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3693 EVT VT = Op.getValueType();
3694 unsigned VTBits = VT.getSizeInBits();
3696 SDValue ShOpLo = Op.getOperand(0);
3697 SDValue ShOpHi = Op.getOperand(1);
3698 SDValue ShAmt = Op.getOperand(2);
3700 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3702 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3704 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3705 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3706 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3707 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3708 DAG.getConstant(VTBits, MVT::i64));
3709 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3711 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3712 ISD::SETGE, dl, DAG);
3713 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3715 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3716 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3718 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3720 // AArch64 shifts larger than the register width are wrapped rather than
3721 // clamped, so we can't just emit "hi >> x".
3722 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3723 SDValue TrueValHi = Opc == ISD::SRA
3724 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3725 DAG.getConstant(VTBits - 1, MVT::i64))
3726 : DAG.getConstant(0, VT);
3728 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3730 SDValue Ops[2] = { Lo, Hi };
3731 return DAG.getMergeValues(Ops, dl);
3734 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3735 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3736 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3737 SelectionDAG &DAG) const {
3738 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3739 EVT VT = Op.getValueType();
3740 unsigned VTBits = VT.getSizeInBits();
3742 SDValue ShOpLo = Op.getOperand(0);
3743 SDValue ShOpHi = Op.getOperand(1);
3744 SDValue ShAmt = Op.getOperand(2);
3747 assert(Op.getOpcode() == ISD::SHL_PARTS);
3748 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3749 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3750 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3751 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3752 DAG.getConstant(VTBits, MVT::i64));
3753 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3754 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3756 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3758 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3759 ISD::SETGE, dl, DAG);
3760 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3762 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3764 // AArch64 shifts of larger than register sizes are wrapped rather than
3765 // clamped, so we can't just emit "lo << a" if a is too big.
3766 SDValue TrueValLo = DAG.getConstant(0, VT);
3767 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3769 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3771 SDValue Ops[2] = { Lo, Hi };
3772 return DAG.getMergeValues(Ops, dl);
3775 bool AArch64TargetLowering::isOffsetFoldingLegal(
3776 const GlobalAddressSDNode *GA) const {
3777 // The AArch64 target doesn't support folding offsets into global addresses.
3781 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3782 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3783 // FIXME: We should be able to handle f128 as well with a clever lowering.
3784 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3788 return AArch64_AM::getFP64Imm(Imm) != -1;
3789 else if (VT == MVT::f32)
3790 return AArch64_AM::getFP32Imm(Imm) != -1;
3794 //===----------------------------------------------------------------------===//
3795 // AArch64 Optimization Hooks
3796 //===----------------------------------------------------------------------===//
3798 //===----------------------------------------------------------------------===//
3799 // AArch64 Inline Assembly Support
3800 //===----------------------------------------------------------------------===//
3802 // Table of Constraints
3803 // TODO: This is the current set of constraints supported by ARM for the
3804 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3806 // r - A general register
3807 // w - An FP/SIMD register of some size in the range v0-v31
3808 // x - An FP/SIMD register of some size in the range v0-v15
3809 // I - Constant that can be used with an ADD instruction
3810 // J - Constant that can be used with a SUB instruction
3811 // K - Constant that can be used with a 32-bit logical instruction
3812 // L - Constant that can be used with a 64-bit logical instruction
3813 // M - Constant that can be used as a 32-bit MOV immediate
3814 // N - Constant that can be used as a 64-bit MOV immediate
3815 // Q - A memory reference with base register and no offset
3816 // S - A symbolic address
3817 // Y - Floating point constant zero
3818 // Z - Integer constant zero
3820 // Note that general register operands will be output using their 64-bit x
3821 // register name, whatever the size of the variable, unless the asm operand
3822 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3823 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3826 /// getConstraintType - Given a constraint letter, return the type of
3827 /// constraint it is for this target.
3828 AArch64TargetLowering::ConstraintType
3829 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3830 if (Constraint.size() == 1) {
3831 switch (Constraint[0]) {
3838 return C_RegisterClass;
3839 // An address with a single base register. Due to the way we
3840 // currently handle addresses it is the same as 'r'.
3845 return TargetLowering::getConstraintType(Constraint);
3848 /// Examine constraint type and operand type and determine a weight value.
3849 /// This object must already have been set up with the operand type
3850 /// and the current alternative constraint selected.
3851 TargetLowering::ConstraintWeight
3852 AArch64TargetLowering::getSingleConstraintMatchWeight(
3853 AsmOperandInfo &info, const char *constraint) const {
3854 ConstraintWeight weight = CW_Invalid;
3855 Value *CallOperandVal = info.CallOperandVal;
3856 // If we don't have a value, we can't do a match,
3857 // but allow it at the lowest weight.
3858 if (!CallOperandVal)
3860 Type *type = CallOperandVal->getType();
3861 // Look at the constraint type.
3862 switch (*constraint) {
3864 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3868 if (type->isFloatingPointTy() || type->isVectorTy())
3869 weight = CW_Register;
3872 weight = CW_Constant;
3878 std::pair<unsigned, const TargetRegisterClass *>
3879 AArch64TargetLowering::getRegForInlineAsmConstraint(
3880 const std::string &Constraint, MVT VT) const {
3881 if (Constraint.size() == 1) {
3882 switch (Constraint[0]) {
3884 if (VT.getSizeInBits() == 64)
3885 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3886 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3889 return std::make_pair(0U, &AArch64::FPR32RegClass);
3890 if (VT.getSizeInBits() == 64)
3891 return std::make_pair(0U, &AArch64::FPR64RegClass);
3892 if (VT.getSizeInBits() == 128)
3893 return std::make_pair(0U, &AArch64::FPR128RegClass);
3895 // The instructions that this constraint is designed for can
3896 // only take 128-bit registers so just use that regclass.
3898 if (VT.getSizeInBits() == 128)
3899 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3903 if (StringRef("{cc}").equals_lower(Constraint))
3904 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3906 // Use the default implementation in TargetLowering to convert the register
3907 // constraint into a member of a register class.
3908 std::pair<unsigned, const TargetRegisterClass *> Res;
3909 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3911 // Not found as a standard register?
3913 unsigned Size = Constraint.size();
3914 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3915 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3916 const std::string Reg =
3917 std::string(&Constraint[2], &Constraint[Size - 1]);
3918 int RegNo = atoi(Reg.c_str());
3919 if (RegNo >= 0 && RegNo <= 31) {
3920 // v0 - v31 are aliases of q0 - q31.
3921 // By default we'll emit v0-v31 for this unless there's a modifier where
3922 // we'll emit the correct register as well.
3923 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3924 Res.second = &AArch64::FPR128RegClass;
3932 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3933 /// vector. If it is invalid, don't add anything to Ops.
3934 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3935 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3936 SelectionDAG &DAG) const {
3939 // Currently only support length 1 constraints.
3940 if (Constraint.length() != 1)
3943 char ConstraintLetter = Constraint[0];
3944 switch (ConstraintLetter) {
3948 // This set of constraints deal with valid constants for various instructions.
3949 // Validate and return a target constant for them if we can.
3951 // 'z' maps to xzr or wzr so it needs an input of 0.
3952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3953 if (!C || C->getZExtValue() != 0)
3956 if (Op.getValueType() == MVT::i64)
3957 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3959 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3969 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3973 // Grab the value and do some validation.
3974 uint64_t CVal = C->getZExtValue();
3975 switch (ConstraintLetter) {
3976 // The I constraint applies only to simple ADD or SUB immediate operands:
3977 // i.e. 0 to 4095 with optional shift by 12
3978 // The J constraint applies only to ADD or SUB immediates that would be
3979 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3980 // instruction [or vice versa], in other words -1 to -4095 with optional
3981 // left shift by 12.
3983 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
3987 uint64_t NVal = -C->getSExtValue();
3988 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
3992 // The K and L constraints apply *only* to logical immediates, including
3993 // what used to be the MOVI alias for ORR (though the MOVI alias has now
3994 // been removed and MOV should be used). So these constraints have to
3995 // distinguish between bit patterns that are valid 32-bit or 64-bit
3996 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
3997 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4000 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4004 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4007 // The M and N constraints are a superset of K and L respectively, for use
4008 // with the MOV (immediate) alias. As well as the logical immediates they
4009 // also match 32 or 64-bit immediates that can be loaded either using a
4010 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4011 // (M) or 64-bit 0x1234000000000000 (N) etc.
4012 // As a note some of this code is liberally stolen from the asm parser.
4014 if (!isUInt<32>(CVal))
4016 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4018 if ((CVal & 0xFFFF) == CVal)
4020 if ((CVal & 0xFFFF0000ULL) == CVal)
4022 uint64_t NCVal = ~(uint32_t)CVal;
4023 if ((NCVal & 0xFFFFULL) == NCVal)
4025 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4030 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4032 if ((CVal & 0xFFFFULL) == CVal)
4034 if ((CVal & 0xFFFF0000ULL) == CVal)
4036 if ((CVal & 0xFFFF00000000ULL) == CVal)
4038 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4040 uint64_t NCVal = ~CVal;
4041 if ((NCVal & 0xFFFFULL) == NCVal)
4043 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4045 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4047 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4055 // All assembler immediates are 64-bit integers.
4056 Result = DAG.getTargetConstant(CVal, MVT::i64);
4060 if (Result.getNode()) {
4061 Ops.push_back(Result);
4065 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4068 //===----------------------------------------------------------------------===//
4069 // AArch64 Advanced SIMD Support
4070 //===----------------------------------------------------------------------===//
4072 /// WidenVector - Given a value in the V64 register class, produce the
4073 /// equivalent value in the V128 register class.
4074 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4075 EVT VT = V64Reg.getValueType();
4076 unsigned NarrowSize = VT.getVectorNumElements();
4077 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4078 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4081 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4082 V64Reg, DAG.getConstant(0, MVT::i32));
4085 /// getExtFactor - Determine the adjustment factor for the position when
4086 /// generating an "extract from vector registers" instruction.
4087 static unsigned getExtFactor(SDValue &V) {
4088 EVT EltType = V.getValueType().getVectorElementType();
4089 return EltType.getSizeInBits() / 8;
4092 /// NarrowVector - Given a value in the V128 register class, produce the
4093 /// equivalent value in the V64 register class.
4094 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4095 EVT VT = V128Reg.getValueType();
4096 unsigned WideSize = VT.getVectorNumElements();
4097 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4098 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4101 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4104 // Gather data to see if the operation can be modelled as a
4105 // shuffle in combination with VEXTs.
4106 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4107 SelectionDAG &DAG) const {
4109 EVT VT = Op.getValueType();
4110 unsigned NumElts = VT.getVectorNumElements();
4112 SmallVector<SDValue, 2> SourceVecs;
4113 SmallVector<unsigned, 2> MinElts;
4114 SmallVector<unsigned, 2> MaxElts;
4116 for (unsigned i = 0; i < NumElts; ++i) {
4117 SDValue V = Op.getOperand(i);
4118 if (V.getOpcode() == ISD::UNDEF)
4120 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4121 // A shuffle can only come from building a vector from various
4122 // elements of other vectors.
4126 // Record this extraction against the appropriate vector if possible...
4127 SDValue SourceVec = V.getOperand(0);
4128 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4129 bool FoundSource = false;
4130 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4131 if (SourceVecs[j] == SourceVec) {
4132 if (MinElts[j] > EltNo)
4134 if (MaxElts[j] < EltNo)
4141 // Or record a new source if not...
4143 SourceVecs.push_back(SourceVec);
4144 MinElts.push_back(EltNo);
4145 MaxElts.push_back(EltNo);
4149 // Currently only do something sane when at most two source vectors
4151 if (SourceVecs.size() > 2)
4154 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4155 int VEXTOffsets[2] = { 0, 0 };
4157 // This loop extracts the usage patterns of the source vectors
4158 // and prepares appropriate SDValues for a shuffle if possible.
4159 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4160 if (SourceVecs[i].getValueType() == VT) {
4161 // No VEXT necessary
4162 ShuffleSrcs[i] = SourceVecs[i];
4165 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4166 // We can pad out the smaller vector for free, so if it's part of a
4168 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, SourceVecs[i],
4169 DAG.getUNDEF(SourceVecs[i].getValueType()));
4173 // Don't attempt to extract subvectors from BUILD_VECTOR sources
4174 // that expand or trunc the original value.
4175 // TODO: We can try to bitcast and ANY_EXTEND the result but
4176 // we need to consider the cost of vector ANY_EXTEND, and the
4177 // legality of all the types.
4178 if (SourceVecs[i].getValueType().getVectorElementType() !=
4179 VT.getVectorElementType())
4182 // Since only 64-bit and 128-bit vectors are legal on ARM and
4183 // we've eliminated the other cases...
4184 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2 * NumElts &&
4185 "unexpected vector sizes in ReconstructShuffle");
4187 if (MaxElts[i] - MinElts[i] >= NumElts) {
4188 // Span too large for a VEXT to cope
4192 if (MinElts[i] >= NumElts) {
4193 // The extraction can just take the second half
4194 VEXTOffsets[i] = NumElts;
4196 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4197 DAG.getIntPtrConstant(NumElts));
4198 } else if (MaxElts[i] < NumElts) {
4199 // The extraction can just take the first half
4201 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4202 SourceVecs[i], DAG.getIntPtrConstant(0));
4204 // An actual VEXT is needed
4205 VEXTOffsets[i] = MinElts[i];
4206 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4207 SourceVecs[i], DAG.getIntPtrConstant(0));
4209 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4210 DAG.getIntPtrConstant(NumElts));
4211 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4212 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4213 DAG.getConstant(Imm, MVT::i32));
4217 SmallVector<int, 8> Mask;
4219 for (unsigned i = 0; i < NumElts; ++i) {
4220 SDValue Entry = Op.getOperand(i);
4221 if (Entry.getOpcode() == ISD::UNDEF) {
4226 SDValue ExtractVec = Entry.getOperand(0);
4228 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4229 if (ExtractVec == SourceVecs[0]) {
4230 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4232 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4236 // Final check before we try to produce nonsense...
4237 if (isShuffleMaskLegal(Mask, VT))
4238 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4244 // check if an EXT instruction can handle the shuffle mask when the
4245 // vector sources of the shuffle are the same.
4246 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4247 unsigned NumElts = VT.getVectorNumElements();
4249 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4255 // If this is a VEXT shuffle, the immediate value is the index of the first
4256 // element. The other shuffle indices must be the successive elements after
4258 unsigned ExpectedElt = Imm;
4259 for (unsigned i = 1; i < NumElts; ++i) {
4260 // Increment the expected index. If it wraps around, just follow it
4261 // back to index zero and keep going.
4263 if (ExpectedElt == NumElts)
4267 continue; // ignore UNDEF indices
4268 if (ExpectedElt != static_cast<unsigned>(M[i]))
4275 // check if an EXT instruction can handle the shuffle mask when the
4276 // vector sources of the shuffle are different.
4277 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4279 // Look for the first non-undef element.
4280 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4281 [](int Elt) {return Elt >= 0;});
4283 // Benefit form APInt to handle overflow when calculating expected element.
4284 unsigned NumElts = VT.getVectorNumElements();
4285 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4286 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4287 // The following shuffle indices must be the successive elements after the
4288 // first real element.
4289 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4290 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4291 if (FirstWrongElt != M.end())
4294 // The index of an EXT is the first element if it is not UNDEF.
4295 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4296 // value of the first element. E.g.
4297 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4298 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4299 // ExpectedElt is the last mask index plus 1.
4300 Imm = ExpectedElt.getZExtValue();
4302 // There are two difference cases requiring to reverse input vectors.
4303 // For example, for vector <4 x i32> we have the following cases,
4304 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4305 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4306 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4307 // to reverse two input vectors.
4316 /// isREVMask - Check if a vector shuffle corresponds to a REV
4317 /// instruction with the specified blocksize. (The order of the elements
4318 /// within each block of the vector is reversed.)
4319 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4320 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4321 "Only possible block sizes for REV are: 16, 32, 64");
4323 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4327 unsigned NumElts = VT.getVectorNumElements();
4328 unsigned BlockElts = M[0] + 1;
4329 // If the first shuffle index is UNDEF, be optimistic.
4331 BlockElts = BlockSize / EltSz;
4333 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4336 for (unsigned i = 0; i < NumElts; ++i) {
4338 continue; // ignore UNDEF indices
4339 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4346 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4347 unsigned NumElts = VT.getVectorNumElements();
4348 WhichResult = (M[0] == 0 ? 0 : 1);
4349 unsigned Idx = WhichResult * NumElts / 2;
4350 for (unsigned i = 0; i != NumElts; i += 2) {
4351 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4352 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4360 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4361 unsigned NumElts = VT.getVectorNumElements();
4362 WhichResult = (M[0] == 0 ? 0 : 1);
4363 for (unsigned i = 0; i != NumElts; ++i) {
4365 continue; // ignore UNDEF indices
4366 if ((unsigned)M[i] != 2 * i + WhichResult)
4373 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4374 unsigned NumElts = VT.getVectorNumElements();
4375 WhichResult = (M[0] == 0 ? 0 : 1);
4376 for (unsigned i = 0; i < NumElts; i += 2) {
4377 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4378 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4384 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4385 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4386 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4387 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4388 unsigned NumElts = VT.getVectorNumElements();
4389 WhichResult = (M[0] == 0 ? 0 : 1);
4390 unsigned Idx = WhichResult * NumElts / 2;
4391 for (unsigned i = 0; i != NumElts; i += 2) {
4392 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4393 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4401 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4402 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4403 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4404 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4405 unsigned Half = VT.getVectorNumElements() / 2;
4406 WhichResult = (M[0] == 0 ? 0 : 1);
4407 for (unsigned j = 0; j != 2; ++j) {
4408 unsigned Idx = WhichResult;
4409 for (unsigned i = 0; i != Half; ++i) {
4410 int MIdx = M[i + j * Half];
4411 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4420 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4421 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4422 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4423 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4424 unsigned NumElts = VT.getVectorNumElements();
4425 WhichResult = (M[0] == 0 ? 0 : 1);
4426 for (unsigned i = 0; i < NumElts; i += 2) {
4427 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4428 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4434 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4435 bool &DstIsLeft, int &Anomaly) {
4436 if (M.size() != static_cast<size_t>(NumInputElements))
4439 int NumLHSMatch = 0, NumRHSMatch = 0;
4440 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4442 for (int i = 0; i < NumInputElements; ++i) {
4452 LastLHSMismatch = i;
4454 if (M[i] == i + NumInputElements)
4457 LastRHSMismatch = i;
4460 if (NumLHSMatch == NumInputElements - 1) {
4462 Anomaly = LastLHSMismatch;
4464 } else if (NumRHSMatch == NumInputElements - 1) {
4466 Anomaly = LastRHSMismatch;
4473 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4474 if (VT.getSizeInBits() != 128)
4477 unsigned NumElts = VT.getVectorNumElements();
4479 for (int I = 0, E = NumElts / 2; I != E; I++) {
4484 int Offset = NumElts / 2;
4485 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4486 if (Mask[I] != I + SplitLHS * Offset)
4493 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4495 EVT VT = Op.getValueType();
4496 SDValue V0 = Op.getOperand(0);
4497 SDValue V1 = Op.getOperand(1);
4498 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4500 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4501 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4504 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4506 if (!isConcatMask(Mask, VT, SplitV0))
4509 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4510 VT.getVectorNumElements() / 2);
4512 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4513 DAG.getConstant(0, MVT::i64));
4515 if (V1.getValueType().getSizeInBits() == 128) {
4516 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4517 DAG.getConstant(0, MVT::i64));
4519 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4522 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4523 /// the specified operations to build the shuffle.
4524 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4525 SDValue RHS, SelectionDAG &DAG,
4527 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4528 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4529 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4532 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4541 OP_VUZPL, // VUZP, left result
4542 OP_VUZPR, // VUZP, right result
4543 OP_VZIPL, // VZIP, left result
4544 OP_VZIPR, // VZIP, right result
4545 OP_VTRNL, // VTRN, left result
4546 OP_VTRNR // VTRN, right result
4549 if (OpNum == OP_COPY) {
4550 if (LHSID == (1 * 9 + 2) * 9 + 3)
4552 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4556 SDValue OpLHS, OpRHS;
4557 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4558 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4559 EVT VT = OpLHS.getValueType();
4563 llvm_unreachable("Unknown shuffle opcode!");
4565 // VREV divides the vector in half and swaps within the half.
4566 if (VT.getVectorElementType() == MVT::i32 ||
4567 VT.getVectorElementType() == MVT::f32)
4568 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4569 // vrev <4 x i16> -> REV32
4570 if (VT.getVectorElementType() == MVT::i16)
4571 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4572 // vrev <4 x i8> -> REV16
4573 assert(VT.getVectorElementType() == MVT::i8);
4574 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4579 EVT EltTy = VT.getVectorElementType();
4581 if (EltTy == MVT::i8)
4582 Opcode = AArch64ISD::DUPLANE8;
4583 else if (EltTy == MVT::i16)
4584 Opcode = AArch64ISD::DUPLANE16;
4585 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4586 Opcode = AArch64ISD::DUPLANE32;
4587 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4588 Opcode = AArch64ISD::DUPLANE64;
4590 llvm_unreachable("Invalid vector element type?");
4592 if (VT.getSizeInBits() == 64)
4593 OpLHS = WidenVector(OpLHS, DAG);
4594 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4595 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4600 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4601 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4602 DAG.getConstant(Imm, MVT::i32));
4605 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4608 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4611 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4614 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4617 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4620 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4625 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4626 SelectionDAG &DAG) {
4627 // Check to see if we can use the TBL instruction.
4628 SDValue V1 = Op.getOperand(0);
4629 SDValue V2 = Op.getOperand(1);
4632 EVT EltVT = Op.getValueType().getVectorElementType();
4633 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4635 SmallVector<SDValue, 8> TBLMask;
4636 for (int Val : ShuffleMask) {
4637 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4638 unsigned Offset = Byte + Val * BytesPerElt;
4639 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4643 MVT IndexVT = MVT::v8i8;
4644 unsigned IndexLen = 8;
4645 if (Op.getValueType().getSizeInBits() == 128) {
4646 IndexVT = MVT::v16i8;
4650 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4651 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4654 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4656 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4657 Shuffle = DAG.getNode(
4658 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4659 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4660 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4661 makeArrayRef(TBLMask.data(), IndexLen)));
4663 if (IndexLen == 8) {
4664 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4665 Shuffle = DAG.getNode(
4666 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4667 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4668 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4669 makeArrayRef(TBLMask.data(), IndexLen)));
4671 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4672 // cannot currently represent the register constraints on the input
4674 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4675 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4676 // &TBLMask[0], IndexLen));
4677 Shuffle = DAG.getNode(
4678 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4679 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4680 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4681 makeArrayRef(TBLMask.data(), IndexLen)));
4684 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4687 static unsigned getDUPLANEOp(EVT EltType) {
4688 if (EltType == MVT::i8)
4689 return AArch64ISD::DUPLANE8;
4690 if (EltType == MVT::i16)
4691 return AArch64ISD::DUPLANE16;
4692 if (EltType == MVT::i32 || EltType == MVT::f32)
4693 return AArch64ISD::DUPLANE32;
4694 if (EltType == MVT::i64 || EltType == MVT::f64)
4695 return AArch64ISD::DUPLANE64;
4697 llvm_unreachable("Invalid vector element type?");
4700 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4701 SelectionDAG &DAG) const {
4703 EVT VT = Op.getValueType();
4705 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4707 // Convert shuffles that are directly supported on NEON to target-specific
4708 // DAG nodes, instead of keeping them as shuffles and matching them again
4709 // during code selection. This is more efficient and avoids the possibility
4710 // of inconsistencies between legalization and selection.
4711 ArrayRef<int> ShuffleMask = SVN->getMask();
4713 SDValue V1 = Op.getOperand(0);
4714 SDValue V2 = Op.getOperand(1);
4716 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4717 V1.getValueType().getSimpleVT())) {
4718 int Lane = SVN->getSplatIndex();
4719 // If this is undef splat, generate it via "just" vdup, if possible.
4723 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4724 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4726 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4727 // constant. If so, we can just reference the lane's definition directly.
4728 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4729 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4730 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4732 // Otherwise, duplicate from the lane of the input vector.
4733 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4735 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4736 // to make a vector of the same size as this SHUFFLE. We can ignore the
4737 // extract entirely, and canonicalise the concat using WidenVector.
4738 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4739 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4740 V1 = V1.getOperand(0);
4741 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4742 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4743 Lane -= Idx * VT.getVectorNumElements() / 2;
4744 V1 = WidenVector(V1.getOperand(Idx), DAG);
4745 } else if (VT.getSizeInBits() == 64)
4746 V1 = WidenVector(V1, DAG);
4748 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4751 if (isREVMask(ShuffleMask, VT, 64))
4752 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4753 if (isREVMask(ShuffleMask, VT, 32))
4754 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4755 if (isREVMask(ShuffleMask, VT, 16))
4756 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4758 bool ReverseEXT = false;
4760 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4763 Imm *= getExtFactor(V1);
4764 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4765 DAG.getConstant(Imm, MVT::i32));
4766 } else if (V2->getOpcode() == ISD::UNDEF &&
4767 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4768 Imm *= getExtFactor(V1);
4769 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4770 DAG.getConstant(Imm, MVT::i32));
4773 unsigned WhichResult;
4774 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4775 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4776 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4778 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4779 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4780 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4782 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4783 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4784 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4787 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4788 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4789 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4791 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4792 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4793 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4795 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4796 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4797 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4800 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4801 if (Concat.getNode())
4806 int NumInputElements = V1.getValueType().getVectorNumElements();
4807 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4808 SDValue DstVec = DstIsLeft ? V1 : V2;
4809 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4811 SDValue SrcVec = V1;
4812 int SrcLane = ShuffleMask[Anomaly];
4813 if (SrcLane >= NumInputElements) {
4815 SrcLane -= VT.getVectorNumElements();
4817 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4819 EVT ScalarVT = VT.getVectorElementType();
4820 if (ScalarVT.getSizeInBits() < 32)
4821 ScalarVT = MVT::i32;
4824 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4825 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4829 // If the shuffle is not directly supported and it has 4 elements, use
4830 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4831 unsigned NumElts = VT.getVectorNumElements();
4833 unsigned PFIndexes[4];
4834 for (unsigned i = 0; i != 4; ++i) {
4835 if (ShuffleMask[i] < 0)
4838 PFIndexes[i] = ShuffleMask[i];
4841 // Compute the index in the perfect shuffle table.
4842 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4843 PFIndexes[2] * 9 + PFIndexes[3];
4844 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4845 unsigned Cost = (PFEntry >> 30);
4848 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4851 return GenerateTBL(Op, ShuffleMask, DAG);
4854 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4856 EVT VT = BVN->getValueType(0);
4857 APInt SplatBits, SplatUndef;
4858 unsigned SplatBitSize;
4860 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4861 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4863 for (unsigned i = 0; i < NumSplats; ++i) {
4864 CnstBits <<= SplatBitSize;
4865 UndefBits <<= SplatBitSize;
4866 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4867 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4876 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4877 SelectionDAG &DAG) const {
4878 BuildVectorSDNode *BVN =
4879 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4880 SDValue LHS = Op.getOperand(0);
4882 EVT VT = Op.getValueType();
4887 APInt CnstBits(VT.getSizeInBits(), 0);
4888 APInt UndefBits(VT.getSizeInBits(), 0);
4889 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4890 // We only have BIC vector immediate instruction, which is and-not.
4891 CnstBits = ~CnstBits;
4893 // We make use of a little bit of goto ickiness in order to avoid having to
4894 // duplicate the immediate matching logic for the undef toggled case.
4895 bool SecondTry = false;
4898 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4899 CnstBits = CnstBits.zextOrTrunc(64);
4900 uint64_t CnstVal = CnstBits.getZExtValue();
4902 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4903 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4904 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4905 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4906 DAG.getConstant(CnstVal, MVT::i32),
4907 DAG.getConstant(0, MVT::i32));
4908 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4911 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4912 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4913 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4914 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4915 DAG.getConstant(CnstVal, MVT::i32),
4916 DAG.getConstant(8, MVT::i32));
4917 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4920 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4921 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4922 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4923 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4924 DAG.getConstant(CnstVal, MVT::i32),
4925 DAG.getConstant(16, MVT::i32));
4926 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4929 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4930 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4931 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4932 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4933 DAG.getConstant(CnstVal, MVT::i32),
4934 DAG.getConstant(24, MVT::i32));
4935 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4938 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4939 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4940 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4941 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4942 DAG.getConstant(CnstVal, MVT::i32),
4943 DAG.getConstant(0, MVT::i32));
4944 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4947 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4948 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4949 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4950 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4951 DAG.getConstant(CnstVal, MVT::i32),
4952 DAG.getConstant(8, MVT::i32));
4953 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4960 CnstBits = ~UndefBits;
4964 // We can always fall back to a non-immediate AND.
4969 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4970 // consists of only the same constant int value, returned in reference arg
4972 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4973 uint64_t &ConstVal) {
4974 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4977 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4980 EVT VT = Bvec->getValueType(0);
4981 unsigned NumElts = VT.getVectorNumElements();
4982 for (unsigned i = 1; i < NumElts; ++i)
4983 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
4985 ConstVal = FirstElt->getZExtValue();
4989 static unsigned getIntrinsicID(const SDNode *N) {
4990 unsigned Opcode = N->getOpcode();
4993 return Intrinsic::not_intrinsic;
4994 case ISD::INTRINSIC_WO_CHAIN: {
4995 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4996 if (IID < Intrinsic::num_intrinsics)
4998 return Intrinsic::not_intrinsic;
5003 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5004 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5005 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5006 // Also, logical shift right -> sri, with the same structure.
5007 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5008 EVT VT = N->getValueType(0);
5015 // Is the first op an AND?
5016 const SDValue And = N->getOperand(0);
5017 if (And.getOpcode() != ISD::AND)
5020 // Is the second op an shl or lshr?
5021 SDValue Shift = N->getOperand(1);
5022 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5023 // or AArch64ISD::VLSHR vector, #shift
5024 unsigned ShiftOpc = Shift.getOpcode();
5025 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5027 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5029 // Is the shift amount constant?
5030 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5034 // Is the and mask vector all constant?
5036 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5039 // Is C1 == ~C2, taking into account how much one can shift elements of a
5041 uint64_t C2 = C2node->getZExtValue();
5042 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5043 if (C2 > ElemSizeInBits)
5045 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5046 if ((C1 & ElemMask) != (~C2 & ElemMask))
5049 SDValue X = And.getOperand(0);
5050 SDValue Y = Shift.getOperand(0);
5053 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5055 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5056 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5058 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5059 DEBUG(N->dump(&DAG));
5060 DEBUG(dbgs() << "into: \n");
5061 DEBUG(ResultSLI->dump(&DAG));
5067 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5068 SelectionDAG &DAG) const {
5069 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5070 if (EnableAArch64SlrGeneration) {
5071 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5076 BuildVectorSDNode *BVN =
5077 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5078 SDValue LHS = Op.getOperand(1);
5080 EVT VT = Op.getValueType();
5082 // OR commutes, so try swapping the operands.
5084 LHS = Op.getOperand(0);
5085 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5090 APInt CnstBits(VT.getSizeInBits(), 0);
5091 APInt UndefBits(VT.getSizeInBits(), 0);
5092 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5093 // We make use of a little bit of goto ickiness in order to avoid having to
5094 // duplicate the immediate matching logic for the undef toggled case.
5095 bool SecondTry = false;
5098 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5099 CnstBits = CnstBits.zextOrTrunc(64);
5100 uint64_t CnstVal = CnstBits.getZExtValue();
5102 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5103 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5104 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5105 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5106 DAG.getConstant(CnstVal, MVT::i32),
5107 DAG.getConstant(0, MVT::i32));
5108 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5111 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5112 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5113 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5114 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5115 DAG.getConstant(CnstVal, MVT::i32),
5116 DAG.getConstant(8, MVT::i32));
5117 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5120 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5121 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5122 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5123 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5124 DAG.getConstant(CnstVal, MVT::i32),
5125 DAG.getConstant(16, MVT::i32));
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5129 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5130 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5131 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5132 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5133 DAG.getConstant(CnstVal, MVT::i32),
5134 DAG.getConstant(24, MVT::i32));
5135 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5138 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5139 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5140 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5141 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5142 DAG.getConstant(CnstVal, MVT::i32),
5143 DAG.getConstant(0, MVT::i32));
5144 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5147 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5148 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5149 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5150 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5151 DAG.getConstant(CnstVal, MVT::i32),
5152 DAG.getConstant(8, MVT::i32));
5153 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5160 CnstBits = UndefBits;
5164 // We can always fall back to a non-immediate OR.
5169 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5170 SelectionDAG &DAG) const {
5171 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5173 EVT VT = Op.getValueType();
5175 APInt CnstBits(VT.getSizeInBits(), 0);
5176 APInt UndefBits(VT.getSizeInBits(), 0);
5177 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5178 // We make use of a little bit of goto ickiness in order to avoid having to
5179 // duplicate the immediate matching logic for the undef toggled case.
5180 bool SecondTry = false;
5183 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5184 CnstBits = CnstBits.zextOrTrunc(64);
5185 uint64_t CnstVal = CnstBits.getZExtValue();
5187 // Certain magic vector constants (used to express things like NOT
5188 // and NEG) are passed through unmodified. This allows codegen patterns
5189 // for these operations to match. Special-purpose patterns will lower
5190 // these immediates to MOVIs if it proves necessary.
5191 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5194 // The many faces of MOVI...
5195 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5196 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5197 if (VT.getSizeInBits() == 128) {
5198 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5199 DAG.getConstant(CnstVal, MVT::i32));
5200 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5203 // Support the V64 version via subregister insertion.
5204 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5205 DAG.getConstant(CnstVal, MVT::i32));
5206 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5209 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5210 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5211 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5212 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5213 DAG.getConstant(CnstVal, MVT::i32),
5214 DAG.getConstant(0, MVT::i32));
5215 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5218 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5219 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5220 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5221 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5222 DAG.getConstant(CnstVal, MVT::i32),
5223 DAG.getConstant(8, MVT::i32));
5224 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5227 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5228 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5229 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5230 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5231 DAG.getConstant(CnstVal, MVT::i32),
5232 DAG.getConstant(16, MVT::i32));
5233 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5236 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5237 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5238 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5239 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5240 DAG.getConstant(CnstVal, MVT::i32),
5241 DAG.getConstant(24, MVT::i32));
5242 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5245 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5246 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5247 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5248 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5249 DAG.getConstant(CnstVal, MVT::i32),
5250 DAG.getConstant(0, MVT::i32));
5251 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5254 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5255 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5256 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5257 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5258 DAG.getConstant(CnstVal, MVT::i32),
5259 DAG.getConstant(8, MVT::i32));
5260 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5263 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5264 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5265 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5266 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5267 DAG.getConstant(CnstVal, MVT::i32),
5268 DAG.getConstant(264, MVT::i32));
5269 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5272 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5273 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5274 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5275 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5276 DAG.getConstant(CnstVal, MVT::i32),
5277 DAG.getConstant(272, MVT::i32));
5278 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5281 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5282 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5283 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5284 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5285 DAG.getConstant(CnstVal, MVT::i32));
5286 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5289 // The few faces of FMOV...
5290 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5291 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5292 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5293 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5294 DAG.getConstant(CnstVal, MVT::i32));
5295 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5298 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5299 VT.getSizeInBits() == 128) {
5300 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5301 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5302 DAG.getConstant(CnstVal, MVT::i32));
5303 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5306 // The many faces of MVNI...
5308 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5309 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5310 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5311 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5312 DAG.getConstant(CnstVal, MVT::i32),
5313 DAG.getConstant(0, MVT::i32));
5314 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5317 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5318 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5319 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5320 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5321 DAG.getConstant(CnstVal, MVT::i32),
5322 DAG.getConstant(8, MVT::i32));
5323 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5326 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5327 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5328 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5329 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5330 DAG.getConstant(CnstVal, MVT::i32),
5331 DAG.getConstant(16, MVT::i32));
5332 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5335 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5336 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5337 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5338 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5339 DAG.getConstant(CnstVal, MVT::i32),
5340 DAG.getConstant(24, MVT::i32));
5341 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5344 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5345 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5346 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5347 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5348 DAG.getConstant(CnstVal, MVT::i32),
5349 DAG.getConstant(0, MVT::i32));
5350 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5353 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5354 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5355 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5356 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5357 DAG.getConstant(CnstVal, MVT::i32),
5358 DAG.getConstant(8, MVT::i32));
5359 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5362 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5363 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5364 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5365 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5366 DAG.getConstant(CnstVal, MVT::i32),
5367 DAG.getConstant(264, MVT::i32));
5368 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5371 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5372 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5373 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5374 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5375 DAG.getConstant(CnstVal, MVT::i32),
5376 DAG.getConstant(272, MVT::i32));
5377 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5384 CnstBits = UndefBits;
5389 // Scan through the operands to find some interesting properties we can
5391 // 1) If only one value is used, we can use a DUP, or
5392 // 2) if only the low element is not undef, we can just insert that, or
5393 // 3) if only one constant value is used (w/ some non-constant lanes),
5394 // we can splat the constant value into the whole vector then fill
5395 // in the non-constant lanes.
5396 // 4) FIXME: If different constant values are used, but we can intelligently
5397 // select the values we'll be overwriting for the non-constant
5398 // lanes such that we can directly materialize the vector
5399 // some other way (MOVI, e.g.), we can be sneaky.
5400 unsigned NumElts = VT.getVectorNumElements();
5401 bool isOnlyLowElement = true;
5402 bool usesOnlyOneValue = true;
5403 bool usesOnlyOneConstantValue = true;
5404 bool isConstant = true;
5405 unsigned NumConstantLanes = 0;
5407 SDValue ConstantValue;
5408 for (unsigned i = 0; i < NumElts; ++i) {
5409 SDValue V = Op.getOperand(i);
5410 if (V.getOpcode() == ISD::UNDEF)
5413 isOnlyLowElement = false;
5414 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5417 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5419 if (!ConstantValue.getNode())
5421 else if (ConstantValue != V)
5422 usesOnlyOneConstantValue = false;
5425 if (!Value.getNode())
5427 else if (V != Value)
5428 usesOnlyOneValue = false;
5431 if (!Value.getNode())
5432 return DAG.getUNDEF(VT);
5434 if (isOnlyLowElement)
5435 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5437 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5438 // i32 and try again.
5439 if (usesOnlyOneValue) {
5441 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5442 Value.getValueType() != VT)
5443 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5445 // This is actually a DUPLANExx operation, which keeps everything vectory.
5447 // DUPLANE works on 128-bit vectors, widen it if necessary.
5448 SDValue Lane = Value.getOperand(1);
5449 Value = Value.getOperand(0);
5450 if (Value.getValueType().getSizeInBits() == 64)
5451 Value = WidenVector(Value, DAG);
5453 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5454 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5457 if (VT.getVectorElementType().isFloatingPoint()) {
5458 SmallVector<SDValue, 8> Ops;
5460 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5461 for (unsigned i = 0; i < NumElts; ++i)
5462 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5463 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5464 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5465 Val = LowerBUILD_VECTOR(Val, DAG);
5467 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5471 // If there was only one constant value used and for more than one lane,
5472 // start by splatting that value, then replace the non-constant lanes. This
5473 // is better than the default, which will perform a separate initialization
5475 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5476 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5477 // Now insert the non-constant lanes.
5478 for (unsigned i = 0; i < NumElts; ++i) {
5479 SDValue V = Op.getOperand(i);
5480 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5481 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5482 // Note that type legalization likely mucked about with the VT of the
5483 // source operand, so we may have to convert it here before inserting.
5484 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5490 // If all elements are constants and the case above didn't get hit, fall back
5491 // to the default expansion, which will generate a load from the constant
5496 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5498 SDValue shuffle = ReconstructShuffle(Op, DAG);
5499 if (shuffle != SDValue())
5503 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5504 // know the default expansion would otherwise fall back on something even
5505 // worse. For a vector with one or two non-undef values, that's
5506 // scalar_to_vector for the elements followed by a shuffle (provided the
5507 // shuffle is valid for the target) and materialization element by element
5508 // on the stack followed by a load for everything else.
5509 if (!isConstant && !usesOnlyOneValue) {
5510 SDValue Vec = DAG.getUNDEF(VT);
5511 SDValue Op0 = Op.getOperand(0);
5512 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5514 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5515 // a) Avoid a RMW dependency on the full vector register, and
5516 // b) Allow the register coalescer to fold away the copy if the
5517 // value is already in an S or D register.
5518 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5519 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5521 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5522 DAG.getTargetConstant(SubIdx, MVT::i32));
5523 Vec = SDValue(N, 0);
5526 for (; i < NumElts; ++i) {
5527 SDValue V = Op.getOperand(i);
5528 if (V.getOpcode() == ISD::UNDEF)
5530 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5531 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5536 // Just use the default expansion. We failed to find a better alternative.
5540 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5541 SelectionDAG &DAG) const {
5542 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5544 // Check for non-constant lane.
5545 if (!isa<ConstantSDNode>(Op.getOperand(2)))
5548 EVT VT = Op.getOperand(0).getValueType();
5550 // Insertion/extraction are legal for V128 types.
5551 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5552 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5555 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5556 VT != MVT::v1i64 && VT != MVT::v2f32)
5559 // For V64 types, we perform insertion by expanding the value
5560 // to a V128 type and perform the insertion on that.
5562 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5563 EVT WideTy = WideVec.getValueType();
5565 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5566 Op.getOperand(1), Op.getOperand(2));
5567 // Re-narrow the resultant vector.
5568 return NarrowVector(Node, DAG);
5572 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5573 SelectionDAG &DAG) const {
5574 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5576 // Check for non-constant lane.
5577 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5580 EVT VT = Op.getOperand(0).getValueType();
5582 // Insertion/extraction are legal for V128 types.
5583 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5584 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5587 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5588 VT != MVT::v1i64 && VT != MVT::v2f32)
5591 // For V64 types, we perform extraction by expanding the value
5592 // to a V128 type and perform the extraction on that.
5594 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5595 EVT WideTy = WideVec.getValueType();
5597 EVT ExtrTy = WideTy.getVectorElementType();
5598 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5601 // For extractions, we just return the result directly.
5602 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5606 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5607 SelectionDAG &DAG) const {
5608 EVT VT = Op.getOperand(0).getValueType();
5614 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5617 unsigned Val = Cst->getZExtValue();
5619 unsigned Size = Op.getValueType().getSizeInBits();
5623 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5626 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5629 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5632 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5635 llvm_unreachable("Unexpected vector type in extract_subvector!");
5638 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5640 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5646 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5648 if (VT.getVectorNumElements() == 4 &&
5649 (VT.is128BitVector() || VT.is64BitVector())) {
5650 unsigned PFIndexes[4];
5651 for (unsigned i = 0; i != 4; ++i) {
5655 PFIndexes[i] = M[i];
5658 // Compute the index in the perfect shuffle table.
5659 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5660 PFIndexes[2] * 9 + PFIndexes[3];
5661 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5662 unsigned Cost = (PFEntry >> 30);
5670 unsigned DummyUnsigned;
5672 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5673 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5674 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5675 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5676 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5677 isZIPMask(M, VT, DummyUnsigned) ||
5678 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5679 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5680 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5681 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5682 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5685 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5686 /// operand of a vector shift operation, where all the elements of the
5687 /// build_vector must have the same constant integer value.
5688 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5689 // Ignore bit_converts.
5690 while (Op.getOpcode() == ISD::BITCAST)
5691 Op = Op.getOperand(0);
5692 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5693 APInt SplatBits, SplatUndef;
5694 unsigned SplatBitSize;
5696 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5697 HasAnyUndefs, ElementBits) ||
5698 SplatBitSize > ElementBits)
5700 Cnt = SplatBits.getSExtValue();
5704 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5705 /// operand of a vector shift left operation. That value must be in the range:
5706 /// 0 <= Value < ElementBits for a left shift; or
5707 /// 0 <= Value <= ElementBits for a long left shift.
5708 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5709 assert(VT.isVector() && "vector shift count is not a vector type");
5710 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5711 if (!getVShiftImm(Op, ElementBits, Cnt))
5713 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5716 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5717 /// operand of a vector shift right operation. For a shift opcode, the value
5718 /// is positive, but for an intrinsic the value count must be negative. The
5719 /// absolute value must be in the range:
5720 /// 1 <= |Value| <= ElementBits for a right shift; or
5721 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5722 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5724 assert(VT.isVector() && "vector shift count is not a vector type");
5725 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5726 if (!getVShiftImm(Op, ElementBits, Cnt))
5730 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5733 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5734 SelectionDAG &DAG) const {
5735 EVT VT = Op.getValueType();
5739 if (!Op.getOperand(1).getValueType().isVector())
5741 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5743 switch (Op.getOpcode()) {
5745 llvm_unreachable("unexpected shift opcode");
5748 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5749 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5750 DAG.getConstant(Cnt, MVT::i32));
5751 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5752 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5753 Op.getOperand(0), Op.getOperand(1));
5756 // Right shift immediate
5757 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5760 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5761 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5762 DAG.getConstant(Cnt, MVT::i32));
5765 // Right shift register. Note, there is not a shift right register
5766 // instruction, but the shift left register instruction takes a signed
5767 // value, where negative numbers specify a right shift.
5768 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5769 : Intrinsic::aarch64_neon_ushl;
5770 // negate the shift amount
5771 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5772 SDValue NegShiftLeft =
5773 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5774 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5775 return NegShiftLeft;
5781 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5782 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5783 SDLoc dl, SelectionDAG &DAG) {
5784 EVT SrcVT = LHS.getValueType();
5786 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5787 APInt CnstBits(VT.getSizeInBits(), 0);
5788 APInt UndefBits(VT.getSizeInBits(), 0);
5789 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5790 bool IsZero = IsCnst && (CnstBits == 0);
5792 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5796 case AArch64CC::NE: {
5799 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5801 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5802 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5806 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5807 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5810 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5811 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5814 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5815 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5818 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5819 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5823 // If we ignore NaNs then we can use to the MI implementation.
5827 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5828 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5835 case AArch64CC::NE: {
5838 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5840 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5841 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5845 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5846 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5849 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5850 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5853 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5854 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5857 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5858 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5860 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5862 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5865 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5866 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5868 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5870 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5874 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5875 SelectionDAG &DAG) const {
5876 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5877 SDValue LHS = Op.getOperand(0);
5878 SDValue RHS = Op.getOperand(1);
5881 if (LHS.getValueType().getVectorElementType().isInteger()) {
5882 assert(LHS.getValueType() == RHS.getValueType());
5883 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5884 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5888 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5889 LHS.getValueType().getVectorElementType() == MVT::f64);
5891 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5892 // clean. Some of them require two branches to implement.
5893 AArch64CC::CondCode CC1, CC2;
5895 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5897 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5899 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5903 if (CC2 != AArch64CC::AL) {
5905 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5906 if (!Cmp2.getNode())
5909 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5913 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5918 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5919 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5920 /// specified in the intrinsic calls.
5921 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5923 unsigned Intrinsic) const {
5924 switch (Intrinsic) {
5925 case Intrinsic::aarch64_neon_ld2:
5926 case Intrinsic::aarch64_neon_ld3:
5927 case Intrinsic::aarch64_neon_ld4:
5928 case Intrinsic::aarch64_neon_ld1x2:
5929 case Intrinsic::aarch64_neon_ld1x3:
5930 case Intrinsic::aarch64_neon_ld1x4:
5931 case Intrinsic::aarch64_neon_ld2lane:
5932 case Intrinsic::aarch64_neon_ld3lane:
5933 case Intrinsic::aarch64_neon_ld4lane:
5934 case Intrinsic::aarch64_neon_ld2r:
5935 case Intrinsic::aarch64_neon_ld3r:
5936 case Intrinsic::aarch64_neon_ld4r: {
5937 Info.opc = ISD::INTRINSIC_W_CHAIN;
5938 // Conservatively set memVT to the entire set of vectors loaded.
5939 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5940 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5941 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5944 Info.vol = false; // volatile loads with NEON intrinsics not supported
5945 Info.readMem = true;
5946 Info.writeMem = false;
5949 case Intrinsic::aarch64_neon_st2:
5950 case Intrinsic::aarch64_neon_st3:
5951 case Intrinsic::aarch64_neon_st4:
5952 case Intrinsic::aarch64_neon_st1x2:
5953 case Intrinsic::aarch64_neon_st1x3:
5954 case Intrinsic::aarch64_neon_st1x4:
5955 case Intrinsic::aarch64_neon_st2lane:
5956 case Intrinsic::aarch64_neon_st3lane:
5957 case Intrinsic::aarch64_neon_st4lane: {
5958 Info.opc = ISD::INTRINSIC_VOID;
5959 // Conservatively set memVT to the entire set of vectors stored.
5960 unsigned NumElts = 0;
5961 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5962 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5963 if (!ArgTy->isVectorTy())
5965 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5967 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5968 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5971 Info.vol = false; // volatile stores with NEON intrinsics not supported
5972 Info.readMem = false;
5973 Info.writeMem = true;
5976 case Intrinsic::aarch64_ldaxr:
5977 case Intrinsic::aarch64_ldxr: {
5978 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
5979 Info.opc = ISD::INTRINSIC_W_CHAIN;
5980 Info.memVT = MVT::getVT(PtrTy->getElementType());
5981 Info.ptrVal = I.getArgOperand(0);
5983 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
5985 Info.readMem = true;
5986 Info.writeMem = false;
5989 case Intrinsic::aarch64_stlxr:
5990 case Intrinsic::aarch64_stxr: {
5991 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
5992 Info.opc = ISD::INTRINSIC_W_CHAIN;
5993 Info.memVT = MVT::getVT(PtrTy->getElementType());
5994 Info.ptrVal = I.getArgOperand(1);
5996 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
5998 Info.readMem = false;
5999 Info.writeMem = true;
6002 case Intrinsic::aarch64_ldaxp:
6003 case Intrinsic::aarch64_ldxp: {
6004 Info.opc = ISD::INTRINSIC_W_CHAIN;
6005 Info.memVT = MVT::i128;
6006 Info.ptrVal = I.getArgOperand(0);
6010 Info.readMem = true;
6011 Info.writeMem = false;
6014 case Intrinsic::aarch64_stlxp:
6015 case Intrinsic::aarch64_stxp: {
6016 Info.opc = ISD::INTRINSIC_W_CHAIN;
6017 Info.memVT = MVT::i128;
6018 Info.ptrVal = I.getArgOperand(2);
6022 Info.readMem = false;
6023 Info.writeMem = true;
6033 // Truncations from 64-bit GPR to 32-bit GPR is free.
6034 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6035 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6037 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6038 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6039 if (NumBits1 <= NumBits2)
6043 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6044 if (!VT1.isInteger() || !VT2.isInteger())
6046 unsigned NumBits1 = VT1.getSizeInBits();
6047 unsigned NumBits2 = VT2.getSizeInBits();
6048 if (NumBits1 <= NumBits2)
6053 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6055 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6056 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6058 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6059 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6060 if (NumBits1 == 32 && NumBits2 == 64)
6064 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6065 if (!VT1.isInteger() || !VT2.isInteger())
6067 unsigned NumBits1 = VT1.getSizeInBits();
6068 unsigned NumBits2 = VT2.getSizeInBits();
6069 if (NumBits1 == 32 && NumBits2 == 64)
6074 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6075 EVT VT1 = Val.getValueType();
6076 if (isZExtFree(VT1, VT2)) {
6080 if (Val.getOpcode() != ISD::LOAD)
6083 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6084 return (VT1.isSimple() && VT1.isInteger() && VT2.isSimple() &&
6085 VT2.isInteger() && VT1.getSizeInBits() <= 32);
6088 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6089 unsigned &RequiredAligment) const {
6090 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6092 // Cyclone supports unaligned accesses.
6093 RequiredAligment = 0;
6094 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6095 return NumBits == 32 || NumBits == 64;
6098 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6099 unsigned &RequiredAligment) const {
6100 if (!LoadedType.isSimple() ||
6101 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6103 // Cyclone supports unaligned accesses.
6104 RequiredAligment = 0;
6105 unsigned NumBits = LoadedType.getSizeInBits();
6106 return NumBits == 32 || NumBits == 64;
6109 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6110 unsigned AlignCheck) {
6111 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6112 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6115 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6116 unsigned SrcAlign, bool IsMemset,
6119 MachineFunction &MF) const {
6120 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6121 // instruction to materialize the v2i64 zero and one store (with restrictive
6122 // addressing mode). Just do two i64 store of zero-registers.
6124 const Function *F = MF.getFunction();
6125 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6126 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6127 Attribute::NoImplicitFloat) &&
6128 (memOpAlign(SrcAlign, DstAlign, 16) ||
6129 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6132 return Size >= 8 ? MVT::i64 : MVT::i32;
6135 // 12-bit optionally shifted immediates are legal for adds.
6136 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6137 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6142 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6143 // immediates is the same as for an add or a sub.
6144 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6147 return isLegalAddImmediate(Immed);
6150 /// isLegalAddressingMode - Return true if the addressing mode represented
6151 /// by AM is legal for this target, for a load/store of the specified type.
6152 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6154 // AArch64 has five basic addressing modes:
6156 // reg + 9-bit signed offset
6157 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6159 // reg + SIZE_IN_BYTES * reg
6161 // No global is ever allowed as a base.
6165 // No reg+reg+imm addressing.
6166 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6169 // check reg + imm case:
6170 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6171 uint64_t NumBytes = 0;
6172 if (Ty->isSized()) {
6173 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6174 NumBytes = NumBits / 8;
6175 if (!isPowerOf2_64(NumBits))
6180 int64_t Offset = AM.BaseOffs;
6182 // 9-bit signed offset
6183 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6186 // 12-bit unsigned offset
6187 unsigned shift = Log2_64(NumBytes);
6188 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6189 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6190 (Offset >> shift) << shift == Offset)
6195 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6197 if (!AM.Scale || AM.Scale == 1 ||
6198 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6203 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6205 // Scaling factors are not free at all.
6206 // Operands | Rt Latency
6207 // -------------------------------------------
6209 // -------------------------------------------
6210 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6211 // Rt, [Xn, Wm, <extend> #imm] |
6212 if (isLegalAddressingMode(AM, Ty))
6213 // Scale represents reg2 * scale, thus account for 1 if
6214 // it is not equal to 0 or 1.
6215 return AM.Scale != 0 && AM.Scale != 1;
6219 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6220 VT = VT.getScalarType();
6225 switch (VT.getSimpleVT().SimpleTy) {
6237 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6238 // LR is a callee-save register, but we must treat it as clobbered by any call
6239 // site. Hence we include LR in the scratch registers, which are in turn added
6240 // as implicit-defs for stackmaps and patchpoints.
6241 static const MCPhysReg ScratchRegs[] = {
6242 AArch64::X16, AArch64::X17, AArch64::LR, 0
6248 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6249 EVT VT = N->getValueType(0);
6250 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6251 // it with shift to let it be lowered to UBFX.
6252 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6253 isa<ConstantSDNode>(N->getOperand(1))) {
6254 uint64_t TruncMask = N->getConstantOperandVal(1);
6255 if (isMask_64(TruncMask) &&
6256 N->getOperand(0).getOpcode() == ISD::SRL &&
6257 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6263 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6265 assert(Ty->isIntegerTy());
6267 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6271 int64_t Val = Imm.getSExtValue();
6272 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6275 if ((int64_t)Val < 0)
6278 Val &= (1LL << 32) - 1;
6280 unsigned LZ = countLeadingZeros((uint64_t)Val);
6281 unsigned Shift = (63 - LZ) / 16;
6282 // MOVZ is free so return true for one or fewer MOVK.
6283 return (Shift < 3) ? true : false;
6286 // Generate SUBS and CSEL for integer abs.
6287 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6288 EVT VT = N->getValueType(0);
6290 SDValue N0 = N->getOperand(0);
6291 SDValue N1 = N->getOperand(1);
6294 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6295 // and change it to SUB and CSEL.
6296 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6297 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6298 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6299 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6300 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6301 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6303 // Generate SUBS & CSEL.
6305 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6306 N0.getOperand(0), DAG.getConstant(0, VT));
6307 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6308 DAG.getConstant(AArch64CC::PL, MVT::i32),
6309 SDValue(Cmp.getNode(), 1));
6314 // performXorCombine - Attempts to handle integer ABS.
6315 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6316 TargetLowering::DAGCombinerInfo &DCI,
6317 const AArch64Subtarget *Subtarget) {
6318 if (DCI.isBeforeLegalizeOps())
6321 return performIntegerAbsCombine(N, DAG);
6324 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6325 TargetLowering::DAGCombinerInfo &DCI,
6326 const AArch64Subtarget *Subtarget) {
6327 if (DCI.isBeforeLegalizeOps())
6330 // Multiplication of a power of two plus/minus one can be done more
6331 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6332 // future CPUs have a cheaper MADD instruction, this may need to be
6333 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6334 // 64-bit is 5 cycles, so this is always a win.
6335 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6336 APInt Value = C->getAPIntValue();
6337 EVT VT = N->getValueType(0);
6338 APInt VP1 = Value + 1;
6339 if (VP1.isPowerOf2()) {
6340 // Multiplying by one less than a power of two, replace with a shift
6342 SDValue ShiftedVal =
6343 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6344 DAG.getConstant(VP1.logBase2(), MVT::i64));
6345 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6347 APInt VM1 = Value - 1;
6348 if (VM1.isPowerOf2()) {
6349 // Multiplying by one more than a power of two, replace with a shift
6351 SDValue ShiftedVal =
6352 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6353 DAG.getConstant(VM1.logBase2(), MVT::i64));
6354 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6360 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6361 EVT VT = N->getValueType(0);
6362 if (VT != MVT::f32 && VT != MVT::f64)
6364 // Only optimize when the source and destination types have the same width.
6365 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6368 // If the result of an integer load is only used by an integer-to-float
6369 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6370 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6371 SDValue N0 = N->getOperand(0);
6372 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6373 // Do not change the width of a volatile load.
6374 !cast<LoadSDNode>(N0)->isVolatile()) {
6375 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6376 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6377 LN0->getPointerInfo(), LN0->isVolatile(),
6378 LN0->isNonTemporal(), LN0->isInvariant(),
6379 LN0->getAlignment());
6381 // Make sure successors of the original load stay after it by updating them
6382 // to use the new Chain.
6383 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6386 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6387 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6393 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6394 /// searches for and classifies those shifts.
6395 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6397 if (N.getOpcode() == ISD::SHL)
6399 else if (N.getOpcode() == ISD::SRL)
6404 if (!isa<ConstantSDNode>(N.getOperand(1)))
6407 ShiftAmount = N->getConstantOperandVal(1);
6408 Src = N->getOperand(0);
6412 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6413 /// registers viewed as a high/low pair. This function looks for the pattern:
6414 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6415 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6417 static SDValue tryCombineToEXTR(SDNode *N,
6418 TargetLowering::DAGCombinerInfo &DCI) {
6419 SelectionDAG &DAG = DCI.DAG;
6421 EVT VT = N->getValueType(0);
6423 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6425 if (VT != MVT::i32 && VT != MVT::i64)
6429 uint32_t ShiftLHS = 0;
6431 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6435 uint32_t ShiftRHS = 0;
6437 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6440 // If they're both trying to come from the high part of the register, they're
6441 // not really an EXTR.
6442 if (LHSFromHi == RHSFromHi)
6445 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6449 std::swap(LHS, RHS);
6450 std::swap(ShiftLHS, ShiftRHS);
6453 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6454 DAG.getConstant(ShiftRHS, MVT::i64));
6457 static SDValue tryCombineToBSL(SDNode *N,
6458 TargetLowering::DAGCombinerInfo &DCI) {
6459 EVT VT = N->getValueType(0);
6460 SelectionDAG &DAG = DCI.DAG;
6466 SDValue N0 = N->getOperand(0);
6467 if (N0.getOpcode() != ISD::AND)
6470 SDValue N1 = N->getOperand(1);
6471 if (N1.getOpcode() != ISD::AND)
6474 // We only have to look for constant vectors here since the general, variable
6475 // case can be handled in TableGen.
6476 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6477 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6478 for (int i = 1; i >= 0; --i)
6479 for (int j = 1; j >= 0; --j) {
6480 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6481 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6485 bool FoundMatch = true;
6486 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6487 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6488 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6490 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6497 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6498 N0->getOperand(1 - i), N1->getOperand(1 - j));
6504 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6505 const AArch64Subtarget *Subtarget) {
6506 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6507 if (!EnableAArch64ExtrGeneration)
6509 SelectionDAG &DAG = DCI.DAG;
6510 EVT VT = N->getValueType(0);
6512 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6515 SDValue Res = tryCombineToEXTR(N, DCI);
6519 Res = tryCombineToBSL(N, DCI);
6526 static SDValue performBitcastCombine(SDNode *N,
6527 TargetLowering::DAGCombinerInfo &DCI,
6528 SelectionDAG &DAG) {
6529 // Wait 'til after everything is legalized to try this. That way we have
6530 // legal vector types and such.
6531 if (DCI.isBeforeLegalizeOps())
6534 // Remove extraneous bitcasts around an extract_subvector.
6536 // (v4i16 (bitconvert
6537 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6539 // (extract_subvector ((v8i16 ...), (i64 4)))
6541 // Only interested in 64-bit vectors as the ultimate result.
6542 EVT VT = N->getValueType(0);
6545 if (VT.getSimpleVT().getSizeInBits() != 64)
6547 // Is the operand an extract_subvector starting at the beginning or halfway
6548 // point of the vector? A low half may also come through as an
6549 // EXTRACT_SUBREG, so look for that, too.
6550 SDValue Op0 = N->getOperand(0);
6551 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6552 !(Op0->isMachineOpcode() &&
6553 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6555 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6556 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6557 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6559 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6560 if (idx != AArch64::dsub)
6562 // The dsub reference is equivalent to a lane zero subvector reference.
6565 // Look through the bitcast of the input to the extract.
6566 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6568 SDValue Source = Op0->getOperand(0)->getOperand(0);
6569 // If the source type has twice the number of elements as our destination
6570 // type, we know this is an extract of the high or low half of the vector.
6571 EVT SVT = Source->getValueType(0);
6572 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6575 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6577 // Create the simplified form to just extract the low or high half of the
6578 // vector directly rather than bothering with the bitcasts.
6580 unsigned NumElements = VT.getVectorNumElements();
6582 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6583 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6585 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6586 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6592 static SDValue performConcatVectorsCombine(SDNode *N,
6593 TargetLowering::DAGCombinerInfo &DCI,
6594 SelectionDAG &DAG) {
6595 // Wait 'til after everything is legalized to try this. That way we have
6596 // legal vector types and such.
6597 if (DCI.isBeforeLegalizeOps())
6601 EVT VT = N->getValueType(0);
6603 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6604 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6605 // canonicalise to that.
6606 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6607 assert(VT.getVectorElementType().getSizeInBits() == 64);
6608 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6609 WidenVector(N->getOperand(0), DAG),
6610 DAG.getConstant(0, MVT::i64));
6613 // Canonicalise concat_vectors so that the right-hand vector has as few
6614 // bit-casts as possible before its real operation. The primary matching
6615 // destination for these operations will be the narrowing "2" instructions,
6616 // which depend on the operation being performed on this right-hand vector.
6618 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6620 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6622 SDValue Op1 = N->getOperand(1);
6623 if (Op1->getOpcode() != ISD::BITCAST)
6625 SDValue RHS = Op1->getOperand(0);
6626 MVT RHSTy = RHS.getValueType().getSimpleVT();
6627 // If the RHS is not a vector, this is not the pattern we're looking for.
6628 if (!RHSTy.isVector())
6631 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6633 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6634 RHSTy.getVectorNumElements() * 2);
6636 ISD::BITCAST, dl, VT,
6637 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6638 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6641 static SDValue tryCombineFixedPointConvert(SDNode *N,
6642 TargetLowering::DAGCombinerInfo &DCI,
6643 SelectionDAG &DAG) {
6644 // Wait 'til after everything is legalized to try this. That way we have
6645 // legal vector types and such.
6646 if (DCI.isBeforeLegalizeOps())
6648 // Transform a scalar conversion of a value from a lane extract into a
6649 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6650 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6651 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6653 // The second form interacts better with instruction selection and the
6654 // register allocator to avoid cross-class register copies that aren't
6655 // coalescable due to a lane reference.
6657 // Check the operand and see if it originates from a lane extract.
6658 SDValue Op1 = N->getOperand(1);
6659 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6660 // Yep, no additional predication needed. Perform the transform.
6661 SDValue IID = N->getOperand(0);
6662 SDValue Shift = N->getOperand(2);
6663 SDValue Vec = Op1.getOperand(0);
6664 SDValue Lane = Op1.getOperand(1);
6665 EVT ResTy = N->getValueType(0);
6669 // The vector width should be 128 bits by the time we get here, even
6670 // if it started as 64 bits (the extract_vector handling will have
6672 assert(Vec.getValueType().getSizeInBits() == 128 &&
6673 "unexpected vector size on extract_vector_elt!");
6674 if (Vec.getValueType() == MVT::v4i32)
6675 VecResTy = MVT::v4f32;
6676 else if (Vec.getValueType() == MVT::v2i64)
6677 VecResTy = MVT::v2f64;
6679 assert(0 && "unexpected vector type!");
6682 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6683 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6688 // AArch64 high-vector "long" operations are formed by performing the non-high
6689 // version on an extract_subvector of each operand which gets the high half:
6691 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6693 // However, there are cases which don't have an extract_high explicitly, but
6694 // have another operation that can be made compatible with one for free. For
6697 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6699 // This routine does the actual conversion of such DUPs, once outer routines
6700 // have determined that everything else is in order.
6701 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6702 // We can handle most types of duplicate, but the lane ones have an extra
6703 // operand saying *which* lane, so we need to know.
6705 switch (N.getOpcode()) {
6706 case AArch64ISD::DUP:
6709 case AArch64ISD::DUPLANE8:
6710 case AArch64ISD::DUPLANE16:
6711 case AArch64ISD::DUPLANE32:
6712 case AArch64ISD::DUPLANE64:
6719 MVT NarrowTy = N.getSimpleValueType();
6720 if (!NarrowTy.is64BitVector())
6723 MVT ElementTy = NarrowTy.getVectorElementType();
6724 unsigned NumElems = NarrowTy.getVectorNumElements();
6725 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6729 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6732 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6734 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6735 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6738 static bool isEssentiallyExtractSubvector(SDValue N) {
6739 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6742 return N.getOpcode() == ISD::BITCAST &&
6743 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6746 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6747 struct GenericSetCCInfo {
6748 const SDValue *Opnd0;
6749 const SDValue *Opnd1;
6753 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6754 struct AArch64SetCCInfo {
6756 AArch64CC::CondCode CC;
6759 /// \brief Helper structure to keep track of SetCC information.
6761 GenericSetCCInfo Generic;
6762 AArch64SetCCInfo AArch64;
6765 /// \brief Helper structure to be able to read SetCC information. If set to
6766 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6767 /// GenericSetCCInfo.
6768 struct SetCCInfoAndKind {
6773 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6775 /// AArch64 lowered one.
6776 /// \p SetCCInfo is filled accordingly.
6777 /// \post SetCCInfo is meanginfull only when this function returns true.
6778 /// \return True when Op is a kind of SET_CC operation.
6779 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6780 // If this is a setcc, this is straight forward.
6781 if (Op.getOpcode() == ISD::SETCC) {
6782 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6783 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6784 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6785 SetCCInfo.IsAArch64 = false;
6788 // Otherwise, check if this is a matching csel instruction.
6792 if (Op.getOpcode() != AArch64ISD::CSEL)
6794 // Set the information about the operands.
6795 // TODO: we want the operands of the Cmp not the csel
6796 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6797 SetCCInfo.IsAArch64 = true;
6798 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6799 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6801 // Check that the operands matches the constraints:
6802 // (1) Both operands must be constants.
6803 // (2) One must be 1 and the other must be 0.
6804 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6805 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6808 if (!TValue || !FValue)
6812 if (!TValue->isOne()) {
6813 // Update the comparison when we are interested in !cc.
6814 std::swap(TValue, FValue);
6815 SetCCInfo.Info.AArch64.CC =
6816 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6818 return TValue->isOne() && FValue->isNullValue();
6821 // Returns true if Op is setcc or zext of setcc.
6822 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6823 if (isSetCC(Op, Info))
6825 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6826 isSetCC(Op->getOperand(0), Info));
6829 // The folding we want to perform is:
6830 // (add x, [zext] (setcc cc ...) )
6832 // (csel x, (add x, 1), !cc ...)
6834 // The latter will get matched to a CSINC instruction.
6835 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6836 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6837 SDValue LHS = Op->getOperand(0);
6838 SDValue RHS = Op->getOperand(1);
6839 SetCCInfoAndKind InfoAndKind;
6841 // If neither operand is a SET_CC, give up.
6842 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6843 std::swap(LHS, RHS);
6844 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6848 // FIXME: This could be generatized to work for FP comparisons.
6849 EVT CmpVT = InfoAndKind.IsAArch64
6850 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
6851 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6852 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6858 if (InfoAndKind.IsAArch64) {
6859 CCVal = DAG.getConstant(
6860 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
6861 Cmp = *InfoAndKind.Info.AArch64.Cmp;
6863 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6864 *InfoAndKind.Info.Generic.Opnd1,
6865 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6868 EVT VT = Op->getValueType(0);
6869 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6870 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6873 // The basic add/sub long vector instructions have variants with "2" on the end
6874 // which act on the high-half of their inputs. They are normally matched by
6877 // (add (zeroext (extract_high LHS)),
6878 // (zeroext (extract_high RHS)))
6879 // -> uaddl2 vD, vN, vM
6881 // However, if one of the extracts is something like a duplicate, this
6882 // instruction can still be used profitably. This function puts the DAG into a
6883 // more appropriate form for those patterns to trigger.
6884 static SDValue performAddSubLongCombine(SDNode *N,
6885 TargetLowering::DAGCombinerInfo &DCI,
6886 SelectionDAG &DAG) {
6887 if (DCI.isBeforeLegalizeOps())
6890 MVT VT = N->getSimpleValueType(0);
6891 if (!VT.is128BitVector()) {
6892 if (N->getOpcode() == ISD::ADD)
6893 return performSetccAddFolding(N, DAG);
6897 // Make sure both branches are extended in the same way.
6898 SDValue LHS = N->getOperand(0);
6899 SDValue RHS = N->getOperand(1);
6900 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
6901 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
6902 LHS.getOpcode() != RHS.getOpcode())
6905 unsigned ExtType = LHS.getOpcode();
6907 // It's not worth doing if at least one of the inputs isn't already an
6908 // extract, but we don't know which it'll be so we have to try both.
6909 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
6910 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
6914 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6915 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
6916 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
6920 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
6923 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
6926 // Massage DAGs which we can use the high-half "long" operations on into
6927 // something isel will recognize better. E.g.
6929 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
6930 // (aarch64_neon_umull (extract_high (v2i64 vec)))
6931 // (extract_high (v2i64 (dup128 scalar)))))
6933 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
6934 TargetLowering::DAGCombinerInfo &DCI,
6935 SelectionDAG &DAG) {
6936 if (DCI.isBeforeLegalizeOps())
6939 SDValue LHS = N->getOperand(1);
6940 SDValue RHS = N->getOperand(2);
6941 assert(LHS.getValueType().is64BitVector() &&
6942 RHS.getValueType().is64BitVector() &&
6943 "unexpected shape for long operation");
6945 // Either node could be a DUP, but it's not worth doing both of them (you'd
6946 // just as well use the non-high version) so look for a corresponding extract
6947 // operation on the other "wing".
6948 if (isEssentiallyExtractSubvector(LHS)) {
6949 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
6952 } else if (isEssentiallyExtractSubvector(RHS)) {
6953 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
6958 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
6959 N->getOperand(0), LHS, RHS);
6962 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
6963 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
6964 unsigned ElemBits = ElemTy.getSizeInBits();
6966 int64_t ShiftAmount;
6967 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
6968 APInt SplatValue, SplatUndef;
6969 unsigned SplatBitSize;
6971 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
6972 HasAnyUndefs, ElemBits) ||
6973 SplatBitSize != ElemBits)
6976 ShiftAmount = SplatValue.getSExtValue();
6977 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
6978 ShiftAmount = CVN->getSExtValue();
6986 llvm_unreachable("Unknown shift intrinsic");
6987 case Intrinsic::aarch64_neon_sqshl:
6988 Opcode = AArch64ISD::SQSHL_I;
6989 IsRightShift = false;
6991 case Intrinsic::aarch64_neon_uqshl:
6992 Opcode = AArch64ISD::UQSHL_I;
6993 IsRightShift = false;
6995 case Intrinsic::aarch64_neon_srshl:
6996 Opcode = AArch64ISD::SRSHR_I;
6997 IsRightShift = true;
6999 case Intrinsic::aarch64_neon_urshl:
7000 Opcode = AArch64ISD::URSHR_I;
7001 IsRightShift = true;
7003 case Intrinsic::aarch64_neon_sqshlu:
7004 Opcode = AArch64ISD::SQSHLU_I;
7005 IsRightShift = false;
7009 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7010 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7011 DAG.getConstant(-ShiftAmount, MVT::i32));
7012 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount <= ElemBits)
7013 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7014 DAG.getConstant(ShiftAmount, MVT::i32));
7019 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7020 // the intrinsics must be legal and take an i32, this means there's almost
7021 // certainly going to be a zext in the DAG which we can eliminate.
7022 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7023 SDValue AndN = N->getOperand(2);
7024 if (AndN.getOpcode() != ISD::AND)
7027 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7028 if (!CMask || CMask->getZExtValue() != Mask)
7031 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7032 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7035 static SDValue performIntrinsicCombine(SDNode *N,
7036 TargetLowering::DAGCombinerInfo &DCI,
7037 const AArch64Subtarget *Subtarget) {
7038 SelectionDAG &DAG = DCI.DAG;
7039 unsigned IID = getIntrinsicID(N);
7043 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7044 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7045 return tryCombineFixedPointConvert(N, DCI, DAG);
7047 case Intrinsic::aarch64_neon_fmax:
7048 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7049 N->getOperand(1), N->getOperand(2));
7050 case Intrinsic::aarch64_neon_fmin:
7051 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7052 N->getOperand(1), N->getOperand(2));
7053 case Intrinsic::aarch64_neon_smull:
7054 case Intrinsic::aarch64_neon_umull:
7055 case Intrinsic::aarch64_neon_pmull:
7056 case Intrinsic::aarch64_neon_sqdmull:
7057 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7058 case Intrinsic::aarch64_neon_sqshl:
7059 case Intrinsic::aarch64_neon_uqshl:
7060 case Intrinsic::aarch64_neon_sqshlu:
7061 case Intrinsic::aarch64_neon_srshl:
7062 case Intrinsic::aarch64_neon_urshl:
7063 return tryCombineShiftImm(IID, N, DAG);
7064 case Intrinsic::aarch64_crc32b:
7065 case Intrinsic::aarch64_crc32cb:
7066 return tryCombineCRC32(0xff, N, DAG);
7067 case Intrinsic::aarch64_crc32h:
7068 case Intrinsic::aarch64_crc32ch:
7069 return tryCombineCRC32(0xffff, N, DAG);
7074 static SDValue performExtendCombine(SDNode *N,
7075 TargetLowering::DAGCombinerInfo &DCI,
7076 SelectionDAG &DAG) {
7077 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7078 // we can convert that DUP into another extract_high (of a bigger DUP), which
7079 // helps the backend to decide that an sabdl2 would be useful, saving a real
7080 // extract_high operation.
7081 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7082 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7083 SDNode *ABDNode = N->getOperand(0).getNode();
7084 unsigned IID = getIntrinsicID(ABDNode);
7085 if (IID == Intrinsic::aarch64_neon_sabd ||
7086 IID == Intrinsic::aarch64_neon_uabd) {
7087 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7088 if (!NewABD.getNode())
7091 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7096 // This is effectively a custom type legalization for AArch64.
7098 // Type legalization will split an extend of a small, legal, type to a larger
7099 // illegal type by first splitting the destination type, often creating
7100 // illegal source types, which then get legalized in isel-confusing ways,
7101 // leading to really terrible codegen. E.g.,
7102 // %result = v8i32 sext v8i8 %value
7104 // %losrc = extract_subreg %value, ...
7105 // %hisrc = extract_subreg %value, ...
7106 // %lo = v4i32 sext v4i8 %losrc
7107 // %hi = v4i32 sext v4i8 %hisrc
7108 // Things go rapidly downhill from there.
7110 // For AArch64, the [sz]ext vector instructions can only go up one element
7111 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7112 // take two instructions.
7114 // This implies that the most efficient way to do the extend from v8i8
7115 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7116 // the normal splitting to happen for the v8i16->v8i32.
7118 // This is pre-legalization to catch some cases where the default
7119 // type legalization will create ill-tempered code.
7120 if (!DCI.isBeforeLegalizeOps())
7123 // We're only interested in cleaning things up for non-legal vector types
7124 // here. If both the source and destination are legal, things will just
7125 // work naturally without any fiddling.
7126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7127 EVT ResVT = N->getValueType(0);
7128 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7130 // If the vector type isn't a simple VT, it's beyond the scope of what
7131 // we're worried about here. Let legalization do its thing and hope for
7133 if (!ResVT.isSimple())
7136 SDValue Src = N->getOperand(0);
7137 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7138 // If the source VT is a 64-bit vector, we can play games and get the
7139 // better results we want.
7140 if (SrcVT.getSizeInBits() != 64)
7143 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7144 unsigned ElementCount = SrcVT.getVectorNumElements();
7145 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7147 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7149 // Now split the rest of the operation into two halves, each with a 64
7153 unsigned NumElements = ResVT.getVectorNumElements();
7154 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7155 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7156 ResVT.getVectorElementType(), NumElements / 2);
7158 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7159 LoVT.getVectorNumElements());
7160 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7161 DAG.getIntPtrConstant(0));
7162 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7163 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7164 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7165 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7167 // Now combine the parts back together so we still have a single result
7168 // like the combiner expects.
7169 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7172 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7173 /// value. The load store optimizer pass will merge them to store pair stores.
7174 /// This has better performance than a splat of the scalar followed by a split
7175 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7176 /// followed by an ext.b and two stores.
7177 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7178 SDValue StVal = St->getValue();
7179 EVT VT = StVal.getValueType();
7181 // Don't replace floating point stores, they possibly won't be transformed to
7182 // stp because of the store pair suppress pass.
7183 if (VT.isFloatingPoint())
7186 // Check for insert vector elements.
7187 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7190 // We can express a splat as store pair(s) for 2 or 4 elements.
7191 unsigned NumVecElts = VT.getVectorNumElements();
7192 if (NumVecElts != 4 && NumVecElts != 2)
7194 SDValue SplatVal = StVal.getOperand(1);
7195 unsigned RemainInsertElts = NumVecElts - 1;
7197 // Check that this is a splat.
7198 while (--RemainInsertElts) {
7199 SDValue NextInsertElt = StVal.getOperand(0);
7200 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7202 if (NextInsertElt.getOperand(1) != SplatVal)
7204 StVal = NextInsertElt;
7206 unsigned OrigAlignment = St->getAlignment();
7207 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7208 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7210 // Create scalar stores. This is at least as good as the code sequence for a
7211 // split unaligned store wich is a dup.s, ext.b, and two stores.
7212 // Most of the time the three stores should be replaced by store pair
7213 // instructions (stp).
7215 SDValue BasePtr = St->getBasePtr();
7217 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7218 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7220 unsigned Offset = EltOffset;
7221 while (--NumVecElts) {
7222 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7223 DAG.getConstant(Offset, MVT::i64));
7224 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7225 St->getPointerInfo(), St->isVolatile(),
7226 St->isNonTemporal(), Alignment);
7227 Offset += EltOffset;
7232 static SDValue performSTORECombine(SDNode *N,
7233 TargetLowering::DAGCombinerInfo &DCI,
7235 const AArch64Subtarget *Subtarget) {
7236 if (!DCI.isBeforeLegalize())
7239 StoreSDNode *S = cast<StoreSDNode>(N);
7240 if (S->isVolatile())
7243 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7244 // page boundries. We want to split such stores.
7245 if (!Subtarget->isCyclone())
7248 // Don't split at Oz.
7249 MachineFunction &MF = DAG.getMachineFunction();
7250 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7251 AttributeSet::FunctionIndex, Attribute::MinSize);
7255 SDValue StVal = S->getValue();
7256 EVT VT = StVal.getValueType();
7258 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7259 // those up regresses performance on micro-benchmarks and olden/bh.
7260 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7263 // Split unaligned 16B stores. They are terrible for performance.
7264 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7265 // extensions can use this to mark that it does not want splitting to happen
7266 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7267 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7268 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7269 S->getAlignment() <= 2)
7272 // If we get a splat of a scalar convert this vector store to a store of
7273 // scalars. They will be merged into store pairs thereby removing two
7275 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7276 if (ReplacedSplat != SDValue())
7277 return ReplacedSplat;
7280 unsigned NumElts = VT.getVectorNumElements() / 2;
7281 // Split VT into two.
7283 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7284 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7285 DAG.getIntPtrConstant(0));
7286 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7287 DAG.getIntPtrConstant(NumElts));
7288 SDValue BasePtr = S->getBasePtr();
7290 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7291 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7292 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7293 DAG.getConstant(8, MVT::i64));
7294 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7295 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7299 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7300 /// post-increment LD1R.
7301 static SDValue performPostLD1Combine(SDNode *N,
7302 TargetLowering::DAGCombinerInfo &DCI,
7304 if (DCI.isBeforeLegalizeOps())
7307 SelectionDAG &DAG = DCI.DAG;
7308 EVT VT = N->getValueType(0);
7310 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7311 SDNode *LD = N->getOperand(LoadIdx).getNode();
7312 // If it is not LOAD, can not do such combine.
7313 if (LD->getOpcode() != ISD::LOAD)
7316 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7317 EVT MemVT = LoadSDN->getMemoryVT();
7318 // Check if memory operand is the same type as the vector element.
7319 if (MemVT != VT.getVectorElementType())
7322 // Check if there are other uses. If so, do not combine as it will introduce
7324 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7326 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7332 SDValue Addr = LD->getOperand(1);
7333 SDValue Vector = N->getOperand(0);
7334 // Search for a use of the address operand that is an increment.
7335 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7336 Addr.getNode()->use_end(); UI != UE; ++UI) {
7338 if (User->getOpcode() != ISD::ADD
7339 || UI.getUse().getResNo() != Addr.getResNo())
7342 // Check that the add is independent of the load. Otherwise, folding it
7343 // would create a cycle.
7344 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7346 // Also check that add is not used in the vector operand. This would also
7348 if (User->isPredecessorOf(Vector.getNode()))
7351 // If the increment is a constant, it must match the memory ref size.
7352 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7353 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7354 uint32_t IncVal = CInc->getZExtValue();
7355 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7356 if (IncVal != NumBytes)
7358 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7361 SmallVector<SDValue, 8> Ops;
7362 Ops.push_back(LD->getOperand(0)); // Chain
7364 Ops.push_back(Vector); // The vector to be inserted
7365 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7367 Ops.push_back(Addr);
7370 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7371 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7372 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7373 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7375 LoadSDN->getMemOperand());
7378 std::vector<SDValue> NewResults;
7379 NewResults.push_back(SDValue(LD, 0)); // The result of load
7380 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7381 DCI.CombineTo(LD, NewResults);
7382 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7383 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7390 /// Target-specific DAG combine function for NEON load/store intrinsics
7391 /// to merge base address updates.
7392 static SDValue performNEONPostLDSTCombine(SDNode *N,
7393 TargetLowering::DAGCombinerInfo &DCI,
7394 SelectionDAG &DAG) {
7395 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7398 unsigned AddrOpIdx = N->getNumOperands() - 1;
7399 SDValue Addr = N->getOperand(AddrOpIdx);
7401 // Search for a use of the address operand that is an increment.
7402 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7403 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7405 if (User->getOpcode() != ISD::ADD ||
7406 UI.getUse().getResNo() != Addr.getResNo())
7409 // Check that the add is independent of the load/store. Otherwise, folding
7410 // it would create a cycle.
7411 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7414 // Find the new opcode for the updating load/store.
7415 bool IsStore = false;
7416 bool IsLaneOp = false;
7417 bool IsDupOp = false;
7418 unsigned NewOpc = 0;
7419 unsigned NumVecs = 0;
7420 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7422 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7423 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7425 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7427 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7429 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7430 NumVecs = 2; IsStore = true; break;
7431 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7432 NumVecs = 3; IsStore = true; break;
7433 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7434 NumVecs = 4; IsStore = true; break;
7435 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7437 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7439 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7441 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7442 NumVecs = 2; IsStore = true; break;
7443 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7444 NumVecs = 3; IsStore = true; break;
7445 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7446 NumVecs = 4; IsStore = true; break;
7447 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7448 NumVecs = 2; IsDupOp = true; break;
7449 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7450 NumVecs = 3; IsDupOp = true; break;
7451 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7452 NumVecs = 4; IsDupOp = true; break;
7453 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7454 NumVecs = 2; IsLaneOp = true; break;
7455 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7456 NumVecs = 3; IsLaneOp = true; break;
7457 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7458 NumVecs = 4; IsLaneOp = true; break;
7459 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7460 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7461 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7462 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7463 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7464 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7469 VecTy = N->getOperand(2).getValueType();
7471 VecTy = N->getValueType(0);
7473 // If the increment is a constant, it must match the memory ref size.
7474 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7475 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7476 uint32_t IncVal = CInc->getZExtValue();
7477 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7478 if (IsLaneOp || IsDupOp)
7479 NumBytes /= VecTy.getVectorNumElements();
7480 if (IncVal != NumBytes)
7482 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7484 SmallVector<SDValue, 8> Ops;
7485 Ops.push_back(N->getOperand(0)); // Incoming chain
7486 // Load lane and store have vector list as input.
7487 if (IsLaneOp || IsStore)
7488 for (unsigned i = 2; i < AddrOpIdx; ++i)
7489 Ops.push_back(N->getOperand(i));
7490 Ops.push_back(Addr); // Base register
7495 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7497 for (n = 0; n < NumResultVecs; ++n)
7499 Tys[n++] = MVT::i64; // Type of write back register
7500 Tys[n] = MVT::Other; // Type of the chain
7501 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7503 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7504 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7505 MemInt->getMemoryVT(),
7506 MemInt->getMemOperand());
7509 std::vector<SDValue> NewResults;
7510 for (unsigned i = 0; i < NumResultVecs; ++i) {
7511 NewResults.push_back(SDValue(UpdN.getNode(), i));
7513 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7514 DCI.CombineTo(N, NewResults);
7515 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7522 // Optimize compare with zero and branch.
7523 static SDValue performBRCONDCombine(SDNode *N,
7524 TargetLowering::DAGCombinerInfo &DCI,
7525 SelectionDAG &DAG) {
7526 SDValue Chain = N->getOperand(0);
7527 SDValue Dest = N->getOperand(1);
7528 SDValue CCVal = N->getOperand(2);
7529 SDValue Cmp = N->getOperand(3);
7531 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7532 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7533 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7536 unsigned CmpOpc = Cmp.getOpcode();
7537 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7540 // Only attempt folding if there is only one use of the flag and no use of the
7542 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7545 SDValue LHS = Cmp.getOperand(0);
7546 SDValue RHS = Cmp.getOperand(1);
7548 assert(LHS.getValueType() == RHS.getValueType() &&
7549 "Expected the value type to be the same for both operands!");
7550 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7553 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7554 std::swap(LHS, RHS);
7556 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7559 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7560 LHS.getOpcode() == ISD::SRL)
7563 // Fold the compare into the branch instruction.
7565 if (CC == AArch64CC::EQ)
7566 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7568 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7570 // Do not add new nodes to DAG combiner worklist.
7571 DCI.CombineTo(N, BR, false);
7576 // vselect (v1i1 setcc) ->
7577 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7578 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7579 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7581 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7582 SDValue N0 = N->getOperand(0);
7583 EVT CCVT = N0.getValueType();
7585 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7586 CCVT.getVectorElementType() != MVT::i1)
7589 EVT ResVT = N->getValueType(0);
7590 EVT CmpVT = N0.getOperand(0).getValueType();
7591 // Only combine when the result type is of the same size as the compared
7593 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7596 SDValue IfTrue = N->getOperand(1);
7597 SDValue IfFalse = N->getOperand(2);
7599 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7600 N0.getOperand(0), N0.getOperand(1),
7601 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7602 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7606 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7607 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7608 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7609 /// with a vector one followed by a DUP shuffle on the result.
7610 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7611 SDValue N0 = N->getOperand(0);
7612 EVT ResVT = N->getValueType(0);
7614 if (!N->getOperand(1).getValueType().isVector())
7617 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7622 EVT SrcVT = N0.getOperand(0).getValueType();
7623 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7624 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7625 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7627 // First perform a vector comparison, where lane 0 is the one we're interested
7630 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7632 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7633 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7635 // Now duplicate the comparison mask we want across all other lanes.
7636 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7637 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7638 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7641 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7644 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7645 DAGCombinerInfo &DCI) const {
7646 SelectionDAG &DAG = DCI.DAG;
7647 switch (N->getOpcode()) {
7652 return performAddSubLongCombine(N, DCI, DAG);
7654 return performXorCombine(N, DAG, DCI, Subtarget);
7656 return performMulCombine(N, DAG, DCI, Subtarget);
7657 case ISD::SINT_TO_FP:
7658 case ISD::UINT_TO_FP:
7659 return performIntToFpCombine(N, DAG);
7661 return performORCombine(N, DCI, Subtarget);
7662 case ISD::INTRINSIC_WO_CHAIN:
7663 return performIntrinsicCombine(N, DCI, Subtarget);
7664 case ISD::ANY_EXTEND:
7665 case ISD::ZERO_EXTEND:
7666 case ISD::SIGN_EXTEND:
7667 return performExtendCombine(N, DCI, DAG);
7669 return performBitcastCombine(N, DCI, DAG);
7670 case ISD::CONCAT_VECTORS:
7671 return performConcatVectorsCombine(N, DCI, DAG);
7673 return performSelectCombine(N, DAG);
7675 return performVSelectCombine(N, DCI.DAG);
7677 return performSTORECombine(N, DCI, DAG, Subtarget);
7678 case AArch64ISD::BRCOND:
7679 return performBRCONDCombine(N, DCI, DAG);
7680 case AArch64ISD::DUP:
7681 return performPostLD1Combine(N, DCI, false);
7682 case ISD::INSERT_VECTOR_ELT:
7683 return performPostLD1Combine(N, DCI, true);
7684 case ISD::INTRINSIC_VOID:
7685 case ISD::INTRINSIC_W_CHAIN:
7686 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7687 case Intrinsic::aarch64_neon_ld2:
7688 case Intrinsic::aarch64_neon_ld3:
7689 case Intrinsic::aarch64_neon_ld4:
7690 case Intrinsic::aarch64_neon_ld1x2:
7691 case Intrinsic::aarch64_neon_ld1x3:
7692 case Intrinsic::aarch64_neon_ld1x4:
7693 case Intrinsic::aarch64_neon_ld2lane:
7694 case Intrinsic::aarch64_neon_ld3lane:
7695 case Intrinsic::aarch64_neon_ld4lane:
7696 case Intrinsic::aarch64_neon_ld2r:
7697 case Intrinsic::aarch64_neon_ld3r:
7698 case Intrinsic::aarch64_neon_ld4r:
7699 case Intrinsic::aarch64_neon_st2:
7700 case Intrinsic::aarch64_neon_st3:
7701 case Intrinsic::aarch64_neon_st4:
7702 case Intrinsic::aarch64_neon_st1x2:
7703 case Intrinsic::aarch64_neon_st1x3:
7704 case Intrinsic::aarch64_neon_st1x4:
7705 case Intrinsic::aarch64_neon_st2lane:
7706 case Intrinsic::aarch64_neon_st3lane:
7707 case Intrinsic::aarch64_neon_st4lane:
7708 return performNEONPostLDSTCombine(N, DCI, DAG);
7716 // Check if the return value is used as only a return value, as otherwise
7717 // we can't perform a tail-call. In particular, we need to check for
7718 // target ISD nodes that are returns and any other "odd" constructs
7719 // that the generic analysis code won't necessarily catch.
7720 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7721 SDValue &Chain) const {
7722 if (N->getNumValues() != 1)
7724 if (!N->hasNUsesOfValue(1, 0))
7727 SDValue TCChain = Chain;
7728 SDNode *Copy = *N->use_begin();
7729 if (Copy->getOpcode() == ISD::CopyToReg) {
7730 // If the copy has a glue operand, we conservatively assume it isn't safe to
7731 // perform a tail call.
7732 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7735 TCChain = Copy->getOperand(0);
7736 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7739 bool HasRet = false;
7740 for (SDNode *Node : Copy->uses()) {
7741 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7753 // Return whether the an instruction can potentially be optimized to a tail
7754 // call. This will cause the optimizers to attempt to move, or duplicate,
7755 // return instructions to help enable tail call optimizations for this
7757 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7758 if (!CI->isTailCall())
7764 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7766 ISD::MemIndexedMode &AM,
7768 SelectionDAG &DAG) const {
7769 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7772 Base = Op->getOperand(0);
7773 // All of the indexed addressing mode instructions take a signed
7774 // 9 bit immediate offset.
7775 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7776 int64_t RHSC = (int64_t)RHS->getZExtValue();
7777 if (RHSC >= 256 || RHSC <= -256)
7779 IsInc = (Op->getOpcode() == ISD::ADD);
7780 Offset = Op->getOperand(1);
7786 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7788 ISD::MemIndexedMode &AM,
7789 SelectionDAG &DAG) const {
7792 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7793 VT = LD->getMemoryVT();
7794 Ptr = LD->getBasePtr();
7795 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7796 VT = ST->getMemoryVT();
7797 Ptr = ST->getBasePtr();
7802 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7804 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7808 bool AArch64TargetLowering::getPostIndexedAddressParts(
7809 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7810 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7813 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7814 VT = LD->getMemoryVT();
7815 Ptr = LD->getBasePtr();
7816 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7817 VT = ST->getMemoryVT();
7818 Ptr = ST->getBasePtr();
7823 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7825 // Post-indexing updates the base, so it's not a valid transform
7826 // if that's not the same as the load's pointer.
7829 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7833 void AArch64TargetLowering::ReplaceNodeResults(
7834 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
7835 switch (N->getOpcode()) {
7837 llvm_unreachable("Don't know how to custom expand this");
7838 case ISD::FP_TO_UINT:
7839 case ISD::FP_TO_SINT:
7840 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7841 // Let normal code take care of it by not adding anything to Results.
7846 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7847 // Loads and stores less than 128-bits are already atomic; ones above that
7848 // are doomed anyway, so defer to the default libcall and blame the OS when
7850 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7851 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7852 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7853 return LI->getType()->getPrimitiveSizeInBits() == 128;
7855 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7856 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7859 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7860 AtomicOrdering Ord) const {
7861 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7862 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7864 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7866 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7867 // intrinsic must return {i64, i64} and we have to recombine them into a
7868 // single i128 here.
7869 if (ValTy->getPrimitiveSizeInBits() == 128) {
7871 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
7872 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7874 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7875 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
7877 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
7878 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
7879 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
7880 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
7881 return Builder.CreateOr(
7882 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
7885 Type *Tys[] = { Addr->getType() };
7887 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
7888 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
7890 return Builder.CreateTruncOrBitCast(
7891 Builder.CreateCall(Ldxr, Addr),
7892 cast<PointerType>(Addr->getType())->getElementType());
7895 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
7896 Value *Val, Value *Addr,
7897 AtomicOrdering Ord) const {
7898 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7900 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7902 // Since the intrinsics must have legal type, the i128 intrinsics take two
7903 // parameters: "i64, i64". We must marshal Val into the appropriate form
7905 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
7907 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
7908 Function *Stxr = Intrinsic::getDeclaration(M, Int);
7909 Type *Int64Ty = Type::getInt64Ty(M->getContext());
7911 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
7912 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
7913 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7914 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
7918 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
7919 Type *Tys[] = { Addr->getType() };
7920 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
7922 return Builder.CreateCall2(
7923 Stxr, Builder.CreateZExtOrBitCast(
7924 Val, Stxr->getFunctionType()->getParamType(0)),