1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
46 static cl::opt<AlignMode>
47 Align(cl::desc("Load/store alignment support"),
48 cl::Hidden, cl::init(NoStrictAlign),
50 clEnumValN(StrictAlign, "aarch64-strict-align",
51 "Disallow all unaligned memory accesses"),
52 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
53 "Allow unaligned memory accesses"),
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
64 cl::desc("Allow AArch64 SLI/SRI formation"),
67 //===----------------------------------------------------------------------===//
68 // AArch64 Lowering public interface.
69 //===----------------------------------------------------------------------===//
70 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
71 if (TT.isOSBinFormatMachO())
72 return new AArch64_MachoTargetObjectFile();
74 return new AArch64_ELFTargetObjectFile();
77 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
79 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82 // we have to make something up. Arbitrarily, choose ZeroOrOne.
83 setBooleanContents(ZeroOrOneBooleanContent);
84 // When comparing vectors the result sets the different elements in the
85 // vector to all-one or all-zero.
86 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
92 if (Subtarget->hasFPARMv8()) {
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
99 if (Subtarget->hasNEON()) {
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102 // Someone set us up the NEON.
103 addDRTypeForNEON(MVT::v2f32);
104 addDRTypeForNEON(MVT::v8i8);
105 addDRTypeForNEON(MVT::v4i16);
106 addDRTypeForNEON(MVT::v2i32);
107 addDRTypeForNEON(MVT::v1i64);
108 addDRTypeForNEON(MVT::v1f64);
110 addQRTypeForNEON(MVT::v4f32);
111 addQRTypeForNEON(MVT::v2f64);
112 addQRTypeForNEON(MVT::v16i8);
113 addQRTypeForNEON(MVT::v8i16);
114 addQRTypeForNEON(MVT::v4i32);
115 addQRTypeForNEON(MVT::v2i64);
118 // Compute derived properties from the register classes
119 computeRegisterProperties();
121 // Provide all sorts of operation actions
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
141 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
142 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::FREM, MVT::f32, Expand);
149 setOperationAction(ISD::FREM, MVT::f64, Expand);
150 setOperationAction(ISD::FREM, MVT::f80, Expand);
152 // Custom lowering hooks are needed for XOR
153 // to fold it into CSINC/CSINV.
154 setOperationAction(ISD::XOR, MVT::i32, Custom);
155 setOperationAction(ISD::XOR, MVT::i64, Custom);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
158 // there's a valid register class, so we need custom operations in most cases.
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
198 // Variable arguments.
199 setOperationAction(ISD::VASTART, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Custom);
201 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
202 setOperationAction(ISD::VAEND, MVT::Other, Expand);
204 // Variable-sized objects.
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
209 // Exception handling.
210 // FIXME: These are guesses. Has this been defined yet?
211 setExceptionPointerRegister(AArch64::X0);
212 setExceptionSelectorRegister(AArch64::X1);
214 // Constant pool entries
215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
221 setOperationAction(ISD::ADDC, MVT::i32, Custom);
222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
223 setOperationAction(ISD::SUBC, MVT::i32, Custom);
224 setOperationAction(ISD::SUBE, MVT::i32, Custom);
225 setOperationAction(ISD::ADDC, MVT::i64, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
227 setOperationAction(ISD::SUBC, MVT::i64, Custom);
228 setOperationAction(ISD::SUBE, MVT::i64, Custom);
230 // AArch64 lacks both left-rotate and popcount instructions.
231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
234 // AArch64 doesn't have {U|S}MUL_LOHI.
235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240 // counterparts, which AArch64 supports directly.
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
247 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::SREM, MVT::i64, Expand);
253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::UREM, MVT::i32, Expand);
256 setOperationAction(ISD::UREM, MVT::i64, Expand);
258 // Custom lower Add/Sub/Mul with overflow.
259 setOperationAction(ISD::SADDO, MVT::i32, Custom);
260 setOperationAction(ISD::SADDO, MVT::i64, Custom);
261 setOperationAction(ISD::UADDO, MVT::i32, Custom);
262 setOperationAction(ISD::UADDO, MVT::i64, Custom);
263 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
265 setOperationAction(ISD::USUBO, MVT::i32, Custom);
266 setOperationAction(ISD::USUBO, MVT::i64, Custom);
267 setOperationAction(ISD::SMULO, MVT::i32, Custom);
268 setOperationAction(ISD::SMULO, MVT::i64, Custom);
269 setOperationAction(ISD::UMULO, MVT::i32, Custom);
270 setOperationAction(ISD::UMULO, MVT::i64, Custom);
272 setOperationAction(ISD::FSIN, MVT::f32, Expand);
273 setOperationAction(ISD::FSIN, MVT::f64, Expand);
274 setOperationAction(ISD::FCOS, MVT::f32, Expand);
275 setOperationAction(ISD::FCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FPOW, MVT::f32, Expand);
277 setOperationAction(ISD::FPOW, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
281 // AArch64 has implementations of a lot of rounding-like FP operations.
282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284 MVT Ty = RoundingTypes[I];
285 setOperationAction(ISD::FFLOOR, Ty, Legal);
286 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
287 setOperationAction(ISD::FCEIL, Ty, Legal);
288 setOperationAction(ISD::FRINT, Ty, Legal);
289 setOperationAction(ISD::FTRUNC, Ty, Legal);
290 setOperationAction(ISD::FROUND, Ty, Legal);
293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
295 if (Subtarget->isTargetMachO()) {
296 // For iOS, we don't want to the normal expansion of a libcall to
297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
306 // AArch64 does not have floating-point extending loads, i1 sign-extending
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
308 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
309 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
311 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
312 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
313 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
319 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
321 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
322 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
324 // Indexed loads and stores are supported.
325 for (unsigned im = (unsigned)ISD::PRE_INC;
326 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
327 setIndexedLoadAction(im, MVT::i8, Legal);
328 setIndexedLoadAction(im, MVT::i16, Legal);
329 setIndexedLoadAction(im, MVT::i32, Legal);
330 setIndexedLoadAction(im, MVT::i64, Legal);
331 setIndexedLoadAction(im, MVT::f64, Legal);
332 setIndexedLoadAction(im, MVT::f32, Legal);
333 setIndexedStoreAction(im, MVT::i8, Legal);
334 setIndexedStoreAction(im, MVT::i16, Legal);
335 setIndexedStoreAction(im, MVT::i32, Legal);
336 setIndexedStoreAction(im, MVT::i64, Legal);
337 setIndexedStoreAction(im, MVT::f64, Legal);
338 setIndexedStoreAction(im, MVT::f32, Legal);
342 setOperationAction(ISD::TRAP, MVT::Other, Legal);
344 // We combine OR nodes for bitfield operations.
345 setTargetDAGCombine(ISD::OR);
347 // Vector add and sub nodes may conceal a high-half opportunity.
348 // Also, try to fold ADD into CSINC/CSINV..
349 setTargetDAGCombine(ISD::ADD);
350 setTargetDAGCombine(ISD::SUB);
352 setTargetDAGCombine(ISD::XOR);
353 setTargetDAGCombine(ISD::SINT_TO_FP);
354 setTargetDAGCombine(ISD::UINT_TO_FP);
356 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
358 setTargetDAGCombine(ISD::ANY_EXTEND);
359 setTargetDAGCombine(ISD::ZERO_EXTEND);
360 setTargetDAGCombine(ISD::SIGN_EXTEND);
361 setTargetDAGCombine(ISD::BITCAST);
362 setTargetDAGCombine(ISD::CONCAT_VECTORS);
363 setTargetDAGCombine(ISD::STORE);
365 setTargetDAGCombine(ISD::MUL);
367 setTargetDAGCombine(ISD::SELECT);
368 setTargetDAGCombine(ISD::VSELECT);
370 setTargetDAGCombine(ISD::INTRINSIC_VOID);
371 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
372 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
374 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
375 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
376 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
378 setStackPointerRegisterToSaveRestore(AArch64::SP);
380 setSchedulingPreference(Sched::Hybrid);
383 MaskAndBranchFoldingIsLegal = true;
385 setMinFunctionAlignment(2);
387 RequireStrictAlign = (Align == StrictAlign);
389 setHasExtractBitsInsn(true);
391 if (Subtarget->hasNEON()) {
392 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
393 // silliness like this:
394 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
395 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
396 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
397 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
398 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
399 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
400 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
401 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
402 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
403 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
404 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
405 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
406 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
407 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
408 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
409 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
410 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
411 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
412 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
413 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
414 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
415 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
416 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
417 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
418 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
420 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
421 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
422 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
423 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
424 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
426 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
428 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
429 // elements smaller than i32, so promote the input to i32 first.
430 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
431 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
432 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
433 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
434 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
435 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
436 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
437 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
438 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
440 // AArch64 doesn't have MUL.2d:
441 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
442 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
443 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
444 // Likewise, narrowing and extending vector loads/stores aren't handled
446 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
447 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
449 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
452 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
453 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
454 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
455 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
457 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
459 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
460 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
461 setTruncStoreAction((MVT::SimpleValueType)VT,
462 (MVT::SimpleValueType)InnerVT, Expand);
463 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
464 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
465 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
468 // AArch64 has implementations of a lot of rounding-like FP operations.
469 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
470 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
471 MVT Ty = RoundingVecTypes[I];
472 setOperationAction(ISD::FFLOOR, Ty, Legal);
473 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
474 setOperationAction(ISD::FCEIL, Ty, Legal);
475 setOperationAction(ISD::FRINT, Ty, Legal);
476 setOperationAction(ISD::FTRUNC, Ty, Legal);
477 setOperationAction(ISD::FROUND, Ty, Legal);
482 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
483 if (VT == MVT::v2f32) {
484 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
485 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
487 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
488 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
489 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
490 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
491 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
493 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
494 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
497 // Mark vector float intrinsics as expand.
498 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
499 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
503 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
504 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
505 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
506 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
507 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
510 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
517 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
518 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
519 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
520 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
521 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
523 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
524 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
525 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
526 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
528 // CNT supports only B element sizes.
529 if (VT != MVT::v8i8 && VT != MVT::v16i8)
530 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
532 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
533 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
534 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
535 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
536 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
538 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
539 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
541 if (Subtarget->isLittleEndian()) {
542 for (unsigned im = (unsigned)ISD::PRE_INC;
543 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
544 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
545 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
550 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
551 addRegisterClass(VT, &AArch64::FPR64RegClass);
552 addTypeForNEON(VT, MVT::v2i32);
555 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
556 addRegisterClass(VT, &AArch64::FPR128RegClass);
557 addTypeForNEON(VT, MVT::v4i32);
560 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
563 return VT.changeVectorElementTypeToInteger();
566 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
567 /// Mask are known to be either zero or one and return them in the
568 /// KnownZero/KnownOne bitsets.
569 void AArch64TargetLowering::computeKnownBitsForTargetNode(
570 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
571 const SelectionDAG &DAG, unsigned Depth) const {
572 switch (Op.getOpcode()) {
575 case AArch64ISD::CSEL: {
576 APInt KnownZero2, KnownOne2;
577 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
578 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
579 KnownZero &= KnownZero2;
580 KnownOne &= KnownOne2;
583 case ISD::INTRINSIC_W_CHAIN: {
584 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
585 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
588 case Intrinsic::aarch64_ldaxr:
589 case Intrinsic::aarch64_ldxr: {
590 unsigned BitWidth = KnownOne.getBitWidth();
591 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
592 unsigned MemBits = VT.getScalarType().getSizeInBits();
593 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
599 case ISD::INTRINSIC_WO_CHAIN:
600 case ISD::INTRINSIC_VOID: {
601 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
605 case Intrinsic::aarch64_neon_umaxv:
606 case Intrinsic::aarch64_neon_uminv: {
607 // Figure out the datatype of the vector operand. The UMINV instruction
608 // will zero extend the result, so we can mark as known zero all the
609 // bits larger than the element datatype. 32-bit or larget doesn't need
610 // this as those are legal types and will be handled by isel directly.
611 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
612 unsigned BitWidth = KnownZero.getBitWidth();
613 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
614 assert(BitWidth >= 8 && "Unexpected width!");
615 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
617 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
618 assert(BitWidth >= 16 && "Unexpected width!");
619 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
629 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
633 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
634 // FIXME: On AArch64, this depends on the type.
635 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
636 // and the offset has to be a multiple of the related size in bytes.
641 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
642 const TargetLibraryInfo *libInfo) const {
643 return AArch64::createFastISel(funcInfo, libInfo);
646 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
650 case AArch64ISD::CALL: return "AArch64ISD::CALL";
651 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
652 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
653 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
654 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
655 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
656 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
657 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
658 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
659 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
660 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
661 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
662 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
663 case AArch64ISD::ADC: return "AArch64ISD::ADC";
664 case AArch64ISD::SBC: return "AArch64ISD::SBC";
665 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
666 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
667 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
668 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
669 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
670 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
671 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
672 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
673 case AArch64ISD::DUP: return "AArch64ISD::DUP";
674 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
675 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
676 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
677 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
678 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
679 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
680 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
681 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
682 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
683 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
684 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
685 case AArch64ISD::BICi: return "AArch64ISD::BICi";
686 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
687 case AArch64ISD::BSL: return "AArch64ISD::BSL";
688 case AArch64ISD::NEG: return "AArch64ISD::NEG";
689 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
690 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
691 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
692 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
693 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
694 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
695 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
696 case AArch64ISD::REV16: return "AArch64ISD::REV16";
697 case AArch64ISD::REV32: return "AArch64ISD::REV32";
698 case AArch64ISD::REV64: return "AArch64ISD::REV64";
699 case AArch64ISD::EXT: return "AArch64ISD::EXT";
700 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
701 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
702 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
703 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
704 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
705 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
706 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
707 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
708 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
709 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
710 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
711 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
712 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
713 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
714 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
715 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
716 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
717 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
718 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
719 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
720 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
721 case AArch64ISD::NOT: return "AArch64ISD::NOT";
722 case AArch64ISD::BIT: return "AArch64ISD::BIT";
723 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
724 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
725 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
726 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
727 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
728 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
729 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
730 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
731 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
732 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
733 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
734 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
735 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
736 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
737 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
738 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
739 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
740 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
741 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
742 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
743 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
744 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
745 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
746 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
747 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
748 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
749 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
750 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
751 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
752 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
753 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
754 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
755 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
756 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
757 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
758 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
763 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
764 MachineBasicBlock *MBB) const {
765 // We materialise the F128CSEL pseudo-instruction as some control flow and a
769 // [... previous instrs leading to comparison ...]
775 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
777 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
778 MachineFunction *MF = MBB->getParent();
779 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
780 DebugLoc DL = MI->getDebugLoc();
781 MachineFunction::iterator It = MBB;
784 unsigned DestReg = MI->getOperand(0).getReg();
785 unsigned IfTrueReg = MI->getOperand(1).getReg();
786 unsigned IfFalseReg = MI->getOperand(2).getReg();
787 unsigned CondCode = MI->getOperand(3).getImm();
788 bool NZCVKilled = MI->getOperand(4).isKill();
790 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
791 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
792 MF->insert(It, TrueBB);
793 MF->insert(It, EndBB);
795 // Transfer rest of current basic-block to EndBB
796 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
798 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
800 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
801 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
802 MBB->addSuccessor(TrueBB);
803 MBB->addSuccessor(EndBB);
805 // TrueBB falls through to the end.
806 TrueBB->addSuccessor(EndBB);
809 TrueBB->addLiveIn(AArch64::NZCV);
810 EndBB->addLiveIn(AArch64::NZCV);
813 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
819 MI->eraseFromParent();
824 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
825 MachineBasicBlock *BB) const {
826 switch (MI->getOpcode()) {
831 llvm_unreachable("Unexpected instruction for custom inserter!");
833 case AArch64::F128CSEL:
834 return EmitF128CSEL(MI, BB);
836 case TargetOpcode::STACKMAP:
837 case TargetOpcode::PATCHPOINT:
838 return emitPatchPoint(MI, BB);
842 //===----------------------------------------------------------------------===//
843 // AArch64 Lowering private implementation.
844 //===----------------------------------------------------------------------===//
846 //===----------------------------------------------------------------------===//
848 //===----------------------------------------------------------------------===//
850 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
852 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
855 llvm_unreachable("Unknown condition code!");
857 return AArch64CC::NE;
859 return AArch64CC::EQ;
861 return AArch64CC::GT;
863 return AArch64CC::GE;
865 return AArch64CC::LT;
867 return AArch64CC::LE;
869 return AArch64CC::HI;
871 return AArch64CC::HS;
873 return AArch64CC::LO;
875 return AArch64CC::LS;
879 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
880 static void changeFPCCToAArch64CC(ISD::CondCode CC,
881 AArch64CC::CondCode &CondCode,
882 AArch64CC::CondCode &CondCode2) {
883 CondCode2 = AArch64CC::AL;
886 llvm_unreachable("Unknown FP condition!");
889 CondCode = AArch64CC::EQ;
893 CondCode = AArch64CC::GT;
897 CondCode = AArch64CC::GE;
900 CondCode = AArch64CC::MI;
903 CondCode = AArch64CC::LS;
906 CondCode = AArch64CC::MI;
907 CondCode2 = AArch64CC::GT;
910 CondCode = AArch64CC::VC;
913 CondCode = AArch64CC::VS;
916 CondCode = AArch64CC::EQ;
917 CondCode2 = AArch64CC::VS;
920 CondCode = AArch64CC::HI;
923 CondCode = AArch64CC::PL;
927 CondCode = AArch64CC::LT;
931 CondCode = AArch64CC::LE;
935 CondCode = AArch64CC::NE;
940 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
941 /// CC usable with the vector instructions. Fewer operations are available
942 /// without a real NZCV register, so we have to use less efficient combinations
943 /// to get the same effect.
944 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
945 AArch64CC::CondCode &CondCode,
946 AArch64CC::CondCode &CondCode2,
951 // Mostly the scalar mappings work fine.
952 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
955 Invert = true; // Fallthrough
957 CondCode = AArch64CC::MI;
958 CondCode2 = AArch64CC::GE;
965 // All of the compare-mask comparisons are ordered, but we can switch
966 // between the two by a double inversion. E.g. ULE == !OGT.
968 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
973 static bool isLegalArithImmed(uint64_t C) {
974 // Matches AArch64DAGToDAGISel::SelectArithImmed().
975 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
978 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
979 SDLoc dl, SelectionDAG &DAG) {
980 EVT VT = LHS.getValueType();
982 if (VT.isFloatingPoint())
983 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
985 // The CMP instruction is just an alias for SUBS, and representing it as
986 // SUBS means that it's possible to get CSE with subtract operations.
987 // A later phase can perform the optimization of setting the destination
988 // register to WZR/XZR if it ends up being unused.
989 unsigned Opcode = AArch64ISD::SUBS;
991 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
992 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
993 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
994 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
995 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
996 // can be set differently by this operation. It comes down to whether
997 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
998 // everything is fine. If not then the optimization is wrong. Thus general
999 // comparisons are only valid if op2 != 0.
1001 // So, finally, the only LLVM-native comparisons that don't mention C and V
1002 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1003 // the absence of information about op2.
1004 Opcode = AArch64ISD::ADDS;
1005 RHS = RHS.getOperand(1);
1006 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1007 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1008 !isUnsignedIntSetCC(CC)) {
1009 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1010 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1011 // of the signed comparisons.
1012 Opcode = AArch64ISD::ANDS;
1013 RHS = LHS.getOperand(1);
1014 LHS = LHS.getOperand(0);
1017 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1021 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1022 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1023 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1024 EVT VT = RHS.getValueType();
1025 uint64_t C = RHSC->getZExtValue();
1026 if (!isLegalArithImmed(C)) {
1027 // Constant does not fit, try adjusting it by one?
1033 if ((VT == MVT::i32 && C != 0x80000000 &&
1034 isLegalArithImmed((uint32_t)(C - 1))) ||
1035 (VT == MVT::i64 && C != 0x80000000ULL &&
1036 isLegalArithImmed(C - 1ULL))) {
1037 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1038 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1039 RHS = DAG.getConstant(C, VT);
1044 if ((VT == MVT::i32 && C != 0 &&
1045 isLegalArithImmed((uint32_t)(C - 1))) ||
1046 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1047 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1048 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1049 RHS = DAG.getConstant(C, VT);
1054 if ((VT == MVT::i32 && C != 0x7fffffff &&
1055 isLegalArithImmed((uint32_t)(C + 1))) ||
1056 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1057 isLegalArithImmed(C + 1ULL))) {
1058 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1059 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1060 RHS = DAG.getConstant(C, VT);
1065 if ((VT == MVT::i32 && C != 0xffffffff &&
1066 isLegalArithImmed((uint32_t)(C + 1))) ||
1067 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1068 isLegalArithImmed(C + 1ULL))) {
1069 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1070 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1071 RHS = DAG.getConstant(C, VT);
1078 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1079 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1080 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1084 static std::pair<SDValue, SDValue>
1085 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1086 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1087 "Unsupported value type");
1088 SDValue Value, Overflow;
1090 SDValue LHS = Op.getOperand(0);
1091 SDValue RHS = Op.getOperand(1);
1093 switch (Op.getOpcode()) {
1095 llvm_unreachable("Unknown overflow instruction!");
1097 Opc = AArch64ISD::ADDS;
1101 Opc = AArch64ISD::ADDS;
1105 Opc = AArch64ISD::SUBS;
1109 Opc = AArch64ISD::SUBS;
1112 // Multiply needs a little bit extra work.
1116 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1117 if (Op.getValueType() == MVT::i32) {
1118 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1119 // For a 32 bit multiply with overflow check we want the instruction
1120 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1121 // need to generate the following pattern:
1122 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1123 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1124 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1125 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1126 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1127 DAG.getConstant(0, MVT::i64));
1128 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1129 // operation. We need to clear out the upper 32 bits, because we used a
1130 // widening multiply that wrote all 64 bits. In the end this should be a
1132 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1134 // The signed overflow check requires more than just a simple check for
1135 // any bit set in the upper 32 bits of the result. These bits could be
1136 // just the sign bits of a negative number. To perform the overflow
1137 // check we have to arithmetic shift right the 32nd bit of the result by
1138 // 31 bits. Then we compare the result to the upper 32 bits.
1139 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1140 DAG.getConstant(32, MVT::i64));
1141 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1142 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1143 DAG.getConstant(31, MVT::i64));
1144 // It is important that LowerBits is last, otherwise the arithmetic
1145 // shift will not be folded into the compare (SUBS).
1146 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1147 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1150 // The overflow check for unsigned multiply is easy. We only need to
1151 // check if any of the upper 32 bits are set. This can be done with a
1152 // CMP (shifted register). For that we need to generate the following
1154 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1155 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1156 DAG.getConstant(32, MVT::i64));
1157 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1159 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1160 UpperBits).getValue(1);
1164 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1165 // For the 64 bit multiply
1166 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1168 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1169 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1170 DAG.getConstant(63, MVT::i64));
1171 // It is important that LowerBits is last, otherwise the arithmetic
1172 // shift will not be folded into the compare (SUBS).
1173 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1174 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1177 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1178 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1180 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1181 UpperBits).getValue(1);
1188 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1190 // Emit the AArch64 operation with overflow check.
1191 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1192 Overflow = Value.getValue(1);
1194 return std::make_pair(Value, Overflow);
1197 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1198 RTLIB::Libcall Call) const {
1199 SmallVector<SDValue, 2> Ops;
1200 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1201 Ops.push_back(Op.getOperand(i));
1203 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1207 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1208 SDValue Sel = Op.getOperand(0);
1209 SDValue Other = Op.getOperand(1);
1211 // If neither operand is a SELECT_CC, give up.
1212 if (Sel.getOpcode() != ISD::SELECT_CC)
1213 std::swap(Sel, Other);
1214 if (Sel.getOpcode() != ISD::SELECT_CC)
1217 // The folding we want to perform is:
1218 // (xor x, (select_cc a, b, cc, 0, -1) )
1220 // (csel x, (xor x, -1), cc ...)
1222 // The latter will get matched to a CSINV instruction.
1224 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1225 SDValue LHS = Sel.getOperand(0);
1226 SDValue RHS = Sel.getOperand(1);
1227 SDValue TVal = Sel.getOperand(2);
1228 SDValue FVal = Sel.getOperand(3);
1231 // FIXME: This could be generalized to non-integer comparisons.
1232 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1235 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1236 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1238 // The the values aren't constants, this isn't the pattern we're looking for.
1239 if (!CFVal || !CTVal)
1242 // We can commute the SELECT_CC by inverting the condition. This
1243 // might be needed to make this fit into a CSINV pattern.
1244 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1245 std::swap(TVal, FVal);
1246 std::swap(CTVal, CFVal);
1247 CC = ISD::getSetCCInverse(CC, true);
1250 // If the constants line up, perform the transform!
1251 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1253 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1256 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1257 DAG.getConstant(-1ULL, Other.getValueType()));
1259 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1266 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1267 EVT VT = Op.getValueType();
1269 // Let legalize expand this if it isn't a legal type yet.
1270 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1273 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1276 bool ExtraOp = false;
1277 switch (Op.getOpcode()) {
1279 llvm_unreachable("Invalid code");
1281 Opc = AArch64ISD::ADDS;
1284 Opc = AArch64ISD::SUBS;
1287 Opc = AArch64ISD::ADCS;
1291 Opc = AArch64ISD::SBCS;
1297 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1298 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1302 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1303 // Let legalize expand this if it isn't a legal type yet.
1304 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1307 AArch64CC::CondCode CC;
1308 // The actual operation that sets the overflow or carry flag.
1309 SDValue Value, Overflow;
1310 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1312 // We use 0 and 1 as false and true values.
1313 SDValue TVal = DAG.getConstant(1, MVT::i32);
1314 SDValue FVal = DAG.getConstant(0, MVT::i32);
1316 // We use an inverted condition, because the conditional select is inverted
1317 // too. This will allow it to be selected to a single instruction:
1318 // CSINC Wd, WZR, WZR, invert(cond).
1319 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1320 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1323 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1324 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1327 // Prefetch operands are:
1328 // 1: Address to prefetch
1330 // 3: int locality (0 = no locality ... 3 = extreme locality)
1331 // 4: bool isDataCache
1332 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1334 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1335 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1336 // The data thing is not used.
1337 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1339 bool IsStream = !Locality;
1340 // When the locality number is set
1342 // The front-end should have filtered out the out-of-range values
1343 assert(Locality <= 3 && "Prefetch locality out-of-range");
1344 // The locality degree is the opposite of the cache speed.
1345 // Put the number the other way around.
1346 // The encoding starts at 0 for level 1
1347 Locality = 3 - Locality;
1350 // built the mask value encoding the expected behavior.
1351 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1352 (Locality << 1) | // Cache level bits
1353 (unsigned)IsStream; // Stream bit
1354 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1355 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1358 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1359 SelectionDAG &DAG) const {
1360 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1363 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1365 return LowerF128Call(Op, DAG, LC);
1368 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1369 SelectionDAG &DAG) const {
1370 if (Op.getOperand(0).getValueType() != MVT::f128) {
1371 // It's legal except when f128 is involved
1376 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1378 // FP_ROUND node has a second operand indicating whether it is known to be
1379 // precise. That doesn't take part in the LibCall so we can't directly use
1381 SDValue SrcVal = Op.getOperand(0);
1382 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1383 /*isSigned*/ false, SDLoc(Op)).first;
1386 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1387 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1388 // Any additional optimization in this function should be recorded
1389 // in the cost tables.
1390 EVT InVT = Op.getOperand(0).getValueType();
1391 EVT VT = Op.getValueType();
1393 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1396 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1398 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1401 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1403 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1404 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1407 // Type changing conversions are illegal.
1411 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1412 SelectionDAG &DAG) const {
1413 if (Op.getOperand(0).getValueType().isVector())
1414 return LowerVectorFP_TO_INT(Op, DAG);
1416 if (Op.getOperand(0).getValueType() != MVT::f128) {
1417 // It's legal except when f128 is involved
1422 if (Op.getOpcode() == ISD::FP_TO_SINT)
1423 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1425 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1427 SmallVector<SDValue, 2> Ops;
1428 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1429 Ops.push_back(Op.getOperand(i));
1431 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1435 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1436 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1437 // Any additional optimization in this function should be recorded
1438 // in the cost tables.
1439 EVT VT = Op.getValueType();
1441 SDValue In = Op.getOperand(0);
1442 EVT InVT = In.getValueType();
1444 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1446 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1447 InVT.getVectorNumElements());
1448 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1449 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1452 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1454 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1455 EVT CastVT = VT.changeVectorElementTypeToInteger();
1456 In = DAG.getNode(CastOpc, dl, CastVT, In);
1457 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1463 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1464 SelectionDAG &DAG) const {
1465 if (Op.getValueType().isVector())
1466 return LowerVectorINT_TO_FP(Op, DAG);
1468 // i128 conversions are libcalls.
1469 if (Op.getOperand(0).getValueType() == MVT::i128)
1472 // Other conversions are legal, unless it's to the completely software-based
1474 if (Op.getValueType() != MVT::f128)
1478 if (Op.getOpcode() == ISD::SINT_TO_FP)
1479 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1481 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1483 return LowerF128Call(Op, DAG, LC);
1486 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1487 SelectionDAG &DAG) const {
1488 // For iOS, we want to call an alternative entry point: __sincos_stret,
1489 // which returns the values in two S / D registers.
1491 SDValue Arg = Op.getOperand(0);
1492 EVT ArgVT = Arg.getValueType();
1493 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1500 Entry.isSExt = false;
1501 Entry.isZExt = false;
1502 Args.push_back(Entry);
1504 const char *LibcallName =
1505 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1506 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1508 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1509 TargetLowering::CallLoweringInfo CLI(DAG);
1510 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1511 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1513 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1514 return CallResult.first;
1517 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1518 if (Op.getValueType() != MVT::f16)
1521 assert(Op.getOperand(0).getValueType() == MVT::i16);
1524 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1525 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1527 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1528 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1533 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1534 SelectionDAG &DAG) const {
1535 switch (Op.getOpcode()) {
1537 llvm_unreachable("unimplemented operand");
1540 return LowerBITCAST(Op, DAG);
1541 case ISD::GlobalAddress:
1542 return LowerGlobalAddress(Op, DAG);
1543 case ISD::GlobalTLSAddress:
1544 return LowerGlobalTLSAddress(Op, DAG);
1546 return LowerSETCC(Op, DAG);
1548 return LowerBR_CC(Op, DAG);
1550 return LowerSELECT(Op, DAG);
1551 case ISD::SELECT_CC:
1552 return LowerSELECT_CC(Op, DAG);
1553 case ISD::JumpTable:
1554 return LowerJumpTable(Op, DAG);
1555 case ISD::ConstantPool:
1556 return LowerConstantPool(Op, DAG);
1557 case ISD::BlockAddress:
1558 return LowerBlockAddress(Op, DAG);
1560 return LowerVASTART(Op, DAG);
1562 return LowerVACOPY(Op, DAG);
1564 return LowerVAARG(Op, DAG);
1569 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1576 return LowerXALUO(Op, DAG);
1578 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1580 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1582 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1584 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1586 return LowerFP_ROUND(Op, DAG);
1587 case ISD::FP_EXTEND:
1588 return LowerFP_EXTEND(Op, DAG);
1589 case ISD::FRAMEADDR:
1590 return LowerFRAMEADDR(Op, DAG);
1591 case ISD::RETURNADDR:
1592 return LowerRETURNADDR(Op, DAG);
1593 case ISD::INSERT_VECTOR_ELT:
1594 return LowerINSERT_VECTOR_ELT(Op, DAG);
1595 case ISD::EXTRACT_VECTOR_ELT:
1596 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1597 case ISD::BUILD_VECTOR:
1598 return LowerBUILD_VECTOR(Op, DAG);
1599 case ISD::VECTOR_SHUFFLE:
1600 return LowerVECTOR_SHUFFLE(Op, DAG);
1601 case ISD::EXTRACT_SUBVECTOR:
1602 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1606 return LowerVectorSRA_SRL_SHL(Op, DAG);
1607 case ISD::SHL_PARTS:
1608 return LowerShiftLeftParts(Op, DAG);
1609 case ISD::SRL_PARTS:
1610 case ISD::SRA_PARTS:
1611 return LowerShiftRightParts(Op, DAG);
1613 return LowerCTPOP(Op, DAG);
1614 case ISD::FCOPYSIGN:
1615 return LowerFCOPYSIGN(Op, DAG);
1617 return LowerVectorAND(Op, DAG);
1619 return LowerVectorOR(Op, DAG);
1621 return LowerXOR(Op, DAG);
1623 return LowerPREFETCH(Op, DAG);
1624 case ISD::SINT_TO_FP:
1625 case ISD::UINT_TO_FP:
1626 return LowerINT_TO_FP(Op, DAG);
1627 case ISD::FP_TO_SINT:
1628 case ISD::FP_TO_UINT:
1629 return LowerFP_TO_INT(Op, DAG);
1631 return LowerFSINCOS(Op, DAG);
1635 /// getFunctionAlignment - Return the Log2 alignment of this function.
1636 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1640 //===----------------------------------------------------------------------===//
1641 // Calling Convention Implementation
1642 //===----------------------------------------------------------------------===//
1644 #include "AArch64GenCallingConv.inc"
1646 /// Selects the correct CCAssignFn for a the given CallingConvention
1648 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1649 bool IsVarArg) const {
1652 llvm_unreachable("Unsupported calling convention.");
1653 case CallingConv::WebKit_JS:
1654 return CC_AArch64_WebKit_JS;
1655 case CallingConv::C:
1656 case CallingConv::Fast:
1657 if (!Subtarget->isTargetDarwin())
1658 return CC_AArch64_AAPCS;
1659 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1663 SDValue AArch64TargetLowering::LowerFormalArguments(
1664 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1665 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1666 SmallVectorImpl<SDValue> &InVals) const {
1667 MachineFunction &MF = DAG.getMachineFunction();
1668 MachineFrameInfo *MFI = MF.getFrameInfo();
1670 // Assign locations to all of the incoming arguments.
1671 SmallVector<CCValAssign, 16> ArgLocs;
1672 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1673 getTargetMachine(), ArgLocs, *DAG.getContext());
1675 // At this point, Ins[].VT may already be promoted to i32. To correctly
1676 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1677 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1678 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1679 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1681 unsigned NumArgs = Ins.size();
1682 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1683 unsigned CurArgIdx = 0;
1684 for (unsigned i = 0; i != NumArgs; ++i) {
1685 MVT ValVT = Ins[i].VT;
1686 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1687 CurArgIdx = Ins[i].OrigArgIndex;
1689 // Get type of the original argument.
1690 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1691 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1692 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1693 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1695 else if (ActualMVT == MVT::i16)
1698 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1700 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1701 assert(!Res && "Call operand has unhandled type");
1704 assert(ArgLocs.size() == Ins.size());
1705 SmallVector<SDValue, 16> ArgValues;
1706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1707 CCValAssign &VA = ArgLocs[i];
1709 if (Ins[i].Flags.isByVal()) {
1710 // Byval is used for HFAs in the PCS, but the system should work in a
1711 // non-compliant manner for larger structs.
1712 EVT PtrTy = getPointerTy();
1713 int Size = Ins[i].Flags.getByValSize();
1714 unsigned NumRegs = (Size + 7) / 8;
1716 // FIXME: This works on big-endian for composite byvals, which are the common
1717 // case. It should also work for fundamental types too.
1719 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1720 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1721 InVals.push_back(FrameIdxN);
1726 if (VA.isRegLoc()) {
1727 // Arguments stored in registers.
1728 EVT RegVT = VA.getLocVT();
1731 const TargetRegisterClass *RC;
1733 if (RegVT == MVT::i32)
1734 RC = &AArch64::GPR32RegClass;
1735 else if (RegVT == MVT::i64)
1736 RC = &AArch64::GPR64RegClass;
1737 else if (RegVT == MVT::f16)
1738 RC = &AArch64::FPR16RegClass;
1739 else if (RegVT == MVT::f32)
1740 RC = &AArch64::FPR32RegClass;
1741 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1742 RC = &AArch64::FPR64RegClass;
1743 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1744 RC = &AArch64::FPR128RegClass;
1746 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1748 // Transform the arguments in physical registers into virtual ones.
1749 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1750 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1752 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1753 // to 64 bits. Insert an assert[sz]ext to capture this, then
1754 // truncate to the right size.
1755 switch (VA.getLocInfo()) {
1757 llvm_unreachable("Unknown loc info!");
1758 case CCValAssign::Full:
1760 case CCValAssign::BCvt:
1761 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1763 case CCValAssign::AExt:
1764 case CCValAssign::SExt:
1765 case CCValAssign::ZExt:
1766 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1767 // nodes after our lowering.
1768 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1772 InVals.push_back(ArgValue);
1774 } else { // VA.isRegLoc()
1775 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1776 unsigned ArgOffset = VA.getLocMemOffset();
1777 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1779 uint32_t BEAlign = 0;
1780 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1781 BEAlign = 8 - ArgSize;
1783 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1785 // Create load nodes to retrieve arguments from the stack.
1786 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1789 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1790 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1791 MVT MemVT = VA.getValVT();
1793 switch (VA.getLocInfo()) {
1796 case CCValAssign::BCvt:
1797 MemVT = VA.getLocVT();
1799 case CCValAssign::SExt:
1800 ExtType = ISD::SEXTLOAD;
1802 case CCValAssign::ZExt:
1803 ExtType = ISD::ZEXTLOAD;
1805 case CCValAssign::AExt:
1806 ExtType = ISD::EXTLOAD;
1810 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1811 MachinePointerInfo::getFixedStack(FI),
1812 MemVT, false, false, false, nullptr);
1814 InVals.push_back(ArgValue);
1820 if (!Subtarget->isTargetDarwin()) {
1821 // The AAPCS variadic function ABI is identical to the non-variadic
1822 // one. As a result there may be more arguments in registers and we should
1823 // save them for future reference.
1824 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1827 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1828 // This will point to the next argument passed via stack.
1829 unsigned StackOffset = CCInfo.getNextStackOffset();
1830 // We currently pass all varargs at 8-byte alignment.
1831 StackOffset = ((StackOffset + 7) & ~7);
1832 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1835 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1836 unsigned StackArgSize = CCInfo.getNextStackOffset();
1837 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1838 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1839 // This is a non-standard ABI so by fiat I say we're allowed to make full
1840 // use of the stack area to be popped, which must be aligned to 16 bytes in
1842 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1844 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1845 // a multiple of 16.
1846 FuncInfo->setArgumentStackToRestore(StackArgSize);
1848 // This realignment carries over to the available bytes below. Our own
1849 // callers will guarantee the space is free by giving an aligned value to
1852 // Even if we're not expected to free up the space, it's useful to know how
1853 // much is there while considering tail calls (because we can reuse it).
1854 FuncInfo->setBytesInStackArgArea(StackArgSize);
1859 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1860 SelectionDAG &DAG, SDLoc DL,
1861 SDValue &Chain) const {
1862 MachineFunction &MF = DAG.getMachineFunction();
1863 MachineFrameInfo *MFI = MF.getFrameInfo();
1864 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1866 SmallVector<SDValue, 8> MemOps;
1868 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1869 AArch64::X3, AArch64::X4, AArch64::X5,
1870 AArch64::X6, AArch64::X7 };
1871 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1872 unsigned FirstVariadicGPR =
1873 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1875 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1877 if (GPRSaveSize != 0) {
1878 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1880 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1882 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1883 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1884 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1886 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1887 MachinePointerInfo::getStack(i * 8), false, false, 0);
1888 MemOps.push_back(Store);
1889 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1890 DAG.getConstant(8, getPointerTy()));
1893 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1894 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1896 if (Subtarget->hasFPARMv8()) {
1897 static const MCPhysReg FPRArgRegs[] = {
1898 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1899 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1900 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1901 unsigned FirstVariadicFPR =
1902 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1904 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1906 if (FPRSaveSize != 0) {
1907 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1909 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1911 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1912 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1913 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1916 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1917 MachinePointerInfo::getStack(i * 16), false, false, 0);
1918 MemOps.push_back(Store);
1919 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1920 DAG.getConstant(16, getPointerTy()));
1923 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1924 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1927 if (!MemOps.empty()) {
1928 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1932 /// LowerCallResult - Lower the result values of a call into the
1933 /// appropriate copies out of appropriate physical registers.
1934 SDValue AArch64TargetLowering::LowerCallResult(
1935 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1936 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1937 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1938 SDValue ThisVal) const {
1939 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1940 ? RetCC_AArch64_WebKit_JS
1941 : RetCC_AArch64_AAPCS;
1942 // Assign locations to each value returned by this call.
1943 SmallVector<CCValAssign, 16> RVLocs;
1944 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1945 getTargetMachine(), RVLocs, *DAG.getContext());
1946 CCInfo.AnalyzeCallResult(Ins, RetCC);
1948 // Copy all of the result registers out of their specified physreg.
1949 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1950 CCValAssign VA = RVLocs[i];
1952 // Pass 'this' value directly from the argument to return value, to avoid
1953 // reg unit interference
1954 if (i == 0 && isThisReturn) {
1955 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1956 "unexpected return calling convention register assignment");
1957 InVals.push_back(ThisVal);
1962 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1963 Chain = Val.getValue(1);
1964 InFlag = Val.getValue(2);
1966 switch (VA.getLocInfo()) {
1968 llvm_unreachable("Unknown loc info!");
1969 case CCValAssign::Full:
1971 case CCValAssign::BCvt:
1972 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1976 InVals.push_back(Val);
1982 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1983 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1984 bool isCalleeStructRet, bool isCallerStructRet,
1985 const SmallVectorImpl<ISD::OutputArg> &Outs,
1986 const SmallVectorImpl<SDValue> &OutVals,
1987 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1988 // For CallingConv::C this function knows whether the ABI needs
1989 // changing. That's not true for other conventions so they will have to opt in
1991 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1994 const MachineFunction &MF = DAG.getMachineFunction();
1995 const Function *CallerF = MF.getFunction();
1996 CallingConv::ID CallerCC = CallerF->getCallingConv();
1997 bool CCMatch = CallerCC == CalleeCC;
1999 // Byval parameters hand the function a pointer directly into the stack area
2000 // we want to reuse during a tail call. Working around this *is* possible (see
2001 // X86) but less efficient and uglier in LowerCall.
2002 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2003 e = CallerF->arg_end();
2005 if (i->hasByValAttr())
2008 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2009 if (IsTailCallConvention(CalleeCC) && CCMatch)
2014 // Now we search for cases where we can use a tail call without changing the
2015 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2018 // I want anyone implementing a new calling convention to think long and hard
2019 // about this assert.
2020 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2021 "Unexpected variadic calling convention");
2023 if (isVarArg && !Outs.empty()) {
2024 // At least two cases here: if caller is fastcc then we can't have any
2025 // memory arguments (we'd be expected to clean up the stack afterwards). If
2026 // caller is C then we could potentially use its argument area.
2028 // FIXME: for now we take the most conservative of these in both cases:
2029 // disallow all variadic memory operands.
2030 SmallVector<CCValAssign, 16> ArgLocs;
2031 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2032 getTargetMachine(), ArgLocs, *DAG.getContext());
2034 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2035 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2036 if (!ArgLocs[i].isRegLoc())
2040 // If the calling conventions do not match, then we'd better make sure the
2041 // results are returned in the same way as what the caller expects.
2043 SmallVector<CCValAssign, 16> RVLocs1;
2044 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2045 getTargetMachine(), RVLocs1, *DAG.getContext());
2046 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2048 SmallVector<CCValAssign, 16> RVLocs2;
2049 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2050 getTargetMachine(), RVLocs2, *DAG.getContext());
2051 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2053 if (RVLocs1.size() != RVLocs2.size())
2055 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2056 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2058 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2060 if (RVLocs1[i].isRegLoc()) {
2061 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2064 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2070 // Nothing more to check if the callee is taking no arguments
2074 SmallVector<CCValAssign, 16> ArgLocs;
2075 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2076 getTargetMachine(), ArgLocs, *DAG.getContext());
2078 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2080 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2082 // If the stack arguments for this call would fit into our own save area then
2083 // the call can be made tail.
2084 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2087 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2089 MachineFrameInfo *MFI,
2090 int ClobberedFI) const {
2091 SmallVector<SDValue, 8> ArgChains;
2092 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2093 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2095 // Include the original chain at the beginning of the list. When this is
2096 // used by target LowerCall hooks, this helps legalize find the
2097 // CALLSEQ_BEGIN node.
2098 ArgChains.push_back(Chain);
2100 // Add a chain value for each stack argument corresponding
2101 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2102 UE = DAG.getEntryNode().getNode()->use_end();
2104 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2105 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2106 if (FI->getIndex() < 0) {
2107 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2108 int64_t InLastByte = InFirstByte;
2109 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2111 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2112 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2113 ArgChains.push_back(SDValue(L, 1));
2116 // Build a tokenfactor for all the chains.
2117 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2120 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2121 bool TailCallOpt) const {
2122 return CallCC == CallingConv::Fast && TailCallOpt;
2125 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2126 return CallCC == CallingConv::Fast;
2129 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2130 /// and add input and output parameter nodes.
2132 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2133 SmallVectorImpl<SDValue> &InVals) const {
2134 SelectionDAG &DAG = CLI.DAG;
2136 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2137 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2138 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2139 SDValue Chain = CLI.Chain;
2140 SDValue Callee = CLI.Callee;
2141 bool &IsTailCall = CLI.IsTailCall;
2142 CallingConv::ID CallConv = CLI.CallConv;
2143 bool IsVarArg = CLI.IsVarArg;
2145 MachineFunction &MF = DAG.getMachineFunction();
2146 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2147 bool IsThisReturn = false;
2149 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2150 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2151 bool IsSibCall = false;
2154 // Check if it's really possible to do a tail call.
2155 IsTailCall = isEligibleForTailCallOptimization(
2156 Callee, CallConv, IsVarArg, IsStructRet,
2157 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2158 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2159 report_fatal_error("failed to perform tail call elimination on a call "
2160 "site marked musttail");
2162 // A sibling call is one where we're under the usual C ABI and not planning
2163 // to change that but can still do a tail call:
2164 if (!TailCallOpt && IsTailCall)
2171 // Analyze operands of the call, assigning locations to each operand.
2172 SmallVector<CCValAssign, 16> ArgLocs;
2173 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2174 getTargetMachine(), ArgLocs, *DAG.getContext());
2177 // Handle fixed and variable vector arguments differently.
2178 // Variable vector arguments always go into memory.
2179 unsigned NumArgs = Outs.size();
2181 for (unsigned i = 0; i != NumArgs; ++i) {
2182 MVT ArgVT = Outs[i].VT;
2183 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2184 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2185 /*IsVarArg=*/ !Outs[i].IsFixed);
2186 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2187 assert(!Res && "Call operand has unhandled type");
2191 // At this point, Outs[].VT may already be promoted to i32. To correctly
2192 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2193 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2194 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2195 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2197 unsigned NumArgs = Outs.size();
2198 for (unsigned i = 0; i != NumArgs; ++i) {
2199 MVT ValVT = Outs[i].VT;
2200 // Get type of the original argument.
2201 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2202 /*AllowUnknown*/ true);
2203 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2204 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2205 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2206 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2208 else if (ActualMVT == MVT::i16)
2211 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2212 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2213 assert(!Res && "Call operand has unhandled type");
2218 // Get a count of how many bytes are to be pushed on the stack.
2219 unsigned NumBytes = CCInfo.getNextStackOffset();
2222 // Since we're not changing the ABI to make this a tail call, the memory
2223 // operands are already available in the caller's incoming argument space.
2227 // FPDiff is the byte offset of the call's argument area from the callee's.
2228 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2229 // by this amount for a tail call. In a sibling call it must be 0 because the
2230 // caller will deallocate the entire stack and the callee still expects its
2231 // arguments to begin at SP+0. Completely unused for non-tail calls.
2234 if (IsTailCall && !IsSibCall) {
2235 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2237 // Since callee will pop argument stack as a tail call, we must keep the
2238 // popped size 16-byte aligned.
2239 NumBytes = RoundUpToAlignment(NumBytes, 16);
2241 // FPDiff will be negative if this tail call requires more space than we
2242 // would automatically have in our incoming argument space. Positive if we
2243 // can actually shrink the stack.
2244 FPDiff = NumReusableBytes - NumBytes;
2246 // The stack pointer must be 16-byte aligned at all times it's used for a
2247 // memory operation, which in practice means at *all* times and in
2248 // particular across call boundaries. Therefore our own arguments started at
2249 // a 16-byte aligned SP and the delta applied for the tail call should
2250 // satisfy the same constraint.
2251 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2254 // Adjust the stack pointer for the new arguments...
2255 // These operations are automatically eliminated by the prolog/epilog pass
2258 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2260 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2262 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2263 SmallVector<SDValue, 8> MemOpChains;
2265 // Walk the register/memloc assignments, inserting copies/loads.
2266 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2267 ++i, ++realArgIdx) {
2268 CCValAssign &VA = ArgLocs[i];
2269 SDValue Arg = OutVals[realArgIdx];
2270 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2272 // Promote the value if needed.
2273 switch (VA.getLocInfo()) {
2275 llvm_unreachable("Unknown loc info!");
2276 case CCValAssign::Full:
2278 case CCValAssign::SExt:
2279 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2281 case CCValAssign::ZExt:
2282 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2284 case CCValAssign::AExt:
2285 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2286 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2287 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2288 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2290 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2292 case CCValAssign::BCvt:
2293 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2295 case CCValAssign::FPExt:
2296 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2300 if (VA.isRegLoc()) {
2301 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2302 assert(VA.getLocVT() == MVT::i64 &&
2303 "unexpected calling convention register assignment");
2304 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2305 "unexpected use of 'returned'");
2306 IsThisReturn = true;
2308 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2310 assert(VA.isMemLoc());
2313 MachinePointerInfo DstInfo;
2315 // FIXME: This works on big-endian for composite byvals, which are the
2316 // common case. It should also work for fundamental types too.
2317 uint32_t BEAlign = 0;
2318 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2319 : VA.getLocVT().getSizeInBits();
2320 OpSize = (OpSize + 7) / 8;
2321 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2323 BEAlign = 8 - OpSize;
2325 unsigned LocMemOffset = VA.getLocMemOffset();
2326 int32_t Offset = LocMemOffset + BEAlign;
2327 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2328 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2331 Offset = Offset + FPDiff;
2332 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2334 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2335 DstInfo = MachinePointerInfo::getFixedStack(FI);
2337 // Make sure any stack arguments overlapping with where we're storing
2338 // are loaded before this eventual operation. Otherwise they'll be
2340 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2342 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2344 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2345 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2348 if (Outs[i].Flags.isByVal()) {
2350 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2351 SDValue Cpy = DAG.getMemcpy(
2352 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2353 /*isVolatile = */ false,
2354 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2356 MemOpChains.push_back(Cpy);
2358 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2359 // promoted to a legal register type i32, we should truncate Arg back to
2361 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2362 VA.getValVT() == MVT::i16)
2363 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2366 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2367 MemOpChains.push_back(Store);
2372 if (!MemOpChains.empty())
2373 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2375 // Build a sequence of copy-to-reg nodes chained together with token chain
2376 // and flag operands which copy the outgoing args into the appropriate regs.
2378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2379 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2380 RegsToPass[i].second, InFlag);
2381 InFlag = Chain.getValue(1);
2384 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2385 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2386 // node so that legalize doesn't hack it.
2387 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2388 Subtarget->isTargetMachO()) {
2389 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2390 const GlobalValue *GV = G->getGlobal();
2391 bool InternalLinkage = GV->hasInternalLinkage();
2392 if (InternalLinkage)
2393 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2395 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2397 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2399 } else if (ExternalSymbolSDNode *S =
2400 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2401 const char *Sym = S->getSymbol();
2403 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2404 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2406 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2407 const GlobalValue *GV = G->getGlobal();
2408 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2409 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2410 const char *Sym = S->getSymbol();
2411 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2414 // We don't usually want to end the call-sequence here because we would tidy
2415 // the frame up *after* the call, however in the ABI-changing tail-call case
2416 // we've carefully laid out the parameters so that when sp is reset they'll be
2417 // in the correct location.
2418 if (IsTailCall && !IsSibCall) {
2419 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2420 DAG.getIntPtrConstant(0, true), InFlag, DL);
2421 InFlag = Chain.getValue(1);
2424 std::vector<SDValue> Ops;
2425 Ops.push_back(Chain);
2426 Ops.push_back(Callee);
2429 // Each tail call may have to adjust the stack by a different amount, so
2430 // this information must travel along with the operation for eventual
2431 // consumption by emitEpilogue.
2432 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2435 // Add argument registers to the end of the list so that they are known live
2437 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2438 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2439 RegsToPass[i].second.getValueType()));
2441 // Add a register mask operand representing the call-preserved registers.
2442 const uint32_t *Mask;
2443 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2444 const AArch64RegisterInfo *ARI =
2445 static_cast<const AArch64RegisterInfo *>(TRI);
2447 // For 'this' returns, use the X0-preserving mask if applicable
2448 Mask = ARI->getThisReturnPreservedMask(CallConv);
2450 IsThisReturn = false;
2451 Mask = ARI->getCallPreservedMask(CallConv);
2454 Mask = ARI->getCallPreservedMask(CallConv);
2456 assert(Mask && "Missing call preserved mask for calling convention");
2457 Ops.push_back(DAG.getRegisterMask(Mask));
2459 if (InFlag.getNode())
2460 Ops.push_back(InFlag);
2462 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2464 // If we're doing a tall call, use a TC_RETURN here rather than an
2465 // actual call instruction.
2467 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2469 // Returns a chain and a flag for retval copy to use.
2470 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2471 InFlag = Chain.getValue(1);
2473 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2474 ? RoundUpToAlignment(NumBytes, 16)
2477 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2478 DAG.getIntPtrConstant(CalleePopBytes, true),
2481 InFlag = Chain.getValue(1);
2483 // Handle result values, copying them out of physregs into vregs that we
2485 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2486 InVals, IsThisReturn,
2487 IsThisReturn ? OutVals[0] : SDValue());
2490 bool AArch64TargetLowering::CanLowerReturn(
2491 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2492 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2493 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2494 ? RetCC_AArch64_WebKit_JS
2495 : RetCC_AArch64_AAPCS;
2496 SmallVector<CCValAssign, 16> RVLocs;
2497 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2498 return CCInfo.CheckReturn(Outs, RetCC);
2502 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2504 const SmallVectorImpl<ISD::OutputArg> &Outs,
2505 const SmallVectorImpl<SDValue> &OutVals,
2506 SDLoc DL, SelectionDAG &DAG) const {
2507 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2508 ? RetCC_AArch64_WebKit_JS
2509 : RetCC_AArch64_AAPCS;
2510 SmallVector<CCValAssign, 16> RVLocs;
2511 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2512 getTargetMachine(), RVLocs, *DAG.getContext());
2513 CCInfo.AnalyzeReturn(Outs, RetCC);
2515 // Copy the result values into the output registers.
2517 SmallVector<SDValue, 4> RetOps(1, Chain);
2518 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2519 ++i, ++realRVLocIdx) {
2520 CCValAssign &VA = RVLocs[i];
2521 assert(VA.isRegLoc() && "Can only return in registers!");
2522 SDValue Arg = OutVals[realRVLocIdx];
2524 switch (VA.getLocInfo()) {
2526 llvm_unreachable("Unknown loc info!");
2527 case CCValAssign::Full:
2528 if (Outs[i].ArgVT == MVT::i1) {
2529 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2530 // value. This is strictly redundant on Darwin (which uses "zeroext
2531 // i1"), but will be optimised out before ISel.
2532 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2533 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2536 case CCValAssign::BCvt:
2537 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2541 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2542 Flag = Chain.getValue(1);
2543 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2546 RetOps[0] = Chain; // Update chain.
2548 // Add the flag if we have it.
2550 RetOps.push_back(Flag);
2552 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2555 //===----------------------------------------------------------------------===//
2556 // Other Lowering Code
2557 //===----------------------------------------------------------------------===//
2559 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2560 SelectionDAG &DAG) const {
2561 EVT PtrVT = getPointerTy();
2563 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2564 unsigned char OpFlags =
2565 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2567 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2568 "unexpected offset in global node");
2570 // This also catched the large code model case for Darwin.
2571 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2572 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2573 // FIXME: Once remat is capable of dealing with instructions with register
2574 // operands, expand this into two nodes instead of using a wrapper node.
2575 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2578 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2579 const unsigned char MO_NC = AArch64II::MO_NC;
2581 AArch64ISD::WrapperLarge, DL, PtrVT,
2582 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2583 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2584 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2585 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2587 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2588 // the only correct model on Darwin.
2589 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2590 OpFlags | AArch64II::MO_PAGE);
2591 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2592 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2594 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2595 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2599 /// \brief Convert a TLS address reference into the correct sequence of loads
2600 /// and calls to compute the variable's address (for Darwin, currently) and
2601 /// return an SDValue containing the final node.
2603 /// Darwin only has one TLS scheme which must be capable of dealing with the
2604 /// fully general situation, in the worst case. This means:
2605 /// + "extern __thread" declaration.
2606 /// + Defined in a possibly unknown dynamic library.
2608 /// The general system is that each __thread variable has a [3 x i64] descriptor
2609 /// which contains information used by the runtime to calculate the address. The
2610 /// only part of this the compiler needs to know about is the first xword, which
2611 /// contains a function pointer that must be called with the address of the
2612 /// entire descriptor in "x0".
2614 /// Since this descriptor may be in a different unit, in general even the
2615 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2617 /// adrp x0, _var@TLVPPAGE
2618 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2619 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2620 /// ; the function pointer
2621 /// blr x1 ; Uses descriptor address in x0
2622 /// ; Address of _var is now in x0.
2624 /// If the address of _var's descriptor *is* known to the linker, then it can
2625 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2626 /// a slight efficiency gain.
2628 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2629 SelectionDAG &DAG) const {
2630 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2633 MVT PtrVT = getPointerTy();
2634 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2637 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2638 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2640 // The first entry in the descriptor is a function pointer that we must call
2641 // to obtain the address of the variable.
2642 SDValue Chain = DAG.getEntryNode();
2643 SDValue FuncTLVGet =
2644 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2645 false, true, true, 8);
2646 Chain = FuncTLVGet.getValue(1);
2648 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2649 MFI->setAdjustsStack(true);
2651 // TLS calls preserve all registers except those that absolutely must be
2652 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2654 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2655 const AArch64RegisterInfo *ARI =
2656 static_cast<const AArch64RegisterInfo *>(TRI);
2657 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2659 // Finally, we can make the call. This is just a degenerate version of a
2660 // normal AArch64 call node: x0 takes the address of the descriptor, and
2661 // returns the address of the variable in this thread.
2662 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2664 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2665 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2666 DAG.getRegisterMask(Mask), Chain.getValue(1));
2667 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2670 /// When accessing thread-local variables under either the general-dynamic or
2671 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2672 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2673 /// is a function pointer to carry out the resolution. This function takes the
2674 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2675 /// other registers (except LR, NZCV) are preserved.
2677 /// Thus, the ideal call sequence on AArch64 is:
2679 /// adrp x0, :tlsdesc:thread_var
2680 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2681 /// add x0, x0, :tlsdesc_lo12:thread_var
2682 /// .tlsdesccall thread_var
2684 /// (TPIDR_EL0 offset now in x0).
2686 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2687 /// relocation to help the linker relax this sequence if it turns out to be too
2690 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2692 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2693 SDValue DescAddr, SDLoc DL,
2694 SelectionDAG &DAG) const {
2695 EVT PtrVT = getPointerTy();
2697 // The function we need to call is simply the first entry in the GOT for this
2698 // descriptor, load it in preparation.
2699 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2701 // TLS calls preserve all registers except those that absolutely must be
2702 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2704 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2705 const AArch64RegisterInfo *ARI =
2706 static_cast<const AArch64RegisterInfo *>(TRI);
2707 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2709 // The function takes only one argument: the address of the descriptor itself
2711 SDValue Glue, Chain;
2712 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2713 Glue = Chain.getValue(1);
2715 // We're now ready to populate the argument list, as with a normal call:
2716 SmallVector<SDValue, 6> Ops;
2717 Ops.push_back(Chain);
2718 Ops.push_back(Func);
2719 Ops.push_back(SymAddr);
2720 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2721 Ops.push_back(DAG.getRegisterMask(Mask));
2722 Ops.push_back(Glue);
2724 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2725 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2726 Glue = Chain.getValue(1);
2728 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2732 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2733 SelectionDAG &DAG) const {
2734 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2735 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2736 "ELF TLS only supported in small memory model");
2737 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2739 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2742 EVT PtrVT = getPointerTy();
2744 const GlobalValue *GV = GA->getGlobal();
2746 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2748 if (Model == TLSModel::LocalExec) {
2749 SDValue HiVar = DAG.getTargetGlobalAddress(
2750 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2751 SDValue LoVar = DAG.getTargetGlobalAddress(
2753 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2755 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2756 DAG.getTargetConstant(16, MVT::i32)),
2758 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2759 DAG.getTargetConstant(0, MVT::i32)),
2761 } else if (Model == TLSModel::InitialExec) {
2762 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2763 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2764 } else if (Model == TLSModel::LocalDynamic) {
2765 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2766 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2767 // the beginning of the module's TLS region, followed by a DTPREL offset
2770 // These accesses will need deduplicating if there's more than one.
2771 AArch64FunctionInfo *MFI =
2772 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2773 MFI->incNumLocalDynamicTLSAccesses();
2775 // Accesses used in this sequence go via the TLS descriptor which lives in
2776 // the GOT. Prepare an address we can use to handle this.
2777 SDValue HiDesc = DAG.getTargetExternalSymbol(
2778 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2779 SDValue LoDesc = DAG.getTargetExternalSymbol(
2780 "_TLS_MODULE_BASE_", PtrVT,
2781 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2783 // First argument to the descriptor call is the address of the descriptor
2785 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2786 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2788 // The call needs a relocation too for linker relaxation. It doesn't make
2789 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2791 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2794 // Now we can calculate the offset from TPIDR_EL0 to this module's
2795 // thread-local area.
2796 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2798 // Now use :dtprel_whatever: operations to calculate this variable's offset
2799 // in its thread-storage area.
2800 SDValue HiVar = DAG.getTargetGlobalAddress(
2801 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2802 SDValue LoVar = DAG.getTargetGlobalAddress(
2803 GV, DL, MVT::i64, 0,
2804 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2807 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2808 DAG.getTargetConstant(16, MVT::i32)),
2811 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2812 DAG.getTargetConstant(0, MVT::i32)),
2815 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2816 } else if (Model == TLSModel::GeneralDynamic) {
2817 // Accesses used in this sequence go via the TLS descriptor which lives in
2818 // the GOT. Prepare an address we can use to handle this.
2819 SDValue HiDesc = DAG.getTargetGlobalAddress(
2820 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2821 SDValue LoDesc = DAG.getTargetGlobalAddress(
2823 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2825 // First argument to the descriptor call is the address of the descriptor
2827 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2828 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2830 // The call needs a relocation too for linker relaxation. It doesn't make
2831 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2834 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2836 // Finally we can make a call to calculate the offset from tpidr_el0.
2837 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2839 llvm_unreachable("Unsupported ELF TLS access model");
2841 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2844 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2845 SelectionDAG &DAG) const {
2846 if (Subtarget->isTargetDarwin())
2847 return LowerDarwinGlobalTLSAddress(Op, DAG);
2848 else if (Subtarget->isTargetELF())
2849 return LowerELFGlobalTLSAddress(Op, DAG);
2851 llvm_unreachable("Unexpected platform trying to use TLS");
2853 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2854 SDValue Chain = Op.getOperand(0);
2855 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2856 SDValue LHS = Op.getOperand(2);
2857 SDValue RHS = Op.getOperand(3);
2858 SDValue Dest = Op.getOperand(4);
2861 // Handle f128 first, since lowering it will result in comparing the return
2862 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2863 // is expecting to deal with.
2864 if (LHS.getValueType() == MVT::f128) {
2865 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2867 // If softenSetCCOperands returned a scalar, we need to compare the result
2868 // against zero to select between true and false values.
2869 if (!RHS.getNode()) {
2870 RHS = DAG.getConstant(0, LHS.getValueType());
2875 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2877 unsigned Opc = LHS.getOpcode();
2878 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2879 cast<ConstantSDNode>(RHS)->isOne() &&
2880 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2881 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2882 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2883 "Unexpected condition code.");
2884 // Only lower legal XALUO ops.
2885 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2888 // The actual operation with overflow check.
2889 AArch64CC::CondCode OFCC;
2890 SDValue Value, Overflow;
2891 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2893 if (CC == ISD::SETNE)
2894 OFCC = getInvertedCondCode(OFCC);
2895 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2897 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2901 if (LHS.getValueType().isInteger()) {
2902 assert((LHS.getValueType() == RHS.getValueType()) &&
2903 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2905 // If the RHS of the comparison is zero, we can potentially fold this
2906 // to a specialized branch.
2907 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2908 if (RHSC && RHSC->getZExtValue() == 0) {
2909 if (CC == ISD::SETEQ) {
2910 // See if we can use a TBZ to fold in an AND as well.
2911 // TBZ has a smaller branch displacement than CBZ. If the offset is
2912 // out of bounds, a late MI-layer pass rewrites branches.
2913 // 403.gcc is an example that hits this case.
2914 if (LHS.getOpcode() == ISD::AND &&
2915 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2916 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2917 SDValue Test = LHS.getOperand(0);
2918 uint64_t Mask = LHS.getConstantOperandVal(1);
2920 // TBZ only operates on i64's, but the ext should be free.
2921 if (Test.getValueType() == MVT::i32)
2922 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2924 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2925 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2928 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2929 } else if (CC == ISD::SETNE) {
2930 // See if we can use a TBZ to fold in an AND as well.
2931 // TBZ has a smaller branch displacement than CBZ. If the offset is
2932 // out of bounds, a late MI-layer pass rewrites branches.
2933 // 403.gcc is an example that hits this case.
2934 if (LHS.getOpcode() == ISD::AND &&
2935 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2936 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2937 SDValue Test = LHS.getOperand(0);
2938 uint64_t Mask = LHS.getConstantOperandVal(1);
2940 // TBNZ only operates on i64's, but the ext should be free.
2941 if (Test.getValueType() == MVT::i32)
2942 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2944 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2945 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2948 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2953 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2954 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2958 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2960 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2961 // clean. Some of them require two branches to implement.
2962 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2963 AArch64CC::CondCode CC1, CC2;
2964 changeFPCCToAArch64CC(CC, CC1, CC2);
2965 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2967 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2968 if (CC2 != AArch64CC::AL) {
2969 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2970 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2977 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2978 SelectionDAG &DAG) const {
2979 EVT VT = Op.getValueType();
2982 SDValue In1 = Op.getOperand(0);
2983 SDValue In2 = Op.getOperand(1);
2984 EVT SrcVT = In2.getValueType();
2986 if (SrcVT == MVT::f32 && VT == MVT::f64)
2987 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2988 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2989 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2991 // FIXME: Src type is different, bail out for now. Can VT really be a
2998 SDValue EltMask, VecVal1, VecVal2;
2999 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3002 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3004 if (!VT.isVector()) {
3005 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3006 DAG.getUNDEF(VecVT), In1);
3007 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3008 DAG.getUNDEF(VecVT), In2);
3010 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3011 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3013 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3017 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3018 // immediate moves cannot materialize that in a single instruction for
3019 // 64-bit elements. Instead, materialize zero and then negate it.
3020 EltMask = DAG.getConstant(0, EltVT);
3022 if (!VT.isVector()) {
3023 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3024 DAG.getUNDEF(VecVT), In1);
3025 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3026 DAG.getUNDEF(VecVT), In2);
3028 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3029 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3032 llvm_unreachable("Invalid type for copysign!");
3035 std::vector<SDValue> BuildVectorOps;
3036 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3037 BuildVectorOps.push_back(EltMask);
3039 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3041 // If we couldn't materialize the mask above, then the mask vector will be
3042 // the zero vector, and we need to negate it here.
3043 if (VT == MVT::f64 || VT == MVT::v2f64) {
3044 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3045 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3046 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3050 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3053 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3054 else if (VT == MVT::f64)
3055 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3057 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3060 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3061 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3062 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3065 // While there is no integer popcount instruction, it can
3066 // be more efficiently lowered to the following sequence that uses
3067 // AdvSIMD registers/instructions as long as the copies to/from
3068 // the AdvSIMD registers are cheap.
3069 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3070 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3071 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3072 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3073 SDValue Val = Op.getOperand(0);
3075 EVT VT = Op.getValueType();
3076 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3079 if (VT == MVT::i32) {
3080 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3081 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3084 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3087 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3088 SDValue UaddLV = DAG.getNode(
3089 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3090 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3093 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3097 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3099 if (Op.getValueType().isVector())
3100 return LowerVSETCC(Op, DAG);
3102 SDValue LHS = Op.getOperand(0);
3103 SDValue RHS = Op.getOperand(1);
3104 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3107 // We chose ZeroOrOneBooleanContents, so use zero and one.
3108 EVT VT = Op.getValueType();
3109 SDValue TVal = DAG.getConstant(1, VT);
3110 SDValue FVal = DAG.getConstant(0, VT);
3112 // Handle f128 first, since one possible outcome is a normal integer
3113 // comparison which gets picked up by the next if statement.
3114 if (LHS.getValueType() == MVT::f128) {
3115 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3117 // If softenSetCCOperands returned a scalar, use it.
3118 if (!RHS.getNode()) {
3119 assert(LHS.getValueType() == Op.getValueType() &&
3120 "Unexpected setcc expansion!");
3125 if (LHS.getValueType().isInteger()) {
3128 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3130 // Note that we inverted the condition above, so we reverse the order of
3131 // the true and false operands here. This will allow the setcc to be
3132 // matched to a single CSINC instruction.
3133 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3136 // Now we know we're dealing with FP values.
3137 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3139 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3140 // and do the comparison.
3141 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3143 AArch64CC::CondCode CC1, CC2;
3144 changeFPCCToAArch64CC(CC, CC1, CC2);
3145 if (CC2 == AArch64CC::AL) {
3146 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3147 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3149 // Note that we inverted the condition above, so we reverse the order of
3150 // the true and false operands here. This will allow the setcc to be
3151 // matched to a single CSINC instruction.
3152 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3154 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3155 // totally clean. Some of them require two CSELs to implement. As is in
3156 // this case, we emit the first CSEL and then emit a second using the output
3157 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3159 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3160 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3162 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3164 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3165 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3169 /// A SELECT_CC operation is really some kind of max or min if both values being
3170 /// compared are, in some sense, equal to the results in either case. However,
3171 /// it is permissible to compare f32 values and produce directly extended f64
3174 /// Extending the comparison operands would also be allowed, but is less likely
3175 /// to happen in practice since their use is right here. Note that truncate
3176 /// operations would *not* be semantically equivalent.
3177 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3181 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3182 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3183 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3184 Result.getValueType() == MVT::f64) {
3186 APFloat CmpVal = CCmp->getValueAPF();
3187 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3188 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3191 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3194 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3195 SelectionDAG &DAG) const {
3196 SDValue CC = Op->getOperand(0);
3197 SDValue TVal = Op->getOperand(1);
3198 SDValue FVal = Op->getOperand(2);
3201 unsigned Opc = CC.getOpcode();
3202 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3204 if (CC.getResNo() == 1 &&
3205 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3206 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3207 // Only lower legal XALUO ops.
3208 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3211 AArch64CC::CondCode OFCC;
3212 SDValue Value, Overflow;
3213 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3214 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3216 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3220 if (CC.getOpcode() == ISD::SETCC)
3221 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3222 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3224 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3228 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3229 SelectionDAG &DAG) const {
3230 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3231 SDValue LHS = Op.getOperand(0);
3232 SDValue RHS = Op.getOperand(1);
3233 SDValue TVal = Op.getOperand(2);
3234 SDValue FVal = Op.getOperand(3);
3237 // Handle f128 first, because it will result in a comparison of some RTLIB
3238 // call result against zero.
3239 if (LHS.getValueType() == MVT::f128) {
3240 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3242 // If softenSetCCOperands returned a scalar, we need to compare the result
3243 // against zero to select between true and false values.
3244 if (!RHS.getNode()) {
3245 RHS = DAG.getConstant(0, LHS.getValueType());
3250 // Handle integers first.
3251 if (LHS.getValueType().isInteger()) {
3252 assert((LHS.getValueType() == RHS.getValueType()) &&
3253 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3255 unsigned Opcode = AArch64ISD::CSEL;
3257 // If both the TVal and the FVal are constants, see if we can swap them in
3258 // order to for a CSINV or CSINC out of them.
3259 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3260 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3262 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3263 std::swap(TVal, FVal);
3264 std::swap(CTVal, CFVal);
3265 CC = ISD::getSetCCInverse(CC, true);
3266 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3267 std::swap(TVal, FVal);
3268 std::swap(CTVal, CFVal);
3269 CC = ISD::getSetCCInverse(CC, true);
3270 } else if (TVal.getOpcode() == ISD::XOR) {
3271 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3272 // with a CSINV rather than a CSEL.
3273 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3275 if (CVal && CVal->isAllOnesValue()) {
3276 std::swap(TVal, FVal);
3277 std::swap(CTVal, CFVal);
3278 CC = ISD::getSetCCInverse(CC, true);
3280 } else if (TVal.getOpcode() == ISD::SUB) {
3281 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3282 // that we can match with a CSNEG rather than a CSEL.
3283 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3285 if (CVal && CVal->isNullValue()) {
3286 std::swap(TVal, FVal);
3287 std::swap(CTVal, CFVal);
3288 CC = ISD::getSetCCInverse(CC, true);
3290 } else if (CTVal && CFVal) {
3291 const int64_t TrueVal = CTVal->getSExtValue();
3292 const int64_t FalseVal = CFVal->getSExtValue();
3295 // If both TVal and FVal are constants, see if FVal is the
3296 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3297 // instead of a CSEL in that case.
3298 if (TrueVal == ~FalseVal) {
3299 Opcode = AArch64ISD::CSINV;
3300 } else if (TrueVal == -FalseVal) {
3301 Opcode = AArch64ISD::CSNEG;
3302 } else if (TVal.getValueType() == MVT::i32) {
3303 // If our operands are only 32-bit wide, make sure we use 32-bit
3304 // arithmetic for the check whether we can use CSINC. This ensures that
3305 // the addition in the check will wrap around properly in case there is
3306 // an overflow (which would not be the case if we do the check with
3307 // 64-bit arithmetic).
3308 const uint32_t TrueVal32 = CTVal->getZExtValue();
3309 const uint32_t FalseVal32 = CFVal->getZExtValue();
3311 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3312 Opcode = AArch64ISD::CSINC;
3314 if (TrueVal32 > FalseVal32) {
3318 // 64-bit check whether we can use CSINC.
3319 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3320 Opcode = AArch64ISD::CSINC;
3322 if (TrueVal > FalseVal) {
3327 // Swap TVal and FVal if necessary.
3329 std::swap(TVal, FVal);
3330 std::swap(CTVal, CFVal);
3331 CC = ISD::getSetCCInverse(CC, true);
3334 if (Opcode != AArch64ISD::CSEL) {
3335 // Drop FVal since we can get its value by simply inverting/negating
3342 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3344 EVT VT = Op.getValueType();
3345 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3348 // Now we know we're dealing with FP values.
3349 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3350 assert(LHS.getValueType() == RHS.getValueType());
3351 EVT VT = Op.getValueType();
3353 // Try to match this select into a max/min operation, which have dedicated
3354 // opcode in the instruction set.
3355 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3357 if (getTargetMachine().Options.NoNaNsFPMath) {
3358 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3359 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3360 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3361 CC = ISD::getSetCCSwappedOperands(CC);
3362 std::swap(MinMaxLHS, MinMaxRHS);
3365 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3366 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3376 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3384 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3390 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3391 // and do the comparison.
3392 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3394 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3395 // clean. Some of them require two CSELs to implement.
3396 AArch64CC::CondCode CC1, CC2;
3397 changeFPCCToAArch64CC(CC, CC1, CC2);
3398 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3399 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3401 // If we need a second CSEL, emit it, using the output of the first as the
3402 // RHS. We're effectively OR'ing the two CC's together.
3403 if (CC2 != AArch64CC::AL) {
3404 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3405 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3408 // Otherwise, return the output of the first CSEL.
3412 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3413 SelectionDAG &DAG) const {
3414 // Jump table entries as PC relative offsets. No additional tweaking
3415 // is necessary here. Just get the address of the jump table.
3416 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3417 EVT PtrVT = getPointerTy();
3420 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3421 !Subtarget->isTargetMachO()) {
3422 const unsigned char MO_NC = AArch64II::MO_NC;
3424 AArch64ISD::WrapperLarge, DL, PtrVT,
3425 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3426 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3427 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3428 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3429 AArch64II::MO_G0 | MO_NC));
3433 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3434 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3435 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3436 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3437 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3440 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3441 SelectionDAG &DAG) const {
3442 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3443 EVT PtrVT = getPointerTy();
3446 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3447 // Use the GOT for the large code model on iOS.
3448 if (Subtarget->isTargetMachO()) {
3449 SDValue GotAddr = DAG.getTargetConstantPool(
3450 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3452 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3455 const unsigned char MO_NC = AArch64II::MO_NC;
3457 AArch64ISD::WrapperLarge, DL, PtrVT,
3458 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3459 CP->getOffset(), AArch64II::MO_G3),
3460 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3461 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3462 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3463 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3464 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3465 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3467 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3468 // ELF, the only valid one on Darwin.
3470 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3471 CP->getOffset(), AArch64II::MO_PAGE);
3472 SDValue Lo = DAG.getTargetConstantPool(
3473 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3474 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3476 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3477 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3481 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3482 SelectionDAG &DAG) const {
3483 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3484 EVT PtrVT = getPointerTy();
3486 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3487 !Subtarget->isTargetMachO()) {
3488 const unsigned char MO_NC = AArch64II::MO_NC;
3490 AArch64ISD::WrapperLarge, DL, PtrVT,
3491 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3492 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3493 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3494 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3496 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3497 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3499 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3500 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3504 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3505 SelectionDAG &DAG) const {
3506 AArch64FunctionInfo *FuncInfo =
3507 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3511 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3512 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3513 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3514 MachinePointerInfo(SV), false, false, 0);
3517 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3518 SelectionDAG &DAG) const {
3519 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3520 // Standard, section B.3.
3521 MachineFunction &MF = DAG.getMachineFunction();
3522 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3525 SDValue Chain = Op.getOperand(0);
3526 SDValue VAList = Op.getOperand(1);
3527 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3528 SmallVector<SDValue, 4> MemOps;
3530 // void *__stack at offset 0
3532 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3533 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3534 MachinePointerInfo(SV), false, false, 8));
3536 // void *__gr_top at offset 8
3537 int GPRSize = FuncInfo->getVarArgsGPRSize();
3539 SDValue GRTop, GRTopAddr;
3541 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3542 DAG.getConstant(8, getPointerTy()));
3544 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3545 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3546 DAG.getConstant(GPRSize, getPointerTy()));
3548 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3549 MachinePointerInfo(SV, 8), false, false, 8));
3552 // void *__vr_top at offset 16
3553 int FPRSize = FuncInfo->getVarArgsFPRSize();
3555 SDValue VRTop, VRTopAddr;
3556 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3557 DAG.getConstant(16, getPointerTy()));
3559 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3560 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3561 DAG.getConstant(FPRSize, getPointerTy()));
3563 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3564 MachinePointerInfo(SV, 16), false, false, 8));
3567 // int __gr_offs at offset 24
3568 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3569 DAG.getConstant(24, getPointerTy()));
3570 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3571 GROffsAddr, MachinePointerInfo(SV, 24), false,
3574 // int __vr_offs at offset 28
3575 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3576 DAG.getConstant(28, getPointerTy()));
3577 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3578 VROffsAddr, MachinePointerInfo(SV, 28), false,
3581 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3584 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3585 SelectionDAG &DAG) const {
3586 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3587 : LowerAAPCS_VASTART(Op, DAG);
3590 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3591 SelectionDAG &DAG) const {
3592 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3594 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3595 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3596 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3598 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3599 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3600 8, false, false, MachinePointerInfo(DestSV),
3601 MachinePointerInfo(SrcSV));
3604 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3605 assert(Subtarget->isTargetDarwin() &&
3606 "automatic va_arg instruction only works on Darwin");
3608 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3609 EVT VT = Op.getValueType();
3611 SDValue Chain = Op.getOperand(0);
3612 SDValue Addr = Op.getOperand(1);
3613 unsigned Align = Op.getConstantOperandVal(3);
3615 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3616 MachinePointerInfo(V), false, false, false, 0);
3617 Chain = VAList.getValue(1);
3620 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3621 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3622 DAG.getConstant(Align - 1, getPointerTy()));
3623 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3624 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3627 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3628 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3630 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3631 // up to 64 bits. At the very least, we have to increase the striding of the
3632 // vaargs list to match this, and for FP values we need to introduce
3633 // FP_ROUND nodes as well.
3634 if (VT.isInteger() && !VT.isVector())
3636 bool NeedFPTrunc = false;
3637 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3642 // Increment the pointer, VAList, to the next vaarg
3643 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3644 DAG.getConstant(ArgSize, getPointerTy()));
3645 // Store the incremented VAList to the legalized pointer
3646 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3649 // Load the actual argument out of the pointer VAList
3651 // Load the value as an f64.
3652 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3653 MachinePointerInfo(), false, false, false, 0);
3654 // Round the value down to an f32.
3655 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3656 DAG.getIntPtrConstant(1));
3657 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3658 // Merge the rounded value with the chain output of the load.
3659 return DAG.getMergeValues(Ops, DL);
3662 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3666 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3667 SelectionDAG &DAG) const {
3668 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3669 MFI->setFrameAddressIsTaken(true);
3671 EVT VT = Op.getValueType();
3673 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3675 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3677 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3678 MachinePointerInfo(), false, false, false, 0);
3682 // FIXME? Maybe this could be a TableGen attribute on some registers and
3683 // this table could be generated automatically from RegInfo.
3684 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3686 unsigned Reg = StringSwitch<unsigned>(RegName)
3687 .Case("sp", AArch64::SP)
3691 report_fatal_error("Invalid register name global variable");
3694 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3695 SelectionDAG &DAG) const {
3696 MachineFunction &MF = DAG.getMachineFunction();
3697 MachineFrameInfo *MFI = MF.getFrameInfo();
3698 MFI->setReturnAddressIsTaken(true);
3700 EVT VT = Op.getValueType();
3702 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3704 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3705 SDValue Offset = DAG.getConstant(8, getPointerTy());
3706 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3707 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3708 MachinePointerInfo(), false, false, false, 0);
3711 // Return LR, which contains the return address. Mark it an implicit live-in.
3712 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3713 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3716 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3717 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3718 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3719 SelectionDAG &DAG) const {
3720 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3721 EVT VT = Op.getValueType();
3722 unsigned VTBits = VT.getSizeInBits();
3724 SDValue ShOpLo = Op.getOperand(0);
3725 SDValue ShOpHi = Op.getOperand(1);
3726 SDValue ShAmt = Op.getOperand(2);
3728 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3730 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3732 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3733 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3734 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3735 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3736 DAG.getConstant(VTBits, MVT::i64));
3737 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3739 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3740 ISD::SETGE, dl, DAG);
3741 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3743 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3744 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3746 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3748 // AArch64 shifts larger than the register width are wrapped rather than
3749 // clamped, so we can't just emit "hi >> x".
3750 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3751 SDValue TrueValHi = Opc == ISD::SRA
3752 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3753 DAG.getConstant(VTBits - 1, MVT::i64))
3754 : DAG.getConstant(0, VT);
3756 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3758 SDValue Ops[2] = { Lo, Hi };
3759 return DAG.getMergeValues(Ops, dl);
3762 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3763 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3764 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3765 SelectionDAG &DAG) const {
3766 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3767 EVT VT = Op.getValueType();
3768 unsigned VTBits = VT.getSizeInBits();
3770 SDValue ShOpLo = Op.getOperand(0);
3771 SDValue ShOpHi = Op.getOperand(1);
3772 SDValue ShAmt = Op.getOperand(2);
3775 assert(Op.getOpcode() == ISD::SHL_PARTS);
3776 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3777 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3778 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3779 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3780 DAG.getConstant(VTBits, MVT::i64));
3781 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3782 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3784 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3786 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3787 ISD::SETGE, dl, DAG);
3788 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3790 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3792 // AArch64 shifts of larger than register sizes are wrapped rather than
3793 // clamped, so we can't just emit "lo << a" if a is too big.
3794 SDValue TrueValLo = DAG.getConstant(0, VT);
3795 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3797 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3799 SDValue Ops[2] = { Lo, Hi };
3800 return DAG.getMergeValues(Ops, dl);
3803 bool AArch64TargetLowering::isOffsetFoldingLegal(
3804 const GlobalAddressSDNode *GA) const {
3805 // The AArch64 target doesn't support folding offsets into global addresses.
3809 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3810 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3811 // FIXME: We should be able to handle f128 as well with a clever lowering.
3812 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3816 return AArch64_AM::getFP64Imm(Imm) != -1;
3817 else if (VT == MVT::f32)
3818 return AArch64_AM::getFP32Imm(Imm) != -1;
3822 //===----------------------------------------------------------------------===//
3823 // AArch64 Optimization Hooks
3824 //===----------------------------------------------------------------------===//
3826 //===----------------------------------------------------------------------===//
3827 // AArch64 Inline Assembly Support
3828 //===----------------------------------------------------------------------===//
3830 // Table of Constraints
3831 // TODO: This is the current set of constraints supported by ARM for the
3832 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3834 // r - A general register
3835 // w - An FP/SIMD register of some size in the range v0-v31
3836 // x - An FP/SIMD register of some size in the range v0-v15
3837 // I - Constant that can be used with an ADD instruction
3838 // J - Constant that can be used with a SUB instruction
3839 // K - Constant that can be used with a 32-bit logical instruction
3840 // L - Constant that can be used with a 64-bit logical instruction
3841 // M - Constant that can be used as a 32-bit MOV immediate
3842 // N - Constant that can be used as a 64-bit MOV immediate
3843 // Q - A memory reference with base register and no offset
3844 // S - A symbolic address
3845 // Y - Floating point constant zero
3846 // Z - Integer constant zero
3848 // Note that general register operands will be output using their 64-bit x
3849 // register name, whatever the size of the variable, unless the asm operand
3850 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3851 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3854 /// getConstraintType - Given a constraint letter, return the type of
3855 /// constraint it is for this target.
3856 AArch64TargetLowering::ConstraintType
3857 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3858 if (Constraint.size() == 1) {
3859 switch (Constraint[0]) {
3866 return C_RegisterClass;
3867 // An address with a single base register. Due to the way we
3868 // currently handle addresses it is the same as 'r'.
3873 return TargetLowering::getConstraintType(Constraint);
3876 /// Examine constraint type and operand type and determine a weight value.
3877 /// This object must already have been set up with the operand type
3878 /// and the current alternative constraint selected.
3879 TargetLowering::ConstraintWeight
3880 AArch64TargetLowering::getSingleConstraintMatchWeight(
3881 AsmOperandInfo &info, const char *constraint) const {
3882 ConstraintWeight weight = CW_Invalid;
3883 Value *CallOperandVal = info.CallOperandVal;
3884 // If we don't have a value, we can't do a match,
3885 // but allow it at the lowest weight.
3886 if (!CallOperandVal)
3888 Type *type = CallOperandVal->getType();
3889 // Look at the constraint type.
3890 switch (*constraint) {
3892 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3896 if (type->isFloatingPointTy() || type->isVectorTy())
3897 weight = CW_Register;
3900 weight = CW_Constant;
3906 std::pair<unsigned, const TargetRegisterClass *>
3907 AArch64TargetLowering::getRegForInlineAsmConstraint(
3908 const std::string &Constraint, MVT VT) const {
3909 if (Constraint.size() == 1) {
3910 switch (Constraint[0]) {
3912 if (VT.getSizeInBits() == 64)
3913 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3914 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3917 return std::make_pair(0U, &AArch64::FPR32RegClass);
3918 if (VT.getSizeInBits() == 64)
3919 return std::make_pair(0U, &AArch64::FPR64RegClass);
3920 if (VT.getSizeInBits() == 128)
3921 return std::make_pair(0U, &AArch64::FPR128RegClass);
3923 // The instructions that this constraint is designed for can
3924 // only take 128-bit registers so just use that regclass.
3926 if (VT.getSizeInBits() == 128)
3927 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3931 if (StringRef("{cc}").equals_lower(Constraint))
3932 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3934 // Use the default implementation in TargetLowering to convert the register
3935 // constraint into a member of a register class.
3936 std::pair<unsigned, const TargetRegisterClass *> Res;
3937 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3939 // Not found as a standard register?
3941 unsigned Size = Constraint.size();
3942 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3943 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3944 const std::string Reg =
3945 std::string(&Constraint[2], &Constraint[Size - 1]);
3946 int RegNo = atoi(Reg.c_str());
3947 if (RegNo >= 0 && RegNo <= 31) {
3948 // v0 - v31 are aliases of q0 - q31.
3949 // By default we'll emit v0-v31 for this unless there's a modifier where
3950 // we'll emit the correct register as well.
3951 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3952 Res.second = &AArch64::FPR128RegClass;
3960 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3961 /// vector. If it is invalid, don't add anything to Ops.
3962 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3963 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3964 SelectionDAG &DAG) const {
3967 // Currently only support length 1 constraints.
3968 if (Constraint.length() != 1)
3971 char ConstraintLetter = Constraint[0];
3972 switch (ConstraintLetter) {
3976 // This set of constraints deal with valid constants for various instructions.
3977 // Validate and return a target constant for them if we can.
3979 // 'z' maps to xzr or wzr so it needs an input of 0.
3980 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3981 if (!C || C->getZExtValue() != 0)
3984 if (Op.getValueType() == MVT::i64)
3985 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3987 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3997 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4001 // Grab the value and do some validation.
4002 uint64_t CVal = C->getZExtValue();
4003 switch (ConstraintLetter) {
4004 // The I constraint applies only to simple ADD or SUB immediate operands:
4005 // i.e. 0 to 4095 with optional shift by 12
4006 // The J constraint applies only to ADD or SUB immediates that would be
4007 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4008 // instruction [or vice versa], in other words -1 to -4095 with optional
4009 // left shift by 12.
4011 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4015 uint64_t NVal = -C->getSExtValue();
4016 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
4020 // The K and L constraints apply *only* to logical immediates, including
4021 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4022 // been removed and MOV should be used). So these constraints have to
4023 // distinguish between bit patterns that are valid 32-bit or 64-bit
4024 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4025 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4028 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4032 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4035 // The M and N constraints are a superset of K and L respectively, for use
4036 // with the MOV (immediate) alias. As well as the logical immediates they
4037 // also match 32 or 64-bit immediates that can be loaded either using a
4038 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4039 // (M) or 64-bit 0x1234000000000000 (N) etc.
4040 // As a note some of this code is liberally stolen from the asm parser.
4042 if (!isUInt<32>(CVal))
4044 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4046 if ((CVal & 0xFFFF) == CVal)
4048 if ((CVal & 0xFFFF0000ULL) == CVal)
4050 uint64_t NCVal = ~(uint32_t)CVal;
4051 if ((NCVal & 0xFFFFULL) == NCVal)
4053 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4058 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4060 if ((CVal & 0xFFFFULL) == CVal)
4062 if ((CVal & 0xFFFF0000ULL) == CVal)
4064 if ((CVal & 0xFFFF00000000ULL) == CVal)
4066 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4068 uint64_t NCVal = ~CVal;
4069 if ((NCVal & 0xFFFFULL) == NCVal)
4071 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4073 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4075 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4083 // All assembler immediates are 64-bit integers.
4084 Result = DAG.getTargetConstant(CVal, MVT::i64);
4088 if (Result.getNode()) {
4089 Ops.push_back(Result);
4093 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4096 //===----------------------------------------------------------------------===//
4097 // AArch64 Advanced SIMD Support
4098 //===----------------------------------------------------------------------===//
4100 /// WidenVector - Given a value in the V64 register class, produce the
4101 /// equivalent value in the V128 register class.
4102 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4103 EVT VT = V64Reg.getValueType();
4104 unsigned NarrowSize = VT.getVectorNumElements();
4105 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4106 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4109 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4110 V64Reg, DAG.getConstant(0, MVT::i32));
4113 /// getExtFactor - Determine the adjustment factor for the position when
4114 /// generating an "extract from vector registers" instruction.
4115 static unsigned getExtFactor(SDValue &V) {
4116 EVT EltType = V.getValueType().getVectorElementType();
4117 return EltType.getSizeInBits() / 8;
4120 /// NarrowVector - Given a value in the V128 register class, produce the
4121 /// equivalent value in the V64 register class.
4122 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4123 EVT VT = V128Reg.getValueType();
4124 unsigned WideSize = VT.getVectorNumElements();
4125 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4126 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4129 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4132 // Gather data to see if the operation can be modelled as a
4133 // shuffle in combination with VEXTs.
4134 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4135 SelectionDAG &DAG) const {
4136 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4138 EVT VT = Op.getValueType();
4139 unsigned NumElts = VT.getVectorNumElements();
4141 SmallVector<SDValue, 2> SourceVecs;
4142 SmallVector<unsigned, 2> MinElts;
4143 SmallVector<unsigned, 2> MaxElts;
4145 for (unsigned i = 0; i < NumElts; ++i) {
4146 SDValue V = Op.getOperand(i);
4147 if (V.getOpcode() == ISD::UNDEF)
4149 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4150 // A shuffle can only come from building a vector from various
4151 // elements of other vectors.
4155 // Record this extraction against the appropriate vector if possible...
4156 SDValue SourceVec = V.getOperand(0);
4157 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4158 bool FoundSource = false;
4159 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4160 if (SourceVecs[j] == SourceVec) {
4161 if (MinElts[j] > EltNo)
4163 if (MaxElts[j] < EltNo)
4170 // Or record a new source if not...
4172 SourceVecs.push_back(SourceVec);
4173 MinElts.push_back(EltNo);
4174 MaxElts.push_back(EltNo);
4178 // Currently only do something sane when at most two source vectors
4180 if (SourceVecs.size() > 2)
4183 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4184 int VEXTOffsets[2] = { 0, 0 };
4185 int OffsetMultipliers[2] = { 1, 1 };
4187 // This loop extracts the usage patterns of the source vectors
4188 // and prepares appropriate SDValues for a shuffle if possible.
4189 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4190 unsigned NumSrcElts = SourceVecs[i].getValueType().getVectorNumElements();
4191 SDValue CurSource = SourceVecs[i];
4192 if (SourceVecs[i].getValueType().getVectorElementType() !=
4193 VT.getVectorElementType()) {
4194 // It may hit this case if SourceVecs[i] is AssertSext/AssertZext.
4195 // Then bitcast it to the vector which holds asserted element type,
4196 // and record the multiplier of element width between SourceVecs and
4197 // Build_vector which is needed to extract the correct lanes later.
4199 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4200 SourceVecs[i].getValueSizeInBits() /
4201 VT.getVectorElementType().getSizeInBits());
4203 CurSource = DAG.getNode(ISD::BITCAST, dl, CastVT, SourceVecs[i]);
4204 OffsetMultipliers[i] = CastVT.getVectorNumElements() / NumSrcElts;
4205 NumSrcElts *= OffsetMultipliers[i];
4206 MaxElts[i] *= OffsetMultipliers[i];
4207 MinElts[i] *= OffsetMultipliers[i];
4210 if (CurSource.getValueType() == VT) {
4211 // No VEXT necessary
4212 ShuffleSrcs[i] = CurSource;
4215 } else if (NumSrcElts < NumElts) {
4216 // We can pad out the smaller vector for free, so if it's part of a
4218 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, CurSource,
4219 DAG.getUNDEF(CurSource.getValueType()));
4223 // Since only 64-bit and 128-bit vectors are legal on ARM and
4224 // we've eliminated the other cases...
4225 assert(NumSrcElts == 2 * NumElts &&
4226 "unexpected vector sizes in ReconstructShuffle");
4228 if (MaxElts[i] - MinElts[i] >= NumElts) {
4229 // Span too large for a VEXT to cope
4233 if (MinElts[i] >= NumElts) {
4234 // The extraction can just take the second half
4235 VEXTOffsets[i] = NumElts;
4236 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4237 DAG.getIntPtrConstant(NumElts));
4238 } else if (MaxElts[i] < NumElts) {
4239 // The extraction can just take the first half
4241 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4242 DAG.getIntPtrConstant(0));
4244 // An actual VEXT is needed
4245 VEXTOffsets[i] = MinElts[i];
4246 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4247 DAG.getIntPtrConstant(0));
4248 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4249 DAG.getIntPtrConstant(NumElts));
4250 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4251 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4252 DAG.getConstant(Imm, MVT::i32));
4256 SmallVector<int, 8> Mask;
4258 for (unsigned i = 0; i < NumElts; ++i) {
4259 SDValue Entry = Op.getOperand(i);
4260 if (Entry.getOpcode() == ISD::UNDEF) {
4265 SDValue ExtractVec = Entry.getOperand(0);
4267 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4268 if (ExtractVec == SourceVecs[0]) {
4269 Mask.push_back(ExtractElt * OffsetMultipliers[0] - VEXTOffsets[0]);
4271 Mask.push_back(ExtractElt * OffsetMultipliers[1] + NumElts -
4276 // Final check before we try to produce nonsense...
4277 if (isShuffleMaskLegal(Mask, VT))
4278 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4284 // check if an EXT instruction can handle the shuffle mask when the
4285 // vector sources of the shuffle are the same.
4286 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4287 unsigned NumElts = VT.getVectorNumElements();
4289 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4295 // If this is a VEXT shuffle, the immediate value is the index of the first
4296 // element. The other shuffle indices must be the successive elements after
4298 unsigned ExpectedElt = Imm;
4299 for (unsigned i = 1; i < NumElts; ++i) {
4300 // Increment the expected index. If it wraps around, just follow it
4301 // back to index zero and keep going.
4303 if (ExpectedElt == NumElts)
4307 continue; // ignore UNDEF indices
4308 if (ExpectedElt != static_cast<unsigned>(M[i]))
4315 // check if an EXT instruction can handle the shuffle mask when the
4316 // vector sources of the shuffle are different.
4317 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4319 // Look for the first non-undef element.
4320 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4321 [](int Elt) {return Elt >= 0;});
4323 // Benefit form APInt to handle overflow when calculating expected element.
4324 unsigned NumElts = VT.getVectorNumElements();
4325 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4326 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4327 // The following shuffle indices must be the successive elements after the
4328 // first real element.
4329 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4330 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4331 if (FirstWrongElt != M.end())
4334 // The index of an EXT is the first element if it is not UNDEF.
4335 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4336 // value of the first element. E.g.
4337 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4338 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4339 // ExpectedElt is the last mask index plus 1.
4340 Imm = ExpectedElt.getZExtValue();
4342 // There are two difference cases requiring to reverse input vectors.
4343 // For example, for vector <4 x i32> we have the following cases,
4344 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4345 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4346 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4347 // to reverse two input vectors.
4356 /// isREVMask - Check if a vector shuffle corresponds to a REV
4357 /// instruction with the specified blocksize. (The order of the elements
4358 /// within each block of the vector is reversed.)
4359 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4360 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4361 "Only possible block sizes for REV are: 16, 32, 64");
4363 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4367 unsigned NumElts = VT.getVectorNumElements();
4368 unsigned BlockElts = M[0] + 1;
4369 // If the first shuffle index is UNDEF, be optimistic.
4371 BlockElts = BlockSize / EltSz;
4373 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4376 for (unsigned i = 0; i < NumElts; ++i) {
4378 continue; // ignore UNDEF indices
4379 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4386 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4387 unsigned NumElts = VT.getVectorNumElements();
4388 WhichResult = (M[0] == 0 ? 0 : 1);
4389 unsigned Idx = WhichResult * NumElts / 2;
4390 for (unsigned i = 0; i != NumElts; i += 2) {
4391 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4392 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4400 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4401 unsigned NumElts = VT.getVectorNumElements();
4402 WhichResult = (M[0] == 0 ? 0 : 1);
4403 for (unsigned i = 0; i != NumElts; ++i) {
4405 continue; // ignore UNDEF indices
4406 if ((unsigned)M[i] != 2 * i + WhichResult)
4413 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4414 unsigned NumElts = VT.getVectorNumElements();
4415 WhichResult = (M[0] == 0 ? 0 : 1);
4416 for (unsigned i = 0; i < NumElts; i += 2) {
4417 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4418 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4424 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4425 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4426 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4427 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4428 unsigned NumElts = VT.getVectorNumElements();
4429 WhichResult = (M[0] == 0 ? 0 : 1);
4430 unsigned Idx = WhichResult * NumElts / 2;
4431 for (unsigned i = 0; i != NumElts; i += 2) {
4432 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4433 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4441 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4442 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4443 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4444 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4445 unsigned Half = VT.getVectorNumElements() / 2;
4446 WhichResult = (M[0] == 0 ? 0 : 1);
4447 for (unsigned j = 0; j != 2; ++j) {
4448 unsigned Idx = WhichResult;
4449 for (unsigned i = 0; i != Half; ++i) {
4450 int MIdx = M[i + j * Half];
4451 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4460 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4461 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4462 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4463 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4464 unsigned NumElts = VT.getVectorNumElements();
4465 WhichResult = (M[0] == 0 ? 0 : 1);
4466 for (unsigned i = 0; i < NumElts; i += 2) {
4467 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4468 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4474 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4475 bool &DstIsLeft, int &Anomaly) {
4476 if (M.size() != static_cast<size_t>(NumInputElements))
4479 int NumLHSMatch = 0, NumRHSMatch = 0;
4480 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4482 for (int i = 0; i < NumInputElements; ++i) {
4492 LastLHSMismatch = i;
4494 if (M[i] == i + NumInputElements)
4497 LastRHSMismatch = i;
4500 if (NumLHSMatch == NumInputElements - 1) {
4502 Anomaly = LastLHSMismatch;
4504 } else if (NumRHSMatch == NumInputElements - 1) {
4506 Anomaly = LastRHSMismatch;
4513 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4514 if (VT.getSizeInBits() != 128)
4517 unsigned NumElts = VT.getVectorNumElements();
4519 for (int I = 0, E = NumElts / 2; I != E; I++) {
4524 int Offset = NumElts / 2;
4525 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4526 if (Mask[I] != I + SplitLHS * Offset)
4533 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4535 EVT VT = Op.getValueType();
4536 SDValue V0 = Op.getOperand(0);
4537 SDValue V1 = Op.getOperand(1);
4538 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4540 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4541 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4544 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4546 if (!isConcatMask(Mask, VT, SplitV0))
4549 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4550 VT.getVectorNumElements() / 2);
4552 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4553 DAG.getConstant(0, MVT::i64));
4555 if (V1.getValueType().getSizeInBits() == 128) {
4556 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4557 DAG.getConstant(0, MVT::i64));
4559 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4562 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4563 /// the specified operations to build the shuffle.
4564 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4565 SDValue RHS, SelectionDAG &DAG,
4567 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4568 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4569 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4572 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4581 OP_VUZPL, // VUZP, left result
4582 OP_VUZPR, // VUZP, right result
4583 OP_VZIPL, // VZIP, left result
4584 OP_VZIPR, // VZIP, right result
4585 OP_VTRNL, // VTRN, left result
4586 OP_VTRNR // VTRN, right result
4589 if (OpNum == OP_COPY) {
4590 if (LHSID == (1 * 9 + 2) * 9 + 3)
4592 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4596 SDValue OpLHS, OpRHS;
4597 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4598 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4599 EVT VT = OpLHS.getValueType();
4603 llvm_unreachable("Unknown shuffle opcode!");
4605 // VREV divides the vector in half and swaps within the half.
4606 if (VT.getVectorElementType() == MVT::i32 ||
4607 VT.getVectorElementType() == MVT::f32)
4608 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4609 // vrev <4 x i16> -> REV32
4610 if (VT.getVectorElementType() == MVT::i16)
4611 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4612 // vrev <4 x i8> -> REV16
4613 assert(VT.getVectorElementType() == MVT::i8);
4614 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4619 EVT EltTy = VT.getVectorElementType();
4621 if (EltTy == MVT::i8)
4622 Opcode = AArch64ISD::DUPLANE8;
4623 else if (EltTy == MVT::i16)
4624 Opcode = AArch64ISD::DUPLANE16;
4625 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4626 Opcode = AArch64ISD::DUPLANE32;
4627 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4628 Opcode = AArch64ISD::DUPLANE64;
4630 llvm_unreachable("Invalid vector element type?");
4632 if (VT.getSizeInBits() == 64)
4633 OpLHS = WidenVector(OpLHS, DAG);
4634 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4635 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4640 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4641 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4642 DAG.getConstant(Imm, MVT::i32));
4645 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4648 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4651 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4654 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4657 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4660 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4665 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4666 SelectionDAG &DAG) {
4667 // Check to see if we can use the TBL instruction.
4668 SDValue V1 = Op.getOperand(0);
4669 SDValue V2 = Op.getOperand(1);
4672 EVT EltVT = Op.getValueType().getVectorElementType();
4673 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4675 SmallVector<SDValue, 8> TBLMask;
4676 for (int Val : ShuffleMask) {
4677 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4678 unsigned Offset = Byte + Val * BytesPerElt;
4679 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4683 MVT IndexVT = MVT::v8i8;
4684 unsigned IndexLen = 8;
4685 if (Op.getValueType().getSizeInBits() == 128) {
4686 IndexVT = MVT::v16i8;
4690 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4691 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4694 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4696 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4697 Shuffle = DAG.getNode(
4698 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4699 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4700 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4701 makeArrayRef(TBLMask.data(), IndexLen)));
4703 if (IndexLen == 8) {
4704 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4705 Shuffle = DAG.getNode(
4706 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4707 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4708 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4709 makeArrayRef(TBLMask.data(), IndexLen)));
4711 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4712 // cannot currently represent the register constraints on the input
4714 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4715 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4716 // &TBLMask[0], IndexLen));
4717 Shuffle = DAG.getNode(
4718 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4719 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4720 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4721 makeArrayRef(TBLMask.data(), IndexLen)));
4724 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4727 static unsigned getDUPLANEOp(EVT EltType) {
4728 if (EltType == MVT::i8)
4729 return AArch64ISD::DUPLANE8;
4730 if (EltType == MVT::i16)
4731 return AArch64ISD::DUPLANE16;
4732 if (EltType == MVT::i32 || EltType == MVT::f32)
4733 return AArch64ISD::DUPLANE32;
4734 if (EltType == MVT::i64 || EltType == MVT::f64)
4735 return AArch64ISD::DUPLANE64;
4737 llvm_unreachable("Invalid vector element type?");
4740 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4741 SelectionDAG &DAG) const {
4743 EVT VT = Op.getValueType();
4745 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4747 // Convert shuffles that are directly supported on NEON to target-specific
4748 // DAG nodes, instead of keeping them as shuffles and matching them again
4749 // during code selection. This is more efficient and avoids the possibility
4750 // of inconsistencies between legalization and selection.
4751 ArrayRef<int> ShuffleMask = SVN->getMask();
4753 SDValue V1 = Op.getOperand(0);
4754 SDValue V2 = Op.getOperand(1);
4756 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4757 V1.getValueType().getSimpleVT())) {
4758 int Lane = SVN->getSplatIndex();
4759 // If this is undef splat, generate it via "just" vdup, if possible.
4763 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4764 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4766 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4767 // constant. If so, we can just reference the lane's definition directly.
4768 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4769 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4770 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4772 // Otherwise, duplicate from the lane of the input vector.
4773 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4775 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4776 // to make a vector of the same size as this SHUFFLE. We can ignore the
4777 // extract entirely, and canonicalise the concat using WidenVector.
4778 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4779 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4780 V1 = V1.getOperand(0);
4781 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4782 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4783 Lane -= Idx * VT.getVectorNumElements() / 2;
4784 V1 = WidenVector(V1.getOperand(Idx), DAG);
4785 } else if (VT.getSizeInBits() == 64)
4786 V1 = WidenVector(V1, DAG);
4788 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4791 if (isREVMask(ShuffleMask, VT, 64))
4792 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4793 if (isREVMask(ShuffleMask, VT, 32))
4794 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4795 if (isREVMask(ShuffleMask, VT, 16))
4796 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4798 bool ReverseEXT = false;
4800 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4803 Imm *= getExtFactor(V1);
4804 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4805 DAG.getConstant(Imm, MVT::i32));
4806 } else if (V2->getOpcode() == ISD::UNDEF &&
4807 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4808 Imm *= getExtFactor(V1);
4809 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4810 DAG.getConstant(Imm, MVT::i32));
4813 unsigned WhichResult;
4814 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4815 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4816 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4818 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4819 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4820 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4822 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4823 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4824 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4827 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4828 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4829 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4831 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4832 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4833 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4835 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4836 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4837 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4840 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4841 if (Concat.getNode())
4846 int NumInputElements = V1.getValueType().getVectorNumElements();
4847 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4848 SDValue DstVec = DstIsLeft ? V1 : V2;
4849 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4851 SDValue SrcVec = V1;
4852 int SrcLane = ShuffleMask[Anomaly];
4853 if (SrcLane >= NumInputElements) {
4855 SrcLane -= VT.getVectorNumElements();
4857 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4859 EVT ScalarVT = VT.getVectorElementType();
4860 if (ScalarVT.getSizeInBits() < 32)
4861 ScalarVT = MVT::i32;
4864 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4865 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4869 // If the shuffle is not directly supported and it has 4 elements, use
4870 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4871 unsigned NumElts = VT.getVectorNumElements();
4873 unsigned PFIndexes[4];
4874 for (unsigned i = 0; i != 4; ++i) {
4875 if (ShuffleMask[i] < 0)
4878 PFIndexes[i] = ShuffleMask[i];
4881 // Compute the index in the perfect shuffle table.
4882 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4883 PFIndexes[2] * 9 + PFIndexes[3];
4884 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4885 unsigned Cost = (PFEntry >> 30);
4888 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4891 return GenerateTBL(Op, ShuffleMask, DAG);
4894 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4896 EVT VT = BVN->getValueType(0);
4897 APInt SplatBits, SplatUndef;
4898 unsigned SplatBitSize;
4900 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4901 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4903 for (unsigned i = 0; i < NumSplats; ++i) {
4904 CnstBits <<= SplatBitSize;
4905 UndefBits <<= SplatBitSize;
4906 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4907 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4916 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4917 SelectionDAG &DAG) const {
4918 BuildVectorSDNode *BVN =
4919 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4920 SDValue LHS = Op.getOperand(0);
4922 EVT VT = Op.getValueType();
4927 APInt CnstBits(VT.getSizeInBits(), 0);
4928 APInt UndefBits(VT.getSizeInBits(), 0);
4929 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4930 // We only have BIC vector immediate instruction, which is and-not.
4931 CnstBits = ~CnstBits;
4933 // We make use of a little bit of goto ickiness in order to avoid having to
4934 // duplicate the immediate matching logic for the undef toggled case.
4935 bool SecondTry = false;
4938 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4939 CnstBits = CnstBits.zextOrTrunc(64);
4940 uint64_t CnstVal = CnstBits.getZExtValue();
4942 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4943 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4944 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4945 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4946 DAG.getConstant(CnstVal, MVT::i32),
4947 DAG.getConstant(0, MVT::i32));
4948 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4951 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4952 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4953 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4954 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4955 DAG.getConstant(CnstVal, MVT::i32),
4956 DAG.getConstant(8, MVT::i32));
4957 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4960 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4961 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4962 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4963 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4964 DAG.getConstant(CnstVal, MVT::i32),
4965 DAG.getConstant(16, MVT::i32));
4966 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4969 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4970 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4971 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4972 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4973 DAG.getConstant(CnstVal, MVT::i32),
4974 DAG.getConstant(24, MVT::i32));
4975 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4978 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4979 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4980 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4981 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4982 DAG.getConstant(CnstVal, MVT::i32),
4983 DAG.getConstant(0, MVT::i32));
4984 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4987 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4988 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4989 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4990 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4991 DAG.getConstant(CnstVal, MVT::i32),
4992 DAG.getConstant(8, MVT::i32));
4993 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5000 CnstBits = ~UndefBits;
5004 // We can always fall back to a non-immediate AND.
5009 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5010 // consists of only the same constant int value, returned in reference arg
5012 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5013 uint64_t &ConstVal) {
5014 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5017 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5020 EVT VT = Bvec->getValueType(0);
5021 unsigned NumElts = VT.getVectorNumElements();
5022 for (unsigned i = 1; i < NumElts; ++i)
5023 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5025 ConstVal = FirstElt->getZExtValue();
5029 static unsigned getIntrinsicID(const SDNode *N) {
5030 unsigned Opcode = N->getOpcode();
5033 return Intrinsic::not_intrinsic;
5034 case ISD::INTRINSIC_WO_CHAIN: {
5035 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5036 if (IID < Intrinsic::num_intrinsics)
5038 return Intrinsic::not_intrinsic;
5043 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5044 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5045 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5046 // Also, logical shift right -> sri, with the same structure.
5047 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5048 EVT VT = N->getValueType(0);
5055 // Is the first op an AND?
5056 const SDValue And = N->getOperand(0);
5057 if (And.getOpcode() != ISD::AND)
5060 // Is the second op an shl or lshr?
5061 SDValue Shift = N->getOperand(1);
5062 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5063 // or AArch64ISD::VLSHR vector, #shift
5064 unsigned ShiftOpc = Shift.getOpcode();
5065 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5067 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5069 // Is the shift amount constant?
5070 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5074 // Is the and mask vector all constant?
5076 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5079 // Is C1 == ~C2, taking into account how much one can shift elements of a
5081 uint64_t C2 = C2node->getZExtValue();
5082 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5083 if (C2 > ElemSizeInBits)
5085 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5086 if ((C1 & ElemMask) != (~C2 & ElemMask))
5089 SDValue X = And.getOperand(0);
5090 SDValue Y = Shift.getOperand(0);
5093 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5095 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5096 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5098 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5099 DEBUG(N->dump(&DAG));
5100 DEBUG(dbgs() << "into: \n");
5101 DEBUG(ResultSLI->dump(&DAG));
5107 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5108 SelectionDAG &DAG) const {
5109 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5110 if (EnableAArch64SlrGeneration) {
5111 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5116 BuildVectorSDNode *BVN =
5117 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5118 SDValue LHS = Op.getOperand(1);
5120 EVT VT = Op.getValueType();
5122 // OR commutes, so try swapping the operands.
5124 LHS = Op.getOperand(0);
5125 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5130 APInt CnstBits(VT.getSizeInBits(), 0);
5131 APInt UndefBits(VT.getSizeInBits(), 0);
5132 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5133 // We make use of a little bit of goto ickiness in order to avoid having to
5134 // duplicate the immediate matching logic for the undef toggled case.
5135 bool SecondTry = false;
5138 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5139 CnstBits = CnstBits.zextOrTrunc(64);
5140 uint64_t CnstVal = CnstBits.getZExtValue();
5142 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5143 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5144 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5145 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5146 DAG.getConstant(CnstVal, MVT::i32),
5147 DAG.getConstant(0, MVT::i32));
5148 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5151 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5152 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5153 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5154 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5155 DAG.getConstant(CnstVal, MVT::i32),
5156 DAG.getConstant(8, MVT::i32));
5157 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5160 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5161 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5162 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5163 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5164 DAG.getConstant(CnstVal, MVT::i32),
5165 DAG.getConstant(16, MVT::i32));
5166 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5169 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5170 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5171 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5172 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5173 DAG.getConstant(CnstVal, MVT::i32),
5174 DAG.getConstant(24, MVT::i32));
5175 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5178 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5179 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5180 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5181 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5182 DAG.getConstant(CnstVal, MVT::i32),
5183 DAG.getConstant(0, MVT::i32));
5184 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5187 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5188 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5189 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5190 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5191 DAG.getConstant(CnstVal, MVT::i32),
5192 DAG.getConstant(8, MVT::i32));
5193 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5200 CnstBits = UndefBits;
5204 // We can always fall back to a non-immediate OR.
5209 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5210 // be truncated to fit element width.
5211 static SDValue NormalizeBuildVector(SDValue Op,
5212 SelectionDAG &DAG) {
5213 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5215 EVT VT = Op.getValueType();
5216 EVT EltTy= VT.getVectorElementType();
5218 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5221 SmallVector<SDValue, 16> Ops;
5222 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5223 SDValue Lane = Op.getOperand(I);
5224 if (Lane.getOpcode() == ISD::Constant) {
5225 APInt LowBits(EltTy.getSizeInBits(),
5226 cast<ConstantSDNode>(Lane)->getZExtValue());
5227 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5229 Ops.push_back(Lane);
5231 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5234 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5235 SelectionDAG &DAG) const {
5237 EVT VT = Op.getValueType();
5238 Op = NormalizeBuildVector(Op, DAG);
5239 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5241 APInt CnstBits(VT.getSizeInBits(), 0);
5242 APInt UndefBits(VT.getSizeInBits(), 0);
5243 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5244 // We make use of a little bit of goto ickiness in order to avoid having to
5245 // duplicate the immediate matching logic for the undef toggled case.
5246 bool SecondTry = false;
5249 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5250 CnstBits = CnstBits.zextOrTrunc(64);
5251 uint64_t CnstVal = CnstBits.getZExtValue();
5253 // Certain magic vector constants (used to express things like NOT
5254 // and NEG) are passed through unmodified. This allows codegen patterns
5255 // for these operations to match. Special-purpose patterns will lower
5256 // these immediates to MOVIs if it proves necessary.
5257 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5260 // The many faces of MOVI...
5261 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5262 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5263 if (VT.getSizeInBits() == 128) {
5264 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5265 DAG.getConstant(CnstVal, MVT::i32));
5266 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5269 // Support the V64 version via subregister insertion.
5270 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5271 DAG.getConstant(CnstVal, MVT::i32));
5272 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5275 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5276 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5277 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5278 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5279 DAG.getConstant(CnstVal, MVT::i32),
5280 DAG.getConstant(0, MVT::i32));
5281 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5284 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5285 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5286 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5287 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5288 DAG.getConstant(CnstVal, MVT::i32),
5289 DAG.getConstant(8, MVT::i32));
5290 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5293 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5294 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5295 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5296 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5297 DAG.getConstant(CnstVal, MVT::i32),
5298 DAG.getConstant(16, MVT::i32));
5299 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5302 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5303 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5304 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5305 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5306 DAG.getConstant(CnstVal, MVT::i32),
5307 DAG.getConstant(24, MVT::i32));
5308 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5311 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5312 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5313 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5314 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5315 DAG.getConstant(CnstVal, MVT::i32),
5316 DAG.getConstant(0, MVT::i32));
5317 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5320 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5321 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5322 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5323 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5324 DAG.getConstant(CnstVal, MVT::i32),
5325 DAG.getConstant(8, MVT::i32));
5326 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5329 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5330 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5331 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5332 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5333 DAG.getConstant(CnstVal, MVT::i32),
5334 DAG.getConstant(264, MVT::i32));
5335 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5338 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5339 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5340 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5341 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5342 DAG.getConstant(CnstVal, MVT::i32),
5343 DAG.getConstant(272, MVT::i32));
5344 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5347 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5348 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5349 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5350 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5351 DAG.getConstant(CnstVal, MVT::i32));
5352 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5355 // The few faces of FMOV...
5356 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5357 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5358 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5359 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5360 DAG.getConstant(CnstVal, MVT::i32));
5361 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5364 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5365 VT.getSizeInBits() == 128) {
5366 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5367 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5368 DAG.getConstant(CnstVal, MVT::i32));
5369 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5372 // The many faces of MVNI...
5374 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5375 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5376 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5377 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5378 DAG.getConstant(CnstVal, MVT::i32),
5379 DAG.getConstant(0, MVT::i32));
5380 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5383 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5384 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5385 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5386 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5387 DAG.getConstant(CnstVal, MVT::i32),
5388 DAG.getConstant(8, MVT::i32));
5389 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5392 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5393 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5394 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5395 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5396 DAG.getConstant(CnstVal, MVT::i32),
5397 DAG.getConstant(16, MVT::i32));
5398 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5401 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5402 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5403 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5404 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5405 DAG.getConstant(CnstVal, MVT::i32),
5406 DAG.getConstant(24, MVT::i32));
5407 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5410 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5411 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5412 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5413 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5414 DAG.getConstant(CnstVal, MVT::i32),
5415 DAG.getConstant(0, MVT::i32));
5416 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5419 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5420 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5421 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5422 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5423 DAG.getConstant(CnstVal, MVT::i32),
5424 DAG.getConstant(8, MVT::i32));
5425 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5428 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5429 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5430 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5431 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5432 DAG.getConstant(CnstVal, MVT::i32),
5433 DAG.getConstant(264, MVT::i32));
5434 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5437 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5438 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5439 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5440 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5441 DAG.getConstant(CnstVal, MVT::i32),
5442 DAG.getConstant(272, MVT::i32));
5443 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5450 CnstBits = UndefBits;
5455 // Scan through the operands to find some interesting properties we can
5457 // 1) If only one value is used, we can use a DUP, or
5458 // 2) if only the low element is not undef, we can just insert that, or
5459 // 3) if only one constant value is used (w/ some non-constant lanes),
5460 // we can splat the constant value into the whole vector then fill
5461 // in the non-constant lanes.
5462 // 4) FIXME: If different constant values are used, but we can intelligently
5463 // select the values we'll be overwriting for the non-constant
5464 // lanes such that we can directly materialize the vector
5465 // some other way (MOVI, e.g.), we can be sneaky.
5466 unsigned NumElts = VT.getVectorNumElements();
5467 bool isOnlyLowElement = true;
5468 bool usesOnlyOneValue = true;
5469 bool usesOnlyOneConstantValue = true;
5470 bool isConstant = true;
5471 unsigned NumConstantLanes = 0;
5473 SDValue ConstantValue;
5474 for (unsigned i = 0; i < NumElts; ++i) {
5475 SDValue V = Op.getOperand(i);
5476 if (V.getOpcode() == ISD::UNDEF)
5479 isOnlyLowElement = false;
5480 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5483 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5485 if (!ConstantValue.getNode())
5487 else if (ConstantValue != V)
5488 usesOnlyOneConstantValue = false;
5491 if (!Value.getNode())
5493 else if (V != Value)
5494 usesOnlyOneValue = false;
5497 if (!Value.getNode())
5498 return DAG.getUNDEF(VT);
5500 if (isOnlyLowElement)
5501 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5503 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5504 // i32 and try again.
5505 if (usesOnlyOneValue) {
5507 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5508 Value.getValueType() != VT)
5509 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5511 // This is actually a DUPLANExx operation, which keeps everything vectory.
5513 // DUPLANE works on 128-bit vectors, widen it if necessary.
5514 SDValue Lane = Value.getOperand(1);
5515 Value = Value.getOperand(0);
5516 if (Value.getValueType().getSizeInBits() == 64)
5517 Value = WidenVector(Value, DAG);
5519 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5520 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5523 if (VT.getVectorElementType().isFloatingPoint()) {
5524 SmallVector<SDValue, 8> Ops;
5526 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5527 for (unsigned i = 0; i < NumElts; ++i)
5528 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5529 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5530 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5531 Val = LowerBUILD_VECTOR(Val, DAG);
5533 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5537 // If there was only one constant value used and for more than one lane,
5538 // start by splatting that value, then replace the non-constant lanes. This
5539 // is better than the default, which will perform a separate initialization
5541 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5542 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5543 // Now insert the non-constant lanes.
5544 for (unsigned i = 0; i < NumElts; ++i) {
5545 SDValue V = Op.getOperand(i);
5546 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5547 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5548 // Note that type legalization likely mucked about with the VT of the
5549 // source operand, so we may have to convert it here before inserting.
5550 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5556 // If all elements are constants and the case above didn't get hit, fall back
5557 // to the default expansion, which will generate a load from the constant
5562 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5564 SDValue shuffle = ReconstructShuffle(Op, DAG);
5565 if (shuffle != SDValue())
5569 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5570 // know the default expansion would otherwise fall back on something even
5571 // worse. For a vector with one or two non-undef values, that's
5572 // scalar_to_vector for the elements followed by a shuffle (provided the
5573 // shuffle is valid for the target) and materialization element by element
5574 // on the stack followed by a load for everything else.
5575 if (!isConstant && !usesOnlyOneValue) {
5576 SDValue Vec = DAG.getUNDEF(VT);
5577 SDValue Op0 = Op.getOperand(0);
5578 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5580 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5581 // a) Avoid a RMW dependency on the full vector register, and
5582 // b) Allow the register coalescer to fold away the copy if the
5583 // value is already in an S or D register.
5584 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5585 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5587 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5588 DAG.getTargetConstant(SubIdx, MVT::i32));
5589 Vec = SDValue(N, 0);
5592 for (; i < NumElts; ++i) {
5593 SDValue V = Op.getOperand(i);
5594 if (V.getOpcode() == ISD::UNDEF)
5596 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5597 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5602 // Just use the default expansion. We failed to find a better alternative.
5606 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5607 SelectionDAG &DAG) const {
5608 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5610 // Check for non-constant or out of range lane.
5611 EVT VT = Op.getOperand(0).getValueType();
5612 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5613 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5617 // Insertion/extraction are legal for V128 types.
5618 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5619 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5622 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5623 VT != MVT::v1i64 && VT != MVT::v2f32)
5626 // For V64 types, we perform insertion by expanding the value
5627 // to a V128 type and perform the insertion on that.
5629 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5630 EVT WideTy = WideVec.getValueType();
5632 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5633 Op.getOperand(1), Op.getOperand(2));
5634 // Re-narrow the resultant vector.
5635 return NarrowVector(Node, DAG);
5639 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5640 SelectionDAG &DAG) const {
5641 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5643 // Check for non-constant or out of range lane.
5644 EVT VT = Op.getOperand(0).getValueType();
5645 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5646 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5650 // Insertion/extraction are legal for V128 types.
5651 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5652 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5655 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5656 VT != MVT::v1i64 && VT != MVT::v2f32)
5659 // For V64 types, we perform extraction by expanding the value
5660 // to a V128 type and perform the extraction on that.
5662 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5663 EVT WideTy = WideVec.getValueType();
5665 EVT ExtrTy = WideTy.getVectorElementType();
5666 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5669 // For extractions, we just return the result directly.
5670 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5674 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5675 SelectionDAG &DAG) const {
5676 EVT VT = Op.getOperand(0).getValueType();
5682 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5685 unsigned Val = Cst->getZExtValue();
5687 unsigned Size = Op.getValueType().getSizeInBits();
5691 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5694 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5697 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5700 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5703 llvm_unreachable("Unexpected vector type in extract_subvector!");
5706 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5708 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5714 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5716 if (VT.getVectorNumElements() == 4 &&
5717 (VT.is128BitVector() || VT.is64BitVector())) {
5718 unsigned PFIndexes[4];
5719 for (unsigned i = 0; i != 4; ++i) {
5723 PFIndexes[i] = M[i];
5726 // Compute the index in the perfect shuffle table.
5727 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5728 PFIndexes[2] * 9 + PFIndexes[3];
5729 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5730 unsigned Cost = (PFEntry >> 30);
5738 unsigned DummyUnsigned;
5740 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5741 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5742 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5743 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5744 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5745 isZIPMask(M, VT, DummyUnsigned) ||
5746 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5747 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5748 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5749 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5750 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5753 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5754 /// operand of a vector shift operation, where all the elements of the
5755 /// build_vector must have the same constant integer value.
5756 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5757 // Ignore bit_converts.
5758 while (Op.getOpcode() == ISD::BITCAST)
5759 Op = Op.getOperand(0);
5760 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5761 APInt SplatBits, SplatUndef;
5762 unsigned SplatBitSize;
5764 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5765 HasAnyUndefs, ElementBits) ||
5766 SplatBitSize > ElementBits)
5768 Cnt = SplatBits.getSExtValue();
5772 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5773 /// operand of a vector shift left operation. That value must be in the range:
5774 /// 0 <= Value < ElementBits for a left shift; or
5775 /// 0 <= Value <= ElementBits for a long left shift.
5776 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5777 assert(VT.isVector() && "vector shift count is not a vector type");
5778 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5779 if (!getVShiftImm(Op, ElementBits, Cnt))
5781 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5784 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5785 /// operand of a vector shift right operation. For a shift opcode, the value
5786 /// is positive, but for an intrinsic the value count must be negative. The
5787 /// absolute value must be in the range:
5788 /// 1 <= |Value| <= ElementBits for a right shift; or
5789 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5790 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5792 assert(VT.isVector() && "vector shift count is not a vector type");
5793 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5794 if (!getVShiftImm(Op, ElementBits, Cnt))
5798 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5801 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5802 SelectionDAG &DAG) const {
5803 EVT VT = Op.getValueType();
5807 if (!Op.getOperand(1).getValueType().isVector())
5809 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5811 switch (Op.getOpcode()) {
5813 llvm_unreachable("unexpected shift opcode");
5816 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5817 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5818 DAG.getConstant(Cnt, MVT::i32));
5819 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5820 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5821 Op.getOperand(0), Op.getOperand(1));
5824 // Right shift immediate
5825 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5828 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5829 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5830 DAG.getConstant(Cnt, MVT::i32));
5833 // Right shift register. Note, there is not a shift right register
5834 // instruction, but the shift left register instruction takes a signed
5835 // value, where negative numbers specify a right shift.
5836 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5837 : Intrinsic::aarch64_neon_ushl;
5838 // negate the shift amount
5839 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5840 SDValue NegShiftLeft =
5841 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5842 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5843 return NegShiftLeft;
5849 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5850 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5851 SDLoc dl, SelectionDAG &DAG) {
5852 EVT SrcVT = LHS.getValueType();
5854 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5855 APInt CnstBits(VT.getSizeInBits(), 0);
5856 APInt UndefBits(VT.getSizeInBits(), 0);
5857 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5858 bool IsZero = IsCnst && (CnstBits == 0);
5860 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5864 case AArch64CC::NE: {
5867 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5869 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5870 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5874 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5875 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5878 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5879 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5882 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5883 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5886 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5887 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5891 // If we ignore NaNs then we can use to the MI implementation.
5895 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5896 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5903 case AArch64CC::NE: {
5906 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5908 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5909 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5913 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5914 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5917 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5918 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5921 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5922 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5925 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5926 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5928 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5930 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5933 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5934 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5936 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5938 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5942 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5943 SelectionDAG &DAG) const {
5944 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5945 SDValue LHS = Op.getOperand(0);
5946 SDValue RHS = Op.getOperand(1);
5949 if (LHS.getValueType().getVectorElementType().isInteger()) {
5950 assert(LHS.getValueType() == RHS.getValueType());
5951 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5952 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5956 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5957 LHS.getValueType().getVectorElementType() == MVT::f64);
5959 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5960 // clean. Some of them require two branches to implement.
5961 AArch64CC::CondCode CC1, CC2;
5963 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5965 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5967 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5971 if (CC2 != AArch64CC::AL) {
5973 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5974 if (!Cmp2.getNode())
5977 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5981 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5986 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5987 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5988 /// specified in the intrinsic calls.
5989 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5991 unsigned Intrinsic) const {
5992 switch (Intrinsic) {
5993 case Intrinsic::aarch64_neon_ld2:
5994 case Intrinsic::aarch64_neon_ld3:
5995 case Intrinsic::aarch64_neon_ld4:
5996 case Intrinsic::aarch64_neon_ld1x2:
5997 case Intrinsic::aarch64_neon_ld1x3:
5998 case Intrinsic::aarch64_neon_ld1x4:
5999 case Intrinsic::aarch64_neon_ld2lane:
6000 case Intrinsic::aarch64_neon_ld3lane:
6001 case Intrinsic::aarch64_neon_ld4lane:
6002 case Intrinsic::aarch64_neon_ld2r:
6003 case Intrinsic::aarch64_neon_ld3r:
6004 case Intrinsic::aarch64_neon_ld4r: {
6005 Info.opc = ISD::INTRINSIC_W_CHAIN;
6006 // Conservatively set memVT to the entire set of vectors loaded.
6007 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6008 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6009 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6012 Info.vol = false; // volatile loads with NEON intrinsics not supported
6013 Info.readMem = true;
6014 Info.writeMem = false;
6017 case Intrinsic::aarch64_neon_st2:
6018 case Intrinsic::aarch64_neon_st3:
6019 case Intrinsic::aarch64_neon_st4:
6020 case Intrinsic::aarch64_neon_st1x2:
6021 case Intrinsic::aarch64_neon_st1x3:
6022 case Intrinsic::aarch64_neon_st1x4:
6023 case Intrinsic::aarch64_neon_st2lane:
6024 case Intrinsic::aarch64_neon_st3lane:
6025 case Intrinsic::aarch64_neon_st4lane: {
6026 Info.opc = ISD::INTRINSIC_VOID;
6027 // Conservatively set memVT to the entire set of vectors stored.
6028 unsigned NumElts = 0;
6029 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6030 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6031 if (!ArgTy->isVectorTy())
6033 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6035 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6036 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6039 Info.vol = false; // volatile stores with NEON intrinsics not supported
6040 Info.readMem = false;
6041 Info.writeMem = true;
6044 case Intrinsic::aarch64_ldaxr:
6045 case Intrinsic::aarch64_ldxr: {
6046 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6047 Info.opc = ISD::INTRINSIC_W_CHAIN;
6048 Info.memVT = MVT::getVT(PtrTy->getElementType());
6049 Info.ptrVal = I.getArgOperand(0);
6051 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6053 Info.readMem = true;
6054 Info.writeMem = false;
6057 case Intrinsic::aarch64_stlxr:
6058 case Intrinsic::aarch64_stxr: {
6059 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6060 Info.opc = ISD::INTRINSIC_W_CHAIN;
6061 Info.memVT = MVT::getVT(PtrTy->getElementType());
6062 Info.ptrVal = I.getArgOperand(1);
6064 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6066 Info.readMem = false;
6067 Info.writeMem = true;
6070 case Intrinsic::aarch64_ldaxp:
6071 case Intrinsic::aarch64_ldxp: {
6072 Info.opc = ISD::INTRINSIC_W_CHAIN;
6073 Info.memVT = MVT::i128;
6074 Info.ptrVal = I.getArgOperand(0);
6078 Info.readMem = true;
6079 Info.writeMem = false;
6082 case Intrinsic::aarch64_stlxp:
6083 case Intrinsic::aarch64_stxp: {
6084 Info.opc = ISD::INTRINSIC_W_CHAIN;
6085 Info.memVT = MVT::i128;
6086 Info.ptrVal = I.getArgOperand(2);
6090 Info.readMem = false;
6091 Info.writeMem = true;
6101 // Truncations from 64-bit GPR to 32-bit GPR is free.
6102 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6103 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6105 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6106 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6107 return NumBits1 > NumBits2;
6109 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6110 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6112 unsigned NumBits1 = VT1.getSizeInBits();
6113 unsigned NumBits2 = VT2.getSizeInBits();
6114 return NumBits1 > NumBits2;
6117 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6119 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6120 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6122 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6123 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6124 return NumBits1 == 32 && NumBits2 == 64;
6126 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6127 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6129 unsigned NumBits1 = VT1.getSizeInBits();
6130 unsigned NumBits2 = VT2.getSizeInBits();
6131 return NumBits1 == 32 && NumBits2 == 64;
6134 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6135 EVT VT1 = Val.getValueType();
6136 if (isZExtFree(VT1, VT2)) {
6140 if (Val.getOpcode() != ISD::LOAD)
6143 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6144 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6145 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6146 VT1.getSizeInBits() <= 32);
6149 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6150 unsigned &RequiredAligment) const {
6151 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6153 // Cyclone supports unaligned accesses.
6154 RequiredAligment = 0;
6155 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6156 return NumBits == 32 || NumBits == 64;
6159 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6160 unsigned &RequiredAligment) const {
6161 if (!LoadedType.isSimple() ||
6162 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6164 // Cyclone supports unaligned accesses.
6165 RequiredAligment = 0;
6166 unsigned NumBits = LoadedType.getSizeInBits();
6167 return NumBits == 32 || NumBits == 64;
6170 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6171 unsigned AlignCheck) {
6172 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6173 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6176 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6177 unsigned SrcAlign, bool IsMemset,
6180 MachineFunction &MF) const {
6181 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6182 // instruction to materialize the v2i64 zero and one store (with restrictive
6183 // addressing mode). Just do two i64 store of zero-registers.
6185 const Function *F = MF.getFunction();
6186 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6187 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6188 Attribute::NoImplicitFloat) &&
6189 (memOpAlign(SrcAlign, DstAlign, 16) ||
6190 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6193 return Size >= 8 ? MVT::i64 : MVT::i32;
6196 // 12-bit optionally shifted immediates are legal for adds.
6197 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6198 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6203 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6204 // immediates is the same as for an add or a sub.
6205 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6208 return isLegalAddImmediate(Immed);
6211 /// isLegalAddressingMode - Return true if the addressing mode represented
6212 /// by AM is legal for this target, for a load/store of the specified type.
6213 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6215 // AArch64 has five basic addressing modes:
6217 // reg + 9-bit signed offset
6218 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6220 // reg + SIZE_IN_BYTES * reg
6222 // No global is ever allowed as a base.
6226 // No reg+reg+imm addressing.
6227 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6230 // check reg + imm case:
6231 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6232 uint64_t NumBytes = 0;
6233 if (Ty->isSized()) {
6234 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6235 NumBytes = NumBits / 8;
6236 if (!isPowerOf2_64(NumBits))
6241 int64_t Offset = AM.BaseOffs;
6243 // 9-bit signed offset
6244 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6247 // 12-bit unsigned offset
6248 unsigned shift = Log2_64(NumBytes);
6249 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6250 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6251 (Offset >> shift) << shift == Offset)
6256 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6258 if (!AM.Scale || AM.Scale == 1 ||
6259 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6264 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6266 // Scaling factors are not free at all.
6267 // Operands | Rt Latency
6268 // -------------------------------------------
6270 // -------------------------------------------
6271 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6272 // Rt, [Xn, Wm, <extend> #imm] |
6273 if (isLegalAddressingMode(AM, Ty))
6274 // Scale represents reg2 * scale, thus account for 1 if
6275 // it is not equal to 0 or 1.
6276 return AM.Scale != 0 && AM.Scale != 1;
6280 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6281 VT = VT.getScalarType();
6286 switch (VT.getSimpleVT().SimpleTy) {
6298 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6299 // LR is a callee-save register, but we must treat it as clobbered by any call
6300 // site. Hence we include LR in the scratch registers, which are in turn added
6301 // as implicit-defs for stackmaps and patchpoints.
6302 static const MCPhysReg ScratchRegs[] = {
6303 AArch64::X16, AArch64::X17, AArch64::LR, 0
6309 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6310 EVT VT = N->getValueType(0);
6311 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6312 // it with shift to let it be lowered to UBFX.
6313 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6314 isa<ConstantSDNode>(N->getOperand(1))) {
6315 uint64_t TruncMask = N->getConstantOperandVal(1);
6316 if (isMask_64(TruncMask) &&
6317 N->getOperand(0).getOpcode() == ISD::SRL &&
6318 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6324 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6326 assert(Ty->isIntegerTy());
6328 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6332 int64_t Val = Imm.getSExtValue();
6333 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6336 if ((int64_t)Val < 0)
6339 Val &= (1LL << 32) - 1;
6341 unsigned LZ = countLeadingZeros((uint64_t)Val);
6342 unsigned Shift = (63 - LZ) / 16;
6343 // MOVZ is free so return true for one or fewer MOVK.
6344 return (Shift < 3) ? true : false;
6347 // Generate SUBS and CSEL for integer abs.
6348 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6349 EVT VT = N->getValueType(0);
6351 SDValue N0 = N->getOperand(0);
6352 SDValue N1 = N->getOperand(1);
6355 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6356 // and change it to SUB and CSEL.
6357 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6358 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6359 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6360 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6361 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6362 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6364 // Generate SUBS & CSEL.
6366 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6367 N0.getOperand(0), DAG.getConstant(0, VT));
6368 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6369 DAG.getConstant(AArch64CC::PL, MVT::i32),
6370 SDValue(Cmp.getNode(), 1));
6375 // performXorCombine - Attempts to handle integer ABS.
6376 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6377 TargetLowering::DAGCombinerInfo &DCI,
6378 const AArch64Subtarget *Subtarget) {
6379 if (DCI.isBeforeLegalizeOps())
6382 return performIntegerAbsCombine(N, DAG);
6386 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6388 std::vector<SDNode *> *Created) const {
6389 // fold (sdiv X, pow2)
6390 EVT VT = N->getValueType(0);
6391 if ((VT != MVT::i32 && VT != MVT::i64) ||
6392 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6396 SDValue N0 = N->getOperand(0);
6397 unsigned Lg2 = Divisor.countTrailingZeros();
6398 SDValue Zero = DAG.getConstant(0, VT);
6399 SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT);
6401 // Add (N0 < 0) ? Pow2 - 1 : 0;
6403 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6404 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6405 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6408 Created->push_back(Cmp.getNode());
6409 Created->push_back(Add.getNode());
6410 Created->push_back(CSel.getNode());
6415 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6417 // If we're dividing by a positive value, we're done. Otherwise, we must
6418 // negate the result.
6419 if (Divisor.isNonNegative())
6423 Created->push_back(SRA.getNode());
6424 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6427 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6428 TargetLowering::DAGCombinerInfo &DCI,
6429 const AArch64Subtarget *Subtarget) {
6430 if (DCI.isBeforeLegalizeOps())
6433 // Multiplication of a power of two plus/minus one can be done more
6434 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6435 // future CPUs have a cheaper MADD instruction, this may need to be
6436 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6437 // 64-bit is 5 cycles, so this is always a win.
6438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6439 APInt Value = C->getAPIntValue();
6440 EVT VT = N->getValueType(0);
6441 if (Value.isNonNegative()) {
6442 // (mul x, 2^N + 1) => (add (shl x, N), x)
6443 APInt VM1 = Value - 1;
6444 if (VM1.isPowerOf2()) {
6445 SDValue ShiftedVal =
6446 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6447 DAG.getConstant(VM1.logBase2(), MVT::i64));
6448 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6451 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6452 APInt VP1 = Value + 1;
6453 if (VP1.isPowerOf2()) {
6454 SDValue ShiftedVal =
6455 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6456 DAG.getConstant(VP1.logBase2(), MVT::i64));
6457 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6461 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6462 APInt VNM1 = -Value - 1;
6463 if (VNM1.isPowerOf2()) {
6464 SDValue ShiftedVal =
6465 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6466 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6468 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6469 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6471 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6472 APInt VNP1 = -Value + 1;
6473 if (VNP1.isPowerOf2()) {
6474 SDValue ShiftedVal =
6475 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6476 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6477 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6485 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6486 SelectionDAG &DAG) {
6487 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6488 // optimize away operation when it's from a constant.
6490 // The general transformation is:
6491 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6492 // AND(VECTOR_CMP(x,y), constant2)
6493 // constant2 = UNARYOP(constant)
6495 // Early exit if this isn't a vector operation or if the operand of the
6496 // unary operation isn't a bitwise AND.
6497 EVT VT = N->getValueType(0);
6498 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6499 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC)
6502 // Now check that the other operand of the AND is a constant splat. We could
6503 // make the transformation for non-constant splats as well, but it's unclear
6504 // that would be a benefit as it would not eliminate any operations, just
6505 // perform one more step in scalar code before moving to the vector unit.
6506 if (BuildVectorSDNode *BV =
6507 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6508 // Bail out if the vector isn't a constant splat.
6509 if (!BV->getConstantSplatNode())
6512 // Everything checks out. Build up the new and improved node.
6514 EVT IntVT = BV->getValueType(0);
6515 // Create a new constant of the appropriate type for the transformed
6517 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6518 // The AND node needs bitcasts to/from an integer vector type around it.
6519 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6520 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6521 N->getOperand(0)->getOperand(0), MaskConst);
6522 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6529 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6530 // First try to optimize away the conversion when it's conditionally from
6531 // a constant. Vectors only.
6532 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6533 if (Res != SDValue())
6536 EVT VT = N->getValueType(0);
6537 if (VT != MVT::f32 && VT != MVT::f64)
6540 // Only optimize when the source and destination types have the same width.
6541 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6544 // If the result of an integer load is only used by an integer-to-float
6545 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6546 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6547 SDValue N0 = N->getOperand(0);
6548 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6549 // Do not change the width of a volatile load.
6550 !cast<LoadSDNode>(N0)->isVolatile()) {
6551 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6552 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6553 LN0->getPointerInfo(), LN0->isVolatile(),
6554 LN0->isNonTemporal(), LN0->isInvariant(),
6555 LN0->getAlignment());
6557 // Make sure successors of the original load stay after it by updating them
6558 // to use the new Chain.
6559 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6562 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6563 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6569 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6570 /// searches for and classifies those shifts.
6571 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6573 if (N.getOpcode() == ISD::SHL)
6575 else if (N.getOpcode() == ISD::SRL)
6580 if (!isa<ConstantSDNode>(N.getOperand(1)))
6583 ShiftAmount = N->getConstantOperandVal(1);
6584 Src = N->getOperand(0);
6588 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6589 /// registers viewed as a high/low pair. This function looks for the pattern:
6590 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6591 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6593 static SDValue tryCombineToEXTR(SDNode *N,
6594 TargetLowering::DAGCombinerInfo &DCI) {
6595 SelectionDAG &DAG = DCI.DAG;
6597 EVT VT = N->getValueType(0);
6599 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6601 if (VT != MVT::i32 && VT != MVT::i64)
6605 uint32_t ShiftLHS = 0;
6607 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6611 uint32_t ShiftRHS = 0;
6613 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6616 // If they're both trying to come from the high part of the register, they're
6617 // not really an EXTR.
6618 if (LHSFromHi == RHSFromHi)
6621 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6625 std::swap(LHS, RHS);
6626 std::swap(ShiftLHS, ShiftRHS);
6629 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6630 DAG.getConstant(ShiftRHS, MVT::i64));
6633 static SDValue tryCombineToBSL(SDNode *N,
6634 TargetLowering::DAGCombinerInfo &DCI) {
6635 EVT VT = N->getValueType(0);
6636 SelectionDAG &DAG = DCI.DAG;
6642 SDValue N0 = N->getOperand(0);
6643 if (N0.getOpcode() != ISD::AND)
6646 SDValue N1 = N->getOperand(1);
6647 if (N1.getOpcode() != ISD::AND)
6650 // We only have to look for constant vectors here since the general, variable
6651 // case can be handled in TableGen.
6652 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6653 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6654 for (int i = 1; i >= 0; --i)
6655 for (int j = 1; j >= 0; --j) {
6656 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6657 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6661 bool FoundMatch = true;
6662 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6663 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6664 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6666 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6673 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6674 N0->getOperand(1 - i), N1->getOperand(1 - j));
6680 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6681 const AArch64Subtarget *Subtarget) {
6682 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6683 if (!EnableAArch64ExtrGeneration)
6685 SelectionDAG &DAG = DCI.DAG;
6686 EVT VT = N->getValueType(0);
6688 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6691 SDValue Res = tryCombineToEXTR(N, DCI);
6695 Res = tryCombineToBSL(N, DCI);
6702 static SDValue performBitcastCombine(SDNode *N,
6703 TargetLowering::DAGCombinerInfo &DCI,
6704 SelectionDAG &DAG) {
6705 // Wait 'til after everything is legalized to try this. That way we have
6706 // legal vector types and such.
6707 if (DCI.isBeforeLegalizeOps())
6710 // Remove extraneous bitcasts around an extract_subvector.
6712 // (v4i16 (bitconvert
6713 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6715 // (extract_subvector ((v8i16 ...), (i64 4)))
6717 // Only interested in 64-bit vectors as the ultimate result.
6718 EVT VT = N->getValueType(0);
6721 if (VT.getSimpleVT().getSizeInBits() != 64)
6723 // Is the operand an extract_subvector starting at the beginning or halfway
6724 // point of the vector? A low half may also come through as an
6725 // EXTRACT_SUBREG, so look for that, too.
6726 SDValue Op0 = N->getOperand(0);
6727 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6728 !(Op0->isMachineOpcode() &&
6729 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6731 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6732 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6733 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6735 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6736 if (idx != AArch64::dsub)
6738 // The dsub reference is equivalent to a lane zero subvector reference.
6741 // Look through the bitcast of the input to the extract.
6742 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6744 SDValue Source = Op0->getOperand(0)->getOperand(0);
6745 // If the source type has twice the number of elements as our destination
6746 // type, we know this is an extract of the high or low half of the vector.
6747 EVT SVT = Source->getValueType(0);
6748 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6751 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6753 // Create the simplified form to just extract the low or high half of the
6754 // vector directly rather than bothering with the bitcasts.
6756 unsigned NumElements = VT.getVectorNumElements();
6758 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6759 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6761 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6762 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6768 static SDValue performConcatVectorsCombine(SDNode *N,
6769 TargetLowering::DAGCombinerInfo &DCI,
6770 SelectionDAG &DAG) {
6771 // Wait 'til after everything is legalized to try this. That way we have
6772 // legal vector types and such.
6773 if (DCI.isBeforeLegalizeOps())
6777 EVT VT = N->getValueType(0);
6779 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6780 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6781 // canonicalise to that.
6782 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6783 assert(VT.getVectorElementType().getSizeInBits() == 64);
6784 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6785 WidenVector(N->getOperand(0), DAG),
6786 DAG.getConstant(0, MVT::i64));
6789 // Canonicalise concat_vectors so that the right-hand vector has as few
6790 // bit-casts as possible before its real operation. The primary matching
6791 // destination for these operations will be the narrowing "2" instructions,
6792 // which depend on the operation being performed on this right-hand vector.
6794 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6796 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6798 SDValue Op1 = N->getOperand(1);
6799 if (Op1->getOpcode() != ISD::BITCAST)
6801 SDValue RHS = Op1->getOperand(0);
6802 MVT RHSTy = RHS.getValueType().getSimpleVT();
6803 // If the RHS is not a vector, this is not the pattern we're looking for.
6804 if (!RHSTy.isVector())
6807 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6809 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6810 RHSTy.getVectorNumElements() * 2);
6812 ISD::BITCAST, dl, VT,
6813 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6814 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6817 static SDValue tryCombineFixedPointConvert(SDNode *N,
6818 TargetLowering::DAGCombinerInfo &DCI,
6819 SelectionDAG &DAG) {
6820 // Wait 'til after everything is legalized to try this. That way we have
6821 // legal vector types and such.
6822 if (DCI.isBeforeLegalizeOps())
6824 // Transform a scalar conversion of a value from a lane extract into a
6825 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6826 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6827 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6829 // The second form interacts better with instruction selection and the
6830 // register allocator to avoid cross-class register copies that aren't
6831 // coalescable due to a lane reference.
6833 // Check the operand and see if it originates from a lane extract.
6834 SDValue Op1 = N->getOperand(1);
6835 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6836 // Yep, no additional predication needed. Perform the transform.
6837 SDValue IID = N->getOperand(0);
6838 SDValue Shift = N->getOperand(2);
6839 SDValue Vec = Op1.getOperand(0);
6840 SDValue Lane = Op1.getOperand(1);
6841 EVT ResTy = N->getValueType(0);
6845 // The vector width should be 128 bits by the time we get here, even
6846 // if it started as 64 bits (the extract_vector handling will have
6848 assert(Vec.getValueType().getSizeInBits() == 128 &&
6849 "unexpected vector size on extract_vector_elt!");
6850 if (Vec.getValueType() == MVT::v4i32)
6851 VecResTy = MVT::v4f32;
6852 else if (Vec.getValueType() == MVT::v2i64)
6853 VecResTy = MVT::v2f64;
6855 llvm_unreachable("unexpected vector type!");
6858 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6859 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6864 // AArch64 high-vector "long" operations are formed by performing the non-high
6865 // version on an extract_subvector of each operand which gets the high half:
6867 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6869 // However, there are cases which don't have an extract_high explicitly, but
6870 // have another operation that can be made compatible with one for free. For
6873 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6875 // This routine does the actual conversion of such DUPs, once outer routines
6876 // have determined that everything else is in order.
6877 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6878 // We can handle most types of duplicate, but the lane ones have an extra
6879 // operand saying *which* lane, so we need to know.
6881 switch (N.getOpcode()) {
6882 case AArch64ISD::DUP:
6885 case AArch64ISD::DUPLANE8:
6886 case AArch64ISD::DUPLANE16:
6887 case AArch64ISD::DUPLANE32:
6888 case AArch64ISD::DUPLANE64:
6895 MVT NarrowTy = N.getSimpleValueType();
6896 if (!NarrowTy.is64BitVector())
6899 MVT ElementTy = NarrowTy.getVectorElementType();
6900 unsigned NumElems = NarrowTy.getVectorNumElements();
6901 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6905 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6908 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6910 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6911 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6914 static bool isEssentiallyExtractSubvector(SDValue N) {
6915 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6918 return N.getOpcode() == ISD::BITCAST &&
6919 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6922 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6923 struct GenericSetCCInfo {
6924 const SDValue *Opnd0;
6925 const SDValue *Opnd1;
6929 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6930 struct AArch64SetCCInfo {
6932 AArch64CC::CondCode CC;
6935 /// \brief Helper structure to keep track of SetCC information.
6937 GenericSetCCInfo Generic;
6938 AArch64SetCCInfo AArch64;
6941 /// \brief Helper structure to be able to read SetCC information. If set to
6942 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6943 /// GenericSetCCInfo.
6944 struct SetCCInfoAndKind {
6949 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6951 /// AArch64 lowered one.
6952 /// \p SetCCInfo is filled accordingly.
6953 /// \post SetCCInfo is meanginfull only when this function returns true.
6954 /// \return True when Op is a kind of SET_CC operation.
6955 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6956 // If this is a setcc, this is straight forward.
6957 if (Op.getOpcode() == ISD::SETCC) {
6958 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6959 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6960 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6961 SetCCInfo.IsAArch64 = false;
6964 // Otherwise, check if this is a matching csel instruction.
6968 if (Op.getOpcode() != AArch64ISD::CSEL)
6970 // Set the information about the operands.
6971 // TODO: we want the operands of the Cmp not the csel
6972 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6973 SetCCInfo.IsAArch64 = true;
6974 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6975 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6977 // Check that the operands matches the constraints:
6978 // (1) Both operands must be constants.
6979 // (2) One must be 1 and the other must be 0.
6980 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6981 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6984 if (!TValue || !FValue)
6988 if (!TValue->isOne()) {
6989 // Update the comparison when we are interested in !cc.
6990 std::swap(TValue, FValue);
6991 SetCCInfo.Info.AArch64.CC =
6992 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6994 return TValue->isOne() && FValue->isNullValue();
6997 // Returns true if Op is setcc or zext of setcc.
6998 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6999 if (isSetCC(Op, Info))
7001 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7002 isSetCC(Op->getOperand(0), Info));
7005 // The folding we want to perform is:
7006 // (add x, [zext] (setcc cc ...) )
7008 // (csel x, (add x, 1), !cc ...)
7010 // The latter will get matched to a CSINC instruction.
7011 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7012 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7013 SDValue LHS = Op->getOperand(0);
7014 SDValue RHS = Op->getOperand(1);
7015 SetCCInfoAndKind InfoAndKind;
7017 // If neither operand is a SET_CC, give up.
7018 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7019 std::swap(LHS, RHS);
7020 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7024 // FIXME: This could be generatized to work for FP comparisons.
7025 EVT CmpVT = InfoAndKind.IsAArch64
7026 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7027 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7028 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7034 if (InfoAndKind.IsAArch64) {
7035 CCVal = DAG.getConstant(
7036 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7037 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7039 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7040 *InfoAndKind.Info.Generic.Opnd1,
7041 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7044 EVT VT = Op->getValueType(0);
7045 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7046 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7049 // The basic add/sub long vector instructions have variants with "2" on the end
7050 // which act on the high-half of their inputs. They are normally matched by
7053 // (add (zeroext (extract_high LHS)),
7054 // (zeroext (extract_high RHS)))
7055 // -> uaddl2 vD, vN, vM
7057 // However, if one of the extracts is something like a duplicate, this
7058 // instruction can still be used profitably. This function puts the DAG into a
7059 // more appropriate form for those patterns to trigger.
7060 static SDValue performAddSubLongCombine(SDNode *N,
7061 TargetLowering::DAGCombinerInfo &DCI,
7062 SelectionDAG &DAG) {
7063 if (DCI.isBeforeLegalizeOps())
7066 MVT VT = N->getSimpleValueType(0);
7067 if (!VT.is128BitVector()) {
7068 if (N->getOpcode() == ISD::ADD)
7069 return performSetccAddFolding(N, DAG);
7073 // Make sure both branches are extended in the same way.
7074 SDValue LHS = N->getOperand(0);
7075 SDValue RHS = N->getOperand(1);
7076 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7077 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7078 LHS.getOpcode() != RHS.getOpcode())
7081 unsigned ExtType = LHS.getOpcode();
7083 // It's not worth doing if at least one of the inputs isn't already an
7084 // extract, but we don't know which it'll be so we have to try both.
7085 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7086 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7090 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7091 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7092 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7096 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7099 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7102 // Massage DAGs which we can use the high-half "long" operations on into
7103 // something isel will recognize better. E.g.
7105 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7106 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7107 // (extract_high (v2i64 (dup128 scalar)))))
7109 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7110 TargetLowering::DAGCombinerInfo &DCI,
7111 SelectionDAG &DAG) {
7112 if (DCI.isBeforeLegalizeOps())
7115 SDValue LHS = N->getOperand(1);
7116 SDValue RHS = N->getOperand(2);
7117 assert(LHS.getValueType().is64BitVector() &&
7118 RHS.getValueType().is64BitVector() &&
7119 "unexpected shape for long operation");
7121 // Either node could be a DUP, but it's not worth doing both of them (you'd
7122 // just as well use the non-high version) so look for a corresponding extract
7123 // operation on the other "wing".
7124 if (isEssentiallyExtractSubvector(LHS)) {
7125 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7128 } else if (isEssentiallyExtractSubvector(RHS)) {
7129 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7134 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7135 N->getOperand(0), LHS, RHS);
7138 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7139 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7140 unsigned ElemBits = ElemTy.getSizeInBits();
7142 int64_t ShiftAmount;
7143 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7144 APInt SplatValue, SplatUndef;
7145 unsigned SplatBitSize;
7147 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7148 HasAnyUndefs, ElemBits) ||
7149 SplatBitSize != ElemBits)
7152 ShiftAmount = SplatValue.getSExtValue();
7153 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7154 ShiftAmount = CVN->getSExtValue();
7162 llvm_unreachable("Unknown shift intrinsic");
7163 case Intrinsic::aarch64_neon_sqshl:
7164 Opcode = AArch64ISD::SQSHL_I;
7165 IsRightShift = false;
7167 case Intrinsic::aarch64_neon_uqshl:
7168 Opcode = AArch64ISD::UQSHL_I;
7169 IsRightShift = false;
7171 case Intrinsic::aarch64_neon_srshl:
7172 Opcode = AArch64ISD::SRSHR_I;
7173 IsRightShift = true;
7175 case Intrinsic::aarch64_neon_urshl:
7176 Opcode = AArch64ISD::URSHR_I;
7177 IsRightShift = true;
7179 case Intrinsic::aarch64_neon_sqshlu:
7180 Opcode = AArch64ISD::SQSHLU_I;
7181 IsRightShift = false;
7185 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7186 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7187 DAG.getConstant(-ShiftAmount, MVT::i32));
7188 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7189 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7190 DAG.getConstant(ShiftAmount, MVT::i32));
7195 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7196 // the intrinsics must be legal and take an i32, this means there's almost
7197 // certainly going to be a zext in the DAG which we can eliminate.
7198 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7199 SDValue AndN = N->getOperand(2);
7200 if (AndN.getOpcode() != ISD::AND)
7203 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7204 if (!CMask || CMask->getZExtValue() != Mask)
7207 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7208 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7211 static SDValue performIntrinsicCombine(SDNode *N,
7212 TargetLowering::DAGCombinerInfo &DCI,
7213 const AArch64Subtarget *Subtarget) {
7214 SelectionDAG &DAG = DCI.DAG;
7215 unsigned IID = getIntrinsicID(N);
7219 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7220 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7221 return tryCombineFixedPointConvert(N, DCI, DAG);
7223 case Intrinsic::aarch64_neon_fmax:
7224 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7225 N->getOperand(1), N->getOperand(2));
7226 case Intrinsic::aarch64_neon_fmin:
7227 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7228 N->getOperand(1), N->getOperand(2));
7229 case Intrinsic::aarch64_neon_smull:
7230 case Intrinsic::aarch64_neon_umull:
7231 case Intrinsic::aarch64_neon_pmull:
7232 case Intrinsic::aarch64_neon_sqdmull:
7233 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7234 case Intrinsic::aarch64_neon_sqshl:
7235 case Intrinsic::aarch64_neon_uqshl:
7236 case Intrinsic::aarch64_neon_sqshlu:
7237 case Intrinsic::aarch64_neon_srshl:
7238 case Intrinsic::aarch64_neon_urshl:
7239 return tryCombineShiftImm(IID, N, DAG);
7240 case Intrinsic::aarch64_crc32b:
7241 case Intrinsic::aarch64_crc32cb:
7242 return tryCombineCRC32(0xff, N, DAG);
7243 case Intrinsic::aarch64_crc32h:
7244 case Intrinsic::aarch64_crc32ch:
7245 return tryCombineCRC32(0xffff, N, DAG);
7250 static SDValue performExtendCombine(SDNode *N,
7251 TargetLowering::DAGCombinerInfo &DCI,
7252 SelectionDAG &DAG) {
7253 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7254 // we can convert that DUP into another extract_high (of a bigger DUP), which
7255 // helps the backend to decide that an sabdl2 would be useful, saving a real
7256 // extract_high operation.
7257 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7258 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7259 SDNode *ABDNode = N->getOperand(0).getNode();
7260 unsigned IID = getIntrinsicID(ABDNode);
7261 if (IID == Intrinsic::aarch64_neon_sabd ||
7262 IID == Intrinsic::aarch64_neon_uabd) {
7263 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7264 if (!NewABD.getNode())
7267 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7272 // This is effectively a custom type legalization for AArch64.
7274 // Type legalization will split an extend of a small, legal, type to a larger
7275 // illegal type by first splitting the destination type, often creating
7276 // illegal source types, which then get legalized in isel-confusing ways,
7277 // leading to really terrible codegen. E.g.,
7278 // %result = v8i32 sext v8i8 %value
7280 // %losrc = extract_subreg %value, ...
7281 // %hisrc = extract_subreg %value, ...
7282 // %lo = v4i32 sext v4i8 %losrc
7283 // %hi = v4i32 sext v4i8 %hisrc
7284 // Things go rapidly downhill from there.
7286 // For AArch64, the [sz]ext vector instructions can only go up one element
7287 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7288 // take two instructions.
7290 // This implies that the most efficient way to do the extend from v8i8
7291 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7292 // the normal splitting to happen for the v8i16->v8i32.
7294 // This is pre-legalization to catch some cases where the default
7295 // type legalization will create ill-tempered code.
7296 if (!DCI.isBeforeLegalizeOps())
7299 // We're only interested in cleaning things up for non-legal vector types
7300 // here. If both the source and destination are legal, things will just
7301 // work naturally without any fiddling.
7302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7303 EVT ResVT = N->getValueType(0);
7304 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7306 // If the vector type isn't a simple VT, it's beyond the scope of what
7307 // we're worried about here. Let legalization do its thing and hope for
7309 if (!ResVT.isSimple())
7312 SDValue Src = N->getOperand(0);
7313 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7314 // If the source VT is a 64-bit vector, we can play games and get the
7315 // better results we want.
7316 if (SrcVT.getSizeInBits() != 64)
7319 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7320 unsigned ElementCount = SrcVT.getVectorNumElements();
7321 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7323 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7325 // Now split the rest of the operation into two halves, each with a 64
7329 unsigned NumElements = ResVT.getVectorNumElements();
7330 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7331 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7332 ResVT.getVectorElementType(), NumElements / 2);
7334 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7335 LoVT.getVectorNumElements());
7336 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7337 DAG.getIntPtrConstant(0));
7338 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7339 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7340 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7341 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7343 // Now combine the parts back together so we still have a single result
7344 // like the combiner expects.
7345 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7348 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7349 /// value. The load store optimizer pass will merge them to store pair stores.
7350 /// This has better performance than a splat of the scalar followed by a split
7351 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7352 /// followed by an ext.b and two stores.
7353 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7354 SDValue StVal = St->getValue();
7355 EVT VT = StVal.getValueType();
7357 // Don't replace floating point stores, they possibly won't be transformed to
7358 // stp because of the store pair suppress pass.
7359 if (VT.isFloatingPoint())
7362 // Check for insert vector elements.
7363 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7366 // We can express a splat as store pair(s) for 2 or 4 elements.
7367 unsigned NumVecElts = VT.getVectorNumElements();
7368 if (NumVecElts != 4 && NumVecElts != 2)
7370 SDValue SplatVal = StVal.getOperand(1);
7371 unsigned RemainInsertElts = NumVecElts - 1;
7373 // Check that this is a splat.
7374 while (--RemainInsertElts) {
7375 SDValue NextInsertElt = StVal.getOperand(0);
7376 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7378 if (NextInsertElt.getOperand(1) != SplatVal)
7380 StVal = NextInsertElt;
7382 unsigned OrigAlignment = St->getAlignment();
7383 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7384 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7386 // Create scalar stores. This is at least as good as the code sequence for a
7387 // split unaligned store wich is a dup.s, ext.b, and two stores.
7388 // Most of the time the three stores should be replaced by store pair
7389 // instructions (stp).
7391 SDValue BasePtr = St->getBasePtr();
7393 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7394 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7396 unsigned Offset = EltOffset;
7397 while (--NumVecElts) {
7398 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7399 DAG.getConstant(Offset, MVT::i64));
7400 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7401 St->getPointerInfo(), St->isVolatile(),
7402 St->isNonTemporal(), Alignment);
7403 Offset += EltOffset;
7408 static SDValue performSTORECombine(SDNode *N,
7409 TargetLowering::DAGCombinerInfo &DCI,
7411 const AArch64Subtarget *Subtarget) {
7412 if (!DCI.isBeforeLegalize())
7415 StoreSDNode *S = cast<StoreSDNode>(N);
7416 if (S->isVolatile())
7419 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7420 // page boundries. We want to split such stores.
7421 if (!Subtarget->isCyclone())
7424 // Don't split at Oz.
7425 MachineFunction &MF = DAG.getMachineFunction();
7426 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7427 AttributeSet::FunctionIndex, Attribute::MinSize);
7431 SDValue StVal = S->getValue();
7432 EVT VT = StVal.getValueType();
7434 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7435 // those up regresses performance on micro-benchmarks and olden/bh.
7436 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7439 // Split unaligned 16B stores. They are terrible for performance.
7440 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7441 // extensions can use this to mark that it does not want splitting to happen
7442 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7443 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7444 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7445 S->getAlignment() <= 2)
7448 // If we get a splat of a scalar convert this vector store to a store of
7449 // scalars. They will be merged into store pairs thereby removing two
7451 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7452 if (ReplacedSplat != SDValue())
7453 return ReplacedSplat;
7456 unsigned NumElts = VT.getVectorNumElements() / 2;
7457 // Split VT into two.
7459 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7460 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7461 DAG.getIntPtrConstant(0));
7462 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7463 DAG.getIntPtrConstant(NumElts));
7464 SDValue BasePtr = S->getBasePtr();
7466 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7467 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7468 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7469 DAG.getConstant(8, MVT::i64));
7470 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7471 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7475 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7476 /// post-increment LD1R.
7477 static SDValue performPostLD1Combine(SDNode *N,
7478 TargetLowering::DAGCombinerInfo &DCI,
7480 if (DCI.isBeforeLegalizeOps())
7483 SelectionDAG &DAG = DCI.DAG;
7484 EVT VT = N->getValueType(0);
7486 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7487 SDNode *LD = N->getOperand(LoadIdx).getNode();
7488 // If it is not LOAD, can not do such combine.
7489 if (LD->getOpcode() != ISD::LOAD)
7492 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7493 EVT MemVT = LoadSDN->getMemoryVT();
7494 // Check if memory operand is the same type as the vector element.
7495 if (MemVT != VT.getVectorElementType())
7498 // Check if there are other uses. If so, do not combine as it will introduce
7500 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7502 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7508 SDValue Addr = LD->getOperand(1);
7509 SDValue Vector = N->getOperand(0);
7510 // Search for a use of the address operand that is an increment.
7511 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7512 Addr.getNode()->use_end(); UI != UE; ++UI) {
7514 if (User->getOpcode() != ISD::ADD
7515 || UI.getUse().getResNo() != Addr.getResNo())
7518 // Check that the add is independent of the load. Otherwise, folding it
7519 // would create a cycle.
7520 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7522 // Also check that add is not used in the vector operand. This would also
7524 if (User->isPredecessorOf(Vector.getNode()))
7527 // If the increment is a constant, it must match the memory ref size.
7528 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7529 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7530 uint32_t IncVal = CInc->getZExtValue();
7531 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7532 if (IncVal != NumBytes)
7534 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7537 SmallVector<SDValue, 8> Ops;
7538 Ops.push_back(LD->getOperand(0)); // Chain
7540 Ops.push_back(Vector); // The vector to be inserted
7541 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7543 Ops.push_back(Addr);
7546 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7547 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7548 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7549 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7551 LoadSDN->getMemOperand());
7554 std::vector<SDValue> NewResults;
7555 NewResults.push_back(SDValue(LD, 0)); // The result of load
7556 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7557 DCI.CombineTo(LD, NewResults);
7558 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7559 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7566 /// Target-specific DAG combine function for NEON load/store intrinsics
7567 /// to merge base address updates.
7568 static SDValue performNEONPostLDSTCombine(SDNode *N,
7569 TargetLowering::DAGCombinerInfo &DCI,
7570 SelectionDAG &DAG) {
7571 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7574 unsigned AddrOpIdx = N->getNumOperands() - 1;
7575 SDValue Addr = N->getOperand(AddrOpIdx);
7577 // Search for a use of the address operand that is an increment.
7578 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7579 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7581 if (User->getOpcode() != ISD::ADD ||
7582 UI.getUse().getResNo() != Addr.getResNo())
7585 // Check that the add is independent of the load/store. Otherwise, folding
7586 // it would create a cycle.
7587 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7590 // Find the new opcode for the updating load/store.
7591 bool IsStore = false;
7592 bool IsLaneOp = false;
7593 bool IsDupOp = false;
7594 unsigned NewOpc = 0;
7595 unsigned NumVecs = 0;
7596 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7598 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7599 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7601 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7603 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7605 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7606 NumVecs = 2; IsStore = true; break;
7607 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7608 NumVecs = 3; IsStore = true; break;
7609 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7610 NumVecs = 4; IsStore = true; break;
7611 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7613 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7615 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7617 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7618 NumVecs = 2; IsStore = true; break;
7619 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7620 NumVecs = 3; IsStore = true; break;
7621 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7622 NumVecs = 4; IsStore = true; break;
7623 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7624 NumVecs = 2; IsDupOp = true; break;
7625 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7626 NumVecs = 3; IsDupOp = true; break;
7627 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7628 NumVecs = 4; IsDupOp = true; break;
7629 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7630 NumVecs = 2; IsLaneOp = true; break;
7631 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7632 NumVecs = 3; IsLaneOp = true; break;
7633 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7634 NumVecs = 4; IsLaneOp = true; break;
7635 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7636 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7637 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7638 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7639 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7640 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7645 VecTy = N->getOperand(2).getValueType();
7647 VecTy = N->getValueType(0);
7649 // If the increment is a constant, it must match the memory ref size.
7650 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7651 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7652 uint32_t IncVal = CInc->getZExtValue();
7653 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7654 if (IsLaneOp || IsDupOp)
7655 NumBytes /= VecTy.getVectorNumElements();
7656 if (IncVal != NumBytes)
7658 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7660 SmallVector<SDValue, 8> Ops;
7661 Ops.push_back(N->getOperand(0)); // Incoming chain
7662 // Load lane and store have vector list as input.
7663 if (IsLaneOp || IsStore)
7664 for (unsigned i = 2; i < AddrOpIdx; ++i)
7665 Ops.push_back(N->getOperand(i));
7666 Ops.push_back(Addr); // Base register
7671 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7673 for (n = 0; n < NumResultVecs; ++n)
7675 Tys[n++] = MVT::i64; // Type of write back register
7676 Tys[n] = MVT::Other; // Type of the chain
7677 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7679 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7680 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7681 MemInt->getMemoryVT(),
7682 MemInt->getMemOperand());
7685 std::vector<SDValue> NewResults;
7686 for (unsigned i = 0; i < NumResultVecs; ++i) {
7687 NewResults.push_back(SDValue(UpdN.getNode(), i));
7689 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7690 DCI.CombineTo(N, NewResults);
7691 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7698 // Optimize compare with zero and branch.
7699 static SDValue performBRCONDCombine(SDNode *N,
7700 TargetLowering::DAGCombinerInfo &DCI,
7701 SelectionDAG &DAG) {
7702 SDValue Chain = N->getOperand(0);
7703 SDValue Dest = N->getOperand(1);
7704 SDValue CCVal = N->getOperand(2);
7705 SDValue Cmp = N->getOperand(3);
7707 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7708 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7709 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7712 unsigned CmpOpc = Cmp.getOpcode();
7713 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7716 // Only attempt folding if there is only one use of the flag and no use of the
7718 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7721 SDValue LHS = Cmp.getOperand(0);
7722 SDValue RHS = Cmp.getOperand(1);
7724 assert(LHS.getValueType() == RHS.getValueType() &&
7725 "Expected the value type to be the same for both operands!");
7726 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7729 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7730 std::swap(LHS, RHS);
7732 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7735 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7736 LHS.getOpcode() == ISD::SRL)
7739 // Fold the compare into the branch instruction.
7741 if (CC == AArch64CC::EQ)
7742 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7744 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7746 // Do not add new nodes to DAG combiner worklist.
7747 DCI.CombineTo(N, BR, false);
7752 // vselect (v1i1 setcc) ->
7753 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7754 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7755 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7757 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7758 SDValue N0 = N->getOperand(0);
7759 EVT CCVT = N0.getValueType();
7761 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7762 CCVT.getVectorElementType() != MVT::i1)
7765 EVT ResVT = N->getValueType(0);
7766 EVT CmpVT = N0.getOperand(0).getValueType();
7767 // Only combine when the result type is of the same size as the compared
7769 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7772 SDValue IfTrue = N->getOperand(1);
7773 SDValue IfFalse = N->getOperand(2);
7775 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7776 N0.getOperand(0), N0.getOperand(1),
7777 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7778 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7782 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7783 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7784 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7785 /// with a vector one followed by a DUP shuffle on the result.
7786 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7787 SDValue N0 = N->getOperand(0);
7788 EVT ResVT = N->getValueType(0);
7790 if (!N->getOperand(1).getValueType().isVector())
7793 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7798 EVT SrcVT = N0.getOperand(0).getValueType();
7799 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7800 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7801 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7803 // First perform a vector comparison, where lane 0 is the one we're interested
7806 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7808 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7809 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7811 // Now duplicate the comparison mask we want across all other lanes.
7812 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7813 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7814 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7817 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7820 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7821 DAGCombinerInfo &DCI) const {
7822 SelectionDAG &DAG = DCI.DAG;
7823 switch (N->getOpcode()) {
7828 return performAddSubLongCombine(N, DCI, DAG);
7830 return performXorCombine(N, DAG, DCI, Subtarget);
7832 return performMulCombine(N, DAG, DCI, Subtarget);
7833 case ISD::SINT_TO_FP:
7834 case ISD::UINT_TO_FP:
7835 return performIntToFpCombine(N, DAG);
7837 return performORCombine(N, DCI, Subtarget);
7838 case ISD::INTRINSIC_WO_CHAIN:
7839 return performIntrinsicCombine(N, DCI, Subtarget);
7840 case ISD::ANY_EXTEND:
7841 case ISD::ZERO_EXTEND:
7842 case ISD::SIGN_EXTEND:
7843 return performExtendCombine(N, DCI, DAG);
7845 return performBitcastCombine(N, DCI, DAG);
7846 case ISD::CONCAT_VECTORS:
7847 return performConcatVectorsCombine(N, DCI, DAG);
7849 return performSelectCombine(N, DAG);
7851 return performVSelectCombine(N, DCI.DAG);
7853 return performSTORECombine(N, DCI, DAG, Subtarget);
7854 case AArch64ISD::BRCOND:
7855 return performBRCONDCombine(N, DCI, DAG);
7856 case AArch64ISD::DUP:
7857 return performPostLD1Combine(N, DCI, false);
7858 case ISD::INSERT_VECTOR_ELT:
7859 return performPostLD1Combine(N, DCI, true);
7860 case ISD::INTRINSIC_VOID:
7861 case ISD::INTRINSIC_W_CHAIN:
7862 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7863 case Intrinsic::aarch64_neon_ld2:
7864 case Intrinsic::aarch64_neon_ld3:
7865 case Intrinsic::aarch64_neon_ld4:
7866 case Intrinsic::aarch64_neon_ld1x2:
7867 case Intrinsic::aarch64_neon_ld1x3:
7868 case Intrinsic::aarch64_neon_ld1x4:
7869 case Intrinsic::aarch64_neon_ld2lane:
7870 case Intrinsic::aarch64_neon_ld3lane:
7871 case Intrinsic::aarch64_neon_ld4lane:
7872 case Intrinsic::aarch64_neon_ld2r:
7873 case Intrinsic::aarch64_neon_ld3r:
7874 case Intrinsic::aarch64_neon_ld4r:
7875 case Intrinsic::aarch64_neon_st2:
7876 case Intrinsic::aarch64_neon_st3:
7877 case Intrinsic::aarch64_neon_st4:
7878 case Intrinsic::aarch64_neon_st1x2:
7879 case Intrinsic::aarch64_neon_st1x3:
7880 case Intrinsic::aarch64_neon_st1x4:
7881 case Intrinsic::aarch64_neon_st2lane:
7882 case Intrinsic::aarch64_neon_st3lane:
7883 case Intrinsic::aarch64_neon_st4lane:
7884 return performNEONPostLDSTCombine(N, DCI, DAG);
7892 // Check if the return value is used as only a return value, as otherwise
7893 // we can't perform a tail-call. In particular, we need to check for
7894 // target ISD nodes that are returns and any other "odd" constructs
7895 // that the generic analysis code won't necessarily catch.
7896 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7897 SDValue &Chain) const {
7898 if (N->getNumValues() != 1)
7900 if (!N->hasNUsesOfValue(1, 0))
7903 SDValue TCChain = Chain;
7904 SDNode *Copy = *N->use_begin();
7905 if (Copy->getOpcode() == ISD::CopyToReg) {
7906 // If the copy has a glue operand, we conservatively assume it isn't safe to
7907 // perform a tail call.
7908 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7911 TCChain = Copy->getOperand(0);
7912 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7915 bool HasRet = false;
7916 for (SDNode *Node : Copy->uses()) {
7917 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7929 // Return whether the an instruction can potentially be optimized to a tail
7930 // call. This will cause the optimizers to attempt to move, or duplicate,
7931 // return instructions to help enable tail call optimizations for this
7933 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7934 if (!CI->isTailCall())
7940 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7942 ISD::MemIndexedMode &AM,
7944 SelectionDAG &DAG) const {
7945 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7948 Base = Op->getOperand(0);
7949 // All of the indexed addressing mode instructions take a signed
7950 // 9 bit immediate offset.
7951 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7952 int64_t RHSC = (int64_t)RHS->getZExtValue();
7953 if (RHSC >= 256 || RHSC <= -256)
7955 IsInc = (Op->getOpcode() == ISD::ADD);
7956 Offset = Op->getOperand(1);
7962 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7964 ISD::MemIndexedMode &AM,
7965 SelectionDAG &DAG) const {
7968 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7969 VT = LD->getMemoryVT();
7970 Ptr = LD->getBasePtr();
7971 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7972 VT = ST->getMemoryVT();
7973 Ptr = ST->getBasePtr();
7978 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7980 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7984 bool AArch64TargetLowering::getPostIndexedAddressParts(
7985 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7986 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7989 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7990 VT = LD->getMemoryVT();
7991 Ptr = LD->getBasePtr();
7992 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7993 VT = ST->getMemoryVT();
7994 Ptr = ST->getBasePtr();
7999 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8001 // Post-indexing updates the base, so it's not a valid transform
8002 // if that's not the same as the load's pointer.
8005 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8009 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8010 SelectionDAG &DAG) {
8011 if (N->getValueType(0) != MVT::i16)
8015 SDValue Op = N->getOperand(0);
8016 assert(Op.getValueType() == MVT::f16 &&
8017 "Inconsistent bitcast? Only 16-bit types should be i16 or f16");
8019 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8020 DAG.getUNDEF(MVT::i32), Op,
8021 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8023 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8024 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8027 void AArch64TargetLowering::ReplaceNodeResults(
8028 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8029 switch (N->getOpcode()) {
8031 llvm_unreachable("Don't know how to custom expand this");
8033 ReplaceBITCASTResults(N, Results, DAG);
8035 case ISD::FP_TO_UINT:
8036 case ISD::FP_TO_SINT:
8037 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8038 // Let normal code take care of it by not adding anything to Results.
8043 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
8044 // Loads and stores less than 128-bits are already atomic; ones above that
8045 // are doomed anyway, so defer to the default libcall and blame the OS when
8047 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
8048 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
8049 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
8050 return LI->getType()->getPrimitiveSizeInBits() == 128;
8052 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
8053 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
8056 TargetLoweringBase::LegalizeTypeAction
8057 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8058 MVT SVT = VT.getSimpleVT();
8059 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8060 // v4i16, v2i32 instead of to promote.
8061 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8062 || SVT == MVT::v1f32)
8063 return TypeWidenVector;
8065 return TargetLoweringBase::getPreferredVectorAction(VT);
8068 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8069 AtomicOrdering Ord) const {
8070 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8071 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8073 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
8075 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8076 // intrinsic must return {i64, i64} and we have to recombine them into a
8077 // single i128 here.
8078 if (ValTy->getPrimitiveSizeInBits() == 128) {
8080 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8081 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8083 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8084 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8086 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8087 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8088 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8089 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8090 return Builder.CreateOr(
8091 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8094 Type *Tys[] = { Addr->getType() };
8096 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8097 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8099 return Builder.CreateTruncOrBitCast(
8100 Builder.CreateCall(Ldxr, Addr),
8101 cast<PointerType>(Addr->getType())->getElementType());
8104 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8105 Value *Val, Value *Addr,
8106 AtomicOrdering Ord) const {
8107 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8109 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
8111 // Since the intrinsics must have legal type, the i128 intrinsics take two
8112 // parameters: "i64, i64". We must marshal Val into the appropriate form
8114 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8116 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8117 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8118 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8120 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8121 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8122 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8123 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8127 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8128 Type *Tys[] = { Addr->getType() };
8129 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8131 return Builder.CreateCall2(
8132 Stxr, Builder.CreateZExtOrBitCast(
8133 Val, Stxr->getFunctionType()->getParamType(0)),