1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
43 // Place holder until extr generation is tested fully.
45 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
46 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
50 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
51 cl::desc("Allow AArch64 SLI/SRI formation"),
54 // FIXME: The necessary dtprel relocations don't seem to be supported
55 // well in the GNU bfd and gold linkers at the moment. Therefore, by
56 // default, for now, fall back to GeneralDynamic code generation.
57 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
58 "aarch64-elf-ldtls-generation", cl::Hidden,
59 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
62 /// Value type used for condition codes.
63 static const MVT MVT_CC = MVT::i32;
65 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
66 const AArch64Subtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
70 // we have to make something up. Arbitrarily, choose ZeroOrOne.
71 setBooleanContents(ZeroOrOneBooleanContent);
72 // When comparing vectors the result sets the different elements in the
73 // vector to all-one or all-zero.
74 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
78 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
80 if (Subtarget->hasFPARMv8()) {
81 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
82 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
83 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
84 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
87 if (Subtarget->hasNEON()) {
88 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
89 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
90 // Someone set us up the NEON.
91 addDRTypeForNEON(MVT::v2f32);
92 addDRTypeForNEON(MVT::v8i8);
93 addDRTypeForNEON(MVT::v4i16);
94 addDRTypeForNEON(MVT::v2i32);
95 addDRTypeForNEON(MVT::v1i64);
96 addDRTypeForNEON(MVT::v1f64);
97 addDRTypeForNEON(MVT::v4f16);
99 addQRTypeForNEON(MVT::v4f32);
100 addQRTypeForNEON(MVT::v2f64);
101 addQRTypeForNEON(MVT::v16i8);
102 addQRTypeForNEON(MVT::v8i16);
103 addQRTypeForNEON(MVT::v4i32);
104 addQRTypeForNEON(MVT::v2i64);
105 addQRTypeForNEON(MVT::v8f16);
108 // Compute derived properties from the register classes
109 computeRegisterProperties(Subtarget->getRegisterInfo());
111 // Provide all sorts of operation actions
112 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
120 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
121 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
122 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
123 setOperationAction(ISD::SELECT, MVT::i32, Custom);
124 setOperationAction(ISD::SELECT, MVT::i64, Custom);
125 setOperationAction(ISD::SELECT, MVT::f32, Custom);
126 setOperationAction(ISD::SELECT, MVT::f64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
131 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
135 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
136 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Expand);
139 setOperationAction(ISD::FREM, MVT::f64, Expand);
140 setOperationAction(ISD::FREM, MVT::f80, Expand);
142 // Custom lowering hooks are needed for XOR
143 // to fold it into CSINC/CSINV.
144 setOperationAction(ISD::XOR, MVT::i32, Custom);
145 setOperationAction(ISD::XOR, MVT::i64, Custom);
147 // Virtually no operation on f128 is legal, but LLVM can't expand them when
148 // there's a valid register class, so we need custom operations in most cases.
149 setOperationAction(ISD::FABS, MVT::f128, Expand);
150 setOperationAction(ISD::FADD, MVT::f128, Custom);
151 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
152 setOperationAction(ISD::FCOS, MVT::f128, Expand);
153 setOperationAction(ISD::FDIV, MVT::f128, Custom);
154 setOperationAction(ISD::FMA, MVT::f128, Expand);
155 setOperationAction(ISD::FMUL, MVT::f128, Custom);
156 setOperationAction(ISD::FNEG, MVT::f128, Expand);
157 setOperationAction(ISD::FPOW, MVT::f128, Expand);
158 setOperationAction(ISD::FREM, MVT::f128, Expand);
159 setOperationAction(ISD::FRINT, MVT::f128, Expand);
160 setOperationAction(ISD::FSIN, MVT::f128, Expand);
161 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
162 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
163 setOperationAction(ISD::FSUB, MVT::f128, Custom);
164 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
166 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
167 setOperationAction(ISD::SELECT, MVT::f128, Custom);
168 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
169 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
171 // Lowering for many of the conversions is actually specified by the non-f128
172 // type. The LowerXXX function will be trivial when f128 isn't involved.
173 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
177 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
178 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
182 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
183 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
184 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
186 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
188 // Variable arguments.
189 setOperationAction(ISD::VASTART, MVT::Other, Custom);
190 setOperationAction(ISD::VAARG, MVT::Other, Custom);
191 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
192 setOperationAction(ISD::VAEND, MVT::Other, Expand);
194 // Variable-sized objects.
195 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
196 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
197 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
199 // Exception handling.
200 // FIXME: These are guesses. Has this been defined yet?
201 setExceptionPointerRegister(AArch64::X0);
202 setExceptionSelectorRegister(AArch64::X1);
204 // Constant pool entries
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
208 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
210 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
211 setOperationAction(ISD::ADDC, MVT::i32, Custom);
212 setOperationAction(ISD::ADDE, MVT::i32, Custom);
213 setOperationAction(ISD::SUBC, MVT::i32, Custom);
214 setOperationAction(ISD::SUBE, MVT::i32, Custom);
215 setOperationAction(ISD::ADDC, MVT::i64, Custom);
216 setOperationAction(ISD::ADDE, MVT::i64, Custom);
217 setOperationAction(ISD::SUBC, MVT::i64, Custom);
218 setOperationAction(ISD::SUBE, MVT::i64, Custom);
220 // AArch64 lacks both left-rotate and popcount instructions.
221 setOperationAction(ISD::ROTL, MVT::i32, Expand);
222 setOperationAction(ISD::ROTL, MVT::i64, Expand);
224 // AArch64 doesn't have {U|S}MUL_LOHI.
225 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
226 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
229 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
230 // counterparts, which AArch64 supports directly.
231 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
232 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
233 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
234 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
236 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
237 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
239 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
240 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
241 setOperationAction(ISD::SREM, MVT::i32, Expand);
242 setOperationAction(ISD::SREM, MVT::i64, Expand);
243 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
244 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
245 setOperationAction(ISD::UREM, MVT::i32, Expand);
246 setOperationAction(ISD::UREM, MVT::i64, Expand);
248 // Custom lower Add/Sub/Mul with overflow.
249 setOperationAction(ISD::SADDO, MVT::i32, Custom);
250 setOperationAction(ISD::SADDO, MVT::i64, Custom);
251 setOperationAction(ISD::UADDO, MVT::i32, Custom);
252 setOperationAction(ISD::UADDO, MVT::i64, Custom);
253 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
254 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
255 setOperationAction(ISD::USUBO, MVT::i32, Custom);
256 setOperationAction(ISD::USUBO, MVT::i64, Custom);
257 setOperationAction(ISD::SMULO, MVT::i32, Custom);
258 setOperationAction(ISD::SMULO, MVT::i64, Custom);
259 setOperationAction(ISD::UMULO, MVT::i32, Custom);
260 setOperationAction(ISD::UMULO, MVT::i64, Custom);
262 setOperationAction(ISD::FSIN, MVT::f32, Expand);
263 setOperationAction(ISD::FSIN, MVT::f64, Expand);
264 setOperationAction(ISD::FCOS, MVT::f32, Expand);
265 setOperationAction(ISD::FCOS, MVT::f64, Expand);
266 setOperationAction(ISD::FPOW, MVT::f32, Expand);
267 setOperationAction(ISD::FPOW, MVT::f64, Expand);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
269 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
271 // f16 is a storage-only type, always promote it to f32.
272 setOperationAction(ISD::SETCC, MVT::f16, Promote);
273 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
274 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
275 setOperationAction(ISD::SELECT, MVT::f16, Promote);
276 setOperationAction(ISD::FADD, MVT::f16, Promote);
277 setOperationAction(ISD::FSUB, MVT::f16, Promote);
278 setOperationAction(ISD::FMUL, MVT::f16, Promote);
279 setOperationAction(ISD::FDIV, MVT::f16, Promote);
280 setOperationAction(ISD::FREM, MVT::f16, Promote);
281 setOperationAction(ISD::FMA, MVT::f16, Promote);
282 setOperationAction(ISD::FNEG, MVT::f16, Promote);
283 setOperationAction(ISD::FABS, MVT::f16, Promote);
284 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
285 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
286 setOperationAction(ISD::FCOS, MVT::f16, Promote);
287 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
288 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
289 setOperationAction(ISD::FPOW, MVT::f16, Promote);
290 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
291 setOperationAction(ISD::FRINT, MVT::f16, Promote);
292 setOperationAction(ISD::FSIN, MVT::f16, Promote);
293 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
294 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
295 setOperationAction(ISD::FEXP, MVT::f16, Promote);
296 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
297 setOperationAction(ISD::FLOG, MVT::f16, Promote);
298 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
299 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
300 setOperationAction(ISD::FROUND, MVT::f16, Promote);
301 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
302 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
303 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
305 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
307 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
308 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
309 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
310 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
311 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
312 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
313 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
314 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
315 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
316 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
317 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
318 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
320 // Expand all other v4f16 operations.
321 // FIXME: We could generate better code by promoting some operations to
323 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
324 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
325 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
328 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
329 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
330 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
331 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
332 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
333 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
334 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
335 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
336 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
337 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
338 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
339 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
340 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
341 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
342 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
343 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
344 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
345 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
346 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
347 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
348 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
351 // v8f16 is also a storage-only type, so expand it.
352 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
353 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
354 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
355 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
356 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
357 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
358 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
359 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
360 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
361 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
362 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
363 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
364 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
365 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
366 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
368 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
371 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
372 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
373 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
374 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
375 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
376 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
377 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
378 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
379 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
380 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
381 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
382 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
384 // AArch64 has implementations of a lot of rounding-like FP operations.
385 for (MVT Ty : {MVT::f32, MVT::f64}) {
386 setOperationAction(ISD::FFLOOR, Ty, Legal);
387 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
388 setOperationAction(ISD::FCEIL, Ty, Legal);
389 setOperationAction(ISD::FRINT, Ty, Legal);
390 setOperationAction(ISD::FTRUNC, Ty, Legal);
391 setOperationAction(ISD::FROUND, Ty, Legal);
394 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
396 if (Subtarget->isTargetMachO()) {
397 // For iOS, we don't want to the normal expansion of a libcall to
398 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
400 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
401 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
403 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
404 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
407 // Make floating-point constants legal for the large code model, so they don't
408 // become loads from the constant pool.
409 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
410 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
411 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
414 // AArch64 does not have floating-point extending loads, i1 sign-extending
415 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
416 for (MVT VT : MVT::fp_valuetypes()) {
417 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
418 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
419 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
420 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
422 for (MVT VT : MVT::integer_valuetypes())
423 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
425 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
426 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
427 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
428 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
429 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
430 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
431 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
433 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
434 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
436 // Indexed loads and stores are supported.
437 for (unsigned im = (unsigned)ISD::PRE_INC;
438 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
439 setIndexedLoadAction(im, MVT::i8, Legal);
440 setIndexedLoadAction(im, MVT::i16, Legal);
441 setIndexedLoadAction(im, MVT::i32, Legal);
442 setIndexedLoadAction(im, MVT::i64, Legal);
443 setIndexedLoadAction(im, MVT::f64, Legal);
444 setIndexedLoadAction(im, MVT::f32, Legal);
445 setIndexedStoreAction(im, MVT::i8, Legal);
446 setIndexedStoreAction(im, MVT::i16, Legal);
447 setIndexedStoreAction(im, MVT::i32, Legal);
448 setIndexedStoreAction(im, MVT::i64, Legal);
449 setIndexedStoreAction(im, MVT::f64, Legal);
450 setIndexedStoreAction(im, MVT::f32, Legal);
454 setOperationAction(ISD::TRAP, MVT::Other, Legal);
456 // We combine OR nodes for bitfield operations.
457 setTargetDAGCombine(ISD::OR);
459 // Vector add and sub nodes may conceal a high-half opportunity.
460 // Also, try to fold ADD into CSINC/CSINV..
461 setTargetDAGCombine(ISD::ADD);
462 setTargetDAGCombine(ISD::SUB);
464 setTargetDAGCombine(ISD::XOR);
465 setTargetDAGCombine(ISD::SINT_TO_FP);
466 setTargetDAGCombine(ISD::UINT_TO_FP);
468 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
470 setTargetDAGCombine(ISD::ANY_EXTEND);
471 setTargetDAGCombine(ISD::ZERO_EXTEND);
472 setTargetDAGCombine(ISD::SIGN_EXTEND);
473 setTargetDAGCombine(ISD::BITCAST);
474 setTargetDAGCombine(ISD::CONCAT_VECTORS);
475 setTargetDAGCombine(ISD::STORE);
477 setTargetDAGCombine(ISD::MUL);
479 setTargetDAGCombine(ISD::SELECT);
480 setTargetDAGCombine(ISD::VSELECT);
481 setTargetDAGCombine(ISD::SELECT_CC);
483 setTargetDAGCombine(ISD::INTRINSIC_VOID);
484 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
485 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
487 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
488 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
489 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
491 setStackPointerRegisterToSaveRestore(AArch64::SP);
493 setSchedulingPreference(Sched::Hybrid);
496 MaskAndBranchFoldingIsLegal = true;
497 EnableExtLdPromotion = true;
499 setMinFunctionAlignment(2);
501 setHasExtractBitsInsn(true);
503 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
505 if (Subtarget->hasNEON()) {
506 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
507 // silliness like this:
508 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
509 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
510 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
512 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
513 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
514 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
515 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
516 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
517 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
518 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
519 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
520 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
521 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
522 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
523 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
524 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
525 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
526 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
527 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
528 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
529 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
530 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
531 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
532 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
534 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
535 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
536 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
537 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
538 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
540 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
542 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
543 // elements smaller than i32, so promote the input to i32 first.
544 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
545 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
546 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
547 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
548 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
549 // -> v8f16 conversions.
550 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
551 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
552 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
553 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
554 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
555 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
556 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
557 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
559 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
560 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
561 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
562 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
564 // AArch64 doesn't have MUL.2d:
565 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
566 // Custom handling for some quad-vector types to detect MULL.
567 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
568 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
569 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
571 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
572 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
573 // Likewise, narrowing and extending vector loads/stores aren't handled
575 for (MVT VT : MVT::vector_valuetypes()) {
576 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
578 setOperationAction(ISD::MULHS, VT, Expand);
579 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
580 setOperationAction(ISD::MULHU, VT, Expand);
581 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
583 setOperationAction(ISD::BSWAP, VT, Expand);
585 for (MVT InnerVT : MVT::vector_valuetypes()) {
586 setTruncStoreAction(VT, InnerVT, Expand);
587 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
588 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
589 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
593 // AArch64 has implementations of a lot of rounding-like FP operations.
594 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
595 setOperationAction(ISD::FFLOOR, Ty, Legal);
596 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
597 setOperationAction(ISD::FCEIL, Ty, Legal);
598 setOperationAction(ISD::FRINT, Ty, Legal);
599 setOperationAction(ISD::FTRUNC, Ty, Legal);
600 setOperationAction(ISD::FROUND, Ty, Legal);
604 // Prefer likely predicted branches to selects on out-of-order cores.
605 if (Subtarget->isCortexA57())
606 PredictableSelectIsExpensive = true;
609 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
610 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
611 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
612 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
614 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
615 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
616 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
617 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
618 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
620 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
621 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
624 // Mark vector float intrinsics as expand.
625 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
626 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
627 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
633 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
636 // But we do support custom-lowering for FCOPYSIGN.
637 setOperationAction(ISD::FCOPYSIGN, VT.getSimpleVT(), Custom);
640 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
641 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
642 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
644 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
645 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
646 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
647 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
648 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
649 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
650 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
651 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
653 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
654 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
655 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
656 for (MVT InnerVT : MVT::all_valuetypes())
657 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
659 // CNT supports only B element sizes.
660 if (VT != MVT::v8i8 && VT != MVT::v16i8)
661 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
663 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
664 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
665 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
666 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
667 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
669 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
670 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
672 // [SU][MIN|MAX] and [SU]ABSDIFF are available for all NEON types apart from
674 if (!VT.isFloatingPoint() &&
675 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
676 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
677 ISD::SABSDIFF, ISD::UABSDIFF})
678 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
680 if (Subtarget->isLittleEndian()) {
681 for (unsigned im = (unsigned)ISD::PRE_INC;
682 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
683 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
684 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
689 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
690 addRegisterClass(VT, &AArch64::FPR64RegClass);
691 addTypeForNEON(VT, MVT::v2i32);
694 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
695 addRegisterClass(VT, &AArch64::FPR128RegClass);
696 addTypeForNEON(VT, MVT::v4i32);
699 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
703 return VT.changeVectorElementTypeToInteger();
706 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
707 /// Mask are known to be either zero or one and return them in the
708 /// KnownZero/KnownOne bitsets.
709 void AArch64TargetLowering::computeKnownBitsForTargetNode(
710 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
711 const SelectionDAG &DAG, unsigned Depth) const {
712 switch (Op.getOpcode()) {
715 case AArch64ISD::CSEL: {
716 APInt KnownZero2, KnownOne2;
717 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
718 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
719 KnownZero &= KnownZero2;
720 KnownOne &= KnownOne2;
723 case ISD::INTRINSIC_W_CHAIN: {
724 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
725 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
728 case Intrinsic::aarch64_ldaxr:
729 case Intrinsic::aarch64_ldxr: {
730 unsigned BitWidth = KnownOne.getBitWidth();
731 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
732 unsigned MemBits = VT.getScalarType().getSizeInBits();
733 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
739 case ISD::INTRINSIC_WO_CHAIN:
740 case ISD::INTRINSIC_VOID: {
741 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
745 case Intrinsic::aarch64_neon_umaxv:
746 case Intrinsic::aarch64_neon_uminv: {
747 // Figure out the datatype of the vector operand. The UMINV instruction
748 // will zero extend the result, so we can mark as known zero all the
749 // bits larger than the element datatype. 32-bit or larget doesn't need
750 // this as those are legal types and will be handled by isel directly.
751 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
752 unsigned BitWidth = KnownZero.getBitWidth();
753 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
754 assert(BitWidth >= 8 && "Unexpected width!");
755 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
757 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
758 assert(BitWidth >= 16 && "Unexpected width!");
759 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
769 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
774 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
778 if (Subtarget->requiresStrictAlign())
780 // FIXME: True for Cyclone, but not necessary others.
787 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
788 const TargetLibraryInfo *libInfo) const {
789 return AArch64::createFastISel(funcInfo, libInfo);
792 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
793 switch ((AArch64ISD::NodeType)Opcode) {
794 case AArch64ISD::FIRST_NUMBER: break;
795 case AArch64ISD::CALL: return "AArch64ISD::CALL";
796 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
797 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
798 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
799 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
800 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
801 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
802 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
803 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
804 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
805 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
806 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
807 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
808 case AArch64ISD::ADC: return "AArch64ISD::ADC";
809 case AArch64ISD::SBC: return "AArch64ISD::SBC";
810 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
811 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
812 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
813 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
814 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
815 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
816 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
817 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
818 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
819 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
820 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
821 case AArch64ISD::DUP: return "AArch64ISD::DUP";
822 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
823 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
824 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
825 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
826 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
827 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
828 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
829 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
830 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
831 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
832 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
833 case AArch64ISD::BICi: return "AArch64ISD::BICi";
834 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
835 case AArch64ISD::BSL: return "AArch64ISD::BSL";
836 case AArch64ISD::NEG: return "AArch64ISD::NEG";
837 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
838 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
839 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
840 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
841 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
842 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
843 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
844 case AArch64ISD::REV16: return "AArch64ISD::REV16";
845 case AArch64ISD::REV32: return "AArch64ISD::REV32";
846 case AArch64ISD::REV64: return "AArch64ISD::REV64";
847 case AArch64ISD::EXT: return "AArch64ISD::EXT";
848 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
849 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
850 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
851 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
852 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
853 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
854 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
855 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
856 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
857 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
858 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
859 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
860 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
861 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
862 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
863 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
864 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
865 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
866 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
867 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
868 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
869 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
870 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
871 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
872 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
873 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
874 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
875 case AArch64ISD::NOT: return "AArch64ISD::NOT";
876 case AArch64ISD::BIT: return "AArch64ISD::BIT";
877 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
878 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
879 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
880 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
881 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
882 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
883 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
884 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
885 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
886 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
887 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
888 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
889 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
890 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
891 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
892 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
893 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
894 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
895 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
896 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
897 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
898 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
899 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
900 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
901 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
902 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
903 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
904 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
905 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
906 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
907 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
908 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
909 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
910 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
911 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
912 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
913 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
914 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
915 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
916 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
922 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
923 MachineBasicBlock *MBB) const {
924 // We materialise the F128CSEL pseudo-instruction as some control flow and a
928 // [... previous instrs leading to comparison ...]
934 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
936 MachineFunction *MF = MBB->getParent();
937 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
938 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
939 DebugLoc DL = MI->getDebugLoc();
940 MachineFunction::iterator It = MBB;
943 unsigned DestReg = MI->getOperand(0).getReg();
944 unsigned IfTrueReg = MI->getOperand(1).getReg();
945 unsigned IfFalseReg = MI->getOperand(2).getReg();
946 unsigned CondCode = MI->getOperand(3).getImm();
947 bool NZCVKilled = MI->getOperand(4).isKill();
949 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
950 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
951 MF->insert(It, TrueBB);
952 MF->insert(It, EndBB);
954 // Transfer rest of current basic-block to EndBB
955 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
957 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
959 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
960 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
961 MBB->addSuccessor(TrueBB);
962 MBB->addSuccessor(EndBB);
964 // TrueBB falls through to the end.
965 TrueBB->addSuccessor(EndBB);
968 TrueBB->addLiveIn(AArch64::NZCV);
969 EndBB->addLiveIn(AArch64::NZCV);
972 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
978 MI->eraseFromParent();
983 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
984 MachineBasicBlock *BB) const {
985 switch (MI->getOpcode()) {
990 llvm_unreachable("Unexpected instruction for custom inserter!");
992 case AArch64::F128CSEL:
993 return EmitF128CSEL(MI, BB);
995 case TargetOpcode::STACKMAP:
996 case TargetOpcode::PATCHPOINT:
997 return emitPatchPoint(MI, BB);
1001 //===----------------------------------------------------------------------===//
1002 // AArch64 Lowering private implementation.
1003 //===----------------------------------------------------------------------===//
1005 //===----------------------------------------------------------------------===//
1007 //===----------------------------------------------------------------------===//
1009 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1011 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1014 llvm_unreachable("Unknown condition code!");
1016 return AArch64CC::NE;
1018 return AArch64CC::EQ;
1020 return AArch64CC::GT;
1022 return AArch64CC::GE;
1024 return AArch64CC::LT;
1026 return AArch64CC::LE;
1028 return AArch64CC::HI;
1030 return AArch64CC::HS;
1032 return AArch64CC::LO;
1034 return AArch64CC::LS;
1038 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1039 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1040 AArch64CC::CondCode &CondCode,
1041 AArch64CC::CondCode &CondCode2) {
1042 CondCode2 = AArch64CC::AL;
1045 llvm_unreachable("Unknown FP condition!");
1048 CondCode = AArch64CC::EQ;
1052 CondCode = AArch64CC::GT;
1056 CondCode = AArch64CC::GE;
1059 CondCode = AArch64CC::MI;
1062 CondCode = AArch64CC::LS;
1065 CondCode = AArch64CC::MI;
1066 CondCode2 = AArch64CC::GT;
1069 CondCode = AArch64CC::VC;
1072 CondCode = AArch64CC::VS;
1075 CondCode = AArch64CC::EQ;
1076 CondCode2 = AArch64CC::VS;
1079 CondCode = AArch64CC::HI;
1082 CondCode = AArch64CC::PL;
1086 CondCode = AArch64CC::LT;
1090 CondCode = AArch64CC::LE;
1094 CondCode = AArch64CC::NE;
1099 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1100 /// CC usable with the vector instructions. Fewer operations are available
1101 /// without a real NZCV register, so we have to use less efficient combinations
1102 /// to get the same effect.
1103 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1104 AArch64CC::CondCode &CondCode,
1105 AArch64CC::CondCode &CondCode2,
1110 // Mostly the scalar mappings work fine.
1111 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1114 Invert = true; // Fallthrough
1116 CondCode = AArch64CC::MI;
1117 CondCode2 = AArch64CC::GE;
1124 // All of the compare-mask comparisons are ordered, but we can switch
1125 // between the two by a double inversion. E.g. ULE == !OGT.
1127 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1132 static bool isLegalArithImmed(uint64_t C) {
1133 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1134 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1137 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1138 SDLoc dl, SelectionDAG &DAG) {
1139 EVT VT = LHS.getValueType();
1141 if (VT.isFloatingPoint())
1142 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1144 // The CMP instruction is just an alias for SUBS, and representing it as
1145 // SUBS means that it's possible to get CSE with subtract operations.
1146 // A later phase can perform the optimization of setting the destination
1147 // register to WZR/XZR if it ends up being unused.
1148 unsigned Opcode = AArch64ISD::SUBS;
1150 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1151 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1152 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1153 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1154 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1155 // can be set differently by this operation. It comes down to whether
1156 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1157 // everything is fine. If not then the optimization is wrong. Thus general
1158 // comparisons are only valid if op2 != 0.
1160 // So, finally, the only LLVM-native comparisons that don't mention C and V
1161 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1162 // the absence of information about op2.
1163 Opcode = AArch64ISD::ADDS;
1164 RHS = RHS.getOperand(1);
1165 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1166 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1167 !isUnsignedIntSetCC(CC)) {
1168 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1169 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1170 // of the signed comparisons.
1171 Opcode = AArch64ISD::ANDS;
1172 RHS = LHS.getOperand(1);
1173 LHS = LHS.getOperand(0);
1176 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1180 /// \defgroup AArch64CCMP CMP;CCMP matching
1182 /// These functions deal with the formation of CMP;CCMP;... sequences.
1183 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1184 /// a comparison. They set the NZCV flags to a predefined value if their
1185 /// predicate is false. This allows to express arbitrary conjunctions, for
1186 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1189 /// ccmp B, inv(CB), CA
1190 /// check for CB flags
1192 /// In general we can create code for arbitrary "... (and (and A B) C)"
1193 /// sequences. We can also implement some "or" expressions, because "(or A B)"
1194 /// is equivalent to "not (and (not A) (not B))" and we can implement some
1195 /// negation operations:
1196 /// We can negate the results of a single comparison by inverting the flags
1197 /// used when the predicate fails and inverting the flags tested in the next
1198 /// instruction; We can also negate the results of the whole previous
1199 /// conditional compare sequence by inverting the flags tested in the next
1200 /// instruction. However there is no way to negate the result of a partial
1203 /// Therefore on encountering an "or" expression we can negate the subtree on
1204 /// one side and have to be able to push the negate to the leafs of the subtree
1205 /// on the other side (see also the comments in code). As complete example:
1206 /// "or (or (setCA (cmp A)) (setCB (cmp B)))
1207 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1208 /// is transformed to
1209 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1210 /// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1211 /// and implemented as:
1213 /// ccmp D, inv(CD), CC
1214 /// ccmp A, CA, inv(CD)
1215 /// ccmp B, CB, inv(CA)
1216 /// check for CB flags
1217 /// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1218 /// by conditional compare sequences.
1221 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1222 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1223 ISD::CondCode CC, SDValue CCOp,
1224 SDValue Condition, unsigned NZCV,
1225 SDLoc DL, SelectionDAG &DAG) {
1226 unsigned Opcode = 0;
1227 if (LHS.getValueType().isFloatingPoint())
1228 Opcode = AArch64ISD::FCCMP;
1229 else if (RHS.getOpcode() == ISD::SUB) {
1230 SDValue SubOp0 = RHS.getOperand(0);
1231 if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
1232 if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1233 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1234 Opcode = AArch64ISD::CCMN;
1235 RHS = RHS.getOperand(1);
1239 Opcode = AArch64ISD::CCMP;
1241 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1242 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1245 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1246 /// CanPushNegate is set to true if we can push a negate operation through
1247 /// the tree in a was that we are left with AND operations and negate operations
1248 /// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1249 /// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1250 /// brought into such a form.
1251 static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
1252 unsigned Depth = 0) {
1253 if (!Val.hasOneUse())
1255 unsigned Opcode = Val->getOpcode();
1256 if (Opcode == ISD::SETCC) {
1257 CanPushNegate = true;
1260 // Protect against stack overflow.
1263 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1264 SDValue O0 = Val->getOperand(0);
1265 SDValue O1 = Val->getOperand(1);
1266 bool CanPushNegateL;
1267 if (!isConjunctionDisjunctionTree(O0, CanPushNegateL, Depth+1))
1269 bool CanPushNegateR;
1270 if (!isConjunctionDisjunctionTree(O1, CanPushNegateR, Depth+1))
1272 // We cannot push a negate through an AND operation (it would become an OR),
1273 // we can however change a (not (or x y)) to (and (not x) (not y)) if we can
1274 // push the negate through the x/y subtrees.
1275 CanPushNegate = (Opcode == ISD::OR) && CanPushNegateL && CanPushNegateR;
1281 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1282 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1283 /// Tries to transform the given i1 producing node @p Val to a series compare
1284 /// and conditional compare operations. @returns an NZCV flags producing node
1285 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1286 /// transformation was not possible.
1287 /// On recursive invocations @p PushNegate may be set to true to have negation
1288 /// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1289 /// for the comparisons in the current subtree; @p Depth limits the search
1290 /// depth to avoid stack overflow.
1291 static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1292 AArch64CC::CondCode &OutCC, bool PushNegate = false,
1293 SDValue CCOp = SDValue(), AArch64CC::CondCode Predicate = AArch64CC::AL,
1294 unsigned Depth = 0) {
1295 // We're at a tree leaf, produce a conditional comparison operation.
1296 unsigned Opcode = Val->getOpcode();
1297 if (Opcode == ISD::SETCC) {
1298 SDValue LHS = Val->getOperand(0);
1299 SDValue RHS = Val->getOperand(1);
1300 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1301 bool isInteger = LHS.getValueType().isInteger();
1303 CC = getSetCCInverse(CC, isInteger);
1305 // Determine OutCC and handle FP special case.
1307 OutCC = changeIntCCToAArch64CC(CC);
1309 assert(LHS.getValueType().isFloatingPoint());
1310 AArch64CC::CondCode ExtraCC;
1311 changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
1312 // Surpisingly some floating point conditions can't be tested with a
1313 // single condition code. Construct an additional comparison in this case.
1314 // See comment below on how we deal with OR conditions.
1315 if (ExtraCC != AArch64CC::AL) {
1317 if (!CCOp.getNode())
1318 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1320 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1321 // Note that we want the inverse of ExtraCC, so NZCV is not inversed.
1322 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
1323 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
1327 Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
1328 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1332 // Produce a normal comparison if we are first in the chain
1333 if (!CCOp.getNode())
1334 return emitComparison(LHS, RHS, CC, DL, DAG);
1335 // Otherwise produce a ccmp.
1336 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1337 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1338 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1339 return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
1341 } else if (Opcode != ISD::AND && Opcode != ISD::OR)
1344 assert((Opcode == ISD::OR || !PushNegate)
1345 && "Can only push negate through OR operation");
1347 // Check if both sides can be transformed.
1348 SDValue LHS = Val->getOperand(0);
1349 SDValue RHS = Val->getOperand(1);
1350 bool CanPushNegateL;
1351 if (!isConjunctionDisjunctionTree(LHS, CanPushNegateL, Depth+1))
1353 bool CanPushNegateR;
1354 if (!isConjunctionDisjunctionTree(RHS, CanPushNegateR, Depth+1))
1357 // Do we need to negate our operands?
1358 bool NegateOperands = Opcode == ISD::OR;
1359 // We can negate the results of all previous operations by inverting the
1360 // predicate flags giving us a free negation for one side. For the other side
1361 // we need to be able to push the negation to the leafs of the tree.
1362 if (NegateOperands) {
1363 if (!CanPushNegateL && !CanPushNegateR)
1365 // Order the side where we can push the negate through to LHS.
1366 if (!CanPushNegateL && CanPushNegateR) {
1367 std::swap(LHS, RHS);
1368 CanPushNegateL = true;
1372 // Emit RHS. If we want to negate the tree we only need to push a negate
1373 // through if we are already in a PushNegate case, otherwise we can negate
1374 // the "flags to test" afterwards.
1375 AArch64CC::CondCode RHSCC;
1376 SDValue CmpR = emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, PushNegate,
1377 CCOp, Predicate, Depth+1);
1378 if (NegateOperands && !PushNegate)
1379 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1380 // Emit LHS. We must push the negate through if we need to negate it.
1381 SDValue CmpL = emitConjunctionDisjunctionTree(DAG, LHS, OutCC, NegateOperands,
1382 CmpR, RHSCC, Depth+1);
1383 // If we transformed an OR to and AND then we have to negate the result
1384 // (or absorb a PushNegate resulting in a double negation).
1385 if (Opcode == ISD::OR && !PushNegate)
1386 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1392 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1393 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1394 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1395 EVT VT = RHS.getValueType();
1396 uint64_t C = RHSC->getZExtValue();
1397 if (!isLegalArithImmed(C)) {
1398 // Constant does not fit, try adjusting it by one?
1404 if ((VT == MVT::i32 && C != 0x80000000 &&
1405 isLegalArithImmed((uint32_t)(C - 1))) ||
1406 (VT == MVT::i64 && C != 0x80000000ULL &&
1407 isLegalArithImmed(C - 1ULL))) {
1408 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1409 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1410 RHS = DAG.getConstant(C, dl, VT);
1415 if ((VT == MVT::i32 && C != 0 &&
1416 isLegalArithImmed((uint32_t)(C - 1))) ||
1417 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1418 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1419 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1420 RHS = DAG.getConstant(C, dl, VT);
1425 if ((VT == MVT::i32 && C != INT32_MAX &&
1426 isLegalArithImmed((uint32_t)(C + 1))) ||
1427 (VT == MVT::i64 && C != INT64_MAX &&
1428 isLegalArithImmed(C + 1ULL))) {
1429 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1430 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1431 RHS = DAG.getConstant(C, dl, VT);
1436 if ((VT == MVT::i32 && C != UINT32_MAX &&
1437 isLegalArithImmed((uint32_t)(C + 1))) ||
1438 (VT == MVT::i64 && C != UINT64_MAX &&
1439 isLegalArithImmed(C + 1ULL))) {
1440 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1441 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1442 RHS = DAG.getConstant(C, dl, VT);
1449 AArch64CC::CondCode AArch64CC;
1450 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1451 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1453 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1454 // For the i8 operand, the largest immediate is 255, so this can be easily
1455 // encoded in the compare instruction. For the i16 operand, however, the
1456 // largest immediate cannot be encoded in the compare.
1457 // Therefore, use a sign extending load and cmn to avoid materializing the
1458 // -1 constant. For example,
1460 // ldrh w0, [x0, #0]
1463 // ldrsh w0, [x0, #0]
1465 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1466 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1467 // ensure both the LHS and RHS are truely zero extended and to make sure the
1468 // transformation is profitable.
1469 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1470 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1471 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1472 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1473 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1474 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1476 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1477 DAG.getValueType(MVT::i16));
1478 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1479 RHS.getValueType()),
1481 AArch64CC = changeIntCCToAArch64CC(CC);
1485 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1486 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1487 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1488 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1494 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1495 AArch64CC = changeIntCCToAArch64CC(CC);
1497 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1501 static std::pair<SDValue, SDValue>
1502 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1503 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1504 "Unsupported value type");
1505 SDValue Value, Overflow;
1507 SDValue LHS = Op.getOperand(0);
1508 SDValue RHS = Op.getOperand(1);
1510 switch (Op.getOpcode()) {
1512 llvm_unreachable("Unknown overflow instruction!");
1514 Opc = AArch64ISD::ADDS;
1518 Opc = AArch64ISD::ADDS;
1522 Opc = AArch64ISD::SUBS;
1526 Opc = AArch64ISD::SUBS;
1529 // Multiply needs a little bit extra work.
1533 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1534 if (Op.getValueType() == MVT::i32) {
1535 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1536 // For a 32 bit multiply with overflow check we want the instruction
1537 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1538 // need to generate the following pattern:
1539 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1540 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1541 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1542 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1543 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1544 DAG.getConstant(0, DL, MVT::i64));
1545 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1546 // operation. We need to clear out the upper 32 bits, because we used a
1547 // widening multiply that wrote all 64 bits. In the end this should be a
1549 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1551 // The signed overflow check requires more than just a simple check for
1552 // any bit set in the upper 32 bits of the result. These bits could be
1553 // just the sign bits of a negative number. To perform the overflow
1554 // check we have to arithmetic shift right the 32nd bit of the result by
1555 // 31 bits. Then we compare the result to the upper 32 bits.
1556 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1557 DAG.getConstant(32, DL, MVT::i64));
1558 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1559 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1560 DAG.getConstant(31, DL, MVT::i64));
1561 // It is important that LowerBits is last, otherwise the arithmetic
1562 // shift will not be folded into the compare (SUBS).
1563 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1564 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1567 // The overflow check for unsigned multiply is easy. We only need to
1568 // check if any of the upper 32 bits are set. This can be done with a
1569 // CMP (shifted register). For that we need to generate the following
1571 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1572 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1573 DAG.getConstant(32, DL, MVT::i64));
1574 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1576 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1577 DAG.getConstant(0, DL, MVT::i64),
1578 UpperBits).getValue(1);
1582 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1583 // For the 64 bit multiply
1584 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1586 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1587 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1588 DAG.getConstant(63, DL, MVT::i64));
1589 // It is important that LowerBits is last, otherwise the arithmetic
1590 // shift will not be folded into the compare (SUBS).
1591 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1592 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1595 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1596 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1598 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1599 DAG.getConstant(0, DL, MVT::i64),
1600 UpperBits).getValue(1);
1607 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1609 // Emit the AArch64 operation with overflow check.
1610 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1611 Overflow = Value.getValue(1);
1613 return std::make_pair(Value, Overflow);
1616 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1617 RTLIB::Libcall Call) const {
1618 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1619 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1623 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1624 SDValue Sel = Op.getOperand(0);
1625 SDValue Other = Op.getOperand(1);
1627 // If neither operand is a SELECT_CC, give up.
1628 if (Sel.getOpcode() != ISD::SELECT_CC)
1629 std::swap(Sel, Other);
1630 if (Sel.getOpcode() != ISD::SELECT_CC)
1633 // The folding we want to perform is:
1634 // (xor x, (select_cc a, b, cc, 0, -1) )
1636 // (csel x, (xor x, -1), cc ...)
1638 // The latter will get matched to a CSINV instruction.
1640 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1641 SDValue LHS = Sel.getOperand(0);
1642 SDValue RHS = Sel.getOperand(1);
1643 SDValue TVal = Sel.getOperand(2);
1644 SDValue FVal = Sel.getOperand(3);
1647 // FIXME: This could be generalized to non-integer comparisons.
1648 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1651 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1652 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1654 // The values aren't constants, this isn't the pattern we're looking for.
1655 if (!CFVal || !CTVal)
1658 // We can commute the SELECT_CC by inverting the condition. This
1659 // might be needed to make this fit into a CSINV pattern.
1660 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1661 std::swap(TVal, FVal);
1662 std::swap(CTVal, CFVal);
1663 CC = ISD::getSetCCInverse(CC, true);
1666 // If the constants line up, perform the transform!
1667 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1669 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1672 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1673 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1675 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1682 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1683 EVT VT = Op.getValueType();
1685 // Let legalize expand this if it isn't a legal type yet.
1686 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1689 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1692 bool ExtraOp = false;
1693 switch (Op.getOpcode()) {
1695 llvm_unreachable("Invalid code");
1697 Opc = AArch64ISD::ADDS;
1700 Opc = AArch64ISD::SUBS;
1703 Opc = AArch64ISD::ADCS;
1707 Opc = AArch64ISD::SBCS;
1713 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1714 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1718 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1719 // Let legalize expand this if it isn't a legal type yet.
1720 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1724 AArch64CC::CondCode CC;
1725 // The actual operation that sets the overflow or carry flag.
1726 SDValue Value, Overflow;
1727 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1729 // We use 0 and 1 as false and true values.
1730 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1731 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1733 // We use an inverted condition, because the conditional select is inverted
1734 // too. This will allow it to be selected to a single instruction:
1735 // CSINC Wd, WZR, WZR, invert(cond).
1736 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1737 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1740 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1741 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1744 // Prefetch operands are:
1745 // 1: Address to prefetch
1747 // 3: int locality (0 = no locality ... 3 = extreme locality)
1748 // 4: bool isDataCache
1749 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1751 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1752 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1753 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1755 bool IsStream = !Locality;
1756 // When the locality number is set
1758 // The front-end should have filtered out the out-of-range values
1759 assert(Locality <= 3 && "Prefetch locality out-of-range");
1760 // The locality degree is the opposite of the cache speed.
1761 // Put the number the other way around.
1762 // The encoding starts at 0 for level 1
1763 Locality = 3 - Locality;
1766 // built the mask value encoding the expected behavior.
1767 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1768 (!IsData << 3) | // IsDataCache bit
1769 (Locality << 1) | // Cache level bits
1770 (unsigned)IsStream; // Stream bit
1771 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1772 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1775 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1776 SelectionDAG &DAG) const {
1777 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1780 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1782 return LowerF128Call(Op, DAG, LC);
1785 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1786 SelectionDAG &DAG) const {
1787 if (Op.getOperand(0).getValueType() != MVT::f128) {
1788 // It's legal except when f128 is involved
1793 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1795 // FP_ROUND node has a second operand indicating whether it is known to be
1796 // precise. That doesn't take part in the LibCall so we can't directly use
1798 SDValue SrcVal = Op.getOperand(0);
1799 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1800 /*isSigned*/ false, SDLoc(Op)).first;
1803 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1804 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1805 // Any additional optimization in this function should be recorded
1806 // in the cost tables.
1807 EVT InVT = Op.getOperand(0).getValueType();
1808 EVT VT = Op.getValueType();
1810 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1813 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1815 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1818 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1821 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1822 VT.getVectorNumElements());
1823 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1824 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1827 // Type changing conversions are illegal.
1831 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1832 SelectionDAG &DAG) const {
1833 if (Op.getOperand(0).getValueType().isVector())
1834 return LowerVectorFP_TO_INT(Op, DAG);
1836 // f16 conversions are promoted to f32.
1837 if (Op.getOperand(0).getValueType() == MVT::f16) {
1840 Op.getOpcode(), dl, Op.getValueType(),
1841 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1844 if (Op.getOperand(0).getValueType() != MVT::f128) {
1845 // It's legal except when f128 is involved
1850 if (Op.getOpcode() == ISD::FP_TO_SINT)
1851 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1853 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1855 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1856 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1860 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1861 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1862 // Any additional optimization in this function should be recorded
1863 // in the cost tables.
1864 EVT VT = Op.getValueType();
1866 SDValue In = Op.getOperand(0);
1867 EVT InVT = In.getValueType();
1869 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1871 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1872 InVT.getVectorNumElements());
1873 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1874 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1877 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1879 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1880 EVT CastVT = VT.changeVectorElementTypeToInteger();
1881 In = DAG.getNode(CastOpc, dl, CastVT, In);
1882 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1888 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1889 SelectionDAG &DAG) const {
1890 if (Op.getValueType().isVector())
1891 return LowerVectorINT_TO_FP(Op, DAG);
1893 // f16 conversions are promoted to f32.
1894 if (Op.getValueType() == MVT::f16) {
1897 ISD::FP_ROUND, dl, MVT::f16,
1898 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1899 DAG.getIntPtrConstant(0, dl));
1902 // i128 conversions are libcalls.
1903 if (Op.getOperand(0).getValueType() == MVT::i128)
1906 // Other conversions are legal, unless it's to the completely software-based
1908 if (Op.getValueType() != MVT::f128)
1912 if (Op.getOpcode() == ISD::SINT_TO_FP)
1913 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1915 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1917 return LowerF128Call(Op, DAG, LC);
1920 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1921 SelectionDAG &DAG) const {
1922 // For iOS, we want to call an alternative entry point: __sincos_stret,
1923 // which returns the values in two S / D registers.
1925 SDValue Arg = Op.getOperand(0);
1926 EVT ArgVT = Arg.getValueType();
1927 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1934 Entry.isSExt = false;
1935 Entry.isZExt = false;
1936 Args.push_back(Entry);
1938 const char *LibcallName =
1939 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1941 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
1943 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1944 TargetLowering::CallLoweringInfo CLI(DAG);
1945 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1946 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1948 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1949 return CallResult.first;
1952 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1953 if (Op.getValueType() != MVT::f16)
1956 assert(Op.getOperand(0).getValueType() == MVT::i16);
1959 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1960 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1962 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1963 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1967 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1968 if (OrigVT.getSizeInBits() >= 64)
1971 assert(OrigVT.isSimple() && "Expecting a simple value type");
1973 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1974 switch (OrigSimpleTy) {
1975 default: llvm_unreachable("Unexpected Vector Type");
1984 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1987 unsigned ExtOpcode) {
1988 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1989 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1990 // 64-bits we need to insert a new extension so that it will be 64-bits.
1991 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1992 if (OrigTy.getSizeInBits() >= 64)
1995 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1996 EVT NewVT = getExtensionTo64Bits(OrigTy);
1998 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
2001 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2003 EVT VT = N->getValueType(0);
2005 if (N->getOpcode() != ISD::BUILD_VECTOR)
2008 for (const SDValue &Elt : N->op_values()) {
2009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2010 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2011 unsigned HalfSize = EltSize / 2;
2013 if (!isIntN(HalfSize, C->getSExtValue()))
2016 if (!isUIntN(HalfSize, C->getZExtValue()))
2027 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2028 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2029 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2030 N->getOperand(0)->getValueType(0),
2034 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2035 EVT VT = N->getValueType(0);
2037 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
2038 unsigned NumElts = VT.getVectorNumElements();
2039 MVT TruncVT = MVT::getIntegerVT(EltSize);
2040 SmallVector<SDValue, 8> Ops;
2041 for (unsigned i = 0; i != NumElts; ++i) {
2042 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2043 const APInt &CInt = C->getAPIntValue();
2044 // Element types smaller than 32 bits are not legal, so use i32 elements.
2045 // The values are implicitly truncated so sext vs. zext doesn't matter.
2046 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2048 return DAG.getNode(ISD::BUILD_VECTOR, dl,
2049 MVT::getVectorVT(TruncVT, NumElts), Ops);
2052 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2053 if (N->getOpcode() == ISD::SIGN_EXTEND)
2055 if (isExtendedBUILD_VECTOR(N, DAG, true))
2060 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2061 if (N->getOpcode() == ISD::ZERO_EXTEND)
2063 if (isExtendedBUILD_VECTOR(N, DAG, false))
2068 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2069 unsigned Opcode = N->getOpcode();
2070 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2071 SDNode *N0 = N->getOperand(0).getNode();
2072 SDNode *N1 = N->getOperand(1).getNode();
2073 return N0->hasOneUse() && N1->hasOneUse() &&
2074 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2079 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2080 unsigned Opcode = N->getOpcode();
2081 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2082 SDNode *N0 = N->getOperand(0).getNode();
2083 SDNode *N1 = N->getOperand(1).getNode();
2084 return N0->hasOneUse() && N1->hasOneUse() &&
2085 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2090 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2091 // Multiplications are only custom-lowered for 128-bit vectors so that
2092 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2093 EVT VT = Op.getValueType();
2094 assert(VT.is128BitVector() && VT.isInteger() &&
2095 "unexpected type for custom-lowering ISD::MUL");
2096 SDNode *N0 = Op.getOperand(0).getNode();
2097 SDNode *N1 = Op.getOperand(1).getNode();
2098 unsigned NewOpc = 0;
2100 bool isN0SExt = isSignExtended(N0, DAG);
2101 bool isN1SExt = isSignExtended(N1, DAG);
2102 if (isN0SExt && isN1SExt)
2103 NewOpc = AArch64ISD::SMULL;
2105 bool isN0ZExt = isZeroExtended(N0, DAG);
2106 bool isN1ZExt = isZeroExtended(N1, DAG);
2107 if (isN0ZExt && isN1ZExt)
2108 NewOpc = AArch64ISD::UMULL;
2109 else if (isN1SExt || isN1ZExt) {
2110 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2111 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2112 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2113 NewOpc = AArch64ISD::SMULL;
2115 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2116 NewOpc = AArch64ISD::UMULL;
2118 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2120 NewOpc = AArch64ISD::UMULL;
2126 if (VT == MVT::v2i64)
2127 // Fall through to expand this. It is not legal.
2130 // Other vector multiplications are legal.
2135 // Legalize to a S/UMULL instruction
2138 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2140 Op0 = skipExtensionForVectorMULL(N0, DAG);
2141 assert(Op0.getValueType().is64BitVector() &&
2142 Op1.getValueType().is64BitVector() &&
2143 "unexpected types for extended operands to VMULL");
2144 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2146 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2147 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2148 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2149 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2150 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2151 EVT Op1VT = Op1.getValueType();
2152 return DAG.getNode(N0->getOpcode(), DL, VT,
2153 DAG.getNode(NewOpc, DL, VT,
2154 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2155 DAG.getNode(NewOpc, DL, VT,
2156 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2159 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2160 SelectionDAG &DAG) const {
2161 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2164 default: return SDValue(); // Don't custom lower most intrinsics.
2165 case Intrinsic::aarch64_thread_pointer: {
2166 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2167 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2172 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2173 SelectionDAG &DAG) const {
2174 switch (Op.getOpcode()) {
2176 llvm_unreachable("unimplemented operand");
2179 return LowerBITCAST(Op, DAG);
2180 case ISD::GlobalAddress:
2181 return LowerGlobalAddress(Op, DAG);
2182 case ISD::GlobalTLSAddress:
2183 return LowerGlobalTLSAddress(Op, DAG);
2185 return LowerSETCC(Op, DAG);
2187 return LowerBR_CC(Op, DAG);
2189 return LowerSELECT(Op, DAG);
2190 case ISD::SELECT_CC:
2191 return LowerSELECT_CC(Op, DAG);
2192 case ISD::JumpTable:
2193 return LowerJumpTable(Op, DAG);
2194 case ISD::ConstantPool:
2195 return LowerConstantPool(Op, DAG);
2196 case ISD::BlockAddress:
2197 return LowerBlockAddress(Op, DAG);
2199 return LowerVASTART(Op, DAG);
2201 return LowerVACOPY(Op, DAG);
2203 return LowerVAARG(Op, DAG);
2208 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2215 return LowerXALUO(Op, DAG);
2217 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2219 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2221 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2223 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2225 return LowerFP_ROUND(Op, DAG);
2226 case ISD::FP_EXTEND:
2227 return LowerFP_EXTEND(Op, DAG);
2228 case ISD::FRAMEADDR:
2229 return LowerFRAMEADDR(Op, DAG);
2230 case ISD::RETURNADDR:
2231 return LowerRETURNADDR(Op, DAG);
2232 case ISD::INSERT_VECTOR_ELT:
2233 return LowerINSERT_VECTOR_ELT(Op, DAG);
2234 case ISD::EXTRACT_VECTOR_ELT:
2235 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2236 case ISD::BUILD_VECTOR:
2237 return LowerBUILD_VECTOR(Op, DAG);
2238 case ISD::VECTOR_SHUFFLE:
2239 return LowerVECTOR_SHUFFLE(Op, DAG);
2240 case ISD::EXTRACT_SUBVECTOR:
2241 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2245 return LowerVectorSRA_SRL_SHL(Op, DAG);
2246 case ISD::SHL_PARTS:
2247 return LowerShiftLeftParts(Op, DAG);
2248 case ISD::SRL_PARTS:
2249 case ISD::SRA_PARTS:
2250 return LowerShiftRightParts(Op, DAG);
2252 return LowerCTPOP(Op, DAG);
2253 case ISD::FCOPYSIGN:
2254 return LowerFCOPYSIGN(Op, DAG);
2256 return LowerVectorAND(Op, DAG);
2258 return LowerVectorOR(Op, DAG);
2260 return LowerXOR(Op, DAG);
2262 return LowerPREFETCH(Op, DAG);
2263 case ISD::SINT_TO_FP:
2264 case ISD::UINT_TO_FP:
2265 return LowerINT_TO_FP(Op, DAG);
2266 case ISD::FP_TO_SINT:
2267 case ISD::FP_TO_UINT:
2268 return LowerFP_TO_INT(Op, DAG);
2270 return LowerFSINCOS(Op, DAG);
2272 return LowerMUL(Op, DAG);
2273 case ISD::INTRINSIC_WO_CHAIN:
2274 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2278 /// getFunctionAlignment - Return the Log2 alignment of this function.
2279 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2283 //===----------------------------------------------------------------------===//
2284 // Calling Convention Implementation
2285 //===----------------------------------------------------------------------===//
2287 #include "AArch64GenCallingConv.inc"
2289 /// Selects the correct CCAssignFn for a given CallingConvention value.
2290 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2291 bool IsVarArg) const {
2294 llvm_unreachable("Unsupported calling convention.");
2295 case CallingConv::WebKit_JS:
2296 return CC_AArch64_WebKit_JS;
2297 case CallingConv::GHC:
2298 return CC_AArch64_GHC;
2299 case CallingConv::C:
2300 case CallingConv::Fast:
2301 if (!Subtarget->isTargetDarwin())
2302 return CC_AArch64_AAPCS;
2303 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2307 SDValue AArch64TargetLowering::LowerFormalArguments(
2308 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2309 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2310 SmallVectorImpl<SDValue> &InVals) const {
2311 MachineFunction &MF = DAG.getMachineFunction();
2312 MachineFrameInfo *MFI = MF.getFrameInfo();
2314 // Assign locations to all of the incoming arguments.
2315 SmallVector<CCValAssign, 16> ArgLocs;
2316 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2319 // At this point, Ins[].VT may already be promoted to i32. To correctly
2320 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2321 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2322 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2323 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2325 unsigned NumArgs = Ins.size();
2326 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2327 unsigned CurArgIdx = 0;
2328 for (unsigned i = 0; i != NumArgs; ++i) {
2329 MVT ValVT = Ins[i].VT;
2330 if (Ins[i].isOrigArg()) {
2331 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2332 CurArgIdx = Ins[i].getOrigArgIndex();
2334 // Get type of the original argument.
2335 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2336 /*AllowUnknown*/ true);
2337 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2338 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2339 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2341 else if (ActualMVT == MVT::i16)
2344 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2346 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2347 assert(!Res && "Call operand has unhandled type");
2350 assert(ArgLocs.size() == Ins.size());
2351 SmallVector<SDValue, 16> ArgValues;
2352 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2353 CCValAssign &VA = ArgLocs[i];
2355 if (Ins[i].Flags.isByVal()) {
2356 // Byval is used for HFAs in the PCS, but the system should work in a
2357 // non-compliant manner for larger structs.
2358 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2359 int Size = Ins[i].Flags.getByValSize();
2360 unsigned NumRegs = (Size + 7) / 8;
2362 // FIXME: This works on big-endian for composite byvals, which are the common
2363 // case. It should also work for fundamental types too.
2365 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2366 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2367 InVals.push_back(FrameIdxN);
2372 if (VA.isRegLoc()) {
2373 // Arguments stored in registers.
2374 EVT RegVT = VA.getLocVT();
2377 const TargetRegisterClass *RC;
2379 if (RegVT == MVT::i32)
2380 RC = &AArch64::GPR32RegClass;
2381 else if (RegVT == MVT::i64)
2382 RC = &AArch64::GPR64RegClass;
2383 else if (RegVT == MVT::f16)
2384 RC = &AArch64::FPR16RegClass;
2385 else if (RegVT == MVT::f32)
2386 RC = &AArch64::FPR32RegClass;
2387 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2388 RC = &AArch64::FPR64RegClass;
2389 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2390 RC = &AArch64::FPR128RegClass;
2392 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2394 // Transform the arguments in physical registers into virtual ones.
2395 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2396 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2398 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2399 // to 64 bits. Insert an assert[sz]ext to capture this, then
2400 // truncate to the right size.
2401 switch (VA.getLocInfo()) {
2403 llvm_unreachable("Unknown loc info!");
2404 case CCValAssign::Full:
2406 case CCValAssign::BCvt:
2407 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2409 case CCValAssign::AExt:
2410 case CCValAssign::SExt:
2411 case CCValAssign::ZExt:
2412 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2413 // nodes after our lowering.
2414 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2418 InVals.push_back(ArgValue);
2420 } else { // VA.isRegLoc()
2421 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2422 unsigned ArgOffset = VA.getLocMemOffset();
2423 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2425 uint32_t BEAlign = 0;
2426 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2427 !Ins[i].Flags.isInConsecutiveRegs())
2428 BEAlign = 8 - ArgSize;
2430 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2432 // Create load nodes to retrieve arguments from the stack.
2433 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2436 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2437 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2438 MVT MemVT = VA.getValVT();
2440 switch (VA.getLocInfo()) {
2443 case CCValAssign::BCvt:
2444 MemVT = VA.getLocVT();
2446 case CCValAssign::SExt:
2447 ExtType = ISD::SEXTLOAD;
2449 case CCValAssign::ZExt:
2450 ExtType = ISD::ZEXTLOAD;
2452 case CCValAssign::AExt:
2453 ExtType = ISD::EXTLOAD;
2457 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2458 MachinePointerInfo::getFixedStack(FI),
2459 MemVT, false, false, false, 0);
2461 InVals.push_back(ArgValue);
2467 if (!Subtarget->isTargetDarwin()) {
2468 // The AAPCS variadic function ABI is identical to the non-variadic
2469 // one. As a result there may be more arguments in registers and we should
2470 // save them for future reference.
2471 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2474 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2475 // This will point to the next argument passed via stack.
2476 unsigned StackOffset = CCInfo.getNextStackOffset();
2477 // We currently pass all varargs at 8-byte alignment.
2478 StackOffset = ((StackOffset + 7) & ~7);
2479 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2482 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2483 unsigned StackArgSize = CCInfo.getNextStackOffset();
2484 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2485 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2486 // This is a non-standard ABI so by fiat I say we're allowed to make full
2487 // use of the stack area to be popped, which must be aligned to 16 bytes in
2489 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2491 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2492 // a multiple of 16.
2493 FuncInfo->setArgumentStackToRestore(StackArgSize);
2495 // This realignment carries over to the available bytes below. Our own
2496 // callers will guarantee the space is free by giving an aligned value to
2499 // Even if we're not expected to free up the space, it's useful to know how
2500 // much is there while considering tail calls (because we can reuse it).
2501 FuncInfo->setBytesInStackArgArea(StackArgSize);
2506 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2507 SelectionDAG &DAG, SDLoc DL,
2508 SDValue &Chain) const {
2509 MachineFunction &MF = DAG.getMachineFunction();
2510 MachineFrameInfo *MFI = MF.getFrameInfo();
2511 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2512 auto PtrVT = getPointerTy(DAG.getDataLayout());
2514 SmallVector<SDValue, 8> MemOps;
2516 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2517 AArch64::X3, AArch64::X4, AArch64::X5,
2518 AArch64::X6, AArch64::X7 };
2519 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2520 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2522 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2524 if (GPRSaveSize != 0) {
2525 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2527 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2529 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2530 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2531 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2533 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2534 MachinePointerInfo::getStack(i * 8), false, false, 0);
2535 MemOps.push_back(Store);
2537 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2540 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2541 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2543 if (Subtarget->hasFPARMv8()) {
2544 static const MCPhysReg FPRArgRegs[] = {
2545 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2546 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2547 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2548 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2550 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2552 if (FPRSaveSize != 0) {
2553 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2555 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2557 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2558 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2559 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2562 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2563 MachinePointerInfo::getStack(i * 16), false, false, 0);
2564 MemOps.push_back(Store);
2565 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2566 DAG.getConstant(16, DL, PtrVT));
2569 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2570 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2573 if (!MemOps.empty()) {
2574 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2578 /// LowerCallResult - Lower the result values of a call into the
2579 /// appropriate copies out of appropriate physical registers.
2580 SDValue AArch64TargetLowering::LowerCallResult(
2581 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2582 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2583 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2584 SDValue ThisVal) const {
2585 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2586 ? RetCC_AArch64_WebKit_JS
2587 : RetCC_AArch64_AAPCS;
2588 // Assign locations to each value returned by this call.
2589 SmallVector<CCValAssign, 16> RVLocs;
2590 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2592 CCInfo.AnalyzeCallResult(Ins, RetCC);
2594 // Copy all of the result registers out of their specified physreg.
2595 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2596 CCValAssign VA = RVLocs[i];
2598 // Pass 'this' value directly from the argument to return value, to avoid
2599 // reg unit interference
2600 if (i == 0 && isThisReturn) {
2601 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2602 "unexpected return calling convention register assignment");
2603 InVals.push_back(ThisVal);
2608 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2609 Chain = Val.getValue(1);
2610 InFlag = Val.getValue(2);
2612 switch (VA.getLocInfo()) {
2614 llvm_unreachable("Unknown loc info!");
2615 case CCValAssign::Full:
2617 case CCValAssign::BCvt:
2618 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2622 InVals.push_back(Val);
2628 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2629 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2630 bool isCalleeStructRet, bool isCallerStructRet,
2631 const SmallVectorImpl<ISD::OutputArg> &Outs,
2632 const SmallVectorImpl<SDValue> &OutVals,
2633 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2634 // For CallingConv::C this function knows whether the ABI needs
2635 // changing. That's not true for other conventions so they will have to opt in
2637 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2640 const MachineFunction &MF = DAG.getMachineFunction();
2641 const Function *CallerF = MF.getFunction();
2642 CallingConv::ID CallerCC = CallerF->getCallingConv();
2643 bool CCMatch = CallerCC == CalleeCC;
2645 // Byval parameters hand the function a pointer directly into the stack area
2646 // we want to reuse during a tail call. Working around this *is* possible (see
2647 // X86) but less efficient and uglier in LowerCall.
2648 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2649 e = CallerF->arg_end();
2651 if (i->hasByValAttr())
2654 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2655 if (IsTailCallConvention(CalleeCC) && CCMatch)
2660 // Externally-defined functions with weak linkage should not be
2661 // tail-called on AArch64 when the OS does not support dynamic
2662 // pre-emption of symbols, as the AAELF spec requires normal calls
2663 // to undefined weak functions to be replaced with a NOP or jump to the
2664 // next instruction. The behaviour of branch instructions in this
2665 // situation (as used for tail calls) is implementation-defined, so we
2666 // cannot rely on the linker replacing the tail call with a return.
2667 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2668 const GlobalValue *GV = G->getGlobal();
2669 const Triple &TT = getTargetMachine().getTargetTriple();
2670 if (GV->hasExternalWeakLinkage() &&
2671 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2675 // Now we search for cases where we can use a tail call without changing the
2676 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2679 // I want anyone implementing a new calling convention to think long and hard
2680 // about this assert.
2681 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2682 "Unexpected variadic calling convention");
2684 if (isVarArg && !Outs.empty()) {
2685 // At least two cases here: if caller is fastcc then we can't have any
2686 // memory arguments (we'd be expected to clean up the stack afterwards). If
2687 // caller is C then we could potentially use its argument area.
2689 // FIXME: for now we take the most conservative of these in both cases:
2690 // disallow all variadic memory operands.
2691 SmallVector<CCValAssign, 16> ArgLocs;
2692 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2695 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2696 for (const CCValAssign &ArgLoc : ArgLocs)
2697 if (!ArgLoc.isRegLoc())
2701 // If the calling conventions do not match, then we'd better make sure the
2702 // results are returned in the same way as what the caller expects.
2704 SmallVector<CCValAssign, 16> RVLocs1;
2705 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2707 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2709 SmallVector<CCValAssign, 16> RVLocs2;
2710 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2712 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2714 if (RVLocs1.size() != RVLocs2.size())
2716 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2717 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2719 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2721 if (RVLocs1[i].isRegLoc()) {
2722 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2725 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2731 // Nothing more to check if the callee is taking no arguments
2735 SmallVector<CCValAssign, 16> ArgLocs;
2736 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2739 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2741 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2743 // If the stack arguments for this call would fit into our own save area then
2744 // the call can be made tail.
2745 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2748 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2750 MachineFrameInfo *MFI,
2751 int ClobberedFI) const {
2752 SmallVector<SDValue, 8> ArgChains;
2753 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2754 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2756 // Include the original chain at the beginning of the list. When this is
2757 // used by target LowerCall hooks, this helps legalize find the
2758 // CALLSEQ_BEGIN node.
2759 ArgChains.push_back(Chain);
2761 // Add a chain value for each stack argument corresponding
2762 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2763 UE = DAG.getEntryNode().getNode()->use_end();
2765 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2766 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2767 if (FI->getIndex() < 0) {
2768 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2769 int64_t InLastByte = InFirstByte;
2770 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2772 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2773 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2774 ArgChains.push_back(SDValue(L, 1));
2777 // Build a tokenfactor for all the chains.
2778 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2781 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2782 bool TailCallOpt) const {
2783 return CallCC == CallingConv::Fast && TailCallOpt;
2786 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2787 return CallCC == CallingConv::Fast;
2790 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2791 /// and add input and output parameter nodes.
2793 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2794 SmallVectorImpl<SDValue> &InVals) const {
2795 SelectionDAG &DAG = CLI.DAG;
2797 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2798 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2799 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2800 SDValue Chain = CLI.Chain;
2801 SDValue Callee = CLI.Callee;
2802 bool &IsTailCall = CLI.IsTailCall;
2803 CallingConv::ID CallConv = CLI.CallConv;
2804 bool IsVarArg = CLI.IsVarArg;
2806 MachineFunction &MF = DAG.getMachineFunction();
2807 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2808 bool IsThisReturn = false;
2810 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2811 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2812 bool IsSibCall = false;
2815 // Check if it's really possible to do a tail call.
2816 IsTailCall = isEligibleForTailCallOptimization(
2817 Callee, CallConv, IsVarArg, IsStructRet,
2818 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2819 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2820 report_fatal_error("failed to perform tail call elimination on a call "
2821 "site marked musttail");
2823 // A sibling call is one where we're under the usual C ABI and not planning
2824 // to change that but can still do a tail call:
2825 if (!TailCallOpt && IsTailCall)
2832 // Analyze operands of the call, assigning locations to each operand.
2833 SmallVector<CCValAssign, 16> ArgLocs;
2834 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2838 // Handle fixed and variable vector arguments differently.
2839 // Variable vector arguments always go into memory.
2840 unsigned NumArgs = Outs.size();
2842 for (unsigned i = 0; i != NumArgs; ++i) {
2843 MVT ArgVT = Outs[i].VT;
2844 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2845 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2846 /*IsVarArg=*/ !Outs[i].IsFixed);
2847 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2848 assert(!Res && "Call operand has unhandled type");
2852 // At this point, Outs[].VT may already be promoted to i32. To correctly
2853 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2854 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2855 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2856 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2858 unsigned NumArgs = Outs.size();
2859 for (unsigned i = 0; i != NumArgs; ++i) {
2860 MVT ValVT = Outs[i].VT;
2861 // Get type of the original argument.
2862 EVT ActualVT = getValueType(DAG.getDataLayout(),
2863 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2864 /*AllowUnknown*/ true);
2865 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2866 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2867 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2868 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2870 else if (ActualMVT == MVT::i16)
2873 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2874 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2875 assert(!Res && "Call operand has unhandled type");
2880 // Get a count of how many bytes are to be pushed on the stack.
2881 unsigned NumBytes = CCInfo.getNextStackOffset();
2884 // Since we're not changing the ABI to make this a tail call, the memory
2885 // operands are already available in the caller's incoming argument space.
2889 // FPDiff is the byte offset of the call's argument area from the callee's.
2890 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2891 // by this amount for a tail call. In a sibling call it must be 0 because the
2892 // caller will deallocate the entire stack and the callee still expects its
2893 // arguments to begin at SP+0. Completely unused for non-tail calls.
2896 if (IsTailCall && !IsSibCall) {
2897 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2899 // Since callee will pop argument stack as a tail call, we must keep the
2900 // popped size 16-byte aligned.
2901 NumBytes = RoundUpToAlignment(NumBytes, 16);
2903 // FPDiff will be negative if this tail call requires more space than we
2904 // would automatically have in our incoming argument space. Positive if we
2905 // can actually shrink the stack.
2906 FPDiff = NumReusableBytes - NumBytes;
2908 // The stack pointer must be 16-byte aligned at all times it's used for a
2909 // memory operation, which in practice means at *all* times and in
2910 // particular across call boundaries. Therefore our own arguments started at
2911 // a 16-byte aligned SP and the delta applied for the tail call should
2912 // satisfy the same constraint.
2913 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2916 // Adjust the stack pointer for the new arguments...
2917 // These operations are automatically eliminated by the prolog/epilog pass
2919 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2923 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
2924 getPointerTy(DAG.getDataLayout()));
2926 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2927 SmallVector<SDValue, 8> MemOpChains;
2928 auto PtrVT = getPointerTy(DAG.getDataLayout());
2930 // Walk the register/memloc assignments, inserting copies/loads.
2931 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2932 ++i, ++realArgIdx) {
2933 CCValAssign &VA = ArgLocs[i];
2934 SDValue Arg = OutVals[realArgIdx];
2935 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2937 // Promote the value if needed.
2938 switch (VA.getLocInfo()) {
2940 llvm_unreachable("Unknown loc info!");
2941 case CCValAssign::Full:
2943 case CCValAssign::SExt:
2944 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2946 case CCValAssign::ZExt:
2947 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2949 case CCValAssign::AExt:
2950 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2951 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2952 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2953 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2955 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2957 case CCValAssign::BCvt:
2958 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2960 case CCValAssign::FPExt:
2961 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2965 if (VA.isRegLoc()) {
2966 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2967 assert(VA.getLocVT() == MVT::i64 &&
2968 "unexpected calling convention register assignment");
2969 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2970 "unexpected use of 'returned'");
2971 IsThisReturn = true;
2973 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2975 assert(VA.isMemLoc());
2978 MachinePointerInfo DstInfo;
2980 // FIXME: This works on big-endian for composite byvals, which are the
2981 // common case. It should also work for fundamental types too.
2982 uint32_t BEAlign = 0;
2983 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2984 : VA.getValVT().getSizeInBits();
2985 OpSize = (OpSize + 7) / 8;
2986 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2987 !Flags.isInConsecutiveRegs()) {
2989 BEAlign = 8 - OpSize;
2991 unsigned LocMemOffset = VA.getLocMemOffset();
2992 int32_t Offset = LocMemOffset + BEAlign;
2993 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2994 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
2997 Offset = Offset + FPDiff;
2998 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3000 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3001 DstInfo = MachinePointerInfo::getFixedStack(FI);
3003 // Make sure any stack arguments overlapping with where we're storing
3004 // are loaded before this eventual operation. Otherwise they'll be
3006 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3008 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3010 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3011 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
3014 if (Outs[i].Flags.isByVal()) {
3016 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3017 SDValue Cpy = DAG.getMemcpy(
3018 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3019 /*isVol = */ false, /*AlwaysInline = */ false,
3020 /*isTailCall = */ false,
3021 DstInfo, MachinePointerInfo());
3023 MemOpChains.push_back(Cpy);
3025 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3026 // promoted to a legal register type i32, we should truncate Arg back to
3028 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3029 VA.getValVT() == MVT::i16)
3030 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3033 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
3034 MemOpChains.push_back(Store);
3039 if (!MemOpChains.empty())
3040 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3042 // Build a sequence of copy-to-reg nodes chained together with token chain
3043 // and flag operands which copy the outgoing args into the appropriate regs.
3045 for (auto &RegToPass : RegsToPass) {
3046 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3047 RegToPass.second, InFlag);
3048 InFlag = Chain.getValue(1);
3051 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3052 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3053 // node so that legalize doesn't hack it.
3054 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3055 Subtarget->isTargetMachO()) {
3056 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3057 const GlobalValue *GV = G->getGlobal();
3058 bool InternalLinkage = GV->hasInternalLinkage();
3059 if (InternalLinkage)
3060 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3063 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3064 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3066 } else if (ExternalSymbolSDNode *S =
3067 dyn_cast<ExternalSymbolSDNode>(Callee)) {
3068 const char *Sym = S->getSymbol();
3069 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3070 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3072 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3073 const GlobalValue *GV = G->getGlobal();
3074 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3075 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3076 const char *Sym = S->getSymbol();
3077 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3080 // We don't usually want to end the call-sequence here because we would tidy
3081 // the frame up *after* the call, however in the ABI-changing tail-call case
3082 // we've carefully laid out the parameters so that when sp is reset they'll be
3083 // in the correct location.
3084 if (IsTailCall && !IsSibCall) {
3085 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3086 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3087 InFlag = Chain.getValue(1);
3090 std::vector<SDValue> Ops;
3091 Ops.push_back(Chain);
3092 Ops.push_back(Callee);
3095 // Each tail call may have to adjust the stack by a different amount, so
3096 // this information must travel along with the operation for eventual
3097 // consumption by emitEpilogue.
3098 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3101 // Add argument registers to the end of the list so that they are known live
3103 for (auto &RegToPass : RegsToPass)
3104 Ops.push_back(DAG.getRegister(RegToPass.first,
3105 RegToPass.second.getValueType()));
3107 // Add a register mask operand representing the call-preserved registers.
3108 const uint32_t *Mask;
3109 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3111 // For 'this' returns, use the X0-preserving mask if applicable
3112 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3114 IsThisReturn = false;
3115 Mask = TRI->getCallPreservedMask(MF, CallConv);
3118 Mask = TRI->getCallPreservedMask(MF, CallConv);
3120 assert(Mask && "Missing call preserved mask for calling convention");
3121 Ops.push_back(DAG.getRegisterMask(Mask));
3123 if (InFlag.getNode())
3124 Ops.push_back(InFlag);
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3128 // If we're doing a tall call, use a TC_RETURN here rather than an
3129 // actual call instruction.
3131 MF.getFrameInfo()->setHasTailCall();
3132 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3135 // Returns a chain and a flag for retval copy to use.
3136 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3137 InFlag = Chain.getValue(1);
3139 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
3140 ? RoundUpToAlignment(NumBytes, 16)
3143 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3144 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3147 InFlag = Chain.getValue(1);
3149 // Handle result values, copying them out of physregs into vregs that we
3151 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3152 InVals, IsThisReturn,
3153 IsThisReturn ? OutVals[0] : SDValue());
3156 bool AArch64TargetLowering::CanLowerReturn(
3157 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3158 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3159 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3160 ? RetCC_AArch64_WebKit_JS
3161 : RetCC_AArch64_AAPCS;
3162 SmallVector<CCValAssign, 16> RVLocs;
3163 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3164 return CCInfo.CheckReturn(Outs, RetCC);
3168 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3170 const SmallVectorImpl<ISD::OutputArg> &Outs,
3171 const SmallVectorImpl<SDValue> &OutVals,
3172 SDLoc DL, SelectionDAG &DAG) const {
3173 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3174 ? RetCC_AArch64_WebKit_JS
3175 : RetCC_AArch64_AAPCS;
3176 SmallVector<CCValAssign, 16> RVLocs;
3177 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3179 CCInfo.AnalyzeReturn(Outs, RetCC);
3181 // Copy the result values into the output registers.
3183 SmallVector<SDValue, 4> RetOps(1, Chain);
3184 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3185 ++i, ++realRVLocIdx) {
3186 CCValAssign &VA = RVLocs[i];
3187 assert(VA.isRegLoc() && "Can only return in registers!");
3188 SDValue Arg = OutVals[realRVLocIdx];
3190 switch (VA.getLocInfo()) {
3192 llvm_unreachable("Unknown loc info!");
3193 case CCValAssign::Full:
3194 if (Outs[i].ArgVT == MVT::i1) {
3195 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3196 // value. This is strictly redundant on Darwin (which uses "zeroext
3197 // i1"), but will be optimised out before ISel.
3198 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3199 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3202 case CCValAssign::BCvt:
3203 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3207 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3208 Flag = Chain.getValue(1);
3209 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3212 RetOps[0] = Chain; // Update chain.
3214 // Add the flag if we have it.
3216 RetOps.push_back(Flag);
3218 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3221 //===----------------------------------------------------------------------===//
3222 // Other Lowering Code
3223 //===----------------------------------------------------------------------===//
3225 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3226 SelectionDAG &DAG) const {
3227 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3229 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3230 const GlobalValue *GV = GN->getGlobal();
3231 unsigned char OpFlags =
3232 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3234 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
3235 "unexpected offset in global node");
3237 // This also catched the large code model case for Darwin.
3238 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3239 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
3240 // FIXME: Once remat is capable of dealing with instructions with register
3241 // operands, expand this into two nodes instead of using a wrapper node.
3242 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3245 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
3246 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3247 "use of MO_CONSTPOOL only supported on small model");
3248 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3249 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3250 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3251 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3252 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3253 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3254 MachinePointerInfo::getConstantPool(),
3255 /*isVolatile=*/ false,
3256 /*isNonTemporal=*/ true,
3257 /*isInvariant=*/ true, 8);
3258 if (GN->getOffset() != 0)
3259 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3260 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3264 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3265 const unsigned char MO_NC = AArch64II::MO_NC;
3267 AArch64ISD::WrapperLarge, DL, PtrVT,
3268 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3269 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3270 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3271 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3273 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3274 // the only correct model on Darwin.
3275 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3276 OpFlags | AArch64II::MO_PAGE);
3277 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3278 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3280 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3281 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3285 /// \brief Convert a TLS address reference into the correct sequence of loads
3286 /// and calls to compute the variable's address (for Darwin, currently) and
3287 /// return an SDValue containing the final node.
3289 /// Darwin only has one TLS scheme which must be capable of dealing with the
3290 /// fully general situation, in the worst case. This means:
3291 /// + "extern __thread" declaration.
3292 /// + Defined in a possibly unknown dynamic library.
3294 /// The general system is that each __thread variable has a [3 x i64] descriptor
3295 /// which contains information used by the runtime to calculate the address. The
3296 /// only part of this the compiler needs to know about is the first xword, which
3297 /// contains a function pointer that must be called with the address of the
3298 /// entire descriptor in "x0".
3300 /// Since this descriptor may be in a different unit, in general even the
3301 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3303 /// adrp x0, _var@TLVPPAGE
3304 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3305 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3306 /// ; the function pointer
3307 /// blr x1 ; Uses descriptor address in x0
3308 /// ; Address of _var is now in x0.
3310 /// If the address of _var's descriptor *is* known to the linker, then it can
3311 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3312 /// a slight efficiency gain.
3314 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3315 SelectionDAG &DAG) const {
3316 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3319 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3320 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3323 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3324 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3326 // The first entry in the descriptor is a function pointer that we must call
3327 // to obtain the address of the variable.
3328 SDValue Chain = DAG.getEntryNode();
3329 SDValue FuncTLVGet =
3330 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3331 false, true, true, 8);
3332 Chain = FuncTLVGet.getValue(1);
3334 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3335 MFI->setAdjustsStack(true);
3337 // TLS calls preserve all registers except those that absolutely must be
3338 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3340 const uint32_t *Mask =
3341 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3343 // Finally, we can make the call. This is just a degenerate version of a
3344 // normal AArch64 call node: x0 takes the address of the descriptor, and
3345 // returns the address of the variable in this thread.
3346 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3348 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3349 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3350 DAG.getRegisterMask(Mask), Chain.getValue(1));
3351 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3354 /// When accessing thread-local variables under either the general-dynamic or
3355 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3356 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3357 /// is a function pointer to carry out the resolution.
3359 /// The sequence is:
3360 /// adrp x0, :tlsdesc:var
3361 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3362 /// add x0, x0, #:tlsdesc_lo12:var
3363 /// .tlsdesccall var
3365 /// (TPIDR_EL0 offset now in x0)
3367 /// The above sequence must be produced unscheduled, to enable the linker to
3368 /// optimize/relax this sequence.
3369 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3370 /// above sequence, and expanded really late in the compilation flow, to ensure
3371 /// the sequence is produced as per above.
3372 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3373 SelectionDAG &DAG) const {
3374 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3376 SDValue Chain = DAG.getEntryNode();
3377 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3379 SmallVector<SDValue, 2> Ops;
3380 Ops.push_back(Chain);
3381 Ops.push_back(SymAddr);
3383 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3384 SDValue Glue = Chain.getValue(1);
3386 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3390 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3391 SelectionDAG &DAG) const {
3392 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3393 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3394 "ELF TLS only supported in small memory model");
3395 // Different choices can be made for the maximum size of the TLS area for a
3396 // module. For the small address model, the default TLS size is 16MiB and the
3397 // maximum TLS size is 4GiB.
3398 // FIXME: add -mtls-size command line option and make it control the 16MiB
3399 // vs. 4GiB code sequence generation.
3400 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3402 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3404 if (DAG.getTarget().Options.EmulatedTLS)
3405 return LowerToTLSEmulatedModel(GA, DAG);
3407 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3408 if (Model == TLSModel::LocalDynamic)
3409 Model = TLSModel::GeneralDynamic;
3413 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3415 const GlobalValue *GV = GA->getGlobal();
3417 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3419 if (Model == TLSModel::LocalExec) {
3420 SDValue HiVar = DAG.getTargetGlobalAddress(
3421 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3422 SDValue LoVar = DAG.getTargetGlobalAddress(
3424 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3426 SDValue TPWithOff_lo =
3427 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3429 DAG.getTargetConstant(0, DL, MVT::i32)),
3432 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3434 DAG.getTargetConstant(0, DL, MVT::i32)),
3437 } else if (Model == TLSModel::InitialExec) {
3438 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3439 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3440 } else if (Model == TLSModel::LocalDynamic) {
3441 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3442 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3443 // the beginning of the module's TLS region, followed by a DTPREL offset
3446 // These accesses will need deduplicating if there's more than one.
3447 AArch64FunctionInfo *MFI =
3448 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3449 MFI->incNumLocalDynamicTLSAccesses();
3451 // The call needs a relocation too for linker relaxation. It doesn't make
3452 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3454 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3457 // Now we can calculate the offset from TPIDR_EL0 to this module's
3458 // thread-local area.
3459 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3461 // Now use :dtprel_whatever: operations to calculate this variable's offset
3462 // in its thread-storage area.
3463 SDValue HiVar = DAG.getTargetGlobalAddress(
3464 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3465 SDValue LoVar = DAG.getTargetGlobalAddress(
3466 GV, DL, MVT::i64, 0,
3467 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3469 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3470 DAG.getTargetConstant(0, DL, MVT::i32)),
3472 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3473 DAG.getTargetConstant(0, DL, MVT::i32)),
3475 } else if (Model == TLSModel::GeneralDynamic) {
3476 // The call needs a relocation too for linker relaxation. It doesn't make
3477 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3480 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3482 // Finally we can make a call to calculate the offset from tpidr_el0.
3483 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3485 llvm_unreachable("Unsupported ELF TLS access model");
3487 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3490 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3491 SelectionDAG &DAG) const {
3492 if (Subtarget->isTargetDarwin())
3493 return LowerDarwinGlobalTLSAddress(Op, DAG);
3494 else if (Subtarget->isTargetELF())
3495 return LowerELFGlobalTLSAddress(Op, DAG);
3497 llvm_unreachable("Unexpected platform trying to use TLS");
3499 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3500 SDValue Chain = Op.getOperand(0);
3501 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3502 SDValue LHS = Op.getOperand(2);
3503 SDValue RHS = Op.getOperand(3);
3504 SDValue Dest = Op.getOperand(4);
3507 // Handle f128 first, since lowering it will result in comparing the return
3508 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3509 // is expecting to deal with.
3510 if (LHS.getValueType() == MVT::f128) {
3511 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3513 // If softenSetCCOperands returned a scalar, we need to compare the result
3514 // against zero to select between true and false values.
3515 if (!RHS.getNode()) {
3516 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3521 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3523 unsigned Opc = LHS.getOpcode();
3524 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3525 cast<ConstantSDNode>(RHS)->isOne() &&
3526 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3527 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3528 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3529 "Unexpected condition code.");
3530 // Only lower legal XALUO ops.
3531 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3534 // The actual operation with overflow check.
3535 AArch64CC::CondCode OFCC;
3536 SDValue Value, Overflow;
3537 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3539 if (CC == ISD::SETNE)
3540 OFCC = getInvertedCondCode(OFCC);
3541 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3543 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3547 if (LHS.getValueType().isInteger()) {
3548 assert((LHS.getValueType() == RHS.getValueType()) &&
3549 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3551 // If the RHS of the comparison is zero, we can potentially fold this
3552 // to a specialized branch.
3553 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3554 if (RHSC && RHSC->getZExtValue() == 0) {
3555 if (CC == ISD::SETEQ) {
3556 // See if we can use a TBZ to fold in an AND as well.
3557 // TBZ has a smaller branch displacement than CBZ. If the offset is
3558 // out of bounds, a late MI-layer pass rewrites branches.
3559 // 403.gcc is an example that hits this case.
3560 if (LHS.getOpcode() == ISD::AND &&
3561 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3562 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3563 SDValue Test = LHS.getOperand(0);
3564 uint64_t Mask = LHS.getConstantOperandVal(1);
3565 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3566 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3570 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3571 } else if (CC == ISD::SETNE) {
3572 // See if we can use a TBZ to fold in an AND as well.
3573 // TBZ has a smaller branch displacement than CBZ. If the offset is
3574 // out of bounds, a late MI-layer pass rewrites branches.
3575 // 403.gcc is an example that hits this case.
3576 if (LHS.getOpcode() == ISD::AND &&
3577 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3578 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3579 SDValue Test = LHS.getOperand(0);
3580 uint64_t Mask = LHS.getConstantOperandVal(1);
3581 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3582 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3586 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3587 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3588 // Don't combine AND since emitComparison converts the AND to an ANDS
3589 // (a.k.a. TST) and the test in the test bit and branch instruction
3590 // becomes redundant. This would also increase register pressure.
3591 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3592 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3593 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3596 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3597 LHS.getOpcode() != ISD::AND) {
3598 // Don't combine AND since emitComparison converts the AND to an ANDS
3599 // (a.k.a. TST) and the test in the test bit and branch instruction
3600 // becomes redundant. This would also increase register pressure.
3601 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3602 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3603 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3607 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3608 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3612 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3614 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3615 // clean. Some of them require two branches to implement.
3616 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3617 AArch64CC::CondCode CC1, CC2;
3618 changeFPCCToAArch64CC(CC, CC1, CC2);
3619 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3621 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3622 if (CC2 != AArch64CC::AL) {
3623 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3624 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3631 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3632 SelectionDAG &DAG) const {
3633 EVT VT = Op.getValueType();
3636 SDValue In1 = Op.getOperand(0);
3637 SDValue In2 = Op.getOperand(1);
3638 EVT SrcVT = In2.getValueType();
3640 if (SrcVT == MVT::f32 && VT == MVT::f64)
3641 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3642 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3643 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3644 DAG.getIntPtrConstant(0, DL));
3646 // FIXME: Src type is different, bail out for now. Can VT really be a
3654 SDValue VecVal1, VecVal2;
3655 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3657 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
3658 EltMask = 0x80000000ULL;
3660 if (!VT.isVector()) {
3661 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3662 DAG.getUNDEF(VecVT), In1);
3663 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3664 DAG.getUNDEF(VecVT), In2);
3666 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3667 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3669 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3673 // We want to materialize a mask with the high bit set, but the AdvSIMD
3674 // immediate moves cannot materialize that in a single instruction for
3675 // 64-bit elements. Instead, materialize zero and then negate it.
3678 if (!VT.isVector()) {
3679 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3680 DAG.getUNDEF(VecVT), In1);
3681 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3682 DAG.getUNDEF(VecVT), In2);
3684 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3685 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3688 llvm_unreachable("Invalid type for copysign!");
3691 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3693 // If we couldn't materialize the mask above, then the mask vector will be
3694 // the zero vector, and we need to negate it here.
3695 if (VT == MVT::f64 || VT == MVT::v2f64) {
3696 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3697 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3698 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3702 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3705 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3706 else if (VT == MVT::f64)
3707 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3709 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3712 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3713 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3714 Attribute::NoImplicitFloat))
3717 if (!Subtarget->hasNEON())
3720 // While there is no integer popcount instruction, it can
3721 // be more efficiently lowered to the following sequence that uses
3722 // AdvSIMD registers/instructions as long as the copies to/from
3723 // the AdvSIMD registers are cheap.
3724 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3725 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3726 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3727 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3728 SDValue Val = Op.getOperand(0);
3730 EVT VT = Op.getValueType();
3733 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3734 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3736 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3737 SDValue UaddLV = DAG.getNode(
3738 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3739 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3742 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3746 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3748 if (Op.getValueType().isVector())
3749 return LowerVSETCC(Op, DAG);
3751 SDValue LHS = Op.getOperand(0);
3752 SDValue RHS = Op.getOperand(1);
3753 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3756 // We chose ZeroOrOneBooleanContents, so use zero and one.
3757 EVT VT = Op.getValueType();
3758 SDValue TVal = DAG.getConstant(1, dl, VT);
3759 SDValue FVal = DAG.getConstant(0, dl, VT);
3761 // Handle f128 first, since one possible outcome is a normal integer
3762 // comparison which gets picked up by the next if statement.
3763 if (LHS.getValueType() == MVT::f128) {
3764 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3766 // If softenSetCCOperands returned a scalar, use it.
3767 if (!RHS.getNode()) {
3768 assert(LHS.getValueType() == Op.getValueType() &&
3769 "Unexpected setcc expansion!");
3774 if (LHS.getValueType().isInteger()) {
3777 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3779 // Note that we inverted the condition above, so we reverse the order of
3780 // the true and false operands here. This will allow the setcc to be
3781 // matched to a single CSINC instruction.
3782 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3785 // Now we know we're dealing with FP values.
3786 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3788 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3789 // and do the comparison.
3790 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3792 AArch64CC::CondCode CC1, CC2;
3793 changeFPCCToAArch64CC(CC, CC1, CC2);
3794 if (CC2 == AArch64CC::AL) {
3795 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3796 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3798 // Note that we inverted the condition above, so we reverse the order of
3799 // the true and false operands here. This will allow the setcc to be
3800 // matched to a single CSINC instruction.
3801 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3803 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3804 // totally clean. Some of them require two CSELs to implement. As is in
3805 // this case, we emit the first CSEL and then emit a second using the output
3806 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3808 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3809 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3811 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3813 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3814 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3818 /// A SELECT_CC operation is really some kind of max or min if both values being
3819 /// compared are, in some sense, equal to the results in either case. However,
3820 /// it is permissible to compare f32 values and produce directly extended f64
3823 /// Extending the comparison operands would also be allowed, but is less likely
3824 /// to happen in practice since their use is right here. Note that truncate
3825 /// operations would *not* be semantically equivalent.
3826 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3828 return (Cmp.getValueType() == MVT::f32 ||
3829 Cmp.getValueType() == MVT::f64);
3831 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3832 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3833 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3834 Result.getValueType() == MVT::f64) {
3836 APFloat CmpVal = CCmp->getValueAPF();
3837 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3838 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3841 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3844 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3845 SDValue RHS, SDValue TVal,
3846 SDValue FVal, SDLoc dl,
3847 SelectionDAG &DAG) const {
3848 // Handle f128 first, because it will result in a comparison of some RTLIB
3849 // call result against zero.
3850 if (LHS.getValueType() == MVT::f128) {
3851 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3853 // If softenSetCCOperands returned a scalar, we need to compare the result
3854 // against zero to select between true and false values.
3855 if (!RHS.getNode()) {
3856 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3861 // Handle integers first.
3862 if (LHS.getValueType().isInteger()) {
3863 assert((LHS.getValueType() == RHS.getValueType()) &&
3864 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3866 unsigned Opcode = AArch64ISD::CSEL;
3868 // If both the TVal and the FVal are constants, see if we can swap them in
3869 // order to for a CSINV or CSINC out of them.
3870 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3871 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3873 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3874 std::swap(TVal, FVal);
3875 std::swap(CTVal, CFVal);
3876 CC = ISD::getSetCCInverse(CC, true);
3877 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3878 std::swap(TVal, FVal);
3879 std::swap(CTVal, CFVal);
3880 CC = ISD::getSetCCInverse(CC, true);
3881 } else if (TVal.getOpcode() == ISD::XOR) {
3882 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3883 // with a CSINV rather than a CSEL.
3884 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3886 if (CVal && CVal->isAllOnesValue()) {
3887 std::swap(TVal, FVal);
3888 std::swap(CTVal, CFVal);
3889 CC = ISD::getSetCCInverse(CC, true);
3891 } else if (TVal.getOpcode() == ISD::SUB) {
3892 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3893 // that we can match with a CSNEG rather than a CSEL.
3894 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3896 if (CVal && CVal->isNullValue()) {
3897 std::swap(TVal, FVal);
3898 std::swap(CTVal, CFVal);
3899 CC = ISD::getSetCCInverse(CC, true);
3901 } else if (CTVal && CFVal) {
3902 const int64_t TrueVal = CTVal->getSExtValue();
3903 const int64_t FalseVal = CFVal->getSExtValue();
3906 // If both TVal and FVal are constants, see if FVal is the
3907 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3908 // instead of a CSEL in that case.
3909 if (TrueVal == ~FalseVal) {
3910 Opcode = AArch64ISD::CSINV;
3911 } else if (TrueVal == -FalseVal) {
3912 Opcode = AArch64ISD::CSNEG;
3913 } else if (TVal.getValueType() == MVT::i32) {
3914 // If our operands are only 32-bit wide, make sure we use 32-bit
3915 // arithmetic for the check whether we can use CSINC. This ensures that
3916 // the addition in the check will wrap around properly in case there is
3917 // an overflow (which would not be the case if we do the check with
3918 // 64-bit arithmetic).
3919 const uint32_t TrueVal32 = CTVal->getZExtValue();
3920 const uint32_t FalseVal32 = CFVal->getZExtValue();
3922 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3923 Opcode = AArch64ISD::CSINC;
3925 if (TrueVal32 > FalseVal32) {
3929 // 64-bit check whether we can use CSINC.
3930 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3931 Opcode = AArch64ISD::CSINC;
3933 if (TrueVal > FalseVal) {
3938 // Swap TVal and FVal if necessary.
3940 std::swap(TVal, FVal);
3941 std::swap(CTVal, CFVal);
3942 CC = ISD::getSetCCInverse(CC, true);
3945 if (Opcode != AArch64ISD::CSEL) {
3946 // Drop FVal since we can get its value by simply inverting/negating
3953 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3955 EVT VT = TVal.getValueType();
3956 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3959 // Now we know we're dealing with FP values.
3960 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3961 assert(LHS.getValueType() == RHS.getValueType());
3962 EVT VT = TVal.getValueType();
3963 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3965 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3966 // clean. Some of them require two CSELs to implement.
3967 AArch64CC::CondCode CC1, CC2;
3968 changeFPCCToAArch64CC(CC, CC1, CC2);
3969 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3970 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3972 // If we need a second CSEL, emit it, using the output of the first as the
3973 // RHS. We're effectively OR'ing the two CC's together.
3974 if (CC2 != AArch64CC::AL) {
3975 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3976 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3979 // Otherwise, return the output of the first CSEL.
3983 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3984 SelectionDAG &DAG) const {
3985 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3986 SDValue LHS = Op.getOperand(0);
3987 SDValue RHS = Op.getOperand(1);
3988 SDValue TVal = Op.getOperand(2);
3989 SDValue FVal = Op.getOperand(3);
3991 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3994 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3995 SelectionDAG &DAG) const {
3996 SDValue CCVal = Op->getOperand(0);
3997 SDValue TVal = Op->getOperand(1);
3998 SDValue FVal = Op->getOperand(2);
4001 unsigned Opc = CCVal.getOpcode();
4002 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4004 if (CCVal.getResNo() == 1 &&
4005 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4006 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4007 // Only lower legal XALUO ops.
4008 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4011 AArch64CC::CondCode OFCC;
4012 SDValue Value, Overflow;
4013 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4014 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4016 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4020 // Lower it the same way as we would lower a SELECT_CC node.
4023 if (CCVal.getOpcode() == ISD::SETCC) {
4024 LHS = CCVal.getOperand(0);
4025 RHS = CCVal.getOperand(1);
4026 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4029 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4032 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4035 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4036 SelectionDAG &DAG) const {
4037 // Jump table entries as PC relative offsets. No additional tweaking
4038 // is necessary here. Just get the address of the jump table.
4039 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4040 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4043 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4044 !Subtarget->isTargetMachO()) {
4045 const unsigned char MO_NC = AArch64II::MO_NC;
4047 AArch64ISD::WrapperLarge, DL, PtrVT,
4048 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
4049 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
4050 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
4051 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4052 AArch64II::MO_G0 | MO_NC));
4056 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
4057 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4058 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4059 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4060 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4063 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4064 SelectionDAG &DAG) const {
4065 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4066 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4069 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4070 // Use the GOT for the large code model on iOS.
4071 if (Subtarget->isTargetMachO()) {
4072 SDValue GotAddr = DAG.getTargetConstantPool(
4073 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4075 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
4078 const unsigned char MO_NC = AArch64II::MO_NC;
4080 AArch64ISD::WrapperLarge, DL, PtrVT,
4081 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4082 CP->getOffset(), AArch64II::MO_G3),
4083 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4084 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
4085 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4086 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
4087 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4088 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
4090 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4091 // ELF, the only valid one on Darwin.
4093 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4094 CP->getOffset(), AArch64II::MO_PAGE);
4095 SDValue Lo = DAG.getTargetConstantPool(
4096 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4097 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4099 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4100 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4104 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4105 SelectionDAG &DAG) const {
4106 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4107 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4109 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4110 !Subtarget->isTargetMachO()) {
4111 const unsigned char MO_NC = AArch64II::MO_NC;
4113 AArch64ISD::WrapperLarge, DL, PtrVT,
4114 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
4115 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
4116 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
4117 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
4119 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
4120 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
4122 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4123 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4127 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4128 SelectionDAG &DAG) const {
4129 AArch64FunctionInfo *FuncInfo =
4130 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4133 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4134 getPointerTy(DAG.getDataLayout()));
4135 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4136 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4137 MachinePointerInfo(SV), false, false, 0);
4140 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4141 SelectionDAG &DAG) const {
4142 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4143 // Standard, section B.3.
4144 MachineFunction &MF = DAG.getMachineFunction();
4145 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4146 auto PtrVT = getPointerTy(DAG.getDataLayout());
4149 SDValue Chain = Op.getOperand(0);
4150 SDValue VAList = Op.getOperand(1);
4151 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4152 SmallVector<SDValue, 4> MemOps;
4154 // void *__stack at offset 0
4155 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4156 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4157 MachinePointerInfo(SV), false, false, 8));
4159 // void *__gr_top at offset 8
4160 int GPRSize = FuncInfo->getVarArgsGPRSize();
4162 SDValue GRTop, GRTopAddr;
4165 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4167 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4168 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4169 DAG.getConstant(GPRSize, DL, PtrVT));
4171 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4172 MachinePointerInfo(SV, 8), false, false, 8));
4175 // void *__vr_top at offset 16
4176 int FPRSize = FuncInfo->getVarArgsFPRSize();
4178 SDValue VRTop, VRTopAddr;
4179 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4180 DAG.getConstant(16, DL, PtrVT));
4182 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4183 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4184 DAG.getConstant(FPRSize, DL, PtrVT));
4186 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4187 MachinePointerInfo(SV, 16), false, false, 8));
4190 // int __gr_offs at offset 24
4191 SDValue GROffsAddr =
4192 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4193 MemOps.push_back(DAG.getStore(Chain, DL,
4194 DAG.getConstant(-GPRSize, DL, MVT::i32),
4195 GROffsAddr, MachinePointerInfo(SV, 24), false,
4198 // int __vr_offs at offset 28
4199 SDValue VROffsAddr =
4200 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4201 MemOps.push_back(DAG.getStore(Chain, DL,
4202 DAG.getConstant(-FPRSize, DL, MVT::i32),
4203 VROffsAddr, MachinePointerInfo(SV, 28), false,
4206 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4209 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4210 SelectionDAG &DAG) const {
4211 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
4212 : LowerAAPCS_VASTART(Op, DAG);
4215 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4216 SelectionDAG &DAG) const {
4217 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4220 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
4221 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4222 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4224 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4226 DAG.getConstant(VaListSize, DL, MVT::i32),
4227 8, false, false, false, MachinePointerInfo(DestSV),
4228 MachinePointerInfo(SrcSV));
4231 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4232 assert(Subtarget->isTargetDarwin() &&
4233 "automatic va_arg instruction only works on Darwin");
4235 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4236 EVT VT = Op.getValueType();
4238 SDValue Chain = Op.getOperand(0);
4239 SDValue Addr = Op.getOperand(1);
4240 unsigned Align = Op.getConstantOperandVal(3);
4241 auto PtrVT = getPointerTy(DAG.getDataLayout());
4243 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V),
4244 false, false, false, 0);
4245 Chain = VAList.getValue(1);
4248 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4249 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4250 DAG.getConstant(Align - 1, DL, PtrVT));
4251 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4252 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4255 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4256 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4258 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4259 // up to 64 bits. At the very least, we have to increase the striding of the
4260 // vaargs list to match this, and for FP values we need to introduce
4261 // FP_ROUND nodes as well.
4262 if (VT.isInteger() && !VT.isVector())
4264 bool NeedFPTrunc = false;
4265 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4270 // Increment the pointer, VAList, to the next vaarg
4271 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4272 DAG.getConstant(ArgSize, DL, PtrVT));
4273 // Store the incremented VAList to the legalized pointer
4274 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4277 // Load the actual argument out of the pointer VAList
4279 // Load the value as an f64.
4280 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4281 MachinePointerInfo(), false, false, false, 0);
4282 // Round the value down to an f32.
4283 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4284 DAG.getIntPtrConstant(1, DL));
4285 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4286 // Merge the rounded value with the chain output of the load.
4287 return DAG.getMergeValues(Ops, DL);
4290 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4294 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4295 SelectionDAG &DAG) const {
4296 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4297 MFI->setFrameAddressIsTaken(true);
4299 EVT VT = Op.getValueType();
4301 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4303 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4305 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4306 MachinePointerInfo(), false, false, false, 0);
4310 // FIXME? Maybe this could be a TableGen attribute on some registers and
4311 // this table could be generated automatically from RegInfo.
4312 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4313 SelectionDAG &DAG) const {
4314 unsigned Reg = StringSwitch<unsigned>(RegName)
4315 .Case("sp", AArch64::SP)
4319 report_fatal_error(Twine("Invalid register name \""
4320 + StringRef(RegName) + "\"."));
4323 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4324 SelectionDAG &DAG) const {
4325 MachineFunction &MF = DAG.getMachineFunction();
4326 MachineFrameInfo *MFI = MF.getFrameInfo();
4327 MFI->setReturnAddressIsTaken(true);
4329 EVT VT = Op.getValueType();
4331 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4333 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4334 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4335 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4336 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4337 MachinePointerInfo(), false, false, false, 0);
4340 // Return LR, which contains the return address. Mark it an implicit live-in.
4341 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4342 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4345 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4346 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4347 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4348 SelectionDAG &DAG) const {
4349 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4350 EVT VT = Op.getValueType();
4351 unsigned VTBits = VT.getSizeInBits();
4353 SDValue ShOpLo = Op.getOperand(0);
4354 SDValue ShOpHi = Op.getOperand(1);
4355 SDValue ShAmt = Op.getOperand(2);
4357 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4359 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4361 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4362 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4363 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4364 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4365 DAG.getConstant(VTBits, dl, MVT::i64));
4366 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4368 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4369 ISD::SETGE, dl, DAG);
4370 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4372 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4373 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4375 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4377 // AArch64 shifts larger than the register width are wrapped rather than
4378 // clamped, so we can't just emit "hi >> x".
4379 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4380 SDValue TrueValHi = Opc == ISD::SRA
4381 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4382 DAG.getConstant(VTBits - 1, dl,
4384 : DAG.getConstant(0, dl, VT);
4386 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4388 SDValue Ops[2] = { Lo, Hi };
4389 return DAG.getMergeValues(Ops, dl);
4392 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4393 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4394 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4395 SelectionDAG &DAG) const {
4396 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4397 EVT VT = Op.getValueType();
4398 unsigned VTBits = VT.getSizeInBits();
4400 SDValue ShOpLo = Op.getOperand(0);
4401 SDValue ShOpHi = Op.getOperand(1);
4402 SDValue ShAmt = Op.getOperand(2);
4405 assert(Op.getOpcode() == ISD::SHL_PARTS);
4406 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4407 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4408 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4409 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4410 DAG.getConstant(VTBits, dl, MVT::i64));
4411 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4412 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4414 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4416 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4417 ISD::SETGE, dl, DAG);
4418 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4420 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4422 // AArch64 shifts of larger than register sizes are wrapped rather than
4423 // clamped, so we can't just emit "lo << a" if a is too big.
4424 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4425 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4427 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4429 SDValue Ops[2] = { Lo, Hi };
4430 return DAG.getMergeValues(Ops, dl);
4433 bool AArch64TargetLowering::isOffsetFoldingLegal(
4434 const GlobalAddressSDNode *GA) const {
4435 // The AArch64 target doesn't support folding offsets into global addresses.
4439 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4440 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4441 // FIXME: We should be able to handle f128 as well with a clever lowering.
4442 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4446 return AArch64_AM::getFP64Imm(Imm) != -1;
4447 else if (VT == MVT::f32)
4448 return AArch64_AM::getFP32Imm(Imm) != -1;
4452 //===----------------------------------------------------------------------===//
4453 // AArch64 Optimization Hooks
4454 //===----------------------------------------------------------------------===//
4456 //===----------------------------------------------------------------------===//
4457 // AArch64 Inline Assembly Support
4458 //===----------------------------------------------------------------------===//
4460 // Table of Constraints
4461 // TODO: This is the current set of constraints supported by ARM for the
4462 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4464 // r - A general register
4465 // w - An FP/SIMD register of some size in the range v0-v31
4466 // x - An FP/SIMD register of some size in the range v0-v15
4467 // I - Constant that can be used with an ADD instruction
4468 // J - Constant that can be used with a SUB instruction
4469 // K - Constant that can be used with a 32-bit logical instruction
4470 // L - Constant that can be used with a 64-bit logical instruction
4471 // M - Constant that can be used as a 32-bit MOV immediate
4472 // N - Constant that can be used as a 64-bit MOV immediate
4473 // Q - A memory reference with base register and no offset
4474 // S - A symbolic address
4475 // Y - Floating point constant zero
4476 // Z - Integer constant zero
4478 // Note that general register operands will be output using their 64-bit x
4479 // register name, whatever the size of the variable, unless the asm operand
4480 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4481 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4484 /// getConstraintType - Given a constraint letter, return the type of
4485 /// constraint it is for this target.
4486 AArch64TargetLowering::ConstraintType
4487 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4488 if (Constraint.size() == 1) {
4489 switch (Constraint[0]) {
4496 return C_RegisterClass;
4497 // An address with a single base register. Due to the way we
4498 // currently handle addresses it is the same as 'r'.
4503 return TargetLowering::getConstraintType(Constraint);
4506 /// Examine constraint type and operand type and determine a weight value.
4507 /// This object must already have been set up with the operand type
4508 /// and the current alternative constraint selected.
4509 TargetLowering::ConstraintWeight
4510 AArch64TargetLowering::getSingleConstraintMatchWeight(
4511 AsmOperandInfo &info, const char *constraint) const {
4512 ConstraintWeight weight = CW_Invalid;
4513 Value *CallOperandVal = info.CallOperandVal;
4514 // If we don't have a value, we can't do a match,
4515 // but allow it at the lowest weight.
4516 if (!CallOperandVal)
4518 Type *type = CallOperandVal->getType();
4519 // Look at the constraint type.
4520 switch (*constraint) {
4522 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4526 if (type->isFloatingPointTy() || type->isVectorTy())
4527 weight = CW_Register;
4530 weight = CW_Constant;
4536 std::pair<unsigned, const TargetRegisterClass *>
4537 AArch64TargetLowering::getRegForInlineAsmConstraint(
4538 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4539 if (Constraint.size() == 1) {
4540 switch (Constraint[0]) {
4542 if (VT.getSizeInBits() == 64)
4543 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4544 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4547 return std::make_pair(0U, &AArch64::FPR32RegClass);
4548 if (VT.getSizeInBits() == 64)
4549 return std::make_pair(0U, &AArch64::FPR64RegClass);
4550 if (VT.getSizeInBits() == 128)
4551 return std::make_pair(0U, &AArch64::FPR128RegClass);
4553 // The instructions that this constraint is designed for can
4554 // only take 128-bit registers so just use that regclass.
4556 if (VT.getSizeInBits() == 128)
4557 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4561 if (StringRef("{cc}").equals_lower(Constraint))
4562 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4564 // Use the default implementation in TargetLowering to convert the register
4565 // constraint into a member of a register class.
4566 std::pair<unsigned, const TargetRegisterClass *> Res;
4567 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4569 // Not found as a standard register?
4571 unsigned Size = Constraint.size();
4572 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4573 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4575 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4576 if (!Failed && RegNo >= 0 && RegNo <= 31) {
4577 // v0 - v31 are aliases of q0 - q31.
4578 // By default we'll emit v0-v31 for this unless there's a modifier where
4579 // we'll emit the correct register as well.
4580 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4581 Res.second = &AArch64::FPR128RegClass;
4589 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4590 /// vector. If it is invalid, don't add anything to Ops.
4591 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4592 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4593 SelectionDAG &DAG) const {
4596 // Currently only support length 1 constraints.
4597 if (Constraint.length() != 1)
4600 char ConstraintLetter = Constraint[0];
4601 switch (ConstraintLetter) {
4605 // This set of constraints deal with valid constants for various instructions.
4606 // Validate and return a target constant for them if we can.
4608 // 'z' maps to xzr or wzr so it needs an input of 0.
4609 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4610 if (!C || C->getZExtValue() != 0)
4613 if (Op.getValueType() == MVT::i64)
4614 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4616 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4626 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4630 // Grab the value and do some validation.
4631 uint64_t CVal = C->getZExtValue();
4632 switch (ConstraintLetter) {
4633 // The I constraint applies only to simple ADD or SUB immediate operands:
4634 // i.e. 0 to 4095 with optional shift by 12
4635 // The J constraint applies only to ADD or SUB immediates that would be
4636 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4637 // instruction [or vice versa], in other words -1 to -4095 with optional
4638 // left shift by 12.
4640 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4644 uint64_t NVal = -C->getSExtValue();
4645 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4646 CVal = C->getSExtValue();
4651 // The K and L constraints apply *only* to logical immediates, including
4652 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4653 // been removed and MOV should be used). So these constraints have to
4654 // distinguish between bit patterns that are valid 32-bit or 64-bit
4655 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4656 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4659 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4663 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4666 // The M and N constraints are a superset of K and L respectively, for use
4667 // with the MOV (immediate) alias. As well as the logical immediates they
4668 // also match 32 or 64-bit immediates that can be loaded either using a
4669 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4670 // (M) or 64-bit 0x1234000000000000 (N) etc.
4671 // As a note some of this code is liberally stolen from the asm parser.
4673 if (!isUInt<32>(CVal))
4675 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4677 if ((CVal & 0xFFFF) == CVal)
4679 if ((CVal & 0xFFFF0000ULL) == CVal)
4681 uint64_t NCVal = ~(uint32_t)CVal;
4682 if ((NCVal & 0xFFFFULL) == NCVal)
4684 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4689 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4691 if ((CVal & 0xFFFFULL) == CVal)
4693 if ((CVal & 0xFFFF0000ULL) == CVal)
4695 if ((CVal & 0xFFFF00000000ULL) == CVal)
4697 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4699 uint64_t NCVal = ~CVal;
4700 if ((NCVal & 0xFFFFULL) == NCVal)
4702 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4704 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4706 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4714 // All assembler immediates are 64-bit integers.
4715 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4719 if (Result.getNode()) {
4720 Ops.push_back(Result);
4724 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4727 //===----------------------------------------------------------------------===//
4728 // AArch64 Advanced SIMD Support
4729 //===----------------------------------------------------------------------===//
4731 /// WidenVector - Given a value in the V64 register class, produce the
4732 /// equivalent value in the V128 register class.
4733 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4734 EVT VT = V64Reg.getValueType();
4735 unsigned NarrowSize = VT.getVectorNumElements();
4736 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4737 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4740 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4741 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4744 /// getExtFactor - Determine the adjustment factor for the position when
4745 /// generating an "extract from vector registers" instruction.
4746 static unsigned getExtFactor(SDValue &V) {
4747 EVT EltType = V.getValueType().getVectorElementType();
4748 return EltType.getSizeInBits() / 8;
4751 /// NarrowVector - Given a value in the V128 register class, produce the
4752 /// equivalent value in the V64 register class.
4753 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4754 EVT VT = V128Reg.getValueType();
4755 unsigned WideSize = VT.getVectorNumElements();
4756 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4757 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4760 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4763 // Gather data to see if the operation can be modelled as a
4764 // shuffle in combination with VEXTs.
4765 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4766 SelectionDAG &DAG) const {
4767 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4769 EVT VT = Op.getValueType();
4770 unsigned NumElts = VT.getVectorNumElements();
4772 struct ShuffleSourceInfo {
4777 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4778 // be compatible with the shuffle we intend to construct. As a result
4779 // ShuffleVec will be some sliding window into the original Vec.
4782 // Code should guarantee that element i in Vec starts at element "WindowBase
4783 // + i * WindowScale in ShuffleVec".
4787 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4788 ShuffleSourceInfo(SDValue Vec)
4789 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4793 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4795 SmallVector<ShuffleSourceInfo, 2> Sources;
4796 for (unsigned i = 0; i < NumElts; ++i) {
4797 SDValue V = Op.getOperand(i);
4798 if (V.getOpcode() == ISD::UNDEF)
4800 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4801 // A shuffle can only come from building a vector from various
4802 // elements of other vectors.
4806 // Add this element source to the list if it's not already there.
4807 SDValue SourceVec = V.getOperand(0);
4808 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4809 if (Source == Sources.end())
4810 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4812 // Update the minimum and maximum lane number seen.
4813 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4814 Source->MinElt = std::min(Source->MinElt, EltNo);
4815 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4818 // Currently only do something sane when at most two source vectors
4820 if (Sources.size() > 2)
4823 // Find out the smallest element size among result and two sources, and use
4824 // it as element size to build the shuffle_vector.
4825 EVT SmallestEltTy = VT.getVectorElementType();
4826 for (auto &Source : Sources) {
4827 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4828 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4829 SmallestEltTy = SrcEltTy;
4832 unsigned ResMultiplier =
4833 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4834 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4835 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4837 // If the source vector is too wide or too narrow, we may nevertheless be able
4838 // to construct a compatible shuffle either by concatenating it with UNDEF or
4839 // extracting a suitable range of elements.
4840 for (auto &Src : Sources) {
4841 EVT SrcVT = Src.ShuffleVec.getValueType();
4843 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4846 // This stage of the search produces a source with the same element type as
4847 // the original, but with a total width matching the BUILD_VECTOR output.
4848 EVT EltVT = SrcVT.getVectorElementType();
4849 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4850 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4852 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4853 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4854 // We can pad out the smaller vector for free, so if it's part of a
4857 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4858 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4862 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4864 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4865 // Span too large for a VEXT to cope
4869 if (Src.MinElt >= NumSrcElts) {
4870 // The extraction can just take the second half
4872 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4873 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4874 Src.WindowBase = -NumSrcElts;
4875 } else if (Src.MaxElt < NumSrcElts) {
4876 // The extraction can just take the first half
4878 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4879 DAG.getConstant(0, dl, MVT::i64));
4881 // An actual VEXT is needed
4883 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4884 DAG.getConstant(0, dl, MVT::i64));
4886 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4887 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4888 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4890 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4892 DAG.getConstant(Imm, dl, MVT::i32));
4893 Src.WindowBase = -Src.MinElt;
4897 // Another possible incompatibility occurs from the vector element types. We
4898 // can fix this by bitcasting the source vectors to the same type we intend
4900 for (auto &Src : Sources) {
4901 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4902 if (SrcEltTy == SmallestEltTy)
4904 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4905 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4906 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4907 Src.WindowBase *= Src.WindowScale;
4910 // Final sanity check before we try to actually produce a shuffle.
4912 for (auto Src : Sources)
4913 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4916 // The stars all align, our next step is to produce the mask for the shuffle.
4917 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4918 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4919 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4920 SDValue Entry = Op.getOperand(i);
4921 if (Entry.getOpcode() == ISD::UNDEF)
4924 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4925 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4927 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4928 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4930 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4931 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4932 VT.getVectorElementType().getSizeInBits());
4933 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4935 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4936 // starting at the appropriate offset.
4937 int *LaneMask = &Mask[i * ResMultiplier];
4939 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4940 ExtractBase += NumElts * (Src - Sources.begin());
4941 for (int j = 0; j < LanesDefined; ++j)
4942 LaneMask[j] = ExtractBase + j;
4945 // Final check before we try to produce nonsense...
4946 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4949 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4950 for (unsigned i = 0; i < Sources.size(); ++i)
4951 ShuffleOps[i] = Sources[i].ShuffleVec;
4953 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4954 ShuffleOps[1], &Mask[0]);
4955 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4958 // check if an EXT instruction can handle the shuffle mask when the
4959 // vector sources of the shuffle are the same.
4960 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4961 unsigned NumElts = VT.getVectorNumElements();
4963 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4969 // If this is a VEXT shuffle, the immediate value is the index of the first
4970 // element. The other shuffle indices must be the successive elements after
4972 unsigned ExpectedElt = Imm;
4973 for (unsigned i = 1; i < NumElts; ++i) {
4974 // Increment the expected index. If it wraps around, just follow it
4975 // back to index zero and keep going.
4977 if (ExpectedElt == NumElts)
4981 continue; // ignore UNDEF indices
4982 if (ExpectedElt != static_cast<unsigned>(M[i]))
4989 // check if an EXT instruction can handle the shuffle mask when the
4990 // vector sources of the shuffle are different.
4991 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4993 // Look for the first non-undef element.
4994 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4995 [](int Elt) {return Elt >= 0;});
4997 // Benefit form APInt to handle overflow when calculating expected element.
4998 unsigned NumElts = VT.getVectorNumElements();
4999 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
5000 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
5001 // The following shuffle indices must be the successive elements after the
5002 // first real element.
5003 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5004 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5005 if (FirstWrongElt != M.end())
5008 // The index of an EXT is the first element if it is not UNDEF.
5009 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5010 // value of the first element. E.g.
5011 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5012 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5013 // ExpectedElt is the last mask index plus 1.
5014 Imm = ExpectedElt.getZExtValue();
5016 // There are two difference cases requiring to reverse input vectors.
5017 // For example, for vector <4 x i32> we have the following cases,
5018 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5019 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5020 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5021 // to reverse two input vectors.
5030 /// isREVMask - Check if a vector shuffle corresponds to a REV
5031 /// instruction with the specified blocksize. (The order of the elements
5032 /// within each block of the vector is reversed.)
5033 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5034 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
5035 "Only possible block sizes for REV are: 16, 32, 64");
5037 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5041 unsigned NumElts = VT.getVectorNumElements();
5042 unsigned BlockElts = M[0] + 1;
5043 // If the first shuffle index is UNDEF, be optimistic.
5045 BlockElts = BlockSize / EltSz;
5047 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5050 for (unsigned i = 0; i < NumElts; ++i) {
5052 continue; // ignore UNDEF indices
5053 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5060 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5061 unsigned NumElts = VT.getVectorNumElements();
5062 WhichResult = (M[0] == 0 ? 0 : 1);
5063 unsigned Idx = WhichResult * NumElts / 2;
5064 for (unsigned i = 0; i != NumElts; i += 2) {
5065 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5066 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5074 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5075 unsigned NumElts = VT.getVectorNumElements();
5076 WhichResult = (M[0] == 0 ? 0 : 1);
5077 for (unsigned i = 0; i != NumElts; ++i) {
5079 continue; // ignore UNDEF indices
5080 if ((unsigned)M[i] != 2 * i + WhichResult)
5087 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5088 unsigned NumElts = VT.getVectorNumElements();
5089 WhichResult = (M[0] == 0 ? 0 : 1);
5090 for (unsigned i = 0; i < NumElts; i += 2) {
5091 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5092 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5098 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5099 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5100 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5101 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5102 unsigned NumElts = VT.getVectorNumElements();
5103 WhichResult = (M[0] == 0 ? 0 : 1);
5104 unsigned Idx = WhichResult * NumElts / 2;
5105 for (unsigned i = 0; i != NumElts; i += 2) {
5106 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5107 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5115 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5116 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5117 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5118 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5119 unsigned Half = VT.getVectorNumElements() / 2;
5120 WhichResult = (M[0] == 0 ? 0 : 1);
5121 for (unsigned j = 0; j != 2; ++j) {
5122 unsigned Idx = WhichResult;
5123 for (unsigned i = 0; i != Half; ++i) {
5124 int MIdx = M[i + j * Half];
5125 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5134 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5135 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5136 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5137 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5138 unsigned NumElts = VT.getVectorNumElements();
5139 WhichResult = (M[0] == 0 ? 0 : 1);
5140 for (unsigned i = 0; i < NumElts; i += 2) {
5141 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5142 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5148 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5149 bool &DstIsLeft, int &Anomaly) {
5150 if (M.size() != static_cast<size_t>(NumInputElements))
5153 int NumLHSMatch = 0, NumRHSMatch = 0;
5154 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5156 for (int i = 0; i < NumInputElements; ++i) {
5166 LastLHSMismatch = i;
5168 if (M[i] == i + NumInputElements)
5171 LastRHSMismatch = i;
5174 if (NumLHSMatch == NumInputElements - 1) {
5176 Anomaly = LastLHSMismatch;
5178 } else if (NumRHSMatch == NumInputElements - 1) {
5180 Anomaly = LastRHSMismatch;
5187 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5188 if (VT.getSizeInBits() != 128)
5191 unsigned NumElts = VT.getVectorNumElements();
5193 for (int I = 0, E = NumElts / 2; I != E; I++) {
5198 int Offset = NumElts / 2;
5199 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5200 if (Mask[I] != I + SplitLHS * Offset)
5207 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5209 EVT VT = Op.getValueType();
5210 SDValue V0 = Op.getOperand(0);
5211 SDValue V1 = Op.getOperand(1);
5212 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5214 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5215 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5218 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
5220 if (!isConcatMask(Mask, VT, SplitV0))
5223 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5224 VT.getVectorNumElements() / 2);
5226 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5227 DAG.getConstant(0, DL, MVT::i64));
5229 if (V1.getValueType().getSizeInBits() == 128) {
5230 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5231 DAG.getConstant(0, DL, MVT::i64));
5233 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5236 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5237 /// the specified operations to build the shuffle.
5238 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5239 SDValue RHS, SelectionDAG &DAG,
5241 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5242 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5243 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5246 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5255 OP_VUZPL, // VUZP, left result
5256 OP_VUZPR, // VUZP, right result
5257 OP_VZIPL, // VZIP, left result
5258 OP_VZIPR, // VZIP, right result
5259 OP_VTRNL, // VTRN, left result
5260 OP_VTRNR // VTRN, right result
5263 if (OpNum == OP_COPY) {
5264 if (LHSID == (1 * 9 + 2) * 9 + 3)
5266 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5270 SDValue OpLHS, OpRHS;
5271 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5272 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5273 EVT VT = OpLHS.getValueType();
5277 llvm_unreachable("Unknown shuffle opcode!");
5279 // VREV divides the vector in half and swaps within the half.
5280 if (VT.getVectorElementType() == MVT::i32 ||
5281 VT.getVectorElementType() == MVT::f32)
5282 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5283 // vrev <4 x i16> -> REV32
5284 if (VT.getVectorElementType() == MVT::i16 ||
5285 VT.getVectorElementType() == MVT::f16)
5286 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5287 // vrev <4 x i8> -> REV16
5288 assert(VT.getVectorElementType() == MVT::i8);
5289 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5294 EVT EltTy = VT.getVectorElementType();
5296 if (EltTy == MVT::i8)
5297 Opcode = AArch64ISD::DUPLANE8;
5298 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5299 Opcode = AArch64ISD::DUPLANE16;
5300 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5301 Opcode = AArch64ISD::DUPLANE32;
5302 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5303 Opcode = AArch64ISD::DUPLANE64;
5305 llvm_unreachable("Invalid vector element type?");
5307 if (VT.getSizeInBits() == 64)
5308 OpLHS = WidenVector(OpLHS, DAG);
5309 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5310 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5315 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5316 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5317 DAG.getConstant(Imm, dl, MVT::i32));
5320 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5323 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5326 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5329 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5332 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5335 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5340 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5341 SelectionDAG &DAG) {
5342 // Check to see if we can use the TBL instruction.
5343 SDValue V1 = Op.getOperand(0);
5344 SDValue V2 = Op.getOperand(1);
5347 EVT EltVT = Op.getValueType().getVectorElementType();
5348 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5350 SmallVector<SDValue, 8> TBLMask;
5351 for (int Val : ShuffleMask) {
5352 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5353 unsigned Offset = Byte + Val * BytesPerElt;
5354 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5358 MVT IndexVT = MVT::v8i8;
5359 unsigned IndexLen = 8;
5360 if (Op.getValueType().getSizeInBits() == 128) {
5361 IndexVT = MVT::v16i8;
5365 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5366 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5369 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5371 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5372 Shuffle = DAG.getNode(
5373 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5374 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5375 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5376 makeArrayRef(TBLMask.data(), IndexLen)));
5378 if (IndexLen == 8) {
5379 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5380 Shuffle = DAG.getNode(
5381 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5382 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5383 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5384 makeArrayRef(TBLMask.data(), IndexLen)));
5386 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5387 // cannot currently represent the register constraints on the input
5389 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5390 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5391 // &TBLMask[0], IndexLen));
5392 Shuffle = DAG.getNode(
5393 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5394 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5396 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5397 makeArrayRef(TBLMask.data(), IndexLen)));
5400 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5403 static unsigned getDUPLANEOp(EVT EltType) {
5404 if (EltType == MVT::i8)
5405 return AArch64ISD::DUPLANE8;
5406 if (EltType == MVT::i16 || EltType == MVT::f16)
5407 return AArch64ISD::DUPLANE16;
5408 if (EltType == MVT::i32 || EltType == MVT::f32)
5409 return AArch64ISD::DUPLANE32;
5410 if (EltType == MVT::i64 || EltType == MVT::f64)
5411 return AArch64ISD::DUPLANE64;
5413 llvm_unreachable("Invalid vector element type?");
5416 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5417 SelectionDAG &DAG) const {
5419 EVT VT = Op.getValueType();
5421 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5423 // Convert shuffles that are directly supported on NEON to target-specific
5424 // DAG nodes, instead of keeping them as shuffles and matching them again
5425 // during code selection. This is more efficient and avoids the possibility
5426 // of inconsistencies between legalization and selection.
5427 ArrayRef<int> ShuffleMask = SVN->getMask();
5429 SDValue V1 = Op.getOperand(0);
5430 SDValue V2 = Op.getOperand(1);
5432 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5433 V1.getValueType().getSimpleVT())) {
5434 int Lane = SVN->getSplatIndex();
5435 // If this is undef splat, generate it via "just" vdup, if possible.
5439 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5440 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5442 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5443 // constant. If so, we can just reference the lane's definition directly.
5444 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5445 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5446 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5448 // Otherwise, duplicate from the lane of the input vector.
5449 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5451 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5452 // to make a vector of the same size as this SHUFFLE. We can ignore the
5453 // extract entirely, and canonicalise the concat using WidenVector.
5454 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5455 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5456 V1 = V1.getOperand(0);
5457 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5458 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5459 Lane -= Idx * VT.getVectorNumElements() / 2;
5460 V1 = WidenVector(V1.getOperand(Idx), DAG);
5461 } else if (VT.getSizeInBits() == 64)
5462 V1 = WidenVector(V1, DAG);
5464 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5467 if (isREVMask(ShuffleMask, VT, 64))
5468 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5469 if (isREVMask(ShuffleMask, VT, 32))
5470 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5471 if (isREVMask(ShuffleMask, VT, 16))
5472 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5474 bool ReverseEXT = false;
5476 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5479 Imm *= getExtFactor(V1);
5480 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5481 DAG.getConstant(Imm, dl, MVT::i32));
5482 } else if (V2->getOpcode() == ISD::UNDEF &&
5483 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5484 Imm *= getExtFactor(V1);
5485 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5486 DAG.getConstant(Imm, dl, MVT::i32));
5489 unsigned WhichResult;
5490 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5491 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5492 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5494 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5495 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5496 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5498 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5499 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5500 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5503 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5504 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5505 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5507 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5508 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5509 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5511 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5512 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5513 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5516 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5517 if (Concat.getNode())
5522 int NumInputElements = V1.getValueType().getVectorNumElements();
5523 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5524 SDValue DstVec = DstIsLeft ? V1 : V2;
5525 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5527 SDValue SrcVec = V1;
5528 int SrcLane = ShuffleMask[Anomaly];
5529 if (SrcLane >= NumInputElements) {
5531 SrcLane -= VT.getVectorNumElements();
5533 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5535 EVT ScalarVT = VT.getVectorElementType();
5537 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5538 ScalarVT = MVT::i32;
5541 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5542 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5546 // If the shuffle is not directly supported and it has 4 elements, use
5547 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5548 unsigned NumElts = VT.getVectorNumElements();
5550 unsigned PFIndexes[4];
5551 for (unsigned i = 0; i != 4; ++i) {
5552 if (ShuffleMask[i] < 0)
5555 PFIndexes[i] = ShuffleMask[i];
5558 // Compute the index in the perfect shuffle table.
5559 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5560 PFIndexes[2] * 9 + PFIndexes[3];
5561 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5562 unsigned Cost = (PFEntry >> 30);
5565 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5568 return GenerateTBL(Op, ShuffleMask, DAG);
5571 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5573 EVT VT = BVN->getValueType(0);
5574 APInt SplatBits, SplatUndef;
5575 unsigned SplatBitSize;
5577 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5578 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5580 for (unsigned i = 0; i < NumSplats; ++i) {
5581 CnstBits <<= SplatBitSize;
5582 UndefBits <<= SplatBitSize;
5583 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5584 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5593 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5594 SelectionDAG &DAG) const {
5595 BuildVectorSDNode *BVN =
5596 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5597 SDValue LHS = Op.getOperand(0);
5599 EVT VT = Op.getValueType();
5604 APInt CnstBits(VT.getSizeInBits(), 0);
5605 APInt UndefBits(VT.getSizeInBits(), 0);
5606 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5607 // We only have BIC vector immediate instruction, which is and-not.
5608 CnstBits = ~CnstBits;
5610 // We make use of a little bit of goto ickiness in order to avoid having to
5611 // duplicate the immediate matching logic for the undef toggled case.
5612 bool SecondTry = false;
5615 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5616 CnstBits = CnstBits.zextOrTrunc(64);
5617 uint64_t CnstVal = CnstBits.getZExtValue();
5619 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5620 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5621 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5622 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5623 DAG.getConstant(CnstVal, dl, MVT::i32),
5624 DAG.getConstant(0, dl, MVT::i32));
5625 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5628 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5629 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5630 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5631 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5632 DAG.getConstant(CnstVal, dl, MVT::i32),
5633 DAG.getConstant(8, dl, MVT::i32));
5634 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5637 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5638 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5639 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5640 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5641 DAG.getConstant(CnstVal, dl, MVT::i32),
5642 DAG.getConstant(16, dl, MVT::i32));
5643 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5646 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5647 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5648 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5649 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5650 DAG.getConstant(CnstVal, dl, MVT::i32),
5651 DAG.getConstant(24, dl, MVT::i32));
5652 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5655 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5656 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5657 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5658 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5659 DAG.getConstant(CnstVal, dl, MVT::i32),
5660 DAG.getConstant(0, dl, MVT::i32));
5661 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5664 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5665 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5666 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5667 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5668 DAG.getConstant(CnstVal, dl, MVT::i32),
5669 DAG.getConstant(8, dl, MVT::i32));
5670 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5677 CnstBits = ~UndefBits;
5681 // We can always fall back to a non-immediate AND.
5686 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5687 // consists of only the same constant int value, returned in reference arg
5689 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5690 uint64_t &ConstVal) {
5691 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5694 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5697 EVT VT = Bvec->getValueType(0);
5698 unsigned NumElts = VT.getVectorNumElements();
5699 for (unsigned i = 1; i < NumElts; ++i)
5700 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5702 ConstVal = FirstElt->getZExtValue();
5706 static unsigned getIntrinsicID(const SDNode *N) {
5707 unsigned Opcode = N->getOpcode();
5710 return Intrinsic::not_intrinsic;
5711 case ISD::INTRINSIC_WO_CHAIN: {
5712 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5713 if (IID < Intrinsic::num_intrinsics)
5715 return Intrinsic::not_intrinsic;
5720 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5721 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5722 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5723 // Also, logical shift right -> sri, with the same structure.
5724 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5725 EVT VT = N->getValueType(0);
5732 // Is the first op an AND?
5733 const SDValue And = N->getOperand(0);
5734 if (And.getOpcode() != ISD::AND)
5737 // Is the second op an shl or lshr?
5738 SDValue Shift = N->getOperand(1);
5739 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5740 // or AArch64ISD::VLSHR vector, #shift
5741 unsigned ShiftOpc = Shift.getOpcode();
5742 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5744 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5746 // Is the shift amount constant?
5747 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5751 // Is the and mask vector all constant?
5753 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5756 // Is C1 == ~C2, taking into account how much one can shift elements of a
5758 uint64_t C2 = C2node->getZExtValue();
5759 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5760 if (C2 > ElemSizeInBits)
5762 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5763 if ((C1 & ElemMask) != (~C2 & ElemMask))
5766 SDValue X = And.getOperand(0);
5767 SDValue Y = Shift.getOperand(0);
5770 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5772 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5773 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5774 Shift.getOperand(1));
5776 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5777 DEBUG(N->dump(&DAG));
5778 DEBUG(dbgs() << "into: \n");
5779 DEBUG(ResultSLI->dump(&DAG));
5785 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5786 SelectionDAG &DAG) const {
5787 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5788 if (EnableAArch64SlrGeneration) {
5789 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5794 BuildVectorSDNode *BVN =
5795 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5796 SDValue LHS = Op.getOperand(1);
5798 EVT VT = Op.getValueType();
5800 // OR commutes, so try swapping the operands.
5802 LHS = Op.getOperand(0);
5803 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5808 APInt CnstBits(VT.getSizeInBits(), 0);
5809 APInt UndefBits(VT.getSizeInBits(), 0);
5810 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5811 // We make use of a little bit of goto ickiness in order to avoid having to
5812 // duplicate the immediate matching logic for the undef toggled case.
5813 bool SecondTry = false;
5816 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5817 CnstBits = CnstBits.zextOrTrunc(64);
5818 uint64_t CnstVal = CnstBits.getZExtValue();
5820 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5821 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5822 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5823 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5824 DAG.getConstant(CnstVal, dl, MVT::i32),
5825 DAG.getConstant(0, dl, MVT::i32));
5826 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5829 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5830 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5831 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5832 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5833 DAG.getConstant(CnstVal, dl, MVT::i32),
5834 DAG.getConstant(8, dl, MVT::i32));
5835 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5838 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5839 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5840 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5841 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5842 DAG.getConstant(CnstVal, dl, MVT::i32),
5843 DAG.getConstant(16, dl, MVT::i32));
5844 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5847 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5848 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5849 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5850 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5851 DAG.getConstant(CnstVal, dl, MVT::i32),
5852 DAG.getConstant(24, dl, MVT::i32));
5853 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5856 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5857 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5858 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5859 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5860 DAG.getConstant(CnstVal, dl, MVT::i32),
5861 DAG.getConstant(0, dl, MVT::i32));
5862 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5865 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5866 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5867 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5868 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5869 DAG.getConstant(CnstVal, dl, MVT::i32),
5870 DAG.getConstant(8, dl, MVT::i32));
5871 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5878 CnstBits = UndefBits;
5882 // We can always fall back to a non-immediate OR.
5887 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5888 // be truncated to fit element width.
5889 static SDValue NormalizeBuildVector(SDValue Op,
5890 SelectionDAG &DAG) {
5891 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5893 EVT VT = Op.getValueType();
5894 EVT EltTy= VT.getVectorElementType();
5896 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5899 SmallVector<SDValue, 16> Ops;
5900 for (SDValue Lane : Op->ops()) {
5901 if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
5902 APInt LowBits(EltTy.getSizeInBits(),
5903 CstLane->getZExtValue());
5904 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5906 Ops.push_back(Lane);
5908 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5911 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5912 SelectionDAG &DAG) const {
5914 EVT VT = Op.getValueType();
5915 Op = NormalizeBuildVector(Op, DAG);
5916 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5918 APInt CnstBits(VT.getSizeInBits(), 0);
5919 APInt UndefBits(VT.getSizeInBits(), 0);
5920 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5921 // We make use of a little bit of goto ickiness in order to avoid having to
5922 // duplicate the immediate matching logic for the undef toggled case.
5923 bool SecondTry = false;
5926 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5927 CnstBits = CnstBits.zextOrTrunc(64);
5928 uint64_t CnstVal = CnstBits.getZExtValue();
5930 // Certain magic vector constants (used to express things like NOT
5931 // and NEG) are passed through unmodified. This allows codegen patterns
5932 // for these operations to match. Special-purpose patterns will lower
5933 // these immediates to MOVIs if it proves necessary.
5934 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5937 // The many faces of MOVI...
5938 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5939 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5940 if (VT.getSizeInBits() == 128) {
5941 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5942 DAG.getConstant(CnstVal, dl, MVT::i32));
5943 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5946 // Support the V64 version via subregister insertion.
5947 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5948 DAG.getConstant(CnstVal, dl, MVT::i32));
5949 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5952 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5953 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5954 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5955 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5956 DAG.getConstant(CnstVal, dl, MVT::i32),
5957 DAG.getConstant(0, dl, MVT::i32));
5958 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5961 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5962 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5963 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5964 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5965 DAG.getConstant(CnstVal, dl, MVT::i32),
5966 DAG.getConstant(8, dl, MVT::i32));
5967 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5970 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5971 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5972 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5973 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5974 DAG.getConstant(CnstVal, dl, MVT::i32),
5975 DAG.getConstant(16, dl, MVT::i32));
5976 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5979 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5980 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5981 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5982 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5983 DAG.getConstant(CnstVal, dl, MVT::i32),
5984 DAG.getConstant(24, dl, MVT::i32));
5985 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5988 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5989 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5990 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5991 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5992 DAG.getConstant(CnstVal, dl, MVT::i32),
5993 DAG.getConstant(0, dl, MVT::i32));
5994 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5997 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5998 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5999 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6000 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6001 DAG.getConstant(CnstVal, dl, MVT::i32),
6002 DAG.getConstant(8, dl, MVT::i32));
6003 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6006 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6007 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6008 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6009 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6010 DAG.getConstant(CnstVal, dl, MVT::i32),
6011 DAG.getConstant(264, dl, MVT::i32));
6012 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6015 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6016 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6017 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6018 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6019 DAG.getConstant(CnstVal, dl, MVT::i32),
6020 DAG.getConstant(272, dl, MVT::i32));
6021 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6024 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
6025 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
6026 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6027 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
6028 DAG.getConstant(CnstVal, dl, MVT::i32));
6029 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6032 // The few faces of FMOV...
6033 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
6034 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
6035 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6036 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
6037 DAG.getConstant(CnstVal, dl, MVT::i32));
6038 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6041 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
6042 VT.getSizeInBits() == 128) {
6043 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
6044 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
6045 DAG.getConstant(CnstVal, dl, MVT::i32));
6046 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6049 // The many faces of MVNI...
6051 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6052 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6053 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6054 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6055 DAG.getConstant(CnstVal, dl, MVT::i32),
6056 DAG.getConstant(0, dl, MVT::i32));
6057 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6060 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6061 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6062 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6063 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6064 DAG.getConstant(CnstVal, dl, MVT::i32),
6065 DAG.getConstant(8, dl, MVT::i32));
6066 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6069 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6070 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6071 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6072 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6073 DAG.getConstant(CnstVal, dl, MVT::i32),
6074 DAG.getConstant(16, dl, MVT::i32));
6075 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6078 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6079 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6080 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6081 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6082 DAG.getConstant(CnstVal, dl, MVT::i32),
6083 DAG.getConstant(24, dl, MVT::i32));
6084 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6087 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6088 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6089 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6090 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6091 DAG.getConstant(CnstVal, dl, MVT::i32),
6092 DAG.getConstant(0, dl, MVT::i32));
6093 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6096 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6097 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6098 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6099 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6100 DAG.getConstant(CnstVal, dl, MVT::i32),
6101 DAG.getConstant(8, dl, MVT::i32));
6102 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6105 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6106 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6107 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6108 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6109 DAG.getConstant(CnstVal, dl, MVT::i32),
6110 DAG.getConstant(264, dl, MVT::i32));
6111 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6114 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6115 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6116 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6117 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6118 DAG.getConstant(CnstVal, dl, MVT::i32),
6119 DAG.getConstant(272, dl, MVT::i32));
6120 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6127 CnstBits = UndefBits;
6132 // Scan through the operands to find some interesting properties we can
6134 // 1) If only one value is used, we can use a DUP, or
6135 // 2) if only the low element is not undef, we can just insert that, or
6136 // 3) if only one constant value is used (w/ some non-constant lanes),
6137 // we can splat the constant value into the whole vector then fill
6138 // in the non-constant lanes.
6139 // 4) FIXME: If different constant values are used, but we can intelligently
6140 // select the values we'll be overwriting for the non-constant
6141 // lanes such that we can directly materialize the vector
6142 // some other way (MOVI, e.g.), we can be sneaky.
6143 unsigned NumElts = VT.getVectorNumElements();
6144 bool isOnlyLowElement = true;
6145 bool usesOnlyOneValue = true;
6146 bool usesOnlyOneConstantValue = true;
6147 bool isConstant = true;
6148 unsigned NumConstantLanes = 0;
6150 SDValue ConstantValue;
6151 for (unsigned i = 0; i < NumElts; ++i) {
6152 SDValue V = Op.getOperand(i);
6153 if (V.getOpcode() == ISD::UNDEF)
6156 isOnlyLowElement = false;
6157 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6160 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
6162 if (!ConstantValue.getNode())
6164 else if (ConstantValue != V)
6165 usesOnlyOneConstantValue = false;
6168 if (!Value.getNode())
6170 else if (V != Value)
6171 usesOnlyOneValue = false;
6174 if (!Value.getNode())
6175 return DAG.getUNDEF(VT);
6177 if (isOnlyLowElement)
6178 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6180 // Use DUP for non-constant splats. For f32 constant splats, reduce to
6181 // i32 and try again.
6182 if (usesOnlyOneValue) {
6184 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6185 Value.getValueType() != VT)
6186 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6188 // This is actually a DUPLANExx operation, which keeps everything vectory.
6190 // DUPLANE works on 128-bit vectors, widen it if necessary.
6191 SDValue Lane = Value.getOperand(1);
6192 Value = Value.getOperand(0);
6193 if (Value.getValueType().getSizeInBits() == 64)
6194 Value = WidenVector(Value, DAG);
6196 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6197 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6200 if (VT.getVectorElementType().isFloatingPoint()) {
6201 SmallVector<SDValue, 8> Ops;
6202 EVT EltTy = VT.getVectorElementType();
6203 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
6204 "Unsupported floating-point vector type");
6205 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
6206 for (unsigned i = 0; i < NumElts; ++i)
6207 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
6208 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
6209 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
6210 Val = LowerBUILD_VECTOR(Val, DAG);
6212 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6216 // If there was only one constant value used and for more than one lane,
6217 // start by splatting that value, then replace the non-constant lanes. This
6218 // is better than the default, which will perform a separate initialization
6220 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6221 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6222 // Now insert the non-constant lanes.
6223 for (unsigned i = 0; i < NumElts; ++i) {
6224 SDValue V = Op.getOperand(i);
6225 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6226 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6227 // Note that type legalization likely mucked about with the VT of the
6228 // source operand, so we may have to convert it here before inserting.
6229 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6235 // If all elements are constants and the case above didn't get hit, fall back
6236 // to the default expansion, which will generate a load from the constant
6241 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6243 if (SDValue shuffle = ReconstructShuffle(Op, DAG))
6247 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6248 // know the default expansion would otherwise fall back on something even
6249 // worse. For a vector with one or two non-undef values, that's
6250 // scalar_to_vector for the elements followed by a shuffle (provided the
6251 // shuffle is valid for the target) and materialization element by element
6252 // on the stack followed by a load for everything else.
6253 if (!isConstant && !usesOnlyOneValue) {
6254 SDValue Vec = DAG.getUNDEF(VT);
6255 SDValue Op0 = Op.getOperand(0);
6256 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6258 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6259 // a) Avoid a RMW dependency on the full vector register, and
6260 // b) Allow the register coalescer to fold away the copy if the
6261 // value is already in an S or D register.
6262 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6263 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6265 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6266 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6267 Vec = SDValue(N, 0);
6270 for (; i < NumElts; ++i) {
6271 SDValue V = Op.getOperand(i);
6272 if (V.getOpcode() == ISD::UNDEF)
6274 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6275 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6280 // Just use the default expansion. We failed to find a better alternative.
6284 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6285 SelectionDAG &DAG) const {
6286 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6288 // Check for non-constant or out of range lane.
6289 EVT VT = Op.getOperand(0).getValueType();
6290 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6291 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6295 // Insertion/extraction are legal for V128 types.
6296 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6297 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6301 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6302 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6305 // For V64 types, we perform insertion by expanding the value
6306 // to a V128 type and perform the insertion on that.
6308 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6309 EVT WideTy = WideVec.getValueType();
6311 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6312 Op.getOperand(1), Op.getOperand(2));
6313 // Re-narrow the resultant vector.
6314 return NarrowVector(Node, DAG);
6318 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6319 SelectionDAG &DAG) const {
6320 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6322 // Check for non-constant or out of range lane.
6323 EVT VT = Op.getOperand(0).getValueType();
6324 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6325 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6329 // Insertion/extraction are legal for V128 types.
6330 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6331 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6335 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6336 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6339 // For V64 types, we perform extraction by expanding the value
6340 // to a V128 type and perform the extraction on that.
6342 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6343 EVT WideTy = WideVec.getValueType();
6345 EVT ExtrTy = WideTy.getVectorElementType();
6346 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6349 // For extractions, we just return the result directly.
6350 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6354 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6355 SelectionDAG &DAG) const {
6356 EVT VT = Op.getOperand(0).getValueType();
6362 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6365 unsigned Val = Cst->getZExtValue();
6367 unsigned Size = Op.getValueType().getSizeInBits();
6371 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6374 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6377 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6380 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6383 llvm_unreachable("Unexpected vector type in extract_subvector!");
6386 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6388 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6394 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6396 if (VT.getVectorNumElements() == 4 &&
6397 (VT.is128BitVector() || VT.is64BitVector())) {
6398 unsigned PFIndexes[4];
6399 for (unsigned i = 0; i != 4; ++i) {
6403 PFIndexes[i] = M[i];
6406 // Compute the index in the perfect shuffle table.
6407 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6408 PFIndexes[2] * 9 + PFIndexes[3];
6409 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6410 unsigned Cost = (PFEntry >> 30);
6418 unsigned DummyUnsigned;
6420 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6421 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6422 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6423 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6424 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6425 isZIPMask(M, VT, DummyUnsigned) ||
6426 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6427 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6428 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6429 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6430 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6433 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6434 /// operand of a vector shift operation, where all the elements of the
6435 /// build_vector must have the same constant integer value.
6436 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6437 // Ignore bit_converts.
6438 while (Op.getOpcode() == ISD::BITCAST)
6439 Op = Op.getOperand(0);
6440 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6441 APInt SplatBits, SplatUndef;
6442 unsigned SplatBitSize;
6444 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6445 HasAnyUndefs, ElementBits) ||
6446 SplatBitSize > ElementBits)
6448 Cnt = SplatBits.getSExtValue();
6452 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6453 /// operand of a vector shift left operation. That value must be in the range:
6454 /// 0 <= Value < ElementBits for a left shift; or
6455 /// 0 <= Value <= ElementBits for a long left shift.
6456 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6457 assert(VT.isVector() && "vector shift count is not a vector type");
6458 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6459 if (!getVShiftImm(Op, ElementBits, Cnt))
6461 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6464 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6465 /// operand of a vector shift right operation. The value must be in the range:
6466 /// 1 <= Value <= ElementBits for a right shift; or
6467 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6468 assert(VT.isVector() && "vector shift count is not a vector type");
6469 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6470 if (!getVShiftImm(Op, ElementBits, Cnt))
6472 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6475 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6476 SelectionDAG &DAG) const {
6477 EVT VT = Op.getValueType();
6481 if (!Op.getOperand(1).getValueType().isVector())
6483 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6485 switch (Op.getOpcode()) {
6487 llvm_unreachable("unexpected shift opcode");
6490 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6491 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6492 DAG.getConstant(Cnt, DL, MVT::i32));
6493 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6494 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6496 Op.getOperand(0), Op.getOperand(1));
6499 // Right shift immediate
6500 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6502 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6503 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6504 DAG.getConstant(Cnt, DL, MVT::i32));
6507 // Right shift register. Note, there is not a shift right register
6508 // instruction, but the shift left register instruction takes a signed
6509 // value, where negative numbers specify a right shift.
6510 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6511 : Intrinsic::aarch64_neon_ushl;
6512 // negate the shift amount
6513 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6514 SDValue NegShiftLeft =
6515 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6516 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6518 return NegShiftLeft;
6524 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6525 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6526 SDLoc dl, SelectionDAG &DAG) {
6527 EVT SrcVT = LHS.getValueType();
6528 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6529 "function only supposed to emit natural comparisons");
6531 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6532 APInt CnstBits(VT.getSizeInBits(), 0);
6533 APInt UndefBits(VT.getSizeInBits(), 0);
6534 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6535 bool IsZero = IsCnst && (CnstBits == 0);
6537 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6541 case AArch64CC::NE: {
6544 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6546 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6547 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6551 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6552 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6555 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6556 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6559 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6560 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6563 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6564 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6568 // If we ignore NaNs then we can use to the MI implementation.
6572 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6573 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6580 case AArch64CC::NE: {
6583 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6585 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6586 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6590 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6591 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6594 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6595 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6598 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6599 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6602 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6603 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6605 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6607 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6610 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6611 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6613 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6615 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6619 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6620 SelectionDAG &DAG) const {
6621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6622 SDValue LHS = Op.getOperand(0);
6623 SDValue RHS = Op.getOperand(1);
6624 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6627 if (LHS.getValueType().getVectorElementType().isInteger()) {
6628 assert(LHS.getValueType() == RHS.getValueType());
6629 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6631 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6632 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6635 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6636 LHS.getValueType().getVectorElementType() == MVT::f64);
6638 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6639 // clean. Some of them require two branches to implement.
6640 AArch64CC::CondCode CC1, CC2;
6642 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6644 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6646 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6650 if (CC2 != AArch64CC::AL) {
6652 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6653 if (!Cmp2.getNode())
6656 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6659 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6662 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6667 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6668 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6669 /// specified in the intrinsic calls.
6670 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6672 unsigned Intrinsic) const {
6673 auto &DL = I.getModule()->getDataLayout();
6674 switch (Intrinsic) {
6675 case Intrinsic::aarch64_neon_ld2:
6676 case Intrinsic::aarch64_neon_ld3:
6677 case Intrinsic::aarch64_neon_ld4:
6678 case Intrinsic::aarch64_neon_ld1x2:
6679 case Intrinsic::aarch64_neon_ld1x3:
6680 case Intrinsic::aarch64_neon_ld1x4:
6681 case Intrinsic::aarch64_neon_ld2lane:
6682 case Intrinsic::aarch64_neon_ld3lane:
6683 case Intrinsic::aarch64_neon_ld4lane:
6684 case Intrinsic::aarch64_neon_ld2r:
6685 case Intrinsic::aarch64_neon_ld3r:
6686 case Intrinsic::aarch64_neon_ld4r: {
6687 Info.opc = ISD::INTRINSIC_W_CHAIN;
6688 // Conservatively set memVT to the entire set of vectors loaded.
6689 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
6690 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6691 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6694 Info.vol = false; // volatile loads with NEON intrinsics not supported
6695 Info.readMem = true;
6696 Info.writeMem = false;
6699 case Intrinsic::aarch64_neon_st2:
6700 case Intrinsic::aarch64_neon_st3:
6701 case Intrinsic::aarch64_neon_st4:
6702 case Intrinsic::aarch64_neon_st1x2:
6703 case Intrinsic::aarch64_neon_st1x3:
6704 case Intrinsic::aarch64_neon_st1x4:
6705 case Intrinsic::aarch64_neon_st2lane:
6706 case Intrinsic::aarch64_neon_st3lane:
6707 case Intrinsic::aarch64_neon_st4lane: {
6708 Info.opc = ISD::INTRINSIC_VOID;
6709 // Conservatively set memVT to the entire set of vectors stored.
6710 unsigned NumElts = 0;
6711 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6712 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6713 if (!ArgTy->isVectorTy())
6715 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
6717 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6718 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6721 Info.vol = false; // volatile stores with NEON intrinsics not supported
6722 Info.readMem = false;
6723 Info.writeMem = true;
6726 case Intrinsic::aarch64_ldaxr:
6727 case Intrinsic::aarch64_ldxr: {
6728 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6729 Info.opc = ISD::INTRINSIC_W_CHAIN;
6730 Info.memVT = MVT::getVT(PtrTy->getElementType());
6731 Info.ptrVal = I.getArgOperand(0);
6733 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6735 Info.readMem = true;
6736 Info.writeMem = false;
6739 case Intrinsic::aarch64_stlxr:
6740 case Intrinsic::aarch64_stxr: {
6741 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6742 Info.opc = ISD::INTRINSIC_W_CHAIN;
6743 Info.memVT = MVT::getVT(PtrTy->getElementType());
6744 Info.ptrVal = I.getArgOperand(1);
6746 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6748 Info.readMem = false;
6749 Info.writeMem = true;
6752 case Intrinsic::aarch64_ldaxp:
6753 case Intrinsic::aarch64_ldxp: {
6754 Info.opc = ISD::INTRINSIC_W_CHAIN;
6755 Info.memVT = MVT::i128;
6756 Info.ptrVal = I.getArgOperand(0);
6760 Info.readMem = true;
6761 Info.writeMem = false;
6764 case Intrinsic::aarch64_stlxp:
6765 case Intrinsic::aarch64_stxp: {
6766 Info.opc = ISD::INTRINSIC_W_CHAIN;
6767 Info.memVT = MVT::i128;
6768 Info.ptrVal = I.getArgOperand(2);
6772 Info.readMem = false;
6773 Info.writeMem = true;
6783 // Truncations from 64-bit GPR to 32-bit GPR is free.
6784 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6785 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6787 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6788 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6789 return NumBits1 > NumBits2;
6791 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6792 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6794 unsigned NumBits1 = VT1.getSizeInBits();
6795 unsigned NumBits2 = VT2.getSizeInBits();
6796 return NumBits1 > NumBits2;
6799 /// Check if it is profitable to hoist instruction in then/else to if.
6800 /// Not profitable if I and it's user can form a FMA instruction
6801 /// because we prefer FMSUB/FMADD.
6802 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6803 if (I->getOpcode() != Instruction::FMul)
6806 if (I->getNumUses() != 1)
6809 Instruction *User = I->user_back();
6812 !(User->getOpcode() == Instruction::FSub ||
6813 User->getOpcode() == Instruction::FAdd))
6816 const TargetOptions &Options = getTargetMachine().Options;
6817 const DataLayout &DL = I->getModule()->getDataLayout();
6818 EVT VT = getValueType(DL, User->getOperand(0)->getType());
6820 if (isFMAFasterThanFMulAndFAdd(VT) &&
6821 isOperationLegalOrCustom(ISD::FMA, VT) &&
6822 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6828 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6830 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6831 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6833 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6834 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6835 return NumBits1 == 32 && NumBits2 == 64;
6837 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6838 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6840 unsigned NumBits1 = VT1.getSizeInBits();
6841 unsigned NumBits2 = VT2.getSizeInBits();
6842 return NumBits1 == 32 && NumBits2 == 64;
6845 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6846 EVT VT1 = Val.getValueType();
6847 if (isZExtFree(VT1, VT2)) {
6851 if (Val.getOpcode() != ISD::LOAD)
6854 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6855 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6856 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6857 VT1.getSizeInBits() <= 32);
6860 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6861 if (isa<FPExtInst>(Ext))
6864 // Vector types are next free.
6865 if (Ext->getType()->isVectorTy())
6868 for (const Use &U : Ext->uses()) {
6869 // The extension is free if we can fold it with a left shift in an
6870 // addressing mode or an arithmetic operation: add, sub, and cmp.
6872 // Is there a shift?
6873 const Instruction *Instr = cast<Instruction>(U.getUser());
6875 // Is this a constant shift?
6876 switch (Instr->getOpcode()) {
6877 case Instruction::Shl:
6878 if (!isa<ConstantInt>(Instr->getOperand(1)))
6881 case Instruction::GetElementPtr: {
6882 gep_type_iterator GTI = gep_type_begin(Instr);
6883 auto &DL = Ext->getModule()->getDataLayout();
6884 std::advance(GTI, U.getOperandNo());
6886 // This extension will end up with a shift because of the scaling factor.
6887 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6888 // Get the shift amount based on the scaling factor:
6889 // log2(sizeof(IdxTy)) - log2(8).
6891 countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy)) - 3;
6892 // Is the constant foldable in the shift of the addressing mode?
6893 // I.e., shift amount is between 1 and 4 inclusive.
6894 if (ShiftAmt == 0 || ShiftAmt > 4)
6898 case Instruction::Trunc:
6899 // Check if this is a noop.
6900 // trunc(sext ty1 to ty2) to ty1.
6901 if (Instr->getType() == Ext->getOperand(0)->getType())
6908 // At this point we can use the bfm family, so this extension is free
6914 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6915 unsigned &RequiredAligment) const {
6916 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6918 // Cyclone supports unaligned accesses.
6919 RequiredAligment = 0;
6920 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6921 return NumBits == 32 || NumBits == 64;
6924 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6925 unsigned &RequiredAligment) const {
6926 if (!LoadedType.isSimple() ||
6927 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6929 // Cyclone supports unaligned accesses.
6930 RequiredAligment = 0;
6931 unsigned NumBits = LoadedType.getSizeInBits();
6932 return NumBits == 32 || NumBits == 64;
6935 /// \brief Lower an interleaved load into a ldN intrinsic.
6937 /// E.g. Lower an interleaved load (Factor = 2):
6938 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6939 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6940 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6943 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6944 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6945 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6946 bool AArch64TargetLowering::lowerInterleavedLoad(
6947 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6948 ArrayRef<unsigned> Indices, unsigned Factor) const {
6949 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6950 "Invalid interleave factor");
6951 assert(!Shuffles.empty() && "Empty shufflevector input");
6952 assert(Shuffles.size() == Indices.size() &&
6953 "Unmatched number of shufflevectors and indices");
6955 const DataLayout &DL = LI->getModule()->getDataLayout();
6957 VectorType *VecTy = Shuffles[0]->getType();
6958 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
6960 // Skip illegal vector types.
6961 if (VecSize != 64 && VecSize != 128)
6964 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6965 // load integer vectors first and then convert to pointer vectors.
6966 Type *EltTy = VecTy->getVectorElementType();
6967 if (EltTy->isPointerTy())
6969 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
6971 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
6972 Type *Tys[2] = {VecTy, PtrTy};
6973 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
6974 Intrinsic::aarch64_neon_ld3,
6975 Intrinsic::aarch64_neon_ld4};
6977 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
6979 IRBuilder<> Builder(LI);
6980 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
6982 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
6984 // Replace uses of each shufflevector with the corresponding vector loaded
6986 for (unsigned i = 0; i < Shuffles.size(); i++) {
6987 ShuffleVectorInst *SVI = Shuffles[i];
6988 unsigned Index = Indices[i];
6990 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
6992 // Convert the integer vector to pointer vector if the element is pointer.
6993 if (EltTy->isPointerTy())
6994 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
6996 SVI->replaceAllUsesWith(SubVec);
7002 /// \brief Get a mask consisting of sequential integers starting from \p Start.
7004 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
7005 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
7007 SmallVector<Constant *, 16> Mask;
7008 for (unsigned i = 0; i < NumElts; i++)
7009 Mask.push_back(Builder.getInt32(Start + i));
7011 return ConstantVector::get(Mask);
7014 /// \brief Lower an interleaved store into a stN intrinsic.
7016 /// E.g. Lower an interleaved store (Factor = 3):
7017 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7018 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
7019 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7022 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7023 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7024 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7025 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7027 /// Note that the new shufflevectors will be removed and we'll only generate one
7028 /// st3 instruction in CodeGen.
7029 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7030 ShuffleVectorInst *SVI,
7031 unsigned Factor) const {
7032 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7033 "Invalid interleave factor");
7035 VectorType *VecTy = SVI->getType();
7036 assert(VecTy->getVectorNumElements() % Factor == 0 &&
7037 "Invalid interleaved store");
7039 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
7040 Type *EltTy = VecTy->getVectorElementType();
7041 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
7043 const DataLayout &DL = SI->getModule()->getDataLayout();
7044 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
7046 // Skip illegal vector types.
7047 if (SubVecSize != 64 && SubVecSize != 128)
7050 Value *Op0 = SVI->getOperand(0);
7051 Value *Op1 = SVI->getOperand(1);
7052 IRBuilder<> Builder(SI);
7054 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
7055 // vectors to integer vectors.
7056 if (EltTy->isPointerTy()) {
7057 Type *IntTy = DL.getIntPtrType(EltTy);
7058 unsigned NumOpElts =
7059 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
7061 // Convert to the corresponding integer vector.
7062 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
7063 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
7064 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
7066 SubVecTy = VectorType::get(IntTy, NumSubElts);
7069 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
7070 Type *Tys[2] = {SubVecTy, PtrTy};
7071 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
7072 Intrinsic::aarch64_neon_st3,
7073 Intrinsic::aarch64_neon_st4};
7075 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
7077 SmallVector<Value *, 5> Ops;
7079 // Split the shufflevector operands into sub vectors for the new stN call.
7080 for (unsigned i = 0; i < Factor; i++)
7081 Ops.push_back(Builder.CreateShuffleVector(
7082 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
7084 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
7085 Builder.CreateCall(StNFunc, Ops);
7089 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
7090 unsigned AlignCheck) {
7091 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
7092 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7095 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7096 unsigned SrcAlign, bool IsMemset,
7099 MachineFunction &MF) const {
7100 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
7101 // instruction to materialize the v2i64 zero and one store (with restrictive
7102 // addressing mode). Just do two i64 store of zero-registers.
7104 const Function *F = MF.getFunction();
7105 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
7106 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
7107 (memOpAlign(SrcAlign, DstAlign, 16) ||
7108 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
7112 (memOpAlign(SrcAlign, DstAlign, 8) ||
7113 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
7117 (memOpAlign(SrcAlign, DstAlign, 4) ||
7118 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
7124 // 12-bit optionally shifted immediates are legal for adds.
7125 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7126 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
7131 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
7132 // immediates is the same as for an add or a sub.
7133 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7136 return isLegalAddImmediate(Immed);
7139 /// isLegalAddressingMode - Return true if the addressing mode represented
7140 /// by AM is legal for this target, for a load/store of the specified type.
7141 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7142 const AddrMode &AM, Type *Ty,
7143 unsigned AS) const {
7144 // AArch64 has five basic addressing modes:
7146 // reg + 9-bit signed offset
7147 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
7149 // reg + SIZE_IN_BYTES * reg
7151 // No global is ever allowed as a base.
7155 // No reg+reg+imm addressing.
7156 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
7159 // check reg + imm case:
7160 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
7161 uint64_t NumBytes = 0;
7162 if (Ty->isSized()) {
7163 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
7164 NumBytes = NumBits / 8;
7165 if (!isPowerOf2_64(NumBits))
7170 int64_t Offset = AM.BaseOffs;
7172 // 9-bit signed offset
7173 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
7176 // 12-bit unsigned offset
7177 unsigned shift = Log2_64(NumBytes);
7178 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
7179 // Must be a multiple of NumBytes (NumBytes is a power of 2)
7180 (Offset >> shift) << shift == Offset)
7185 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
7187 if (!AM.Scale || AM.Scale == 1 ||
7188 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
7193 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7194 const AddrMode &AM, Type *Ty,
7195 unsigned AS) const {
7196 // Scaling factors are not free at all.
7197 // Operands | Rt Latency
7198 // -------------------------------------------
7200 // -------------------------------------------
7201 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
7202 // Rt, [Xn, Wm, <extend> #imm] |
7203 if (isLegalAddressingMode(DL, AM, Ty, AS))
7204 // Scale represents reg2 * scale, thus account for 1 if
7205 // it is not equal to 0 or 1.
7206 return AM.Scale != 0 && AM.Scale != 1;
7210 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7211 VT = VT.getScalarType();
7216 switch (VT.getSimpleVT().SimpleTy) {
7228 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7229 // LR is a callee-save register, but we must treat it as clobbered by any call
7230 // site. Hence we include LR in the scratch registers, which are in turn added
7231 // as implicit-defs for stackmaps and patchpoints.
7232 static const MCPhysReg ScratchRegs[] = {
7233 AArch64::X16, AArch64::X17, AArch64::LR, 0
7239 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7240 EVT VT = N->getValueType(0);
7241 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
7242 // it with shift to let it be lowered to UBFX.
7243 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7244 isa<ConstantSDNode>(N->getOperand(1))) {
7245 uint64_t TruncMask = N->getConstantOperandVal(1);
7246 if (isMask_64(TruncMask) &&
7247 N->getOperand(0).getOpcode() == ISD::SRL &&
7248 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7254 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7256 assert(Ty->isIntegerTy());
7258 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7262 int64_t Val = Imm.getSExtValue();
7263 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7266 if ((int64_t)Val < 0)
7269 Val &= (1LL << 32) - 1;
7271 unsigned LZ = countLeadingZeros((uint64_t)Val);
7272 unsigned Shift = (63 - LZ) / 16;
7273 // MOVZ is free so return true for one or fewer MOVK.
7277 // Generate SUBS and CSEL for integer abs.
7278 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7279 EVT VT = N->getValueType(0);
7281 SDValue N0 = N->getOperand(0);
7282 SDValue N1 = N->getOperand(1);
7285 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7286 // and change it to SUB and CSEL.
7287 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7288 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7289 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7290 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7291 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7292 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7294 // Generate SUBS & CSEL.
7296 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7297 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7298 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7299 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7300 SDValue(Cmp.getNode(), 1));
7305 // performXorCombine - Attempts to handle integer ABS.
7306 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7307 TargetLowering::DAGCombinerInfo &DCI,
7308 const AArch64Subtarget *Subtarget) {
7309 if (DCI.isBeforeLegalizeOps())
7312 return performIntegerAbsCombine(N, DAG);
7316 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7318 std::vector<SDNode *> *Created) const {
7319 // fold (sdiv X, pow2)
7320 EVT VT = N->getValueType(0);
7321 if ((VT != MVT::i32 && VT != MVT::i64) ||
7322 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7326 SDValue N0 = N->getOperand(0);
7327 unsigned Lg2 = Divisor.countTrailingZeros();
7328 SDValue Zero = DAG.getConstant(0, DL, VT);
7329 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7331 // Add (N0 < 0) ? Pow2 - 1 : 0;
7333 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7334 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7335 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7338 Created->push_back(Cmp.getNode());
7339 Created->push_back(Add.getNode());
7340 Created->push_back(CSel.getNode());
7345 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7347 // If we're dividing by a positive value, we're done. Otherwise, we must
7348 // negate the result.
7349 if (Divisor.isNonNegative())
7353 Created->push_back(SRA.getNode());
7354 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7357 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7358 TargetLowering::DAGCombinerInfo &DCI,
7359 const AArch64Subtarget *Subtarget) {
7360 if (DCI.isBeforeLegalizeOps())
7363 // Multiplication of a power of two plus/minus one can be done more
7364 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7365 // future CPUs have a cheaper MADD instruction, this may need to be
7366 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7367 // 64-bit is 5 cycles, so this is always a win.
7368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7369 APInt Value = C->getAPIntValue();
7370 EVT VT = N->getValueType(0);
7372 if (Value.isNonNegative()) {
7373 // (mul x, 2^N + 1) => (add (shl x, N), x)
7374 APInt VM1 = Value - 1;
7375 if (VM1.isPowerOf2()) {
7376 SDValue ShiftedVal =
7377 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7378 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7379 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7382 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7383 APInt VP1 = Value + 1;
7384 if (VP1.isPowerOf2()) {
7385 SDValue ShiftedVal =
7386 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7387 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7388 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7392 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7393 APInt VNP1 = -Value + 1;
7394 if (VNP1.isPowerOf2()) {
7395 SDValue ShiftedVal =
7396 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7397 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7398 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7401 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7402 APInt VNM1 = -Value - 1;
7403 if (VNM1.isPowerOf2()) {
7404 SDValue ShiftedVal =
7405 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7406 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7408 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7409 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7416 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7417 SelectionDAG &DAG) {
7418 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7419 // optimize away operation when it's from a constant.
7421 // The general transformation is:
7422 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7423 // AND(VECTOR_CMP(x,y), constant2)
7424 // constant2 = UNARYOP(constant)
7426 // Early exit if this isn't a vector operation, the operand of the
7427 // unary operation isn't a bitwise AND, or if the sizes of the operations
7429 EVT VT = N->getValueType(0);
7430 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7431 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7432 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7435 // Now check that the other operand of the AND is a constant. We could
7436 // make the transformation for non-constant splats as well, but it's unclear
7437 // that would be a benefit as it would not eliminate any operations, just
7438 // perform one more step in scalar code before moving to the vector unit.
7439 if (BuildVectorSDNode *BV =
7440 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7441 // Bail out if the vector isn't a constant.
7442 if (!BV->isConstant())
7445 // Everything checks out. Build up the new and improved node.
7447 EVT IntVT = BV->getValueType(0);
7448 // Create a new constant of the appropriate type for the transformed
7450 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7451 // The AND node needs bitcasts to/from an integer vector type around it.
7452 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7453 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7454 N->getOperand(0)->getOperand(0), MaskConst);
7455 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7462 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7463 const AArch64Subtarget *Subtarget) {
7464 // First try to optimize away the conversion when it's conditionally from
7465 // a constant. Vectors only.
7466 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
7469 EVT VT = N->getValueType(0);
7470 if (VT != MVT::f32 && VT != MVT::f64)
7473 // Only optimize when the source and destination types have the same width.
7474 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7477 // If the result of an integer load is only used by an integer-to-float
7478 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7479 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7480 SDValue N0 = N->getOperand(0);
7481 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7482 // Do not change the width of a volatile load.
7483 !cast<LoadSDNode>(N0)->isVolatile()) {
7484 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7485 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7486 LN0->getPointerInfo(), LN0->isVolatile(),
7487 LN0->isNonTemporal(), LN0->isInvariant(),
7488 LN0->getAlignment());
7490 // Make sure successors of the original load stay after it by updating them
7491 // to use the new Chain.
7492 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7495 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7496 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7502 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7503 /// searches for and classifies those shifts.
7504 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7506 if (N.getOpcode() == ISD::SHL)
7508 else if (N.getOpcode() == ISD::SRL)
7513 if (!isa<ConstantSDNode>(N.getOperand(1)))
7516 ShiftAmount = N->getConstantOperandVal(1);
7517 Src = N->getOperand(0);
7521 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7522 /// registers viewed as a high/low pair. This function looks for the pattern:
7523 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7524 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7526 static SDValue tryCombineToEXTR(SDNode *N,
7527 TargetLowering::DAGCombinerInfo &DCI) {
7528 SelectionDAG &DAG = DCI.DAG;
7530 EVT VT = N->getValueType(0);
7532 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7534 if (VT != MVT::i32 && VT != MVT::i64)
7538 uint32_t ShiftLHS = 0;
7540 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7544 uint32_t ShiftRHS = 0;
7546 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7549 // If they're both trying to come from the high part of the register, they're
7550 // not really an EXTR.
7551 if (LHSFromHi == RHSFromHi)
7554 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7558 std::swap(LHS, RHS);
7559 std::swap(ShiftLHS, ShiftRHS);
7562 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7563 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7566 static SDValue tryCombineToBSL(SDNode *N,
7567 TargetLowering::DAGCombinerInfo &DCI) {
7568 EVT VT = N->getValueType(0);
7569 SelectionDAG &DAG = DCI.DAG;
7575 SDValue N0 = N->getOperand(0);
7576 if (N0.getOpcode() != ISD::AND)
7579 SDValue N1 = N->getOperand(1);
7580 if (N1.getOpcode() != ISD::AND)
7583 // We only have to look for constant vectors here since the general, variable
7584 // case can be handled in TableGen.
7585 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7586 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7587 for (int i = 1; i >= 0; --i)
7588 for (int j = 1; j >= 0; --j) {
7589 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7590 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7594 bool FoundMatch = true;
7595 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7596 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7597 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7599 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7606 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7607 N0->getOperand(1 - i), N1->getOperand(1 - j));
7613 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7614 const AArch64Subtarget *Subtarget) {
7615 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7616 if (!EnableAArch64ExtrGeneration)
7618 SelectionDAG &DAG = DCI.DAG;
7619 EVT VT = N->getValueType(0);
7621 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7624 SDValue Res = tryCombineToEXTR(N, DCI);
7628 Res = tryCombineToBSL(N, DCI);
7635 static SDValue performBitcastCombine(SDNode *N,
7636 TargetLowering::DAGCombinerInfo &DCI,
7637 SelectionDAG &DAG) {
7638 // Wait 'til after everything is legalized to try this. That way we have
7639 // legal vector types and such.
7640 if (DCI.isBeforeLegalizeOps())
7643 // Remove extraneous bitcasts around an extract_subvector.
7645 // (v4i16 (bitconvert
7646 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7648 // (extract_subvector ((v8i16 ...), (i64 4)))
7650 // Only interested in 64-bit vectors as the ultimate result.
7651 EVT VT = N->getValueType(0);
7654 if (VT.getSimpleVT().getSizeInBits() != 64)
7656 // Is the operand an extract_subvector starting at the beginning or halfway
7657 // point of the vector? A low half may also come through as an
7658 // EXTRACT_SUBREG, so look for that, too.
7659 SDValue Op0 = N->getOperand(0);
7660 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7661 !(Op0->isMachineOpcode() &&
7662 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7664 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7665 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7666 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7668 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7669 if (idx != AArch64::dsub)
7671 // The dsub reference is equivalent to a lane zero subvector reference.
7674 // Look through the bitcast of the input to the extract.
7675 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7677 SDValue Source = Op0->getOperand(0)->getOperand(0);
7678 // If the source type has twice the number of elements as our destination
7679 // type, we know this is an extract of the high or low half of the vector.
7680 EVT SVT = Source->getValueType(0);
7681 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7684 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7686 // Create the simplified form to just extract the low or high half of the
7687 // vector directly rather than bothering with the bitcasts.
7689 unsigned NumElements = VT.getVectorNumElements();
7691 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7692 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7694 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7695 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7701 static SDValue performConcatVectorsCombine(SDNode *N,
7702 TargetLowering::DAGCombinerInfo &DCI,
7703 SelectionDAG &DAG) {
7705 EVT VT = N->getValueType(0);
7706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7708 // Optimize concat_vectors of truncated vectors, where the intermediate
7709 // type is illegal, to avoid said illegality, e.g.,
7710 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7711 // (v2i16 (truncate (v2i64)))))
7713 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7714 // (v4i32 (bitcast (v2i64))),
7716 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7717 // on both input and result type, so we might generate worse code.
7718 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7719 if (N->getNumOperands() == 2 &&
7720 N0->getOpcode() == ISD::TRUNCATE &&
7721 N1->getOpcode() == ISD::TRUNCATE) {
7722 SDValue N00 = N0->getOperand(0);
7723 SDValue N10 = N1->getOperand(0);
7724 EVT N00VT = N00.getValueType();
7726 if (N00VT == N10.getValueType() &&
7727 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7728 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7729 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7730 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7731 for (size_t i = 0; i < Mask.size(); ++i)
7733 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7734 DAG.getVectorShuffle(
7736 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7737 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7741 // Wait 'til after everything is legalized to try this. That way we have
7742 // legal vector types and such.
7743 if (DCI.isBeforeLegalizeOps())
7746 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7747 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7748 // canonicalise to that.
7749 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7750 assert(VT.getVectorElementType().getSizeInBits() == 64);
7751 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7752 DAG.getConstant(0, dl, MVT::i64));
7755 // Canonicalise concat_vectors so that the right-hand vector has as few
7756 // bit-casts as possible before its real operation. The primary matching
7757 // destination for these operations will be the narrowing "2" instructions,
7758 // which depend on the operation being performed on this right-hand vector.
7760 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7762 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7764 if (N1->getOpcode() != ISD::BITCAST)
7766 SDValue RHS = N1->getOperand(0);
7767 MVT RHSTy = RHS.getValueType().getSimpleVT();
7768 // If the RHS is not a vector, this is not the pattern we're looking for.
7769 if (!RHSTy.isVector())
7772 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7774 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7775 RHSTy.getVectorNumElements() * 2);
7776 return DAG.getNode(ISD::BITCAST, dl, VT,
7777 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7778 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7782 static SDValue tryCombineFixedPointConvert(SDNode *N,
7783 TargetLowering::DAGCombinerInfo &DCI,
7784 SelectionDAG &DAG) {
7785 // Wait 'til after everything is legalized to try this. That way we have
7786 // legal vector types and such.
7787 if (DCI.isBeforeLegalizeOps())
7789 // Transform a scalar conversion of a value from a lane extract into a
7790 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7791 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7792 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7794 // The second form interacts better with instruction selection and the
7795 // register allocator to avoid cross-class register copies that aren't
7796 // coalescable due to a lane reference.
7798 // Check the operand and see if it originates from a lane extract.
7799 SDValue Op1 = N->getOperand(1);
7800 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7801 // Yep, no additional predication needed. Perform the transform.
7802 SDValue IID = N->getOperand(0);
7803 SDValue Shift = N->getOperand(2);
7804 SDValue Vec = Op1.getOperand(0);
7805 SDValue Lane = Op1.getOperand(1);
7806 EVT ResTy = N->getValueType(0);
7810 // The vector width should be 128 bits by the time we get here, even
7811 // if it started as 64 bits (the extract_vector handling will have
7813 assert(Vec.getValueType().getSizeInBits() == 128 &&
7814 "unexpected vector size on extract_vector_elt!");
7815 if (Vec.getValueType() == MVT::v4i32)
7816 VecResTy = MVT::v4f32;
7817 else if (Vec.getValueType() == MVT::v2i64)
7818 VecResTy = MVT::v2f64;
7820 llvm_unreachable("unexpected vector type!");
7823 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7829 // AArch64 high-vector "long" operations are formed by performing the non-high
7830 // version on an extract_subvector of each operand which gets the high half:
7832 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7834 // However, there are cases which don't have an extract_high explicitly, but
7835 // have another operation that can be made compatible with one for free. For
7838 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7840 // This routine does the actual conversion of such DUPs, once outer routines
7841 // have determined that everything else is in order.
7842 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7844 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7845 switch (N.getOpcode()) {
7846 case AArch64ISD::DUP:
7847 case AArch64ISD::DUPLANE8:
7848 case AArch64ISD::DUPLANE16:
7849 case AArch64ISD::DUPLANE32:
7850 case AArch64ISD::DUPLANE64:
7851 case AArch64ISD::MOVI:
7852 case AArch64ISD::MOVIshift:
7853 case AArch64ISD::MOVIedit:
7854 case AArch64ISD::MOVImsl:
7855 case AArch64ISD::MVNIshift:
7856 case AArch64ISD::MVNImsl:
7859 // FMOV could be supported, but isn't very useful, as it would only occur
7860 // if you passed a bitcast' floating point immediate to an eligible long
7861 // integer op (addl, smull, ...).
7865 MVT NarrowTy = N.getSimpleValueType();
7866 if (!NarrowTy.is64BitVector())
7869 MVT ElementTy = NarrowTy.getVectorElementType();
7870 unsigned NumElems = NarrowTy.getVectorNumElements();
7871 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7874 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7875 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7876 DAG.getConstant(NumElems, dl, MVT::i64));
7879 static bool isEssentiallyExtractSubvector(SDValue N) {
7880 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7883 return N.getOpcode() == ISD::BITCAST &&
7884 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7887 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7888 struct GenericSetCCInfo {
7889 const SDValue *Opnd0;
7890 const SDValue *Opnd1;
7894 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7895 struct AArch64SetCCInfo {
7897 AArch64CC::CondCode CC;
7900 /// \brief Helper structure to keep track of SetCC information.
7902 GenericSetCCInfo Generic;
7903 AArch64SetCCInfo AArch64;
7906 /// \brief Helper structure to be able to read SetCC information. If set to
7907 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7908 /// GenericSetCCInfo.
7909 struct SetCCInfoAndKind {
7914 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7916 /// AArch64 lowered one.
7917 /// \p SetCCInfo is filled accordingly.
7918 /// \post SetCCInfo is meanginfull only when this function returns true.
7919 /// \return True when Op is a kind of SET_CC operation.
7920 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7921 // If this is a setcc, this is straight forward.
7922 if (Op.getOpcode() == ISD::SETCC) {
7923 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7924 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7925 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7926 SetCCInfo.IsAArch64 = false;
7929 // Otherwise, check if this is a matching csel instruction.
7933 if (Op.getOpcode() != AArch64ISD::CSEL)
7935 // Set the information about the operands.
7936 // TODO: we want the operands of the Cmp not the csel
7937 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7938 SetCCInfo.IsAArch64 = true;
7939 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7940 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7942 // Check that the operands matches the constraints:
7943 // (1) Both operands must be constants.
7944 // (2) One must be 1 and the other must be 0.
7945 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7946 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7949 if (!TValue || !FValue)
7953 if (!TValue->isOne()) {
7954 // Update the comparison when we are interested in !cc.
7955 std::swap(TValue, FValue);
7956 SetCCInfo.Info.AArch64.CC =
7957 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7959 return TValue->isOne() && FValue->isNullValue();
7962 // Returns true if Op is setcc or zext of setcc.
7963 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7964 if (isSetCC(Op, Info))
7966 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7967 isSetCC(Op->getOperand(0), Info));
7970 // The folding we want to perform is:
7971 // (add x, [zext] (setcc cc ...) )
7973 // (csel x, (add x, 1), !cc ...)
7975 // The latter will get matched to a CSINC instruction.
7976 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7977 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7978 SDValue LHS = Op->getOperand(0);
7979 SDValue RHS = Op->getOperand(1);
7980 SetCCInfoAndKind InfoAndKind;
7982 // If neither operand is a SET_CC, give up.
7983 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7984 std::swap(LHS, RHS);
7985 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7989 // FIXME: This could be generatized to work for FP comparisons.
7990 EVT CmpVT = InfoAndKind.IsAArch64
7991 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7992 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7993 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7999 if (InfoAndKind.IsAArch64) {
8000 CCVal = DAG.getConstant(
8001 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8003 Cmp = *InfoAndKind.Info.AArch64.Cmp;
8005 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
8006 *InfoAndKind.Info.Generic.Opnd1,
8007 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
8010 EVT VT = Op->getValueType(0);
8011 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8012 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8015 // The basic add/sub long vector instructions have variants with "2" on the end
8016 // which act on the high-half of their inputs. They are normally matched by
8019 // (add (zeroext (extract_high LHS)),
8020 // (zeroext (extract_high RHS)))
8021 // -> uaddl2 vD, vN, vM
8023 // However, if one of the extracts is something like a duplicate, this
8024 // instruction can still be used profitably. This function puts the DAG into a
8025 // more appropriate form for those patterns to trigger.
8026 static SDValue performAddSubLongCombine(SDNode *N,
8027 TargetLowering::DAGCombinerInfo &DCI,
8028 SelectionDAG &DAG) {
8029 if (DCI.isBeforeLegalizeOps())
8032 MVT VT = N->getSimpleValueType(0);
8033 if (!VT.is128BitVector()) {
8034 if (N->getOpcode() == ISD::ADD)
8035 return performSetccAddFolding(N, DAG);
8039 // Make sure both branches are extended in the same way.
8040 SDValue LHS = N->getOperand(0);
8041 SDValue RHS = N->getOperand(1);
8042 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8043 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8044 LHS.getOpcode() != RHS.getOpcode())
8047 unsigned ExtType = LHS.getOpcode();
8049 // It's not worth doing if at least one of the inputs isn't already an
8050 // extract, but we don't know which it'll be so we have to try both.
8051 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
8052 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
8056 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8057 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
8058 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
8062 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8065 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8068 // Massage DAGs which we can use the high-half "long" operations on into
8069 // something isel will recognize better. E.g.
8071 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
8072 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8073 // (extract_high (v2i64 (dup128 scalar)))))
8075 static SDValue tryCombineLongOpWithDup(SDNode *N,
8076 TargetLowering::DAGCombinerInfo &DCI,
8077 SelectionDAG &DAG) {
8078 if (DCI.isBeforeLegalizeOps())
8081 bool IsIntrinsic = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
8082 SDValue LHS = N->getOperand(IsIntrinsic ? 1 : 0);
8083 SDValue RHS = N->getOperand(IsIntrinsic ? 2 : 1);
8084 assert(LHS.getValueType().is64BitVector() &&
8085 RHS.getValueType().is64BitVector() &&
8086 "unexpected shape for long operation");
8088 // Either node could be a DUP, but it's not worth doing both of them (you'd
8089 // just as well use the non-high version) so look for a corresponding extract
8090 // operation on the other "wing".
8091 if (isEssentiallyExtractSubvector(LHS)) {
8092 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
8095 } else if (isEssentiallyExtractSubvector(RHS)) {
8096 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
8101 // N could either be an intrinsic or a sabsdiff/uabsdiff node.
8103 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
8104 N->getOperand(0), LHS, RHS);
8106 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
8110 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
8111 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
8112 unsigned ElemBits = ElemTy.getSizeInBits();
8114 int64_t ShiftAmount;
8115 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
8116 APInt SplatValue, SplatUndef;
8117 unsigned SplatBitSize;
8119 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
8120 HasAnyUndefs, ElemBits) ||
8121 SplatBitSize != ElemBits)
8124 ShiftAmount = SplatValue.getSExtValue();
8125 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
8126 ShiftAmount = CVN->getSExtValue();
8134 llvm_unreachable("Unknown shift intrinsic");
8135 case Intrinsic::aarch64_neon_sqshl:
8136 Opcode = AArch64ISD::SQSHL_I;
8137 IsRightShift = false;
8139 case Intrinsic::aarch64_neon_uqshl:
8140 Opcode = AArch64ISD::UQSHL_I;
8141 IsRightShift = false;
8143 case Intrinsic::aarch64_neon_srshl:
8144 Opcode = AArch64ISD::SRSHR_I;
8145 IsRightShift = true;
8147 case Intrinsic::aarch64_neon_urshl:
8148 Opcode = AArch64ISD::URSHR_I;
8149 IsRightShift = true;
8151 case Intrinsic::aarch64_neon_sqshlu:
8152 Opcode = AArch64ISD::SQSHLU_I;
8153 IsRightShift = false;
8157 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8159 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8160 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8161 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
8163 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8164 DAG.getConstant(ShiftAmount, dl, MVT::i32));
8170 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
8171 // the intrinsics must be legal and take an i32, this means there's almost
8172 // certainly going to be a zext in the DAG which we can eliminate.
8173 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
8174 SDValue AndN = N->getOperand(2);
8175 if (AndN.getOpcode() != ISD::AND)
8178 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
8179 if (!CMask || CMask->getZExtValue() != Mask)
8182 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
8183 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
8186 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
8187 SelectionDAG &DAG) {
8189 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
8190 DAG.getNode(Opc, dl,
8191 N->getOperand(1).getSimpleValueType(),
8193 DAG.getConstant(0, dl, MVT::i64));
8196 static SDValue performIntrinsicCombine(SDNode *N,
8197 TargetLowering::DAGCombinerInfo &DCI,
8198 const AArch64Subtarget *Subtarget) {
8199 SelectionDAG &DAG = DCI.DAG;
8200 unsigned IID = getIntrinsicID(N);
8204 case Intrinsic::aarch64_neon_vcvtfxs2fp:
8205 case Intrinsic::aarch64_neon_vcvtfxu2fp:
8206 return tryCombineFixedPointConvert(N, DCI, DAG);
8207 case Intrinsic::aarch64_neon_saddv:
8208 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
8209 case Intrinsic::aarch64_neon_uaddv:
8210 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
8211 case Intrinsic::aarch64_neon_sminv:
8212 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
8213 case Intrinsic::aarch64_neon_uminv:
8214 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
8215 case Intrinsic::aarch64_neon_smaxv:
8216 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
8217 case Intrinsic::aarch64_neon_umaxv:
8218 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
8219 case Intrinsic::aarch64_neon_fmax:
8220 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
8221 N->getOperand(1), N->getOperand(2));
8222 case Intrinsic::aarch64_neon_fmin:
8223 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
8224 N->getOperand(1), N->getOperand(2));
8225 case Intrinsic::aarch64_neon_sabd:
8226 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
8227 N->getOperand(1), N->getOperand(2));
8228 case Intrinsic::aarch64_neon_uabd:
8229 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
8230 N->getOperand(1), N->getOperand(2));
8231 case Intrinsic::aarch64_neon_smull:
8232 case Intrinsic::aarch64_neon_umull:
8233 case Intrinsic::aarch64_neon_pmull:
8234 case Intrinsic::aarch64_neon_sqdmull:
8235 return tryCombineLongOpWithDup(N, DCI, DAG);
8236 case Intrinsic::aarch64_neon_sqshl:
8237 case Intrinsic::aarch64_neon_uqshl:
8238 case Intrinsic::aarch64_neon_sqshlu:
8239 case Intrinsic::aarch64_neon_srshl:
8240 case Intrinsic::aarch64_neon_urshl:
8241 return tryCombineShiftImm(IID, N, DAG);
8242 case Intrinsic::aarch64_crc32b:
8243 case Intrinsic::aarch64_crc32cb:
8244 return tryCombineCRC32(0xff, N, DAG);
8245 case Intrinsic::aarch64_crc32h:
8246 case Intrinsic::aarch64_crc32ch:
8247 return tryCombineCRC32(0xffff, N, DAG);
8252 static SDValue performExtendCombine(SDNode *N,
8253 TargetLowering::DAGCombinerInfo &DCI,
8254 SelectionDAG &DAG) {
8255 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8256 // we can convert that DUP into another extract_high (of a bigger DUP), which
8257 // helps the backend to decide that an sabdl2 would be useful, saving a real
8258 // extract_high operation.
8259 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8260 (N->getOperand(0).getOpcode() == ISD::SABSDIFF ||
8261 N->getOperand(0).getOpcode() == ISD::UABSDIFF)) {
8262 SDNode *ABDNode = N->getOperand(0).getNode();
8263 SDValue NewABD = tryCombineLongOpWithDup(ABDNode, DCI, DAG);
8264 if (!NewABD.getNode())
8267 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8271 // This is effectively a custom type legalization for AArch64.
8273 // Type legalization will split an extend of a small, legal, type to a larger
8274 // illegal type by first splitting the destination type, often creating
8275 // illegal source types, which then get legalized in isel-confusing ways,
8276 // leading to really terrible codegen. E.g.,
8277 // %result = v8i32 sext v8i8 %value
8279 // %losrc = extract_subreg %value, ...
8280 // %hisrc = extract_subreg %value, ...
8281 // %lo = v4i32 sext v4i8 %losrc
8282 // %hi = v4i32 sext v4i8 %hisrc
8283 // Things go rapidly downhill from there.
8285 // For AArch64, the [sz]ext vector instructions can only go up one element
8286 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8287 // take two instructions.
8289 // This implies that the most efficient way to do the extend from v8i8
8290 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8291 // the normal splitting to happen for the v8i16->v8i32.
8293 // This is pre-legalization to catch some cases where the default
8294 // type legalization will create ill-tempered code.
8295 if (!DCI.isBeforeLegalizeOps())
8298 // We're only interested in cleaning things up for non-legal vector types
8299 // here. If both the source and destination are legal, things will just
8300 // work naturally without any fiddling.
8301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8302 EVT ResVT = N->getValueType(0);
8303 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8305 // If the vector type isn't a simple VT, it's beyond the scope of what
8306 // we're worried about here. Let legalization do its thing and hope for
8308 SDValue Src = N->getOperand(0);
8309 EVT SrcVT = Src->getValueType(0);
8310 if (!ResVT.isSimple() || !SrcVT.isSimple())
8313 // If the source VT is a 64-bit vector, we can play games and get the
8314 // better results we want.
8315 if (SrcVT.getSizeInBits() != 64)
8318 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8319 unsigned ElementCount = SrcVT.getVectorNumElements();
8320 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8322 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8324 // Now split the rest of the operation into two halves, each with a 64
8328 unsigned NumElements = ResVT.getVectorNumElements();
8329 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8330 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8331 ResVT.getVectorElementType(), NumElements / 2);
8333 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8334 LoVT.getVectorNumElements());
8335 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8336 DAG.getConstant(0, DL, MVT::i64));
8337 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8338 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8339 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8340 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8342 // Now combine the parts back together so we still have a single result
8343 // like the combiner expects.
8344 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8347 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8348 /// value. The load store optimizer pass will merge them to store pair stores.
8349 /// This has better performance than a splat of the scalar followed by a split
8350 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8351 /// followed by an ext.b and two stores.
8352 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8353 SDValue StVal = St->getValue();
8354 EVT VT = StVal.getValueType();
8356 // Don't replace floating point stores, they possibly won't be transformed to
8357 // stp because of the store pair suppress pass.
8358 if (VT.isFloatingPoint())
8361 // Check for insert vector elements.
8362 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8365 // We can express a splat as store pair(s) for 2 or 4 elements.
8366 unsigned NumVecElts = VT.getVectorNumElements();
8367 if (NumVecElts != 4 && NumVecElts != 2)
8369 SDValue SplatVal = StVal.getOperand(1);
8370 unsigned RemainInsertElts = NumVecElts - 1;
8372 // Check that this is a splat.
8373 while (--RemainInsertElts) {
8374 SDValue NextInsertElt = StVal.getOperand(0);
8375 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8377 if (NextInsertElt.getOperand(1) != SplatVal)
8379 StVal = NextInsertElt;
8381 unsigned OrigAlignment = St->getAlignment();
8382 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8383 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8385 // Create scalar stores. This is at least as good as the code sequence for a
8386 // split unaligned store wich is a dup.s, ext.b, and two stores.
8387 // Most of the time the three stores should be replaced by store pair
8388 // instructions (stp).
8390 SDValue BasePtr = St->getBasePtr();
8392 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8393 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8395 unsigned Offset = EltOffset;
8396 while (--NumVecElts) {
8397 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8398 DAG.getConstant(Offset, DL, MVT::i64));
8399 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8400 St->getPointerInfo(), St->isVolatile(),
8401 St->isNonTemporal(), Alignment);
8402 Offset += EltOffset;
8407 static SDValue performSTORECombine(SDNode *N,
8408 TargetLowering::DAGCombinerInfo &DCI,
8410 const AArch64Subtarget *Subtarget) {
8411 if (!DCI.isBeforeLegalize())
8414 StoreSDNode *S = cast<StoreSDNode>(N);
8415 if (S->isVolatile())
8418 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8419 // page boundaries. We want to split such stores.
8420 if (!Subtarget->isCyclone())
8423 // Don't split at Oz.
8424 MachineFunction &MF = DAG.getMachineFunction();
8425 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8429 SDValue StVal = S->getValue();
8430 EVT VT = StVal.getValueType();
8432 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8433 // those up regresses performance on micro-benchmarks and olden/bh.
8434 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8437 // Split unaligned 16B stores. They are terrible for performance.
8438 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8439 // extensions can use this to mark that it does not want splitting to happen
8440 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8441 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8442 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8443 S->getAlignment() <= 2)
8446 // If we get a splat of a scalar convert this vector store to a store of
8447 // scalars. They will be merged into store pairs thereby removing two
8449 if (SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S))
8450 return ReplacedSplat;
8453 unsigned NumElts = VT.getVectorNumElements() / 2;
8454 // Split VT into two.
8456 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8457 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8458 DAG.getConstant(0, DL, MVT::i64));
8459 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8460 DAG.getConstant(NumElts, DL, MVT::i64));
8461 SDValue BasePtr = S->getBasePtr();
8463 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8464 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8465 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8466 DAG.getConstant(8, DL, MVT::i64));
8467 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8468 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8472 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8473 /// post-increment LD1R.
8474 static SDValue performPostLD1Combine(SDNode *N,
8475 TargetLowering::DAGCombinerInfo &DCI,
8477 if (DCI.isBeforeLegalizeOps())
8480 SelectionDAG &DAG = DCI.DAG;
8481 EVT VT = N->getValueType(0);
8483 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8484 SDNode *LD = N->getOperand(LoadIdx).getNode();
8485 // If it is not LOAD, can not do such combine.
8486 if (LD->getOpcode() != ISD::LOAD)
8489 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8490 EVT MemVT = LoadSDN->getMemoryVT();
8491 // Check if memory operand is the same type as the vector element.
8492 if (MemVT != VT.getVectorElementType())
8495 // Check if there are other uses. If so, do not combine as it will introduce
8497 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8499 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8505 SDValue Addr = LD->getOperand(1);
8506 SDValue Vector = N->getOperand(0);
8507 // Search for a use of the address operand that is an increment.
8508 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8509 Addr.getNode()->use_end(); UI != UE; ++UI) {
8511 if (User->getOpcode() != ISD::ADD
8512 || UI.getUse().getResNo() != Addr.getResNo())
8515 // Check that the add is independent of the load. Otherwise, folding it
8516 // would create a cycle.
8517 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8519 // Also check that add is not used in the vector operand. This would also
8521 if (User->isPredecessorOf(Vector.getNode()))
8524 // If the increment is a constant, it must match the memory ref size.
8525 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8526 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8527 uint32_t IncVal = CInc->getZExtValue();
8528 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8529 if (IncVal != NumBytes)
8531 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8534 // Finally, check that the vector doesn't depend on the load.
8535 // Again, this would create a cycle.
8536 // The load depending on the vector is fine, as that's the case for the
8537 // LD1*post we'll eventually generate anyway.
8538 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8541 SmallVector<SDValue, 8> Ops;
8542 Ops.push_back(LD->getOperand(0)); // Chain
8544 Ops.push_back(Vector); // The vector to be inserted
8545 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8547 Ops.push_back(Addr);
8550 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8551 SDVTList SDTys = DAG.getVTList(Tys);
8552 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8553 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8555 LoadSDN->getMemOperand());
8558 SmallVector<SDValue, 2> NewResults;
8559 NewResults.push_back(SDValue(LD, 0)); // The result of load
8560 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8561 DCI.CombineTo(LD, NewResults);
8562 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8563 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8570 /// Target-specific DAG combine function for NEON load/store intrinsics
8571 /// to merge base address updates.
8572 static SDValue performNEONPostLDSTCombine(SDNode *N,
8573 TargetLowering::DAGCombinerInfo &DCI,
8574 SelectionDAG &DAG) {
8575 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8578 unsigned AddrOpIdx = N->getNumOperands() - 1;
8579 SDValue Addr = N->getOperand(AddrOpIdx);
8581 // Search for a use of the address operand that is an increment.
8582 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8583 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8585 if (User->getOpcode() != ISD::ADD ||
8586 UI.getUse().getResNo() != Addr.getResNo())
8589 // Check that the add is independent of the load/store. Otherwise, folding
8590 // it would create a cycle.
8591 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8594 // Find the new opcode for the updating load/store.
8595 bool IsStore = false;
8596 bool IsLaneOp = false;
8597 bool IsDupOp = false;
8598 unsigned NewOpc = 0;
8599 unsigned NumVecs = 0;
8600 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8602 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8603 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8605 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8607 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8609 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8610 NumVecs = 2; IsStore = true; break;
8611 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8612 NumVecs = 3; IsStore = true; break;
8613 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8614 NumVecs = 4; IsStore = true; break;
8615 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8617 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8619 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8621 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8622 NumVecs = 2; IsStore = true; break;
8623 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8624 NumVecs = 3; IsStore = true; break;
8625 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8626 NumVecs = 4; IsStore = true; break;
8627 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8628 NumVecs = 2; IsDupOp = true; break;
8629 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8630 NumVecs = 3; IsDupOp = true; break;
8631 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8632 NumVecs = 4; IsDupOp = true; break;
8633 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8634 NumVecs = 2; IsLaneOp = true; break;
8635 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8636 NumVecs = 3; IsLaneOp = true; break;
8637 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8638 NumVecs = 4; IsLaneOp = true; break;
8639 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8640 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8641 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8642 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8643 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8644 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8649 VecTy = N->getOperand(2).getValueType();
8651 VecTy = N->getValueType(0);
8653 // If the increment is a constant, it must match the memory ref size.
8654 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8655 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8656 uint32_t IncVal = CInc->getZExtValue();
8657 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8658 if (IsLaneOp || IsDupOp)
8659 NumBytes /= VecTy.getVectorNumElements();
8660 if (IncVal != NumBytes)
8662 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8664 SmallVector<SDValue, 8> Ops;
8665 Ops.push_back(N->getOperand(0)); // Incoming chain
8666 // Load lane and store have vector list as input.
8667 if (IsLaneOp || IsStore)
8668 for (unsigned i = 2; i < AddrOpIdx; ++i)
8669 Ops.push_back(N->getOperand(i));
8670 Ops.push_back(Addr); // Base register
8675 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8677 for (n = 0; n < NumResultVecs; ++n)
8679 Tys[n++] = MVT::i64; // Type of write back register
8680 Tys[n] = MVT::Other; // Type of the chain
8681 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8683 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8684 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8685 MemInt->getMemoryVT(),
8686 MemInt->getMemOperand());
8689 std::vector<SDValue> NewResults;
8690 for (unsigned i = 0; i < NumResultVecs; ++i) {
8691 NewResults.push_back(SDValue(UpdN.getNode(), i));
8693 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8694 DCI.CombineTo(N, NewResults);
8695 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8702 // Checks to see if the value is the prescribed width and returns information
8703 // about its extension mode.
8705 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8706 ExtType = ISD::NON_EXTLOAD;
8707 switch(V.getNode()->getOpcode()) {
8711 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8712 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8713 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8714 ExtType = LoadNode->getExtensionType();
8719 case ISD::AssertSext: {
8720 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8721 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8722 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8723 ExtType = ISD::SEXTLOAD;
8728 case ISD::AssertZext: {
8729 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8730 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8731 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8732 ExtType = ISD::ZEXTLOAD;
8738 case ISD::TargetConstant: {
8739 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8749 // This function does a whole lot of voodoo to determine if the tests are
8750 // equivalent without and with a mask. Essentially what happens is that given a
8753 // +-------------+ +-------------+ +-------------+ +-------------+
8754 // | Input | | AddConstant | | CompConstant| | CC |
8755 // +-------------+ +-------------+ +-------------+ +-------------+
8757 // V V | +----------+
8758 // +-------------+ +----+ | |
8759 // | ADD | |0xff| | |
8760 // +-------------+ +----+ | |
8763 // +-------------+ | |
8765 // +-------------+ | |
8774 // The AND node may be safely removed for some combinations of inputs. In
8775 // particular we need to take into account the extension type of the Input,
8776 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8777 // width of the input (this can work for any width inputs, the above graph is
8778 // specific to 8 bits.
8780 // The specific equations were worked out by generating output tables for each
8781 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8782 // problem was simplified by working with 4 bit inputs, which means we only
8783 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8784 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8785 // patterns present in both extensions (0,7). For every distinct set of
8786 // AddConstant and CompConstants bit patterns we can consider the masked and
8787 // unmasked versions to be equivalent if the result of this function is true for
8788 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8791 // and w10, w8, #0x0f
8793 // cset w9, AArch64CC
8795 // cset w11, AArch64CC
8800 // Since the above function shows when the outputs are equivalent it defines
8801 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8802 // would be expensive to run during compiles. The equations below were written
8803 // in a test harness that confirmed they gave equivalent outputs to the above
8804 // for all inputs function, so they can be used determine if the removal is
8807 // isEquivalentMaskless() is the code for testing if the AND can be removed
8808 // factored out of the DAG recognition as the DAG can take several forms.
8811 bool isEquivalentMaskless(unsigned CC, unsigned width,
8812 ISD::LoadExtType ExtType, signed AddConstant,
8813 signed CompConstant) {
8814 // By being careful about our equations and only writing the in term
8815 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8816 // make them generally applicable to all bit widths.
8817 signed MaxUInt = (1 << width);
8819 // For the purposes of these comparisons sign extending the type is
8820 // equivalent to zero extending the add and displacing it by half the integer
8821 // width. Provided we are careful and make sure our equations are valid over
8822 // the whole range we can just adjust the input and avoid writing equations
8823 // for sign extended inputs.
8824 if (ExtType == ISD::SEXTLOAD)
8825 AddConstant -= (1 << (width-1));
8829 case AArch64CC::GT: {
8830 if ((AddConstant == 0) ||
8831 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8832 (AddConstant >= 0 && CompConstant < 0) ||
8833 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8837 case AArch64CC::GE: {
8838 if ((AddConstant == 0) ||
8839 (AddConstant >= 0 && CompConstant <= 0) ||
8840 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8844 case AArch64CC::LS: {
8845 if ((AddConstant >= 0 && CompConstant < 0) ||
8846 (AddConstant <= 0 && CompConstant >= -1 &&
8847 CompConstant < AddConstant + MaxUInt))
8851 case AArch64CC::MI: {
8852 if ((AddConstant == 0) ||
8853 (AddConstant > 0 && CompConstant <= 0) ||
8854 (AddConstant < 0 && CompConstant <= AddConstant))
8858 case AArch64CC::HS: {
8859 if ((AddConstant >= 0 && CompConstant <= 0) ||
8860 (AddConstant <= 0 && CompConstant >= 0 &&
8861 CompConstant <= AddConstant + MaxUInt))
8865 case AArch64CC::NE: {
8866 if ((AddConstant > 0 && CompConstant < 0) ||
8867 (AddConstant < 0 && CompConstant >= 0 &&
8868 CompConstant < AddConstant + MaxUInt) ||
8869 (AddConstant >= 0 && CompConstant >= 0 &&
8870 CompConstant >= AddConstant) ||
8871 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8880 case AArch64CC::Invalid:
8888 SDValue performCONDCombine(SDNode *N,
8889 TargetLowering::DAGCombinerInfo &DCI,
8890 SelectionDAG &DAG, unsigned CCIndex,
8891 unsigned CmpIndex) {
8892 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8893 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8894 unsigned CondOpcode = SubsNode->getOpcode();
8896 if (CondOpcode != AArch64ISD::SUBS)
8899 // There is a SUBS feeding this condition. Is it fed by a mask we can
8902 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8903 unsigned MaskBits = 0;
8905 if (AndNode->getOpcode() != ISD::AND)
8908 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8909 uint32_t CNV = CN->getZExtValue();
8912 else if (CNV == 65535)
8919 SDValue AddValue = AndNode->getOperand(0);
8921 if (AddValue.getOpcode() != ISD::ADD)
8924 // The basic dag structure is correct, grab the inputs and validate them.
8926 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8927 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8928 SDValue SubsInputValue = SubsNode->getOperand(1);
8930 // The mask is present and the provenance of all the values is a smaller type,
8931 // lets see if the mask is superfluous.
8933 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8934 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8937 ISD::LoadExtType ExtType;
8939 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8940 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8941 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8944 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8945 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8946 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8949 // The AND is not necessary, remove it.
8951 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8952 SubsNode->getValueType(1));
8953 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8955 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8956 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8958 return SDValue(N, 0);
8961 // Optimize compare with zero and branch.
8962 static SDValue performBRCONDCombine(SDNode *N,
8963 TargetLowering::DAGCombinerInfo &DCI,
8964 SelectionDAG &DAG) {
8965 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8968 SDValue Chain = N->getOperand(0);
8969 SDValue Dest = N->getOperand(1);
8970 SDValue CCVal = N->getOperand(2);
8971 SDValue Cmp = N->getOperand(3);
8973 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8974 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8975 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8978 unsigned CmpOpc = Cmp.getOpcode();
8979 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8982 // Only attempt folding if there is only one use of the flag and no use of the
8984 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8987 SDValue LHS = Cmp.getOperand(0);
8988 SDValue RHS = Cmp.getOperand(1);
8990 assert(LHS.getValueType() == RHS.getValueType() &&
8991 "Expected the value type to be the same for both operands!");
8992 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8995 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8996 std::swap(LHS, RHS);
8998 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
9001 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9002 LHS.getOpcode() == ISD::SRL)
9005 // Fold the compare into the branch instruction.
9007 if (CC == AArch64CC::EQ)
9008 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9010 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9012 // Do not add new nodes to DAG combiner worklist.
9013 DCI.CombineTo(N, BR, false);
9018 // vselect (v1i1 setcc) ->
9019 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
9020 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
9021 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
9023 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
9024 SDValue N0 = N->getOperand(0);
9025 EVT CCVT = N0.getValueType();
9027 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9028 CCVT.getVectorElementType() != MVT::i1)
9031 EVT ResVT = N->getValueType(0);
9032 EVT CmpVT = N0.getOperand(0).getValueType();
9033 // Only combine when the result type is of the same size as the compared
9035 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
9038 SDValue IfTrue = N->getOperand(1);
9039 SDValue IfFalse = N->getOperand(2);
9041 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
9042 N0.getOperand(0), N0.getOperand(1),
9043 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9044 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
9048 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
9049 /// the compare-mask instructions rather than going via NZCV, even if LHS and
9050 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
9051 /// with a vector one followed by a DUP shuffle on the result.
9052 static SDValue performSelectCombine(SDNode *N,
9053 TargetLowering::DAGCombinerInfo &DCI) {
9054 SelectionDAG &DAG = DCI.DAG;
9055 SDValue N0 = N->getOperand(0);
9056 EVT ResVT = N->getValueType(0);
9058 if (N0.getOpcode() != ISD::SETCC)
9061 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
9062 // scalar SetCCResultType. We also don't expect vectors, because we assume
9063 // that selects fed by vector SETCCs are canonicalized to VSELECT.
9064 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
9065 "Scalar-SETCC feeding SELECT has unexpected result type!");
9067 // If NumMaskElts == 0, the comparison is larger than select result. The
9068 // largest real NEON comparison is 64-bits per lane, which means the result is
9069 // at most 32-bits and an illegal vector. Just bail out for now.
9070 EVT SrcVT = N0.getOperand(0).getValueType();
9072 // Don't try to do this optimization when the setcc itself has i1 operands.
9073 // There are no legal vectors of i1, so this would be pointless.
9074 if (SrcVT == MVT::i1)
9077 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
9078 if (!ResVT.isVector() || NumMaskElts == 0)
9081 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
9082 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
9084 // Also bail out if the vector CCVT isn't the same size as ResVT.
9085 // This can happen if the SETCC operand size doesn't divide the ResVT size
9086 // (e.g., f64 vs v3f32).
9087 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
9090 // Make sure we didn't create illegal types, if we're not supposed to.
9091 assert(DCI.isBeforeLegalize() ||
9092 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
9094 // First perform a vector comparison, where lane 0 is the one we're interested
9098 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
9100 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
9101 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
9103 // Now duplicate the comparison mask we want across all other lanes.
9104 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
9105 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
9106 Mask = DAG.getNode(ISD::BITCAST, DL,
9107 ResVT.changeVectorElementTypeToInteger(), Mask);
9109 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
9112 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
9113 /// to match FMIN/FMAX patterns.
9114 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
9115 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
9116 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
9117 // vmax/vmin return NaN if either operand is a NaN;
9118 // only do the transformation when it matches that behavior.
9120 SDValue CondLHS = N->getOperand(0);
9121 SDValue CondRHS = N->getOperand(1);
9122 SDValue LHS = N->getOperand(2);
9123 SDValue RHS = N->getOperand(3);
9124 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9128 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
9129 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
9130 IsReversed = false; // x CC y ? x : y
9131 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
9132 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
9133 IsReversed = true ; // x CC y ? y : x
9138 bool IsUnordered = false, IsOrEqual;
9149 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
9150 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
9160 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
9161 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
9165 // If LHS is NaN, an ordered comparison will be false and the result will be
9166 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
9167 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9168 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9171 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
9172 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
9173 // used for unsafe math or if one of the operands is known to be nonzero.
9174 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
9175 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9178 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9181 /// Get rid of unnecessary NVCASTs (that don't change the type).
9182 static SDValue performNVCASTCombine(SDNode *N) {
9183 if (N->getValueType(0) == N->getOperand(0).getValueType())
9184 return N->getOperand(0);
9189 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
9190 DAGCombinerInfo &DCI) const {
9191 SelectionDAG &DAG = DCI.DAG;
9192 switch (N->getOpcode()) {
9197 return performAddSubLongCombine(N, DCI, DAG);
9199 return performXorCombine(N, DAG, DCI, Subtarget);
9201 return performMulCombine(N, DAG, DCI, Subtarget);
9202 case ISD::SINT_TO_FP:
9203 case ISD::UINT_TO_FP:
9204 return performIntToFpCombine(N, DAG, Subtarget);
9206 return performORCombine(N, DCI, Subtarget);
9207 case ISD::INTRINSIC_WO_CHAIN:
9208 return performIntrinsicCombine(N, DCI, Subtarget);
9209 case ISD::ANY_EXTEND:
9210 case ISD::ZERO_EXTEND:
9211 case ISD::SIGN_EXTEND:
9212 return performExtendCombine(N, DCI, DAG);
9214 return performBitcastCombine(N, DCI, DAG);
9215 case ISD::CONCAT_VECTORS:
9216 return performConcatVectorsCombine(N, DCI, DAG);
9218 return performSelectCombine(N, DCI);
9220 return performVSelectCombine(N, DCI.DAG);
9221 case ISD::SELECT_CC:
9222 return performSelectCCCombine(N, DCI.DAG);
9224 return performSTORECombine(N, DCI, DAG, Subtarget);
9225 case AArch64ISD::BRCOND:
9226 return performBRCONDCombine(N, DCI, DAG);
9227 case AArch64ISD::CSEL:
9228 return performCONDCombine(N, DCI, DAG, 2, 3);
9229 case AArch64ISD::DUP:
9230 return performPostLD1Combine(N, DCI, false);
9231 case AArch64ISD::NVCAST:
9232 return performNVCASTCombine(N);
9233 case ISD::INSERT_VECTOR_ELT:
9234 return performPostLD1Combine(N, DCI, true);
9235 case ISD::INTRINSIC_VOID:
9236 case ISD::INTRINSIC_W_CHAIN:
9237 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9238 case Intrinsic::aarch64_neon_ld2:
9239 case Intrinsic::aarch64_neon_ld3:
9240 case Intrinsic::aarch64_neon_ld4:
9241 case Intrinsic::aarch64_neon_ld1x2:
9242 case Intrinsic::aarch64_neon_ld1x3:
9243 case Intrinsic::aarch64_neon_ld1x4:
9244 case Intrinsic::aarch64_neon_ld2lane:
9245 case Intrinsic::aarch64_neon_ld3lane:
9246 case Intrinsic::aarch64_neon_ld4lane:
9247 case Intrinsic::aarch64_neon_ld2r:
9248 case Intrinsic::aarch64_neon_ld3r:
9249 case Intrinsic::aarch64_neon_ld4r:
9250 case Intrinsic::aarch64_neon_st2:
9251 case Intrinsic::aarch64_neon_st3:
9252 case Intrinsic::aarch64_neon_st4:
9253 case Intrinsic::aarch64_neon_st1x2:
9254 case Intrinsic::aarch64_neon_st1x3:
9255 case Intrinsic::aarch64_neon_st1x4:
9256 case Intrinsic::aarch64_neon_st2lane:
9257 case Intrinsic::aarch64_neon_st3lane:
9258 case Intrinsic::aarch64_neon_st4lane:
9259 return performNEONPostLDSTCombine(N, DCI, DAG);
9267 // Check if the return value is used as only a return value, as otherwise
9268 // we can't perform a tail-call. In particular, we need to check for
9269 // target ISD nodes that are returns and any other "odd" constructs
9270 // that the generic analysis code won't necessarily catch.
9271 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9272 SDValue &Chain) const {
9273 if (N->getNumValues() != 1)
9275 if (!N->hasNUsesOfValue(1, 0))
9278 SDValue TCChain = Chain;
9279 SDNode *Copy = *N->use_begin();
9280 if (Copy->getOpcode() == ISD::CopyToReg) {
9281 // If the copy has a glue operand, we conservatively assume it isn't safe to
9282 // perform a tail call.
9283 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9286 TCChain = Copy->getOperand(0);
9287 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9290 bool HasRet = false;
9291 for (SDNode *Node : Copy->uses()) {
9292 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9304 // Return whether the an instruction can potentially be optimized to a tail
9305 // call. This will cause the optimizers to attempt to move, or duplicate,
9306 // return instructions to help enable tail call optimizations for this
9308 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9309 if (!CI->isTailCall())
9315 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9317 ISD::MemIndexedMode &AM,
9319 SelectionDAG &DAG) const {
9320 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9323 Base = Op->getOperand(0);
9324 // All of the indexed addressing mode instructions take a signed
9325 // 9 bit immediate offset.
9326 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9327 int64_t RHSC = (int64_t)RHS->getZExtValue();
9328 if (RHSC >= 256 || RHSC <= -256)
9330 IsInc = (Op->getOpcode() == ISD::ADD);
9331 Offset = Op->getOperand(1);
9337 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9339 ISD::MemIndexedMode &AM,
9340 SelectionDAG &DAG) const {
9343 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9344 VT = LD->getMemoryVT();
9345 Ptr = LD->getBasePtr();
9346 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9347 VT = ST->getMemoryVT();
9348 Ptr = ST->getBasePtr();
9353 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9355 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9359 bool AArch64TargetLowering::getPostIndexedAddressParts(
9360 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9361 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9364 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9365 VT = LD->getMemoryVT();
9366 Ptr = LD->getBasePtr();
9367 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9368 VT = ST->getMemoryVT();
9369 Ptr = ST->getBasePtr();
9374 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9376 // Post-indexing updates the base, so it's not a valid transform
9377 // if that's not the same as the load's pointer.
9380 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9384 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9385 SelectionDAG &DAG) {
9387 SDValue Op = N->getOperand(0);
9389 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9393 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9394 DAG.getUNDEF(MVT::i32), Op,
9395 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9397 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9398 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9401 void AArch64TargetLowering::ReplaceNodeResults(
9402 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9403 switch (N->getOpcode()) {
9405 llvm_unreachable("Don't know how to custom expand this");
9407 ReplaceBITCASTResults(N, Results, DAG);
9409 case ISD::FP_TO_UINT:
9410 case ISD::FP_TO_SINT:
9411 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9412 // Let normal code take care of it by not adding anything to Results.
9417 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9421 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
9422 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9423 // reciprocal if there are three or more FDIVs.
9427 TargetLoweringBase::LegalizeTypeAction
9428 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9429 MVT SVT = VT.getSimpleVT();
9430 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9431 // v4i16, v2i32 instead of to promote.
9432 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9433 || SVT == MVT::v1f32)
9434 return TypeWidenVector;
9436 return TargetLoweringBase::getPreferredVectorAction(VT);
9439 // Loads and stores less than 128-bits are already atomic; ones above that
9440 // are doomed anyway, so defer to the default libcall and blame the OS when
9442 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9443 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9447 // Loads and stores less than 128-bits are already atomic; ones above that
9448 // are doomed anyway, so defer to the default libcall and blame the OS when
9450 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9451 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9455 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9456 TargetLoweringBase::AtomicRMWExpansionKind
9457 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9458 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9459 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9460 : AtomicRMWExpansionKind::None;
9463 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9467 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9468 AtomicOrdering Ord) const {
9469 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9470 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9471 bool IsAcquire = isAtLeastAcquire(Ord);
9473 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9474 // intrinsic must return {i64, i64} and we have to recombine them into a
9475 // single i128 here.
9476 if (ValTy->getPrimitiveSizeInBits() == 128) {
9478 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9479 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9481 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9482 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9484 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9485 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9486 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9487 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9488 return Builder.CreateOr(
9489 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9492 Type *Tys[] = { Addr->getType() };
9494 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9495 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9497 return Builder.CreateTruncOrBitCast(
9498 Builder.CreateCall(Ldxr, Addr),
9499 cast<PointerType>(Addr->getType())->getElementType());
9502 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9503 Value *Val, Value *Addr,
9504 AtomicOrdering Ord) const {
9505 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9506 bool IsRelease = isAtLeastRelease(Ord);
9508 // Since the intrinsics must have legal type, the i128 intrinsics take two
9509 // parameters: "i64, i64". We must marshal Val into the appropriate form
9511 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9513 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9514 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9515 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9517 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9518 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9519 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9520 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9524 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9525 Type *Tys[] = { Addr->getType() };
9526 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9528 return Builder.CreateCall(Stxr,
9529 {Builder.CreateZExtOrBitCast(
9530 Val, Stxr->getFunctionType()->getParamType(0)),
9534 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9535 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9536 return Ty->isArrayTy();
9539 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,