1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
32 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
33 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
35 if (Subtarget->isTargetLinux())
36 return new AArch64LinuxTargetObjectFile();
37 if (Subtarget->isTargetELF())
38 return new TargetLoweringObjectFileELF();
39 llvm_unreachable("unknown subtarget type");
43 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
44 : TargetLowering(TM, createTLOF(TM)),
45 Subtarget(&TM.getSubtarget<AArch64Subtarget>()),
46 RegInfo(TM.getRegisterInfo()),
47 Itins(TM.getInstrItineraryData()) {
49 // SIMD compares set the entire lane's bits to 1
50 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
52 // Scalar register <-> type mapping
53 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
54 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
55 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
56 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
57 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
58 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
60 computeRegisterProperties();
62 // We combine OR nodes for bitfield and NEON BSL operations.
63 setTargetDAGCombine(ISD::OR);
65 setTargetDAGCombine(ISD::AND);
66 setTargetDAGCombine(ISD::SRA);
68 // AArch64 does not have i1 loads, or much of anything for i1 really.
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
73 setStackPointerRegisterToSaveRestore(AArch64::XSP);
74 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
75 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
76 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
78 // We'll lower globals to wrappers for selection.
79 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
80 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
82 // A64 instructions have the comparison predicate attached to the user of the
83 // result, but having a separate comparison is valuable for matching.
84 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
85 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
86 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
87 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Custom);
90 setOperationAction(ISD::SELECT, MVT::i64, Custom);
91 setOperationAction(ISD::SELECT, MVT::f32, Custom);
92 setOperationAction(ISD::SELECT, MVT::f64, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
95 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
96 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
97 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
99 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
101 setOperationAction(ISD::SETCC, MVT::i32, Custom);
102 setOperationAction(ISD::SETCC, MVT::i64, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::SETCC, MVT::f64, Custom);
106 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
107 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
108 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
110 setOperationAction(ISD::VASTART, MVT::Other, Custom);
111 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
112 setOperationAction(ISD::VAEND, MVT::Other, Expand);
113 setOperationAction(ISD::VAARG, MVT::Other, Expand);
115 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
117 setOperationAction(ISD::ROTL, MVT::i32, Expand);
118 setOperationAction(ISD::ROTL, MVT::i64, Expand);
120 setOperationAction(ISD::UREM, MVT::i32, Expand);
121 setOperationAction(ISD::UREM, MVT::i64, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
123 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
125 setOperationAction(ISD::SREM, MVT::i32, Expand);
126 setOperationAction(ISD::SREM, MVT::i64, Expand);
127 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
128 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
130 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
131 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
133 // Legal floating-point operations.
134 setOperationAction(ISD::FABS, MVT::f32, Legal);
135 setOperationAction(ISD::FABS, MVT::f64, Legal);
137 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
138 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
140 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
141 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
143 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
144 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
146 setOperationAction(ISD::FNEG, MVT::f32, Legal);
147 setOperationAction(ISD::FNEG, MVT::f64, Legal);
149 setOperationAction(ISD::FRINT, MVT::f32, Legal);
150 setOperationAction(ISD::FRINT, MVT::f64, Legal);
152 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
153 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
155 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
156 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
158 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
159 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
160 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
162 // Illegal floating-point operations.
163 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
166 setOperationAction(ISD::FCOS, MVT::f32, Expand);
167 setOperationAction(ISD::FCOS, MVT::f64, Expand);
169 setOperationAction(ISD::FEXP, MVT::f32, Expand);
170 setOperationAction(ISD::FEXP, MVT::f64, Expand);
172 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
173 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
175 setOperationAction(ISD::FLOG, MVT::f32, Expand);
176 setOperationAction(ISD::FLOG, MVT::f64, Expand);
178 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
179 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
181 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
182 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
184 setOperationAction(ISD::FPOW, MVT::f32, Expand);
185 setOperationAction(ISD::FPOW, MVT::f64, Expand);
187 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
188 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
190 setOperationAction(ISD::FREM, MVT::f32, Expand);
191 setOperationAction(ISD::FREM, MVT::f64, Expand);
193 setOperationAction(ISD::FSIN, MVT::f32, Expand);
194 setOperationAction(ISD::FSIN, MVT::f64, Expand);
196 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
197 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
199 // Virtually no operation on f128 is legal, but LLVM can't expand them when
200 // there's a valid register class, so we need custom operations in most cases.
201 setOperationAction(ISD::FABS, MVT::f128, Expand);
202 setOperationAction(ISD::FADD, MVT::f128, Custom);
203 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
204 setOperationAction(ISD::FCOS, MVT::f128, Expand);
205 setOperationAction(ISD::FDIV, MVT::f128, Custom);
206 setOperationAction(ISD::FMA, MVT::f128, Expand);
207 setOperationAction(ISD::FMUL, MVT::f128, Custom);
208 setOperationAction(ISD::FNEG, MVT::f128, Expand);
209 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
210 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
211 setOperationAction(ISD::FPOW, MVT::f128, Expand);
212 setOperationAction(ISD::FREM, MVT::f128, Expand);
213 setOperationAction(ISD::FRINT, MVT::f128, Expand);
214 setOperationAction(ISD::FSIN, MVT::f128, Expand);
215 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
216 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
217 setOperationAction(ISD::FSUB, MVT::f128, Custom);
218 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
219 setOperationAction(ISD::SETCC, MVT::f128, Custom);
220 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
221 setOperationAction(ISD::SELECT, MVT::f128, Expand);
222 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
223 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
225 // Lowering for many of the conversions is actually specified by the non-f128
226 // type. The LowerXXX function will be trivial when f128 isn't involved.
227 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
228 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
229 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
230 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
231 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
232 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
233 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
234 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
235 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
236 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
237 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
238 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
239 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
240 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
242 // This prevents LLVM trying to compress double constants into a floating
243 // constant-pool entry and trying to load from there. It's of doubtful benefit
244 // for A64: we'd need LDR followed by FCVT, I believe.
245 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
246 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
247 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
249 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
250 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
251 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
252 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
253 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
254 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
256 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
257 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
259 setExceptionPointerRegister(AArch64::X0);
260 setExceptionSelectorRegister(AArch64::X1);
263 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
264 // It's reasonably important that this value matches the "natural" legal
265 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
266 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
267 if (!VT.isVector()) return MVT::i32;
268 return VT.changeVectorElementTypeToInteger();
271 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
274 static unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
275 AArch64::LDXR_word, AArch64::LDXR_dword};
276 static unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
277 AArch64::LDAXR_word, AArch64::LDAXR_dword};
278 static unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
279 AArch64::STXR_word, AArch64::STXR_dword};
280 static unsigned StoreRels[] = {AArch64::STLXR_byte, AArch64::STLXR_hword,
281 AArch64::STLXR_word, AArch64::STLXR_dword};
283 unsigned *LoadOps, *StoreOps;
284 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
289 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
290 StoreOps = StoreRels;
292 StoreOps = StoreBares;
294 assert(isPowerOf2_32(Size) && Size <= 8 &&
295 "unsupported size for atomic binary op!");
297 LdrOpc = LoadOps[Log2_32(Size)];
298 StrOpc = StoreOps[Log2_32(Size)];
302 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
304 unsigned BinOpcode) const {
305 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
308 const BasicBlock *LLVM_BB = BB->getBasicBlock();
309 MachineFunction *MF = BB->getParent();
310 MachineFunction::iterator It = BB;
313 unsigned dest = MI->getOperand(0).getReg();
314 unsigned ptr = MI->getOperand(1).getReg();
315 unsigned incr = MI->getOperand(2).getReg();
316 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
317 DebugLoc dl = MI->getDebugLoc();
319 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
321 unsigned ldrOpc, strOpc;
322 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
324 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
325 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
326 MF->insert(It, loopMBB);
327 MF->insert(It, exitMBB);
329 // Transfer the remainder of BB and its successor edges to exitMBB.
330 exitMBB->splice(exitMBB->begin(), BB,
331 llvm::next(MachineBasicBlock::iterator(MI)),
333 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
335 const TargetRegisterClass *TRC
336 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
337 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
341 // fallthrough --> loopMBB
342 BB->addSuccessor(loopMBB);
346 // <binop> scratch, dest, incr
347 // stxr stxr_status, scratch, ptr
348 // cbnz stxr_status, loopMBB
349 // fallthrough --> exitMBB
351 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
353 // All arithmetic operations we'll be creating are designed to take an extra
354 // shift or extend operand, which we can conveniently set to zero.
356 // Operand order needs to go the other way for NAND.
357 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
358 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
359 .addReg(incr).addReg(dest).addImm(0);
361 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
362 .addReg(dest).addReg(incr).addImm(0);
365 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
366 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
367 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
369 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
370 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
371 .addReg(stxr_status).addMBB(loopMBB);
373 BB->addSuccessor(loopMBB);
374 BB->addSuccessor(exitMBB);
380 MI->eraseFromParent(); // The instruction is gone now.
386 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
387 MachineBasicBlock *BB,
390 A64CC::CondCodes Cond) const {
391 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
393 const BasicBlock *LLVM_BB = BB->getBasicBlock();
394 MachineFunction *MF = BB->getParent();
395 MachineFunction::iterator It = BB;
398 unsigned dest = MI->getOperand(0).getReg();
399 unsigned ptr = MI->getOperand(1).getReg();
400 unsigned incr = MI->getOperand(2).getReg();
401 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
403 unsigned oldval = dest;
404 DebugLoc dl = MI->getDebugLoc();
406 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
407 const TargetRegisterClass *TRC, *TRCsp;
409 TRC = &AArch64::GPR64RegClass;
410 TRCsp = &AArch64::GPR64xspRegClass;
412 TRC = &AArch64::GPR32RegClass;
413 TRCsp = &AArch64::GPR32wspRegClass;
416 unsigned ldrOpc, strOpc;
417 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
419 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
420 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
421 MF->insert(It, loopMBB);
422 MF->insert(It, exitMBB);
424 // Transfer the remainder of BB and its successor edges to exitMBB.
425 exitMBB->splice(exitMBB->begin(), BB,
426 llvm::next(MachineBasicBlock::iterator(MI)),
428 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
430 unsigned scratch = MRI.createVirtualRegister(TRC);
431 MRI.constrainRegClass(scratch, TRCsp);
435 // fallthrough --> loopMBB
436 BB->addSuccessor(loopMBB);
440 // cmp incr, dest (, sign extend if necessary)
441 // csel scratch, dest, incr, cond
442 // stxr stxr_status, scratch, ptr
443 // cbnz stxr_status, loopMBB
444 // fallthrough --> exitMBB
446 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
448 // Build compare and cmov instructions.
449 MRI.constrainRegClass(incr, TRCsp);
450 BuildMI(BB, dl, TII->get(CmpOp))
451 .addReg(incr).addReg(oldval).addImm(0);
453 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
455 .addReg(oldval).addReg(incr).addImm(Cond);
457 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
458 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
460 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
461 .addReg(scratch).addReg(ptr);
462 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
463 .addReg(stxr_status).addMBB(loopMBB);
465 BB->addSuccessor(loopMBB);
466 BB->addSuccessor(exitMBB);
472 MI->eraseFromParent(); // The instruction is gone now.
478 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
479 MachineBasicBlock *BB,
480 unsigned Size) const {
481 unsigned dest = MI->getOperand(0).getReg();
482 unsigned ptr = MI->getOperand(1).getReg();
483 unsigned oldval = MI->getOperand(2).getReg();
484 unsigned newval = MI->getOperand(3).getReg();
485 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
486 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
487 DebugLoc dl = MI->getDebugLoc();
489 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
490 const TargetRegisterClass *TRCsp;
491 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
493 unsigned ldrOpc, strOpc;
494 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
496 MachineFunction *MF = BB->getParent();
497 const BasicBlock *LLVM_BB = BB->getBasicBlock();
498 MachineFunction::iterator It = BB;
499 ++It; // insert the new blocks after the current block
501 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
502 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
503 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
504 MF->insert(It, loop1MBB);
505 MF->insert(It, loop2MBB);
506 MF->insert(It, exitMBB);
508 // Transfer the remainder of BB and its successor edges to exitMBB.
509 exitMBB->splice(exitMBB->begin(), BB,
510 llvm::next(MachineBasicBlock::iterator(MI)),
512 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
516 // fallthrough --> loop1MBB
517 BB->addSuccessor(loop1MBB);
524 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
526 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
527 MRI.constrainRegClass(dest, TRCsp);
528 BuildMI(BB, dl, TII->get(CmpOp))
529 .addReg(dest).addReg(oldval).addImm(0);
530 BuildMI(BB, dl, TII->get(AArch64::Bcc))
531 .addImm(A64CC::NE).addMBB(exitMBB);
532 BB->addSuccessor(loop2MBB);
533 BB->addSuccessor(exitMBB);
536 // strex stxr_status, newval, [ptr]
537 // cbnz stxr_status, loop1MBB
539 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
540 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
542 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
543 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
544 .addReg(stxr_status).addMBB(loop1MBB);
545 BB->addSuccessor(loop1MBB);
546 BB->addSuccessor(exitMBB);
552 MI->eraseFromParent(); // The instruction is gone now.
558 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
559 MachineBasicBlock *MBB) const {
560 // We materialise the F128CSEL pseudo-instruction using conditional branches
561 // and loads, giving an instruciton sequence like:
570 // Using virtual registers would probably not be beneficial since COPY
571 // instructions are expensive for f128 (there's no actual instruction to
574 // An alternative would be to do an integer-CSEL on some address. E.g.:
579 // csel x0, x0, x1, ne
582 // It's unclear which approach is actually optimal.
583 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
584 MachineFunction *MF = MBB->getParent();
585 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
586 DebugLoc DL = MI->getDebugLoc();
587 MachineFunction::iterator It = MBB;
590 unsigned DestReg = MI->getOperand(0).getReg();
591 unsigned IfTrueReg = MI->getOperand(1).getReg();
592 unsigned IfFalseReg = MI->getOperand(2).getReg();
593 unsigned CondCode = MI->getOperand(3).getImm();
594 bool NZCVKilled = MI->getOperand(4).isKill();
596 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
597 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
598 MF->insert(It, TrueBB);
599 MF->insert(It, EndBB);
601 // Transfer rest of current basic-block to EndBB
602 EndBB->splice(EndBB->begin(), MBB,
603 llvm::next(MachineBasicBlock::iterator(MI)),
605 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
607 // We need somewhere to store the f128 value needed.
608 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
610 // [... start of incoming MBB ...]
611 // str qIFFALSE, [sp]
614 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
616 .addFrameIndex(ScratchFI)
618 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
621 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
623 MBB->addSuccessor(TrueBB);
624 MBB->addSuccessor(EndBB);
628 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
630 .addFrameIndex(ScratchFI)
633 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
635 TrueBB->addSuccessor(EndBB);
639 // [... rest of incoming MBB ...]
641 EndBB->addLiveIn(AArch64::NZCV);
642 MachineInstr *StartOfEnd = EndBB->begin();
643 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
644 .addFrameIndex(ScratchFI)
647 MI->eraseFromParent();
652 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
653 MachineBasicBlock *MBB) const {
654 switch (MI->getOpcode()) {
655 default: llvm_unreachable("Unhandled instruction with custom inserter");
656 case AArch64::F128CSEL:
657 return EmitF128CSEL(MI, MBB);
658 case AArch64::ATOMIC_LOAD_ADD_I8:
659 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
660 case AArch64::ATOMIC_LOAD_ADD_I16:
661 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
662 case AArch64::ATOMIC_LOAD_ADD_I32:
663 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
664 case AArch64::ATOMIC_LOAD_ADD_I64:
665 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
667 case AArch64::ATOMIC_LOAD_SUB_I8:
668 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
669 case AArch64::ATOMIC_LOAD_SUB_I16:
670 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
671 case AArch64::ATOMIC_LOAD_SUB_I32:
672 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
673 case AArch64::ATOMIC_LOAD_SUB_I64:
674 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
676 case AArch64::ATOMIC_LOAD_AND_I8:
677 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
678 case AArch64::ATOMIC_LOAD_AND_I16:
679 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
680 case AArch64::ATOMIC_LOAD_AND_I32:
681 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
682 case AArch64::ATOMIC_LOAD_AND_I64:
683 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
685 case AArch64::ATOMIC_LOAD_OR_I8:
686 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
687 case AArch64::ATOMIC_LOAD_OR_I16:
688 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
689 case AArch64::ATOMIC_LOAD_OR_I32:
690 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
691 case AArch64::ATOMIC_LOAD_OR_I64:
692 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
694 case AArch64::ATOMIC_LOAD_XOR_I8:
695 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
696 case AArch64::ATOMIC_LOAD_XOR_I16:
697 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
698 case AArch64::ATOMIC_LOAD_XOR_I32:
699 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
700 case AArch64::ATOMIC_LOAD_XOR_I64:
701 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
703 case AArch64::ATOMIC_LOAD_NAND_I8:
704 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
705 case AArch64::ATOMIC_LOAD_NAND_I16:
706 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
707 case AArch64::ATOMIC_LOAD_NAND_I32:
708 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
709 case AArch64::ATOMIC_LOAD_NAND_I64:
710 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
712 case AArch64::ATOMIC_LOAD_MIN_I8:
713 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
714 case AArch64::ATOMIC_LOAD_MIN_I16:
715 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
716 case AArch64::ATOMIC_LOAD_MIN_I32:
717 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
718 case AArch64::ATOMIC_LOAD_MIN_I64:
719 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
721 case AArch64::ATOMIC_LOAD_MAX_I8:
722 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
723 case AArch64::ATOMIC_LOAD_MAX_I16:
724 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
725 case AArch64::ATOMIC_LOAD_MAX_I32:
726 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
727 case AArch64::ATOMIC_LOAD_MAX_I64:
728 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
730 case AArch64::ATOMIC_LOAD_UMIN_I8:
731 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
732 case AArch64::ATOMIC_LOAD_UMIN_I16:
733 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
734 case AArch64::ATOMIC_LOAD_UMIN_I32:
735 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
736 case AArch64::ATOMIC_LOAD_UMIN_I64:
737 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
739 case AArch64::ATOMIC_LOAD_UMAX_I8:
740 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
741 case AArch64::ATOMIC_LOAD_UMAX_I16:
742 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
743 case AArch64::ATOMIC_LOAD_UMAX_I32:
744 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
745 case AArch64::ATOMIC_LOAD_UMAX_I64:
746 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
748 case AArch64::ATOMIC_SWAP_I8:
749 return emitAtomicBinary(MI, MBB, 1, 0);
750 case AArch64::ATOMIC_SWAP_I16:
751 return emitAtomicBinary(MI, MBB, 2, 0);
752 case AArch64::ATOMIC_SWAP_I32:
753 return emitAtomicBinary(MI, MBB, 4, 0);
754 case AArch64::ATOMIC_SWAP_I64:
755 return emitAtomicBinary(MI, MBB, 8, 0);
757 case AArch64::ATOMIC_CMP_SWAP_I8:
758 return emitAtomicCmpSwap(MI, MBB, 1);
759 case AArch64::ATOMIC_CMP_SWAP_I16:
760 return emitAtomicCmpSwap(MI, MBB, 2);
761 case AArch64::ATOMIC_CMP_SWAP_I32:
762 return emitAtomicCmpSwap(MI, MBB, 4);
763 case AArch64::ATOMIC_CMP_SWAP_I64:
764 return emitAtomicCmpSwap(MI, MBB, 8);
769 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
771 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
772 case AArch64ISD::Call: return "AArch64ISD::Call";
773 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
774 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
775 case AArch64ISD::BFI: return "AArch64ISD::BFI";
776 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
777 case AArch64ISD::Ret: return "AArch64ISD::Ret";
778 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
779 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
780 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
781 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
782 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
783 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
784 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
785 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
787 default: return NULL;
791 static const uint16_t AArch64FPRArgRegs[] = {
792 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
793 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
795 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
797 static const uint16_t AArch64ArgRegs[] = {
798 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
799 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
801 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
803 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
804 CCValAssign::LocInfo LocInfo,
805 ISD::ArgFlagsTy ArgFlags, CCState &State) {
806 // Mark all remaining general purpose registers as allocated. We don't
807 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
808 // i64 will go in registers (C.11).
809 for (unsigned i = 0; i < NumArgRegs; ++i)
810 State.AllocateReg(AArch64ArgRegs[i]);
815 #include "AArch64GenCallingConv.inc"
817 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
820 default: llvm_unreachable("Unsupported calling convention");
821 case CallingConv::Fast:
828 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
829 SDLoc DL, SDValue &Chain) const {
830 MachineFunction &MF = DAG.getMachineFunction();
831 MachineFrameInfo *MFI = MF.getFrameInfo();
832 AArch64MachineFunctionInfo *FuncInfo
833 = MF.getInfo<AArch64MachineFunctionInfo>();
835 SmallVector<SDValue, 8> MemOps;
837 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
839 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
842 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
844 if (GPRSaveSize != 0) {
845 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
847 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
849 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
850 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
851 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
852 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
853 MachinePointerInfo::getStack(i * 8),
855 MemOps.push_back(Store);
856 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
857 DAG.getConstant(8, getPointerTy()));
861 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
863 if (FPRSaveSize != 0) {
864 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
866 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
868 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
869 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
870 &AArch64::FPR128RegClass);
871 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
872 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
873 MachinePointerInfo::getStack(i * 16),
875 MemOps.push_back(Store);
876 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
877 DAG.getConstant(16, getPointerTy()));
881 int StackIdx = MFI->CreateFixedObject(8, CCInfo.getNextStackOffset(), true);
883 FuncInfo->setVariadicStackIdx(StackIdx);
884 FuncInfo->setVariadicGPRIdx(GPRIdx);
885 FuncInfo->setVariadicGPRSize(GPRSaveSize);
886 FuncInfo->setVariadicFPRIdx(FPRIdx);
887 FuncInfo->setVariadicFPRSize(FPRSaveSize);
889 if (!MemOps.empty()) {
890 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
897 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
898 CallingConv::ID CallConv, bool isVarArg,
899 const SmallVectorImpl<ISD::InputArg> &Ins,
900 SDLoc dl, SelectionDAG &DAG,
901 SmallVectorImpl<SDValue> &InVals) const {
902 MachineFunction &MF = DAG.getMachineFunction();
903 AArch64MachineFunctionInfo *FuncInfo
904 = MF.getInfo<AArch64MachineFunctionInfo>();
905 MachineFrameInfo *MFI = MF.getFrameInfo();
906 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
908 SmallVector<CCValAssign, 16> ArgLocs;
909 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
910 getTargetMachine(), ArgLocs, *DAG.getContext());
911 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
913 SmallVector<SDValue, 16> ArgValues;
916 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
917 CCValAssign &VA = ArgLocs[i];
918 ISD::ArgFlagsTy Flags = Ins[i].Flags;
920 if (Flags.isByVal()) {
921 // Byval is used for small structs and HFAs in the PCS, but the system
922 // should work in a non-compliant manner for larger structs.
923 EVT PtrTy = getPointerTy();
924 int Size = Flags.getByValSize();
925 unsigned NumRegs = (Size + 7) / 8;
927 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
928 VA.getLocMemOffset(),
930 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
931 InVals.push_back(FrameIdxN);
934 } else if (VA.isRegLoc()) {
935 MVT RegVT = VA.getLocVT();
936 const TargetRegisterClass *RC = getRegClassFor(RegVT);
937 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
939 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
940 } else { // VA.isRegLoc()
941 assert(VA.isMemLoc());
943 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
944 VA.getLocMemOffset(), true);
946 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
947 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
948 MachinePointerInfo::getFixedStack(FI),
949 false, false, false, 0);
954 switch (VA.getLocInfo()) {
955 default: llvm_unreachable("Unknown loc info!");
956 case CCValAssign::Full: break;
957 case CCValAssign::BCvt:
958 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
960 case CCValAssign::SExt:
961 case CCValAssign::ZExt:
962 case CCValAssign::AExt: {
963 unsigned DestSize = VA.getValVT().getSizeInBits();
967 case 8: DestSubReg = AArch64::sub_8; break;
968 case 16: DestSubReg = AArch64::sub_16; break;
969 case 32: DestSubReg = AArch64::sub_32; break;
970 case 64: DestSubReg = AArch64::sub_64; break;
971 default: llvm_unreachable("Unexpected argument promotion");
974 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
975 VA.getValVT(), ArgValue,
976 DAG.getTargetConstant(DestSubReg, MVT::i32)),
982 InVals.push_back(ArgValue);
986 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
988 unsigned StackArgSize = CCInfo.getNextStackOffset();
989 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
990 // This is a non-standard ABI so by fiat I say we're allowed to make full
991 // use of the stack area to be popped, which must be aligned to 16 bytes in
993 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
995 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
997 FuncInfo->setArgumentStackToRestore(StackArgSize);
999 // This realignment carries over to the available bytes below. Our own
1000 // callers will guarantee the space is free by giving an aligned value to
1003 // Even if we're not expected to free up the space, it's useful to know how
1004 // much is there while considering tail calls (because we can reuse it).
1005 FuncInfo->setBytesInStackArgArea(StackArgSize);
1011 AArch64TargetLowering::LowerReturn(SDValue Chain,
1012 CallingConv::ID CallConv, bool isVarArg,
1013 const SmallVectorImpl<ISD::OutputArg> &Outs,
1014 const SmallVectorImpl<SDValue> &OutVals,
1015 SDLoc dl, SelectionDAG &DAG) const {
1016 // CCValAssign - represent the assignment of the return value to a location.
1017 SmallVector<CCValAssign, 16> RVLocs;
1019 // CCState - Info about the registers and stack slots.
1020 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1021 getTargetMachine(), RVLocs, *DAG.getContext());
1023 // Analyze outgoing return values.
1024 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1027 SmallVector<SDValue, 4> RetOps(1, Chain);
1029 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1030 // PCS: "If the type, T, of the result of a function is such that
1031 // void func(T arg) would require that arg be passed as a value in a
1032 // register (or set of registers) according to the rules in 5.4, then the
1033 // result is returned in the same registers as would be used for such an
1036 // Otherwise, the caller shall reserve a block of memory of sufficient
1037 // size and alignment to hold the result. The address of the memory block
1038 // shall be passed as an additional argument to the function in x8."
1040 // This is implemented in two places. The register-return values are dealt
1041 // with here, more complex returns are passed as an sret parameter, which
1042 // means we don't have to worry about it during actual return.
1043 CCValAssign &VA = RVLocs[i];
1044 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1047 SDValue Arg = OutVals[i];
1049 // There's no convenient note in the ABI about this as there is for normal
1050 // arguments, but it says return values are passed in the same registers as
1051 // an argument would be. I believe that includes the comments about
1052 // unspecified higher bits, putting the burden of widening on the *caller*
1053 // for return values.
1054 switch (VA.getLocInfo()) {
1055 default: llvm_unreachable("Unknown loc info");
1056 case CCValAssign::Full: break;
1057 case CCValAssign::SExt:
1058 case CCValAssign::ZExt:
1059 case CCValAssign::AExt:
1060 // Floating-point values should only be extended when they're going into
1061 // memory, which can't happen here so an integer extend is acceptable.
1062 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1064 case CCValAssign::BCvt:
1065 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1069 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1070 Flag = Chain.getValue(1);
1071 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1074 RetOps[0] = Chain; // Update chain.
1076 // Add the flag if we have it.
1078 RetOps.push_back(Flag);
1080 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1081 &RetOps[0], RetOps.size());
1085 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1086 SmallVectorImpl<SDValue> &InVals) const {
1087 SelectionDAG &DAG = CLI.DAG;
1089 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
1090 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
1091 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
1092 SDValue Chain = CLI.Chain;
1093 SDValue Callee = CLI.Callee;
1094 bool &IsTailCall = CLI.IsTailCall;
1095 CallingConv::ID CallConv = CLI.CallConv;
1096 bool IsVarArg = CLI.IsVarArg;
1098 MachineFunction &MF = DAG.getMachineFunction();
1099 AArch64MachineFunctionInfo *FuncInfo
1100 = MF.getInfo<AArch64MachineFunctionInfo>();
1101 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1102 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1103 bool IsSibCall = false;
1106 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1107 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1108 Outs, OutVals, Ins, DAG);
1110 // A sibling call is one where we're under the usual C ABI and not planning
1111 // to change that but can still do a tail call:
1112 if (!TailCallOpt && IsTailCall)
1116 SmallVector<CCValAssign, 16> ArgLocs;
1117 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1118 getTargetMachine(), ArgLocs, *DAG.getContext());
1119 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1121 // On AArch64 (and all other architectures I'm aware of) the most this has to
1122 // do is adjust the stack pointer.
1123 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1125 // Since we're not changing the ABI to make this a tail call, the memory
1126 // operands are already available in the caller's incoming argument space.
1130 // FPDiff is the byte offset of the call's argument area from the callee's.
1131 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1132 // by this amount for a tail call. In a sibling call it must be 0 because the
1133 // caller will deallocate the entire stack and the callee still expects its
1134 // arguments to begin at SP+0. Completely unused for non-tail calls.
1137 if (IsTailCall && !IsSibCall) {
1138 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1140 // FPDiff will be negative if this tail call requires more space than we
1141 // would automatically have in our incoming argument space. Positive if we
1142 // can actually shrink the stack.
1143 FPDiff = NumReusableBytes - NumBytes;
1145 // The stack pointer must be 16-byte aligned at all times it's used for a
1146 // memory operation, which in practice means at *all* times and in
1147 // particular across call boundaries. Therefore our own arguments started at
1148 // a 16-byte aligned SP and the delta applied for the tail call should
1149 // satisfy the same constraint.
1150 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1154 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1157 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1160 SmallVector<SDValue, 8> MemOpChains;
1161 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1164 CCValAssign &VA = ArgLocs[i];
1165 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1166 SDValue Arg = OutVals[i];
1168 // Callee does the actual widening, so all extensions just use an implicit
1169 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1170 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1171 // alternative works on integer types too.
1172 switch (VA.getLocInfo()) {
1173 default: llvm_unreachable("Unknown loc info!");
1174 case CCValAssign::Full: break;
1175 case CCValAssign::SExt:
1176 case CCValAssign::ZExt:
1177 case CCValAssign::AExt: {
1178 unsigned SrcSize = VA.getValVT().getSizeInBits();
1182 case 8: SrcSubReg = AArch64::sub_8; break;
1183 case 16: SrcSubReg = AArch64::sub_16; break;
1184 case 32: SrcSubReg = AArch64::sub_32; break;
1185 case 64: SrcSubReg = AArch64::sub_64; break;
1186 default: llvm_unreachable("Unexpected argument promotion");
1189 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1191 DAG.getUNDEF(VA.getLocVT()),
1193 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1198 case CCValAssign::BCvt:
1199 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1203 if (VA.isRegLoc()) {
1204 // A normal register (sub-) argument. For now we just note it down because
1205 // we want to copy things into registers as late as possible to avoid
1206 // register-pressure (and possibly worse).
1207 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1211 assert(VA.isMemLoc() && "unexpected argument location");
1214 MachinePointerInfo DstInfo;
1216 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1217 VA.getLocVT().getSizeInBits();
1218 OpSize = (OpSize + 7) / 8;
1219 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1220 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1222 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1223 DstInfo = MachinePointerInfo::getFixedStack(FI);
1225 // Make sure any stack arguments overlapping with where we're storing are
1226 // loaded before this eventual operation. Otherwise they'll be clobbered.
1227 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1229 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1231 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1232 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1235 if (Flags.isByVal()) {
1236 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1237 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1238 Flags.getByValAlign(),
1239 /*isVolatile = */ false,
1240 /*alwaysInline = */ false,
1241 DstInfo, MachinePointerInfo(0));
1242 MemOpChains.push_back(Cpy);
1244 // Normal stack argument, put it where it's needed.
1245 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1247 MemOpChains.push_back(Store);
1251 // The loads and stores generated above shouldn't clash with each
1252 // other. Combining them with this TokenFactor notes that fact for the rest of
1254 if (!MemOpChains.empty())
1255 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1256 &MemOpChains[0], MemOpChains.size());
1258 // Most of the rest of the instructions need to be glued together; we don't
1259 // want assignments to actual registers used by a call to be rearranged by a
1260 // well-meaning scheduler.
1263 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1264 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1265 RegsToPass[i].second, InFlag);
1266 InFlag = Chain.getValue(1);
1269 // The linker is responsible for inserting veneers when necessary to put a
1270 // function call destination in range, so we don't need to bother with a
1272 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1273 const GlobalValue *GV = G->getGlobal();
1274 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1275 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1276 const char *Sym = S->getSymbol();
1277 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1280 // We don't usually want to end the call-sequence here because we would tidy
1281 // the frame up *after* the call, however in the ABI-changing tail-call case
1282 // we've carefully laid out the parameters so that when sp is reset they'll be
1283 // in the correct location.
1284 if (IsTailCall && !IsSibCall) {
1285 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1286 DAG.getIntPtrConstant(0, true), InFlag, dl);
1287 InFlag = Chain.getValue(1);
1290 // We produce the following DAG scheme for the actual call instruction:
1291 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1293 // Most arguments aren't going to be used and just keep the values live as
1294 // far as LLVM is concerned. It's expected to be selected as simply "bl
1295 // callee" (for a direct, non-tail call).
1296 std::vector<SDValue> Ops;
1297 Ops.push_back(Chain);
1298 Ops.push_back(Callee);
1301 // Each tail call may have to adjust the stack by a different amount, so
1302 // this information must travel along with the operation for eventual
1303 // consumption by emitEpilogue.
1304 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1307 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1308 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1309 RegsToPass[i].second.getValueType()));
1312 // Add a register mask operand representing the call-preserved registers. This
1313 // is used later in codegen to constrain register-allocation.
1314 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1315 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1316 assert(Mask && "Missing call preserved mask for calling convention");
1317 Ops.push_back(DAG.getRegisterMask(Mask));
1319 // If we needed glue, put it in as the last argument.
1320 if (InFlag.getNode())
1321 Ops.push_back(InFlag);
1323 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1326 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1329 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1330 InFlag = Chain.getValue(1);
1332 // Now we can reclaim the stack, just as well do it before working out where
1333 // our return value is.
1335 uint64_t CalleePopBytes
1336 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1338 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1339 DAG.getIntPtrConstant(CalleePopBytes, true),
1341 InFlag = Chain.getValue(1);
1344 return LowerCallResult(Chain, InFlag, CallConv,
1345 IsVarArg, Ins, dl, DAG, InVals);
1349 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1350 CallingConv::ID CallConv, bool IsVarArg,
1351 const SmallVectorImpl<ISD::InputArg> &Ins,
1352 SDLoc dl, SelectionDAG &DAG,
1353 SmallVectorImpl<SDValue> &InVals) const {
1354 // Assign locations to each value returned by this call.
1355 SmallVector<CCValAssign, 16> RVLocs;
1356 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1357 getTargetMachine(), RVLocs, *DAG.getContext());
1358 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1360 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1361 CCValAssign VA = RVLocs[i];
1363 // Return values that are too big to fit into registers should use an sret
1364 // pointer, so this can be a lot simpler than the main argument code.
1365 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1367 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1369 Chain = Val.getValue(1);
1370 InFlag = Val.getValue(2);
1372 switch (VA.getLocInfo()) {
1373 default: llvm_unreachable("Unknown loc info!");
1374 case CCValAssign::Full: break;
1375 case CCValAssign::BCvt:
1376 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1378 case CCValAssign::ZExt:
1379 case CCValAssign::SExt:
1380 case CCValAssign::AExt:
1381 // Floating-point arguments only get extended/truncated if they're going
1382 // in memory, so using the integer operation is acceptable here.
1383 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1387 InVals.push_back(Val);
1394 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1395 CallingConv::ID CalleeCC,
1397 bool IsCalleeStructRet,
1398 bool IsCallerStructRet,
1399 const SmallVectorImpl<ISD::OutputArg> &Outs,
1400 const SmallVectorImpl<SDValue> &OutVals,
1401 const SmallVectorImpl<ISD::InputArg> &Ins,
1402 SelectionDAG& DAG) const {
1404 // For CallingConv::C this function knows whether the ABI needs
1405 // changing. That's not true for other conventions so they will have to opt in
1407 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1410 const MachineFunction &MF = DAG.getMachineFunction();
1411 const Function *CallerF = MF.getFunction();
1412 CallingConv::ID CallerCC = CallerF->getCallingConv();
1413 bool CCMatch = CallerCC == CalleeCC;
1415 // Byval parameters hand the function a pointer directly into the stack area
1416 // we want to reuse during a tail call. Working around this *is* possible (see
1417 // X86) but less efficient and uglier in LowerCall.
1418 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1419 e = CallerF->arg_end(); i != e; ++i)
1420 if (i->hasByValAttr())
1423 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1424 if (IsTailCallConvention(CalleeCC) && CCMatch)
1429 // Now we search for cases where we can use a tail call without changing the
1430 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1433 // I want anyone implementing a new calling convention to think long and hard
1434 // about this assert.
1435 assert((!IsVarArg || CalleeCC == CallingConv::C)
1436 && "Unexpected variadic calling convention");
1438 if (IsVarArg && !Outs.empty()) {
1439 // At least two cases here: if caller is fastcc then we can't have any
1440 // memory arguments (we'd be expected to clean up the stack afterwards). If
1441 // caller is C then we could potentially use its argument area.
1443 // FIXME: for now we take the most conservative of these in both cases:
1444 // disallow all variadic memory operands.
1445 SmallVector<CCValAssign, 16> ArgLocs;
1446 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1447 getTargetMachine(), ArgLocs, *DAG.getContext());
1449 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1450 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1451 if (!ArgLocs[i].isRegLoc())
1455 // If the calling conventions do not match, then we'd better make sure the
1456 // results are returned in the same way as what the caller expects.
1458 SmallVector<CCValAssign, 16> RVLocs1;
1459 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1460 getTargetMachine(), RVLocs1, *DAG.getContext());
1461 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1463 SmallVector<CCValAssign, 16> RVLocs2;
1464 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1465 getTargetMachine(), RVLocs2, *DAG.getContext());
1466 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1468 if (RVLocs1.size() != RVLocs2.size())
1470 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1471 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1473 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1475 if (RVLocs1[i].isRegLoc()) {
1476 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1479 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1485 // Nothing more to check if the callee is taking no arguments
1489 SmallVector<CCValAssign, 16> ArgLocs;
1490 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1491 getTargetMachine(), ArgLocs, *DAG.getContext());
1493 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1495 const AArch64MachineFunctionInfo *FuncInfo
1496 = MF.getInfo<AArch64MachineFunctionInfo>();
1498 // If the stack arguments for this call would fit into our own save area then
1499 // the call can be made tail.
1500 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1503 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1504 bool TailCallOpt) const {
1505 return CallCC == CallingConv::Fast && TailCallOpt;
1508 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1509 return CallCC == CallingConv::Fast;
1512 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1514 MachineFrameInfo *MFI,
1515 int ClobberedFI) const {
1516 SmallVector<SDValue, 8> ArgChains;
1517 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1518 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1520 // Include the original chain at the beginning of the list. When this is
1521 // used by target LowerCall hooks, this helps legalize find the
1522 // CALLSEQ_BEGIN node.
1523 ArgChains.push_back(Chain);
1525 // Add a chain value for each stack argument corresponding
1526 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1527 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1528 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1529 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1530 if (FI->getIndex() < 0) {
1531 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1532 int64_t InLastByte = InFirstByte;
1533 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1535 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1536 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1537 ArgChains.push_back(SDValue(L, 1));
1540 // Build a tokenfactor for all the chains.
1541 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1542 &ArgChains[0], ArgChains.size());
1545 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1547 case ISD::SETEQ: return A64CC::EQ;
1548 case ISD::SETGT: return A64CC::GT;
1549 case ISD::SETGE: return A64CC::GE;
1550 case ISD::SETLT: return A64CC::LT;
1551 case ISD::SETLE: return A64CC::LE;
1552 case ISD::SETNE: return A64CC::NE;
1553 case ISD::SETUGT: return A64CC::HI;
1554 case ISD::SETUGE: return A64CC::HS;
1555 case ISD::SETULT: return A64CC::LO;
1556 case ISD::SETULE: return A64CC::LS;
1557 default: llvm_unreachable("Unexpected condition code");
1561 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1562 // icmp is implemented using adds/subs immediate, which take an unsigned
1563 // 12-bit immediate, optionally shifted left by 12 bits.
1565 // Symmetric by using adds/subs
1569 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1572 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1573 ISD::CondCode CC, SDValue &A64cc,
1574 SelectionDAG &DAG, SDLoc &dl) const {
1575 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1577 EVT VT = RHSC->getValueType(0);
1578 bool knownInvalid = false;
1580 // I'm not convinced the rest of LLVM handles these edge cases properly, but
1581 // we can at least get it right.
1582 if (isSignedIntSetCC(CC)) {
1583 C = RHSC->getSExtValue();
1584 } else if (RHSC->getZExtValue() > INT64_MAX) {
1585 // A 64-bit constant not representable by a signed 64-bit integer is far
1586 // too big to fit into a SUBS immediate anyway.
1587 knownInvalid = true;
1589 C = RHSC->getZExtValue();
1592 if (!knownInvalid && !isLegalICmpImmediate(C)) {
1593 // Constant does not fit, try adjusting it by one?
1598 if (isLegalICmpImmediate(C-1)) {
1599 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1600 RHS = DAG.getConstant(C-1, VT);
1605 if (isLegalICmpImmediate(C-1)) {
1606 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1607 RHS = DAG.getConstant(C-1, VT);
1612 if (isLegalICmpImmediate(C+1)) {
1613 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1614 RHS = DAG.getConstant(C+1, VT);
1619 if (isLegalICmpImmediate(C+1)) {
1620 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1621 RHS = DAG.getConstant(C+1, VT);
1628 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
1629 A64cc = DAG.getConstant(CondCode, MVT::i32);
1630 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1631 DAG.getCondCode(CC));
1634 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1635 A64CC::CondCodes &Alternative) {
1636 A64CC::CondCodes CondCode = A64CC::Invalid;
1637 Alternative = A64CC::Invalid;
1640 default: llvm_unreachable("Unknown FP condition!");
1642 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
1644 case ISD::SETOGT: CondCode = A64CC::GT; break;
1646 case ISD::SETOGE: CondCode = A64CC::GE; break;
1647 case ISD::SETOLT: CondCode = A64CC::MI; break;
1648 case ISD::SETOLE: CondCode = A64CC::LS; break;
1649 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
1650 case ISD::SETO: CondCode = A64CC::VC; break;
1651 case ISD::SETUO: CondCode = A64CC::VS; break;
1652 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
1653 case ISD::SETUGT: CondCode = A64CC::HI; break;
1654 case ISD::SETUGE: CondCode = A64CC::PL; break;
1656 case ISD::SETULT: CondCode = A64CC::LT; break;
1658 case ISD::SETULE: CondCode = A64CC::LE; break;
1660 case ISD::SETUNE: CondCode = A64CC::NE; break;
1666 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1668 EVT PtrVT = getPointerTy();
1669 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1671 switch(getTargetMachine().getCodeModel()) {
1672 case CodeModel::Small:
1673 // The most efficient code is PC-relative anyway for the small memory model,
1674 // so we don't need to worry about relocation model.
1675 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
1676 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1677 AArch64II::MO_NO_FLAG),
1678 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1679 AArch64II::MO_LO12),
1680 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
1681 case CodeModel::Large:
1683 AArch64ISD::WrapperLarge, DL, PtrVT,
1684 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3),
1685 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
1686 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
1687 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
1689 llvm_unreachable("Only small and large code models supported now");
1694 // (BRCOND chain, val, dest)
1696 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1698 SDValue Chain = Op.getOperand(0);
1699 SDValue TheBit = Op.getOperand(1);
1700 SDValue DestBB = Op.getOperand(2);
1702 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
1703 // that as the consumer we are responsible for ignoring rubbish in higher
1705 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
1706 DAG.getConstant(1, MVT::i32));
1708 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
1709 DAG.getConstant(0, TheBit.getValueType()),
1710 DAG.getCondCode(ISD::SETNE));
1712 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
1713 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
1717 // (BR_CC chain, condcode, lhs, rhs, dest)
1719 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1721 SDValue Chain = Op.getOperand(0);
1722 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1723 SDValue LHS = Op.getOperand(2);
1724 SDValue RHS = Op.getOperand(3);
1725 SDValue DestBB = Op.getOperand(4);
1727 if (LHS.getValueType() == MVT::f128) {
1728 // f128 comparisons are lowered to runtime calls by a routine which sets
1729 // LHS, RHS and CC appropriately for the rest of this function to continue.
1730 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
1732 // If softenSetCCOperands returned a scalar, we need to compare the result
1733 // against zero to select between true and false values.
1734 if (RHS.getNode() == 0) {
1735 RHS = DAG.getConstant(0, LHS.getValueType());
1740 if (LHS.getValueType().isInteger()) {
1743 // Integers are handled in a separate function because the combinations of
1744 // immediates and tests can get hairy and we may want to fiddle things.
1745 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
1747 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1748 Chain, CmpOp, A64cc, DestBB);
1751 // Note that some LLVM floating-point CondCodes can't be lowered to a single
1752 // conditional branch, hence FPCCToA64CC can set a second test, where either
1753 // passing is sufficient.
1754 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
1755 CondCode = FPCCToA64CC(CC, Alternative);
1756 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
1757 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1758 DAG.getCondCode(CC));
1759 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1760 Chain, SetCC, A64cc, DestBB);
1762 if (Alternative != A64CC::Invalid) {
1763 A64cc = DAG.getConstant(Alternative, MVT::i32);
1764 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1765 A64BR_CC, SetCC, A64cc, DestBB);
1773 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
1774 RTLIB::Libcall Call) const {
1777 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
1778 EVT ArgVT = Op.getOperand(i).getValueType();
1779 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1780 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
1781 Entry.isSExt = false;
1782 Entry.isZExt = false;
1783 Args.push_back(Entry);
1785 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
1787 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
1789 // By default, the input chain to this libcall is the entry node of the
1790 // function. If the libcall is going to be emitted as a tail call then
1791 // isUsedByReturnOnly will change it to the right chain if the return
1792 // node which is being folded has a non-entry input chain.
1793 SDValue InChain = DAG.getEntryNode();
1795 // isTailCall may be true since the callee does not reference caller stack
1796 // frame. Check if it's in the right position.
1797 SDValue TCChain = InChain;
1798 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
1803 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
1804 0, getLibcallCallingConv(Call), isTailCall,
1805 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1806 Callee, Args, DAG, SDLoc(Op));
1807 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1809 if (!CallInfo.second.getNode())
1810 // It's a tailcall, return the chain (which is the DAG root).
1811 return DAG.getRoot();
1813 return CallInfo.first;
1817 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
1818 if (Op.getOperand(0).getValueType() != MVT::f128) {
1819 // It's legal except when f128 is involved
1824 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1826 SDValue SrcVal = Op.getOperand(0);
1827 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1828 /*isSigned*/ false, SDLoc(Op));
1832 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
1833 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1836 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1838 return LowerF128ToCall(Op, DAG, LC);
1842 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1843 bool IsSigned) const {
1844 if (Op.getOperand(0).getValueType() != MVT::f128) {
1845 // It's legal except when f128 is involved
1851 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1853 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1855 return LowerF128ToCall(Op, DAG, LC);
1859 AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op,
1860 SelectionDAG &DAG) const {
1861 assert(getTargetMachine().getCodeModel() == CodeModel::Large);
1862 assert(getTargetMachine().getRelocationModel() == Reloc::Static);
1864 EVT PtrVT = getPointerTy();
1866 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
1867 const GlobalValue *GV = GN->getGlobal();
1869 SDValue GlobalAddr = DAG.getNode(
1870 AArch64ISD::WrapperLarge, dl, PtrVT,
1871 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3),
1872 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
1873 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
1874 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
1876 if (GN->getOffset() != 0)
1877 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
1878 DAG.getConstant(GN->getOffset(), PtrVT));
1884 AArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op,
1885 SelectionDAG &DAG) const {
1886 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
1888 EVT PtrVT = getPointerTy();
1890 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
1891 const GlobalValue *GV = GN->getGlobal();
1892 unsigned Alignment = GV->getAlignment();
1893 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1894 if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) {
1895 // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate
1896 // to zero when they remain undefined. In PIC mode the GOT can take care of
1897 // this, but in absolute mode we use a constant pool load.
1899 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
1900 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
1901 AArch64II::MO_NO_FLAG),
1902 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
1903 AArch64II::MO_LO12),
1904 DAG.getConstant(8, MVT::i32));
1905 SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
1906 MachinePointerInfo::getConstantPool(),
1907 /*isVolatile=*/ false,
1908 /*isNonTemporal=*/ true,
1909 /*isInvariant=*/ true, 8);
1910 if (GN->getOffset() != 0)
1911 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
1912 DAG.getConstant(GN->getOffset(), PtrVT));
1917 if (Alignment == 0) {
1918 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
1919 if (GVPtrTy->getElementType()->isSized()) {
1921 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
1923 // Be conservative if we can't guess, not that it really matters:
1924 // functions and labels aren't valid for loads, and the methods used to
1925 // actually calculate an address work with any alignment.
1930 unsigned char HiFixup, LoFixup;
1931 bool UseGOT = Subtarget->GVIsIndirectSymbol(GV, RelocM);
1934 HiFixup = AArch64II::MO_GOT;
1935 LoFixup = AArch64II::MO_GOT_LO12;
1938 HiFixup = AArch64II::MO_NO_FLAG;
1939 LoFixup = AArch64II::MO_LO12;
1942 // AArch64's small model demands the following sequence:
1943 // ADRP x0, somewhere
1944 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
1945 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
1946 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1948 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1950 DAG.getConstant(Alignment, MVT::i32));
1953 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
1957 if (GN->getOffset() != 0)
1958 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
1959 DAG.getConstant(GN->getOffset(), PtrVT));
1965 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
1966 SelectionDAG &DAG) const {
1967 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
1968 // we make those distinctions here.
1970 switch (getTargetMachine().getCodeModel()) {
1971 case CodeModel::Small:
1972 return LowerGlobalAddressELFSmall(Op, DAG);
1973 case CodeModel::Large:
1974 return LowerGlobalAddressELFLarge(Op, DAG);
1976 llvm_unreachable("Only small and large code models supported now");
1980 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
1983 SelectionDAG &DAG) const {
1984 EVT PtrVT = getPointerTy();
1986 // The function we need to call is simply the first entry in the GOT for this
1987 // descriptor, load it in preparation.
1988 SDValue Func, Chain;
1989 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
1992 // The function takes only one argument: the address of the descriptor itself
1995 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
1996 Glue = Chain.getValue(1);
1998 // Finally, there's a special calling-convention which means that the lookup
1999 // must preserve all registers (except X0, obviously).
2000 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2001 const AArch64RegisterInfo *A64RI
2002 = static_cast<const AArch64RegisterInfo *>(TRI);
2003 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
2005 // We're now ready to populate the argument list, as with a normal call:
2006 std::vector<SDValue> Ops;
2007 Ops.push_back(Chain);
2008 Ops.push_back(Func);
2009 Ops.push_back(SymAddr);
2010 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2011 Ops.push_back(DAG.getRegisterMask(Mask));
2012 Ops.push_back(Glue);
2014 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2015 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
2017 Glue = Chain.getValue(1);
2019 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
2020 // back to the generic handling code.
2021 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2025 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2026 SelectionDAG &DAG) const {
2027 assert(Subtarget->isTargetELF() &&
2028 "TLS not implemented for non-ELF targets");
2029 assert(getTargetMachine().getCodeModel() == CodeModel::Small
2030 && "TLS only supported in small memory model");
2031 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2033 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2036 EVT PtrVT = getPointerTy();
2038 const GlobalValue *GV = GA->getGlobal();
2040 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2042 if (Model == TLSModel::InitialExec) {
2043 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2044 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2045 AArch64II::MO_GOTTPREL),
2046 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2047 AArch64II::MO_GOTTPREL_LO12),
2048 DAG.getConstant(8, MVT::i32));
2049 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2051 } else if (Model == TLSModel::LocalExec) {
2052 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2053 AArch64II::MO_TPREL_G1);
2054 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2055 AArch64II::MO_TPREL_G0_NC);
2057 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2058 DAG.getTargetConstant(0, MVT::i32)), 0);
2059 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2061 DAG.getTargetConstant(0, MVT::i32)), 0);
2062 } else if (Model == TLSModel::GeneralDynamic) {
2063 // Accesses used in this sequence go via the TLS descriptor which lives in
2064 // the GOT. Prepare an address we can use to handle this.
2065 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2066 AArch64II::MO_TLSDESC);
2067 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2068 AArch64II::MO_TLSDESC_LO12);
2069 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2071 DAG.getConstant(8, MVT::i32));
2072 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2074 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2075 } else if (Model == TLSModel::LocalDynamic) {
2076 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2077 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2078 // the beginning of the module's TLS region, followed by a DTPREL offset
2081 // These accesses will need deduplicating if there's more than one.
2082 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2083 .getInfo<AArch64MachineFunctionInfo>();
2084 MFI->incNumLocalDynamicTLSAccesses();
2087 // Get the location of _TLS_MODULE_BASE_:
2088 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2089 AArch64II::MO_TLSDESC);
2090 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2091 AArch64II::MO_TLSDESC_LO12);
2092 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2094 DAG.getConstant(8, MVT::i32));
2095 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2097 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2099 // Get the variable's offset from _TLS_MODULE_BASE_
2100 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2101 AArch64II::MO_DTPREL_G1);
2102 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2103 AArch64II::MO_DTPREL_G0_NC);
2105 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2106 DAG.getTargetConstant(0, MVT::i32)), 0);
2107 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2109 DAG.getTargetConstant(0, MVT::i32)), 0);
2111 llvm_unreachable("Unsupported TLS access model");
2114 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2118 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2119 bool IsSigned) const {
2120 if (Op.getValueType() != MVT::f128) {
2121 // Legal for everything except f128.
2127 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2129 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2131 return LowerF128ToCall(Op, DAG, LC);
2136 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2137 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2139 EVT PtrVT = getPointerTy();
2141 // When compiling PIC, jump tables get put in the code section so a static
2142 // relocation-style is acceptable for both cases.
2143 switch (getTargetMachine().getCodeModel()) {
2144 case CodeModel::Small:
2145 return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2146 DAG.getTargetJumpTable(JT->getIndex(), PtrVT),
2147 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2148 AArch64II::MO_LO12),
2149 DAG.getConstant(1, MVT::i32));
2150 case CodeModel::Large:
2152 AArch64ISD::WrapperLarge, dl, PtrVT,
2153 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3),
2154 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC),
2155 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC),
2156 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC));
2158 llvm_unreachable("Only small and large code models supported now");
2162 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
2164 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2166 SDValue LHS = Op.getOperand(0);
2167 SDValue RHS = Op.getOperand(1);
2168 SDValue IfTrue = Op.getOperand(2);
2169 SDValue IfFalse = Op.getOperand(3);
2170 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2172 if (LHS.getValueType() == MVT::f128) {
2173 // f128 comparisons are lowered to libcalls, but slot in nicely here
2175 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2177 // If softenSetCCOperands returned a scalar, we need to compare the result
2178 // against zero to select between true and false values.
2179 if (RHS.getNode() == 0) {
2180 RHS = DAG.getConstant(0, LHS.getValueType());
2185 if (LHS.getValueType().isInteger()) {
2188 // Integers are handled in a separate function because the combinations of
2189 // immediates and tests can get hairy and we may want to fiddle things.
2190 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2192 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2193 CmpOp, IfTrue, IfFalse, A64cc);
2196 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2197 // conditional branch, hence FPCCToA64CC can set a second test, where either
2198 // passing is sufficient.
2199 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2200 CondCode = FPCCToA64CC(CC, Alternative);
2201 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2202 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2203 DAG.getCondCode(CC));
2204 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
2206 SetCC, IfTrue, IfFalse, A64cc);
2208 if (Alternative != A64CC::Invalid) {
2209 A64cc = DAG.getConstant(Alternative, MVT::i32);
2210 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2211 SetCC, IfTrue, A64SELECT_CC, A64cc);
2215 return A64SELECT_CC;
2218 // (SELECT testbit, iftrue, iffalse)
2220 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2222 SDValue TheBit = Op.getOperand(0);
2223 SDValue IfTrue = Op.getOperand(1);
2224 SDValue IfFalse = Op.getOperand(2);
2226 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2227 // that as the consumer we are responsible for ignoring rubbish in higher
2229 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2230 DAG.getConstant(1, MVT::i32));
2231 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2232 DAG.getConstant(0, TheBit.getValueType()),
2233 DAG.getCondCode(ISD::SETNE));
2235 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2236 A64CMP, IfTrue, IfFalse,
2237 DAG.getConstant(A64CC::NE, MVT::i32));
2240 // (SETCC lhs, rhs, condcode)
2242 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2244 SDValue LHS = Op.getOperand(0);
2245 SDValue RHS = Op.getOperand(1);
2246 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2247 EVT VT = Op.getValueType();
2249 if (LHS.getValueType() == MVT::f128) {
2250 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
2251 // for the rest of the function (some i32 or i64 values).
2252 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2254 // If softenSetCCOperands returned a scalar, use it.
2255 if (RHS.getNode() == 0) {
2256 assert(LHS.getValueType() == Op.getValueType() &&
2257 "Unexpected setcc expansion!");
2262 if (LHS.getValueType().isInteger()) {
2265 // Integers are handled in a separate function because the combinations of
2266 // immediates and tests can get hairy and we may want to fiddle things.
2267 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2269 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2270 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2274 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2275 // conditional branch, hence FPCCToA64CC can set a second test, where either
2276 // passing is sufficient.
2277 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2278 CondCode = FPCCToA64CC(CC, Alternative);
2279 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2280 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2281 DAG.getCondCode(CC));
2282 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2283 CmpOp, DAG.getConstant(1, VT),
2284 DAG.getConstant(0, VT), A64cc);
2286 if (Alternative != A64CC::Invalid) {
2287 A64cc = DAG.getConstant(Alternative, MVT::i32);
2288 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
2289 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
2292 return A64SELECT_CC;
2296 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2297 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2298 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2300 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
2301 // rather than just 8.
2302 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op),
2303 Op.getOperand(1), Op.getOperand(2),
2304 DAG.getConstant(32, MVT::i32), 8, false, false,
2305 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
2309 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2310 // The layout of the va_list struct is specified in the AArch64 Procedure Call
2311 // Standard, section B.3.
2312 MachineFunction &MF = DAG.getMachineFunction();
2313 AArch64MachineFunctionInfo *FuncInfo
2314 = MF.getInfo<AArch64MachineFunctionInfo>();
2317 SDValue Chain = Op.getOperand(0);
2318 SDValue VAList = Op.getOperand(1);
2319 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2320 SmallVector<SDValue, 4> MemOps;
2322 // void *__stack at offset 0
2323 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
2325 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
2326 MachinePointerInfo(SV), false, false, 0));
2328 // void *__gr_top at offset 8
2329 int GPRSize = FuncInfo->getVariadicGPRSize();
2331 SDValue GRTop, GRTopAddr;
2333 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2334 DAG.getConstant(8, getPointerTy()));
2336 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
2337 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
2338 DAG.getConstant(GPRSize, getPointerTy()));
2340 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
2341 MachinePointerInfo(SV, 8),
2345 // void *__vr_top at offset 16
2346 int FPRSize = FuncInfo->getVariadicFPRSize();
2348 SDValue VRTop, VRTopAddr;
2349 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2350 DAG.getConstant(16, getPointerTy()));
2352 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
2353 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
2354 DAG.getConstant(FPRSize, getPointerTy()));
2356 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
2357 MachinePointerInfo(SV, 16),
2361 // int __gr_offs at offset 24
2362 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2363 DAG.getConstant(24, getPointerTy()));
2364 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
2365 GROffsAddr, MachinePointerInfo(SV, 24),
2368 // int __vr_offs at offset 28
2369 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2370 DAG.getConstant(28, getPointerTy()));
2371 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
2372 VROffsAddr, MachinePointerInfo(SV, 28),
2375 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
2380 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2381 switch (Op.getOpcode()) {
2382 default: llvm_unreachable("Don't know how to custom lower this!");
2383 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
2384 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
2385 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
2386 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
2387 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
2388 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
2389 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
2390 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
2391 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
2392 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
2394 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2395 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
2396 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2397 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
2398 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2399 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2400 case ISD::SELECT: return LowerSELECT(Op, DAG);
2401 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2402 case ISD::SETCC: return LowerSETCC(Op, DAG);
2403 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
2404 case ISD::VASTART: return LowerVASTART(Op, DAG);
2410 static SDValue PerformANDCombine(SDNode *N,
2411 TargetLowering::DAGCombinerInfo &DCI) {
2413 SelectionDAG &DAG = DCI.DAG;
2415 EVT VT = N->getValueType(0);
2417 // We're looking for an SRA/SHL pair which form an SBFX.
2419 if (VT != MVT::i32 && VT != MVT::i64)
2422 if (!isa<ConstantSDNode>(N->getOperand(1)))
2425 uint64_t TruncMask = N->getConstantOperandVal(1);
2426 if (!isMask_64(TruncMask))
2429 uint64_t Width = CountPopulation_64(TruncMask);
2430 SDValue Shift = N->getOperand(0);
2432 if (Shift.getOpcode() != ISD::SRL)
2435 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
2437 uint64_t LSB = Shift->getConstantOperandVal(1);
2439 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
2442 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
2443 DAG.getConstant(LSB, MVT::i64),
2444 DAG.getConstant(LSB + Width - 1, MVT::i64));
2447 /// For a true bitfield insert, the bits getting into that contiguous mask
2448 /// should come from the low part of an existing value: they must be formed from
2449 /// a compatible SHL operation (unless they're already low). This function
2450 /// checks that condition and returns the least-significant bit that's
2451 /// intended. If the operation not a field preparation, -1 is returned.
2452 static int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT,
2453 SDValue &MaskedVal, uint64_t Mask) {
2454 if (!isShiftedMask_64(Mask))
2457 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
2458 // instruction. BFI will do a left-shift by LSB before applying the mask we've
2459 // spotted, so in general we should pre-emptively "undo" that by making sure
2460 // the incoming bits have had a right-shift applied to them.
2462 // This right shift, however, will combine with existing left/right shifts. In
2463 // the simplest case of a completely straight bitfield operation, it will be
2464 // expected to completely cancel out with an existing SHL. More complicated
2465 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
2468 uint64_t LSB = countTrailingZeros(Mask);
2469 int64_t ShiftRightRequired = LSB;
2470 if (MaskedVal.getOpcode() == ISD::SHL &&
2471 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
2472 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
2473 MaskedVal = MaskedVal.getOperand(0);
2474 } else if (MaskedVal.getOpcode() == ISD::SRL &&
2475 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
2476 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
2477 MaskedVal = MaskedVal.getOperand(0);
2480 if (ShiftRightRequired > 0)
2481 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
2482 DAG.getConstant(ShiftRightRequired, MVT::i64));
2483 else if (ShiftRightRequired < 0) {
2484 // We could actually end up with a residual left shift, for example with
2485 // "struc.bitfield = val << 1".
2486 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
2487 DAG.getConstant(-ShiftRightRequired, MVT::i64));
2493 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
2494 /// a mask and an extension. Returns true if a BFI was found and provides
2495 /// information on its surroundings.
2496 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
2499 if (N.getOpcode() == ISD::ZERO_EXTEND) {
2501 N = N.getOperand(0);
2504 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
2505 Mask = N->getConstantOperandVal(1);
2506 N = N.getOperand(0);
2508 // Mask is the whole width.
2509 Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
2512 if (N.getOpcode() == AArch64ISD::BFI) {
2520 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
2521 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
2522 /// can often be further combined with a larger mask. Ultimately, we want mask
2523 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
2524 static SDValue tryCombineToBFI(SDNode *N,
2525 TargetLowering::DAGCombinerInfo &DCI,
2526 const AArch64Subtarget *Subtarget) {
2527 SelectionDAG &DAG = DCI.DAG;
2529 EVT VT = N->getValueType(0);
2531 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2533 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
2534 // abandon the effort.
2535 SDValue LHS = N->getOperand(0);
2536 if (LHS.getOpcode() != ISD::AND)
2540 if (isa<ConstantSDNode>(LHS.getOperand(1)))
2541 LHSMask = LHS->getConstantOperandVal(1);
2545 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
2546 // is or abandon the effort.
2547 SDValue RHS = N->getOperand(1);
2548 if (RHS.getOpcode() != ISD::AND)
2552 if (isa<ConstantSDNode>(RHS.getOperand(1)))
2553 RHSMask = RHS->getConstantOperandVal(1);
2557 // Can't do anything if the masks are incompatible.
2558 if (LHSMask & RHSMask)
2561 // Now we need one of the masks to be a contiguous field. Without loss of
2562 // generality that should be the RHS one.
2563 SDValue Bitfield = LHS.getOperand(0);
2564 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
2565 // We know that LHS is a candidate new value, and RHS isn't already a better
2567 std::swap(LHS, RHS);
2568 std::swap(LHSMask, RHSMask);
2571 // We've done our best to put the right operands in the right places, all we
2572 // can do now is check whether a BFI exists.
2573 Bitfield = RHS.getOperand(0);
2574 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
2578 uint32_t Width = CountPopulation_64(RHSMask);
2579 assert(Width && "Expected non-zero bitfield width");
2581 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
2582 LHS.getOperand(0), Bitfield,
2583 DAG.getConstant(LSB, MVT::i64),
2584 DAG.getConstant(Width, MVT::i64));
2587 if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
2590 return DAG.getNode(ISD::AND, DL, VT, BFI,
2591 DAG.getConstant(LHSMask | RHSMask, VT));
2594 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
2595 /// original input. This is surprisingly common because SROA splits things up
2596 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
2597 /// on the low (say) byte of a word. This is then orred into the rest of the
2598 /// word afterwards.
2600 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
2602 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
2603 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
2605 static SDValue tryCombineToLargerBFI(SDNode *N,
2606 TargetLowering::DAGCombinerInfo &DCI,
2607 const AArch64Subtarget *Subtarget) {
2608 SelectionDAG &DAG = DCI.DAG;
2610 EVT VT = N->getValueType(0);
2612 // First job is to hunt for a MaskedBFI on either the left or right. Swap
2613 // operands if it's actually on the right.
2615 SDValue PossExtraMask;
2616 uint64_t ExistingMask = 0;
2617 bool Extended = false;
2618 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
2619 PossExtraMask = N->getOperand(1);
2620 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
2621 PossExtraMask = N->getOperand(0);
2625 // We can only combine a BFI with another compatible mask.
2626 if (PossExtraMask.getOpcode() != ISD::AND ||
2627 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
2630 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
2632 // Masks must be compatible.
2633 if (ExtraMask & ExistingMask)
2636 SDValue OldBFIVal = BFI.getOperand(0);
2637 SDValue NewBFIVal = BFI.getOperand(1);
2639 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
2640 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
2641 // need to be made compatible.
2642 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
2643 && "Invalid types for BFI");
2644 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
2645 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
2648 // We need the MaskedBFI to be combined with a mask of the *same* value.
2649 if (PossExtraMask.getOperand(0) != OldBFIVal)
2652 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
2653 OldBFIVal, NewBFIVal,
2654 BFI.getOperand(2), BFI.getOperand(3));
2656 // If the masking is trivial, we don't need to create it.
2657 if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
2660 return DAG.getNode(ISD::AND, DL, VT, BFI,
2661 DAG.getConstant(ExtraMask | ExistingMask, VT));
2664 /// An EXTR instruction is made up of two shifts, ORed together. This helper
2665 /// searches for and classifies those shifts.
2666 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
2668 if (N.getOpcode() == ISD::SHL)
2670 else if (N.getOpcode() == ISD::SRL)
2675 if (!isa<ConstantSDNode>(N.getOperand(1)))
2678 ShiftAmount = N->getConstantOperandVal(1);
2679 Src = N->getOperand(0);
2683 /// EXTR instruction extracts a contiguous chunk of bits from two existing
2684 /// registers viewed as a high/low pair. This function looks for the pattern:
2685 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
2686 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
2688 static SDValue tryCombineToEXTR(SDNode *N,
2689 TargetLowering::DAGCombinerInfo &DCI) {
2690 SelectionDAG &DAG = DCI.DAG;
2692 EVT VT = N->getValueType(0);
2694 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2696 if (VT != MVT::i32 && VT != MVT::i64)
2700 uint32_t ShiftLHS = 0;
2702 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
2706 uint32_t ShiftRHS = 0;
2708 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
2711 // If they're both trying to come from the high part of the register, they're
2712 // not really an EXTR.
2713 if (LHSFromHi == RHSFromHi)
2716 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
2720 std::swap(LHS, RHS);
2721 std::swap(ShiftLHS, ShiftRHS);
2724 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
2726 DAG.getConstant(ShiftRHS, MVT::i64));
2729 /// Target-specific dag combine xforms for ISD::OR
2730 static SDValue PerformORCombine(SDNode *N,
2731 TargetLowering::DAGCombinerInfo &DCI,
2732 const AArch64Subtarget *Subtarget) {
2734 SelectionDAG &DAG = DCI.DAG;
2735 EVT VT = N->getValueType(0);
2737 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2740 // Attempt to recognise bitfield-insert operations.
2741 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
2745 // Attempt to combine an existing MaskedBFI operation into one with a larger
2747 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
2751 Res = tryCombineToEXTR(N, DCI);
2758 /// Target-specific dag combine xforms for ISD::SRA
2759 static SDValue PerformSRACombine(SDNode *N,
2760 TargetLowering::DAGCombinerInfo &DCI) {
2762 SelectionDAG &DAG = DCI.DAG;
2764 EVT VT = N->getValueType(0);
2766 // We're looking for an SRA/SHL pair which form an SBFX.
2768 if (VT != MVT::i32 && VT != MVT::i64)
2771 if (!isa<ConstantSDNode>(N->getOperand(1)))
2774 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
2775 SDValue Shift = N->getOperand(0);
2777 if (Shift.getOpcode() != ISD::SHL)
2780 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
2783 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
2784 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
2785 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
2787 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
2790 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
2791 DAG.getConstant(LSB, MVT::i64),
2792 DAG.getConstant(LSB + Width - 1, MVT::i64));
2797 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2798 DAGCombinerInfo &DCI) const {
2799 switch (N->getOpcode()) {
2801 case ISD::AND: return PerformANDCombine(N, DCI);
2802 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
2803 case ISD::SRA: return PerformSRACombine(N, DCI);
2808 AArch64TargetLowering::ConstraintType
2809 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
2810 if (Constraint.size() == 1) {
2811 switch (Constraint[0]) {
2813 case 'w': // An FP/SIMD vector register
2814 return C_RegisterClass;
2815 case 'I': // Constant that can be used with an ADD instruction
2816 case 'J': // Constant that can be used with a SUB instruction
2817 case 'K': // Constant that can be used with a 32-bit logical instruction
2818 case 'L': // Constant that can be used with a 64-bit logical instruction
2819 case 'M': // Constant that can be used as a 32-bit MOV immediate
2820 case 'N': // Constant that can be used as a 64-bit MOV immediate
2821 case 'Y': // Floating point constant zero
2822 case 'Z': // Integer constant zero
2824 case 'Q': // A memory reference with base register and no offset
2826 case 'S': // A symbolic address
2831 // FIXME: Ump, Utf, Usa, Ush
2832 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
2833 // whatever they may be
2834 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
2835 // Usa: An absolute symbolic address
2836 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
2837 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
2838 && Constraint != "Ush" && "Unimplemented constraints");
2840 return TargetLowering::getConstraintType(Constraint);
2843 TargetLowering::ConstraintWeight
2844 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
2845 const char *Constraint) const {
2847 llvm_unreachable("Constraint weight unimplemented");
2851 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2852 std::string &Constraint,
2853 std::vector<SDValue> &Ops,
2854 SelectionDAG &DAG) const {
2855 SDValue Result(0, 0);
2857 // Only length 1 constraints are C_Other.
2858 if (Constraint.size() != 1) return;
2860 // Only C_Other constraints get lowered like this. That means constants for us
2861 // so return early if there's no hope the constraint can be lowered.
2863 switch(Constraint[0]) {
2865 case 'I': case 'J': case 'K': case 'L':
2866 case 'M': case 'N': case 'Z': {
2867 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2871 uint64_t CVal = C->getZExtValue();
2874 switch (Constraint[0]) {
2876 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
2877 // is a peculiarly useless SUB constraint.
2878 llvm_unreachable("Unimplemented C_Other constraint");
2884 if (A64Imms::isLogicalImm(32, CVal, Bits))
2888 if (A64Imms::isLogicalImm(64, CVal, Bits))
2897 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2901 // An absolute symbolic address or label reference.
2902 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
2903 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
2904 GA->getValueType(0));
2905 } else if (const BlockAddressSDNode *BA
2906 = dyn_cast<BlockAddressSDNode>(Op)) {
2907 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
2908 BA->getValueType(0));
2909 } else if (const ExternalSymbolSDNode *ES
2910 = dyn_cast<ExternalSymbolSDNode>(Op)) {
2911 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
2912 ES->getValueType(0));
2918 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2919 if (CFP->isExactlyValue(0.0)) {
2920 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
2927 if (Result.getNode()) {
2928 Ops.push_back(Result);
2932 // It's an unknown constraint for us. Let generic code have a go.
2933 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2936 std::pair<unsigned, const TargetRegisterClass*>
2937 AArch64TargetLowering::getRegForInlineAsmConstraint(
2938 const std::string &Constraint,
2940 if (Constraint.size() == 1) {
2941 switch (Constraint[0]) {
2943 if (VT.getSizeInBits() <= 32)
2944 return std::make_pair(0U, &AArch64::GPR32RegClass);
2945 else if (VT == MVT::i64)
2946 return std::make_pair(0U, &AArch64::GPR64RegClass);
2950 return std::make_pair(0U, &AArch64::FPR16RegClass);
2951 else if (VT == MVT::f32)
2952 return std::make_pair(0U, &AArch64::FPR32RegClass);
2953 else if (VT == MVT::f64)
2954 return std::make_pair(0U, &AArch64::FPR64RegClass);
2955 else if (VT.getSizeInBits() == 64)
2956 return std::make_pair(0U, &AArch64::VPR64RegClass);
2957 else if (VT == MVT::f128)
2958 return std::make_pair(0U, &AArch64::FPR128RegClass);
2959 else if (VT.getSizeInBits() == 128)
2960 return std::make_pair(0U, &AArch64::VPR128RegClass);
2965 // Use the default implementation in TargetLowering to convert the register
2966 // constraint into a member of a register class.
2967 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);