1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is a storage-only type, always promote it to f32.
285 setOperationAction(ISD::SETCC, MVT::f16, Promote);
286 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
287 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT, MVT::f16, Promote);
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FSUB, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FDIV, MVT::f16, Promote);
293 setOperationAction(ISD::FREM, MVT::f16, Promote);
294 setOperationAction(ISD::FMA, MVT::f16, Promote);
295 setOperationAction(ISD::FNEG, MVT::f16, Promote);
296 setOperationAction(ISD::FABS, MVT::f16, Promote);
297 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
298 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
299 setOperationAction(ISD::FCOS, MVT::f16, Promote);
300 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
301 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
302 setOperationAction(ISD::FPOW, MVT::f16, Promote);
303 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
304 setOperationAction(ISD::FRINT, MVT::f16, Promote);
305 setOperationAction(ISD::FSIN, MVT::f16, Promote);
306 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
307 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
308 setOperationAction(ISD::FEXP, MVT::f16, Promote);
309 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
310 setOperationAction(ISD::FLOG, MVT::f16, Promote);
311 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
312 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
313 setOperationAction(ISD::FROUND, MVT::f16, Promote);
314 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
315 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
316 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
318 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
320 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
321 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
322 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
323 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
324 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
325 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
326 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
327 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
333 // Expand all other v4f16 operations.
334 // FIXME: We could generate better code by promoting some operations to
336 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
337 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
338 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
339 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
340 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
341 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
342 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
343 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
344 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
345 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
346 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
347 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
348 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
349 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
350 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
351 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
352 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
353 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
354 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
355 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
356 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
357 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
358 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
359 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
360 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
361 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
364 // v8f16 is also a storage-only type, so expand it.
365 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
366 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
367 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
368 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
371 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
372 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
373 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
374 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
375 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
376 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
377 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
378 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
379 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
380 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
381 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
382 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
383 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
384 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
385 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
386 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
387 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
388 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
389 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
390 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
391 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
392 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
393 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
394 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
395 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
397 // AArch64 has implementations of a lot of rounding-like FP operations.
398 for (MVT Ty : {MVT::f32, MVT::f64}) {
399 setOperationAction(ISD::FFLOOR, Ty, Legal);
400 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
401 setOperationAction(ISD::FCEIL, Ty, Legal);
402 setOperationAction(ISD::FRINT, Ty, Legal);
403 setOperationAction(ISD::FTRUNC, Ty, Legal);
404 setOperationAction(ISD::FROUND, Ty, Legal);
407 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
409 if (Subtarget->isTargetMachO()) {
410 // For iOS, we don't want to the normal expansion of a libcall to
411 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
413 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
414 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
416 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
420 // Make floating-point constants legal for the large code model, so they don't
421 // become loads from the constant pool.
422 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
423 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
424 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
427 // AArch64 does not have floating-point extending loads, i1 sign-extending
428 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
429 for (MVT VT : MVT::fp_valuetypes()) {
430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
435 for (MVT VT : MVT::integer_valuetypes())
436 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
438 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
439 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
440 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
441 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
443 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
444 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
446 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
447 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
449 // Indexed loads and stores are supported.
450 for (unsigned im = (unsigned)ISD::PRE_INC;
451 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
452 setIndexedLoadAction(im, MVT::i8, Legal);
453 setIndexedLoadAction(im, MVT::i16, Legal);
454 setIndexedLoadAction(im, MVT::i32, Legal);
455 setIndexedLoadAction(im, MVT::i64, Legal);
456 setIndexedLoadAction(im, MVT::f64, Legal);
457 setIndexedLoadAction(im, MVT::f32, Legal);
458 setIndexedStoreAction(im, MVT::i8, Legal);
459 setIndexedStoreAction(im, MVT::i16, Legal);
460 setIndexedStoreAction(im, MVT::i32, Legal);
461 setIndexedStoreAction(im, MVT::i64, Legal);
462 setIndexedStoreAction(im, MVT::f64, Legal);
463 setIndexedStoreAction(im, MVT::f32, Legal);
467 setOperationAction(ISD::TRAP, MVT::Other, Legal);
469 // We combine OR nodes for bitfield operations.
470 setTargetDAGCombine(ISD::OR);
472 // Vector add and sub nodes may conceal a high-half opportunity.
473 // Also, try to fold ADD into CSINC/CSINV..
474 setTargetDAGCombine(ISD::ADD);
475 setTargetDAGCombine(ISD::SUB);
477 setTargetDAGCombine(ISD::XOR);
478 setTargetDAGCombine(ISD::SINT_TO_FP);
479 setTargetDAGCombine(ISD::UINT_TO_FP);
481 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
483 setTargetDAGCombine(ISD::ANY_EXTEND);
484 setTargetDAGCombine(ISD::ZERO_EXTEND);
485 setTargetDAGCombine(ISD::SIGN_EXTEND);
486 setTargetDAGCombine(ISD::BITCAST);
487 setTargetDAGCombine(ISD::CONCAT_VECTORS);
488 setTargetDAGCombine(ISD::STORE);
490 setTargetDAGCombine(ISD::MUL);
492 setTargetDAGCombine(ISD::SELECT);
493 setTargetDAGCombine(ISD::VSELECT);
495 setTargetDAGCombine(ISD::INTRINSIC_VOID);
496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
497 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
499 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
500 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
501 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
503 setStackPointerRegisterToSaveRestore(AArch64::SP);
505 setSchedulingPreference(Sched::Hybrid);
508 MaskAndBranchFoldingIsLegal = true;
509 EnableExtLdPromotion = true;
511 setMinFunctionAlignment(2);
513 RequireStrictAlign = (Align == StrictAlign);
515 setHasExtractBitsInsn(true);
517 if (Subtarget->hasNEON()) {
518 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
519 // silliness like this:
520 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
521 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
522 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
523 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
524 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
525 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
526 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
527 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
528 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
529 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
530 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
531 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
532 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
533 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
534 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
535 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
536 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
537 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
538 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
539 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
540 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
541 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
542 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
543 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
544 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
546 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
547 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
548 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
549 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
550 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
552 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
554 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
555 // elements smaller than i32, so promote the input to i32 first.
556 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
557 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
560 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
561 // -> v8f16 conversions.
562 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
563 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
564 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
565 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
566 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
567 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
568 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
569 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
570 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
571 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
572 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
573 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
574 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
576 // AArch64 doesn't have MUL.2d:
577 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
578 // Custom handling for some quad-vector types to detect MULL.
579 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
580 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
581 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
583 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
584 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
585 // Likewise, narrowing and extending vector loads/stores aren't handled
587 for (MVT VT : MVT::vector_valuetypes()) {
588 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
590 setOperationAction(ISD::MULHS, VT, Expand);
591 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
592 setOperationAction(ISD::MULHU, VT, Expand);
593 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
595 setOperationAction(ISD::BSWAP, VT, Expand);
597 for (MVT InnerVT : MVT::vector_valuetypes()) {
598 setTruncStoreAction(VT, InnerVT, Expand);
599 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
600 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
601 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
605 // AArch64 has implementations of a lot of rounding-like FP operations.
606 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
607 setOperationAction(ISD::FFLOOR, Ty, Legal);
608 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
609 setOperationAction(ISD::FCEIL, Ty, Legal);
610 setOperationAction(ISD::FRINT, Ty, Legal);
611 setOperationAction(ISD::FTRUNC, Ty, Legal);
612 setOperationAction(ISD::FROUND, Ty, Legal);
616 // Prefer likely predicted branches to selects on out-of-order cores.
617 if (Subtarget->isCortexA57())
618 PredictableSelectIsExpensive = true;
621 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
622 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
623 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
624 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
626 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
627 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
628 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
629 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
630 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
632 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
633 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
636 // Mark vector float intrinsics as expand.
637 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
638 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
639 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
640 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
645 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
649 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
650 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
651 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
652 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
653 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
654 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
655 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
656 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
662 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
663 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
664 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
665 for (MVT InnerVT : MVT::all_valuetypes())
666 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
668 // CNT supports only B element sizes.
669 if (VT != MVT::v8i8 && VT != MVT::v16i8)
670 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
672 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
673 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
674 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
675 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
676 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
678 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
679 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
681 if (Subtarget->isLittleEndian()) {
682 for (unsigned im = (unsigned)ISD::PRE_INC;
683 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
684 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
685 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
690 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
691 addRegisterClass(VT, &AArch64::FPR64RegClass);
692 addTypeForNEON(VT, MVT::v2i32);
695 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
696 addRegisterClass(VT, &AArch64::FPR128RegClass);
697 addTypeForNEON(VT, MVT::v4i32);
700 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
703 return VT.changeVectorElementTypeToInteger();
706 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
707 /// Mask are known to be either zero or one and return them in the
708 /// KnownZero/KnownOne bitsets.
709 void AArch64TargetLowering::computeKnownBitsForTargetNode(
710 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
711 const SelectionDAG &DAG, unsigned Depth) const {
712 switch (Op.getOpcode()) {
715 case AArch64ISD::CSEL: {
716 APInt KnownZero2, KnownOne2;
717 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
718 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
719 KnownZero &= KnownZero2;
720 KnownOne &= KnownOne2;
723 case ISD::INTRINSIC_W_CHAIN: {
724 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
725 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
728 case Intrinsic::aarch64_ldaxr:
729 case Intrinsic::aarch64_ldxr: {
730 unsigned BitWidth = KnownOne.getBitWidth();
731 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
732 unsigned MemBits = VT.getScalarType().getSizeInBits();
733 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
739 case ISD::INTRINSIC_WO_CHAIN:
740 case ISD::INTRINSIC_VOID: {
741 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
745 case Intrinsic::aarch64_neon_umaxv:
746 case Intrinsic::aarch64_neon_uminv: {
747 // Figure out the datatype of the vector operand. The UMINV instruction
748 // will zero extend the result, so we can mark as known zero all the
749 // bits larger than the element datatype. 32-bit or larget doesn't need
750 // this as those are legal types and will be handled by isel directly.
751 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
752 unsigned BitWidth = KnownZero.getBitWidth();
753 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
754 assert(BitWidth >= 8 && "Unexpected width!");
755 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
757 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
758 assert(BitWidth >= 16 && "Unexpected width!");
759 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
769 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
774 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
775 const TargetLibraryInfo *libInfo) const {
776 return AArch64::createFastISel(funcInfo, libInfo);
779 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
783 case AArch64ISD::CALL: return "AArch64ISD::CALL";
784 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
785 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
786 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
787 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
788 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
789 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
790 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
791 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
792 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
793 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
794 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
795 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
796 case AArch64ISD::ADC: return "AArch64ISD::ADC";
797 case AArch64ISD::SBC: return "AArch64ISD::SBC";
798 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
799 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
800 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
801 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
802 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
803 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
804 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
805 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
806 case AArch64ISD::DUP: return "AArch64ISD::DUP";
807 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
808 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
809 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
810 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
811 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
812 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
813 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
814 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
815 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
816 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
817 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
818 case AArch64ISD::BICi: return "AArch64ISD::BICi";
819 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
820 case AArch64ISD::BSL: return "AArch64ISD::BSL";
821 case AArch64ISD::NEG: return "AArch64ISD::NEG";
822 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
823 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
824 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
825 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
826 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
827 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
828 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
829 case AArch64ISD::REV16: return "AArch64ISD::REV16";
830 case AArch64ISD::REV32: return "AArch64ISD::REV32";
831 case AArch64ISD::REV64: return "AArch64ISD::REV64";
832 case AArch64ISD::EXT: return "AArch64ISD::EXT";
833 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
834 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
835 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
836 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
837 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
838 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
839 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
840 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
841 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
842 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
843 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
844 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
845 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
846 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
847 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
848 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
849 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
850 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
851 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
852 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
853 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
854 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
855 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
856 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
857 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
858 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
859 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
860 case AArch64ISD::NOT: return "AArch64ISD::NOT";
861 case AArch64ISD::BIT: return "AArch64ISD::BIT";
862 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
863 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
864 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
865 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
866 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
867 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
868 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
869 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
870 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
871 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
872 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
873 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
874 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
875 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
876 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
877 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
878 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
879 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
880 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
881 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
882 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
883 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
884 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
885 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
886 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
887 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
888 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
889 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
890 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
891 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
892 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
893 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
894 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
895 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
896 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
897 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
898 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
899 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
900 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
905 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
906 MachineBasicBlock *MBB) const {
907 // We materialise the F128CSEL pseudo-instruction as some control flow and a
911 // [... previous instrs leading to comparison ...]
917 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
919 MachineFunction *MF = MBB->getParent();
920 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
921 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
922 DebugLoc DL = MI->getDebugLoc();
923 MachineFunction::iterator It = MBB;
926 unsigned DestReg = MI->getOperand(0).getReg();
927 unsigned IfTrueReg = MI->getOperand(1).getReg();
928 unsigned IfFalseReg = MI->getOperand(2).getReg();
929 unsigned CondCode = MI->getOperand(3).getImm();
930 bool NZCVKilled = MI->getOperand(4).isKill();
932 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
933 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
934 MF->insert(It, TrueBB);
935 MF->insert(It, EndBB);
937 // Transfer rest of current basic-block to EndBB
938 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
940 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
942 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
943 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
944 MBB->addSuccessor(TrueBB);
945 MBB->addSuccessor(EndBB);
947 // TrueBB falls through to the end.
948 TrueBB->addSuccessor(EndBB);
951 TrueBB->addLiveIn(AArch64::NZCV);
952 EndBB->addLiveIn(AArch64::NZCV);
955 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
961 MI->eraseFromParent();
966 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
967 MachineBasicBlock *BB) const {
968 switch (MI->getOpcode()) {
973 llvm_unreachable("Unexpected instruction for custom inserter!");
975 case AArch64::F128CSEL:
976 return EmitF128CSEL(MI, BB);
978 case TargetOpcode::STACKMAP:
979 case TargetOpcode::PATCHPOINT:
980 return emitPatchPoint(MI, BB);
984 //===----------------------------------------------------------------------===//
985 // AArch64 Lowering private implementation.
986 //===----------------------------------------------------------------------===//
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
992 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
994 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
997 llvm_unreachable("Unknown condition code!");
999 return AArch64CC::NE;
1001 return AArch64CC::EQ;
1003 return AArch64CC::GT;
1005 return AArch64CC::GE;
1007 return AArch64CC::LT;
1009 return AArch64CC::LE;
1011 return AArch64CC::HI;
1013 return AArch64CC::HS;
1015 return AArch64CC::LO;
1017 return AArch64CC::LS;
1021 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1022 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1023 AArch64CC::CondCode &CondCode,
1024 AArch64CC::CondCode &CondCode2) {
1025 CondCode2 = AArch64CC::AL;
1028 llvm_unreachable("Unknown FP condition!");
1031 CondCode = AArch64CC::EQ;
1035 CondCode = AArch64CC::GT;
1039 CondCode = AArch64CC::GE;
1042 CondCode = AArch64CC::MI;
1045 CondCode = AArch64CC::LS;
1048 CondCode = AArch64CC::MI;
1049 CondCode2 = AArch64CC::GT;
1052 CondCode = AArch64CC::VC;
1055 CondCode = AArch64CC::VS;
1058 CondCode = AArch64CC::EQ;
1059 CondCode2 = AArch64CC::VS;
1062 CondCode = AArch64CC::HI;
1065 CondCode = AArch64CC::PL;
1069 CondCode = AArch64CC::LT;
1073 CondCode = AArch64CC::LE;
1077 CondCode = AArch64CC::NE;
1082 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1083 /// CC usable with the vector instructions. Fewer operations are available
1084 /// without a real NZCV register, so we have to use less efficient combinations
1085 /// to get the same effect.
1086 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1087 AArch64CC::CondCode &CondCode,
1088 AArch64CC::CondCode &CondCode2,
1093 // Mostly the scalar mappings work fine.
1094 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1097 Invert = true; // Fallthrough
1099 CondCode = AArch64CC::MI;
1100 CondCode2 = AArch64CC::GE;
1107 // All of the compare-mask comparisons are ordered, but we can switch
1108 // between the two by a double inversion. E.g. ULE == !OGT.
1110 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1115 static bool isLegalArithImmed(uint64_t C) {
1116 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1117 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1120 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1121 SDLoc dl, SelectionDAG &DAG) {
1122 EVT VT = LHS.getValueType();
1124 if (VT.isFloatingPoint())
1125 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1127 // The CMP instruction is just an alias for SUBS, and representing it as
1128 // SUBS means that it's possible to get CSE with subtract operations.
1129 // A later phase can perform the optimization of setting the destination
1130 // register to WZR/XZR if it ends up being unused.
1131 unsigned Opcode = AArch64ISD::SUBS;
1133 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1134 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1135 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1136 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1137 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1138 // can be set differently by this operation. It comes down to whether
1139 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1140 // everything is fine. If not then the optimization is wrong. Thus general
1141 // comparisons are only valid if op2 != 0.
1143 // So, finally, the only LLVM-native comparisons that don't mention C and V
1144 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1145 // the absence of information about op2.
1146 Opcode = AArch64ISD::ADDS;
1147 RHS = RHS.getOperand(1);
1148 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1149 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1150 !isUnsignedIntSetCC(CC)) {
1151 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1152 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1153 // of the signed comparisons.
1154 Opcode = AArch64ISD::ANDS;
1155 RHS = LHS.getOperand(1);
1156 LHS = LHS.getOperand(0);
1159 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1163 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1164 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1166 AArch64CC::CondCode AArch64CC;
1167 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1168 EVT VT = RHS.getValueType();
1169 uint64_t C = RHSC->getZExtValue();
1170 if (!isLegalArithImmed(C)) {
1171 // Constant does not fit, try adjusting it by one?
1177 if ((VT == MVT::i32 && C != 0x80000000 &&
1178 isLegalArithImmed((uint32_t)(C - 1))) ||
1179 (VT == MVT::i64 && C != 0x80000000ULL &&
1180 isLegalArithImmed(C - 1ULL))) {
1181 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1182 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1183 RHS = DAG.getConstant(C, dl, VT);
1188 if ((VT == MVT::i32 && C != 0 &&
1189 isLegalArithImmed((uint32_t)(C - 1))) ||
1190 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1191 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1192 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1193 RHS = DAG.getConstant(C, dl, VT);
1198 if ((VT == MVT::i32 && C != INT32_MAX &&
1199 isLegalArithImmed((uint32_t)(C + 1))) ||
1200 (VT == MVT::i64 && C != INT64_MAX &&
1201 isLegalArithImmed(C + 1ULL))) {
1202 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1203 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1204 RHS = DAG.getConstant(C, dl, VT);
1209 if ((VT == MVT::i32 && C != UINT32_MAX &&
1210 isLegalArithImmed((uint32_t)(C + 1))) ||
1211 (VT == MVT::i64 && C != UINT64_MAX &&
1212 isLegalArithImmed(C + 1ULL))) {
1213 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1214 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1215 RHS = DAG.getConstant(C, dl, VT);
1221 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1222 // For the i8 operand, the largest immediate is 255, so this can be easily
1223 // encoded in the compare instruction. For the i16 operand, however, the
1224 // largest immediate cannot be encoded in the compare.
1225 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1226 // constant. For example,
1228 // ldrh w0, [x0, #0]
1231 // ldrsh w0, [x0, #0]
1233 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1234 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1235 // both the LHS and RHS are truely zero extended and to make sure the
1236 // transformation is profitable.
1237 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1238 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1239 isa<LoadSDNode>(LHS)) {
1240 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1241 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1242 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1243 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1244 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1246 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1247 DAG.getValueType(MVT::i16));
1248 Cmp = emitComparison(SExt,
1249 DAG.getConstant(ValueofRHS, dl,
1250 RHS.getValueType()),
1252 AArch64CC = changeIntCCToAArch64CC(CC);
1253 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1259 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1260 AArch64CC = changeIntCCToAArch64CC(CC);
1261 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1265 static std::pair<SDValue, SDValue>
1266 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1267 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1268 "Unsupported value type");
1269 SDValue Value, Overflow;
1271 SDValue LHS = Op.getOperand(0);
1272 SDValue RHS = Op.getOperand(1);
1274 switch (Op.getOpcode()) {
1276 llvm_unreachable("Unknown overflow instruction!");
1278 Opc = AArch64ISD::ADDS;
1282 Opc = AArch64ISD::ADDS;
1286 Opc = AArch64ISD::SUBS;
1290 Opc = AArch64ISD::SUBS;
1293 // Multiply needs a little bit extra work.
1297 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1298 if (Op.getValueType() == MVT::i32) {
1299 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1300 // For a 32 bit multiply with overflow check we want the instruction
1301 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1302 // need to generate the following pattern:
1303 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1304 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1305 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1306 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1307 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1308 DAG.getConstant(0, DL, MVT::i64));
1309 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1310 // operation. We need to clear out the upper 32 bits, because we used a
1311 // widening multiply that wrote all 64 bits. In the end this should be a
1313 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1315 // The signed overflow check requires more than just a simple check for
1316 // any bit set in the upper 32 bits of the result. These bits could be
1317 // just the sign bits of a negative number. To perform the overflow
1318 // check we have to arithmetic shift right the 32nd bit of the result by
1319 // 31 bits. Then we compare the result to the upper 32 bits.
1320 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1321 DAG.getConstant(32, DL, MVT::i64));
1322 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1323 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1324 DAG.getConstant(31, DL, MVT::i64));
1325 // It is important that LowerBits is last, otherwise the arithmetic
1326 // shift will not be folded into the compare (SUBS).
1327 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1328 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1331 // The overflow check for unsigned multiply is easy. We only need to
1332 // check if any of the upper 32 bits are set. This can be done with a
1333 // CMP (shifted register). For that we need to generate the following
1335 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1336 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1337 DAG.getConstant(32, DL, MVT::i64));
1338 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1340 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1341 DAG.getConstant(0, DL, MVT::i64),
1342 UpperBits).getValue(1);
1346 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1347 // For the 64 bit multiply
1348 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1350 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1351 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1352 DAG.getConstant(63, DL, MVT::i64));
1353 // It is important that LowerBits is last, otherwise the arithmetic
1354 // shift will not be folded into the compare (SUBS).
1355 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1356 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1359 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1360 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1362 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1363 DAG.getConstant(0, DL, MVT::i64),
1364 UpperBits).getValue(1);
1371 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1373 // Emit the AArch64 operation with overflow check.
1374 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1375 Overflow = Value.getValue(1);
1377 return std::make_pair(Value, Overflow);
1380 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1381 RTLIB::Libcall Call) const {
1382 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1383 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1387 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1388 SDValue Sel = Op.getOperand(0);
1389 SDValue Other = Op.getOperand(1);
1391 // If neither operand is a SELECT_CC, give up.
1392 if (Sel.getOpcode() != ISD::SELECT_CC)
1393 std::swap(Sel, Other);
1394 if (Sel.getOpcode() != ISD::SELECT_CC)
1397 // The folding we want to perform is:
1398 // (xor x, (select_cc a, b, cc, 0, -1) )
1400 // (csel x, (xor x, -1), cc ...)
1402 // The latter will get matched to a CSINV instruction.
1404 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1405 SDValue LHS = Sel.getOperand(0);
1406 SDValue RHS = Sel.getOperand(1);
1407 SDValue TVal = Sel.getOperand(2);
1408 SDValue FVal = Sel.getOperand(3);
1411 // FIXME: This could be generalized to non-integer comparisons.
1412 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1415 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1416 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1418 // The the values aren't constants, this isn't the pattern we're looking for.
1419 if (!CFVal || !CTVal)
1422 // We can commute the SELECT_CC by inverting the condition. This
1423 // might be needed to make this fit into a CSINV pattern.
1424 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1425 std::swap(TVal, FVal);
1426 std::swap(CTVal, CFVal);
1427 CC = ISD::getSetCCInverse(CC, true);
1430 // If the constants line up, perform the transform!
1431 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1433 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1436 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1437 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1439 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1446 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1447 EVT VT = Op.getValueType();
1449 // Let legalize expand this if it isn't a legal type yet.
1450 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1453 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1456 bool ExtraOp = false;
1457 switch (Op.getOpcode()) {
1459 llvm_unreachable("Invalid code");
1461 Opc = AArch64ISD::ADDS;
1464 Opc = AArch64ISD::SUBS;
1467 Opc = AArch64ISD::ADCS;
1471 Opc = AArch64ISD::SBCS;
1477 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1478 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1482 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1483 // Let legalize expand this if it isn't a legal type yet.
1484 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1488 AArch64CC::CondCode CC;
1489 // The actual operation that sets the overflow or carry flag.
1490 SDValue Value, Overflow;
1491 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1493 // We use 0 and 1 as false and true values.
1494 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1495 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1497 // We use an inverted condition, because the conditional select is inverted
1498 // too. This will allow it to be selected to a single instruction:
1499 // CSINC Wd, WZR, WZR, invert(cond).
1500 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1501 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1504 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1505 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1508 // Prefetch operands are:
1509 // 1: Address to prefetch
1511 // 3: int locality (0 = no locality ... 3 = extreme locality)
1512 // 4: bool isDataCache
1513 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1515 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1516 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1517 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1519 bool IsStream = !Locality;
1520 // When the locality number is set
1522 // The front-end should have filtered out the out-of-range values
1523 assert(Locality <= 3 && "Prefetch locality out-of-range");
1524 // The locality degree is the opposite of the cache speed.
1525 // Put the number the other way around.
1526 // The encoding starts at 0 for level 1
1527 Locality = 3 - Locality;
1530 // built the mask value encoding the expected behavior.
1531 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1532 (!IsData << 3) | // IsDataCache bit
1533 (Locality << 1) | // Cache level bits
1534 (unsigned)IsStream; // Stream bit
1535 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1536 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1539 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1540 SelectionDAG &DAG) const {
1541 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1544 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1546 return LowerF128Call(Op, DAG, LC);
1549 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1550 SelectionDAG &DAG) const {
1551 if (Op.getOperand(0).getValueType() != MVT::f128) {
1552 // It's legal except when f128 is involved
1557 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1559 // FP_ROUND node has a second operand indicating whether it is known to be
1560 // precise. That doesn't take part in the LibCall so we can't directly use
1562 SDValue SrcVal = Op.getOperand(0);
1563 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1564 /*isSigned*/ false, SDLoc(Op)).first;
1567 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1568 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1569 // Any additional optimization in this function should be recorded
1570 // in the cost tables.
1571 EVT InVT = Op.getOperand(0).getValueType();
1572 EVT VT = Op.getValueType();
1574 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1577 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1579 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1582 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1585 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1586 VT.getVectorNumElements());
1587 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1588 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1591 // Type changing conversions are illegal.
1595 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1596 SelectionDAG &DAG) const {
1597 if (Op.getOperand(0).getValueType().isVector())
1598 return LowerVectorFP_TO_INT(Op, DAG);
1600 // f16 conversions are promoted to f32.
1601 if (Op.getOperand(0).getValueType() == MVT::f16) {
1604 Op.getOpcode(), dl, Op.getValueType(),
1605 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1608 if (Op.getOperand(0).getValueType() != MVT::f128) {
1609 // It's legal except when f128 is involved
1614 if (Op.getOpcode() == ISD::FP_TO_SINT)
1615 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1617 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1619 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1620 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1624 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1625 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1626 // Any additional optimization in this function should be recorded
1627 // in the cost tables.
1628 EVT VT = Op.getValueType();
1630 SDValue In = Op.getOperand(0);
1631 EVT InVT = In.getValueType();
1633 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1635 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1636 InVT.getVectorNumElements());
1637 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1638 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1641 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1643 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1644 EVT CastVT = VT.changeVectorElementTypeToInteger();
1645 In = DAG.getNode(CastOpc, dl, CastVT, In);
1646 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1652 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1653 SelectionDAG &DAG) const {
1654 if (Op.getValueType().isVector())
1655 return LowerVectorINT_TO_FP(Op, DAG);
1657 // f16 conversions are promoted to f32.
1658 if (Op.getValueType() == MVT::f16) {
1661 ISD::FP_ROUND, dl, MVT::f16,
1662 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1663 DAG.getIntPtrConstant(0, dl));
1666 // i128 conversions are libcalls.
1667 if (Op.getOperand(0).getValueType() == MVT::i128)
1670 // Other conversions are legal, unless it's to the completely software-based
1672 if (Op.getValueType() != MVT::f128)
1676 if (Op.getOpcode() == ISD::SINT_TO_FP)
1677 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1679 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1681 return LowerF128Call(Op, DAG, LC);
1684 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1685 SelectionDAG &DAG) const {
1686 // For iOS, we want to call an alternative entry point: __sincos_stret,
1687 // which returns the values in two S / D registers.
1689 SDValue Arg = Op.getOperand(0);
1690 EVT ArgVT = Arg.getValueType();
1691 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1698 Entry.isSExt = false;
1699 Entry.isZExt = false;
1700 Args.push_back(Entry);
1702 const char *LibcallName =
1703 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1704 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1706 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1707 TargetLowering::CallLoweringInfo CLI(DAG);
1708 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1709 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1711 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1712 return CallResult.first;
1715 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1716 if (Op.getValueType() != MVT::f16)
1719 assert(Op.getOperand(0).getValueType() == MVT::i16);
1722 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1723 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1725 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1726 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1730 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1731 if (OrigVT.getSizeInBits() >= 64)
1734 assert(OrigVT.isSimple() && "Expecting a simple value type");
1736 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1737 switch (OrigSimpleTy) {
1738 default: llvm_unreachable("Unexpected Vector Type");
1747 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1750 unsigned ExtOpcode) {
1751 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1752 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1753 // 64-bits we need to insert a new extension so that it will be 64-bits.
1754 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1755 if (OrigTy.getSizeInBits() >= 64)
1758 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1759 EVT NewVT = getExtensionTo64Bits(OrigTy);
1761 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1764 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1766 EVT VT = N->getValueType(0);
1768 if (N->getOpcode() != ISD::BUILD_VECTOR)
1771 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1772 SDNode *Elt = N->getOperand(i).getNode();
1773 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1774 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1775 unsigned HalfSize = EltSize / 2;
1777 if (!isIntN(HalfSize, C->getSExtValue()))
1780 if (!isUIntN(HalfSize, C->getZExtValue()))
1791 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1792 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1793 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1794 N->getOperand(0)->getValueType(0),
1798 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1799 EVT VT = N->getValueType(0);
1801 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1802 unsigned NumElts = VT.getVectorNumElements();
1803 MVT TruncVT = MVT::getIntegerVT(EltSize);
1804 SmallVector<SDValue, 8> Ops;
1805 for (unsigned i = 0; i != NumElts; ++i) {
1806 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1807 const APInt &CInt = C->getAPIntValue();
1808 // Element types smaller than 32 bits are not legal, so use i32 elements.
1809 // The values are implicitly truncated so sext vs. zext doesn't matter.
1810 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
1812 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1813 MVT::getVectorVT(TruncVT, NumElts), Ops);
1816 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1817 if (N->getOpcode() == ISD::SIGN_EXTEND)
1819 if (isExtendedBUILD_VECTOR(N, DAG, true))
1824 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1825 if (N->getOpcode() == ISD::ZERO_EXTEND)
1827 if (isExtendedBUILD_VECTOR(N, DAG, false))
1832 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1833 unsigned Opcode = N->getOpcode();
1834 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1835 SDNode *N0 = N->getOperand(0).getNode();
1836 SDNode *N1 = N->getOperand(1).getNode();
1837 return N0->hasOneUse() && N1->hasOneUse() &&
1838 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1843 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1844 unsigned Opcode = N->getOpcode();
1845 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1846 SDNode *N0 = N->getOperand(0).getNode();
1847 SDNode *N1 = N->getOperand(1).getNode();
1848 return N0->hasOneUse() && N1->hasOneUse() &&
1849 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1854 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1855 // Multiplications are only custom-lowered for 128-bit vectors so that
1856 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1857 EVT VT = Op.getValueType();
1858 assert(VT.is128BitVector() && VT.isInteger() &&
1859 "unexpected type for custom-lowering ISD::MUL");
1860 SDNode *N0 = Op.getOperand(0).getNode();
1861 SDNode *N1 = Op.getOperand(1).getNode();
1862 unsigned NewOpc = 0;
1864 bool isN0SExt = isSignExtended(N0, DAG);
1865 bool isN1SExt = isSignExtended(N1, DAG);
1866 if (isN0SExt && isN1SExt)
1867 NewOpc = AArch64ISD::SMULL;
1869 bool isN0ZExt = isZeroExtended(N0, DAG);
1870 bool isN1ZExt = isZeroExtended(N1, DAG);
1871 if (isN0ZExt && isN1ZExt)
1872 NewOpc = AArch64ISD::UMULL;
1873 else if (isN1SExt || isN1ZExt) {
1874 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1875 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1876 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1877 NewOpc = AArch64ISD::SMULL;
1879 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1880 NewOpc = AArch64ISD::UMULL;
1882 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1884 NewOpc = AArch64ISD::UMULL;
1890 if (VT == MVT::v2i64)
1891 // Fall through to expand this. It is not legal.
1894 // Other vector multiplications are legal.
1899 // Legalize to a S/UMULL instruction
1902 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1904 Op0 = skipExtensionForVectorMULL(N0, DAG);
1905 assert(Op0.getValueType().is64BitVector() &&
1906 Op1.getValueType().is64BitVector() &&
1907 "unexpected types for extended operands to VMULL");
1908 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1910 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1911 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1912 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1913 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1914 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1915 EVT Op1VT = Op1.getValueType();
1916 return DAG.getNode(N0->getOpcode(), DL, VT,
1917 DAG.getNode(NewOpc, DL, VT,
1918 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1919 DAG.getNode(NewOpc, DL, VT,
1920 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1923 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1924 SelectionDAG &DAG) const {
1925 switch (Op.getOpcode()) {
1927 llvm_unreachable("unimplemented operand");
1930 return LowerBITCAST(Op, DAG);
1931 case ISD::GlobalAddress:
1932 return LowerGlobalAddress(Op, DAG);
1933 case ISD::GlobalTLSAddress:
1934 return LowerGlobalTLSAddress(Op, DAG);
1936 return LowerSETCC(Op, DAG);
1938 return LowerBR_CC(Op, DAG);
1940 return LowerSELECT(Op, DAG);
1941 case ISD::SELECT_CC:
1942 return LowerSELECT_CC(Op, DAG);
1943 case ISD::JumpTable:
1944 return LowerJumpTable(Op, DAG);
1945 case ISD::ConstantPool:
1946 return LowerConstantPool(Op, DAG);
1947 case ISD::BlockAddress:
1948 return LowerBlockAddress(Op, DAG);
1950 return LowerVASTART(Op, DAG);
1952 return LowerVACOPY(Op, DAG);
1954 return LowerVAARG(Op, DAG);
1959 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1966 return LowerXALUO(Op, DAG);
1968 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1970 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1972 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1974 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1976 return LowerFP_ROUND(Op, DAG);
1977 case ISD::FP_EXTEND:
1978 return LowerFP_EXTEND(Op, DAG);
1979 case ISD::FRAMEADDR:
1980 return LowerFRAMEADDR(Op, DAG);
1981 case ISD::RETURNADDR:
1982 return LowerRETURNADDR(Op, DAG);
1983 case ISD::INSERT_VECTOR_ELT:
1984 return LowerINSERT_VECTOR_ELT(Op, DAG);
1985 case ISD::EXTRACT_VECTOR_ELT:
1986 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1987 case ISD::BUILD_VECTOR:
1988 return LowerBUILD_VECTOR(Op, DAG);
1989 case ISD::VECTOR_SHUFFLE:
1990 return LowerVECTOR_SHUFFLE(Op, DAG);
1991 case ISD::EXTRACT_SUBVECTOR:
1992 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1996 return LowerVectorSRA_SRL_SHL(Op, DAG);
1997 case ISD::SHL_PARTS:
1998 return LowerShiftLeftParts(Op, DAG);
1999 case ISD::SRL_PARTS:
2000 case ISD::SRA_PARTS:
2001 return LowerShiftRightParts(Op, DAG);
2003 return LowerCTPOP(Op, DAG);
2004 case ISD::FCOPYSIGN:
2005 return LowerFCOPYSIGN(Op, DAG);
2007 return LowerVectorAND(Op, DAG);
2009 return LowerVectorOR(Op, DAG);
2011 return LowerXOR(Op, DAG);
2013 return LowerPREFETCH(Op, DAG);
2014 case ISD::SINT_TO_FP:
2015 case ISD::UINT_TO_FP:
2016 return LowerINT_TO_FP(Op, DAG);
2017 case ISD::FP_TO_SINT:
2018 case ISD::FP_TO_UINT:
2019 return LowerFP_TO_INT(Op, DAG);
2021 return LowerFSINCOS(Op, DAG);
2023 return LowerMUL(Op, DAG);
2027 /// getFunctionAlignment - Return the Log2 alignment of this function.
2028 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2032 //===----------------------------------------------------------------------===//
2033 // Calling Convention Implementation
2034 //===----------------------------------------------------------------------===//
2036 #include "AArch64GenCallingConv.inc"
2038 /// Selects the correct CCAssignFn for a given CallingConvention value.
2039 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2040 bool IsVarArg) const {
2043 llvm_unreachable("Unsupported calling convention.");
2044 case CallingConv::WebKit_JS:
2045 return CC_AArch64_WebKit_JS;
2046 case CallingConv::GHC:
2047 return CC_AArch64_GHC;
2048 case CallingConv::C:
2049 case CallingConv::Fast:
2050 if (!Subtarget->isTargetDarwin())
2051 return CC_AArch64_AAPCS;
2052 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2056 SDValue AArch64TargetLowering::LowerFormalArguments(
2057 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2058 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2059 SmallVectorImpl<SDValue> &InVals) const {
2060 MachineFunction &MF = DAG.getMachineFunction();
2061 MachineFrameInfo *MFI = MF.getFrameInfo();
2063 // Assign locations to all of the incoming arguments.
2064 SmallVector<CCValAssign, 16> ArgLocs;
2065 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2068 // At this point, Ins[].VT may already be promoted to i32. To correctly
2069 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2070 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2071 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2072 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2074 unsigned NumArgs = Ins.size();
2075 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2076 unsigned CurArgIdx = 0;
2077 for (unsigned i = 0; i != NumArgs; ++i) {
2078 MVT ValVT = Ins[i].VT;
2079 if (Ins[i].isOrigArg()) {
2080 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2081 CurArgIdx = Ins[i].getOrigArgIndex();
2083 // Get type of the original argument.
2084 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2085 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2086 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2087 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2089 else if (ActualMVT == MVT::i16)
2092 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2094 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2095 assert(!Res && "Call operand has unhandled type");
2098 assert(ArgLocs.size() == Ins.size());
2099 SmallVector<SDValue, 16> ArgValues;
2100 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2101 CCValAssign &VA = ArgLocs[i];
2103 if (Ins[i].Flags.isByVal()) {
2104 // Byval is used for HFAs in the PCS, but the system should work in a
2105 // non-compliant manner for larger structs.
2106 EVT PtrTy = getPointerTy();
2107 int Size = Ins[i].Flags.getByValSize();
2108 unsigned NumRegs = (Size + 7) / 8;
2110 // FIXME: This works on big-endian for composite byvals, which are the common
2111 // case. It should also work for fundamental types too.
2113 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2114 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2115 InVals.push_back(FrameIdxN);
2120 if (VA.isRegLoc()) {
2121 // Arguments stored in registers.
2122 EVT RegVT = VA.getLocVT();
2125 const TargetRegisterClass *RC;
2127 if (RegVT == MVT::i32)
2128 RC = &AArch64::GPR32RegClass;
2129 else if (RegVT == MVT::i64)
2130 RC = &AArch64::GPR64RegClass;
2131 else if (RegVT == MVT::f16)
2132 RC = &AArch64::FPR16RegClass;
2133 else if (RegVT == MVT::f32)
2134 RC = &AArch64::FPR32RegClass;
2135 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2136 RC = &AArch64::FPR64RegClass;
2137 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2138 RC = &AArch64::FPR128RegClass;
2140 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2142 // Transform the arguments in physical registers into virtual ones.
2143 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2144 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2146 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2147 // to 64 bits. Insert an assert[sz]ext to capture this, then
2148 // truncate to the right size.
2149 switch (VA.getLocInfo()) {
2151 llvm_unreachable("Unknown loc info!");
2152 case CCValAssign::Full:
2154 case CCValAssign::BCvt:
2155 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2157 case CCValAssign::AExt:
2158 case CCValAssign::SExt:
2159 case CCValAssign::ZExt:
2160 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2161 // nodes after our lowering.
2162 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2166 InVals.push_back(ArgValue);
2168 } else { // VA.isRegLoc()
2169 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2170 unsigned ArgOffset = VA.getLocMemOffset();
2171 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2173 uint32_t BEAlign = 0;
2174 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2175 !Ins[i].Flags.isInConsecutiveRegs())
2176 BEAlign = 8 - ArgSize;
2178 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2180 // Create load nodes to retrieve arguments from the stack.
2181 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2184 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2185 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2186 MVT MemVT = VA.getValVT();
2188 switch (VA.getLocInfo()) {
2191 case CCValAssign::BCvt:
2192 MemVT = VA.getLocVT();
2194 case CCValAssign::SExt:
2195 ExtType = ISD::SEXTLOAD;
2197 case CCValAssign::ZExt:
2198 ExtType = ISD::ZEXTLOAD;
2200 case CCValAssign::AExt:
2201 ExtType = ISD::EXTLOAD;
2205 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2206 MachinePointerInfo::getFixedStack(FI),
2207 MemVT, false, false, false, 0);
2209 InVals.push_back(ArgValue);
2215 if (!Subtarget->isTargetDarwin()) {
2216 // The AAPCS variadic function ABI is identical to the non-variadic
2217 // one. As a result there may be more arguments in registers and we should
2218 // save them for future reference.
2219 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2222 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2223 // This will point to the next argument passed via stack.
2224 unsigned StackOffset = CCInfo.getNextStackOffset();
2225 // We currently pass all varargs at 8-byte alignment.
2226 StackOffset = ((StackOffset + 7) & ~7);
2227 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2230 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2231 unsigned StackArgSize = CCInfo.getNextStackOffset();
2232 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2233 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2234 // This is a non-standard ABI so by fiat I say we're allowed to make full
2235 // use of the stack area to be popped, which must be aligned to 16 bytes in
2237 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2239 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2240 // a multiple of 16.
2241 FuncInfo->setArgumentStackToRestore(StackArgSize);
2243 // This realignment carries over to the available bytes below. Our own
2244 // callers will guarantee the space is free by giving an aligned value to
2247 // Even if we're not expected to free up the space, it's useful to know how
2248 // much is there while considering tail calls (because we can reuse it).
2249 FuncInfo->setBytesInStackArgArea(StackArgSize);
2254 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2255 SelectionDAG &DAG, SDLoc DL,
2256 SDValue &Chain) const {
2257 MachineFunction &MF = DAG.getMachineFunction();
2258 MachineFrameInfo *MFI = MF.getFrameInfo();
2259 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2261 SmallVector<SDValue, 8> MemOps;
2263 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2264 AArch64::X3, AArch64::X4, AArch64::X5,
2265 AArch64::X6, AArch64::X7 };
2266 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2267 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2269 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2271 if (GPRSaveSize != 0) {
2272 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2274 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2276 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2277 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2278 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2280 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2281 MachinePointerInfo::getStack(i * 8), false, false, 0);
2282 MemOps.push_back(Store);
2283 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2284 DAG.getConstant(8, DL, getPointerTy()));
2287 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2288 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2290 if (Subtarget->hasFPARMv8()) {
2291 static const MCPhysReg FPRArgRegs[] = {
2292 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2293 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2294 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2295 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2297 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2299 if (FPRSaveSize != 0) {
2300 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2302 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2304 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2305 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2306 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2309 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2310 MachinePointerInfo::getStack(i * 16), false, false, 0);
2311 MemOps.push_back(Store);
2312 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2313 DAG.getConstant(16, DL, getPointerTy()));
2316 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2317 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2320 if (!MemOps.empty()) {
2321 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2325 /// LowerCallResult - Lower the result values of a call into the
2326 /// appropriate copies out of appropriate physical registers.
2327 SDValue AArch64TargetLowering::LowerCallResult(
2328 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2329 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2330 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2331 SDValue ThisVal) const {
2332 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2333 ? RetCC_AArch64_WebKit_JS
2334 : RetCC_AArch64_AAPCS;
2335 // Assign locations to each value returned by this call.
2336 SmallVector<CCValAssign, 16> RVLocs;
2337 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2339 CCInfo.AnalyzeCallResult(Ins, RetCC);
2341 // Copy all of the result registers out of their specified physreg.
2342 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2343 CCValAssign VA = RVLocs[i];
2345 // Pass 'this' value directly from the argument to return value, to avoid
2346 // reg unit interference
2347 if (i == 0 && isThisReturn) {
2348 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2349 "unexpected return calling convention register assignment");
2350 InVals.push_back(ThisVal);
2355 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2356 Chain = Val.getValue(1);
2357 InFlag = Val.getValue(2);
2359 switch (VA.getLocInfo()) {
2361 llvm_unreachable("Unknown loc info!");
2362 case CCValAssign::Full:
2364 case CCValAssign::BCvt:
2365 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2369 InVals.push_back(Val);
2375 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2376 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2377 bool isCalleeStructRet, bool isCallerStructRet,
2378 const SmallVectorImpl<ISD::OutputArg> &Outs,
2379 const SmallVectorImpl<SDValue> &OutVals,
2380 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2381 // For CallingConv::C this function knows whether the ABI needs
2382 // changing. That's not true for other conventions so they will have to opt in
2384 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2387 const MachineFunction &MF = DAG.getMachineFunction();
2388 const Function *CallerF = MF.getFunction();
2389 CallingConv::ID CallerCC = CallerF->getCallingConv();
2390 bool CCMatch = CallerCC == CalleeCC;
2392 // Byval parameters hand the function a pointer directly into the stack area
2393 // we want to reuse during a tail call. Working around this *is* possible (see
2394 // X86) but less efficient and uglier in LowerCall.
2395 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2396 e = CallerF->arg_end();
2398 if (i->hasByValAttr())
2401 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2402 if (IsTailCallConvention(CalleeCC) && CCMatch)
2407 // Externally-defined functions with weak linkage should not be
2408 // tail-called on AArch64 when the OS does not support dynamic
2409 // pre-emption of symbols, as the AAELF spec requires normal calls
2410 // to undefined weak functions to be replaced with a NOP or jump to the
2411 // next instruction. The behaviour of branch instructions in this
2412 // situation (as used for tail calls) is implementation-defined, so we
2413 // cannot rely on the linker replacing the tail call with a return.
2414 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2415 const GlobalValue *GV = G->getGlobal();
2416 const Triple TT(getTargetMachine().getTargetTriple());
2417 if (GV->hasExternalWeakLinkage() &&
2418 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2422 // Now we search for cases where we can use a tail call without changing the
2423 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2426 // I want anyone implementing a new calling convention to think long and hard
2427 // about this assert.
2428 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2429 "Unexpected variadic calling convention");
2431 if (isVarArg && !Outs.empty()) {
2432 // At least two cases here: if caller is fastcc then we can't have any
2433 // memory arguments (we'd be expected to clean up the stack afterwards). If
2434 // caller is C then we could potentially use its argument area.
2436 // FIXME: for now we take the most conservative of these in both cases:
2437 // disallow all variadic memory operands.
2438 SmallVector<CCValAssign, 16> ArgLocs;
2439 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2442 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2443 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2444 if (!ArgLocs[i].isRegLoc())
2448 // If the calling conventions do not match, then we'd better make sure the
2449 // results are returned in the same way as what the caller expects.
2451 SmallVector<CCValAssign, 16> RVLocs1;
2452 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2454 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2456 SmallVector<CCValAssign, 16> RVLocs2;
2457 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2459 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2461 if (RVLocs1.size() != RVLocs2.size())
2463 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2464 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2466 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2468 if (RVLocs1[i].isRegLoc()) {
2469 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2472 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2478 // Nothing more to check if the callee is taking no arguments
2482 SmallVector<CCValAssign, 16> ArgLocs;
2483 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2486 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2488 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2490 // If the stack arguments for this call would fit into our own save area then
2491 // the call can be made tail.
2492 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2495 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2497 MachineFrameInfo *MFI,
2498 int ClobberedFI) const {
2499 SmallVector<SDValue, 8> ArgChains;
2500 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2501 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2503 // Include the original chain at the beginning of the list. When this is
2504 // used by target LowerCall hooks, this helps legalize find the
2505 // CALLSEQ_BEGIN node.
2506 ArgChains.push_back(Chain);
2508 // Add a chain value for each stack argument corresponding
2509 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2510 UE = DAG.getEntryNode().getNode()->use_end();
2512 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2513 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2514 if (FI->getIndex() < 0) {
2515 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2516 int64_t InLastByte = InFirstByte;
2517 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2519 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2520 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2521 ArgChains.push_back(SDValue(L, 1));
2524 // Build a tokenfactor for all the chains.
2525 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2528 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2529 bool TailCallOpt) const {
2530 return CallCC == CallingConv::Fast && TailCallOpt;
2533 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2534 return CallCC == CallingConv::Fast;
2537 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2538 /// and add input and output parameter nodes.
2540 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2541 SmallVectorImpl<SDValue> &InVals) const {
2542 SelectionDAG &DAG = CLI.DAG;
2544 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2545 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2546 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2547 SDValue Chain = CLI.Chain;
2548 SDValue Callee = CLI.Callee;
2549 bool &IsTailCall = CLI.IsTailCall;
2550 CallingConv::ID CallConv = CLI.CallConv;
2551 bool IsVarArg = CLI.IsVarArg;
2553 MachineFunction &MF = DAG.getMachineFunction();
2554 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2555 bool IsThisReturn = false;
2557 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2558 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2559 bool IsSibCall = false;
2562 // Check if it's really possible to do a tail call.
2563 IsTailCall = isEligibleForTailCallOptimization(
2564 Callee, CallConv, IsVarArg, IsStructRet,
2565 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2566 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2567 report_fatal_error("failed to perform tail call elimination on a call "
2568 "site marked musttail");
2570 // A sibling call is one where we're under the usual C ABI and not planning
2571 // to change that but can still do a tail call:
2572 if (!TailCallOpt && IsTailCall)
2579 // Analyze operands of the call, assigning locations to each operand.
2580 SmallVector<CCValAssign, 16> ArgLocs;
2581 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2585 // Handle fixed and variable vector arguments differently.
2586 // Variable vector arguments always go into memory.
2587 unsigned NumArgs = Outs.size();
2589 for (unsigned i = 0; i != NumArgs; ++i) {
2590 MVT ArgVT = Outs[i].VT;
2591 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2592 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2593 /*IsVarArg=*/ !Outs[i].IsFixed);
2594 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2595 assert(!Res && "Call operand has unhandled type");
2599 // At this point, Outs[].VT may already be promoted to i32. To correctly
2600 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2601 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2602 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2603 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2605 unsigned NumArgs = Outs.size();
2606 for (unsigned i = 0; i != NumArgs; ++i) {
2607 MVT ValVT = Outs[i].VT;
2608 // Get type of the original argument.
2609 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2610 /*AllowUnknown*/ true);
2611 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2612 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2613 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2614 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2616 else if (ActualMVT == MVT::i16)
2619 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2620 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2621 assert(!Res && "Call operand has unhandled type");
2626 // Get a count of how many bytes are to be pushed on the stack.
2627 unsigned NumBytes = CCInfo.getNextStackOffset();
2630 // Since we're not changing the ABI to make this a tail call, the memory
2631 // operands are already available in the caller's incoming argument space.
2635 // FPDiff is the byte offset of the call's argument area from the callee's.
2636 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2637 // by this amount for a tail call. In a sibling call it must be 0 because the
2638 // caller will deallocate the entire stack and the callee still expects its
2639 // arguments to begin at SP+0. Completely unused for non-tail calls.
2642 if (IsTailCall && !IsSibCall) {
2643 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2645 // Since callee will pop argument stack as a tail call, we must keep the
2646 // popped size 16-byte aligned.
2647 NumBytes = RoundUpToAlignment(NumBytes, 16);
2649 // FPDiff will be negative if this tail call requires more space than we
2650 // would automatically have in our incoming argument space. Positive if we
2651 // can actually shrink the stack.
2652 FPDiff = NumReusableBytes - NumBytes;
2654 // The stack pointer must be 16-byte aligned at all times it's used for a
2655 // memory operation, which in practice means at *all* times and in
2656 // particular across call boundaries. Therefore our own arguments started at
2657 // a 16-byte aligned SP and the delta applied for the tail call should
2658 // satisfy the same constraint.
2659 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2662 // Adjust the stack pointer for the new arguments...
2663 // These operations are automatically eliminated by the prolog/epilog pass
2665 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2669 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2671 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2672 SmallVector<SDValue, 8> MemOpChains;
2674 // Walk the register/memloc assignments, inserting copies/loads.
2675 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2676 ++i, ++realArgIdx) {
2677 CCValAssign &VA = ArgLocs[i];
2678 SDValue Arg = OutVals[realArgIdx];
2679 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2681 // Promote the value if needed.
2682 switch (VA.getLocInfo()) {
2684 llvm_unreachable("Unknown loc info!");
2685 case CCValAssign::Full:
2687 case CCValAssign::SExt:
2688 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2690 case CCValAssign::ZExt:
2691 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2693 case CCValAssign::AExt:
2694 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2695 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2696 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2697 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2699 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2701 case CCValAssign::BCvt:
2702 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2704 case CCValAssign::FPExt:
2705 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2709 if (VA.isRegLoc()) {
2710 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2711 assert(VA.getLocVT() == MVT::i64 &&
2712 "unexpected calling convention register assignment");
2713 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2714 "unexpected use of 'returned'");
2715 IsThisReturn = true;
2717 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2719 assert(VA.isMemLoc());
2722 MachinePointerInfo DstInfo;
2724 // FIXME: This works on big-endian for composite byvals, which are the
2725 // common case. It should also work for fundamental types too.
2726 uint32_t BEAlign = 0;
2727 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2728 : VA.getValVT().getSizeInBits();
2729 OpSize = (OpSize + 7) / 8;
2730 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2731 !Flags.isInConsecutiveRegs()) {
2733 BEAlign = 8 - OpSize;
2735 unsigned LocMemOffset = VA.getLocMemOffset();
2736 int32_t Offset = LocMemOffset + BEAlign;
2737 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2738 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2741 Offset = Offset + FPDiff;
2742 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2744 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2745 DstInfo = MachinePointerInfo::getFixedStack(FI);
2747 // Make sure any stack arguments overlapping with where we're storing
2748 // are loaded before this eventual operation. Otherwise they'll be
2750 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2752 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2754 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2755 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2758 if (Outs[i].Flags.isByVal()) {
2760 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
2761 SDValue Cpy = DAG.getMemcpy(
2762 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2763 /*isVol = */ false, /*AlwaysInline = */ false,
2764 /*isTailCall = */ false,
2765 DstInfo, MachinePointerInfo());
2767 MemOpChains.push_back(Cpy);
2769 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2770 // promoted to a legal register type i32, we should truncate Arg back to
2772 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2773 VA.getValVT() == MVT::i16)
2774 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2777 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2778 MemOpChains.push_back(Store);
2783 if (!MemOpChains.empty())
2784 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2786 // Build a sequence of copy-to-reg nodes chained together with token chain
2787 // and flag operands which copy the outgoing args into the appropriate regs.
2789 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2790 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2791 RegsToPass[i].second, InFlag);
2792 InFlag = Chain.getValue(1);
2795 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2796 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2797 // node so that legalize doesn't hack it.
2798 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2799 Subtarget->isTargetMachO()) {
2800 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2801 const GlobalValue *GV = G->getGlobal();
2802 bool InternalLinkage = GV->hasInternalLinkage();
2803 if (InternalLinkage)
2804 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2806 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2808 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2810 } else if (ExternalSymbolSDNode *S =
2811 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2812 const char *Sym = S->getSymbol();
2814 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2815 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2817 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2818 const GlobalValue *GV = G->getGlobal();
2819 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2820 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2821 const char *Sym = S->getSymbol();
2822 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2825 // We don't usually want to end the call-sequence here because we would tidy
2826 // the frame up *after* the call, however in the ABI-changing tail-call case
2827 // we've carefully laid out the parameters so that when sp is reset they'll be
2828 // in the correct location.
2829 if (IsTailCall && !IsSibCall) {
2830 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2831 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2832 InFlag = Chain.getValue(1);
2835 std::vector<SDValue> Ops;
2836 Ops.push_back(Chain);
2837 Ops.push_back(Callee);
2840 // Each tail call may have to adjust the stack by a different amount, so
2841 // this information must travel along with the operation for eventual
2842 // consumption by emitEpilogue.
2843 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2846 // Add argument registers to the end of the list so that they are known live
2848 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2849 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2850 RegsToPass[i].second.getValueType()));
2852 // Add a register mask operand representing the call-preserved registers.
2853 const uint32_t *Mask;
2854 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2856 // For 'this' returns, use the X0-preserving mask if applicable
2857 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2859 IsThisReturn = false;
2860 Mask = TRI->getCallPreservedMask(MF, CallConv);
2863 Mask = TRI->getCallPreservedMask(MF, CallConv);
2865 assert(Mask && "Missing call preserved mask for calling convention");
2866 Ops.push_back(DAG.getRegisterMask(Mask));
2868 if (InFlag.getNode())
2869 Ops.push_back(InFlag);
2871 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2873 // If we're doing a tall call, use a TC_RETURN here rather than an
2874 // actual call instruction.
2876 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2878 // Returns a chain and a flag for retval copy to use.
2879 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2880 InFlag = Chain.getValue(1);
2882 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2883 ? RoundUpToAlignment(NumBytes, 16)
2886 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2887 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
2890 InFlag = Chain.getValue(1);
2892 // Handle result values, copying them out of physregs into vregs that we
2894 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2895 InVals, IsThisReturn,
2896 IsThisReturn ? OutVals[0] : SDValue());
2899 bool AArch64TargetLowering::CanLowerReturn(
2900 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2901 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2902 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2903 ? RetCC_AArch64_WebKit_JS
2904 : RetCC_AArch64_AAPCS;
2905 SmallVector<CCValAssign, 16> RVLocs;
2906 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2907 return CCInfo.CheckReturn(Outs, RetCC);
2911 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2913 const SmallVectorImpl<ISD::OutputArg> &Outs,
2914 const SmallVectorImpl<SDValue> &OutVals,
2915 SDLoc DL, SelectionDAG &DAG) const {
2916 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2917 ? RetCC_AArch64_WebKit_JS
2918 : RetCC_AArch64_AAPCS;
2919 SmallVector<CCValAssign, 16> RVLocs;
2920 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2922 CCInfo.AnalyzeReturn(Outs, RetCC);
2924 // Copy the result values into the output registers.
2926 SmallVector<SDValue, 4> RetOps(1, Chain);
2927 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2928 ++i, ++realRVLocIdx) {
2929 CCValAssign &VA = RVLocs[i];
2930 assert(VA.isRegLoc() && "Can only return in registers!");
2931 SDValue Arg = OutVals[realRVLocIdx];
2933 switch (VA.getLocInfo()) {
2935 llvm_unreachable("Unknown loc info!");
2936 case CCValAssign::Full:
2937 if (Outs[i].ArgVT == MVT::i1) {
2938 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2939 // value. This is strictly redundant on Darwin (which uses "zeroext
2940 // i1"), but will be optimised out before ISel.
2941 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2942 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2945 case CCValAssign::BCvt:
2946 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2950 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2951 Flag = Chain.getValue(1);
2952 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2955 RetOps[0] = Chain; // Update chain.
2957 // Add the flag if we have it.
2959 RetOps.push_back(Flag);
2961 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2964 //===----------------------------------------------------------------------===//
2965 // Other Lowering Code
2966 //===----------------------------------------------------------------------===//
2968 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2969 SelectionDAG &DAG) const {
2970 EVT PtrVT = getPointerTy();
2972 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2973 const GlobalValue *GV = GN->getGlobal();
2974 unsigned char OpFlags =
2975 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2977 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2978 "unexpected offset in global node");
2980 // This also catched the large code model case for Darwin.
2981 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2982 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2983 // FIXME: Once remat is capable of dealing with instructions with register
2984 // operands, expand this into two nodes instead of using a wrapper node.
2985 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2988 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2989 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2990 "use of MO_CONSTPOOL only supported on small model");
2991 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2992 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2993 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2994 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2995 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2996 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2997 MachinePointerInfo::getConstantPool(),
2998 /*isVolatile=*/ false,
2999 /*isNonTemporal=*/ true,
3000 /*isInvariant=*/ true, 8);
3001 if (GN->getOffset() != 0)
3002 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3003 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3007 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3008 const unsigned char MO_NC = AArch64II::MO_NC;
3010 AArch64ISD::WrapperLarge, DL, PtrVT,
3011 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3012 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3013 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3014 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3016 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3017 // the only correct model on Darwin.
3018 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3019 OpFlags | AArch64II::MO_PAGE);
3020 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3021 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3023 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3024 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3028 /// \brief Convert a TLS address reference into the correct sequence of loads
3029 /// and calls to compute the variable's address (for Darwin, currently) and
3030 /// return an SDValue containing the final node.
3032 /// Darwin only has one TLS scheme which must be capable of dealing with the
3033 /// fully general situation, in the worst case. This means:
3034 /// + "extern __thread" declaration.
3035 /// + Defined in a possibly unknown dynamic library.
3037 /// The general system is that each __thread variable has a [3 x i64] descriptor
3038 /// which contains information used by the runtime to calculate the address. The
3039 /// only part of this the compiler needs to know about is the first xword, which
3040 /// contains a function pointer that must be called with the address of the
3041 /// entire descriptor in "x0".
3043 /// Since this descriptor may be in a different unit, in general even the
3044 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3046 /// adrp x0, _var@TLVPPAGE
3047 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3048 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3049 /// ; the function pointer
3050 /// blr x1 ; Uses descriptor address in x0
3051 /// ; Address of _var is now in x0.
3053 /// If the address of _var's descriptor *is* known to the linker, then it can
3054 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3055 /// a slight efficiency gain.
3057 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3058 SelectionDAG &DAG) const {
3059 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3062 MVT PtrVT = getPointerTy();
3063 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3066 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3067 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3069 // The first entry in the descriptor is a function pointer that we must call
3070 // to obtain the address of the variable.
3071 SDValue Chain = DAG.getEntryNode();
3072 SDValue FuncTLVGet =
3073 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3074 false, true, true, 8);
3075 Chain = FuncTLVGet.getValue(1);
3077 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3078 MFI->setAdjustsStack(true);
3080 // TLS calls preserve all registers except those that absolutely must be
3081 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3083 const uint32_t *Mask =
3084 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3086 // Finally, we can make the call. This is just a degenerate version of a
3087 // normal AArch64 call node: x0 takes the address of the descriptor, and
3088 // returns the address of the variable in this thread.
3089 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3091 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3092 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3093 DAG.getRegisterMask(Mask), Chain.getValue(1));
3094 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3097 /// When accessing thread-local variables under either the general-dynamic or
3098 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3099 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3100 /// is a function pointer to carry out the resolution.
3102 /// The sequence is:
3103 /// adrp x0, :tlsdesc:var
3104 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3105 /// add x0, x0, #:tlsdesc_lo12:var
3106 /// .tlsdesccall var
3108 /// (TPIDR_EL0 offset now in x0)
3110 /// The above sequence must be produced unscheduled, to enable the linker to
3111 /// optimize/relax this sequence.
3112 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3113 /// above sequence, and expanded really late in the compilation flow, to ensure
3114 /// the sequence is produced as per above.
3115 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3116 SelectionDAG &DAG) const {
3117 EVT PtrVT = getPointerTy();
3119 SDValue Chain = DAG.getEntryNode();
3120 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3122 SmallVector<SDValue, 2> Ops;
3123 Ops.push_back(Chain);
3124 Ops.push_back(SymAddr);
3126 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3127 SDValue Glue = Chain.getValue(1);
3129 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3133 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3134 SelectionDAG &DAG) const {
3135 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3136 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3137 "ELF TLS only supported in small memory model");
3138 // Different choices can be made for the maximum size of the TLS area for a
3139 // module. For the small address model, the default TLS size is 16MiB and the
3140 // maximum TLS size is 4GiB.
3141 // FIXME: add -mtls-size command line option and make it control the 16MiB
3142 // vs. 4GiB code sequence generation.
3143 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3145 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3146 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3147 if (Model == TLSModel::LocalDynamic)
3148 Model = TLSModel::GeneralDynamic;
3152 EVT PtrVT = getPointerTy();
3154 const GlobalValue *GV = GA->getGlobal();
3156 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3158 if (Model == TLSModel::LocalExec) {
3159 SDValue HiVar = DAG.getTargetGlobalAddress(
3160 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3161 SDValue LoVar = DAG.getTargetGlobalAddress(
3163 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3165 SDValue TPWithOff_lo =
3166 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3168 DAG.getTargetConstant(0, DL, MVT::i32)),
3171 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3173 DAG.getTargetConstant(0, DL, MVT::i32)),
3176 } else if (Model == TLSModel::InitialExec) {
3177 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3178 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3179 } else if (Model == TLSModel::LocalDynamic) {
3180 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3181 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3182 // the beginning of the module's TLS region, followed by a DTPREL offset
3185 // These accesses will need deduplicating if there's more than one.
3186 AArch64FunctionInfo *MFI =
3187 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3188 MFI->incNumLocalDynamicTLSAccesses();
3190 // The call needs a relocation too for linker relaxation. It doesn't make
3191 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3193 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3196 // Now we can calculate the offset from TPIDR_EL0 to this module's
3197 // thread-local area.
3198 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3200 // Now use :dtprel_whatever: operations to calculate this variable's offset
3201 // in its thread-storage area.
3202 SDValue HiVar = DAG.getTargetGlobalAddress(
3203 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3204 SDValue LoVar = DAG.getTargetGlobalAddress(
3205 GV, DL, MVT::i64, 0,
3206 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3208 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3209 DAG.getTargetConstant(0, DL, MVT::i32)),
3211 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3212 DAG.getTargetConstant(0, DL, MVT::i32)),
3214 } else if (Model == TLSModel::GeneralDynamic) {
3215 // The call needs a relocation too for linker relaxation. It doesn't make
3216 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3219 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3221 // Finally we can make a call to calculate the offset from tpidr_el0.
3222 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3224 llvm_unreachable("Unsupported ELF TLS access model");
3226 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3229 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3230 SelectionDAG &DAG) const {
3231 if (Subtarget->isTargetDarwin())
3232 return LowerDarwinGlobalTLSAddress(Op, DAG);
3233 else if (Subtarget->isTargetELF())
3234 return LowerELFGlobalTLSAddress(Op, DAG);
3236 llvm_unreachable("Unexpected platform trying to use TLS");
3238 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3239 SDValue Chain = Op.getOperand(0);
3240 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3241 SDValue LHS = Op.getOperand(2);
3242 SDValue RHS = Op.getOperand(3);
3243 SDValue Dest = Op.getOperand(4);
3246 // Handle f128 first, since lowering it will result in comparing the return
3247 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3248 // is expecting to deal with.
3249 if (LHS.getValueType() == MVT::f128) {
3250 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3252 // If softenSetCCOperands returned a scalar, we need to compare the result
3253 // against zero to select between true and false values.
3254 if (!RHS.getNode()) {
3255 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3260 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3262 unsigned Opc = LHS.getOpcode();
3263 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3264 cast<ConstantSDNode>(RHS)->isOne() &&
3265 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3266 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3267 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3268 "Unexpected condition code.");
3269 // Only lower legal XALUO ops.
3270 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3273 // The actual operation with overflow check.
3274 AArch64CC::CondCode OFCC;
3275 SDValue Value, Overflow;
3276 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3278 if (CC == ISD::SETNE)
3279 OFCC = getInvertedCondCode(OFCC);
3280 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3282 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3286 if (LHS.getValueType().isInteger()) {
3287 assert((LHS.getValueType() == RHS.getValueType()) &&
3288 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3290 // If the RHS of the comparison is zero, we can potentially fold this
3291 // to a specialized branch.
3292 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3293 if (RHSC && RHSC->getZExtValue() == 0) {
3294 if (CC == ISD::SETEQ) {
3295 // See if we can use a TBZ to fold in an AND as well.
3296 // TBZ has a smaller branch displacement than CBZ. If the offset is
3297 // out of bounds, a late MI-layer pass rewrites branches.
3298 // 403.gcc is an example that hits this case.
3299 if (LHS.getOpcode() == ISD::AND &&
3300 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3301 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3302 SDValue Test = LHS.getOperand(0);
3303 uint64_t Mask = LHS.getConstantOperandVal(1);
3304 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3305 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3309 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3310 } else if (CC == ISD::SETNE) {
3311 // See if we can use a TBZ to fold in an AND as well.
3312 // TBZ has a smaller branch displacement than CBZ. If the offset is
3313 // out of bounds, a late MI-layer pass rewrites branches.
3314 // 403.gcc is an example that hits this case.
3315 if (LHS.getOpcode() == ISD::AND &&
3316 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3317 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3318 SDValue Test = LHS.getOperand(0);
3319 uint64_t Mask = LHS.getConstantOperandVal(1);
3320 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3321 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3325 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3326 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3327 // Don't combine AND since emitComparison converts the AND to an ANDS
3328 // (a.k.a. TST) and the test in the test bit and branch instruction
3329 // becomes redundant. This would also increase register pressure.
3330 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3331 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3332 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3335 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3336 LHS.getOpcode() != ISD::AND) {
3337 // Don't combine AND since emitComparison converts the AND to an ANDS
3338 // (a.k.a. TST) and the test in the test bit and branch instruction
3339 // becomes redundant. This would also increase register pressure.
3340 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3341 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3342 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3346 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3347 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3351 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3353 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3354 // clean. Some of them require two branches to implement.
3355 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3356 AArch64CC::CondCode CC1, CC2;
3357 changeFPCCToAArch64CC(CC, CC1, CC2);
3358 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3360 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3361 if (CC2 != AArch64CC::AL) {
3362 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3363 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3370 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3371 SelectionDAG &DAG) const {
3372 EVT VT = Op.getValueType();
3375 SDValue In1 = Op.getOperand(0);
3376 SDValue In2 = Op.getOperand(1);
3377 EVT SrcVT = In2.getValueType();
3379 if (SrcVT == MVT::f32 && VT == MVT::f64)
3380 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3381 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3382 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3383 DAG.getIntPtrConstant(0, DL));
3385 // FIXME: Src type is different, bail out for now. Can VT really be a
3393 SDValue VecVal1, VecVal2;
3394 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3397 EltMask = 0x80000000ULL;
3399 if (!VT.isVector()) {
3400 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3401 DAG.getUNDEF(VecVT), In1);
3402 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3403 DAG.getUNDEF(VecVT), In2);
3405 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3406 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3408 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3412 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3413 // immediate moves cannot materialize that in a single instruction for
3414 // 64-bit elements. Instead, materialize zero and then negate it.
3417 if (!VT.isVector()) {
3418 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3419 DAG.getUNDEF(VecVT), In1);
3420 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3421 DAG.getUNDEF(VecVT), In2);
3423 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3424 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3427 llvm_unreachable("Invalid type for copysign!");
3430 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3432 // If we couldn't materialize the mask above, then the mask vector will be
3433 // the zero vector, and we need to negate it here.
3434 if (VT == MVT::f64 || VT == MVT::v2f64) {
3435 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3436 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3437 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3441 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3444 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3445 else if (VT == MVT::f64)
3446 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3448 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3451 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3452 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3453 Attribute::NoImplicitFloat))
3456 if (!Subtarget->hasNEON())
3459 // While there is no integer popcount instruction, it can
3460 // be more efficiently lowered to the following sequence that uses
3461 // AdvSIMD registers/instructions as long as the copies to/from
3462 // the AdvSIMD registers are cheap.
3463 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3464 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3465 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3466 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3467 SDValue Val = Op.getOperand(0);
3469 EVT VT = Op.getValueType();
3472 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3473 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3475 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3476 SDValue UaddLV = DAG.getNode(
3477 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3478 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3481 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3485 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3487 if (Op.getValueType().isVector())
3488 return LowerVSETCC(Op, DAG);
3490 SDValue LHS = Op.getOperand(0);
3491 SDValue RHS = Op.getOperand(1);
3492 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3495 // We chose ZeroOrOneBooleanContents, so use zero and one.
3496 EVT VT = Op.getValueType();
3497 SDValue TVal = DAG.getConstant(1, dl, VT);
3498 SDValue FVal = DAG.getConstant(0, dl, VT);
3500 // Handle f128 first, since one possible outcome is a normal integer
3501 // comparison which gets picked up by the next if statement.
3502 if (LHS.getValueType() == MVT::f128) {
3503 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3505 // If softenSetCCOperands returned a scalar, use it.
3506 if (!RHS.getNode()) {
3507 assert(LHS.getValueType() == Op.getValueType() &&
3508 "Unexpected setcc expansion!");
3513 if (LHS.getValueType().isInteger()) {
3516 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3518 // Note that we inverted the condition above, so we reverse the order of
3519 // the true and false operands here. This will allow the setcc to be
3520 // matched to a single CSINC instruction.
3521 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3524 // Now we know we're dealing with FP values.
3525 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3527 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3528 // and do the comparison.
3529 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3531 AArch64CC::CondCode CC1, CC2;
3532 changeFPCCToAArch64CC(CC, CC1, CC2);
3533 if (CC2 == AArch64CC::AL) {
3534 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3535 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3537 // Note that we inverted the condition above, so we reverse the order of
3538 // the true and false operands here. This will allow the setcc to be
3539 // matched to a single CSINC instruction.
3540 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3542 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3543 // totally clean. Some of them require two CSELs to implement. As is in
3544 // this case, we emit the first CSEL and then emit a second using the output
3545 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3547 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3548 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3550 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3552 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3553 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3557 /// A SELECT_CC operation is really some kind of max or min if both values being
3558 /// compared are, in some sense, equal to the results in either case. However,
3559 /// it is permissible to compare f32 values and produce directly extended f64
3562 /// Extending the comparison operands would also be allowed, but is less likely
3563 /// to happen in practice since their use is right here. Note that truncate
3564 /// operations would *not* be semantically equivalent.
3565 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3569 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3570 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3571 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3572 Result.getValueType() == MVT::f64) {
3574 APFloat CmpVal = CCmp->getValueAPF();
3575 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3576 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3579 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3582 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3583 SDValue RHS, SDValue TVal,
3584 SDValue FVal, SDLoc dl,
3585 SelectionDAG &DAG) const {
3586 // Handle f128 first, because it will result in a comparison of some RTLIB
3587 // call result against zero.
3588 if (LHS.getValueType() == MVT::f128) {
3589 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3591 // If softenSetCCOperands returned a scalar, we need to compare the result
3592 // against zero to select between true and false values.
3593 if (!RHS.getNode()) {
3594 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3599 // Handle integers first.
3600 if (LHS.getValueType().isInteger()) {
3601 assert((LHS.getValueType() == RHS.getValueType()) &&
3602 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3604 unsigned Opcode = AArch64ISD::CSEL;
3606 // If both the TVal and the FVal are constants, see if we can swap them in
3607 // order to for a CSINV or CSINC out of them.
3608 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3609 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3611 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3612 std::swap(TVal, FVal);
3613 std::swap(CTVal, CFVal);
3614 CC = ISD::getSetCCInverse(CC, true);
3615 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3616 std::swap(TVal, FVal);
3617 std::swap(CTVal, CFVal);
3618 CC = ISD::getSetCCInverse(CC, true);
3619 } else if (TVal.getOpcode() == ISD::XOR) {
3620 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3621 // with a CSINV rather than a CSEL.
3622 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3624 if (CVal && CVal->isAllOnesValue()) {
3625 std::swap(TVal, FVal);
3626 std::swap(CTVal, CFVal);
3627 CC = ISD::getSetCCInverse(CC, true);
3629 } else if (TVal.getOpcode() == ISD::SUB) {
3630 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3631 // that we can match with a CSNEG rather than a CSEL.
3632 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3634 if (CVal && CVal->isNullValue()) {
3635 std::swap(TVal, FVal);
3636 std::swap(CTVal, CFVal);
3637 CC = ISD::getSetCCInverse(CC, true);
3639 } else if (CTVal && CFVal) {
3640 const int64_t TrueVal = CTVal->getSExtValue();
3641 const int64_t FalseVal = CFVal->getSExtValue();
3644 // If both TVal and FVal are constants, see if FVal is the
3645 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3646 // instead of a CSEL in that case.
3647 if (TrueVal == ~FalseVal) {
3648 Opcode = AArch64ISD::CSINV;
3649 } else if (TrueVal == -FalseVal) {
3650 Opcode = AArch64ISD::CSNEG;
3651 } else if (TVal.getValueType() == MVT::i32) {
3652 // If our operands are only 32-bit wide, make sure we use 32-bit
3653 // arithmetic for the check whether we can use CSINC. This ensures that
3654 // the addition in the check will wrap around properly in case there is
3655 // an overflow (which would not be the case if we do the check with
3656 // 64-bit arithmetic).
3657 const uint32_t TrueVal32 = CTVal->getZExtValue();
3658 const uint32_t FalseVal32 = CFVal->getZExtValue();
3660 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3661 Opcode = AArch64ISD::CSINC;
3663 if (TrueVal32 > FalseVal32) {
3667 // 64-bit check whether we can use CSINC.
3668 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3669 Opcode = AArch64ISD::CSINC;
3671 if (TrueVal > FalseVal) {
3676 // Swap TVal and FVal if necessary.
3678 std::swap(TVal, FVal);
3679 std::swap(CTVal, CFVal);
3680 CC = ISD::getSetCCInverse(CC, true);
3683 if (Opcode != AArch64ISD::CSEL) {
3684 // Drop FVal since we can get its value by simply inverting/negating
3691 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3693 EVT VT = TVal.getValueType();
3694 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3697 // Now we know we're dealing with FP values.
3698 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3699 assert(LHS.getValueType() == RHS.getValueType());
3700 EVT VT = TVal.getValueType();
3702 // Try to match this select into a max/min operation, which have dedicated
3703 // opcode in the instruction set.
3704 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3706 if (getTargetMachine().Options.NoNaNsFPMath) {
3707 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3708 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3709 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3710 CC = ISD::getSetCCSwappedOperands(CC);
3711 std::swap(MinMaxLHS, MinMaxRHS);
3714 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3715 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3725 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3733 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3739 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3740 // and do the comparison.
3741 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3743 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3744 // clean. Some of them require two CSELs to implement.
3745 AArch64CC::CondCode CC1, CC2;
3746 changeFPCCToAArch64CC(CC, CC1, CC2);
3747 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3748 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3750 // If we need a second CSEL, emit it, using the output of the first as the
3751 // RHS. We're effectively OR'ing the two CC's together.
3752 if (CC2 != AArch64CC::AL) {
3753 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3754 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3757 // Otherwise, return the output of the first CSEL.
3761 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3762 SelectionDAG &DAG) const {
3763 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3764 SDValue LHS = Op.getOperand(0);
3765 SDValue RHS = Op.getOperand(1);
3766 SDValue TVal = Op.getOperand(2);
3767 SDValue FVal = Op.getOperand(3);
3769 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3772 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3773 SelectionDAG &DAG) const {
3774 SDValue CCVal = Op->getOperand(0);
3775 SDValue TVal = Op->getOperand(1);
3776 SDValue FVal = Op->getOperand(2);
3779 unsigned Opc = CCVal.getOpcode();
3780 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3782 if (CCVal.getResNo() == 1 &&
3783 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3784 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3785 // Only lower legal XALUO ops.
3786 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3789 AArch64CC::CondCode OFCC;
3790 SDValue Value, Overflow;
3791 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3792 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
3794 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3798 // Lower it the same way as we would lower a SELECT_CC node.
3801 if (CCVal.getOpcode() == ISD::SETCC) {
3802 LHS = CCVal.getOperand(0);
3803 RHS = CCVal.getOperand(1);
3804 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3807 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
3810 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3813 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3814 SelectionDAG &DAG) const {
3815 // Jump table entries as PC relative offsets. No additional tweaking
3816 // is necessary here. Just get the address of the jump table.
3817 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3818 EVT PtrVT = getPointerTy();
3821 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3822 !Subtarget->isTargetMachO()) {
3823 const unsigned char MO_NC = AArch64II::MO_NC;
3825 AArch64ISD::WrapperLarge, DL, PtrVT,
3826 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3827 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3828 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3829 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3830 AArch64II::MO_G0 | MO_NC));
3834 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3835 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3836 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3837 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3838 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3841 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3842 SelectionDAG &DAG) const {
3843 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3844 EVT PtrVT = getPointerTy();
3847 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3848 // Use the GOT for the large code model on iOS.
3849 if (Subtarget->isTargetMachO()) {
3850 SDValue GotAddr = DAG.getTargetConstantPool(
3851 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3853 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3856 const unsigned char MO_NC = AArch64II::MO_NC;
3858 AArch64ISD::WrapperLarge, DL, PtrVT,
3859 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3860 CP->getOffset(), AArch64II::MO_G3),
3861 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3862 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3863 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3864 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3865 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3866 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3868 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3869 // ELF, the only valid one on Darwin.
3871 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3872 CP->getOffset(), AArch64II::MO_PAGE);
3873 SDValue Lo = DAG.getTargetConstantPool(
3874 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3875 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3877 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3878 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3882 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3883 SelectionDAG &DAG) const {
3884 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3885 EVT PtrVT = getPointerTy();
3887 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3888 !Subtarget->isTargetMachO()) {
3889 const unsigned char MO_NC = AArch64II::MO_NC;
3891 AArch64ISD::WrapperLarge, DL, PtrVT,
3892 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3893 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3894 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3895 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3897 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3898 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3900 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3901 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3905 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3906 SelectionDAG &DAG) const {
3907 AArch64FunctionInfo *FuncInfo =
3908 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3912 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3913 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3914 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3915 MachinePointerInfo(SV), false, false, 0);
3918 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3919 SelectionDAG &DAG) const {
3920 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3921 // Standard, section B.3.
3922 MachineFunction &MF = DAG.getMachineFunction();
3923 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3926 SDValue Chain = Op.getOperand(0);
3927 SDValue VAList = Op.getOperand(1);
3928 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3929 SmallVector<SDValue, 4> MemOps;
3931 // void *__stack at offset 0
3933 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3934 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3935 MachinePointerInfo(SV), false, false, 8));
3937 // void *__gr_top at offset 8
3938 int GPRSize = FuncInfo->getVarArgsGPRSize();
3940 SDValue GRTop, GRTopAddr;
3942 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3943 DAG.getConstant(8, DL, getPointerTy()));
3945 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3946 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3947 DAG.getConstant(GPRSize, DL, getPointerTy()));
3949 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3950 MachinePointerInfo(SV, 8), false, false, 8));
3953 // void *__vr_top at offset 16
3954 int FPRSize = FuncInfo->getVarArgsFPRSize();
3956 SDValue VRTop, VRTopAddr;
3957 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3958 DAG.getConstant(16, DL, getPointerTy()));
3960 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3961 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3962 DAG.getConstant(FPRSize, DL, getPointerTy()));
3964 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3965 MachinePointerInfo(SV, 16), false, false, 8));
3968 // int __gr_offs at offset 24
3969 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3970 DAG.getConstant(24, DL, getPointerTy()));
3971 MemOps.push_back(DAG.getStore(Chain, DL,
3972 DAG.getConstant(-GPRSize, DL, MVT::i32),
3973 GROffsAddr, MachinePointerInfo(SV, 24), false,
3976 // int __vr_offs at offset 28
3977 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3978 DAG.getConstant(28, DL, getPointerTy()));
3979 MemOps.push_back(DAG.getStore(Chain, DL,
3980 DAG.getConstant(-FPRSize, DL, MVT::i32),
3981 VROffsAddr, MachinePointerInfo(SV, 28), false,
3984 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3987 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3988 SelectionDAG &DAG) const {
3989 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3990 : LowerAAPCS_VASTART(Op, DAG);
3993 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3994 SelectionDAG &DAG) const {
3995 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3998 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3999 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4000 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4002 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4004 DAG.getConstant(VaListSize, DL, MVT::i32),
4005 8, false, false, false, MachinePointerInfo(DestSV),
4006 MachinePointerInfo(SrcSV));
4009 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4010 assert(Subtarget->isTargetDarwin() &&
4011 "automatic va_arg instruction only works on Darwin");
4013 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4014 EVT VT = Op.getValueType();
4016 SDValue Chain = Op.getOperand(0);
4017 SDValue Addr = Op.getOperand(1);
4018 unsigned Align = Op.getConstantOperandVal(3);
4020 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
4021 MachinePointerInfo(V), false, false, false, 0);
4022 Chain = VAList.getValue(1);
4025 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4026 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4027 DAG.getConstant(Align - 1, DL, getPointerTy()));
4028 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
4029 DAG.getConstant(-(int64_t)Align, DL, getPointerTy()));
4032 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4033 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4035 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4036 // up to 64 bits. At the very least, we have to increase the striding of the
4037 // vaargs list to match this, and for FP values we need to introduce
4038 // FP_ROUND nodes as well.
4039 if (VT.isInteger() && !VT.isVector())
4041 bool NeedFPTrunc = false;
4042 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4047 // Increment the pointer, VAList, to the next vaarg
4048 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4049 DAG.getConstant(ArgSize, DL, getPointerTy()));
4050 // Store the incremented VAList to the legalized pointer
4051 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4054 // Load the actual argument out of the pointer VAList
4056 // Load the value as an f64.
4057 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4058 MachinePointerInfo(), false, false, false, 0);
4059 // Round the value down to an f32.
4060 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4061 DAG.getIntPtrConstant(1, DL));
4062 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4063 // Merge the rounded value with the chain output of the load.
4064 return DAG.getMergeValues(Ops, DL);
4067 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4071 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4072 SelectionDAG &DAG) const {
4073 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4074 MFI->setFrameAddressIsTaken(true);
4076 EVT VT = Op.getValueType();
4078 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4080 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4082 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4083 MachinePointerInfo(), false, false, false, 0);
4087 // FIXME? Maybe this could be a TableGen attribute on some registers and
4088 // this table could be generated automatically from RegInfo.
4089 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4091 unsigned Reg = StringSwitch<unsigned>(RegName)
4092 .Case("sp", AArch64::SP)
4096 report_fatal_error("Invalid register name global variable");
4099 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4100 SelectionDAG &DAG) const {
4101 MachineFunction &MF = DAG.getMachineFunction();
4102 MachineFrameInfo *MFI = MF.getFrameInfo();
4103 MFI->setReturnAddressIsTaken(true);
4105 EVT VT = Op.getValueType();
4107 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4109 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4110 SDValue Offset = DAG.getConstant(8, DL, getPointerTy());
4111 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4112 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4113 MachinePointerInfo(), false, false, false, 0);
4116 // Return LR, which contains the return address. Mark it an implicit live-in.
4117 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4118 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4121 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4122 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4123 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4124 SelectionDAG &DAG) const {
4125 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4126 EVT VT = Op.getValueType();
4127 unsigned VTBits = VT.getSizeInBits();
4129 SDValue ShOpLo = Op.getOperand(0);
4130 SDValue ShOpHi = Op.getOperand(1);
4131 SDValue ShAmt = Op.getOperand(2);
4133 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4135 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4137 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4138 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4139 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4140 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4141 DAG.getConstant(VTBits, dl, MVT::i64));
4142 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4144 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4145 ISD::SETGE, dl, DAG);
4146 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4148 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4149 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4151 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4153 // AArch64 shifts larger than the register width are wrapped rather than
4154 // clamped, so we can't just emit "hi >> x".
4155 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4156 SDValue TrueValHi = Opc == ISD::SRA
4157 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4158 DAG.getConstant(VTBits - 1, dl,
4160 : DAG.getConstant(0, dl, VT);
4162 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4164 SDValue Ops[2] = { Lo, Hi };
4165 return DAG.getMergeValues(Ops, dl);
4168 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4169 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4170 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4171 SelectionDAG &DAG) const {
4172 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4173 EVT VT = Op.getValueType();
4174 unsigned VTBits = VT.getSizeInBits();
4176 SDValue ShOpLo = Op.getOperand(0);
4177 SDValue ShOpHi = Op.getOperand(1);
4178 SDValue ShAmt = Op.getOperand(2);
4181 assert(Op.getOpcode() == ISD::SHL_PARTS);
4182 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4183 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4184 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4185 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4186 DAG.getConstant(VTBits, dl, MVT::i64));
4187 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4188 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4190 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4192 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4193 ISD::SETGE, dl, DAG);
4194 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4196 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4198 // AArch64 shifts of larger than register sizes are wrapped rather than
4199 // clamped, so we can't just emit "lo << a" if a is too big.
4200 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4201 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4203 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4205 SDValue Ops[2] = { Lo, Hi };
4206 return DAG.getMergeValues(Ops, dl);
4209 bool AArch64TargetLowering::isOffsetFoldingLegal(
4210 const GlobalAddressSDNode *GA) const {
4211 // The AArch64 target doesn't support folding offsets into global addresses.
4215 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4216 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4217 // FIXME: We should be able to handle f128 as well with a clever lowering.
4218 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4222 return AArch64_AM::getFP64Imm(Imm) != -1;
4223 else if (VT == MVT::f32)
4224 return AArch64_AM::getFP32Imm(Imm) != -1;
4228 //===----------------------------------------------------------------------===//
4229 // AArch64 Optimization Hooks
4230 //===----------------------------------------------------------------------===//
4232 //===----------------------------------------------------------------------===//
4233 // AArch64 Inline Assembly Support
4234 //===----------------------------------------------------------------------===//
4236 // Table of Constraints
4237 // TODO: This is the current set of constraints supported by ARM for the
4238 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4240 // r - A general register
4241 // w - An FP/SIMD register of some size in the range v0-v31
4242 // x - An FP/SIMD register of some size in the range v0-v15
4243 // I - Constant that can be used with an ADD instruction
4244 // J - Constant that can be used with a SUB instruction
4245 // K - Constant that can be used with a 32-bit logical instruction
4246 // L - Constant that can be used with a 64-bit logical instruction
4247 // M - Constant that can be used as a 32-bit MOV immediate
4248 // N - Constant that can be used as a 64-bit MOV immediate
4249 // Q - A memory reference with base register and no offset
4250 // S - A symbolic address
4251 // Y - Floating point constant zero
4252 // Z - Integer constant zero
4254 // Note that general register operands will be output using their 64-bit x
4255 // register name, whatever the size of the variable, unless the asm operand
4256 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4257 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4260 /// getConstraintType - Given a constraint letter, return the type of
4261 /// constraint it is for this target.
4262 AArch64TargetLowering::ConstraintType
4263 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4264 if (Constraint.size() == 1) {
4265 switch (Constraint[0]) {
4272 return C_RegisterClass;
4273 // An address with a single base register. Due to the way we
4274 // currently handle addresses it is the same as 'r'.
4279 return TargetLowering::getConstraintType(Constraint);
4282 /// Examine constraint type and operand type and determine a weight value.
4283 /// This object must already have been set up with the operand type
4284 /// and the current alternative constraint selected.
4285 TargetLowering::ConstraintWeight
4286 AArch64TargetLowering::getSingleConstraintMatchWeight(
4287 AsmOperandInfo &info, const char *constraint) const {
4288 ConstraintWeight weight = CW_Invalid;
4289 Value *CallOperandVal = info.CallOperandVal;
4290 // If we don't have a value, we can't do a match,
4291 // but allow it at the lowest weight.
4292 if (!CallOperandVal)
4294 Type *type = CallOperandVal->getType();
4295 // Look at the constraint type.
4296 switch (*constraint) {
4298 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4302 if (type->isFloatingPointTy() || type->isVectorTy())
4303 weight = CW_Register;
4306 weight = CW_Constant;
4312 std::pair<unsigned, const TargetRegisterClass *>
4313 AArch64TargetLowering::getRegForInlineAsmConstraint(
4314 const TargetRegisterInfo *TRI, const std::string &Constraint,
4316 if (Constraint.size() == 1) {
4317 switch (Constraint[0]) {
4319 if (VT.getSizeInBits() == 64)
4320 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4321 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4324 return std::make_pair(0U, &AArch64::FPR32RegClass);
4325 if (VT.getSizeInBits() == 64)
4326 return std::make_pair(0U, &AArch64::FPR64RegClass);
4327 if (VT.getSizeInBits() == 128)
4328 return std::make_pair(0U, &AArch64::FPR128RegClass);
4330 // The instructions that this constraint is designed for can
4331 // only take 128-bit registers so just use that regclass.
4333 if (VT.getSizeInBits() == 128)
4334 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4338 if (StringRef("{cc}").equals_lower(Constraint))
4339 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4341 // Use the default implementation in TargetLowering to convert the register
4342 // constraint into a member of a register class.
4343 std::pair<unsigned, const TargetRegisterClass *> Res;
4344 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4346 // Not found as a standard register?
4348 unsigned Size = Constraint.size();
4349 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4350 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4351 const std::string Reg =
4352 std::string(&Constraint[2], &Constraint[Size - 1]);
4353 int RegNo = atoi(Reg.c_str());
4354 if (RegNo >= 0 && RegNo <= 31) {
4355 // v0 - v31 are aliases of q0 - q31.
4356 // By default we'll emit v0-v31 for this unless there's a modifier where
4357 // we'll emit the correct register as well.
4358 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4359 Res.second = &AArch64::FPR128RegClass;
4367 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4368 /// vector. If it is invalid, don't add anything to Ops.
4369 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4370 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4371 SelectionDAG &DAG) const {
4374 // Currently only support length 1 constraints.
4375 if (Constraint.length() != 1)
4378 char ConstraintLetter = Constraint[0];
4379 switch (ConstraintLetter) {
4383 // This set of constraints deal with valid constants for various instructions.
4384 // Validate and return a target constant for them if we can.
4386 // 'z' maps to xzr or wzr so it needs an input of 0.
4387 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4388 if (!C || C->getZExtValue() != 0)
4391 if (Op.getValueType() == MVT::i64)
4392 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4394 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4404 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4408 // Grab the value and do some validation.
4409 uint64_t CVal = C->getZExtValue();
4410 switch (ConstraintLetter) {
4411 // The I constraint applies only to simple ADD or SUB immediate operands:
4412 // i.e. 0 to 4095 with optional shift by 12
4413 // The J constraint applies only to ADD or SUB immediates that would be
4414 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4415 // instruction [or vice versa], in other words -1 to -4095 with optional
4416 // left shift by 12.
4418 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4422 uint64_t NVal = -C->getSExtValue();
4423 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4424 CVal = C->getSExtValue();
4429 // The K and L constraints apply *only* to logical immediates, including
4430 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4431 // been removed and MOV should be used). So these constraints have to
4432 // distinguish between bit patterns that are valid 32-bit or 64-bit
4433 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4434 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4437 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4441 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4444 // The M and N constraints are a superset of K and L respectively, for use
4445 // with the MOV (immediate) alias. As well as the logical immediates they
4446 // also match 32 or 64-bit immediates that can be loaded either using a
4447 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4448 // (M) or 64-bit 0x1234000000000000 (N) etc.
4449 // As a note some of this code is liberally stolen from the asm parser.
4451 if (!isUInt<32>(CVal))
4453 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4455 if ((CVal & 0xFFFF) == CVal)
4457 if ((CVal & 0xFFFF0000ULL) == CVal)
4459 uint64_t NCVal = ~(uint32_t)CVal;
4460 if ((NCVal & 0xFFFFULL) == NCVal)
4462 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4467 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4469 if ((CVal & 0xFFFFULL) == CVal)
4471 if ((CVal & 0xFFFF0000ULL) == CVal)
4473 if ((CVal & 0xFFFF00000000ULL) == CVal)
4475 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4477 uint64_t NCVal = ~CVal;
4478 if ((NCVal & 0xFFFFULL) == NCVal)
4480 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4482 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4484 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4492 // All assembler immediates are 64-bit integers.
4493 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4497 if (Result.getNode()) {
4498 Ops.push_back(Result);
4502 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4505 //===----------------------------------------------------------------------===//
4506 // AArch64 Advanced SIMD Support
4507 //===----------------------------------------------------------------------===//
4509 /// WidenVector - Given a value in the V64 register class, produce the
4510 /// equivalent value in the V128 register class.
4511 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4512 EVT VT = V64Reg.getValueType();
4513 unsigned NarrowSize = VT.getVectorNumElements();
4514 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4515 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4518 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4519 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4522 /// getExtFactor - Determine the adjustment factor for the position when
4523 /// generating an "extract from vector registers" instruction.
4524 static unsigned getExtFactor(SDValue &V) {
4525 EVT EltType = V.getValueType().getVectorElementType();
4526 return EltType.getSizeInBits() / 8;
4529 /// NarrowVector - Given a value in the V128 register class, produce the
4530 /// equivalent value in the V64 register class.
4531 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4532 EVT VT = V128Reg.getValueType();
4533 unsigned WideSize = VT.getVectorNumElements();
4534 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4535 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4538 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4541 // Gather data to see if the operation can be modelled as a
4542 // shuffle in combination with VEXTs.
4543 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4544 SelectionDAG &DAG) const {
4545 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4547 EVT VT = Op.getValueType();
4548 unsigned NumElts = VT.getVectorNumElements();
4550 struct ShuffleSourceInfo {
4555 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4556 // be compatible with the shuffle we intend to construct. As a result
4557 // ShuffleVec will be some sliding window into the original Vec.
4560 // Code should guarantee that element i in Vec starts at element "WindowBase
4561 // + i * WindowScale in ShuffleVec".
4565 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4566 ShuffleSourceInfo(SDValue Vec)
4567 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4571 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4573 SmallVector<ShuffleSourceInfo, 2> Sources;
4574 for (unsigned i = 0; i < NumElts; ++i) {
4575 SDValue V = Op.getOperand(i);
4576 if (V.getOpcode() == ISD::UNDEF)
4578 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4579 // A shuffle can only come from building a vector from various
4580 // elements of other vectors.
4584 // Add this element source to the list if it's not already there.
4585 SDValue SourceVec = V.getOperand(0);
4586 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4587 if (Source == Sources.end())
4588 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4590 // Update the minimum and maximum lane number seen.
4591 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4592 Source->MinElt = std::min(Source->MinElt, EltNo);
4593 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4596 // Currently only do something sane when at most two source vectors
4598 if (Sources.size() > 2)
4601 // Find out the smallest element size among result and two sources, and use
4602 // it as element size to build the shuffle_vector.
4603 EVT SmallestEltTy = VT.getVectorElementType();
4604 for (auto &Source : Sources) {
4605 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4606 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4607 SmallestEltTy = SrcEltTy;
4610 unsigned ResMultiplier =
4611 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4612 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4613 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4615 // If the source vector is too wide or too narrow, we may nevertheless be able
4616 // to construct a compatible shuffle either by concatenating it with UNDEF or
4617 // extracting a suitable range of elements.
4618 for (auto &Src : Sources) {
4619 EVT SrcVT = Src.ShuffleVec.getValueType();
4621 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4624 // This stage of the search produces a source with the same element type as
4625 // the original, but with a total width matching the BUILD_VECTOR output.
4626 EVT EltVT = SrcVT.getVectorElementType();
4627 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4628 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4630 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4631 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4632 // We can pad out the smaller vector for free, so if it's part of a
4635 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4636 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4640 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4642 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4643 // Span too large for a VEXT to cope
4647 if (Src.MinElt >= NumSrcElts) {
4648 // The extraction can just take the second half
4650 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4651 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4652 Src.WindowBase = -NumSrcElts;
4653 } else if (Src.MaxElt < NumSrcElts) {
4654 // The extraction can just take the first half
4656 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4657 DAG.getConstant(0, dl, MVT::i64));
4659 // An actual VEXT is needed
4661 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4662 DAG.getConstant(0, dl, MVT::i64));
4664 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4665 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4666 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4668 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4670 DAG.getConstant(Imm, dl, MVT::i32));
4671 Src.WindowBase = -Src.MinElt;
4675 // Another possible incompatibility occurs from the vector element types. We
4676 // can fix this by bitcasting the source vectors to the same type we intend
4678 for (auto &Src : Sources) {
4679 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4680 if (SrcEltTy == SmallestEltTy)
4682 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4683 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4684 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4685 Src.WindowBase *= Src.WindowScale;
4688 // Final sanity check before we try to actually produce a shuffle.
4690 for (auto Src : Sources)
4691 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4694 // The stars all align, our next step is to produce the mask for the shuffle.
4695 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4696 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4697 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4698 SDValue Entry = Op.getOperand(i);
4699 if (Entry.getOpcode() == ISD::UNDEF)
4702 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4703 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4705 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4706 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4708 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4709 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4710 VT.getVectorElementType().getSizeInBits());
4711 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4713 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4714 // starting at the appropriate offset.
4715 int *LaneMask = &Mask[i * ResMultiplier];
4717 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4718 ExtractBase += NumElts * (Src - Sources.begin());
4719 for (int j = 0; j < LanesDefined; ++j)
4720 LaneMask[j] = ExtractBase + j;
4723 // Final check before we try to produce nonsense...
4724 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4727 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4728 for (unsigned i = 0; i < Sources.size(); ++i)
4729 ShuffleOps[i] = Sources[i].ShuffleVec;
4731 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4732 ShuffleOps[1], &Mask[0]);
4733 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4736 // check if an EXT instruction can handle the shuffle mask when the
4737 // vector sources of the shuffle are the same.
4738 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4739 unsigned NumElts = VT.getVectorNumElements();
4741 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4747 // If this is a VEXT shuffle, the immediate value is the index of the first
4748 // element. The other shuffle indices must be the successive elements after
4750 unsigned ExpectedElt = Imm;
4751 for (unsigned i = 1; i < NumElts; ++i) {
4752 // Increment the expected index. If it wraps around, just follow it
4753 // back to index zero and keep going.
4755 if (ExpectedElt == NumElts)
4759 continue; // ignore UNDEF indices
4760 if (ExpectedElt != static_cast<unsigned>(M[i]))
4767 // check if an EXT instruction can handle the shuffle mask when the
4768 // vector sources of the shuffle are different.
4769 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4771 // Look for the first non-undef element.
4772 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4773 [](int Elt) {return Elt >= 0;});
4775 // Benefit form APInt to handle overflow when calculating expected element.
4776 unsigned NumElts = VT.getVectorNumElements();
4777 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4778 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4779 // The following shuffle indices must be the successive elements after the
4780 // first real element.
4781 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4782 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4783 if (FirstWrongElt != M.end())
4786 // The index of an EXT is the first element if it is not UNDEF.
4787 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4788 // value of the first element. E.g.
4789 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4790 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4791 // ExpectedElt is the last mask index plus 1.
4792 Imm = ExpectedElt.getZExtValue();
4794 // There are two difference cases requiring to reverse input vectors.
4795 // For example, for vector <4 x i32> we have the following cases,
4796 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4797 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4798 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4799 // to reverse two input vectors.
4808 /// isREVMask - Check if a vector shuffle corresponds to a REV
4809 /// instruction with the specified blocksize. (The order of the elements
4810 /// within each block of the vector is reversed.)
4811 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4812 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4813 "Only possible block sizes for REV are: 16, 32, 64");
4815 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4819 unsigned NumElts = VT.getVectorNumElements();
4820 unsigned BlockElts = M[0] + 1;
4821 // If the first shuffle index is UNDEF, be optimistic.
4823 BlockElts = BlockSize / EltSz;
4825 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4828 for (unsigned i = 0; i < NumElts; ++i) {
4830 continue; // ignore UNDEF indices
4831 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4838 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4839 unsigned NumElts = VT.getVectorNumElements();
4840 WhichResult = (M[0] == 0 ? 0 : 1);
4841 unsigned Idx = WhichResult * NumElts / 2;
4842 for (unsigned i = 0; i != NumElts; i += 2) {
4843 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4844 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4852 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4853 unsigned NumElts = VT.getVectorNumElements();
4854 WhichResult = (M[0] == 0 ? 0 : 1);
4855 for (unsigned i = 0; i != NumElts; ++i) {
4857 continue; // ignore UNDEF indices
4858 if ((unsigned)M[i] != 2 * i + WhichResult)
4865 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4866 unsigned NumElts = VT.getVectorNumElements();
4867 WhichResult = (M[0] == 0 ? 0 : 1);
4868 for (unsigned i = 0; i < NumElts; i += 2) {
4869 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4870 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4876 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4877 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4878 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4879 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4880 unsigned NumElts = VT.getVectorNumElements();
4881 WhichResult = (M[0] == 0 ? 0 : 1);
4882 unsigned Idx = WhichResult * NumElts / 2;
4883 for (unsigned i = 0; i != NumElts; i += 2) {
4884 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4885 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4893 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4894 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4895 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4896 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4897 unsigned Half = VT.getVectorNumElements() / 2;
4898 WhichResult = (M[0] == 0 ? 0 : 1);
4899 for (unsigned j = 0; j != 2; ++j) {
4900 unsigned Idx = WhichResult;
4901 for (unsigned i = 0; i != Half; ++i) {
4902 int MIdx = M[i + j * Half];
4903 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4912 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4913 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4914 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4915 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4916 unsigned NumElts = VT.getVectorNumElements();
4917 WhichResult = (M[0] == 0 ? 0 : 1);
4918 for (unsigned i = 0; i < NumElts; i += 2) {
4919 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4920 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4926 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4927 bool &DstIsLeft, int &Anomaly) {
4928 if (M.size() != static_cast<size_t>(NumInputElements))
4931 int NumLHSMatch = 0, NumRHSMatch = 0;
4932 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4934 for (int i = 0; i < NumInputElements; ++i) {
4944 LastLHSMismatch = i;
4946 if (M[i] == i + NumInputElements)
4949 LastRHSMismatch = i;
4952 if (NumLHSMatch == NumInputElements - 1) {
4954 Anomaly = LastLHSMismatch;
4956 } else if (NumRHSMatch == NumInputElements - 1) {
4958 Anomaly = LastRHSMismatch;
4965 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4966 if (VT.getSizeInBits() != 128)
4969 unsigned NumElts = VT.getVectorNumElements();
4971 for (int I = 0, E = NumElts / 2; I != E; I++) {
4976 int Offset = NumElts / 2;
4977 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4978 if (Mask[I] != I + SplitLHS * Offset)
4985 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4987 EVT VT = Op.getValueType();
4988 SDValue V0 = Op.getOperand(0);
4989 SDValue V1 = Op.getOperand(1);
4990 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4992 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4993 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4996 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4998 if (!isConcatMask(Mask, VT, SplitV0))
5001 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5002 VT.getVectorNumElements() / 2);
5004 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5005 DAG.getConstant(0, DL, MVT::i64));
5007 if (V1.getValueType().getSizeInBits() == 128) {
5008 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5009 DAG.getConstant(0, DL, MVT::i64));
5011 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5014 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5015 /// the specified operations to build the shuffle.
5016 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5017 SDValue RHS, SelectionDAG &DAG,
5019 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5020 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5021 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5024 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5033 OP_VUZPL, // VUZP, left result
5034 OP_VUZPR, // VUZP, right result
5035 OP_VZIPL, // VZIP, left result
5036 OP_VZIPR, // VZIP, right result
5037 OP_VTRNL, // VTRN, left result
5038 OP_VTRNR // VTRN, right result
5041 if (OpNum == OP_COPY) {
5042 if (LHSID == (1 * 9 + 2) * 9 + 3)
5044 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5048 SDValue OpLHS, OpRHS;
5049 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5050 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5051 EVT VT = OpLHS.getValueType();
5055 llvm_unreachable("Unknown shuffle opcode!");
5057 // VREV divides the vector in half and swaps within the half.
5058 if (VT.getVectorElementType() == MVT::i32 ||
5059 VT.getVectorElementType() == MVT::f32)
5060 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5061 // vrev <4 x i16> -> REV32
5062 if (VT.getVectorElementType() == MVT::i16 ||
5063 VT.getVectorElementType() == MVT::f16)
5064 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5065 // vrev <4 x i8> -> REV16
5066 assert(VT.getVectorElementType() == MVT::i8);
5067 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5072 EVT EltTy = VT.getVectorElementType();
5074 if (EltTy == MVT::i8)
5075 Opcode = AArch64ISD::DUPLANE8;
5076 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5077 Opcode = AArch64ISD::DUPLANE16;
5078 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5079 Opcode = AArch64ISD::DUPLANE32;
5080 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5081 Opcode = AArch64ISD::DUPLANE64;
5083 llvm_unreachable("Invalid vector element type?");
5085 if (VT.getSizeInBits() == 64)
5086 OpLHS = WidenVector(OpLHS, DAG);
5087 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5088 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5093 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5094 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5095 DAG.getConstant(Imm, dl, MVT::i32));
5098 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5101 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5104 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5107 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5110 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5113 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5118 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5119 SelectionDAG &DAG) {
5120 // Check to see if we can use the TBL instruction.
5121 SDValue V1 = Op.getOperand(0);
5122 SDValue V2 = Op.getOperand(1);
5125 EVT EltVT = Op.getValueType().getVectorElementType();
5126 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5128 SmallVector<SDValue, 8> TBLMask;
5129 for (int Val : ShuffleMask) {
5130 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5131 unsigned Offset = Byte + Val * BytesPerElt;
5132 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5136 MVT IndexVT = MVT::v8i8;
5137 unsigned IndexLen = 8;
5138 if (Op.getValueType().getSizeInBits() == 128) {
5139 IndexVT = MVT::v16i8;
5143 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5144 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5147 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5149 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5150 Shuffle = DAG.getNode(
5151 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5152 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5153 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5154 makeArrayRef(TBLMask.data(), IndexLen)));
5156 if (IndexLen == 8) {
5157 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5158 Shuffle = DAG.getNode(
5159 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5160 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5161 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5162 makeArrayRef(TBLMask.data(), IndexLen)));
5164 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5165 // cannot currently represent the register constraints on the input
5167 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5168 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5169 // &TBLMask[0], IndexLen));
5170 Shuffle = DAG.getNode(
5171 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5172 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5174 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5175 makeArrayRef(TBLMask.data(), IndexLen)));
5178 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5181 static unsigned getDUPLANEOp(EVT EltType) {
5182 if (EltType == MVT::i8)
5183 return AArch64ISD::DUPLANE8;
5184 if (EltType == MVT::i16 || EltType == MVT::f16)
5185 return AArch64ISD::DUPLANE16;
5186 if (EltType == MVT::i32 || EltType == MVT::f32)
5187 return AArch64ISD::DUPLANE32;
5188 if (EltType == MVT::i64 || EltType == MVT::f64)
5189 return AArch64ISD::DUPLANE64;
5191 llvm_unreachable("Invalid vector element type?");
5194 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5195 SelectionDAG &DAG) const {
5197 EVT VT = Op.getValueType();
5199 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5201 // Convert shuffles that are directly supported on NEON to target-specific
5202 // DAG nodes, instead of keeping them as shuffles and matching them again
5203 // during code selection. This is more efficient and avoids the possibility
5204 // of inconsistencies between legalization and selection.
5205 ArrayRef<int> ShuffleMask = SVN->getMask();
5207 SDValue V1 = Op.getOperand(0);
5208 SDValue V2 = Op.getOperand(1);
5210 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5211 V1.getValueType().getSimpleVT())) {
5212 int Lane = SVN->getSplatIndex();
5213 // If this is undef splat, generate it via "just" vdup, if possible.
5217 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5218 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5220 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5221 // constant. If so, we can just reference the lane's definition directly.
5222 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5223 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5224 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5226 // Otherwise, duplicate from the lane of the input vector.
5227 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5229 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5230 // to make a vector of the same size as this SHUFFLE. We can ignore the
5231 // extract entirely, and canonicalise the concat using WidenVector.
5232 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5233 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5234 V1 = V1.getOperand(0);
5235 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5236 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5237 Lane -= Idx * VT.getVectorNumElements() / 2;
5238 V1 = WidenVector(V1.getOperand(Idx), DAG);
5239 } else if (VT.getSizeInBits() == 64)
5240 V1 = WidenVector(V1, DAG);
5242 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5245 if (isREVMask(ShuffleMask, VT, 64))
5246 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5247 if (isREVMask(ShuffleMask, VT, 32))
5248 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5249 if (isREVMask(ShuffleMask, VT, 16))
5250 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5252 bool ReverseEXT = false;
5254 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5257 Imm *= getExtFactor(V1);
5258 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5259 DAG.getConstant(Imm, dl, MVT::i32));
5260 } else if (V2->getOpcode() == ISD::UNDEF &&
5261 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5262 Imm *= getExtFactor(V1);
5263 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5264 DAG.getConstant(Imm, dl, MVT::i32));
5267 unsigned WhichResult;
5268 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5269 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5270 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5272 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5273 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5274 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5276 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5277 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5278 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5281 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5282 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5283 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5285 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5286 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5287 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5289 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5290 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5291 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5294 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5295 if (Concat.getNode())
5300 int NumInputElements = V1.getValueType().getVectorNumElements();
5301 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5302 SDValue DstVec = DstIsLeft ? V1 : V2;
5303 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5305 SDValue SrcVec = V1;
5306 int SrcLane = ShuffleMask[Anomaly];
5307 if (SrcLane >= NumInputElements) {
5309 SrcLane -= VT.getVectorNumElements();
5311 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5313 EVT ScalarVT = VT.getVectorElementType();
5315 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5316 ScalarVT = MVT::i32;
5319 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5320 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5324 // If the shuffle is not directly supported and it has 4 elements, use
5325 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5326 unsigned NumElts = VT.getVectorNumElements();
5328 unsigned PFIndexes[4];
5329 for (unsigned i = 0; i != 4; ++i) {
5330 if (ShuffleMask[i] < 0)
5333 PFIndexes[i] = ShuffleMask[i];
5336 // Compute the index in the perfect shuffle table.
5337 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5338 PFIndexes[2] * 9 + PFIndexes[3];
5339 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5340 unsigned Cost = (PFEntry >> 30);
5343 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5346 return GenerateTBL(Op, ShuffleMask, DAG);
5349 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5351 EVT VT = BVN->getValueType(0);
5352 APInt SplatBits, SplatUndef;
5353 unsigned SplatBitSize;
5355 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5356 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5358 for (unsigned i = 0; i < NumSplats; ++i) {
5359 CnstBits <<= SplatBitSize;
5360 UndefBits <<= SplatBitSize;
5361 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5362 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5371 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5372 SelectionDAG &DAG) const {
5373 BuildVectorSDNode *BVN =
5374 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5375 SDValue LHS = Op.getOperand(0);
5377 EVT VT = Op.getValueType();
5382 APInt CnstBits(VT.getSizeInBits(), 0);
5383 APInt UndefBits(VT.getSizeInBits(), 0);
5384 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5385 // We only have BIC vector immediate instruction, which is and-not.
5386 CnstBits = ~CnstBits;
5388 // We make use of a little bit of goto ickiness in order to avoid having to
5389 // duplicate the immediate matching logic for the undef toggled case.
5390 bool SecondTry = false;
5393 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5394 CnstBits = CnstBits.zextOrTrunc(64);
5395 uint64_t CnstVal = CnstBits.getZExtValue();
5397 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5400 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5401 DAG.getConstant(CnstVal, dl, MVT::i32),
5402 DAG.getConstant(0, dl, MVT::i32));
5403 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5406 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5409 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5410 DAG.getConstant(CnstVal, dl, MVT::i32),
5411 DAG.getConstant(8, dl, MVT::i32));
5412 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5415 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5416 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5417 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5418 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5419 DAG.getConstant(CnstVal, dl, MVT::i32),
5420 DAG.getConstant(16, dl, MVT::i32));
5421 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5424 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5425 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5426 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5427 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5428 DAG.getConstant(CnstVal, dl, MVT::i32),
5429 DAG.getConstant(24, dl, MVT::i32));
5430 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5433 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5434 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5435 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5436 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5437 DAG.getConstant(CnstVal, dl, MVT::i32),
5438 DAG.getConstant(0, dl, MVT::i32));
5439 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5442 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5443 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5444 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5445 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5446 DAG.getConstant(CnstVal, dl, MVT::i32),
5447 DAG.getConstant(8, dl, MVT::i32));
5448 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5455 CnstBits = ~UndefBits;
5459 // We can always fall back to a non-immediate AND.
5464 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5465 // consists of only the same constant int value, returned in reference arg
5467 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5468 uint64_t &ConstVal) {
5469 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5472 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5475 EVT VT = Bvec->getValueType(0);
5476 unsigned NumElts = VT.getVectorNumElements();
5477 for (unsigned i = 1; i < NumElts; ++i)
5478 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5480 ConstVal = FirstElt->getZExtValue();
5484 static unsigned getIntrinsicID(const SDNode *N) {
5485 unsigned Opcode = N->getOpcode();
5488 return Intrinsic::not_intrinsic;
5489 case ISD::INTRINSIC_WO_CHAIN: {
5490 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5491 if (IID < Intrinsic::num_intrinsics)
5493 return Intrinsic::not_intrinsic;
5498 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5499 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5500 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5501 // Also, logical shift right -> sri, with the same structure.
5502 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5503 EVT VT = N->getValueType(0);
5510 // Is the first op an AND?
5511 const SDValue And = N->getOperand(0);
5512 if (And.getOpcode() != ISD::AND)
5515 // Is the second op an shl or lshr?
5516 SDValue Shift = N->getOperand(1);
5517 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5518 // or AArch64ISD::VLSHR vector, #shift
5519 unsigned ShiftOpc = Shift.getOpcode();
5520 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5522 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5524 // Is the shift amount constant?
5525 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5529 // Is the and mask vector all constant?
5531 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5534 // Is C1 == ~C2, taking into account how much one can shift elements of a
5536 uint64_t C2 = C2node->getZExtValue();
5537 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5538 if (C2 > ElemSizeInBits)
5540 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5541 if ((C1 & ElemMask) != (~C2 & ElemMask))
5544 SDValue X = And.getOperand(0);
5545 SDValue Y = Shift.getOperand(0);
5548 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5550 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5551 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5552 Shift.getOperand(1));
5554 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5555 DEBUG(N->dump(&DAG));
5556 DEBUG(dbgs() << "into: \n");
5557 DEBUG(ResultSLI->dump(&DAG));
5563 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5564 SelectionDAG &DAG) const {
5565 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5566 if (EnableAArch64SlrGeneration) {
5567 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5572 BuildVectorSDNode *BVN =
5573 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5574 SDValue LHS = Op.getOperand(1);
5576 EVT VT = Op.getValueType();
5578 // OR commutes, so try swapping the operands.
5580 LHS = Op.getOperand(0);
5581 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5586 APInt CnstBits(VT.getSizeInBits(), 0);
5587 APInt UndefBits(VT.getSizeInBits(), 0);
5588 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5589 // We make use of a little bit of goto ickiness in order to avoid having to
5590 // duplicate the immediate matching logic for the undef toggled case.
5591 bool SecondTry = false;
5594 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5595 CnstBits = CnstBits.zextOrTrunc(64);
5596 uint64_t CnstVal = CnstBits.getZExtValue();
5598 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5599 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5600 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5601 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5602 DAG.getConstant(CnstVal, dl, MVT::i32),
5603 DAG.getConstant(0, dl, MVT::i32));
5604 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5607 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5608 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5609 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5610 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5611 DAG.getConstant(CnstVal, dl, MVT::i32),
5612 DAG.getConstant(8, dl, MVT::i32));
5613 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5616 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5617 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5618 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5619 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5620 DAG.getConstant(CnstVal, dl, MVT::i32),
5621 DAG.getConstant(16, dl, MVT::i32));
5622 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5625 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5626 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5627 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5628 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5629 DAG.getConstant(CnstVal, dl, MVT::i32),
5630 DAG.getConstant(24, dl, MVT::i32));
5631 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5634 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5635 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5636 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5637 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5638 DAG.getConstant(CnstVal, dl, MVT::i32),
5639 DAG.getConstant(0, dl, MVT::i32));
5640 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5643 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5644 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5645 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5646 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5647 DAG.getConstant(CnstVal, dl, MVT::i32),
5648 DAG.getConstant(8, dl, MVT::i32));
5649 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5656 CnstBits = UndefBits;
5660 // We can always fall back to a non-immediate OR.
5665 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5666 // be truncated to fit element width.
5667 static SDValue NormalizeBuildVector(SDValue Op,
5668 SelectionDAG &DAG) {
5669 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5671 EVT VT = Op.getValueType();
5672 EVT EltTy= VT.getVectorElementType();
5674 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5677 SmallVector<SDValue, 16> Ops;
5678 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5679 SDValue Lane = Op.getOperand(I);
5680 if (Lane.getOpcode() == ISD::Constant) {
5681 APInt LowBits(EltTy.getSizeInBits(),
5682 cast<ConstantSDNode>(Lane)->getZExtValue());
5683 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5685 Ops.push_back(Lane);
5687 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5690 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5691 SelectionDAG &DAG) const {
5693 EVT VT = Op.getValueType();
5694 Op = NormalizeBuildVector(Op, DAG);
5695 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5697 APInt CnstBits(VT.getSizeInBits(), 0);
5698 APInt UndefBits(VT.getSizeInBits(), 0);
5699 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5700 // We make use of a little bit of goto ickiness in order to avoid having to
5701 // duplicate the immediate matching logic for the undef toggled case.
5702 bool SecondTry = false;
5705 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5706 CnstBits = CnstBits.zextOrTrunc(64);
5707 uint64_t CnstVal = CnstBits.getZExtValue();
5709 // Certain magic vector constants (used to express things like NOT
5710 // and NEG) are passed through unmodified. This allows codegen patterns
5711 // for these operations to match. Special-purpose patterns will lower
5712 // these immediates to MOVIs if it proves necessary.
5713 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5716 // The many faces of MOVI...
5717 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5718 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5719 if (VT.getSizeInBits() == 128) {
5720 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5721 DAG.getConstant(CnstVal, dl, MVT::i32));
5722 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5725 // Support the V64 version via subregister insertion.
5726 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5727 DAG.getConstant(CnstVal, dl, MVT::i32));
5728 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5731 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5732 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5733 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5734 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5735 DAG.getConstant(CnstVal, dl, MVT::i32),
5736 DAG.getConstant(0, dl, MVT::i32));
5737 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5740 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5741 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5742 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5743 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5744 DAG.getConstant(CnstVal, dl, MVT::i32),
5745 DAG.getConstant(8, dl, MVT::i32));
5746 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5749 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5750 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5751 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5752 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5753 DAG.getConstant(CnstVal, dl, MVT::i32),
5754 DAG.getConstant(16, dl, MVT::i32));
5755 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5758 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5759 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5760 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5761 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5762 DAG.getConstant(CnstVal, dl, MVT::i32),
5763 DAG.getConstant(24, dl, MVT::i32));
5764 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5767 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5768 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5769 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5770 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5771 DAG.getConstant(CnstVal, dl, MVT::i32),
5772 DAG.getConstant(0, dl, MVT::i32));
5773 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5776 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5777 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5778 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5779 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5780 DAG.getConstant(CnstVal, dl, MVT::i32),
5781 DAG.getConstant(8, dl, MVT::i32));
5782 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5785 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5786 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5787 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5788 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5789 DAG.getConstant(CnstVal, dl, MVT::i32),
5790 DAG.getConstant(264, dl, MVT::i32));
5791 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5794 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5795 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5796 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5797 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5798 DAG.getConstant(CnstVal, dl, MVT::i32),
5799 DAG.getConstant(272, dl, MVT::i32));
5800 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5803 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5804 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5805 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5806 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5807 DAG.getConstant(CnstVal, dl, MVT::i32));
5808 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5811 // The few faces of FMOV...
5812 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5813 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5814 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5815 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5816 DAG.getConstant(CnstVal, dl, MVT::i32));
5817 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5820 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5821 VT.getSizeInBits() == 128) {
5822 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5823 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5824 DAG.getConstant(CnstVal, dl, MVT::i32));
5825 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5828 // The many faces of MVNI...
5830 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5831 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5832 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5833 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5834 DAG.getConstant(CnstVal, dl, MVT::i32),
5835 DAG.getConstant(0, dl, MVT::i32));
5836 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5839 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5840 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5841 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5842 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5843 DAG.getConstant(CnstVal, dl, MVT::i32),
5844 DAG.getConstant(8, dl, MVT::i32));
5845 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5848 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5849 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5850 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5851 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5852 DAG.getConstant(CnstVal, dl, MVT::i32),
5853 DAG.getConstant(16, dl, MVT::i32));
5854 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5857 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5858 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5859 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5860 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5861 DAG.getConstant(CnstVal, dl, MVT::i32),
5862 DAG.getConstant(24, dl, MVT::i32));
5863 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5866 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5867 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5868 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5869 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5870 DAG.getConstant(CnstVal, dl, MVT::i32),
5871 DAG.getConstant(0, dl, MVT::i32));
5872 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5875 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5876 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5877 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5878 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5879 DAG.getConstant(CnstVal, dl, MVT::i32),
5880 DAG.getConstant(8, dl, MVT::i32));
5881 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5884 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5885 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5886 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5887 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5888 DAG.getConstant(CnstVal, dl, MVT::i32),
5889 DAG.getConstant(264, dl, MVT::i32));
5890 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5893 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5894 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5895 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5896 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5897 DAG.getConstant(CnstVal, dl, MVT::i32),
5898 DAG.getConstant(272, dl, MVT::i32));
5899 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5906 CnstBits = UndefBits;
5911 // Scan through the operands to find some interesting properties we can
5913 // 1) If only one value is used, we can use a DUP, or
5914 // 2) if only the low element is not undef, we can just insert that, or
5915 // 3) if only one constant value is used (w/ some non-constant lanes),
5916 // we can splat the constant value into the whole vector then fill
5917 // in the non-constant lanes.
5918 // 4) FIXME: If different constant values are used, but we can intelligently
5919 // select the values we'll be overwriting for the non-constant
5920 // lanes such that we can directly materialize the vector
5921 // some other way (MOVI, e.g.), we can be sneaky.
5922 unsigned NumElts = VT.getVectorNumElements();
5923 bool isOnlyLowElement = true;
5924 bool usesOnlyOneValue = true;
5925 bool usesOnlyOneConstantValue = true;
5926 bool isConstant = true;
5927 unsigned NumConstantLanes = 0;
5929 SDValue ConstantValue;
5930 for (unsigned i = 0; i < NumElts; ++i) {
5931 SDValue V = Op.getOperand(i);
5932 if (V.getOpcode() == ISD::UNDEF)
5935 isOnlyLowElement = false;
5936 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5939 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5941 if (!ConstantValue.getNode())
5943 else if (ConstantValue != V)
5944 usesOnlyOneConstantValue = false;
5947 if (!Value.getNode())
5949 else if (V != Value)
5950 usesOnlyOneValue = false;
5953 if (!Value.getNode())
5954 return DAG.getUNDEF(VT);
5956 if (isOnlyLowElement)
5957 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5959 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5960 // i32 and try again.
5961 if (usesOnlyOneValue) {
5963 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5964 Value.getValueType() != VT)
5965 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5967 // This is actually a DUPLANExx operation, which keeps everything vectory.
5969 // DUPLANE works on 128-bit vectors, widen it if necessary.
5970 SDValue Lane = Value.getOperand(1);
5971 Value = Value.getOperand(0);
5972 if (Value.getValueType().getSizeInBits() == 64)
5973 Value = WidenVector(Value, DAG);
5975 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5976 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5979 if (VT.getVectorElementType().isFloatingPoint()) {
5980 SmallVector<SDValue, 8> Ops;
5981 EVT EltTy = VT.getVectorElementType();
5982 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5983 "Unsupported floating-point vector type");
5984 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5985 for (unsigned i = 0; i < NumElts; ++i)
5986 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5987 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5988 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5989 Val = LowerBUILD_VECTOR(Val, DAG);
5991 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5995 // If there was only one constant value used and for more than one lane,
5996 // start by splatting that value, then replace the non-constant lanes. This
5997 // is better than the default, which will perform a separate initialization
5999 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6000 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6001 // Now insert the non-constant lanes.
6002 for (unsigned i = 0; i < NumElts; ++i) {
6003 SDValue V = Op.getOperand(i);
6004 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6005 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6006 // Note that type legalization likely mucked about with the VT of the
6007 // source operand, so we may have to convert it here before inserting.
6008 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6014 // If all elements are constants and the case above didn't get hit, fall back
6015 // to the default expansion, which will generate a load from the constant
6020 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6022 SDValue shuffle = ReconstructShuffle(Op, DAG);
6023 if (shuffle != SDValue())
6027 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6028 // know the default expansion would otherwise fall back on something even
6029 // worse. For a vector with one or two non-undef values, that's
6030 // scalar_to_vector for the elements followed by a shuffle (provided the
6031 // shuffle is valid for the target) and materialization element by element
6032 // on the stack followed by a load for everything else.
6033 if (!isConstant && !usesOnlyOneValue) {
6034 SDValue Vec = DAG.getUNDEF(VT);
6035 SDValue Op0 = Op.getOperand(0);
6036 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6038 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6039 // a) Avoid a RMW dependency on the full vector register, and
6040 // b) Allow the register coalescer to fold away the copy if the
6041 // value is already in an S or D register.
6042 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6043 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6045 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6046 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6047 Vec = SDValue(N, 0);
6050 for (; i < NumElts; ++i) {
6051 SDValue V = Op.getOperand(i);
6052 if (V.getOpcode() == ISD::UNDEF)
6054 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6055 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6060 // Just use the default expansion. We failed to find a better alternative.
6064 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6065 SelectionDAG &DAG) const {
6066 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6068 // Check for non-constant or out of range lane.
6069 EVT VT = Op.getOperand(0).getValueType();
6070 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6071 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6075 // Insertion/extraction are legal for V128 types.
6076 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6077 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6081 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6082 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6085 // For V64 types, we perform insertion by expanding the value
6086 // to a V128 type and perform the insertion on that.
6088 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6089 EVT WideTy = WideVec.getValueType();
6091 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6092 Op.getOperand(1), Op.getOperand(2));
6093 // Re-narrow the resultant vector.
6094 return NarrowVector(Node, DAG);
6098 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6099 SelectionDAG &DAG) const {
6100 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6102 // Check for non-constant or out of range lane.
6103 EVT VT = Op.getOperand(0).getValueType();
6104 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6105 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6109 // Insertion/extraction are legal for V128 types.
6110 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6111 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6115 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6116 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6119 // For V64 types, we perform extraction by expanding the value
6120 // to a V128 type and perform the extraction on that.
6122 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6123 EVT WideTy = WideVec.getValueType();
6125 EVT ExtrTy = WideTy.getVectorElementType();
6126 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6129 // For extractions, we just return the result directly.
6130 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6134 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6135 SelectionDAG &DAG) const {
6136 EVT VT = Op.getOperand(0).getValueType();
6142 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6145 unsigned Val = Cst->getZExtValue();
6147 unsigned Size = Op.getValueType().getSizeInBits();
6151 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6154 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6157 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6160 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6163 llvm_unreachable("Unexpected vector type in extract_subvector!");
6166 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6168 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6174 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6176 if (VT.getVectorNumElements() == 4 &&
6177 (VT.is128BitVector() || VT.is64BitVector())) {
6178 unsigned PFIndexes[4];
6179 for (unsigned i = 0; i != 4; ++i) {
6183 PFIndexes[i] = M[i];
6186 // Compute the index in the perfect shuffle table.
6187 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6188 PFIndexes[2] * 9 + PFIndexes[3];
6189 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6190 unsigned Cost = (PFEntry >> 30);
6198 unsigned DummyUnsigned;
6200 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6201 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6202 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6203 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6204 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6205 isZIPMask(M, VT, DummyUnsigned) ||
6206 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6207 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6208 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6209 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6210 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6213 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6214 /// operand of a vector shift operation, where all the elements of the
6215 /// build_vector must have the same constant integer value.
6216 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6217 // Ignore bit_converts.
6218 while (Op.getOpcode() == ISD::BITCAST)
6219 Op = Op.getOperand(0);
6220 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6221 APInt SplatBits, SplatUndef;
6222 unsigned SplatBitSize;
6224 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6225 HasAnyUndefs, ElementBits) ||
6226 SplatBitSize > ElementBits)
6228 Cnt = SplatBits.getSExtValue();
6232 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6233 /// operand of a vector shift left operation. That value must be in the range:
6234 /// 0 <= Value < ElementBits for a left shift; or
6235 /// 0 <= Value <= ElementBits for a long left shift.
6236 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6237 assert(VT.isVector() && "vector shift count is not a vector type");
6238 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6239 if (!getVShiftImm(Op, ElementBits, Cnt))
6241 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6244 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6245 /// operand of a vector shift right operation. For a shift opcode, the value
6246 /// is positive, but for an intrinsic the value count must be negative. The
6247 /// absolute value must be in the range:
6248 /// 1 <= |Value| <= ElementBits for a right shift; or
6249 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6250 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6252 assert(VT.isVector() && "vector shift count is not a vector type");
6253 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6254 if (!getVShiftImm(Op, ElementBits, Cnt))
6258 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6261 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6262 SelectionDAG &DAG) const {
6263 EVT VT = Op.getValueType();
6267 if (!Op.getOperand(1).getValueType().isVector())
6269 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6271 switch (Op.getOpcode()) {
6273 llvm_unreachable("unexpected shift opcode");
6276 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6277 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6278 DAG.getConstant(Cnt, DL, MVT::i32));
6279 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6280 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6282 Op.getOperand(0), Op.getOperand(1));
6285 // Right shift immediate
6286 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6289 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6290 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6291 DAG.getConstant(Cnt, DL, MVT::i32));
6294 // Right shift register. Note, there is not a shift right register
6295 // instruction, but the shift left register instruction takes a signed
6296 // value, where negative numbers specify a right shift.
6297 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6298 : Intrinsic::aarch64_neon_ushl;
6299 // negate the shift amount
6300 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6301 SDValue NegShiftLeft =
6302 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6303 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6305 return NegShiftLeft;
6311 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6312 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6313 SDLoc dl, SelectionDAG &DAG) {
6314 EVT SrcVT = LHS.getValueType();
6315 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6316 "function only supposed to emit natural comparisons");
6318 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6319 APInt CnstBits(VT.getSizeInBits(), 0);
6320 APInt UndefBits(VT.getSizeInBits(), 0);
6321 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6322 bool IsZero = IsCnst && (CnstBits == 0);
6324 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6328 case AArch64CC::NE: {
6331 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6333 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6334 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6338 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6339 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6342 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6343 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6346 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6347 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6350 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6351 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6355 // If we ignore NaNs then we can use to the MI implementation.
6359 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6360 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6367 case AArch64CC::NE: {
6370 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6372 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6373 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6377 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6378 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6381 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6382 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6385 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6386 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6389 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6390 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6392 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6394 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6397 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6398 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6400 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6402 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6406 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6407 SelectionDAG &DAG) const {
6408 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6409 SDValue LHS = Op.getOperand(0);
6410 SDValue RHS = Op.getOperand(1);
6411 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6414 if (LHS.getValueType().getVectorElementType().isInteger()) {
6415 assert(LHS.getValueType() == RHS.getValueType());
6416 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6418 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6419 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6422 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6423 LHS.getValueType().getVectorElementType() == MVT::f64);
6425 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6426 // clean. Some of them require two branches to implement.
6427 AArch64CC::CondCode CC1, CC2;
6429 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6431 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6433 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6437 if (CC2 != AArch64CC::AL) {
6439 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6440 if (!Cmp2.getNode())
6443 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6446 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6449 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6454 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6455 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6456 /// specified in the intrinsic calls.
6457 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6459 unsigned Intrinsic) const {
6460 switch (Intrinsic) {
6461 case Intrinsic::aarch64_neon_ld2:
6462 case Intrinsic::aarch64_neon_ld3:
6463 case Intrinsic::aarch64_neon_ld4:
6464 case Intrinsic::aarch64_neon_ld1x2:
6465 case Intrinsic::aarch64_neon_ld1x3:
6466 case Intrinsic::aarch64_neon_ld1x4:
6467 case Intrinsic::aarch64_neon_ld2lane:
6468 case Intrinsic::aarch64_neon_ld3lane:
6469 case Intrinsic::aarch64_neon_ld4lane:
6470 case Intrinsic::aarch64_neon_ld2r:
6471 case Intrinsic::aarch64_neon_ld3r:
6472 case Intrinsic::aarch64_neon_ld4r: {
6473 Info.opc = ISD::INTRINSIC_W_CHAIN;
6474 // Conservatively set memVT to the entire set of vectors loaded.
6475 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6476 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6477 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6480 Info.vol = false; // volatile loads with NEON intrinsics not supported
6481 Info.readMem = true;
6482 Info.writeMem = false;
6485 case Intrinsic::aarch64_neon_st2:
6486 case Intrinsic::aarch64_neon_st3:
6487 case Intrinsic::aarch64_neon_st4:
6488 case Intrinsic::aarch64_neon_st1x2:
6489 case Intrinsic::aarch64_neon_st1x3:
6490 case Intrinsic::aarch64_neon_st1x4:
6491 case Intrinsic::aarch64_neon_st2lane:
6492 case Intrinsic::aarch64_neon_st3lane:
6493 case Intrinsic::aarch64_neon_st4lane: {
6494 Info.opc = ISD::INTRINSIC_VOID;
6495 // Conservatively set memVT to the entire set of vectors stored.
6496 unsigned NumElts = 0;
6497 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6498 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6499 if (!ArgTy->isVectorTy())
6501 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6503 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6504 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6507 Info.vol = false; // volatile stores with NEON intrinsics not supported
6508 Info.readMem = false;
6509 Info.writeMem = true;
6512 case Intrinsic::aarch64_ldaxr:
6513 case Intrinsic::aarch64_ldxr: {
6514 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6515 Info.opc = ISD::INTRINSIC_W_CHAIN;
6516 Info.memVT = MVT::getVT(PtrTy->getElementType());
6517 Info.ptrVal = I.getArgOperand(0);
6519 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6521 Info.readMem = true;
6522 Info.writeMem = false;
6525 case Intrinsic::aarch64_stlxr:
6526 case Intrinsic::aarch64_stxr: {
6527 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6528 Info.opc = ISD::INTRINSIC_W_CHAIN;
6529 Info.memVT = MVT::getVT(PtrTy->getElementType());
6530 Info.ptrVal = I.getArgOperand(1);
6532 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6534 Info.readMem = false;
6535 Info.writeMem = true;
6538 case Intrinsic::aarch64_ldaxp:
6539 case Intrinsic::aarch64_ldxp: {
6540 Info.opc = ISD::INTRINSIC_W_CHAIN;
6541 Info.memVT = MVT::i128;
6542 Info.ptrVal = I.getArgOperand(0);
6546 Info.readMem = true;
6547 Info.writeMem = false;
6550 case Intrinsic::aarch64_stlxp:
6551 case Intrinsic::aarch64_stxp: {
6552 Info.opc = ISD::INTRINSIC_W_CHAIN;
6553 Info.memVT = MVT::i128;
6554 Info.ptrVal = I.getArgOperand(2);
6558 Info.readMem = false;
6559 Info.writeMem = true;
6569 // Truncations from 64-bit GPR to 32-bit GPR is free.
6570 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6571 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6573 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6574 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6575 return NumBits1 > NumBits2;
6577 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6578 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6580 unsigned NumBits1 = VT1.getSizeInBits();
6581 unsigned NumBits2 = VT2.getSizeInBits();
6582 return NumBits1 > NumBits2;
6585 /// Check if it is profitable to hoist instruction in then/else to if.
6586 /// Not profitable if I and it's user can form a FMA instruction
6587 /// because we prefer FMSUB/FMADD.
6588 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6589 if (I->getOpcode() != Instruction::FMul)
6592 if (I->getNumUses() != 1)
6595 Instruction *User = I->user_back();
6598 !(User->getOpcode() == Instruction::FSub ||
6599 User->getOpcode() == Instruction::FAdd))
6602 const TargetOptions &Options = getTargetMachine().Options;
6603 EVT VT = getValueType(User->getOperand(0)->getType());
6605 if (isFMAFasterThanFMulAndFAdd(VT) &&
6606 isOperationLegalOrCustom(ISD::FMA, VT) &&
6607 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6613 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6615 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6616 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6618 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6619 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6620 return NumBits1 == 32 && NumBits2 == 64;
6622 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6623 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6625 unsigned NumBits1 = VT1.getSizeInBits();
6626 unsigned NumBits2 = VT2.getSizeInBits();
6627 return NumBits1 == 32 && NumBits2 == 64;
6630 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6631 EVT VT1 = Val.getValueType();
6632 if (isZExtFree(VT1, VT2)) {
6636 if (Val.getOpcode() != ISD::LOAD)
6639 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6640 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6641 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6642 VT1.getSizeInBits() <= 32);
6645 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6646 if (isa<FPExtInst>(Ext))
6649 // Vector types are next free.
6650 if (Ext->getType()->isVectorTy())
6653 for (const Use &U : Ext->uses()) {
6654 // The extension is free if we can fold it with a left shift in an
6655 // addressing mode or an arithmetic operation: add, sub, and cmp.
6657 // Is there a shift?
6658 const Instruction *Instr = cast<Instruction>(U.getUser());
6660 // Is this a constant shift?
6661 switch (Instr->getOpcode()) {
6662 case Instruction::Shl:
6663 if (!isa<ConstantInt>(Instr->getOperand(1)))
6666 case Instruction::GetElementPtr: {
6667 gep_type_iterator GTI = gep_type_begin(Instr);
6668 std::advance(GTI, U.getOperandNo());
6670 // This extension will end up with a shift because of the scaling factor.
6671 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6672 // Get the shift amount based on the scaling factor:
6673 // log2(sizeof(IdxTy)) - log2(8).
6675 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6676 // Is the constant foldable in the shift of the addressing mode?
6677 // I.e., shift amount is between 1 and 4 inclusive.
6678 if (ShiftAmt == 0 || ShiftAmt > 4)
6682 case Instruction::Trunc:
6683 // Check if this is a noop.
6684 // trunc(sext ty1 to ty2) to ty1.
6685 if (Instr->getType() == Ext->getOperand(0)->getType())
6692 // At this point we can use the bfm family, so this extension is free
6698 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6699 unsigned &RequiredAligment) const {
6700 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6702 // Cyclone supports unaligned accesses.
6703 RequiredAligment = 0;
6704 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6705 return NumBits == 32 || NumBits == 64;
6708 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6709 unsigned &RequiredAligment) const {
6710 if (!LoadedType.isSimple() ||
6711 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6713 // Cyclone supports unaligned accesses.
6714 RequiredAligment = 0;
6715 unsigned NumBits = LoadedType.getSizeInBits();
6716 return NumBits == 32 || NumBits == 64;
6719 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6720 unsigned AlignCheck) {
6721 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6722 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6725 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6726 unsigned SrcAlign, bool IsMemset,
6729 MachineFunction &MF) const {
6730 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6731 // instruction to materialize the v2i64 zero and one store (with restrictive
6732 // addressing mode). Just do two i64 store of zero-registers.
6734 const Function *F = MF.getFunction();
6735 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6736 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6737 (memOpAlign(SrcAlign, DstAlign, 16) ||
6738 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6742 (memOpAlign(SrcAlign, DstAlign, 8) ||
6743 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
6747 (memOpAlign(SrcAlign, DstAlign, 4) ||
6748 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
6754 // 12-bit optionally shifted immediates are legal for adds.
6755 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6756 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6761 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6762 // immediates is the same as for an add or a sub.
6763 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6766 return isLegalAddImmediate(Immed);
6769 /// isLegalAddressingMode - Return true if the addressing mode represented
6770 /// by AM is legal for this target, for a load/store of the specified type.
6771 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6773 // AArch64 has five basic addressing modes:
6775 // reg + 9-bit signed offset
6776 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6778 // reg + SIZE_IN_BYTES * reg
6780 // No global is ever allowed as a base.
6784 // No reg+reg+imm addressing.
6785 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6788 // check reg + imm case:
6789 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6790 uint64_t NumBytes = 0;
6791 if (Ty->isSized()) {
6792 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6793 NumBytes = NumBits / 8;
6794 if (!isPowerOf2_64(NumBits))
6799 int64_t Offset = AM.BaseOffs;
6801 // 9-bit signed offset
6802 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6805 // 12-bit unsigned offset
6806 unsigned shift = Log2_64(NumBytes);
6807 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6808 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6809 (Offset >> shift) << shift == Offset)
6814 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6816 if (!AM.Scale || AM.Scale == 1 ||
6817 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6822 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6824 // Scaling factors are not free at all.
6825 // Operands | Rt Latency
6826 // -------------------------------------------
6828 // -------------------------------------------
6829 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6830 // Rt, [Xn, Wm, <extend> #imm] |
6831 if (isLegalAddressingMode(AM, Ty))
6832 // Scale represents reg2 * scale, thus account for 1 if
6833 // it is not equal to 0 or 1.
6834 return AM.Scale != 0 && AM.Scale != 1;
6838 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6839 VT = VT.getScalarType();
6844 switch (VT.getSimpleVT().SimpleTy) {
6856 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6857 // LR is a callee-save register, but we must treat it as clobbered by any call
6858 // site. Hence we include LR in the scratch registers, which are in turn added
6859 // as implicit-defs for stackmaps and patchpoints.
6860 static const MCPhysReg ScratchRegs[] = {
6861 AArch64::X16, AArch64::X17, AArch64::LR, 0
6867 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6868 EVT VT = N->getValueType(0);
6869 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6870 // it with shift to let it be lowered to UBFX.
6871 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6872 isa<ConstantSDNode>(N->getOperand(1))) {
6873 uint64_t TruncMask = N->getConstantOperandVal(1);
6874 if (isMask_64(TruncMask) &&
6875 N->getOperand(0).getOpcode() == ISD::SRL &&
6876 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6882 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6884 assert(Ty->isIntegerTy());
6886 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6890 int64_t Val = Imm.getSExtValue();
6891 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6894 if ((int64_t)Val < 0)
6897 Val &= (1LL << 32) - 1;
6899 unsigned LZ = countLeadingZeros((uint64_t)Val);
6900 unsigned Shift = (63 - LZ) / 16;
6901 // MOVZ is free so return true for one or fewer MOVK.
6905 // Generate SUBS and CSEL for integer abs.
6906 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6907 EVT VT = N->getValueType(0);
6909 SDValue N0 = N->getOperand(0);
6910 SDValue N1 = N->getOperand(1);
6913 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6914 // and change it to SUB and CSEL.
6915 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6916 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6917 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6918 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6919 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6920 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
6922 // Generate SUBS & CSEL.
6924 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6925 N0.getOperand(0), DAG.getConstant(0, DL, VT));
6926 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6927 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
6928 SDValue(Cmp.getNode(), 1));
6933 // performXorCombine - Attempts to handle integer ABS.
6934 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6935 TargetLowering::DAGCombinerInfo &DCI,
6936 const AArch64Subtarget *Subtarget) {
6937 if (DCI.isBeforeLegalizeOps())
6940 return performIntegerAbsCombine(N, DAG);
6944 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6946 std::vector<SDNode *> *Created) const {
6947 // fold (sdiv X, pow2)
6948 EVT VT = N->getValueType(0);
6949 if ((VT != MVT::i32 && VT != MVT::i64) ||
6950 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6954 SDValue N0 = N->getOperand(0);
6955 unsigned Lg2 = Divisor.countTrailingZeros();
6956 SDValue Zero = DAG.getConstant(0, DL, VT);
6957 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
6959 // Add (N0 < 0) ? Pow2 - 1 : 0;
6961 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6962 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6963 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6966 Created->push_back(Cmp.getNode());
6967 Created->push_back(Add.getNode());
6968 Created->push_back(CSel.getNode());
6973 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
6975 // If we're dividing by a positive value, we're done. Otherwise, we must
6976 // negate the result.
6977 if (Divisor.isNonNegative())
6981 Created->push_back(SRA.getNode());
6982 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
6985 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6986 TargetLowering::DAGCombinerInfo &DCI,
6987 const AArch64Subtarget *Subtarget) {
6988 if (DCI.isBeforeLegalizeOps())
6991 // Multiplication of a power of two plus/minus one can be done more
6992 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6993 // future CPUs have a cheaper MADD instruction, this may need to be
6994 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6995 // 64-bit is 5 cycles, so this is always a win.
6996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6997 APInt Value = C->getAPIntValue();
6998 EVT VT = N->getValueType(0);
7000 if (Value.isNonNegative()) {
7001 // (mul x, 2^N + 1) => (add (shl x, N), x)
7002 APInt VM1 = Value - 1;
7003 if (VM1.isPowerOf2()) {
7004 SDValue ShiftedVal =
7005 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7006 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7007 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7010 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7011 APInt VP1 = Value + 1;
7012 if (VP1.isPowerOf2()) {
7013 SDValue ShiftedVal =
7014 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7015 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7016 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7020 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7021 APInt VNP1 = -Value + 1;
7022 if (VNP1.isPowerOf2()) {
7023 SDValue ShiftedVal =
7024 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7025 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7026 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7029 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7030 APInt VNM1 = -Value - 1;
7031 if (VNM1.isPowerOf2()) {
7032 SDValue ShiftedVal =
7033 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7034 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7036 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7037 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7044 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7045 SelectionDAG &DAG) {
7046 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7047 // optimize away operation when it's from a constant.
7049 // The general transformation is:
7050 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7051 // AND(VECTOR_CMP(x,y), constant2)
7052 // constant2 = UNARYOP(constant)
7054 // Early exit if this isn't a vector operation, the operand of the
7055 // unary operation isn't a bitwise AND, or if the sizes of the operations
7057 EVT VT = N->getValueType(0);
7058 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7059 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7060 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7063 // Now check that the other operand of the AND is a constant. We could
7064 // make the transformation for non-constant splats as well, but it's unclear
7065 // that would be a benefit as it would not eliminate any operations, just
7066 // perform one more step in scalar code before moving to the vector unit.
7067 if (BuildVectorSDNode *BV =
7068 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7069 // Bail out if the vector isn't a constant.
7070 if (!BV->isConstant())
7073 // Everything checks out. Build up the new and improved node.
7075 EVT IntVT = BV->getValueType(0);
7076 // Create a new constant of the appropriate type for the transformed
7078 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7079 // The AND node needs bitcasts to/from an integer vector type around it.
7080 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7081 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7082 N->getOperand(0)->getOperand(0), MaskConst);
7083 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7090 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7091 const AArch64Subtarget *Subtarget) {
7092 // First try to optimize away the conversion when it's conditionally from
7093 // a constant. Vectors only.
7094 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7095 if (Res != SDValue())
7098 EVT VT = N->getValueType(0);
7099 if (VT != MVT::f32 && VT != MVT::f64)
7102 // Only optimize when the source and destination types have the same width.
7103 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7106 // If the result of an integer load is only used by an integer-to-float
7107 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7108 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7109 SDValue N0 = N->getOperand(0);
7110 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7111 // Do not change the width of a volatile load.
7112 !cast<LoadSDNode>(N0)->isVolatile()) {
7113 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7114 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7115 LN0->getPointerInfo(), LN0->isVolatile(),
7116 LN0->isNonTemporal(), LN0->isInvariant(),
7117 LN0->getAlignment());
7119 // Make sure successors of the original load stay after it by updating them
7120 // to use the new Chain.
7121 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7124 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7125 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7131 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7132 /// searches for and classifies those shifts.
7133 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7135 if (N.getOpcode() == ISD::SHL)
7137 else if (N.getOpcode() == ISD::SRL)
7142 if (!isa<ConstantSDNode>(N.getOperand(1)))
7145 ShiftAmount = N->getConstantOperandVal(1);
7146 Src = N->getOperand(0);
7150 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7151 /// registers viewed as a high/low pair. This function looks for the pattern:
7152 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7153 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7155 static SDValue tryCombineToEXTR(SDNode *N,
7156 TargetLowering::DAGCombinerInfo &DCI) {
7157 SelectionDAG &DAG = DCI.DAG;
7159 EVT VT = N->getValueType(0);
7161 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7163 if (VT != MVT::i32 && VT != MVT::i64)
7167 uint32_t ShiftLHS = 0;
7169 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7173 uint32_t ShiftRHS = 0;
7175 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7178 // If they're both trying to come from the high part of the register, they're
7179 // not really an EXTR.
7180 if (LHSFromHi == RHSFromHi)
7183 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7187 std::swap(LHS, RHS);
7188 std::swap(ShiftLHS, ShiftRHS);
7191 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7192 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7195 static SDValue tryCombineToBSL(SDNode *N,
7196 TargetLowering::DAGCombinerInfo &DCI) {
7197 EVT VT = N->getValueType(0);
7198 SelectionDAG &DAG = DCI.DAG;
7204 SDValue N0 = N->getOperand(0);
7205 if (N0.getOpcode() != ISD::AND)
7208 SDValue N1 = N->getOperand(1);
7209 if (N1.getOpcode() != ISD::AND)
7212 // We only have to look for constant vectors here since the general, variable
7213 // case can be handled in TableGen.
7214 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7215 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7216 for (int i = 1; i >= 0; --i)
7217 for (int j = 1; j >= 0; --j) {
7218 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7219 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7223 bool FoundMatch = true;
7224 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7225 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7226 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7228 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7235 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7236 N0->getOperand(1 - i), N1->getOperand(1 - j));
7242 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7243 const AArch64Subtarget *Subtarget) {
7244 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7245 if (!EnableAArch64ExtrGeneration)
7247 SelectionDAG &DAG = DCI.DAG;
7248 EVT VT = N->getValueType(0);
7250 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7253 SDValue Res = tryCombineToEXTR(N, DCI);
7257 Res = tryCombineToBSL(N, DCI);
7264 static SDValue performBitcastCombine(SDNode *N,
7265 TargetLowering::DAGCombinerInfo &DCI,
7266 SelectionDAG &DAG) {
7267 // Wait 'til after everything is legalized to try this. That way we have
7268 // legal vector types and such.
7269 if (DCI.isBeforeLegalizeOps())
7272 // Remove extraneous bitcasts around an extract_subvector.
7274 // (v4i16 (bitconvert
7275 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7277 // (extract_subvector ((v8i16 ...), (i64 4)))
7279 // Only interested in 64-bit vectors as the ultimate result.
7280 EVT VT = N->getValueType(0);
7283 if (VT.getSimpleVT().getSizeInBits() != 64)
7285 // Is the operand an extract_subvector starting at the beginning or halfway
7286 // point of the vector? A low half may also come through as an
7287 // EXTRACT_SUBREG, so look for that, too.
7288 SDValue Op0 = N->getOperand(0);
7289 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7290 !(Op0->isMachineOpcode() &&
7291 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7293 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7294 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7295 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7297 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7298 if (idx != AArch64::dsub)
7300 // The dsub reference is equivalent to a lane zero subvector reference.
7303 // Look through the bitcast of the input to the extract.
7304 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7306 SDValue Source = Op0->getOperand(0)->getOperand(0);
7307 // If the source type has twice the number of elements as our destination
7308 // type, we know this is an extract of the high or low half of the vector.
7309 EVT SVT = Source->getValueType(0);
7310 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7313 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7315 // Create the simplified form to just extract the low or high half of the
7316 // vector directly rather than bothering with the bitcasts.
7318 unsigned NumElements = VT.getVectorNumElements();
7320 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7321 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7323 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7324 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7330 static SDValue performConcatVectorsCombine(SDNode *N,
7331 TargetLowering::DAGCombinerInfo &DCI,
7332 SelectionDAG &DAG) {
7334 EVT VT = N->getValueType(0);
7335 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7337 // Optimize concat_vectors of truncated vectors, where the intermediate
7338 // type is illegal, to avoid said illegality, e.g.,
7339 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7340 // (v2i16 (truncate (v2i64)))))
7342 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7343 // (v4i32 (bitcast (v2i64))),
7345 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7346 // on both input and result type, so we might generate worse code.
7347 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7348 if (N->getNumOperands() == 2 &&
7349 N0->getOpcode() == ISD::TRUNCATE &&
7350 N1->getOpcode() == ISD::TRUNCATE) {
7351 SDValue N00 = N0->getOperand(0);
7352 SDValue N10 = N1->getOperand(0);
7353 EVT N00VT = N00.getValueType();
7355 if (N00VT == N10.getValueType() &&
7356 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7357 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7358 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7359 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7360 for (size_t i = 0; i < Mask.size(); ++i)
7362 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7363 DAG.getVectorShuffle(
7365 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7366 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7370 // Wait 'til after everything is legalized to try this. That way we have
7371 // legal vector types and such.
7372 if (DCI.isBeforeLegalizeOps())
7375 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7376 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7377 // canonicalise to that.
7378 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7379 assert(VT.getVectorElementType().getSizeInBits() == 64);
7380 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7381 DAG.getConstant(0, dl, MVT::i64));
7384 // Canonicalise concat_vectors so that the right-hand vector has as few
7385 // bit-casts as possible before its real operation. The primary matching
7386 // destination for these operations will be the narrowing "2" instructions,
7387 // which depend on the operation being performed on this right-hand vector.
7389 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7391 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7393 if (N1->getOpcode() != ISD::BITCAST)
7395 SDValue RHS = N1->getOperand(0);
7396 MVT RHSTy = RHS.getValueType().getSimpleVT();
7397 // If the RHS is not a vector, this is not the pattern we're looking for.
7398 if (!RHSTy.isVector())
7401 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7403 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7404 RHSTy.getVectorNumElements() * 2);
7405 return DAG.getNode(ISD::BITCAST, dl, VT,
7406 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7407 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7411 static SDValue tryCombineFixedPointConvert(SDNode *N,
7412 TargetLowering::DAGCombinerInfo &DCI,
7413 SelectionDAG &DAG) {
7414 // Wait 'til after everything is legalized to try this. That way we have
7415 // legal vector types and such.
7416 if (DCI.isBeforeLegalizeOps())
7418 // Transform a scalar conversion of a value from a lane extract into a
7419 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7420 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7421 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7423 // The second form interacts better with instruction selection and the
7424 // register allocator to avoid cross-class register copies that aren't
7425 // coalescable due to a lane reference.
7427 // Check the operand and see if it originates from a lane extract.
7428 SDValue Op1 = N->getOperand(1);
7429 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7430 // Yep, no additional predication needed. Perform the transform.
7431 SDValue IID = N->getOperand(0);
7432 SDValue Shift = N->getOperand(2);
7433 SDValue Vec = Op1.getOperand(0);
7434 SDValue Lane = Op1.getOperand(1);
7435 EVT ResTy = N->getValueType(0);
7439 // The vector width should be 128 bits by the time we get here, even
7440 // if it started as 64 bits (the extract_vector handling will have
7442 assert(Vec.getValueType().getSizeInBits() == 128 &&
7443 "unexpected vector size on extract_vector_elt!");
7444 if (Vec.getValueType() == MVT::v4i32)
7445 VecResTy = MVT::v4f32;
7446 else if (Vec.getValueType() == MVT::v2i64)
7447 VecResTy = MVT::v2f64;
7449 llvm_unreachable("unexpected vector type!");
7452 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7453 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7458 // AArch64 high-vector "long" operations are formed by performing the non-high
7459 // version on an extract_subvector of each operand which gets the high half:
7461 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7463 // However, there are cases which don't have an extract_high explicitly, but
7464 // have another operation that can be made compatible with one for free. For
7467 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7469 // This routine does the actual conversion of such DUPs, once outer routines
7470 // have determined that everything else is in order.
7471 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7472 // We can handle most types of duplicate, but the lane ones have an extra
7473 // operand saying *which* lane, so we need to know.
7475 switch (N.getOpcode()) {
7476 case AArch64ISD::DUP:
7479 case AArch64ISD::DUPLANE8:
7480 case AArch64ISD::DUPLANE16:
7481 case AArch64ISD::DUPLANE32:
7482 case AArch64ISD::DUPLANE64:
7489 MVT NarrowTy = N.getSimpleValueType();
7490 if (!NarrowTy.is64BitVector())
7493 MVT ElementTy = NarrowTy.getVectorElementType();
7494 unsigned NumElems = NarrowTy.getVectorNumElements();
7495 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7500 NewDUP = DAG.getNode(N.getOpcode(), dl, NewDUPVT, N.getOperand(0),
7503 NewDUP = DAG.getNode(AArch64ISD::DUP, dl, NewDUPVT, N.getOperand(0));
7505 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy, NewDUP,
7506 DAG.getConstant(NumElems, dl, MVT::i64));
7509 static bool isEssentiallyExtractSubvector(SDValue N) {
7510 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7513 return N.getOpcode() == ISD::BITCAST &&
7514 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7517 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7518 struct GenericSetCCInfo {
7519 const SDValue *Opnd0;
7520 const SDValue *Opnd1;
7524 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7525 struct AArch64SetCCInfo {
7527 AArch64CC::CondCode CC;
7530 /// \brief Helper structure to keep track of SetCC information.
7532 GenericSetCCInfo Generic;
7533 AArch64SetCCInfo AArch64;
7536 /// \brief Helper structure to be able to read SetCC information. If set to
7537 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7538 /// GenericSetCCInfo.
7539 struct SetCCInfoAndKind {
7544 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7546 /// AArch64 lowered one.
7547 /// \p SetCCInfo is filled accordingly.
7548 /// \post SetCCInfo is meanginfull only when this function returns true.
7549 /// \return True when Op is a kind of SET_CC operation.
7550 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7551 // If this is a setcc, this is straight forward.
7552 if (Op.getOpcode() == ISD::SETCC) {
7553 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7554 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7555 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7556 SetCCInfo.IsAArch64 = false;
7559 // Otherwise, check if this is a matching csel instruction.
7563 if (Op.getOpcode() != AArch64ISD::CSEL)
7565 // Set the information about the operands.
7566 // TODO: we want the operands of the Cmp not the csel
7567 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7568 SetCCInfo.IsAArch64 = true;
7569 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7570 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7572 // Check that the operands matches the constraints:
7573 // (1) Both operands must be constants.
7574 // (2) One must be 1 and the other must be 0.
7575 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7576 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7579 if (!TValue || !FValue)
7583 if (!TValue->isOne()) {
7584 // Update the comparison when we are interested in !cc.
7585 std::swap(TValue, FValue);
7586 SetCCInfo.Info.AArch64.CC =
7587 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7589 return TValue->isOne() && FValue->isNullValue();
7592 // Returns true if Op is setcc or zext of setcc.
7593 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7594 if (isSetCC(Op, Info))
7596 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7597 isSetCC(Op->getOperand(0), Info));
7600 // The folding we want to perform is:
7601 // (add x, [zext] (setcc cc ...) )
7603 // (csel x, (add x, 1), !cc ...)
7605 // The latter will get matched to a CSINC instruction.
7606 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7607 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7608 SDValue LHS = Op->getOperand(0);
7609 SDValue RHS = Op->getOperand(1);
7610 SetCCInfoAndKind InfoAndKind;
7612 // If neither operand is a SET_CC, give up.
7613 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7614 std::swap(LHS, RHS);
7615 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7619 // FIXME: This could be generatized to work for FP comparisons.
7620 EVT CmpVT = InfoAndKind.IsAArch64
7621 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7622 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7623 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7629 if (InfoAndKind.IsAArch64) {
7630 CCVal = DAG.getConstant(
7631 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
7633 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7635 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7636 *InfoAndKind.Info.Generic.Opnd1,
7637 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7640 EVT VT = Op->getValueType(0);
7641 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
7642 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7645 // The basic add/sub long vector instructions have variants with "2" on the end
7646 // which act on the high-half of their inputs. They are normally matched by
7649 // (add (zeroext (extract_high LHS)),
7650 // (zeroext (extract_high RHS)))
7651 // -> uaddl2 vD, vN, vM
7653 // However, if one of the extracts is something like a duplicate, this
7654 // instruction can still be used profitably. This function puts the DAG into a
7655 // more appropriate form for those patterns to trigger.
7656 static SDValue performAddSubLongCombine(SDNode *N,
7657 TargetLowering::DAGCombinerInfo &DCI,
7658 SelectionDAG &DAG) {
7659 if (DCI.isBeforeLegalizeOps())
7662 MVT VT = N->getSimpleValueType(0);
7663 if (!VT.is128BitVector()) {
7664 if (N->getOpcode() == ISD::ADD)
7665 return performSetccAddFolding(N, DAG);
7669 // Make sure both branches are extended in the same way.
7670 SDValue LHS = N->getOperand(0);
7671 SDValue RHS = N->getOperand(1);
7672 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7673 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7674 LHS.getOpcode() != RHS.getOpcode())
7677 unsigned ExtType = LHS.getOpcode();
7679 // It's not worth doing if at least one of the inputs isn't already an
7680 // extract, but we don't know which it'll be so we have to try both.
7681 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7682 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7686 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7687 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7688 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7692 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7695 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7698 // Massage DAGs which we can use the high-half "long" operations on into
7699 // something isel will recognize better. E.g.
7701 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7702 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7703 // (extract_high (v2i64 (dup128 scalar)))))
7705 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7706 TargetLowering::DAGCombinerInfo &DCI,
7707 SelectionDAG &DAG) {
7708 if (DCI.isBeforeLegalizeOps())
7711 SDValue LHS = N->getOperand(1);
7712 SDValue RHS = N->getOperand(2);
7713 assert(LHS.getValueType().is64BitVector() &&
7714 RHS.getValueType().is64BitVector() &&
7715 "unexpected shape for long operation");
7717 // Either node could be a DUP, but it's not worth doing both of them (you'd
7718 // just as well use the non-high version) so look for a corresponding extract
7719 // operation on the other "wing".
7720 if (isEssentiallyExtractSubvector(LHS)) {
7721 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7724 } else if (isEssentiallyExtractSubvector(RHS)) {
7725 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7730 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7731 N->getOperand(0), LHS, RHS);
7734 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7735 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7736 unsigned ElemBits = ElemTy.getSizeInBits();
7738 int64_t ShiftAmount;
7739 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7740 APInt SplatValue, SplatUndef;
7741 unsigned SplatBitSize;
7743 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7744 HasAnyUndefs, ElemBits) ||
7745 SplatBitSize != ElemBits)
7748 ShiftAmount = SplatValue.getSExtValue();
7749 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7750 ShiftAmount = CVN->getSExtValue();
7758 llvm_unreachable("Unknown shift intrinsic");
7759 case Intrinsic::aarch64_neon_sqshl:
7760 Opcode = AArch64ISD::SQSHL_I;
7761 IsRightShift = false;
7763 case Intrinsic::aarch64_neon_uqshl:
7764 Opcode = AArch64ISD::UQSHL_I;
7765 IsRightShift = false;
7767 case Intrinsic::aarch64_neon_srshl:
7768 Opcode = AArch64ISD::SRSHR_I;
7769 IsRightShift = true;
7771 case Intrinsic::aarch64_neon_urshl:
7772 Opcode = AArch64ISD::URSHR_I;
7773 IsRightShift = true;
7775 case Intrinsic::aarch64_neon_sqshlu:
7776 Opcode = AArch64ISD::SQSHLU_I;
7777 IsRightShift = false;
7781 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
7783 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7784 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
7785 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
7787 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7788 DAG.getConstant(ShiftAmount, dl, MVT::i32));
7794 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7795 // the intrinsics must be legal and take an i32, this means there's almost
7796 // certainly going to be a zext in the DAG which we can eliminate.
7797 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7798 SDValue AndN = N->getOperand(2);
7799 if (AndN.getOpcode() != ISD::AND)
7802 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7803 if (!CMask || CMask->getZExtValue() != Mask)
7806 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7807 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7810 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7811 SelectionDAG &DAG) {
7813 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
7814 DAG.getNode(Opc, dl,
7815 N->getOperand(1).getSimpleValueType(),
7817 DAG.getConstant(0, dl, MVT::i64));
7820 static SDValue performIntrinsicCombine(SDNode *N,
7821 TargetLowering::DAGCombinerInfo &DCI,
7822 const AArch64Subtarget *Subtarget) {
7823 SelectionDAG &DAG = DCI.DAG;
7824 unsigned IID = getIntrinsicID(N);
7828 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7829 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7830 return tryCombineFixedPointConvert(N, DCI, DAG);
7832 case Intrinsic::aarch64_neon_saddv:
7833 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7834 case Intrinsic::aarch64_neon_uaddv:
7835 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7836 case Intrinsic::aarch64_neon_sminv:
7837 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7838 case Intrinsic::aarch64_neon_uminv:
7839 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7840 case Intrinsic::aarch64_neon_smaxv:
7841 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7842 case Intrinsic::aarch64_neon_umaxv:
7843 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7844 case Intrinsic::aarch64_neon_fmax:
7845 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7846 N->getOperand(1), N->getOperand(2));
7847 case Intrinsic::aarch64_neon_fmin:
7848 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7849 N->getOperand(1), N->getOperand(2));
7850 case Intrinsic::aarch64_neon_smull:
7851 case Intrinsic::aarch64_neon_umull:
7852 case Intrinsic::aarch64_neon_pmull:
7853 case Intrinsic::aarch64_neon_sqdmull:
7854 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7855 case Intrinsic::aarch64_neon_sqshl:
7856 case Intrinsic::aarch64_neon_uqshl:
7857 case Intrinsic::aarch64_neon_sqshlu:
7858 case Intrinsic::aarch64_neon_srshl:
7859 case Intrinsic::aarch64_neon_urshl:
7860 return tryCombineShiftImm(IID, N, DAG);
7861 case Intrinsic::aarch64_crc32b:
7862 case Intrinsic::aarch64_crc32cb:
7863 return tryCombineCRC32(0xff, N, DAG);
7864 case Intrinsic::aarch64_crc32h:
7865 case Intrinsic::aarch64_crc32ch:
7866 return tryCombineCRC32(0xffff, N, DAG);
7871 static SDValue performExtendCombine(SDNode *N,
7872 TargetLowering::DAGCombinerInfo &DCI,
7873 SelectionDAG &DAG) {
7874 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7875 // we can convert that DUP into another extract_high (of a bigger DUP), which
7876 // helps the backend to decide that an sabdl2 would be useful, saving a real
7877 // extract_high operation.
7878 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7879 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7880 SDNode *ABDNode = N->getOperand(0).getNode();
7881 unsigned IID = getIntrinsicID(ABDNode);
7882 if (IID == Intrinsic::aarch64_neon_sabd ||
7883 IID == Intrinsic::aarch64_neon_uabd) {
7884 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7885 if (!NewABD.getNode())
7888 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7893 // This is effectively a custom type legalization for AArch64.
7895 // Type legalization will split an extend of a small, legal, type to a larger
7896 // illegal type by first splitting the destination type, often creating
7897 // illegal source types, which then get legalized in isel-confusing ways,
7898 // leading to really terrible codegen. E.g.,
7899 // %result = v8i32 sext v8i8 %value
7901 // %losrc = extract_subreg %value, ...
7902 // %hisrc = extract_subreg %value, ...
7903 // %lo = v4i32 sext v4i8 %losrc
7904 // %hi = v4i32 sext v4i8 %hisrc
7905 // Things go rapidly downhill from there.
7907 // For AArch64, the [sz]ext vector instructions can only go up one element
7908 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7909 // take two instructions.
7911 // This implies that the most efficient way to do the extend from v8i8
7912 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7913 // the normal splitting to happen for the v8i16->v8i32.
7915 // This is pre-legalization to catch some cases where the default
7916 // type legalization will create ill-tempered code.
7917 if (!DCI.isBeforeLegalizeOps())
7920 // We're only interested in cleaning things up for non-legal vector types
7921 // here. If both the source and destination are legal, things will just
7922 // work naturally without any fiddling.
7923 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7924 EVT ResVT = N->getValueType(0);
7925 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7927 // If the vector type isn't a simple VT, it's beyond the scope of what
7928 // we're worried about here. Let legalization do its thing and hope for
7930 SDValue Src = N->getOperand(0);
7931 EVT SrcVT = Src->getValueType(0);
7932 if (!ResVT.isSimple() || !SrcVT.isSimple())
7935 // If the source VT is a 64-bit vector, we can play games and get the
7936 // better results we want.
7937 if (SrcVT.getSizeInBits() != 64)
7940 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7941 unsigned ElementCount = SrcVT.getVectorNumElements();
7942 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7944 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7946 // Now split the rest of the operation into two halves, each with a 64
7950 unsigned NumElements = ResVT.getVectorNumElements();
7951 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7952 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7953 ResVT.getVectorElementType(), NumElements / 2);
7955 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7956 LoVT.getVectorNumElements());
7957 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7958 DAG.getConstant(0, DL, MVT::i64));
7959 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7960 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
7961 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7962 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7964 // Now combine the parts back together so we still have a single result
7965 // like the combiner expects.
7966 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7969 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7970 /// value. The load store optimizer pass will merge them to store pair stores.
7971 /// This has better performance than a splat of the scalar followed by a split
7972 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7973 /// followed by an ext.b and two stores.
7974 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7975 SDValue StVal = St->getValue();
7976 EVT VT = StVal.getValueType();
7978 // Don't replace floating point stores, they possibly won't be transformed to
7979 // stp because of the store pair suppress pass.
7980 if (VT.isFloatingPoint())
7983 // Check for insert vector elements.
7984 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7987 // We can express a splat as store pair(s) for 2 or 4 elements.
7988 unsigned NumVecElts = VT.getVectorNumElements();
7989 if (NumVecElts != 4 && NumVecElts != 2)
7991 SDValue SplatVal = StVal.getOperand(1);
7992 unsigned RemainInsertElts = NumVecElts - 1;
7994 // Check that this is a splat.
7995 while (--RemainInsertElts) {
7996 SDValue NextInsertElt = StVal.getOperand(0);
7997 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7999 if (NextInsertElt.getOperand(1) != SplatVal)
8001 StVal = NextInsertElt;
8003 unsigned OrigAlignment = St->getAlignment();
8004 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8005 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8007 // Create scalar stores. This is at least as good as the code sequence for a
8008 // split unaligned store wich is a dup.s, ext.b, and two stores.
8009 // Most of the time the three stores should be replaced by store pair
8010 // instructions (stp).
8012 SDValue BasePtr = St->getBasePtr();
8014 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8015 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8017 unsigned Offset = EltOffset;
8018 while (--NumVecElts) {
8019 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8020 DAG.getConstant(Offset, DL, MVT::i64));
8021 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8022 St->getPointerInfo(), St->isVolatile(),
8023 St->isNonTemporal(), Alignment);
8024 Offset += EltOffset;
8029 static SDValue performSTORECombine(SDNode *N,
8030 TargetLowering::DAGCombinerInfo &DCI,
8032 const AArch64Subtarget *Subtarget) {
8033 if (!DCI.isBeforeLegalize())
8036 StoreSDNode *S = cast<StoreSDNode>(N);
8037 if (S->isVolatile())
8040 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8041 // page boundaries. We want to split such stores.
8042 if (!Subtarget->isCyclone())
8045 // Don't split at Oz.
8046 MachineFunction &MF = DAG.getMachineFunction();
8047 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8051 SDValue StVal = S->getValue();
8052 EVT VT = StVal.getValueType();
8054 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8055 // those up regresses performance on micro-benchmarks and olden/bh.
8056 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8059 // Split unaligned 16B stores. They are terrible for performance.
8060 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8061 // extensions can use this to mark that it does not want splitting to happen
8062 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8063 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8064 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8065 S->getAlignment() <= 2)
8068 // If we get a splat of a scalar convert this vector store to a store of
8069 // scalars. They will be merged into store pairs thereby removing two
8071 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8072 if (ReplacedSplat != SDValue())
8073 return ReplacedSplat;
8076 unsigned NumElts = VT.getVectorNumElements() / 2;
8077 // Split VT into two.
8079 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8080 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8081 DAG.getConstant(0, DL, MVT::i64));
8082 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8083 DAG.getConstant(NumElts, DL, MVT::i64));
8084 SDValue BasePtr = S->getBasePtr();
8086 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8087 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8088 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8089 DAG.getConstant(8, DL, MVT::i64));
8090 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8091 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8095 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8096 /// post-increment LD1R.
8097 static SDValue performPostLD1Combine(SDNode *N,
8098 TargetLowering::DAGCombinerInfo &DCI,
8100 if (DCI.isBeforeLegalizeOps())
8103 SelectionDAG &DAG = DCI.DAG;
8104 EVT VT = N->getValueType(0);
8106 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8107 SDNode *LD = N->getOperand(LoadIdx).getNode();
8108 // If it is not LOAD, can not do such combine.
8109 if (LD->getOpcode() != ISD::LOAD)
8112 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8113 EVT MemVT = LoadSDN->getMemoryVT();
8114 // Check if memory operand is the same type as the vector element.
8115 if (MemVT != VT.getVectorElementType())
8118 // Check if there are other uses. If so, do not combine as it will introduce
8120 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8122 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8128 SDValue Addr = LD->getOperand(1);
8129 SDValue Vector = N->getOperand(0);
8130 // Search for a use of the address operand that is an increment.
8131 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8132 Addr.getNode()->use_end(); UI != UE; ++UI) {
8134 if (User->getOpcode() != ISD::ADD
8135 || UI.getUse().getResNo() != Addr.getResNo())
8138 // Check that the add is independent of the load. Otherwise, folding it
8139 // would create a cycle.
8140 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8142 // Also check that add is not used in the vector operand. This would also
8144 if (User->isPredecessorOf(Vector.getNode()))
8147 // If the increment is a constant, it must match the memory ref size.
8148 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8149 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8150 uint32_t IncVal = CInc->getZExtValue();
8151 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8152 if (IncVal != NumBytes)
8154 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8157 // Finally, check that the vector doesn't depend on the load.
8158 // Again, this would create a cycle.
8159 // The load depending on the vector is fine, as that's the case for the
8160 // LD1*post we'll eventually generate anyway.
8161 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8164 SmallVector<SDValue, 8> Ops;
8165 Ops.push_back(LD->getOperand(0)); // Chain
8167 Ops.push_back(Vector); // The vector to be inserted
8168 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8170 Ops.push_back(Addr);
8173 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8174 SDVTList SDTys = DAG.getVTList(Tys);
8175 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8176 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8178 LoadSDN->getMemOperand());
8181 SmallVector<SDValue, 2> NewResults;
8182 NewResults.push_back(SDValue(LD, 0)); // The result of load
8183 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8184 DCI.CombineTo(LD, NewResults);
8185 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8186 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8193 /// Target-specific DAG combine function for NEON load/store intrinsics
8194 /// to merge base address updates.
8195 static SDValue performNEONPostLDSTCombine(SDNode *N,
8196 TargetLowering::DAGCombinerInfo &DCI,
8197 SelectionDAG &DAG) {
8198 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8201 unsigned AddrOpIdx = N->getNumOperands() - 1;
8202 SDValue Addr = N->getOperand(AddrOpIdx);
8204 // Search for a use of the address operand that is an increment.
8205 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8206 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8208 if (User->getOpcode() != ISD::ADD ||
8209 UI.getUse().getResNo() != Addr.getResNo())
8212 // Check that the add is independent of the load/store. Otherwise, folding
8213 // it would create a cycle.
8214 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8217 // Find the new opcode for the updating load/store.
8218 bool IsStore = false;
8219 bool IsLaneOp = false;
8220 bool IsDupOp = false;
8221 unsigned NewOpc = 0;
8222 unsigned NumVecs = 0;
8223 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8225 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8226 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8228 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8230 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8232 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8233 NumVecs = 2; IsStore = true; break;
8234 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8235 NumVecs = 3; IsStore = true; break;
8236 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8237 NumVecs = 4; IsStore = true; break;
8238 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8240 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8242 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8244 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8245 NumVecs = 2; IsStore = true; break;
8246 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8247 NumVecs = 3; IsStore = true; break;
8248 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8249 NumVecs = 4; IsStore = true; break;
8250 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8251 NumVecs = 2; IsDupOp = true; break;
8252 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8253 NumVecs = 3; IsDupOp = true; break;
8254 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8255 NumVecs = 4; IsDupOp = true; break;
8256 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8257 NumVecs = 2; IsLaneOp = true; break;
8258 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8259 NumVecs = 3; IsLaneOp = true; break;
8260 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8261 NumVecs = 4; IsLaneOp = true; break;
8262 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8263 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8264 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8265 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8266 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8267 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8272 VecTy = N->getOperand(2).getValueType();
8274 VecTy = N->getValueType(0);
8276 // If the increment is a constant, it must match the memory ref size.
8277 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8278 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8279 uint32_t IncVal = CInc->getZExtValue();
8280 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8281 if (IsLaneOp || IsDupOp)
8282 NumBytes /= VecTy.getVectorNumElements();
8283 if (IncVal != NumBytes)
8285 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8287 SmallVector<SDValue, 8> Ops;
8288 Ops.push_back(N->getOperand(0)); // Incoming chain
8289 // Load lane and store have vector list as input.
8290 if (IsLaneOp || IsStore)
8291 for (unsigned i = 2; i < AddrOpIdx; ++i)
8292 Ops.push_back(N->getOperand(i));
8293 Ops.push_back(Addr); // Base register
8298 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8300 for (n = 0; n < NumResultVecs; ++n)
8302 Tys[n++] = MVT::i64; // Type of write back register
8303 Tys[n] = MVT::Other; // Type of the chain
8304 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8306 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8307 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8308 MemInt->getMemoryVT(),
8309 MemInt->getMemOperand());
8312 std::vector<SDValue> NewResults;
8313 for (unsigned i = 0; i < NumResultVecs; ++i) {
8314 NewResults.push_back(SDValue(UpdN.getNode(), i));
8316 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8317 DCI.CombineTo(N, NewResults);
8318 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8325 // Checks to see if the value is the prescribed width and returns information
8326 // about its extension mode.
8328 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8329 ExtType = ISD::NON_EXTLOAD;
8330 switch(V.getNode()->getOpcode()) {
8334 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8335 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8336 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8337 ExtType = LoadNode->getExtensionType();
8342 case ISD::AssertSext: {
8343 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8344 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8345 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8346 ExtType = ISD::SEXTLOAD;
8351 case ISD::AssertZext: {
8352 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8353 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8354 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8355 ExtType = ISD::ZEXTLOAD;
8361 case ISD::TargetConstant: {
8362 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8372 // This function does a whole lot of voodoo to determine if the tests are
8373 // equivalent without and with a mask. Essentially what happens is that given a
8376 // +-------------+ +-------------+ +-------------+ +-------------+
8377 // | Input | | AddConstant | | CompConstant| | CC |
8378 // +-------------+ +-------------+ +-------------+ +-------------+
8380 // V V | +----------+
8381 // +-------------+ +----+ | |
8382 // | ADD | |0xff| | |
8383 // +-------------+ +----+ | |
8386 // +-------------+ | |
8388 // +-------------+ | |
8397 // The AND node may be safely removed for some combinations of inputs. In
8398 // particular we need to take into account the extension type of the Input,
8399 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8400 // width of the input (this can work for any width inputs, the above graph is
8401 // specific to 8 bits.
8403 // The specific equations were worked out by generating output tables for each
8404 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8405 // problem was simplified by working with 4 bit inputs, which means we only
8406 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8407 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8408 // patterns present in both extensions (0,7). For every distinct set of
8409 // AddConstant and CompConstants bit patterns we can consider the masked and
8410 // unmasked versions to be equivalent if the result of this function is true for
8411 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8414 // and w10, w8, #0x0f
8416 // cset w9, AArch64CC
8418 // cset w11, AArch64CC
8423 // Since the above function shows when the outputs are equivalent it defines
8424 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8425 // would be expensive to run during compiles. The equations below were written
8426 // in a test harness that confirmed they gave equivalent outputs to the above
8427 // for all inputs function, so they can be used determine if the removal is
8430 // isEquivalentMaskless() is the code for testing if the AND can be removed
8431 // factored out of the DAG recognition as the DAG can take several forms.
8434 bool isEquivalentMaskless(unsigned CC, unsigned width,
8435 ISD::LoadExtType ExtType, signed AddConstant,
8436 signed CompConstant) {
8437 // By being careful about our equations and only writing the in term
8438 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8439 // make them generally applicable to all bit widths.
8440 signed MaxUInt = (1 << width);
8442 // For the purposes of these comparisons sign extending the type is
8443 // equivalent to zero extending the add and displacing it by half the integer
8444 // width. Provided we are careful and make sure our equations are valid over
8445 // the whole range we can just adjust the input and avoid writing equations
8446 // for sign extended inputs.
8447 if (ExtType == ISD::SEXTLOAD)
8448 AddConstant -= (1 << (width-1));
8452 case AArch64CC::GT: {
8453 if ((AddConstant == 0) ||
8454 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8455 (AddConstant >= 0 && CompConstant < 0) ||
8456 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8460 case AArch64CC::GE: {
8461 if ((AddConstant == 0) ||
8462 (AddConstant >= 0 && CompConstant <= 0) ||
8463 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8467 case AArch64CC::LS: {
8468 if ((AddConstant >= 0 && CompConstant < 0) ||
8469 (AddConstant <= 0 && CompConstant >= -1 &&
8470 CompConstant < AddConstant + MaxUInt))
8474 case AArch64CC::MI: {
8475 if ((AddConstant == 0) ||
8476 (AddConstant > 0 && CompConstant <= 0) ||
8477 (AddConstant < 0 && CompConstant <= AddConstant))
8481 case AArch64CC::HS: {
8482 if ((AddConstant >= 0 && CompConstant <= 0) ||
8483 (AddConstant <= 0 && CompConstant >= 0 &&
8484 CompConstant <= AddConstant + MaxUInt))
8488 case AArch64CC::NE: {
8489 if ((AddConstant > 0 && CompConstant < 0) ||
8490 (AddConstant < 0 && CompConstant >= 0 &&
8491 CompConstant < AddConstant + MaxUInt) ||
8492 (AddConstant >= 0 && CompConstant >= 0 &&
8493 CompConstant >= AddConstant) ||
8494 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8503 case AArch64CC::Invalid:
8511 SDValue performCONDCombine(SDNode *N,
8512 TargetLowering::DAGCombinerInfo &DCI,
8513 SelectionDAG &DAG, unsigned CCIndex,
8514 unsigned CmpIndex) {
8515 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8516 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8517 unsigned CondOpcode = SubsNode->getOpcode();
8519 if (CondOpcode != AArch64ISD::SUBS)
8522 // There is a SUBS feeding this condition. Is it fed by a mask we can
8525 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8526 unsigned MaskBits = 0;
8528 if (AndNode->getOpcode() != ISD::AND)
8531 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8532 uint32_t CNV = CN->getZExtValue();
8535 else if (CNV == 65535)
8542 SDValue AddValue = AndNode->getOperand(0);
8544 if (AddValue.getOpcode() != ISD::ADD)
8547 // The basic dag structure is correct, grab the inputs and validate them.
8549 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8550 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8551 SDValue SubsInputValue = SubsNode->getOperand(1);
8553 // The mask is present and the provenance of all the values is a smaller type,
8554 // lets see if the mask is superfluous.
8556 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8557 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8560 ISD::LoadExtType ExtType;
8562 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8563 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8564 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8567 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8568 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8569 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8572 // The AND is not necessary, remove it.
8574 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8575 SubsNode->getValueType(1));
8576 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8578 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8579 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8581 return SDValue(N, 0);
8584 // Optimize compare with zero and branch.
8585 static SDValue performBRCONDCombine(SDNode *N,
8586 TargetLowering::DAGCombinerInfo &DCI,
8587 SelectionDAG &DAG) {
8588 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8591 SDValue Chain = N->getOperand(0);
8592 SDValue Dest = N->getOperand(1);
8593 SDValue CCVal = N->getOperand(2);
8594 SDValue Cmp = N->getOperand(3);
8596 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8597 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8598 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8601 unsigned CmpOpc = Cmp.getOpcode();
8602 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8605 // Only attempt folding if there is only one use of the flag and no use of the
8607 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8610 SDValue LHS = Cmp.getOperand(0);
8611 SDValue RHS = Cmp.getOperand(1);
8613 assert(LHS.getValueType() == RHS.getValueType() &&
8614 "Expected the value type to be the same for both operands!");
8615 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8618 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8619 std::swap(LHS, RHS);
8621 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8624 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8625 LHS.getOpcode() == ISD::SRL)
8628 // Fold the compare into the branch instruction.
8630 if (CC == AArch64CC::EQ)
8631 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8633 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8635 // Do not add new nodes to DAG combiner worklist.
8636 DCI.CombineTo(N, BR, false);
8641 // vselect (v1i1 setcc) ->
8642 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8643 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8644 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8646 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8647 SDValue N0 = N->getOperand(0);
8648 EVT CCVT = N0.getValueType();
8650 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8651 CCVT.getVectorElementType() != MVT::i1)
8654 EVT ResVT = N->getValueType(0);
8655 EVT CmpVT = N0.getOperand(0).getValueType();
8656 // Only combine when the result type is of the same size as the compared
8658 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8661 SDValue IfTrue = N->getOperand(1);
8662 SDValue IfFalse = N->getOperand(2);
8664 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8665 N0.getOperand(0), N0.getOperand(1),
8666 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8667 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8671 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8672 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8673 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8674 /// with a vector one followed by a DUP shuffle on the result.
8675 static SDValue performSelectCombine(SDNode *N,
8676 TargetLowering::DAGCombinerInfo &DCI) {
8677 SelectionDAG &DAG = DCI.DAG;
8678 SDValue N0 = N->getOperand(0);
8679 EVT ResVT = N->getValueType(0);
8681 if (N0.getOpcode() != ISD::SETCC)
8684 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
8685 // scalar SetCCResultType. We also don't expect vectors, because we assume
8686 // that selects fed by vector SETCCs are canonicalized to VSELECT.
8687 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
8688 "Scalar-SETCC feeding SELECT has unexpected result type!");
8690 // If NumMaskElts == 0, the comparison is larger than select result. The
8691 // largest real NEON comparison is 64-bits per lane, which means the result is
8692 // at most 32-bits and an illegal vector. Just bail out for now.
8693 EVT SrcVT = N0.getOperand(0).getValueType();
8695 // Don't try to do this optimization when the setcc itself has i1 operands.
8696 // There are no legal vectors of i1, so this would be pointless.
8697 if (SrcVT == MVT::i1)
8700 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8701 if (!ResVT.isVector() || NumMaskElts == 0)
8704 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8705 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8707 // Also bail out if the vector CCVT isn't the same size as ResVT.
8708 // This can happen if the SETCC operand size doesn't divide the ResVT size
8709 // (e.g., f64 vs v3f32).
8710 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
8713 // Make sure we didn't create illegal types, if we're not supposed to.
8714 assert(DCI.isBeforeLegalize() ||
8715 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
8717 // First perform a vector comparison, where lane 0 is the one we're interested
8721 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8723 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8724 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8726 // Now duplicate the comparison mask we want across all other lanes.
8727 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8728 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8729 Mask = DAG.getNode(ISD::BITCAST, DL,
8730 ResVT.changeVectorElementTypeToInteger(), Mask);
8732 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8735 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8736 DAGCombinerInfo &DCI) const {
8737 SelectionDAG &DAG = DCI.DAG;
8738 switch (N->getOpcode()) {
8743 return performAddSubLongCombine(N, DCI, DAG);
8745 return performXorCombine(N, DAG, DCI, Subtarget);
8747 return performMulCombine(N, DAG, DCI, Subtarget);
8748 case ISD::SINT_TO_FP:
8749 case ISD::UINT_TO_FP:
8750 return performIntToFpCombine(N, DAG, Subtarget);
8752 return performORCombine(N, DCI, Subtarget);
8753 case ISD::INTRINSIC_WO_CHAIN:
8754 return performIntrinsicCombine(N, DCI, Subtarget);
8755 case ISD::ANY_EXTEND:
8756 case ISD::ZERO_EXTEND:
8757 case ISD::SIGN_EXTEND:
8758 return performExtendCombine(N, DCI, DAG);
8760 return performBitcastCombine(N, DCI, DAG);
8761 case ISD::CONCAT_VECTORS:
8762 return performConcatVectorsCombine(N, DCI, DAG);
8764 return performSelectCombine(N, DCI);
8766 return performVSelectCombine(N, DCI.DAG);
8768 return performSTORECombine(N, DCI, DAG, Subtarget);
8769 case AArch64ISD::BRCOND:
8770 return performBRCONDCombine(N, DCI, DAG);
8771 case AArch64ISD::CSEL:
8772 return performCONDCombine(N, DCI, DAG, 2, 3);
8773 case AArch64ISD::DUP:
8774 return performPostLD1Combine(N, DCI, false);
8775 case ISD::INSERT_VECTOR_ELT:
8776 return performPostLD1Combine(N, DCI, true);
8777 case ISD::INTRINSIC_VOID:
8778 case ISD::INTRINSIC_W_CHAIN:
8779 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8780 case Intrinsic::aarch64_neon_ld2:
8781 case Intrinsic::aarch64_neon_ld3:
8782 case Intrinsic::aarch64_neon_ld4:
8783 case Intrinsic::aarch64_neon_ld1x2:
8784 case Intrinsic::aarch64_neon_ld1x3:
8785 case Intrinsic::aarch64_neon_ld1x4:
8786 case Intrinsic::aarch64_neon_ld2lane:
8787 case Intrinsic::aarch64_neon_ld3lane:
8788 case Intrinsic::aarch64_neon_ld4lane:
8789 case Intrinsic::aarch64_neon_ld2r:
8790 case Intrinsic::aarch64_neon_ld3r:
8791 case Intrinsic::aarch64_neon_ld4r:
8792 case Intrinsic::aarch64_neon_st2:
8793 case Intrinsic::aarch64_neon_st3:
8794 case Intrinsic::aarch64_neon_st4:
8795 case Intrinsic::aarch64_neon_st1x2:
8796 case Intrinsic::aarch64_neon_st1x3:
8797 case Intrinsic::aarch64_neon_st1x4:
8798 case Intrinsic::aarch64_neon_st2lane:
8799 case Intrinsic::aarch64_neon_st3lane:
8800 case Intrinsic::aarch64_neon_st4lane:
8801 return performNEONPostLDSTCombine(N, DCI, DAG);
8809 // Check if the return value is used as only a return value, as otherwise
8810 // we can't perform a tail-call. In particular, we need to check for
8811 // target ISD nodes that are returns and any other "odd" constructs
8812 // that the generic analysis code won't necessarily catch.
8813 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8814 SDValue &Chain) const {
8815 if (N->getNumValues() != 1)
8817 if (!N->hasNUsesOfValue(1, 0))
8820 SDValue TCChain = Chain;
8821 SDNode *Copy = *N->use_begin();
8822 if (Copy->getOpcode() == ISD::CopyToReg) {
8823 // If the copy has a glue operand, we conservatively assume it isn't safe to
8824 // perform a tail call.
8825 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8828 TCChain = Copy->getOperand(0);
8829 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8832 bool HasRet = false;
8833 for (SDNode *Node : Copy->uses()) {
8834 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8846 // Return whether the an instruction can potentially be optimized to a tail
8847 // call. This will cause the optimizers to attempt to move, or duplicate,
8848 // return instructions to help enable tail call optimizations for this
8850 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8851 if (!CI->isTailCall())
8857 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8859 ISD::MemIndexedMode &AM,
8861 SelectionDAG &DAG) const {
8862 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8865 Base = Op->getOperand(0);
8866 // All of the indexed addressing mode instructions take a signed
8867 // 9 bit immediate offset.
8868 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8869 int64_t RHSC = (int64_t)RHS->getZExtValue();
8870 if (RHSC >= 256 || RHSC <= -256)
8872 IsInc = (Op->getOpcode() == ISD::ADD);
8873 Offset = Op->getOperand(1);
8879 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8881 ISD::MemIndexedMode &AM,
8882 SelectionDAG &DAG) const {
8885 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8886 VT = LD->getMemoryVT();
8887 Ptr = LD->getBasePtr();
8888 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8889 VT = ST->getMemoryVT();
8890 Ptr = ST->getBasePtr();
8895 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8897 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8901 bool AArch64TargetLowering::getPostIndexedAddressParts(
8902 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8903 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8906 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8907 VT = LD->getMemoryVT();
8908 Ptr = LD->getBasePtr();
8909 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8910 VT = ST->getMemoryVT();
8911 Ptr = ST->getBasePtr();
8916 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8918 // Post-indexing updates the base, so it's not a valid transform
8919 // if that's not the same as the load's pointer.
8922 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8926 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8927 SelectionDAG &DAG) {
8929 SDValue Op = N->getOperand(0);
8931 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8935 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8936 DAG.getUNDEF(MVT::i32), Op,
8937 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
8939 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8940 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8943 void AArch64TargetLowering::ReplaceNodeResults(
8944 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8945 switch (N->getOpcode()) {
8947 llvm_unreachable("Don't know how to custom expand this");
8949 ReplaceBITCASTResults(N, Results, DAG);
8951 case ISD::FP_TO_UINT:
8952 case ISD::FP_TO_SINT:
8953 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8954 // Let normal code take care of it by not adding anything to Results.
8959 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8963 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8964 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8965 // reciprocal if there are three or more FDIVs.
8966 return NumUsers > 2;
8969 TargetLoweringBase::LegalizeTypeAction
8970 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8971 MVT SVT = VT.getSimpleVT();
8972 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8973 // v4i16, v2i32 instead of to promote.
8974 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8975 || SVT == MVT::v1f32)
8976 return TypeWidenVector;
8978 return TargetLoweringBase::getPreferredVectorAction(VT);
8981 // Loads and stores less than 128-bits are already atomic; ones above that
8982 // are doomed anyway, so defer to the default libcall and blame the OS when
8984 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8985 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8989 // Loads and stores less than 128-bits are already atomic; ones above that
8990 // are doomed anyway, so defer to the default libcall and blame the OS when
8992 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8993 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8997 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8998 TargetLoweringBase::AtomicRMWExpansionKind
8999 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9000 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9001 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9002 : AtomicRMWExpansionKind::None;
9005 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9009 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9010 AtomicOrdering Ord) const {
9011 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9012 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9013 bool IsAcquire = isAtLeastAcquire(Ord);
9015 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9016 // intrinsic must return {i64, i64} and we have to recombine them into a
9017 // single i128 here.
9018 if (ValTy->getPrimitiveSizeInBits() == 128) {
9020 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9021 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9023 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9024 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9026 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9027 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9028 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9029 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9030 return Builder.CreateOr(
9031 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9034 Type *Tys[] = { Addr->getType() };
9036 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9037 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9039 return Builder.CreateTruncOrBitCast(
9040 Builder.CreateCall(Ldxr, Addr),
9041 cast<PointerType>(Addr->getType())->getElementType());
9044 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9045 Value *Val, Value *Addr,
9046 AtomicOrdering Ord) const {
9047 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9048 bool IsRelease = isAtLeastRelease(Ord);
9050 // Since the intrinsics must have legal type, the i128 intrinsics take two
9051 // parameters: "i64, i64". We must marshal Val into the appropriate form
9053 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9055 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9056 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9057 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9059 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9060 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9061 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9062 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
9066 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9067 Type *Tys[] = { Addr->getType() };
9068 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9070 return Builder.CreateCall2(
9071 Stxr, Builder.CreateZExtOrBitCast(
9072 Val, Stxr->getFunctionType()->getParamType(0)),
9076 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9077 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9078 return Ty->isArrayTy();