1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is storage-only, so we promote operations to f32 if we know this is
285 // valid, and ignore them otherwise. The operations not mentioned here will
286 // fail to select, but this is not a major problem as no source language
287 // should be emitting native f16 operations yet.
288 setOperationAction(ISD::FADD, MVT::f16, Promote);
289 setOperationAction(ISD::FDIV, MVT::f16, Promote);
290 setOperationAction(ISD::FMUL, MVT::f16, Promote);
291 setOperationAction(ISD::FSUB, MVT::f16, Promote);
293 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
295 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
296 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
297 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
298 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
299 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
300 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
301 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
302 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
303 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
304 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
305 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
306 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
308 // Expand all other v4f16 operations.
309 // FIXME: We could generate better code by promoting some operations to
311 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
312 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
313 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
314 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
315 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
316 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
317 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
318 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
319 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
320 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
321 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
322 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
323 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
324 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
325 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
326 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
327 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
328 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
329 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
330 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
331 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
332 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
333 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
334 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
335 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
336 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
339 // v8f16 is also a storage-only type, so expand it.
340 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
341 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
342 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
343 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
344 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
345 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
346 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
347 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
348 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
349 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
350 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
351 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
352 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
353 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
354 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
355 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
356 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
357 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
358 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
359 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
360 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
361 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
362 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
363 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
364 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
365 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
366 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
367 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
368 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
369 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
370 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
372 // AArch64 has implementations of a lot of rounding-like FP operations.
373 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
374 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
375 MVT Ty = RoundingTypes[I];
376 setOperationAction(ISD::FFLOOR, Ty, Legal);
377 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
378 setOperationAction(ISD::FCEIL, Ty, Legal);
379 setOperationAction(ISD::FRINT, Ty, Legal);
380 setOperationAction(ISD::FTRUNC, Ty, Legal);
381 setOperationAction(ISD::FROUND, Ty, Legal);
384 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
386 if (Subtarget->isTargetMachO()) {
387 // For iOS, we don't want to the normal expansion of a libcall to
388 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
390 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
391 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
393 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
394 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
397 // Make floating-point constants legal for the large code model, so they don't
398 // become loads from the constant pool.
399 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
400 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
401 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
404 // AArch64 does not have floating-point extending loads, i1 sign-extending
405 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
406 for (MVT VT : MVT::fp_valuetypes()) {
407 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
408 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
409 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
410 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
412 for (MVT VT : MVT::integer_valuetypes())
413 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
415 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
416 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
417 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
418 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
419 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
420 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
421 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
423 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
424 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
426 // Indexed loads and stores are supported.
427 for (unsigned im = (unsigned)ISD::PRE_INC;
428 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
429 setIndexedLoadAction(im, MVT::i8, Legal);
430 setIndexedLoadAction(im, MVT::i16, Legal);
431 setIndexedLoadAction(im, MVT::i32, Legal);
432 setIndexedLoadAction(im, MVT::i64, Legal);
433 setIndexedLoadAction(im, MVT::f64, Legal);
434 setIndexedLoadAction(im, MVT::f32, Legal);
435 setIndexedStoreAction(im, MVT::i8, Legal);
436 setIndexedStoreAction(im, MVT::i16, Legal);
437 setIndexedStoreAction(im, MVT::i32, Legal);
438 setIndexedStoreAction(im, MVT::i64, Legal);
439 setIndexedStoreAction(im, MVT::f64, Legal);
440 setIndexedStoreAction(im, MVT::f32, Legal);
444 setOperationAction(ISD::TRAP, MVT::Other, Legal);
446 // We combine OR nodes for bitfield operations.
447 setTargetDAGCombine(ISD::OR);
449 // Vector add and sub nodes may conceal a high-half opportunity.
450 // Also, try to fold ADD into CSINC/CSINV..
451 setTargetDAGCombine(ISD::ADD);
452 setTargetDAGCombine(ISD::SUB);
454 setTargetDAGCombine(ISD::XOR);
455 setTargetDAGCombine(ISD::SINT_TO_FP);
456 setTargetDAGCombine(ISD::UINT_TO_FP);
458 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
460 setTargetDAGCombine(ISD::ANY_EXTEND);
461 setTargetDAGCombine(ISD::ZERO_EXTEND);
462 setTargetDAGCombine(ISD::SIGN_EXTEND);
463 setTargetDAGCombine(ISD::BITCAST);
464 setTargetDAGCombine(ISD::CONCAT_VECTORS);
465 setTargetDAGCombine(ISD::STORE);
467 setTargetDAGCombine(ISD::MUL);
469 setTargetDAGCombine(ISD::SELECT);
470 setTargetDAGCombine(ISD::VSELECT);
472 setTargetDAGCombine(ISD::INTRINSIC_VOID);
473 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
474 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
476 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
477 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
478 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
480 setStackPointerRegisterToSaveRestore(AArch64::SP);
482 setSchedulingPreference(Sched::Hybrid);
485 MaskAndBranchFoldingIsLegal = true;
487 setMinFunctionAlignment(2);
489 RequireStrictAlign = (Align == StrictAlign);
491 setHasExtractBitsInsn(true);
493 if (Subtarget->hasNEON()) {
494 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
495 // silliness like this:
496 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
497 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
498 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
500 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
501 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
502 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
503 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
504 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
505 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
506 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
507 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
508 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
509 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
510 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
511 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
512 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
513 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
514 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
515 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
516 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
517 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
518 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
519 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
520 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
522 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
523 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
524 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
525 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
526 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
528 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
530 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
531 // elements smaller than i32, so promote the input to i32 first.
532 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
533 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
534 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
535 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
536 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
537 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
538 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
539 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
540 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
542 // AArch64 doesn't have MUL.2d:
543 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
544 // Custom handling for some quad-vector types to detect MULL.
545 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
546 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
547 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
549 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
550 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
551 // Likewise, narrowing and extending vector loads/stores aren't handled
553 for (MVT VT : MVT::vector_valuetypes()) {
554 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
556 setOperationAction(ISD::MULHS, VT, Expand);
557 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
558 setOperationAction(ISD::MULHU, VT, Expand);
559 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
561 setOperationAction(ISD::BSWAP, VT, Expand);
563 for (MVT InnerVT : MVT::vector_valuetypes()) {
564 setTruncStoreAction(VT, InnerVT, Expand);
565 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
566 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
567 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
571 // AArch64 has implementations of a lot of rounding-like FP operations.
572 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
573 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
574 MVT Ty = RoundingVecTypes[I];
575 setOperationAction(ISD::FFLOOR, Ty, Legal);
576 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
577 setOperationAction(ISD::FCEIL, Ty, Legal);
578 setOperationAction(ISD::FRINT, Ty, Legal);
579 setOperationAction(ISD::FTRUNC, Ty, Legal);
580 setOperationAction(ISD::FROUND, Ty, Legal);
584 // Prefer likely predicted branches to selects on out-of-order cores.
585 if (Subtarget->isCortexA57())
586 PredictableSelectIsExpensive = true;
589 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
590 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
591 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
592 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
594 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
595 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
596 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
597 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
598 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
600 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
601 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
604 // Mark vector float intrinsics as expand.
605 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
606 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
607 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
608 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
609 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
610 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
611 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
612 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
613 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
614 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
617 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
618 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
619 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
620 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
621 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
622 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
623 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
624 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
625 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
626 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
627 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
628 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
630 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
633 for (MVT InnerVT : MVT::all_valuetypes())
634 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
636 // CNT supports only B element sizes.
637 if (VT != MVT::v8i8 && VT != MVT::v16i8)
638 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
640 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
647 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
649 if (Subtarget->isLittleEndian()) {
650 for (unsigned im = (unsigned)ISD::PRE_INC;
651 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
652 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
653 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
658 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
659 addRegisterClass(VT, &AArch64::FPR64RegClass);
660 addTypeForNEON(VT, MVT::v2i32);
663 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
664 addRegisterClass(VT, &AArch64::FPR128RegClass);
665 addTypeForNEON(VT, MVT::v4i32);
668 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
671 return VT.changeVectorElementTypeToInteger();
674 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
675 /// Mask are known to be either zero or one and return them in the
676 /// KnownZero/KnownOne bitsets.
677 void AArch64TargetLowering::computeKnownBitsForTargetNode(
678 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
679 const SelectionDAG &DAG, unsigned Depth) const {
680 switch (Op.getOpcode()) {
683 case AArch64ISD::CSEL: {
684 APInt KnownZero2, KnownOne2;
685 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
686 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
687 KnownZero &= KnownZero2;
688 KnownOne &= KnownOne2;
691 case ISD::INTRINSIC_W_CHAIN: {
692 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
693 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
696 case Intrinsic::aarch64_ldaxr:
697 case Intrinsic::aarch64_ldxr: {
698 unsigned BitWidth = KnownOne.getBitWidth();
699 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
700 unsigned MemBits = VT.getScalarType().getSizeInBits();
701 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
707 case ISD::INTRINSIC_WO_CHAIN:
708 case ISD::INTRINSIC_VOID: {
709 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
713 case Intrinsic::aarch64_neon_umaxv:
714 case Intrinsic::aarch64_neon_uminv: {
715 // Figure out the datatype of the vector operand. The UMINV instruction
716 // will zero extend the result, so we can mark as known zero all the
717 // bits larger than the element datatype. 32-bit or larget doesn't need
718 // this as those are legal types and will be handled by isel directly.
719 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
720 unsigned BitWidth = KnownZero.getBitWidth();
721 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
722 assert(BitWidth >= 8 && "Unexpected width!");
723 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
725 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
726 assert(BitWidth >= 16 && "Unexpected width!");
727 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
737 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
742 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
743 const TargetLibraryInfo *libInfo) const {
744 return AArch64::createFastISel(funcInfo, libInfo);
747 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
751 case AArch64ISD::CALL: return "AArch64ISD::CALL";
752 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
753 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
754 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
755 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
756 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
757 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
758 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
759 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
760 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
761 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
762 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
763 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
764 case AArch64ISD::ADC: return "AArch64ISD::ADC";
765 case AArch64ISD::SBC: return "AArch64ISD::SBC";
766 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
767 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
768 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
769 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
770 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
771 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
772 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
773 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
774 case AArch64ISD::DUP: return "AArch64ISD::DUP";
775 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
776 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
777 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
778 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
779 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
780 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
781 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
782 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
783 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
784 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
785 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
786 case AArch64ISD::BICi: return "AArch64ISD::BICi";
787 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
788 case AArch64ISD::BSL: return "AArch64ISD::BSL";
789 case AArch64ISD::NEG: return "AArch64ISD::NEG";
790 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
791 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
792 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
793 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
794 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
795 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
796 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
797 case AArch64ISD::REV16: return "AArch64ISD::REV16";
798 case AArch64ISD::REV32: return "AArch64ISD::REV32";
799 case AArch64ISD::REV64: return "AArch64ISD::REV64";
800 case AArch64ISD::EXT: return "AArch64ISD::EXT";
801 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
802 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
803 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
804 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
805 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
806 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
807 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
808 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
809 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
810 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
811 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
812 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
813 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
814 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
815 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
816 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
817 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
818 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
819 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
820 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
821 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
822 case AArch64ISD::NOT: return "AArch64ISD::NOT";
823 case AArch64ISD::BIT: return "AArch64ISD::BIT";
824 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
825 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
826 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
827 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
828 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
829 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
830 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
831 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
832 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
833 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
834 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
835 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
836 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
837 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
838 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
839 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
840 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
841 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
842 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
843 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
844 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
845 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
846 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
847 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
848 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
849 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
850 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
851 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
852 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
853 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
854 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
855 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
856 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
857 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
858 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
859 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
860 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
861 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
862 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
867 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
868 MachineBasicBlock *MBB) const {
869 // We materialise the F128CSEL pseudo-instruction as some control flow and a
873 // [... previous instrs leading to comparison ...]
879 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
881 MachineFunction *MF = MBB->getParent();
882 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
883 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
884 DebugLoc DL = MI->getDebugLoc();
885 MachineFunction::iterator It = MBB;
888 unsigned DestReg = MI->getOperand(0).getReg();
889 unsigned IfTrueReg = MI->getOperand(1).getReg();
890 unsigned IfFalseReg = MI->getOperand(2).getReg();
891 unsigned CondCode = MI->getOperand(3).getImm();
892 bool NZCVKilled = MI->getOperand(4).isKill();
894 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
895 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
896 MF->insert(It, TrueBB);
897 MF->insert(It, EndBB);
899 // Transfer rest of current basic-block to EndBB
900 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
902 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
904 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
905 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
906 MBB->addSuccessor(TrueBB);
907 MBB->addSuccessor(EndBB);
909 // TrueBB falls through to the end.
910 TrueBB->addSuccessor(EndBB);
913 TrueBB->addLiveIn(AArch64::NZCV);
914 EndBB->addLiveIn(AArch64::NZCV);
917 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
923 MI->eraseFromParent();
928 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
929 MachineBasicBlock *BB) const {
930 switch (MI->getOpcode()) {
935 llvm_unreachable("Unexpected instruction for custom inserter!");
937 case AArch64::F128CSEL:
938 return EmitF128CSEL(MI, BB);
940 case TargetOpcode::STACKMAP:
941 case TargetOpcode::PATCHPOINT:
942 return emitPatchPoint(MI, BB);
946 //===----------------------------------------------------------------------===//
947 // AArch64 Lowering private implementation.
948 //===----------------------------------------------------------------------===//
950 //===----------------------------------------------------------------------===//
952 //===----------------------------------------------------------------------===//
954 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
956 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
959 llvm_unreachable("Unknown condition code!");
961 return AArch64CC::NE;
963 return AArch64CC::EQ;
965 return AArch64CC::GT;
967 return AArch64CC::GE;
969 return AArch64CC::LT;
971 return AArch64CC::LE;
973 return AArch64CC::HI;
975 return AArch64CC::HS;
977 return AArch64CC::LO;
979 return AArch64CC::LS;
983 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
984 static void changeFPCCToAArch64CC(ISD::CondCode CC,
985 AArch64CC::CondCode &CondCode,
986 AArch64CC::CondCode &CondCode2) {
987 CondCode2 = AArch64CC::AL;
990 llvm_unreachable("Unknown FP condition!");
993 CondCode = AArch64CC::EQ;
997 CondCode = AArch64CC::GT;
1001 CondCode = AArch64CC::GE;
1004 CondCode = AArch64CC::MI;
1007 CondCode = AArch64CC::LS;
1010 CondCode = AArch64CC::MI;
1011 CondCode2 = AArch64CC::GT;
1014 CondCode = AArch64CC::VC;
1017 CondCode = AArch64CC::VS;
1020 CondCode = AArch64CC::EQ;
1021 CondCode2 = AArch64CC::VS;
1024 CondCode = AArch64CC::HI;
1027 CondCode = AArch64CC::PL;
1031 CondCode = AArch64CC::LT;
1035 CondCode = AArch64CC::LE;
1039 CondCode = AArch64CC::NE;
1044 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1045 /// CC usable with the vector instructions. Fewer operations are available
1046 /// without a real NZCV register, so we have to use less efficient combinations
1047 /// to get the same effect.
1048 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1049 AArch64CC::CondCode &CondCode,
1050 AArch64CC::CondCode &CondCode2,
1055 // Mostly the scalar mappings work fine.
1056 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1059 Invert = true; // Fallthrough
1061 CondCode = AArch64CC::MI;
1062 CondCode2 = AArch64CC::GE;
1069 // All of the compare-mask comparisons are ordered, but we can switch
1070 // between the two by a double inversion. E.g. ULE == !OGT.
1072 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1077 static bool isLegalArithImmed(uint64_t C) {
1078 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1079 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1082 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1083 SDLoc dl, SelectionDAG &DAG) {
1084 EVT VT = LHS.getValueType();
1086 if (VT.isFloatingPoint())
1087 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1089 // The CMP instruction is just an alias for SUBS, and representing it as
1090 // SUBS means that it's possible to get CSE with subtract operations.
1091 // A later phase can perform the optimization of setting the destination
1092 // register to WZR/XZR if it ends up being unused.
1093 unsigned Opcode = AArch64ISD::SUBS;
1095 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1096 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1097 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1098 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1099 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1100 // can be set differently by this operation. It comes down to whether
1101 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1102 // everything is fine. If not then the optimization is wrong. Thus general
1103 // comparisons are only valid if op2 != 0.
1105 // So, finally, the only LLVM-native comparisons that don't mention C and V
1106 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1107 // the absence of information about op2.
1108 Opcode = AArch64ISD::ADDS;
1109 RHS = RHS.getOperand(1);
1110 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1111 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1112 !isUnsignedIntSetCC(CC)) {
1113 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1114 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1115 // of the signed comparisons.
1116 Opcode = AArch64ISD::ANDS;
1117 RHS = LHS.getOperand(1);
1118 LHS = LHS.getOperand(0);
1121 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1125 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1126 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1128 AArch64CC::CondCode AArch64CC;
1129 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1130 EVT VT = RHS.getValueType();
1131 uint64_t C = RHSC->getZExtValue();
1132 if (!isLegalArithImmed(C)) {
1133 // Constant does not fit, try adjusting it by one?
1139 if ((VT == MVT::i32 && C != 0x80000000 &&
1140 isLegalArithImmed((uint32_t)(C - 1))) ||
1141 (VT == MVT::i64 && C != 0x80000000ULL &&
1142 isLegalArithImmed(C - 1ULL))) {
1143 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1144 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1145 RHS = DAG.getConstant(C, VT);
1150 if ((VT == MVT::i32 && C != 0 &&
1151 isLegalArithImmed((uint32_t)(C - 1))) ||
1152 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1153 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1154 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1155 RHS = DAG.getConstant(C, VT);
1160 if ((VT == MVT::i32 && C != INT32_MAX &&
1161 isLegalArithImmed((uint32_t)(C + 1))) ||
1162 (VT == MVT::i64 && C != INT64_MAX &&
1163 isLegalArithImmed(C + 1ULL))) {
1164 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1165 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1166 RHS = DAG.getConstant(C, VT);
1171 if ((VT == MVT::i32 && C != UINT32_MAX &&
1172 isLegalArithImmed((uint32_t)(C + 1))) ||
1173 (VT == MVT::i64 && C != UINT64_MAX &&
1174 isLegalArithImmed(C + 1ULL))) {
1175 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1176 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1177 RHS = DAG.getConstant(C, VT);
1183 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1184 // For the i8 operand, the largest immediate is 255, so this can be easily
1185 // encoded in the compare instruction. For the i16 operand, however, the
1186 // largest immediate cannot be encoded in the compare.
1187 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1188 // constant. For example,
1190 // ldrh w0, [x0, #0]
1193 // ldrsh w0, [x0, #0]
1195 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1196 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1197 // both the LHS and RHS are truely zero extended and to make sure the
1198 // transformation is profitable.
1199 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1200 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1201 isa<LoadSDNode>(LHS)) {
1202 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1203 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1204 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1205 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1206 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1208 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1209 DAG.getValueType(MVT::i16));
1210 Cmp = emitComparison(SExt,
1211 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1213 AArch64CC = changeIntCCToAArch64CC(CC);
1214 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1220 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1221 AArch64CC = changeIntCCToAArch64CC(CC);
1222 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1226 static std::pair<SDValue, SDValue>
1227 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1228 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1229 "Unsupported value type");
1230 SDValue Value, Overflow;
1232 SDValue LHS = Op.getOperand(0);
1233 SDValue RHS = Op.getOperand(1);
1235 switch (Op.getOpcode()) {
1237 llvm_unreachable("Unknown overflow instruction!");
1239 Opc = AArch64ISD::ADDS;
1243 Opc = AArch64ISD::ADDS;
1247 Opc = AArch64ISD::SUBS;
1251 Opc = AArch64ISD::SUBS;
1254 // Multiply needs a little bit extra work.
1258 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1259 if (Op.getValueType() == MVT::i32) {
1260 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1261 // For a 32 bit multiply with overflow check we want the instruction
1262 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1263 // need to generate the following pattern:
1264 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1265 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1266 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1267 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1268 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1269 DAG.getConstant(0, MVT::i64));
1270 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1271 // operation. We need to clear out the upper 32 bits, because we used a
1272 // widening multiply that wrote all 64 bits. In the end this should be a
1274 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1276 // The signed overflow check requires more than just a simple check for
1277 // any bit set in the upper 32 bits of the result. These bits could be
1278 // just the sign bits of a negative number. To perform the overflow
1279 // check we have to arithmetic shift right the 32nd bit of the result by
1280 // 31 bits. Then we compare the result to the upper 32 bits.
1281 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1282 DAG.getConstant(32, MVT::i64));
1283 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1284 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1285 DAG.getConstant(31, MVT::i64));
1286 // It is important that LowerBits is last, otherwise the arithmetic
1287 // shift will not be folded into the compare (SUBS).
1288 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1289 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1292 // The overflow check for unsigned multiply is easy. We only need to
1293 // check if any of the upper 32 bits are set. This can be done with a
1294 // CMP (shifted register). For that we need to generate the following
1296 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1297 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1298 DAG.getConstant(32, MVT::i64));
1299 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1301 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1302 UpperBits).getValue(1);
1306 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1307 // For the 64 bit multiply
1308 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1310 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1311 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1312 DAG.getConstant(63, MVT::i64));
1313 // It is important that LowerBits is last, otherwise the arithmetic
1314 // shift will not be folded into the compare (SUBS).
1315 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1316 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1319 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1320 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1322 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1323 UpperBits).getValue(1);
1330 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1332 // Emit the AArch64 operation with overflow check.
1333 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1334 Overflow = Value.getValue(1);
1336 return std::make_pair(Value, Overflow);
1339 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1340 RTLIB::Libcall Call) const {
1341 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1342 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1346 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1347 SDValue Sel = Op.getOperand(0);
1348 SDValue Other = Op.getOperand(1);
1350 // If neither operand is a SELECT_CC, give up.
1351 if (Sel.getOpcode() != ISD::SELECT_CC)
1352 std::swap(Sel, Other);
1353 if (Sel.getOpcode() != ISD::SELECT_CC)
1356 // The folding we want to perform is:
1357 // (xor x, (select_cc a, b, cc, 0, -1) )
1359 // (csel x, (xor x, -1), cc ...)
1361 // The latter will get matched to a CSINV instruction.
1363 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1364 SDValue LHS = Sel.getOperand(0);
1365 SDValue RHS = Sel.getOperand(1);
1366 SDValue TVal = Sel.getOperand(2);
1367 SDValue FVal = Sel.getOperand(3);
1370 // FIXME: This could be generalized to non-integer comparisons.
1371 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1374 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1375 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1377 // The the values aren't constants, this isn't the pattern we're looking for.
1378 if (!CFVal || !CTVal)
1381 // We can commute the SELECT_CC by inverting the condition. This
1382 // might be needed to make this fit into a CSINV pattern.
1383 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1384 std::swap(TVal, FVal);
1385 std::swap(CTVal, CFVal);
1386 CC = ISD::getSetCCInverse(CC, true);
1389 // If the constants line up, perform the transform!
1390 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1392 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1395 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1396 DAG.getConstant(-1ULL, Other.getValueType()));
1398 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1405 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1406 EVT VT = Op.getValueType();
1408 // Let legalize expand this if it isn't a legal type yet.
1409 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1412 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1415 bool ExtraOp = false;
1416 switch (Op.getOpcode()) {
1418 llvm_unreachable("Invalid code");
1420 Opc = AArch64ISD::ADDS;
1423 Opc = AArch64ISD::SUBS;
1426 Opc = AArch64ISD::ADCS;
1430 Opc = AArch64ISD::SBCS;
1436 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1437 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1441 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1442 // Let legalize expand this if it isn't a legal type yet.
1443 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1446 AArch64CC::CondCode CC;
1447 // The actual operation that sets the overflow or carry flag.
1448 SDValue Value, Overflow;
1449 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1451 // We use 0 and 1 as false and true values.
1452 SDValue TVal = DAG.getConstant(1, MVT::i32);
1453 SDValue FVal = DAG.getConstant(0, MVT::i32);
1455 // We use an inverted condition, because the conditional select is inverted
1456 // too. This will allow it to be selected to a single instruction:
1457 // CSINC Wd, WZR, WZR, invert(cond).
1458 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1459 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1462 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1463 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1466 // Prefetch operands are:
1467 // 1: Address to prefetch
1469 // 3: int locality (0 = no locality ... 3 = extreme locality)
1470 // 4: bool isDataCache
1471 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1473 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1474 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1475 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1477 bool IsStream = !Locality;
1478 // When the locality number is set
1480 // The front-end should have filtered out the out-of-range values
1481 assert(Locality <= 3 && "Prefetch locality out-of-range");
1482 // The locality degree is the opposite of the cache speed.
1483 // Put the number the other way around.
1484 // The encoding starts at 0 for level 1
1485 Locality = 3 - Locality;
1488 // built the mask value encoding the expected behavior.
1489 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1490 (!IsData << 3) | // IsDataCache bit
1491 (Locality << 1) | // Cache level bits
1492 (unsigned)IsStream; // Stream bit
1493 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1494 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1497 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1498 SelectionDAG &DAG) const {
1499 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1502 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1504 return LowerF128Call(Op, DAG, LC);
1507 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1508 SelectionDAG &DAG) const {
1509 if (Op.getOperand(0).getValueType() != MVT::f128) {
1510 // It's legal except when f128 is involved
1515 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1517 // FP_ROUND node has a second operand indicating whether it is known to be
1518 // precise. That doesn't take part in the LibCall so we can't directly use
1520 SDValue SrcVal = Op.getOperand(0);
1521 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1522 /*isSigned*/ false, SDLoc(Op)).first;
1525 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1526 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1527 // Any additional optimization in this function should be recorded
1528 // in the cost tables.
1529 EVT InVT = Op.getOperand(0).getValueType();
1530 EVT VT = Op.getValueType();
1532 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1535 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1537 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1540 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1543 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1544 VT.getVectorNumElements());
1545 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1546 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1549 // Type changing conversions are illegal.
1553 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1554 SelectionDAG &DAG) const {
1555 if (Op.getOperand(0).getValueType().isVector())
1556 return LowerVectorFP_TO_INT(Op, DAG);
1558 if (Op.getOperand(0).getValueType() != MVT::f128) {
1559 // It's legal except when f128 is involved
1564 if (Op.getOpcode() == ISD::FP_TO_SINT)
1565 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1567 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1569 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1570 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1574 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1575 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1576 // Any additional optimization in this function should be recorded
1577 // in the cost tables.
1578 EVT VT = Op.getValueType();
1580 SDValue In = Op.getOperand(0);
1581 EVT InVT = In.getValueType();
1583 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1585 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1586 InVT.getVectorNumElements());
1587 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1588 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1591 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1593 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1594 EVT CastVT = VT.changeVectorElementTypeToInteger();
1595 In = DAG.getNode(CastOpc, dl, CastVT, In);
1596 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1602 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1603 SelectionDAG &DAG) const {
1604 if (Op.getValueType().isVector())
1605 return LowerVectorINT_TO_FP(Op, DAG);
1607 // i128 conversions are libcalls.
1608 if (Op.getOperand(0).getValueType() == MVT::i128)
1611 // Other conversions are legal, unless it's to the completely software-based
1613 if (Op.getValueType() != MVT::f128)
1617 if (Op.getOpcode() == ISD::SINT_TO_FP)
1618 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1620 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1622 return LowerF128Call(Op, DAG, LC);
1625 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1626 SelectionDAG &DAG) const {
1627 // For iOS, we want to call an alternative entry point: __sincos_stret,
1628 // which returns the values in two S / D registers.
1630 SDValue Arg = Op.getOperand(0);
1631 EVT ArgVT = Arg.getValueType();
1632 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1639 Entry.isSExt = false;
1640 Entry.isZExt = false;
1641 Args.push_back(Entry);
1643 const char *LibcallName =
1644 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1645 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1647 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1648 TargetLowering::CallLoweringInfo CLI(DAG);
1649 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1650 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1652 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1653 return CallResult.first;
1656 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1657 if (Op.getValueType() != MVT::f16)
1660 assert(Op.getOperand(0).getValueType() == MVT::i16);
1663 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1664 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1666 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1667 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1671 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1672 if (OrigVT.getSizeInBits() >= 64)
1675 assert(OrigVT.isSimple() && "Expecting a simple value type");
1677 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1678 switch (OrigSimpleTy) {
1679 default: llvm_unreachable("Unexpected Vector Type");
1688 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1691 unsigned ExtOpcode) {
1692 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1693 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1694 // 64-bits we need to insert a new extension so that it will be 64-bits.
1695 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1696 if (OrigTy.getSizeInBits() >= 64)
1699 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1700 EVT NewVT = getExtensionTo64Bits(OrigTy);
1702 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1705 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1707 EVT VT = N->getValueType(0);
1709 if (N->getOpcode() != ISD::BUILD_VECTOR)
1712 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1713 SDNode *Elt = N->getOperand(i).getNode();
1714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1715 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1716 unsigned HalfSize = EltSize / 2;
1718 if (!isIntN(HalfSize, C->getSExtValue()))
1721 if (!isUIntN(HalfSize, C->getZExtValue()))
1732 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1733 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1734 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1735 N->getOperand(0)->getValueType(0),
1739 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1740 EVT VT = N->getValueType(0);
1741 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1742 unsigned NumElts = VT.getVectorNumElements();
1743 MVT TruncVT = MVT::getIntegerVT(EltSize);
1744 SmallVector<SDValue, 8> Ops;
1745 for (unsigned i = 0; i != NumElts; ++i) {
1746 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1747 const APInt &CInt = C->getAPIntValue();
1748 // Element types smaller than 32 bits are not legal, so use i32 elements.
1749 // The values are implicitly truncated so sext vs. zext doesn't matter.
1750 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1752 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1753 MVT::getVectorVT(TruncVT, NumElts), Ops);
1756 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1757 if (N->getOpcode() == ISD::SIGN_EXTEND)
1759 if (isExtendedBUILD_VECTOR(N, DAG, true))
1764 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1765 if (N->getOpcode() == ISD::ZERO_EXTEND)
1767 if (isExtendedBUILD_VECTOR(N, DAG, false))
1772 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1773 unsigned Opcode = N->getOpcode();
1774 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1775 SDNode *N0 = N->getOperand(0).getNode();
1776 SDNode *N1 = N->getOperand(1).getNode();
1777 return N0->hasOneUse() && N1->hasOneUse() &&
1778 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1783 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1784 unsigned Opcode = N->getOpcode();
1785 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1786 SDNode *N0 = N->getOperand(0).getNode();
1787 SDNode *N1 = N->getOperand(1).getNode();
1788 return N0->hasOneUse() && N1->hasOneUse() &&
1789 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1794 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1795 // Multiplications are only custom-lowered for 128-bit vectors so that
1796 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1797 EVT VT = Op.getValueType();
1798 assert(VT.is128BitVector() && VT.isInteger() &&
1799 "unexpected type for custom-lowering ISD::MUL");
1800 SDNode *N0 = Op.getOperand(0).getNode();
1801 SDNode *N1 = Op.getOperand(1).getNode();
1802 unsigned NewOpc = 0;
1804 bool isN0SExt = isSignExtended(N0, DAG);
1805 bool isN1SExt = isSignExtended(N1, DAG);
1806 if (isN0SExt && isN1SExt)
1807 NewOpc = AArch64ISD::SMULL;
1809 bool isN0ZExt = isZeroExtended(N0, DAG);
1810 bool isN1ZExt = isZeroExtended(N1, DAG);
1811 if (isN0ZExt && isN1ZExt)
1812 NewOpc = AArch64ISD::UMULL;
1813 else if (isN1SExt || isN1ZExt) {
1814 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1815 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1816 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1817 NewOpc = AArch64ISD::SMULL;
1819 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1820 NewOpc = AArch64ISD::UMULL;
1822 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1824 NewOpc = AArch64ISD::UMULL;
1830 if (VT == MVT::v2i64)
1831 // Fall through to expand this. It is not legal.
1834 // Other vector multiplications are legal.
1839 // Legalize to a S/UMULL instruction
1842 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1844 Op0 = skipExtensionForVectorMULL(N0, DAG);
1845 assert(Op0.getValueType().is64BitVector() &&
1846 Op1.getValueType().is64BitVector() &&
1847 "unexpected types for extended operands to VMULL");
1848 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1850 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1851 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1852 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1853 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1854 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1855 EVT Op1VT = Op1.getValueType();
1856 return DAG.getNode(N0->getOpcode(), DL, VT,
1857 DAG.getNode(NewOpc, DL, VT,
1858 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1859 DAG.getNode(NewOpc, DL, VT,
1860 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1863 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1864 SelectionDAG &DAG) const {
1865 switch (Op.getOpcode()) {
1867 llvm_unreachable("unimplemented operand");
1870 return LowerBITCAST(Op, DAG);
1871 case ISD::GlobalAddress:
1872 return LowerGlobalAddress(Op, DAG);
1873 case ISD::GlobalTLSAddress:
1874 return LowerGlobalTLSAddress(Op, DAG);
1876 return LowerSETCC(Op, DAG);
1878 return LowerBR_CC(Op, DAG);
1880 return LowerSELECT(Op, DAG);
1881 case ISD::SELECT_CC:
1882 return LowerSELECT_CC(Op, DAG);
1883 case ISD::JumpTable:
1884 return LowerJumpTable(Op, DAG);
1885 case ISD::ConstantPool:
1886 return LowerConstantPool(Op, DAG);
1887 case ISD::BlockAddress:
1888 return LowerBlockAddress(Op, DAG);
1890 return LowerVASTART(Op, DAG);
1892 return LowerVACOPY(Op, DAG);
1894 return LowerVAARG(Op, DAG);
1899 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1906 return LowerXALUO(Op, DAG);
1908 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1910 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1912 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1914 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1916 return LowerFP_ROUND(Op, DAG);
1917 case ISD::FP_EXTEND:
1918 return LowerFP_EXTEND(Op, DAG);
1919 case ISD::FRAMEADDR:
1920 return LowerFRAMEADDR(Op, DAG);
1921 case ISD::RETURNADDR:
1922 return LowerRETURNADDR(Op, DAG);
1923 case ISD::INSERT_VECTOR_ELT:
1924 return LowerINSERT_VECTOR_ELT(Op, DAG);
1925 case ISD::EXTRACT_VECTOR_ELT:
1926 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1927 case ISD::BUILD_VECTOR:
1928 return LowerBUILD_VECTOR(Op, DAG);
1929 case ISD::VECTOR_SHUFFLE:
1930 return LowerVECTOR_SHUFFLE(Op, DAG);
1931 case ISD::EXTRACT_SUBVECTOR:
1932 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1936 return LowerVectorSRA_SRL_SHL(Op, DAG);
1937 case ISD::SHL_PARTS:
1938 return LowerShiftLeftParts(Op, DAG);
1939 case ISD::SRL_PARTS:
1940 case ISD::SRA_PARTS:
1941 return LowerShiftRightParts(Op, DAG);
1943 return LowerCTPOP(Op, DAG);
1944 case ISD::FCOPYSIGN:
1945 return LowerFCOPYSIGN(Op, DAG);
1947 return LowerVectorAND(Op, DAG);
1949 return LowerVectorOR(Op, DAG);
1951 return LowerXOR(Op, DAG);
1953 return LowerPREFETCH(Op, DAG);
1954 case ISD::SINT_TO_FP:
1955 case ISD::UINT_TO_FP:
1956 return LowerINT_TO_FP(Op, DAG);
1957 case ISD::FP_TO_SINT:
1958 case ISD::FP_TO_UINT:
1959 return LowerFP_TO_INT(Op, DAG);
1961 return LowerFSINCOS(Op, DAG);
1963 return LowerMUL(Op, DAG);
1967 /// getFunctionAlignment - Return the Log2 alignment of this function.
1968 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1972 //===----------------------------------------------------------------------===//
1973 // Calling Convention Implementation
1974 //===----------------------------------------------------------------------===//
1976 #include "AArch64GenCallingConv.inc"
1978 /// Selects the correct CCAssignFn for a given CallingConvention value.
1979 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1980 bool IsVarArg) const {
1983 llvm_unreachable("Unsupported calling convention.");
1984 case CallingConv::WebKit_JS:
1985 return CC_AArch64_WebKit_JS;
1986 case CallingConv::GHC:
1987 return CC_AArch64_GHC;
1988 case CallingConv::C:
1989 case CallingConv::Fast:
1990 if (!Subtarget->isTargetDarwin())
1991 return CC_AArch64_AAPCS;
1992 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1996 SDValue AArch64TargetLowering::LowerFormalArguments(
1997 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1998 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1999 SmallVectorImpl<SDValue> &InVals) const {
2000 MachineFunction &MF = DAG.getMachineFunction();
2001 MachineFrameInfo *MFI = MF.getFrameInfo();
2003 // Assign locations to all of the incoming arguments.
2004 SmallVector<CCValAssign, 16> ArgLocs;
2005 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2008 // At this point, Ins[].VT may already be promoted to i32. To correctly
2009 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2010 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2011 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2012 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2014 unsigned NumArgs = Ins.size();
2015 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2016 unsigned CurArgIdx = 0;
2017 for (unsigned i = 0; i != NumArgs; ++i) {
2018 MVT ValVT = Ins[i].VT;
2019 if (Ins[i].isOrigArg()) {
2020 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2021 CurArgIdx = Ins[i].getOrigArgIndex();
2023 // Get type of the original argument.
2024 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2025 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2026 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2027 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2029 else if (ActualMVT == MVT::i16)
2032 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2034 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2035 assert(!Res && "Call operand has unhandled type");
2038 assert(ArgLocs.size() == Ins.size());
2039 SmallVector<SDValue, 16> ArgValues;
2040 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2041 CCValAssign &VA = ArgLocs[i];
2043 if (Ins[i].Flags.isByVal()) {
2044 // Byval is used for HFAs in the PCS, but the system should work in a
2045 // non-compliant manner for larger structs.
2046 EVT PtrTy = getPointerTy();
2047 int Size = Ins[i].Flags.getByValSize();
2048 unsigned NumRegs = (Size + 7) / 8;
2050 // FIXME: This works on big-endian for composite byvals, which are the common
2051 // case. It should also work for fundamental types too.
2053 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2054 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2055 InVals.push_back(FrameIdxN);
2060 if (VA.isRegLoc()) {
2061 // Arguments stored in registers.
2062 EVT RegVT = VA.getLocVT();
2065 const TargetRegisterClass *RC;
2067 if (RegVT == MVT::i32)
2068 RC = &AArch64::GPR32RegClass;
2069 else if (RegVT == MVT::i64)
2070 RC = &AArch64::GPR64RegClass;
2071 else if (RegVT == MVT::f16)
2072 RC = &AArch64::FPR16RegClass;
2073 else if (RegVT == MVT::f32)
2074 RC = &AArch64::FPR32RegClass;
2075 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2076 RC = &AArch64::FPR64RegClass;
2077 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2078 RC = &AArch64::FPR128RegClass;
2080 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2082 // Transform the arguments in physical registers into virtual ones.
2083 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2084 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2086 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2087 // to 64 bits. Insert an assert[sz]ext to capture this, then
2088 // truncate to the right size.
2089 switch (VA.getLocInfo()) {
2091 llvm_unreachable("Unknown loc info!");
2092 case CCValAssign::Full:
2094 case CCValAssign::BCvt:
2095 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2097 case CCValAssign::AExt:
2098 case CCValAssign::SExt:
2099 case CCValAssign::ZExt:
2100 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2101 // nodes after our lowering.
2102 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2106 InVals.push_back(ArgValue);
2108 } else { // VA.isRegLoc()
2109 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2110 unsigned ArgOffset = VA.getLocMemOffset();
2111 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2113 uint32_t BEAlign = 0;
2114 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2115 !Ins[i].Flags.isInConsecutiveRegs())
2116 BEAlign = 8 - ArgSize;
2118 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2120 // Create load nodes to retrieve arguments from the stack.
2121 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2124 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2125 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2126 MVT MemVT = VA.getValVT();
2128 switch (VA.getLocInfo()) {
2131 case CCValAssign::BCvt:
2132 MemVT = VA.getLocVT();
2134 case CCValAssign::SExt:
2135 ExtType = ISD::SEXTLOAD;
2137 case CCValAssign::ZExt:
2138 ExtType = ISD::ZEXTLOAD;
2140 case CCValAssign::AExt:
2141 ExtType = ISD::EXTLOAD;
2145 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2146 MachinePointerInfo::getFixedStack(FI),
2147 MemVT, false, false, false, 0);
2149 InVals.push_back(ArgValue);
2155 if (!Subtarget->isTargetDarwin()) {
2156 // The AAPCS variadic function ABI is identical to the non-variadic
2157 // one. As a result there may be more arguments in registers and we should
2158 // save them for future reference.
2159 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2162 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2163 // This will point to the next argument passed via stack.
2164 unsigned StackOffset = CCInfo.getNextStackOffset();
2165 // We currently pass all varargs at 8-byte alignment.
2166 StackOffset = ((StackOffset + 7) & ~7);
2167 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2170 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2171 unsigned StackArgSize = CCInfo.getNextStackOffset();
2172 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2173 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2174 // This is a non-standard ABI so by fiat I say we're allowed to make full
2175 // use of the stack area to be popped, which must be aligned to 16 bytes in
2177 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2179 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2180 // a multiple of 16.
2181 FuncInfo->setArgumentStackToRestore(StackArgSize);
2183 // This realignment carries over to the available bytes below. Our own
2184 // callers will guarantee the space is free by giving an aligned value to
2187 // Even if we're not expected to free up the space, it's useful to know how
2188 // much is there while considering tail calls (because we can reuse it).
2189 FuncInfo->setBytesInStackArgArea(StackArgSize);
2194 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2195 SelectionDAG &DAG, SDLoc DL,
2196 SDValue &Chain) const {
2197 MachineFunction &MF = DAG.getMachineFunction();
2198 MachineFrameInfo *MFI = MF.getFrameInfo();
2199 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2201 SmallVector<SDValue, 8> MemOps;
2203 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2204 AArch64::X3, AArch64::X4, AArch64::X5,
2205 AArch64::X6, AArch64::X7 };
2206 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2207 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2209 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2211 if (GPRSaveSize != 0) {
2212 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2214 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2216 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2217 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2218 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2220 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2221 MachinePointerInfo::getStack(i * 8), false, false, 0);
2222 MemOps.push_back(Store);
2223 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2224 DAG.getConstant(8, getPointerTy()));
2227 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2228 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2230 if (Subtarget->hasFPARMv8()) {
2231 static const MCPhysReg FPRArgRegs[] = {
2232 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2233 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2234 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2235 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2237 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2239 if (FPRSaveSize != 0) {
2240 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2242 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2244 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2245 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2246 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2249 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2250 MachinePointerInfo::getStack(i * 16), false, false, 0);
2251 MemOps.push_back(Store);
2252 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2253 DAG.getConstant(16, getPointerTy()));
2256 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2257 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2260 if (!MemOps.empty()) {
2261 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2265 /// LowerCallResult - Lower the result values of a call into the
2266 /// appropriate copies out of appropriate physical registers.
2267 SDValue AArch64TargetLowering::LowerCallResult(
2268 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2269 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2270 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2271 SDValue ThisVal) const {
2272 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2273 ? RetCC_AArch64_WebKit_JS
2274 : RetCC_AArch64_AAPCS;
2275 // Assign locations to each value returned by this call.
2276 SmallVector<CCValAssign, 16> RVLocs;
2277 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2279 CCInfo.AnalyzeCallResult(Ins, RetCC);
2281 // Copy all of the result registers out of their specified physreg.
2282 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2283 CCValAssign VA = RVLocs[i];
2285 // Pass 'this' value directly from the argument to return value, to avoid
2286 // reg unit interference
2287 if (i == 0 && isThisReturn) {
2288 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2289 "unexpected return calling convention register assignment");
2290 InVals.push_back(ThisVal);
2295 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2296 Chain = Val.getValue(1);
2297 InFlag = Val.getValue(2);
2299 switch (VA.getLocInfo()) {
2301 llvm_unreachable("Unknown loc info!");
2302 case CCValAssign::Full:
2304 case CCValAssign::BCvt:
2305 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2309 InVals.push_back(Val);
2315 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2316 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2317 bool isCalleeStructRet, bool isCallerStructRet,
2318 const SmallVectorImpl<ISD::OutputArg> &Outs,
2319 const SmallVectorImpl<SDValue> &OutVals,
2320 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2321 // For CallingConv::C this function knows whether the ABI needs
2322 // changing. That's not true for other conventions so they will have to opt in
2324 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2327 const MachineFunction &MF = DAG.getMachineFunction();
2328 const Function *CallerF = MF.getFunction();
2329 CallingConv::ID CallerCC = CallerF->getCallingConv();
2330 bool CCMatch = CallerCC == CalleeCC;
2332 // Byval parameters hand the function a pointer directly into the stack area
2333 // we want to reuse during a tail call. Working around this *is* possible (see
2334 // X86) but less efficient and uglier in LowerCall.
2335 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2336 e = CallerF->arg_end();
2338 if (i->hasByValAttr())
2341 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2342 if (IsTailCallConvention(CalleeCC) && CCMatch)
2347 // Externally-defined functions with weak linkage should not be
2348 // tail-called on AArch64 when the OS does not support dynamic
2349 // pre-emption of symbols, as the AAELF spec requires normal calls
2350 // to undefined weak functions to be replaced with a NOP or jump to the
2351 // next instruction. The behaviour of branch instructions in this
2352 // situation (as used for tail calls) is implementation-defined, so we
2353 // cannot rely on the linker replacing the tail call with a return.
2354 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2355 const GlobalValue *GV = G->getGlobal();
2356 const Triple TT(getTargetMachine().getTargetTriple());
2357 if (GV->hasExternalWeakLinkage() &&
2358 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2362 // Now we search for cases where we can use a tail call without changing the
2363 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2366 // I want anyone implementing a new calling convention to think long and hard
2367 // about this assert.
2368 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2369 "Unexpected variadic calling convention");
2371 if (isVarArg && !Outs.empty()) {
2372 // At least two cases here: if caller is fastcc then we can't have any
2373 // memory arguments (we'd be expected to clean up the stack afterwards). If
2374 // caller is C then we could potentially use its argument area.
2376 // FIXME: for now we take the most conservative of these in both cases:
2377 // disallow all variadic memory operands.
2378 SmallVector<CCValAssign, 16> ArgLocs;
2379 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2382 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2383 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2384 if (!ArgLocs[i].isRegLoc())
2388 // If the calling conventions do not match, then we'd better make sure the
2389 // results are returned in the same way as what the caller expects.
2391 SmallVector<CCValAssign, 16> RVLocs1;
2392 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2394 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2396 SmallVector<CCValAssign, 16> RVLocs2;
2397 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2399 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2401 if (RVLocs1.size() != RVLocs2.size())
2403 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2404 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2406 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2408 if (RVLocs1[i].isRegLoc()) {
2409 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2412 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2418 // Nothing more to check if the callee is taking no arguments
2422 SmallVector<CCValAssign, 16> ArgLocs;
2423 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2426 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2428 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2430 // If the stack arguments for this call would fit into our own save area then
2431 // the call can be made tail.
2432 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2435 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2437 MachineFrameInfo *MFI,
2438 int ClobberedFI) const {
2439 SmallVector<SDValue, 8> ArgChains;
2440 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2441 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2443 // Include the original chain at the beginning of the list. When this is
2444 // used by target LowerCall hooks, this helps legalize find the
2445 // CALLSEQ_BEGIN node.
2446 ArgChains.push_back(Chain);
2448 // Add a chain value for each stack argument corresponding
2449 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2450 UE = DAG.getEntryNode().getNode()->use_end();
2452 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2453 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2454 if (FI->getIndex() < 0) {
2455 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2456 int64_t InLastByte = InFirstByte;
2457 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2459 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2460 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2461 ArgChains.push_back(SDValue(L, 1));
2464 // Build a tokenfactor for all the chains.
2465 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2468 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2469 bool TailCallOpt) const {
2470 return CallCC == CallingConv::Fast && TailCallOpt;
2473 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2474 return CallCC == CallingConv::Fast;
2477 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2478 /// and add input and output parameter nodes.
2480 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2481 SmallVectorImpl<SDValue> &InVals) const {
2482 SelectionDAG &DAG = CLI.DAG;
2484 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2485 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2486 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2487 SDValue Chain = CLI.Chain;
2488 SDValue Callee = CLI.Callee;
2489 bool &IsTailCall = CLI.IsTailCall;
2490 CallingConv::ID CallConv = CLI.CallConv;
2491 bool IsVarArg = CLI.IsVarArg;
2493 MachineFunction &MF = DAG.getMachineFunction();
2494 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2495 bool IsThisReturn = false;
2497 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2498 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2499 bool IsSibCall = false;
2502 // Check if it's really possible to do a tail call.
2503 IsTailCall = isEligibleForTailCallOptimization(
2504 Callee, CallConv, IsVarArg, IsStructRet,
2505 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2506 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2507 report_fatal_error("failed to perform tail call elimination on a call "
2508 "site marked musttail");
2510 // A sibling call is one where we're under the usual C ABI and not planning
2511 // to change that but can still do a tail call:
2512 if (!TailCallOpt && IsTailCall)
2519 // Analyze operands of the call, assigning locations to each operand.
2520 SmallVector<CCValAssign, 16> ArgLocs;
2521 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2525 // Handle fixed and variable vector arguments differently.
2526 // Variable vector arguments always go into memory.
2527 unsigned NumArgs = Outs.size();
2529 for (unsigned i = 0; i != NumArgs; ++i) {
2530 MVT ArgVT = Outs[i].VT;
2531 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2532 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2533 /*IsVarArg=*/ !Outs[i].IsFixed);
2534 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2535 assert(!Res && "Call operand has unhandled type");
2539 // At this point, Outs[].VT may already be promoted to i32. To correctly
2540 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2541 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2542 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2543 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2545 unsigned NumArgs = Outs.size();
2546 for (unsigned i = 0; i != NumArgs; ++i) {
2547 MVT ValVT = Outs[i].VT;
2548 // Get type of the original argument.
2549 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2550 /*AllowUnknown*/ true);
2551 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2552 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2553 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2554 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2556 else if (ActualMVT == MVT::i16)
2559 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2560 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2561 assert(!Res && "Call operand has unhandled type");
2566 // Get a count of how many bytes are to be pushed on the stack.
2567 unsigned NumBytes = CCInfo.getNextStackOffset();
2570 // Since we're not changing the ABI to make this a tail call, the memory
2571 // operands are already available in the caller's incoming argument space.
2575 // FPDiff is the byte offset of the call's argument area from the callee's.
2576 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2577 // by this amount for a tail call. In a sibling call it must be 0 because the
2578 // caller will deallocate the entire stack and the callee still expects its
2579 // arguments to begin at SP+0. Completely unused for non-tail calls.
2582 if (IsTailCall && !IsSibCall) {
2583 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2585 // Since callee will pop argument stack as a tail call, we must keep the
2586 // popped size 16-byte aligned.
2587 NumBytes = RoundUpToAlignment(NumBytes, 16);
2589 // FPDiff will be negative if this tail call requires more space than we
2590 // would automatically have in our incoming argument space. Positive if we
2591 // can actually shrink the stack.
2592 FPDiff = NumReusableBytes - NumBytes;
2594 // The stack pointer must be 16-byte aligned at all times it's used for a
2595 // memory operation, which in practice means at *all* times and in
2596 // particular across call boundaries. Therefore our own arguments started at
2597 // a 16-byte aligned SP and the delta applied for the tail call should
2598 // satisfy the same constraint.
2599 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2602 // Adjust the stack pointer for the new arguments...
2603 // These operations are automatically eliminated by the prolog/epilog pass
2606 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2608 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2610 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2611 SmallVector<SDValue, 8> MemOpChains;
2613 // Walk the register/memloc assignments, inserting copies/loads.
2614 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2615 ++i, ++realArgIdx) {
2616 CCValAssign &VA = ArgLocs[i];
2617 SDValue Arg = OutVals[realArgIdx];
2618 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2620 // Promote the value if needed.
2621 switch (VA.getLocInfo()) {
2623 llvm_unreachable("Unknown loc info!");
2624 case CCValAssign::Full:
2626 case CCValAssign::SExt:
2627 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2629 case CCValAssign::ZExt:
2630 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2632 case CCValAssign::AExt:
2633 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2634 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2635 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2636 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2638 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2640 case CCValAssign::BCvt:
2641 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2643 case CCValAssign::FPExt:
2644 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2648 if (VA.isRegLoc()) {
2649 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2650 assert(VA.getLocVT() == MVT::i64 &&
2651 "unexpected calling convention register assignment");
2652 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2653 "unexpected use of 'returned'");
2654 IsThisReturn = true;
2656 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2658 assert(VA.isMemLoc());
2661 MachinePointerInfo DstInfo;
2663 // FIXME: This works on big-endian for composite byvals, which are the
2664 // common case. It should also work for fundamental types too.
2665 uint32_t BEAlign = 0;
2666 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2667 : VA.getValVT().getSizeInBits();
2668 OpSize = (OpSize + 7) / 8;
2669 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2670 !Flags.isInConsecutiveRegs()) {
2672 BEAlign = 8 - OpSize;
2674 unsigned LocMemOffset = VA.getLocMemOffset();
2675 int32_t Offset = LocMemOffset + BEAlign;
2676 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2677 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2680 Offset = Offset + FPDiff;
2681 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2683 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2684 DstInfo = MachinePointerInfo::getFixedStack(FI);
2686 // Make sure any stack arguments overlapping with where we're storing
2687 // are loaded before this eventual operation. Otherwise they'll be
2689 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2691 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2693 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2694 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2697 if (Outs[i].Flags.isByVal()) {
2699 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2700 SDValue Cpy = DAG.getMemcpy(
2701 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2703 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2705 MemOpChains.push_back(Cpy);
2707 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2708 // promoted to a legal register type i32, we should truncate Arg back to
2710 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2711 VA.getValVT() == MVT::i16)
2712 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2715 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2716 MemOpChains.push_back(Store);
2721 if (!MemOpChains.empty())
2722 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2724 // Build a sequence of copy-to-reg nodes chained together with token chain
2725 // and flag operands which copy the outgoing args into the appropriate regs.
2727 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2728 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2729 RegsToPass[i].second, InFlag);
2730 InFlag = Chain.getValue(1);
2733 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2734 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2735 // node so that legalize doesn't hack it.
2736 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2737 Subtarget->isTargetMachO()) {
2738 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2739 const GlobalValue *GV = G->getGlobal();
2740 bool InternalLinkage = GV->hasInternalLinkage();
2741 if (InternalLinkage)
2742 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2744 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2746 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2748 } else if (ExternalSymbolSDNode *S =
2749 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2750 const char *Sym = S->getSymbol();
2752 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2753 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2755 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2756 const GlobalValue *GV = G->getGlobal();
2757 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2758 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2759 const char *Sym = S->getSymbol();
2760 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2763 // We don't usually want to end the call-sequence here because we would tidy
2764 // the frame up *after* the call, however in the ABI-changing tail-call case
2765 // we've carefully laid out the parameters so that when sp is reset they'll be
2766 // in the correct location.
2767 if (IsTailCall && !IsSibCall) {
2768 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2769 DAG.getIntPtrConstant(0, true), InFlag, DL);
2770 InFlag = Chain.getValue(1);
2773 std::vector<SDValue> Ops;
2774 Ops.push_back(Chain);
2775 Ops.push_back(Callee);
2778 // Each tail call may have to adjust the stack by a different amount, so
2779 // this information must travel along with the operation for eventual
2780 // consumption by emitEpilogue.
2781 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2784 // Add argument registers to the end of the list so that they are known live
2786 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2787 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2788 RegsToPass[i].second.getValueType()));
2790 // Add a register mask operand representing the call-preserved registers.
2791 const uint32_t *Mask;
2792 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2794 // For 'this' returns, use the X0-preserving mask if applicable
2795 Mask = TRI->getThisReturnPreservedMask(CallConv);
2797 IsThisReturn = false;
2798 Mask = TRI->getCallPreservedMask(CallConv);
2801 Mask = TRI->getCallPreservedMask(CallConv);
2803 assert(Mask && "Missing call preserved mask for calling convention");
2804 Ops.push_back(DAG.getRegisterMask(Mask));
2806 if (InFlag.getNode())
2807 Ops.push_back(InFlag);
2809 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2811 // If we're doing a tall call, use a TC_RETURN here rather than an
2812 // actual call instruction.
2814 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2816 // Returns a chain and a flag for retval copy to use.
2817 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2818 InFlag = Chain.getValue(1);
2820 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2821 ? RoundUpToAlignment(NumBytes, 16)
2824 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2825 DAG.getIntPtrConstant(CalleePopBytes, true),
2828 InFlag = Chain.getValue(1);
2830 // Handle result values, copying them out of physregs into vregs that we
2832 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2833 InVals, IsThisReturn,
2834 IsThisReturn ? OutVals[0] : SDValue());
2837 bool AArch64TargetLowering::CanLowerReturn(
2838 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2839 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2840 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2841 ? RetCC_AArch64_WebKit_JS
2842 : RetCC_AArch64_AAPCS;
2843 SmallVector<CCValAssign, 16> RVLocs;
2844 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2845 return CCInfo.CheckReturn(Outs, RetCC);
2849 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2851 const SmallVectorImpl<ISD::OutputArg> &Outs,
2852 const SmallVectorImpl<SDValue> &OutVals,
2853 SDLoc DL, SelectionDAG &DAG) const {
2854 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2855 ? RetCC_AArch64_WebKit_JS
2856 : RetCC_AArch64_AAPCS;
2857 SmallVector<CCValAssign, 16> RVLocs;
2858 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2860 CCInfo.AnalyzeReturn(Outs, RetCC);
2862 // Copy the result values into the output registers.
2864 SmallVector<SDValue, 4> RetOps(1, Chain);
2865 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2866 ++i, ++realRVLocIdx) {
2867 CCValAssign &VA = RVLocs[i];
2868 assert(VA.isRegLoc() && "Can only return in registers!");
2869 SDValue Arg = OutVals[realRVLocIdx];
2871 switch (VA.getLocInfo()) {
2873 llvm_unreachable("Unknown loc info!");
2874 case CCValAssign::Full:
2875 if (Outs[i].ArgVT == MVT::i1) {
2876 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2877 // value. This is strictly redundant on Darwin (which uses "zeroext
2878 // i1"), but will be optimised out before ISel.
2879 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2880 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2883 case CCValAssign::BCvt:
2884 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2888 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2889 Flag = Chain.getValue(1);
2890 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2893 RetOps[0] = Chain; // Update chain.
2895 // Add the flag if we have it.
2897 RetOps.push_back(Flag);
2899 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2902 //===----------------------------------------------------------------------===//
2903 // Other Lowering Code
2904 //===----------------------------------------------------------------------===//
2906 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2907 SelectionDAG &DAG) const {
2908 EVT PtrVT = getPointerTy();
2910 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2911 const GlobalValue *GV = GN->getGlobal();
2912 unsigned char OpFlags =
2913 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2915 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2916 "unexpected offset in global node");
2918 // This also catched the large code model case for Darwin.
2919 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2920 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2921 // FIXME: Once remat is capable of dealing with instructions with register
2922 // operands, expand this into two nodes instead of using a wrapper node.
2923 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2926 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2927 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2928 "use of MO_CONSTPOOL only supported on small model");
2929 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2930 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2931 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2932 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2933 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2934 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2935 MachinePointerInfo::getConstantPool(),
2936 /*isVolatile=*/ false,
2937 /*isNonTemporal=*/ true,
2938 /*isInvariant=*/ true, 8);
2939 if (GN->getOffset() != 0)
2940 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2941 DAG.getConstant(GN->getOffset(), PtrVT));
2945 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2946 const unsigned char MO_NC = AArch64II::MO_NC;
2948 AArch64ISD::WrapperLarge, DL, PtrVT,
2949 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2950 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2951 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2952 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2954 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2955 // the only correct model on Darwin.
2956 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2957 OpFlags | AArch64II::MO_PAGE);
2958 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2959 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2961 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2962 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2966 /// \brief Convert a TLS address reference into the correct sequence of loads
2967 /// and calls to compute the variable's address (for Darwin, currently) and
2968 /// return an SDValue containing the final node.
2970 /// Darwin only has one TLS scheme which must be capable of dealing with the
2971 /// fully general situation, in the worst case. This means:
2972 /// + "extern __thread" declaration.
2973 /// + Defined in a possibly unknown dynamic library.
2975 /// The general system is that each __thread variable has a [3 x i64] descriptor
2976 /// which contains information used by the runtime to calculate the address. The
2977 /// only part of this the compiler needs to know about is the first xword, which
2978 /// contains a function pointer that must be called with the address of the
2979 /// entire descriptor in "x0".
2981 /// Since this descriptor may be in a different unit, in general even the
2982 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2984 /// adrp x0, _var@TLVPPAGE
2985 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2986 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2987 /// ; the function pointer
2988 /// blr x1 ; Uses descriptor address in x0
2989 /// ; Address of _var is now in x0.
2991 /// If the address of _var's descriptor *is* known to the linker, then it can
2992 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2993 /// a slight efficiency gain.
2995 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2996 SelectionDAG &DAG) const {
2997 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3000 MVT PtrVT = getPointerTy();
3001 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3004 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3005 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3007 // The first entry in the descriptor is a function pointer that we must call
3008 // to obtain the address of the variable.
3009 SDValue Chain = DAG.getEntryNode();
3010 SDValue FuncTLVGet =
3011 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3012 false, true, true, 8);
3013 Chain = FuncTLVGet.getValue(1);
3015 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3016 MFI->setAdjustsStack(true);
3018 // TLS calls preserve all registers except those that absolutely must be
3019 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3021 const uint32_t *Mask =
3022 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3024 // Finally, we can make the call. This is just a degenerate version of a
3025 // normal AArch64 call node: x0 takes the address of the descriptor, and
3026 // returns the address of the variable in this thread.
3027 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3029 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3030 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3031 DAG.getRegisterMask(Mask), Chain.getValue(1));
3032 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3035 /// When accessing thread-local variables under either the general-dynamic or
3036 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3037 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3038 /// is a function pointer to carry out the resolution.
3040 /// The sequence is:
3041 /// adrp x0, :tlsdesc:var
3042 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3043 /// add x0, x0, #:tlsdesc_lo12:var
3044 /// .tlsdesccall var
3046 /// (TPIDR_EL0 offset now in x0)
3048 /// The above sequence must be produced unscheduled, to enable the linker to
3049 /// optimize/relax this sequence.
3050 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3051 /// above sequence, and expanded really late in the compilation flow, to ensure
3052 /// the sequence is produced as per above.
3053 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3054 SelectionDAG &DAG) const {
3055 EVT PtrVT = getPointerTy();
3057 SDValue Chain = DAG.getEntryNode();
3058 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3060 SmallVector<SDValue, 2> Ops;
3061 Ops.push_back(Chain);
3062 Ops.push_back(SymAddr);
3064 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3065 SDValue Glue = Chain.getValue(1);
3067 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3071 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3072 SelectionDAG &DAG) const {
3073 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3074 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3075 "ELF TLS only supported in small memory model");
3076 // Different choices can be made for the maximum size of the TLS area for a
3077 // module. For the small address model, the default TLS size is 16MiB and the
3078 // maximum TLS size is 4GiB.
3079 // FIXME: add -mtls-size command line option and make it control the 16MiB
3080 // vs. 4GiB code sequence generation.
3081 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3083 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3084 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3085 if (Model == TLSModel::LocalDynamic)
3086 Model = TLSModel::GeneralDynamic;
3090 EVT PtrVT = getPointerTy();
3092 const GlobalValue *GV = GA->getGlobal();
3094 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3096 if (Model == TLSModel::LocalExec) {
3097 SDValue HiVar = DAG.getTargetGlobalAddress(
3098 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3099 SDValue LoVar = DAG.getTargetGlobalAddress(
3101 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3103 SDValue TPWithOff_lo =
3104 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3105 HiVar, DAG.getTargetConstant(0, MVT::i32)),
3108 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3109 LoVar, DAG.getTargetConstant(0, MVT::i32)),
3112 } else if (Model == TLSModel::InitialExec) {
3113 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3114 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3115 } else if (Model == TLSModel::LocalDynamic) {
3116 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3117 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3118 // the beginning of the module's TLS region, followed by a DTPREL offset
3121 // These accesses will need deduplicating if there's more than one.
3122 AArch64FunctionInfo *MFI =
3123 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3124 MFI->incNumLocalDynamicTLSAccesses();
3126 // The call needs a relocation too for linker relaxation. It doesn't make
3127 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3129 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3132 // Now we can calculate the offset from TPIDR_EL0 to this module's
3133 // thread-local area.
3134 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3136 // Now use :dtprel_whatever: operations to calculate this variable's offset
3137 // in its thread-storage area.
3138 SDValue HiVar = DAG.getTargetGlobalAddress(
3139 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3140 SDValue LoVar = DAG.getTargetGlobalAddress(
3141 GV, DL, MVT::i64, 0,
3142 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3144 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3145 DAG.getTargetConstant(0, MVT::i32)),
3147 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3148 DAG.getTargetConstant(0, MVT::i32)),
3150 } else if (Model == TLSModel::GeneralDynamic) {
3151 // The call needs a relocation too for linker relaxation. It doesn't make
3152 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3155 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3157 // Finally we can make a call to calculate the offset from tpidr_el0.
3158 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3160 llvm_unreachable("Unsupported ELF TLS access model");
3162 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3165 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3166 SelectionDAG &DAG) const {
3167 if (Subtarget->isTargetDarwin())
3168 return LowerDarwinGlobalTLSAddress(Op, DAG);
3169 else if (Subtarget->isTargetELF())
3170 return LowerELFGlobalTLSAddress(Op, DAG);
3172 llvm_unreachable("Unexpected platform trying to use TLS");
3174 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3175 SDValue Chain = Op.getOperand(0);
3176 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3177 SDValue LHS = Op.getOperand(2);
3178 SDValue RHS = Op.getOperand(3);
3179 SDValue Dest = Op.getOperand(4);
3182 // Handle f128 first, since lowering it will result in comparing the return
3183 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3184 // is expecting to deal with.
3185 if (LHS.getValueType() == MVT::f128) {
3186 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3188 // If softenSetCCOperands returned a scalar, we need to compare the result
3189 // against zero to select between true and false values.
3190 if (!RHS.getNode()) {
3191 RHS = DAG.getConstant(0, LHS.getValueType());
3196 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3198 unsigned Opc = LHS.getOpcode();
3199 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3200 cast<ConstantSDNode>(RHS)->isOne() &&
3201 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3202 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3203 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3204 "Unexpected condition code.");
3205 // Only lower legal XALUO ops.
3206 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3209 // The actual operation with overflow check.
3210 AArch64CC::CondCode OFCC;
3211 SDValue Value, Overflow;
3212 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3214 if (CC == ISD::SETNE)
3215 OFCC = getInvertedCondCode(OFCC);
3216 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3218 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3222 if (LHS.getValueType().isInteger()) {
3223 assert((LHS.getValueType() == RHS.getValueType()) &&
3224 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3226 // If the RHS of the comparison is zero, we can potentially fold this
3227 // to a specialized branch.
3228 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3229 if (RHSC && RHSC->getZExtValue() == 0) {
3230 if (CC == ISD::SETEQ) {
3231 // See if we can use a TBZ to fold in an AND as well.
3232 // TBZ has a smaller branch displacement than CBZ. If the offset is
3233 // out of bounds, a late MI-layer pass rewrites branches.
3234 // 403.gcc is an example that hits this case.
3235 if (LHS.getOpcode() == ISD::AND &&
3236 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3237 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3238 SDValue Test = LHS.getOperand(0);
3239 uint64_t Mask = LHS.getConstantOperandVal(1);
3240 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3241 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3244 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3245 } else if (CC == ISD::SETNE) {
3246 // See if we can use a TBZ to fold in an AND as well.
3247 // TBZ has a smaller branch displacement than CBZ. If the offset is
3248 // out of bounds, a late MI-layer pass rewrites branches.
3249 // 403.gcc is an example that hits this case.
3250 if (LHS.getOpcode() == ISD::AND &&
3251 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3252 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3253 SDValue Test = LHS.getOperand(0);
3254 uint64_t Mask = LHS.getConstantOperandVal(1);
3255 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3256 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3259 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3260 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3261 // Don't combine AND since emitComparison converts the AND to an ANDS
3262 // (a.k.a. TST) and the test in the test bit and branch instruction
3263 // becomes redundant. This would also increase register pressure.
3264 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3265 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3266 DAG.getConstant(Mask, MVT::i64), Dest);
3269 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3270 LHS.getOpcode() != ISD::AND) {
3271 // Don't combine AND since emitComparison converts the AND to an ANDS
3272 // (a.k.a. TST) and the test in the test bit and branch instruction
3273 // becomes redundant. This would also increase register pressure.
3274 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3275 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3276 DAG.getConstant(Mask, MVT::i64), Dest);
3280 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3281 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3285 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3287 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3288 // clean. Some of them require two branches to implement.
3289 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3290 AArch64CC::CondCode CC1, CC2;
3291 changeFPCCToAArch64CC(CC, CC1, CC2);
3292 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3294 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3295 if (CC2 != AArch64CC::AL) {
3296 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3297 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3304 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3305 SelectionDAG &DAG) const {
3306 EVT VT = Op.getValueType();
3309 SDValue In1 = Op.getOperand(0);
3310 SDValue In2 = Op.getOperand(1);
3311 EVT SrcVT = In2.getValueType();
3313 if (SrcVT == MVT::f32 && VT == MVT::f64)
3314 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3315 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3316 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3318 // FIXME: Src type is different, bail out for now. Can VT really be a
3326 SDValue VecVal1, VecVal2;
3327 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3330 EltMask = 0x80000000ULL;
3332 if (!VT.isVector()) {
3333 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3334 DAG.getUNDEF(VecVT), In1);
3335 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3336 DAG.getUNDEF(VecVT), In2);
3338 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3339 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3341 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3345 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3346 // immediate moves cannot materialize that in a single instruction for
3347 // 64-bit elements. Instead, materialize zero and then negate it.
3350 if (!VT.isVector()) {
3351 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3352 DAG.getUNDEF(VecVT), In1);
3353 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3354 DAG.getUNDEF(VecVT), In2);
3356 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3357 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3360 llvm_unreachable("Invalid type for copysign!");
3363 SDValue BuildVec = DAG.getConstant(EltMask, VecVT);
3365 // If we couldn't materialize the mask above, then the mask vector will be
3366 // the zero vector, and we need to negate it here.
3367 if (VT == MVT::f64 || VT == MVT::v2f64) {
3368 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3369 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3370 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3374 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3377 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3378 else if (VT == MVT::f64)
3379 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3381 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3384 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3385 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3386 Attribute::NoImplicitFloat))
3389 if (!Subtarget->hasNEON())
3392 // While there is no integer popcount instruction, it can
3393 // be more efficiently lowered to the following sequence that uses
3394 // AdvSIMD registers/instructions as long as the copies to/from
3395 // the AdvSIMD registers are cheap.
3396 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3397 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3398 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3399 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3400 SDValue Val = Op.getOperand(0);
3402 EVT VT = Op.getValueType();
3405 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3406 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3408 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3409 SDValue UaddLV = DAG.getNode(
3410 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3411 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3414 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3418 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3420 if (Op.getValueType().isVector())
3421 return LowerVSETCC(Op, DAG);
3423 SDValue LHS = Op.getOperand(0);
3424 SDValue RHS = Op.getOperand(1);
3425 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3428 // We chose ZeroOrOneBooleanContents, so use zero and one.
3429 EVT VT = Op.getValueType();
3430 SDValue TVal = DAG.getConstant(1, VT);
3431 SDValue FVal = DAG.getConstant(0, VT);
3433 // Handle f128 first, since one possible outcome is a normal integer
3434 // comparison which gets picked up by the next if statement.
3435 if (LHS.getValueType() == MVT::f128) {
3436 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3438 // If softenSetCCOperands returned a scalar, use it.
3439 if (!RHS.getNode()) {
3440 assert(LHS.getValueType() == Op.getValueType() &&
3441 "Unexpected setcc expansion!");
3446 if (LHS.getValueType().isInteger()) {
3449 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3451 // Note that we inverted the condition above, so we reverse the order of
3452 // the true and false operands here. This will allow the setcc to be
3453 // matched to a single CSINC instruction.
3454 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3457 // Now we know we're dealing with FP values.
3458 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3460 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3461 // and do the comparison.
3462 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3464 AArch64CC::CondCode CC1, CC2;
3465 changeFPCCToAArch64CC(CC, CC1, CC2);
3466 if (CC2 == AArch64CC::AL) {
3467 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3468 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3470 // Note that we inverted the condition above, so we reverse the order of
3471 // the true and false operands here. This will allow the setcc to be
3472 // matched to a single CSINC instruction.
3473 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3475 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3476 // totally clean. Some of them require two CSELs to implement. As is in
3477 // this case, we emit the first CSEL and then emit a second using the output
3478 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3480 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3481 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3483 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3485 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3486 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3490 /// A SELECT_CC operation is really some kind of max or min if both values being
3491 /// compared are, in some sense, equal to the results in either case. However,
3492 /// it is permissible to compare f32 values and produce directly extended f64
3495 /// Extending the comparison operands would also be allowed, but is less likely
3496 /// to happen in practice since their use is right here. Note that truncate
3497 /// operations would *not* be semantically equivalent.
3498 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3502 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3503 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3504 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3505 Result.getValueType() == MVT::f64) {
3507 APFloat CmpVal = CCmp->getValueAPF();
3508 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3509 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3512 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3515 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3516 SelectionDAG &DAG) const {
3517 SDValue CC = Op->getOperand(0);
3518 SDValue TVal = Op->getOperand(1);
3519 SDValue FVal = Op->getOperand(2);
3522 unsigned Opc = CC.getOpcode();
3523 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3525 if (CC.getResNo() == 1 &&
3526 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3527 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3528 // Only lower legal XALUO ops.
3529 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3532 AArch64CC::CondCode OFCC;
3533 SDValue Value, Overflow;
3534 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3535 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3537 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3541 if (CC.getOpcode() == ISD::SETCC)
3542 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3543 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3545 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3549 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3550 SelectionDAG &DAG) const {
3551 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3552 SDValue LHS = Op.getOperand(0);
3553 SDValue RHS = Op.getOperand(1);
3554 SDValue TVal = Op.getOperand(2);
3555 SDValue FVal = Op.getOperand(3);
3558 // Handle f128 first, because it will result in a comparison of some RTLIB
3559 // call result against zero.
3560 if (LHS.getValueType() == MVT::f128) {
3561 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3563 // If softenSetCCOperands returned a scalar, we need to compare the result
3564 // against zero to select between true and false values.
3565 if (!RHS.getNode()) {
3566 RHS = DAG.getConstant(0, LHS.getValueType());
3571 // Handle integers first.
3572 if (LHS.getValueType().isInteger()) {
3573 assert((LHS.getValueType() == RHS.getValueType()) &&
3574 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3576 unsigned Opcode = AArch64ISD::CSEL;
3578 // If both the TVal and the FVal are constants, see if we can swap them in
3579 // order to for a CSINV or CSINC out of them.
3580 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3581 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3583 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3584 std::swap(TVal, FVal);
3585 std::swap(CTVal, CFVal);
3586 CC = ISD::getSetCCInverse(CC, true);
3587 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3588 std::swap(TVal, FVal);
3589 std::swap(CTVal, CFVal);
3590 CC = ISD::getSetCCInverse(CC, true);
3591 } else if (TVal.getOpcode() == ISD::XOR) {
3592 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3593 // with a CSINV rather than a CSEL.
3594 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3596 if (CVal && CVal->isAllOnesValue()) {
3597 std::swap(TVal, FVal);
3598 std::swap(CTVal, CFVal);
3599 CC = ISD::getSetCCInverse(CC, true);
3601 } else if (TVal.getOpcode() == ISD::SUB) {
3602 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3603 // that we can match with a CSNEG rather than a CSEL.
3604 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3606 if (CVal && CVal->isNullValue()) {
3607 std::swap(TVal, FVal);
3608 std::swap(CTVal, CFVal);
3609 CC = ISD::getSetCCInverse(CC, true);
3611 } else if (CTVal && CFVal) {
3612 const int64_t TrueVal = CTVal->getSExtValue();
3613 const int64_t FalseVal = CFVal->getSExtValue();
3616 // If both TVal and FVal are constants, see if FVal is the
3617 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3618 // instead of a CSEL in that case.
3619 if (TrueVal == ~FalseVal) {
3620 Opcode = AArch64ISD::CSINV;
3621 } else if (TrueVal == -FalseVal) {
3622 Opcode = AArch64ISD::CSNEG;
3623 } else if (TVal.getValueType() == MVT::i32) {
3624 // If our operands are only 32-bit wide, make sure we use 32-bit
3625 // arithmetic for the check whether we can use CSINC. This ensures that
3626 // the addition in the check will wrap around properly in case there is
3627 // an overflow (which would not be the case if we do the check with
3628 // 64-bit arithmetic).
3629 const uint32_t TrueVal32 = CTVal->getZExtValue();
3630 const uint32_t FalseVal32 = CFVal->getZExtValue();
3632 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3633 Opcode = AArch64ISD::CSINC;
3635 if (TrueVal32 > FalseVal32) {
3639 // 64-bit check whether we can use CSINC.
3640 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3641 Opcode = AArch64ISD::CSINC;
3643 if (TrueVal > FalseVal) {
3648 // Swap TVal and FVal if necessary.
3650 std::swap(TVal, FVal);
3651 std::swap(CTVal, CFVal);
3652 CC = ISD::getSetCCInverse(CC, true);
3655 if (Opcode != AArch64ISD::CSEL) {
3656 // Drop FVal since we can get its value by simply inverting/negating
3663 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3665 EVT VT = Op.getValueType();
3666 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3669 // Now we know we're dealing with FP values.
3670 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3671 assert(LHS.getValueType() == RHS.getValueType());
3672 EVT VT = Op.getValueType();
3674 // Try to match this select into a max/min operation, which have dedicated
3675 // opcode in the instruction set.
3676 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3678 if (getTargetMachine().Options.NoNaNsFPMath) {
3679 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3680 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3681 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3682 CC = ISD::getSetCCSwappedOperands(CC);
3683 std::swap(MinMaxLHS, MinMaxRHS);
3686 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3687 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3697 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3705 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3711 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3712 // and do the comparison.
3713 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3715 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3716 // clean. Some of them require two CSELs to implement.
3717 AArch64CC::CondCode CC1, CC2;
3718 changeFPCCToAArch64CC(CC, CC1, CC2);
3719 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3720 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3722 // If we need a second CSEL, emit it, using the output of the first as the
3723 // RHS. We're effectively OR'ing the two CC's together.
3724 if (CC2 != AArch64CC::AL) {
3725 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3726 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3729 // Otherwise, return the output of the first CSEL.
3733 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3734 SelectionDAG &DAG) const {
3735 // Jump table entries as PC relative offsets. No additional tweaking
3736 // is necessary here. Just get the address of the jump table.
3737 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3738 EVT PtrVT = getPointerTy();
3741 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3742 !Subtarget->isTargetMachO()) {
3743 const unsigned char MO_NC = AArch64II::MO_NC;
3745 AArch64ISD::WrapperLarge, DL, PtrVT,
3746 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3747 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3748 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3749 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3750 AArch64II::MO_G0 | MO_NC));
3754 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3755 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3756 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3757 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3758 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3761 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3762 SelectionDAG &DAG) const {
3763 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3764 EVT PtrVT = getPointerTy();
3767 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3768 // Use the GOT for the large code model on iOS.
3769 if (Subtarget->isTargetMachO()) {
3770 SDValue GotAddr = DAG.getTargetConstantPool(
3771 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3773 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3776 const unsigned char MO_NC = AArch64II::MO_NC;
3778 AArch64ISD::WrapperLarge, DL, PtrVT,
3779 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3780 CP->getOffset(), AArch64II::MO_G3),
3781 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3782 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3783 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3784 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3785 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3786 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3788 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3789 // ELF, the only valid one on Darwin.
3791 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3792 CP->getOffset(), AArch64II::MO_PAGE);
3793 SDValue Lo = DAG.getTargetConstantPool(
3794 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3795 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3797 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3798 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3802 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3803 SelectionDAG &DAG) const {
3804 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3805 EVT PtrVT = getPointerTy();
3807 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3808 !Subtarget->isTargetMachO()) {
3809 const unsigned char MO_NC = AArch64II::MO_NC;
3811 AArch64ISD::WrapperLarge, DL, PtrVT,
3812 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3813 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3814 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3815 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3817 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3818 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3820 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3821 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3825 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3826 SelectionDAG &DAG) const {
3827 AArch64FunctionInfo *FuncInfo =
3828 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3832 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3833 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3834 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3835 MachinePointerInfo(SV), false, false, 0);
3838 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3839 SelectionDAG &DAG) const {
3840 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3841 // Standard, section B.3.
3842 MachineFunction &MF = DAG.getMachineFunction();
3843 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3846 SDValue Chain = Op.getOperand(0);
3847 SDValue VAList = Op.getOperand(1);
3848 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3849 SmallVector<SDValue, 4> MemOps;
3851 // void *__stack at offset 0
3853 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3854 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3855 MachinePointerInfo(SV), false, false, 8));
3857 // void *__gr_top at offset 8
3858 int GPRSize = FuncInfo->getVarArgsGPRSize();
3860 SDValue GRTop, GRTopAddr;
3862 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3863 DAG.getConstant(8, getPointerTy()));
3865 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3866 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3867 DAG.getConstant(GPRSize, getPointerTy()));
3869 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3870 MachinePointerInfo(SV, 8), false, false, 8));
3873 // void *__vr_top at offset 16
3874 int FPRSize = FuncInfo->getVarArgsFPRSize();
3876 SDValue VRTop, VRTopAddr;
3877 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3878 DAG.getConstant(16, getPointerTy()));
3880 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3881 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3882 DAG.getConstant(FPRSize, getPointerTy()));
3884 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3885 MachinePointerInfo(SV, 16), false, false, 8));
3888 // int __gr_offs at offset 24
3889 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3890 DAG.getConstant(24, getPointerTy()));
3891 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3892 GROffsAddr, MachinePointerInfo(SV, 24), false,
3895 // int __vr_offs at offset 28
3896 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3897 DAG.getConstant(28, getPointerTy()));
3898 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3899 VROffsAddr, MachinePointerInfo(SV, 28), false,
3902 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3905 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3906 SelectionDAG &DAG) const {
3907 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3908 : LowerAAPCS_VASTART(Op, DAG);
3911 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3912 SelectionDAG &DAG) const {
3913 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3915 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3916 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3917 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3919 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3920 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3921 8, false, false, MachinePointerInfo(DestSV),
3922 MachinePointerInfo(SrcSV));
3925 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3926 assert(Subtarget->isTargetDarwin() &&
3927 "automatic va_arg instruction only works on Darwin");
3929 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3930 EVT VT = Op.getValueType();
3932 SDValue Chain = Op.getOperand(0);
3933 SDValue Addr = Op.getOperand(1);
3934 unsigned Align = Op.getConstantOperandVal(3);
3936 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3937 MachinePointerInfo(V), false, false, false, 0);
3938 Chain = VAList.getValue(1);
3941 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3942 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3943 DAG.getConstant(Align - 1, getPointerTy()));
3944 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3945 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3948 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3949 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3951 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3952 // up to 64 bits. At the very least, we have to increase the striding of the
3953 // vaargs list to match this, and for FP values we need to introduce
3954 // FP_ROUND nodes as well.
3955 if (VT.isInteger() && !VT.isVector())
3957 bool NeedFPTrunc = false;
3958 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3963 // Increment the pointer, VAList, to the next vaarg
3964 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3965 DAG.getConstant(ArgSize, getPointerTy()));
3966 // Store the incremented VAList to the legalized pointer
3967 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3970 // Load the actual argument out of the pointer VAList
3972 // Load the value as an f64.
3973 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3974 MachinePointerInfo(), false, false, false, 0);
3975 // Round the value down to an f32.
3976 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3977 DAG.getIntPtrConstant(1));
3978 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3979 // Merge the rounded value with the chain output of the load.
3980 return DAG.getMergeValues(Ops, DL);
3983 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3987 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3988 SelectionDAG &DAG) const {
3989 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3990 MFI->setFrameAddressIsTaken(true);
3992 EVT VT = Op.getValueType();
3994 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3996 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3998 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3999 MachinePointerInfo(), false, false, false, 0);
4003 // FIXME? Maybe this could be a TableGen attribute on some registers and
4004 // this table could be generated automatically from RegInfo.
4005 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4007 unsigned Reg = StringSwitch<unsigned>(RegName)
4008 .Case("sp", AArch64::SP)
4012 report_fatal_error("Invalid register name global variable");
4015 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4016 SelectionDAG &DAG) const {
4017 MachineFunction &MF = DAG.getMachineFunction();
4018 MachineFrameInfo *MFI = MF.getFrameInfo();
4019 MFI->setReturnAddressIsTaken(true);
4021 EVT VT = Op.getValueType();
4023 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4025 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4026 SDValue Offset = DAG.getConstant(8, getPointerTy());
4027 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4028 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4029 MachinePointerInfo(), false, false, false, 0);
4032 // Return LR, which contains the return address. Mark it an implicit live-in.
4033 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4034 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4037 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4038 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4039 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4040 SelectionDAG &DAG) const {
4041 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4042 EVT VT = Op.getValueType();
4043 unsigned VTBits = VT.getSizeInBits();
4045 SDValue ShOpLo = Op.getOperand(0);
4046 SDValue ShOpHi = Op.getOperand(1);
4047 SDValue ShAmt = Op.getOperand(2);
4049 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4051 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4053 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4054 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4055 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4056 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4057 DAG.getConstant(VTBits, MVT::i64));
4058 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4060 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4061 ISD::SETGE, dl, DAG);
4062 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4064 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4065 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4067 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4069 // AArch64 shifts larger than the register width are wrapped rather than
4070 // clamped, so we can't just emit "hi >> x".
4071 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4072 SDValue TrueValHi = Opc == ISD::SRA
4073 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4074 DAG.getConstant(VTBits - 1, MVT::i64))
4075 : DAG.getConstant(0, VT);
4077 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4079 SDValue Ops[2] = { Lo, Hi };
4080 return DAG.getMergeValues(Ops, dl);
4083 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4084 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4085 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4086 SelectionDAG &DAG) const {
4087 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4088 EVT VT = Op.getValueType();
4089 unsigned VTBits = VT.getSizeInBits();
4091 SDValue ShOpLo = Op.getOperand(0);
4092 SDValue ShOpHi = Op.getOperand(1);
4093 SDValue ShAmt = Op.getOperand(2);
4096 assert(Op.getOpcode() == ISD::SHL_PARTS);
4097 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4098 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4099 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4100 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4101 DAG.getConstant(VTBits, MVT::i64));
4102 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4103 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4105 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4107 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4108 ISD::SETGE, dl, DAG);
4109 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4111 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4113 // AArch64 shifts of larger than register sizes are wrapped rather than
4114 // clamped, so we can't just emit "lo << a" if a is too big.
4115 SDValue TrueValLo = DAG.getConstant(0, VT);
4116 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4118 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4120 SDValue Ops[2] = { Lo, Hi };
4121 return DAG.getMergeValues(Ops, dl);
4124 bool AArch64TargetLowering::isOffsetFoldingLegal(
4125 const GlobalAddressSDNode *GA) const {
4126 // The AArch64 target doesn't support folding offsets into global addresses.
4130 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4131 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4132 // FIXME: We should be able to handle f128 as well with a clever lowering.
4133 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4137 return AArch64_AM::getFP64Imm(Imm) != -1;
4138 else if (VT == MVT::f32)
4139 return AArch64_AM::getFP32Imm(Imm) != -1;
4143 //===----------------------------------------------------------------------===//
4144 // AArch64 Optimization Hooks
4145 //===----------------------------------------------------------------------===//
4147 //===----------------------------------------------------------------------===//
4148 // AArch64 Inline Assembly Support
4149 //===----------------------------------------------------------------------===//
4151 // Table of Constraints
4152 // TODO: This is the current set of constraints supported by ARM for the
4153 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4155 // r - A general register
4156 // w - An FP/SIMD register of some size in the range v0-v31
4157 // x - An FP/SIMD register of some size in the range v0-v15
4158 // I - Constant that can be used with an ADD instruction
4159 // J - Constant that can be used with a SUB instruction
4160 // K - Constant that can be used with a 32-bit logical instruction
4161 // L - Constant that can be used with a 64-bit logical instruction
4162 // M - Constant that can be used as a 32-bit MOV immediate
4163 // N - Constant that can be used as a 64-bit MOV immediate
4164 // Q - A memory reference with base register and no offset
4165 // S - A symbolic address
4166 // Y - Floating point constant zero
4167 // Z - Integer constant zero
4169 // Note that general register operands will be output using their 64-bit x
4170 // register name, whatever the size of the variable, unless the asm operand
4171 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4172 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4175 /// getConstraintType - Given a constraint letter, return the type of
4176 /// constraint it is for this target.
4177 AArch64TargetLowering::ConstraintType
4178 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4179 if (Constraint.size() == 1) {
4180 switch (Constraint[0]) {
4187 return C_RegisterClass;
4188 // An address with a single base register. Due to the way we
4189 // currently handle addresses it is the same as 'r'.
4194 return TargetLowering::getConstraintType(Constraint);
4197 /// Examine constraint type and operand type and determine a weight value.
4198 /// This object must already have been set up with the operand type
4199 /// and the current alternative constraint selected.
4200 TargetLowering::ConstraintWeight
4201 AArch64TargetLowering::getSingleConstraintMatchWeight(
4202 AsmOperandInfo &info, const char *constraint) const {
4203 ConstraintWeight weight = CW_Invalid;
4204 Value *CallOperandVal = info.CallOperandVal;
4205 // If we don't have a value, we can't do a match,
4206 // but allow it at the lowest weight.
4207 if (!CallOperandVal)
4209 Type *type = CallOperandVal->getType();
4210 // Look at the constraint type.
4211 switch (*constraint) {
4213 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4217 if (type->isFloatingPointTy() || type->isVectorTy())
4218 weight = CW_Register;
4221 weight = CW_Constant;
4227 std::pair<unsigned, const TargetRegisterClass *>
4228 AArch64TargetLowering::getRegForInlineAsmConstraint(
4229 const TargetRegisterInfo *TRI, const std::string &Constraint,
4231 if (Constraint.size() == 1) {
4232 switch (Constraint[0]) {
4234 if (VT.getSizeInBits() == 64)
4235 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4236 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4239 return std::make_pair(0U, &AArch64::FPR32RegClass);
4240 if (VT.getSizeInBits() == 64)
4241 return std::make_pair(0U, &AArch64::FPR64RegClass);
4242 if (VT.getSizeInBits() == 128)
4243 return std::make_pair(0U, &AArch64::FPR128RegClass);
4245 // The instructions that this constraint is designed for can
4246 // only take 128-bit registers so just use that regclass.
4248 if (VT.getSizeInBits() == 128)
4249 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4253 if (StringRef("{cc}").equals_lower(Constraint))
4254 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4256 // Use the default implementation in TargetLowering to convert the register
4257 // constraint into a member of a register class.
4258 std::pair<unsigned, const TargetRegisterClass *> Res;
4259 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4261 // Not found as a standard register?
4263 unsigned Size = Constraint.size();
4264 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4265 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4266 const std::string Reg =
4267 std::string(&Constraint[2], &Constraint[Size - 1]);
4268 int RegNo = atoi(Reg.c_str());
4269 if (RegNo >= 0 && RegNo <= 31) {
4270 // v0 - v31 are aliases of q0 - q31.
4271 // By default we'll emit v0-v31 for this unless there's a modifier where
4272 // we'll emit the correct register as well.
4273 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4274 Res.second = &AArch64::FPR128RegClass;
4282 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4283 /// vector. If it is invalid, don't add anything to Ops.
4284 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4285 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4286 SelectionDAG &DAG) const {
4289 // Currently only support length 1 constraints.
4290 if (Constraint.length() != 1)
4293 char ConstraintLetter = Constraint[0];
4294 switch (ConstraintLetter) {
4298 // This set of constraints deal with valid constants for various instructions.
4299 // Validate and return a target constant for them if we can.
4301 // 'z' maps to xzr or wzr so it needs an input of 0.
4302 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4303 if (!C || C->getZExtValue() != 0)
4306 if (Op.getValueType() == MVT::i64)
4307 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4309 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4319 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4323 // Grab the value and do some validation.
4324 uint64_t CVal = C->getZExtValue();
4325 switch (ConstraintLetter) {
4326 // The I constraint applies only to simple ADD or SUB immediate operands:
4327 // i.e. 0 to 4095 with optional shift by 12
4328 // The J constraint applies only to ADD or SUB immediates that would be
4329 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4330 // instruction [or vice versa], in other words -1 to -4095 with optional
4331 // left shift by 12.
4333 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4337 uint64_t NVal = -C->getSExtValue();
4338 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4339 CVal = C->getSExtValue();
4344 // The K and L constraints apply *only* to logical immediates, including
4345 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4346 // been removed and MOV should be used). So these constraints have to
4347 // distinguish between bit patterns that are valid 32-bit or 64-bit
4348 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4349 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4352 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4356 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4359 // The M and N constraints are a superset of K and L respectively, for use
4360 // with the MOV (immediate) alias. As well as the logical immediates they
4361 // also match 32 or 64-bit immediates that can be loaded either using a
4362 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4363 // (M) or 64-bit 0x1234000000000000 (N) etc.
4364 // As a note some of this code is liberally stolen from the asm parser.
4366 if (!isUInt<32>(CVal))
4368 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4370 if ((CVal & 0xFFFF) == CVal)
4372 if ((CVal & 0xFFFF0000ULL) == CVal)
4374 uint64_t NCVal = ~(uint32_t)CVal;
4375 if ((NCVal & 0xFFFFULL) == NCVal)
4377 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4382 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4384 if ((CVal & 0xFFFFULL) == CVal)
4386 if ((CVal & 0xFFFF0000ULL) == CVal)
4388 if ((CVal & 0xFFFF00000000ULL) == CVal)
4390 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4392 uint64_t NCVal = ~CVal;
4393 if ((NCVal & 0xFFFFULL) == NCVal)
4395 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4397 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4399 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4407 // All assembler immediates are 64-bit integers.
4408 Result = DAG.getTargetConstant(CVal, MVT::i64);
4412 if (Result.getNode()) {
4413 Ops.push_back(Result);
4417 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4420 //===----------------------------------------------------------------------===//
4421 // AArch64 Advanced SIMD Support
4422 //===----------------------------------------------------------------------===//
4424 /// WidenVector - Given a value in the V64 register class, produce the
4425 /// equivalent value in the V128 register class.
4426 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4427 EVT VT = V64Reg.getValueType();
4428 unsigned NarrowSize = VT.getVectorNumElements();
4429 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4430 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4433 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4434 V64Reg, DAG.getConstant(0, MVT::i32));
4437 /// getExtFactor - Determine the adjustment factor for the position when
4438 /// generating an "extract from vector registers" instruction.
4439 static unsigned getExtFactor(SDValue &V) {
4440 EVT EltType = V.getValueType().getVectorElementType();
4441 return EltType.getSizeInBits() / 8;
4444 /// NarrowVector - Given a value in the V128 register class, produce the
4445 /// equivalent value in the V64 register class.
4446 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4447 EVT VT = V128Reg.getValueType();
4448 unsigned WideSize = VT.getVectorNumElements();
4449 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4450 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4453 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4456 // Gather data to see if the operation can be modelled as a
4457 // shuffle in combination with VEXTs.
4458 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4459 SelectionDAG &DAG) const {
4460 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4462 EVT VT = Op.getValueType();
4463 unsigned NumElts = VT.getVectorNumElements();
4465 struct ShuffleSourceInfo {
4470 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4471 // be compatible with the shuffle we intend to construct. As a result
4472 // ShuffleVec will be some sliding window into the original Vec.
4475 // Code should guarantee that element i in Vec starts at element "WindowBase
4476 // + i * WindowScale in ShuffleVec".
4480 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4481 ShuffleSourceInfo(SDValue Vec)
4482 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4486 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4488 SmallVector<ShuffleSourceInfo, 2> Sources;
4489 for (unsigned i = 0; i < NumElts; ++i) {
4490 SDValue V = Op.getOperand(i);
4491 if (V.getOpcode() == ISD::UNDEF)
4493 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4494 // A shuffle can only come from building a vector from various
4495 // elements of other vectors.
4499 // Add this element source to the list if it's not already there.
4500 SDValue SourceVec = V.getOperand(0);
4501 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4502 if (Source == Sources.end())
4503 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4505 // Update the minimum and maximum lane number seen.
4506 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4507 Source->MinElt = std::min(Source->MinElt, EltNo);
4508 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4511 // Currently only do something sane when at most two source vectors
4513 if (Sources.size() > 2)
4516 // Find out the smallest element size among result and two sources, and use
4517 // it as element size to build the shuffle_vector.
4518 EVT SmallestEltTy = VT.getVectorElementType();
4519 for (auto &Source : Sources) {
4520 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4521 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4522 SmallestEltTy = SrcEltTy;
4525 unsigned ResMultiplier =
4526 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4527 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4528 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4530 // If the source vector is too wide or too narrow, we may nevertheless be able
4531 // to construct a compatible shuffle either by concatenating it with UNDEF or
4532 // extracting a suitable range of elements.
4533 for (auto &Src : Sources) {
4534 EVT SrcVT = Src.ShuffleVec.getValueType();
4536 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4539 // This stage of the search produces a source with the same element type as
4540 // the original, but with a total width matching the BUILD_VECTOR output.
4541 EVT EltVT = SrcVT.getVectorElementType();
4542 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4543 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4545 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4546 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4547 // We can pad out the smaller vector for free, so if it's part of a
4550 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4551 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4555 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4557 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4558 // Span too large for a VEXT to cope
4562 if (Src.MinElt >= NumSrcElts) {
4563 // The extraction can just take the second half
4565 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4566 DAG.getConstant(NumSrcElts, MVT::i64));
4567 Src.WindowBase = -NumSrcElts;
4568 } else if (Src.MaxElt < NumSrcElts) {
4569 // The extraction can just take the first half
4571 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4572 DAG.getConstant(0, MVT::i64));
4574 // An actual VEXT is needed
4576 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4577 DAG.getConstant(0, MVT::i64));
4579 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4580 DAG.getConstant(NumSrcElts, MVT::i64));
4581 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4583 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4584 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4585 Src.WindowBase = -Src.MinElt;
4589 // Another possible incompatibility occurs from the vector element types. We
4590 // can fix this by bitcasting the source vectors to the same type we intend
4592 for (auto &Src : Sources) {
4593 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4594 if (SrcEltTy == SmallestEltTy)
4596 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4597 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4598 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4599 Src.WindowBase *= Src.WindowScale;
4602 // Final sanity check before we try to actually produce a shuffle.
4604 for (auto Src : Sources)
4605 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4608 // The stars all align, our next step is to produce the mask for the shuffle.
4609 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4610 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4611 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4612 SDValue Entry = Op.getOperand(i);
4613 if (Entry.getOpcode() == ISD::UNDEF)
4616 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4617 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4619 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4620 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4622 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4623 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4624 VT.getVectorElementType().getSizeInBits());
4625 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4627 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4628 // starting at the appropriate offset.
4629 int *LaneMask = &Mask[i * ResMultiplier];
4631 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4632 ExtractBase += NumElts * (Src - Sources.begin());
4633 for (int j = 0; j < LanesDefined; ++j)
4634 LaneMask[j] = ExtractBase + j;
4637 // Final check before we try to produce nonsense...
4638 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4641 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4642 for (unsigned i = 0; i < Sources.size(); ++i)
4643 ShuffleOps[i] = Sources[i].ShuffleVec;
4645 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4646 ShuffleOps[1], &Mask[0]);
4647 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4650 // check if an EXT instruction can handle the shuffle mask when the
4651 // vector sources of the shuffle are the same.
4652 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4653 unsigned NumElts = VT.getVectorNumElements();
4655 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4661 // If this is a VEXT shuffle, the immediate value is the index of the first
4662 // element. The other shuffle indices must be the successive elements after
4664 unsigned ExpectedElt = Imm;
4665 for (unsigned i = 1; i < NumElts; ++i) {
4666 // Increment the expected index. If it wraps around, just follow it
4667 // back to index zero and keep going.
4669 if (ExpectedElt == NumElts)
4673 continue; // ignore UNDEF indices
4674 if (ExpectedElt != static_cast<unsigned>(M[i]))
4681 // check if an EXT instruction can handle the shuffle mask when the
4682 // vector sources of the shuffle are different.
4683 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4685 // Look for the first non-undef element.
4686 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4687 [](int Elt) {return Elt >= 0;});
4689 // Benefit form APInt to handle overflow when calculating expected element.
4690 unsigned NumElts = VT.getVectorNumElements();
4691 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4692 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4693 // The following shuffle indices must be the successive elements after the
4694 // first real element.
4695 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4696 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4697 if (FirstWrongElt != M.end())
4700 // The index of an EXT is the first element if it is not UNDEF.
4701 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4702 // value of the first element. E.g.
4703 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4704 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4705 // ExpectedElt is the last mask index plus 1.
4706 Imm = ExpectedElt.getZExtValue();
4708 // There are two difference cases requiring to reverse input vectors.
4709 // For example, for vector <4 x i32> we have the following cases,
4710 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4711 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4712 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4713 // to reverse two input vectors.
4722 /// isREVMask - Check if a vector shuffle corresponds to a REV
4723 /// instruction with the specified blocksize. (The order of the elements
4724 /// within each block of the vector is reversed.)
4725 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4726 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4727 "Only possible block sizes for REV are: 16, 32, 64");
4729 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4733 unsigned NumElts = VT.getVectorNumElements();
4734 unsigned BlockElts = M[0] + 1;
4735 // If the first shuffle index is UNDEF, be optimistic.
4737 BlockElts = BlockSize / EltSz;
4739 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4742 for (unsigned i = 0; i < NumElts; ++i) {
4744 continue; // ignore UNDEF indices
4745 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4752 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4753 unsigned NumElts = VT.getVectorNumElements();
4754 WhichResult = (M[0] == 0 ? 0 : 1);
4755 unsigned Idx = WhichResult * NumElts / 2;
4756 for (unsigned i = 0; i != NumElts; i += 2) {
4757 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4758 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4766 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4767 unsigned NumElts = VT.getVectorNumElements();
4768 WhichResult = (M[0] == 0 ? 0 : 1);
4769 for (unsigned i = 0; i != NumElts; ++i) {
4771 continue; // ignore UNDEF indices
4772 if ((unsigned)M[i] != 2 * i + WhichResult)
4779 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4780 unsigned NumElts = VT.getVectorNumElements();
4781 WhichResult = (M[0] == 0 ? 0 : 1);
4782 for (unsigned i = 0; i < NumElts; i += 2) {
4783 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4784 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4790 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4791 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4792 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4793 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4794 unsigned NumElts = VT.getVectorNumElements();
4795 WhichResult = (M[0] == 0 ? 0 : 1);
4796 unsigned Idx = WhichResult * NumElts / 2;
4797 for (unsigned i = 0; i != NumElts; i += 2) {
4798 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4799 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4807 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4808 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4809 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4810 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4811 unsigned Half = VT.getVectorNumElements() / 2;
4812 WhichResult = (M[0] == 0 ? 0 : 1);
4813 for (unsigned j = 0; j != 2; ++j) {
4814 unsigned Idx = WhichResult;
4815 for (unsigned i = 0; i != Half; ++i) {
4816 int MIdx = M[i + j * Half];
4817 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4826 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4827 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4828 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4829 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4830 unsigned NumElts = VT.getVectorNumElements();
4831 WhichResult = (M[0] == 0 ? 0 : 1);
4832 for (unsigned i = 0; i < NumElts; i += 2) {
4833 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4834 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4840 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4841 bool &DstIsLeft, int &Anomaly) {
4842 if (M.size() != static_cast<size_t>(NumInputElements))
4845 int NumLHSMatch = 0, NumRHSMatch = 0;
4846 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4848 for (int i = 0; i < NumInputElements; ++i) {
4858 LastLHSMismatch = i;
4860 if (M[i] == i + NumInputElements)
4863 LastRHSMismatch = i;
4866 if (NumLHSMatch == NumInputElements - 1) {
4868 Anomaly = LastLHSMismatch;
4870 } else if (NumRHSMatch == NumInputElements - 1) {
4872 Anomaly = LastRHSMismatch;
4879 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4880 if (VT.getSizeInBits() != 128)
4883 unsigned NumElts = VT.getVectorNumElements();
4885 for (int I = 0, E = NumElts / 2; I != E; I++) {
4890 int Offset = NumElts / 2;
4891 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4892 if (Mask[I] != I + SplitLHS * Offset)
4899 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4901 EVT VT = Op.getValueType();
4902 SDValue V0 = Op.getOperand(0);
4903 SDValue V1 = Op.getOperand(1);
4904 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4906 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4907 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4910 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4912 if (!isConcatMask(Mask, VT, SplitV0))
4915 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4916 VT.getVectorNumElements() / 2);
4918 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4919 DAG.getConstant(0, MVT::i64));
4921 if (V1.getValueType().getSizeInBits() == 128) {
4922 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4923 DAG.getConstant(0, MVT::i64));
4925 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4928 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4929 /// the specified operations to build the shuffle.
4930 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4931 SDValue RHS, SelectionDAG &DAG,
4933 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4934 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4935 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4938 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4947 OP_VUZPL, // VUZP, left result
4948 OP_VUZPR, // VUZP, right result
4949 OP_VZIPL, // VZIP, left result
4950 OP_VZIPR, // VZIP, right result
4951 OP_VTRNL, // VTRN, left result
4952 OP_VTRNR // VTRN, right result
4955 if (OpNum == OP_COPY) {
4956 if (LHSID == (1 * 9 + 2) * 9 + 3)
4958 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4962 SDValue OpLHS, OpRHS;
4963 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4964 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4965 EVT VT = OpLHS.getValueType();
4969 llvm_unreachable("Unknown shuffle opcode!");
4971 // VREV divides the vector in half and swaps within the half.
4972 if (VT.getVectorElementType() == MVT::i32 ||
4973 VT.getVectorElementType() == MVT::f32)
4974 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4975 // vrev <4 x i16> -> REV32
4976 if (VT.getVectorElementType() == MVT::i16 ||
4977 VT.getVectorElementType() == MVT::f16)
4978 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4979 // vrev <4 x i8> -> REV16
4980 assert(VT.getVectorElementType() == MVT::i8);
4981 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4986 EVT EltTy = VT.getVectorElementType();
4988 if (EltTy == MVT::i8)
4989 Opcode = AArch64ISD::DUPLANE8;
4990 else if (EltTy == MVT::i16)
4991 Opcode = AArch64ISD::DUPLANE16;
4992 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4993 Opcode = AArch64ISD::DUPLANE32;
4994 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4995 Opcode = AArch64ISD::DUPLANE64;
4997 llvm_unreachable("Invalid vector element type?");
4999 if (VT.getSizeInBits() == 64)
5000 OpLHS = WidenVector(OpLHS, DAG);
5001 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5002 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5007 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5008 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5009 DAG.getConstant(Imm, MVT::i32));
5012 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5015 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5018 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5021 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5024 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5027 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5032 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5033 SelectionDAG &DAG) {
5034 // Check to see if we can use the TBL instruction.
5035 SDValue V1 = Op.getOperand(0);
5036 SDValue V2 = Op.getOperand(1);
5039 EVT EltVT = Op.getValueType().getVectorElementType();
5040 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5042 SmallVector<SDValue, 8> TBLMask;
5043 for (int Val : ShuffleMask) {
5044 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5045 unsigned Offset = Byte + Val * BytesPerElt;
5046 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5050 MVT IndexVT = MVT::v8i8;
5051 unsigned IndexLen = 8;
5052 if (Op.getValueType().getSizeInBits() == 128) {
5053 IndexVT = MVT::v16i8;
5057 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5058 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5061 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5063 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5064 Shuffle = DAG.getNode(
5065 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5066 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5067 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5068 makeArrayRef(TBLMask.data(), IndexLen)));
5070 if (IndexLen == 8) {
5071 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5072 Shuffle = DAG.getNode(
5073 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5074 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5075 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5076 makeArrayRef(TBLMask.data(), IndexLen)));
5078 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5079 // cannot currently represent the register constraints on the input
5081 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5082 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5083 // &TBLMask[0], IndexLen));
5084 Shuffle = DAG.getNode(
5085 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5086 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5087 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5088 makeArrayRef(TBLMask.data(), IndexLen)));
5091 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5094 static unsigned getDUPLANEOp(EVT EltType) {
5095 if (EltType == MVT::i8)
5096 return AArch64ISD::DUPLANE8;
5097 if (EltType == MVT::i16 || EltType == MVT::f16)
5098 return AArch64ISD::DUPLANE16;
5099 if (EltType == MVT::i32 || EltType == MVT::f32)
5100 return AArch64ISD::DUPLANE32;
5101 if (EltType == MVT::i64 || EltType == MVT::f64)
5102 return AArch64ISD::DUPLANE64;
5104 llvm_unreachable("Invalid vector element type?");
5107 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5108 SelectionDAG &DAG) const {
5110 EVT VT = Op.getValueType();
5112 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5114 // Convert shuffles that are directly supported on NEON to target-specific
5115 // DAG nodes, instead of keeping them as shuffles and matching them again
5116 // during code selection. This is more efficient and avoids the possibility
5117 // of inconsistencies between legalization and selection.
5118 ArrayRef<int> ShuffleMask = SVN->getMask();
5120 SDValue V1 = Op.getOperand(0);
5121 SDValue V2 = Op.getOperand(1);
5123 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5124 V1.getValueType().getSimpleVT())) {
5125 int Lane = SVN->getSplatIndex();
5126 // If this is undef splat, generate it via "just" vdup, if possible.
5130 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5131 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5133 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5134 // constant. If so, we can just reference the lane's definition directly.
5135 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5136 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5137 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5139 // Otherwise, duplicate from the lane of the input vector.
5140 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5142 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5143 // to make a vector of the same size as this SHUFFLE. We can ignore the
5144 // extract entirely, and canonicalise the concat using WidenVector.
5145 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5146 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5147 V1 = V1.getOperand(0);
5148 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5149 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5150 Lane -= Idx * VT.getVectorNumElements() / 2;
5151 V1 = WidenVector(V1.getOperand(Idx), DAG);
5152 } else if (VT.getSizeInBits() == 64)
5153 V1 = WidenVector(V1, DAG);
5155 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5158 if (isREVMask(ShuffleMask, VT, 64))
5159 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5160 if (isREVMask(ShuffleMask, VT, 32))
5161 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5162 if (isREVMask(ShuffleMask, VT, 16))
5163 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5165 bool ReverseEXT = false;
5167 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5170 Imm *= getExtFactor(V1);
5171 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5172 DAG.getConstant(Imm, MVT::i32));
5173 } else if (V2->getOpcode() == ISD::UNDEF &&
5174 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5175 Imm *= getExtFactor(V1);
5176 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5177 DAG.getConstant(Imm, MVT::i32));
5180 unsigned WhichResult;
5181 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5182 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5183 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5185 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5186 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5187 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5189 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5190 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5191 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5194 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5195 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5196 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5198 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5199 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5200 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5202 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5203 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5204 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5207 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5208 if (Concat.getNode())
5213 int NumInputElements = V1.getValueType().getVectorNumElements();
5214 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5215 SDValue DstVec = DstIsLeft ? V1 : V2;
5216 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5218 SDValue SrcVec = V1;
5219 int SrcLane = ShuffleMask[Anomaly];
5220 if (SrcLane >= NumInputElements) {
5222 SrcLane -= VT.getVectorNumElements();
5224 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5226 EVT ScalarVT = VT.getVectorElementType();
5228 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5229 ScalarVT = MVT::i32;
5232 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5233 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5237 // If the shuffle is not directly supported and it has 4 elements, use
5238 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5239 unsigned NumElts = VT.getVectorNumElements();
5241 unsigned PFIndexes[4];
5242 for (unsigned i = 0; i != 4; ++i) {
5243 if (ShuffleMask[i] < 0)
5246 PFIndexes[i] = ShuffleMask[i];
5249 // Compute the index in the perfect shuffle table.
5250 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5251 PFIndexes[2] * 9 + PFIndexes[3];
5252 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5253 unsigned Cost = (PFEntry >> 30);
5256 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5259 return GenerateTBL(Op, ShuffleMask, DAG);
5262 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5264 EVT VT = BVN->getValueType(0);
5265 APInt SplatBits, SplatUndef;
5266 unsigned SplatBitSize;
5268 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5269 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5271 for (unsigned i = 0; i < NumSplats; ++i) {
5272 CnstBits <<= SplatBitSize;
5273 UndefBits <<= SplatBitSize;
5274 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5275 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5284 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5285 SelectionDAG &DAG) const {
5286 BuildVectorSDNode *BVN =
5287 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5288 SDValue LHS = Op.getOperand(0);
5290 EVT VT = Op.getValueType();
5295 APInt CnstBits(VT.getSizeInBits(), 0);
5296 APInt UndefBits(VT.getSizeInBits(), 0);
5297 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5298 // We only have BIC vector immediate instruction, which is and-not.
5299 CnstBits = ~CnstBits;
5301 // We make use of a little bit of goto ickiness in order to avoid having to
5302 // duplicate the immediate matching logic for the undef toggled case.
5303 bool SecondTry = false;
5306 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5307 CnstBits = CnstBits.zextOrTrunc(64);
5308 uint64_t CnstVal = CnstBits.getZExtValue();
5310 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5311 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5312 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5313 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5314 DAG.getConstant(CnstVal, MVT::i32),
5315 DAG.getConstant(0, MVT::i32));
5316 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5319 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5320 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5321 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5322 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5323 DAG.getConstant(CnstVal, MVT::i32),
5324 DAG.getConstant(8, MVT::i32));
5325 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5328 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5329 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5330 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5331 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5332 DAG.getConstant(CnstVal, MVT::i32),
5333 DAG.getConstant(16, MVT::i32));
5334 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5337 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5338 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5339 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5340 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5341 DAG.getConstant(CnstVal, MVT::i32),
5342 DAG.getConstant(24, MVT::i32));
5343 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5346 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5347 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5348 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5349 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5350 DAG.getConstant(CnstVal, MVT::i32),
5351 DAG.getConstant(0, MVT::i32));
5352 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5355 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5356 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5357 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5358 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5359 DAG.getConstant(CnstVal, MVT::i32),
5360 DAG.getConstant(8, MVT::i32));
5361 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5368 CnstBits = ~UndefBits;
5372 // We can always fall back to a non-immediate AND.
5377 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5378 // consists of only the same constant int value, returned in reference arg
5380 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5381 uint64_t &ConstVal) {
5382 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5385 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5388 EVT VT = Bvec->getValueType(0);
5389 unsigned NumElts = VT.getVectorNumElements();
5390 for (unsigned i = 1; i < NumElts; ++i)
5391 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5393 ConstVal = FirstElt->getZExtValue();
5397 static unsigned getIntrinsicID(const SDNode *N) {
5398 unsigned Opcode = N->getOpcode();
5401 return Intrinsic::not_intrinsic;
5402 case ISD::INTRINSIC_WO_CHAIN: {
5403 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5404 if (IID < Intrinsic::num_intrinsics)
5406 return Intrinsic::not_intrinsic;
5411 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5412 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5413 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5414 // Also, logical shift right -> sri, with the same structure.
5415 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5416 EVT VT = N->getValueType(0);
5423 // Is the first op an AND?
5424 const SDValue And = N->getOperand(0);
5425 if (And.getOpcode() != ISD::AND)
5428 // Is the second op an shl or lshr?
5429 SDValue Shift = N->getOperand(1);
5430 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5431 // or AArch64ISD::VLSHR vector, #shift
5432 unsigned ShiftOpc = Shift.getOpcode();
5433 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5435 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5437 // Is the shift amount constant?
5438 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5442 // Is the and mask vector all constant?
5444 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5447 // Is C1 == ~C2, taking into account how much one can shift elements of a
5449 uint64_t C2 = C2node->getZExtValue();
5450 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5451 if (C2 > ElemSizeInBits)
5453 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5454 if ((C1 & ElemMask) != (~C2 & ElemMask))
5457 SDValue X = And.getOperand(0);
5458 SDValue Y = Shift.getOperand(0);
5461 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5463 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5464 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5466 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5467 DEBUG(N->dump(&DAG));
5468 DEBUG(dbgs() << "into: \n");
5469 DEBUG(ResultSLI->dump(&DAG));
5475 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5476 SelectionDAG &DAG) const {
5477 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5478 if (EnableAArch64SlrGeneration) {
5479 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5484 BuildVectorSDNode *BVN =
5485 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5486 SDValue LHS = Op.getOperand(1);
5488 EVT VT = Op.getValueType();
5490 // OR commutes, so try swapping the operands.
5492 LHS = Op.getOperand(0);
5493 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5498 APInt CnstBits(VT.getSizeInBits(), 0);
5499 APInt UndefBits(VT.getSizeInBits(), 0);
5500 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5501 // We make use of a little bit of goto ickiness in order to avoid having to
5502 // duplicate the immediate matching logic for the undef toggled case.
5503 bool SecondTry = false;
5506 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5507 CnstBits = CnstBits.zextOrTrunc(64);
5508 uint64_t CnstVal = CnstBits.getZExtValue();
5510 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5511 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5512 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5513 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5514 DAG.getConstant(CnstVal, MVT::i32),
5515 DAG.getConstant(0, MVT::i32));
5516 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5519 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5520 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5521 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5522 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5523 DAG.getConstant(CnstVal, MVT::i32),
5524 DAG.getConstant(8, MVT::i32));
5525 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5528 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5529 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5530 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5531 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5532 DAG.getConstant(CnstVal, MVT::i32),
5533 DAG.getConstant(16, MVT::i32));
5534 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5537 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5538 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5539 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5540 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5541 DAG.getConstant(CnstVal, MVT::i32),
5542 DAG.getConstant(24, MVT::i32));
5543 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5546 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5547 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5548 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5549 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5550 DAG.getConstant(CnstVal, MVT::i32),
5551 DAG.getConstant(0, MVT::i32));
5552 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5555 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5556 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5557 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5558 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5559 DAG.getConstant(CnstVal, MVT::i32),
5560 DAG.getConstant(8, MVT::i32));
5561 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5568 CnstBits = UndefBits;
5572 // We can always fall back to a non-immediate OR.
5577 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5578 // be truncated to fit element width.
5579 static SDValue NormalizeBuildVector(SDValue Op,
5580 SelectionDAG &DAG) {
5581 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5583 EVT VT = Op.getValueType();
5584 EVT EltTy= VT.getVectorElementType();
5586 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5589 SmallVector<SDValue, 16> Ops;
5590 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5591 SDValue Lane = Op.getOperand(I);
5592 if (Lane.getOpcode() == ISD::Constant) {
5593 APInt LowBits(EltTy.getSizeInBits(),
5594 cast<ConstantSDNode>(Lane)->getZExtValue());
5595 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5597 Ops.push_back(Lane);
5599 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5602 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5603 SelectionDAG &DAG) const {
5605 EVT VT = Op.getValueType();
5606 Op = NormalizeBuildVector(Op, DAG);
5607 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5609 APInt CnstBits(VT.getSizeInBits(), 0);
5610 APInt UndefBits(VT.getSizeInBits(), 0);
5611 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5612 // We make use of a little bit of goto ickiness in order to avoid having to
5613 // duplicate the immediate matching logic for the undef toggled case.
5614 bool SecondTry = false;
5617 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5618 CnstBits = CnstBits.zextOrTrunc(64);
5619 uint64_t CnstVal = CnstBits.getZExtValue();
5621 // Certain magic vector constants (used to express things like NOT
5622 // and NEG) are passed through unmodified. This allows codegen patterns
5623 // for these operations to match. Special-purpose patterns will lower
5624 // these immediates to MOVIs if it proves necessary.
5625 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5628 // The many faces of MOVI...
5629 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5630 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5631 if (VT.getSizeInBits() == 128) {
5632 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5633 DAG.getConstant(CnstVal, MVT::i32));
5634 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5637 // Support the V64 version via subregister insertion.
5638 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5639 DAG.getConstant(CnstVal, MVT::i32));
5640 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5643 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5644 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5645 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5646 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5647 DAG.getConstant(CnstVal, MVT::i32),
5648 DAG.getConstant(0, MVT::i32));
5649 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5652 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5653 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5654 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5655 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5656 DAG.getConstant(CnstVal, MVT::i32),
5657 DAG.getConstant(8, MVT::i32));
5658 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5661 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5662 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5663 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5664 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5665 DAG.getConstant(CnstVal, MVT::i32),
5666 DAG.getConstant(16, MVT::i32));
5667 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5670 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5671 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5672 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5673 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5674 DAG.getConstant(CnstVal, MVT::i32),
5675 DAG.getConstant(24, MVT::i32));
5676 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5679 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5680 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5681 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5682 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5683 DAG.getConstant(CnstVal, MVT::i32),
5684 DAG.getConstant(0, MVT::i32));
5685 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5688 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5689 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5690 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5691 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5692 DAG.getConstant(CnstVal, MVT::i32),
5693 DAG.getConstant(8, MVT::i32));
5694 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5697 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5698 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5699 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5700 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5701 DAG.getConstant(CnstVal, MVT::i32),
5702 DAG.getConstant(264, MVT::i32));
5703 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5706 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5707 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5708 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5709 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5710 DAG.getConstant(CnstVal, MVT::i32),
5711 DAG.getConstant(272, MVT::i32));
5712 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5715 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5716 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5717 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5718 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5719 DAG.getConstant(CnstVal, MVT::i32));
5720 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5723 // The few faces of FMOV...
5724 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5725 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5726 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5727 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5728 DAG.getConstant(CnstVal, MVT::i32));
5729 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5732 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5733 VT.getSizeInBits() == 128) {
5734 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5735 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5736 DAG.getConstant(CnstVal, MVT::i32));
5737 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5740 // The many faces of MVNI...
5742 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5743 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5744 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5745 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5746 DAG.getConstant(CnstVal, MVT::i32),
5747 DAG.getConstant(0, MVT::i32));
5748 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5751 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5752 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5753 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5754 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5755 DAG.getConstant(CnstVal, MVT::i32),
5756 DAG.getConstant(8, MVT::i32));
5757 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5760 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5761 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5762 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5763 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5764 DAG.getConstant(CnstVal, MVT::i32),
5765 DAG.getConstant(16, MVT::i32));
5766 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5769 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5770 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5771 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5772 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5773 DAG.getConstant(CnstVal, MVT::i32),
5774 DAG.getConstant(24, MVT::i32));
5775 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5778 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5779 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5780 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5781 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5782 DAG.getConstant(CnstVal, MVT::i32),
5783 DAG.getConstant(0, MVT::i32));
5784 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5787 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5788 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5789 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5790 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5791 DAG.getConstant(CnstVal, MVT::i32),
5792 DAG.getConstant(8, MVT::i32));
5793 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5796 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5797 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5798 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5799 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5800 DAG.getConstant(CnstVal, MVT::i32),
5801 DAG.getConstant(264, MVT::i32));
5802 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5805 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5806 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5807 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5808 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5809 DAG.getConstant(CnstVal, MVT::i32),
5810 DAG.getConstant(272, MVT::i32));
5811 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5818 CnstBits = UndefBits;
5823 // Scan through the operands to find some interesting properties we can
5825 // 1) If only one value is used, we can use a DUP, or
5826 // 2) if only the low element is not undef, we can just insert that, or
5827 // 3) if only one constant value is used (w/ some non-constant lanes),
5828 // we can splat the constant value into the whole vector then fill
5829 // in the non-constant lanes.
5830 // 4) FIXME: If different constant values are used, but we can intelligently
5831 // select the values we'll be overwriting for the non-constant
5832 // lanes such that we can directly materialize the vector
5833 // some other way (MOVI, e.g.), we can be sneaky.
5834 unsigned NumElts = VT.getVectorNumElements();
5835 bool isOnlyLowElement = true;
5836 bool usesOnlyOneValue = true;
5837 bool usesOnlyOneConstantValue = true;
5838 bool isConstant = true;
5839 unsigned NumConstantLanes = 0;
5841 SDValue ConstantValue;
5842 for (unsigned i = 0; i < NumElts; ++i) {
5843 SDValue V = Op.getOperand(i);
5844 if (V.getOpcode() == ISD::UNDEF)
5847 isOnlyLowElement = false;
5848 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5851 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5853 if (!ConstantValue.getNode())
5855 else if (ConstantValue != V)
5856 usesOnlyOneConstantValue = false;
5859 if (!Value.getNode())
5861 else if (V != Value)
5862 usesOnlyOneValue = false;
5865 if (!Value.getNode())
5866 return DAG.getUNDEF(VT);
5868 if (isOnlyLowElement)
5869 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5871 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5872 // i32 and try again.
5873 if (usesOnlyOneValue) {
5875 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5876 Value.getValueType() != VT)
5877 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5879 // This is actually a DUPLANExx operation, which keeps everything vectory.
5881 // DUPLANE works on 128-bit vectors, widen it if necessary.
5882 SDValue Lane = Value.getOperand(1);
5883 Value = Value.getOperand(0);
5884 if (Value.getValueType().getSizeInBits() == 64)
5885 Value = WidenVector(Value, DAG);
5887 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5888 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5891 if (VT.getVectorElementType().isFloatingPoint()) {
5892 SmallVector<SDValue, 8> Ops;
5894 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5895 for (unsigned i = 0; i < NumElts; ++i)
5896 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5897 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5898 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5899 Val = LowerBUILD_VECTOR(Val, DAG);
5901 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5905 // If there was only one constant value used and for more than one lane,
5906 // start by splatting that value, then replace the non-constant lanes. This
5907 // is better than the default, which will perform a separate initialization
5909 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5910 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5911 // Now insert the non-constant lanes.
5912 for (unsigned i = 0; i < NumElts; ++i) {
5913 SDValue V = Op.getOperand(i);
5914 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5915 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5916 // Note that type legalization likely mucked about with the VT of the
5917 // source operand, so we may have to convert it here before inserting.
5918 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5924 // If all elements are constants and the case above didn't get hit, fall back
5925 // to the default expansion, which will generate a load from the constant
5930 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5932 SDValue shuffle = ReconstructShuffle(Op, DAG);
5933 if (shuffle != SDValue())
5937 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5938 // know the default expansion would otherwise fall back on something even
5939 // worse. For a vector with one or two non-undef values, that's
5940 // scalar_to_vector for the elements followed by a shuffle (provided the
5941 // shuffle is valid for the target) and materialization element by element
5942 // on the stack followed by a load for everything else.
5943 if (!isConstant && !usesOnlyOneValue) {
5944 SDValue Vec = DAG.getUNDEF(VT);
5945 SDValue Op0 = Op.getOperand(0);
5946 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5948 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5949 // a) Avoid a RMW dependency on the full vector register, and
5950 // b) Allow the register coalescer to fold away the copy if the
5951 // value is already in an S or D register.
5952 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5953 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5955 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5956 DAG.getTargetConstant(SubIdx, MVT::i32));
5957 Vec = SDValue(N, 0);
5960 for (; i < NumElts; ++i) {
5961 SDValue V = Op.getOperand(i);
5962 if (V.getOpcode() == ISD::UNDEF)
5964 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5965 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5970 // Just use the default expansion. We failed to find a better alternative.
5974 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5975 SelectionDAG &DAG) const {
5976 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5978 // Check for non-constant or out of range lane.
5979 EVT VT = Op.getOperand(0).getValueType();
5980 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5981 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5985 // Insertion/extraction are legal for V128 types.
5986 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5987 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
5991 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5992 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
5995 // For V64 types, we perform insertion by expanding the value
5996 // to a V128 type and perform the insertion on that.
5998 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5999 EVT WideTy = WideVec.getValueType();
6001 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6002 Op.getOperand(1), Op.getOperand(2));
6003 // Re-narrow the resultant vector.
6004 return NarrowVector(Node, DAG);
6008 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6009 SelectionDAG &DAG) const {
6010 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6012 // Check for non-constant or out of range lane.
6013 EVT VT = Op.getOperand(0).getValueType();
6014 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6015 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6019 // Insertion/extraction are legal for V128 types.
6020 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6021 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6025 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6026 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6029 // For V64 types, we perform extraction by expanding the value
6030 // to a V128 type and perform the extraction on that.
6032 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6033 EVT WideTy = WideVec.getValueType();
6035 EVT ExtrTy = WideTy.getVectorElementType();
6036 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6039 // For extractions, we just return the result directly.
6040 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6044 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6045 SelectionDAG &DAG) const {
6046 EVT VT = Op.getOperand(0).getValueType();
6052 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6055 unsigned Val = Cst->getZExtValue();
6057 unsigned Size = Op.getValueType().getSizeInBits();
6061 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6064 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6067 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6070 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6073 llvm_unreachable("Unexpected vector type in extract_subvector!");
6076 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6078 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6084 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6086 if (VT.getVectorNumElements() == 4 &&
6087 (VT.is128BitVector() || VT.is64BitVector())) {
6088 unsigned PFIndexes[4];
6089 for (unsigned i = 0; i != 4; ++i) {
6093 PFIndexes[i] = M[i];
6096 // Compute the index in the perfect shuffle table.
6097 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6098 PFIndexes[2] * 9 + PFIndexes[3];
6099 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6100 unsigned Cost = (PFEntry >> 30);
6108 unsigned DummyUnsigned;
6110 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6111 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6112 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6113 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6114 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6115 isZIPMask(M, VT, DummyUnsigned) ||
6116 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6117 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6118 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6119 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6120 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6123 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6124 /// operand of a vector shift operation, where all the elements of the
6125 /// build_vector must have the same constant integer value.
6126 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6127 // Ignore bit_converts.
6128 while (Op.getOpcode() == ISD::BITCAST)
6129 Op = Op.getOperand(0);
6130 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6131 APInt SplatBits, SplatUndef;
6132 unsigned SplatBitSize;
6134 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6135 HasAnyUndefs, ElementBits) ||
6136 SplatBitSize > ElementBits)
6138 Cnt = SplatBits.getSExtValue();
6142 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6143 /// operand of a vector shift left operation. That value must be in the range:
6144 /// 0 <= Value < ElementBits for a left shift; or
6145 /// 0 <= Value <= ElementBits for a long left shift.
6146 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6147 assert(VT.isVector() && "vector shift count is not a vector type");
6148 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6149 if (!getVShiftImm(Op, ElementBits, Cnt))
6151 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6154 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6155 /// operand of a vector shift right operation. For a shift opcode, the value
6156 /// is positive, but for an intrinsic the value count must be negative. The
6157 /// absolute value must be in the range:
6158 /// 1 <= |Value| <= ElementBits for a right shift; or
6159 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6160 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6162 assert(VT.isVector() && "vector shift count is not a vector type");
6163 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6164 if (!getVShiftImm(Op, ElementBits, Cnt))
6168 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6171 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6172 SelectionDAG &DAG) const {
6173 EVT VT = Op.getValueType();
6177 if (!Op.getOperand(1).getValueType().isVector())
6179 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6181 switch (Op.getOpcode()) {
6183 llvm_unreachable("unexpected shift opcode");
6186 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6187 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6188 DAG.getConstant(Cnt, MVT::i32));
6189 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6190 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6191 Op.getOperand(0), Op.getOperand(1));
6194 // Right shift immediate
6195 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6198 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6199 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6200 DAG.getConstant(Cnt, MVT::i32));
6203 // Right shift register. Note, there is not a shift right register
6204 // instruction, but the shift left register instruction takes a signed
6205 // value, where negative numbers specify a right shift.
6206 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6207 : Intrinsic::aarch64_neon_ushl;
6208 // negate the shift amount
6209 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6210 SDValue NegShiftLeft =
6211 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6212 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6213 return NegShiftLeft;
6219 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6220 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6221 SDLoc dl, SelectionDAG &DAG) {
6222 EVT SrcVT = LHS.getValueType();
6223 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6224 "function only supposed to emit natural comparisons");
6226 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6227 APInt CnstBits(VT.getSizeInBits(), 0);
6228 APInt UndefBits(VT.getSizeInBits(), 0);
6229 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6230 bool IsZero = IsCnst && (CnstBits == 0);
6232 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6236 case AArch64CC::NE: {
6239 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6241 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6242 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6246 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6247 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6250 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6251 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6254 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6255 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6258 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6259 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6263 // If we ignore NaNs then we can use to the MI implementation.
6267 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6268 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6275 case AArch64CC::NE: {
6278 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6280 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6281 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6285 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6286 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6289 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6290 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6293 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6294 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6297 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6298 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6300 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6302 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6305 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6306 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6308 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6310 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6314 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6315 SelectionDAG &DAG) const {
6316 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6317 SDValue LHS = Op.getOperand(0);
6318 SDValue RHS = Op.getOperand(1);
6319 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6322 if (LHS.getValueType().getVectorElementType().isInteger()) {
6323 assert(LHS.getValueType() == RHS.getValueType());
6324 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6326 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6327 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6330 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6331 LHS.getValueType().getVectorElementType() == MVT::f64);
6333 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6334 // clean. Some of them require two branches to implement.
6335 AArch64CC::CondCode CC1, CC2;
6337 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6339 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6341 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6345 if (CC2 != AArch64CC::AL) {
6347 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6348 if (!Cmp2.getNode())
6351 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6354 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6357 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6362 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6363 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6364 /// specified in the intrinsic calls.
6365 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6367 unsigned Intrinsic) const {
6368 switch (Intrinsic) {
6369 case Intrinsic::aarch64_neon_ld2:
6370 case Intrinsic::aarch64_neon_ld3:
6371 case Intrinsic::aarch64_neon_ld4:
6372 case Intrinsic::aarch64_neon_ld1x2:
6373 case Intrinsic::aarch64_neon_ld1x3:
6374 case Intrinsic::aarch64_neon_ld1x4:
6375 case Intrinsic::aarch64_neon_ld2lane:
6376 case Intrinsic::aarch64_neon_ld3lane:
6377 case Intrinsic::aarch64_neon_ld4lane:
6378 case Intrinsic::aarch64_neon_ld2r:
6379 case Intrinsic::aarch64_neon_ld3r:
6380 case Intrinsic::aarch64_neon_ld4r: {
6381 Info.opc = ISD::INTRINSIC_W_CHAIN;
6382 // Conservatively set memVT to the entire set of vectors loaded.
6383 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6384 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6385 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6388 Info.vol = false; // volatile loads with NEON intrinsics not supported
6389 Info.readMem = true;
6390 Info.writeMem = false;
6393 case Intrinsic::aarch64_neon_st2:
6394 case Intrinsic::aarch64_neon_st3:
6395 case Intrinsic::aarch64_neon_st4:
6396 case Intrinsic::aarch64_neon_st1x2:
6397 case Intrinsic::aarch64_neon_st1x3:
6398 case Intrinsic::aarch64_neon_st1x4:
6399 case Intrinsic::aarch64_neon_st2lane:
6400 case Intrinsic::aarch64_neon_st3lane:
6401 case Intrinsic::aarch64_neon_st4lane: {
6402 Info.opc = ISD::INTRINSIC_VOID;
6403 // Conservatively set memVT to the entire set of vectors stored.
6404 unsigned NumElts = 0;
6405 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6406 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6407 if (!ArgTy->isVectorTy())
6409 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6411 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6412 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6415 Info.vol = false; // volatile stores with NEON intrinsics not supported
6416 Info.readMem = false;
6417 Info.writeMem = true;
6420 case Intrinsic::aarch64_ldaxr:
6421 case Intrinsic::aarch64_ldxr: {
6422 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6423 Info.opc = ISD::INTRINSIC_W_CHAIN;
6424 Info.memVT = MVT::getVT(PtrTy->getElementType());
6425 Info.ptrVal = I.getArgOperand(0);
6427 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6429 Info.readMem = true;
6430 Info.writeMem = false;
6433 case Intrinsic::aarch64_stlxr:
6434 case Intrinsic::aarch64_stxr: {
6435 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6436 Info.opc = ISD::INTRINSIC_W_CHAIN;
6437 Info.memVT = MVT::getVT(PtrTy->getElementType());
6438 Info.ptrVal = I.getArgOperand(1);
6440 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6442 Info.readMem = false;
6443 Info.writeMem = true;
6446 case Intrinsic::aarch64_ldaxp:
6447 case Intrinsic::aarch64_ldxp: {
6448 Info.opc = ISD::INTRINSIC_W_CHAIN;
6449 Info.memVT = MVT::i128;
6450 Info.ptrVal = I.getArgOperand(0);
6454 Info.readMem = true;
6455 Info.writeMem = false;
6458 case Intrinsic::aarch64_stlxp:
6459 case Intrinsic::aarch64_stxp: {
6460 Info.opc = ISD::INTRINSIC_W_CHAIN;
6461 Info.memVT = MVT::i128;
6462 Info.ptrVal = I.getArgOperand(2);
6466 Info.readMem = false;
6467 Info.writeMem = true;
6477 // Truncations from 64-bit GPR to 32-bit GPR is free.
6478 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6479 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6481 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6482 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6483 return NumBits1 > NumBits2;
6485 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6486 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6488 unsigned NumBits1 = VT1.getSizeInBits();
6489 unsigned NumBits2 = VT2.getSizeInBits();
6490 return NumBits1 > NumBits2;
6493 /// Check if it is profitable to hoist instruction in then/else to if.
6494 /// Not profitable if I and it's user can form a FMA instruction
6495 /// because we prefer FMSUB/FMADD.
6496 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6497 if (I->getOpcode() != Instruction::FMul)
6500 if (I->getNumUses() != 1)
6503 Instruction *User = I->user_back();
6506 !(User->getOpcode() == Instruction::FSub ||
6507 User->getOpcode() == Instruction::FAdd))
6510 const TargetOptions &Options = getTargetMachine().Options;
6511 EVT VT = getValueType(User->getOperand(0)->getType());
6513 if (isFMAFasterThanFMulAndFAdd(VT) &&
6514 isOperationLegalOrCustom(ISD::FMA, VT) &&
6515 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6521 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6523 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6524 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6526 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6527 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6528 return NumBits1 == 32 && NumBits2 == 64;
6530 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6531 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6533 unsigned NumBits1 = VT1.getSizeInBits();
6534 unsigned NumBits2 = VT2.getSizeInBits();
6535 return NumBits1 == 32 && NumBits2 == 64;
6538 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6539 EVT VT1 = Val.getValueType();
6540 if (isZExtFree(VT1, VT2)) {
6544 if (Val.getOpcode() != ISD::LOAD)
6547 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6548 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6549 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6550 VT1.getSizeInBits() <= 32);
6553 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6554 unsigned &RequiredAligment) const {
6555 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6557 // Cyclone supports unaligned accesses.
6558 RequiredAligment = 0;
6559 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6560 return NumBits == 32 || NumBits == 64;
6563 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6564 unsigned &RequiredAligment) const {
6565 if (!LoadedType.isSimple() ||
6566 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6568 // Cyclone supports unaligned accesses.
6569 RequiredAligment = 0;
6570 unsigned NumBits = LoadedType.getSizeInBits();
6571 return NumBits == 32 || NumBits == 64;
6574 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6575 unsigned AlignCheck) {
6576 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6577 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6580 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6581 unsigned SrcAlign, bool IsMemset,
6584 MachineFunction &MF) const {
6585 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6586 // instruction to materialize the v2i64 zero and one store (with restrictive
6587 // addressing mode). Just do two i64 store of zero-registers.
6589 const Function *F = MF.getFunction();
6590 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6591 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6592 (memOpAlign(SrcAlign, DstAlign, 16) ||
6593 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6596 return Size >= 8 ? MVT::i64 : MVT::i32;
6599 // 12-bit optionally shifted immediates are legal for adds.
6600 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6601 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6606 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6607 // immediates is the same as for an add or a sub.
6608 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6611 return isLegalAddImmediate(Immed);
6614 /// isLegalAddressingMode - Return true if the addressing mode represented
6615 /// by AM is legal for this target, for a load/store of the specified type.
6616 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6618 // AArch64 has five basic addressing modes:
6620 // reg + 9-bit signed offset
6621 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6623 // reg + SIZE_IN_BYTES * reg
6625 // No global is ever allowed as a base.
6629 // No reg+reg+imm addressing.
6630 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6633 // check reg + imm case:
6634 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6635 uint64_t NumBytes = 0;
6636 if (Ty->isSized()) {
6637 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6638 NumBytes = NumBits / 8;
6639 if (!isPowerOf2_64(NumBits))
6644 int64_t Offset = AM.BaseOffs;
6646 // 9-bit signed offset
6647 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6650 // 12-bit unsigned offset
6651 unsigned shift = Log2_64(NumBytes);
6652 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6653 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6654 (Offset >> shift) << shift == Offset)
6659 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6661 if (!AM.Scale || AM.Scale == 1 ||
6662 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6667 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6669 // Scaling factors are not free at all.
6670 // Operands | Rt Latency
6671 // -------------------------------------------
6673 // -------------------------------------------
6674 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6675 // Rt, [Xn, Wm, <extend> #imm] |
6676 if (isLegalAddressingMode(AM, Ty))
6677 // Scale represents reg2 * scale, thus account for 1 if
6678 // it is not equal to 0 or 1.
6679 return AM.Scale != 0 && AM.Scale != 1;
6683 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6684 VT = VT.getScalarType();
6689 switch (VT.getSimpleVT().SimpleTy) {
6701 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6702 // LR is a callee-save register, but we must treat it as clobbered by any call
6703 // site. Hence we include LR in the scratch registers, which are in turn added
6704 // as implicit-defs for stackmaps and patchpoints.
6705 static const MCPhysReg ScratchRegs[] = {
6706 AArch64::X16, AArch64::X17, AArch64::LR, 0
6712 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6713 EVT VT = N->getValueType(0);
6714 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6715 // it with shift to let it be lowered to UBFX.
6716 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6717 isa<ConstantSDNode>(N->getOperand(1))) {
6718 uint64_t TruncMask = N->getConstantOperandVal(1);
6719 if (isMask_64(TruncMask) &&
6720 N->getOperand(0).getOpcode() == ISD::SRL &&
6721 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6727 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6729 assert(Ty->isIntegerTy());
6731 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6735 int64_t Val = Imm.getSExtValue();
6736 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6739 if ((int64_t)Val < 0)
6742 Val &= (1LL << 32) - 1;
6744 unsigned LZ = countLeadingZeros((uint64_t)Val);
6745 unsigned Shift = (63 - LZ) / 16;
6746 // MOVZ is free so return true for one or fewer MOVK.
6747 return (Shift < 3) ? true : false;
6750 // Generate SUBS and CSEL for integer abs.
6751 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6752 EVT VT = N->getValueType(0);
6754 SDValue N0 = N->getOperand(0);
6755 SDValue N1 = N->getOperand(1);
6758 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6759 // and change it to SUB and CSEL.
6760 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6761 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6762 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6763 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6764 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6765 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6767 // Generate SUBS & CSEL.
6769 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6770 N0.getOperand(0), DAG.getConstant(0, VT));
6771 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6772 DAG.getConstant(AArch64CC::PL, MVT::i32),
6773 SDValue(Cmp.getNode(), 1));
6778 // performXorCombine - Attempts to handle integer ABS.
6779 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6780 TargetLowering::DAGCombinerInfo &DCI,
6781 const AArch64Subtarget *Subtarget) {
6782 if (DCI.isBeforeLegalizeOps())
6785 return performIntegerAbsCombine(N, DAG);
6789 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6791 std::vector<SDNode *> *Created) const {
6792 // fold (sdiv X, pow2)
6793 EVT VT = N->getValueType(0);
6794 if ((VT != MVT::i32 && VT != MVT::i64) ||
6795 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6799 SDValue N0 = N->getOperand(0);
6800 unsigned Lg2 = Divisor.countTrailingZeros();
6801 SDValue Zero = DAG.getConstant(0, VT);
6802 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6804 // Add (N0 < 0) ? Pow2 - 1 : 0;
6806 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6807 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6808 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6811 Created->push_back(Cmp.getNode());
6812 Created->push_back(Add.getNode());
6813 Created->push_back(CSel.getNode());
6818 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6820 // If we're dividing by a positive value, we're done. Otherwise, we must
6821 // negate the result.
6822 if (Divisor.isNonNegative())
6826 Created->push_back(SRA.getNode());
6827 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6830 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6831 TargetLowering::DAGCombinerInfo &DCI,
6832 const AArch64Subtarget *Subtarget) {
6833 if (DCI.isBeforeLegalizeOps())
6836 // Multiplication of a power of two plus/minus one can be done more
6837 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6838 // future CPUs have a cheaper MADD instruction, this may need to be
6839 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6840 // 64-bit is 5 cycles, so this is always a win.
6841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6842 APInt Value = C->getAPIntValue();
6843 EVT VT = N->getValueType(0);
6844 if (Value.isNonNegative()) {
6845 // (mul x, 2^N + 1) => (add (shl x, N), x)
6846 APInt VM1 = Value - 1;
6847 if (VM1.isPowerOf2()) {
6848 SDValue ShiftedVal =
6849 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6850 DAG.getConstant(VM1.logBase2(), MVT::i64));
6851 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6854 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6855 APInt VP1 = Value + 1;
6856 if (VP1.isPowerOf2()) {
6857 SDValue ShiftedVal =
6858 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6859 DAG.getConstant(VP1.logBase2(), MVT::i64));
6860 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6864 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6865 APInt VNP1 = -Value + 1;
6866 if (VNP1.isPowerOf2()) {
6867 SDValue ShiftedVal =
6868 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6869 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6870 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6873 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6874 APInt VNM1 = -Value - 1;
6875 if (VNM1.isPowerOf2()) {
6876 SDValue ShiftedVal =
6877 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6878 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6880 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6881 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6888 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6889 SelectionDAG &DAG) {
6890 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6891 // optimize away operation when it's from a constant.
6893 // The general transformation is:
6894 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6895 // AND(VECTOR_CMP(x,y), constant2)
6896 // constant2 = UNARYOP(constant)
6898 // Early exit if this isn't a vector operation, the operand of the
6899 // unary operation isn't a bitwise AND, or if the sizes of the operations
6901 EVT VT = N->getValueType(0);
6902 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6903 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6904 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6907 // Now check that the other operand of the AND is a constant. We could
6908 // make the transformation for non-constant splats as well, but it's unclear
6909 // that would be a benefit as it would not eliminate any operations, just
6910 // perform one more step in scalar code before moving to the vector unit.
6911 if (BuildVectorSDNode *BV =
6912 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6913 // Bail out if the vector isn't a constant.
6914 if (!BV->isConstant())
6917 // Everything checks out. Build up the new and improved node.
6919 EVT IntVT = BV->getValueType(0);
6920 // Create a new constant of the appropriate type for the transformed
6922 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6923 // The AND node needs bitcasts to/from an integer vector type around it.
6924 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6925 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6926 N->getOperand(0)->getOperand(0), MaskConst);
6927 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6934 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
6935 const AArch64Subtarget *Subtarget) {
6936 // First try to optimize away the conversion when it's conditionally from
6937 // a constant. Vectors only.
6938 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6939 if (Res != SDValue())
6942 EVT VT = N->getValueType(0);
6943 if (VT != MVT::f32 && VT != MVT::f64)
6946 // Only optimize when the source and destination types have the same width.
6947 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6950 // If the result of an integer load is only used by an integer-to-float
6951 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6952 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6953 SDValue N0 = N->getOperand(0);
6954 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6955 // Do not change the width of a volatile load.
6956 !cast<LoadSDNode>(N0)->isVolatile()) {
6957 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6958 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6959 LN0->getPointerInfo(), LN0->isVolatile(),
6960 LN0->isNonTemporal(), LN0->isInvariant(),
6961 LN0->getAlignment());
6963 // Make sure successors of the original load stay after it by updating them
6964 // to use the new Chain.
6965 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6968 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6969 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6975 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6976 /// searches for and classifies those shifts.
6977 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6979 if (N.getOpcode() == ISD::SHL)
6981 else if (N.getOpcode() == ISD::SRL)
6986 if (!isa<ConstantSDNode>(N.getOperand(1)))
6989 ShiftAmount = N->getConstantOperandVal(1);
6990 Src = N->getOperand(0);
6994 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6995 /// registers viewed as a high/low pair. This function looks for the pattern:
6996 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6997 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6999 static SDValue tryCombineToEXTR(SDNode *N,
7000 TargetLowering::DAGCombinerInfo &DCI) {
7001 SelectionDAG &DAG = DCI.DAG;
7003 EVT VT = N->getValueType(0);
7005 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7007 if (VT != MVT::i32 && VT != MVT::i64)
7011 uint32_t ShiftLHS = 0;
7013 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7017 uint32_t ShiftRHS = 0;
7019 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7022 // If they're both trying to come from the high part of the register, they're
7023 // not really an EXTR.
7024 if (LHSFromHi == RHSFromHi)
7027 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7031 std::swap(LHS, RHS);
7032 std::swap(ShiftLHS, ShiftRHS);
7035 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7036 DAG.getConstant(ShiftRHS, MVT::i64));
7039 static SDValue tryCombineToBSL(SDNode *N,
7040 TargetLowering::DAGCombinerInfo &DCI) {
7041 EVT VT = N->getValueType(0);
7042 SelectionDAG &DAG = DCI.DAG;
7048 SDValue N0 = N->getOperand(0);
7049 if (N0.getOpcode() != ISD::AND)
7052 SDValue N1 = N->getOperand(1);
7053 if (N1.getOpcode() != ISD::AND)
7056 // We only have to look for constant vectors here since the general, variable
7057 // case can be handled in TableGen.
7058 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7059 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7060 for (int i = 1; i >= 0; --i)
7061 for (int j = 1; j >= 0; --j) {
7062 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7063 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7067 bool FoundMatch = true;
7068 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7069 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7070 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7072 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7079 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7080 N0->getOperand(1 - i), N1->getOperand(1 - j));
7086 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7087 const AArch64Subtarget *Subtarget) {
7088 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7089 if (!EnableAArch64ExtrGeneration)
7091 SelectionDAG &DAG = DCI.DAG;
7092 EVT VT = N->getValueType(0);
7094 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7097 SDValue Res = tryCombineToEXTR(N, DCI);
7101 Res = tryCombineToBSL(N, DCI);
7108 static SDValue performBitcastCombine(SDNode *N,
7109 TargetLowering::DAGCombinerInfo &DCI,
7110 SelectionDAG &DAG) {
7111 // Wait 'til after everything is legalized to try this. That way we have
7112 // legal vector types and such.
7113 if (DCI.isBeforeLegalizeOps())
7116 // Remove extraneous bitcasts around an extract_subvector.
7118 // (v4i16 (bitconvert
7119 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7121 // (extract_subvector ((v8i16 ...), (i64 4)))
7123 // Only interested in 64-bit vectors as the ultimate result.
7124 EVT VT = N->getValueType(0);
7127 if (VT.getSimpleVT().getSizeInBits() != 64)
7129 // Is the operand an extract_subvector starting at the beginning or halfway
7130 // point of the vector? A low half may also come through as an
7131 // EXTRACT_SUBREG, so look for that, too.
7132 SDValue Op0 = N->getOperand(0);
7133 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7134 !(Op0->isMachineOpcode() &&
7135 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7137 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7138 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7139 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7141 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7142 if (idx != AArch64::dsub)
7144 // The dsub reference is equivalent to a lane zero subvector reference.
7147 // Look through the bitcast of the input to the extract.
7148 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7150 SDValue Source = Op0->getOperand(0)->getOperand(0);
7151 // If the source type has twice the number of elements as our destination
7152 // type, we know this is an extract of the high or low half of the vector.
7153 EVT SVT = Source->getValueType(0);
7154 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7157 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7159 // Create the simplified form to just extract the low or high half of the
7160 // vector directly rather than bothering with the bitcasts.
7162 unsigned NumElements = VT.getVectorNumElements();
7164 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7165 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7167 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7168 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7174 static SDValue performConcatVectorsCombine(SDNode *N,
7175 TargetLowering::DAGCombinerInfo &DCI,
7176 SelectionDAG &DAG) {
7177 // Wait 'til after everything is legalized to try this. That way we have
7178 // legal vector types and such.
7179 if (DCI.isBeforeLegalizeOps())
7183 EVT VT = N->getValueType(0);
7185 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7186 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7187 // canonicalise to that.
7188 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
7189 assert(VT.getVectorElementType().getSizeInBits() == 64);
7190 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
7191 WidenVector(N->getOperand(0), DAG),
7192 DAG.getConstant(0, MVT::i64));
7195 // Canonicalise concat_vectors so that the right-hand vector has as few
7196 // bit-casts as possible before its real operation. The primary matching
7197 // destination for these operations will be the narrowing "2" instructions,
7198 // which depend on the operation being performed on this right-hand vector.
7200 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7202 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7204 SDValue Op1 = N->getOperand(1);
7205 if (Op1->getOpcode() != ISD::BITCAST)
7207 SDValue RHS = Op1->getOperand(0);
7208 MVT RHSTy = RHS.getValueType().getSimpleVT();
7209 // If the RHS is not a vector, this is not the pattern we're looking for.
7210 if (!RHSTy.isVector())
7213 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7215 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7216 RHSTy.getVectorNumElements() * 2);
7218 ISD::BITCAST, dl, VT,
7219 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7220 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
7223 static SDValue tryCombineFixedPointConvert(SDNode *N,
7224 TargetLowering::DAGCombinerInfo &DCI,
7225 SelectionDAG &DAG) {
7226 // Wait 'til after everything is legalized to try this. That way we have
7227 // legal vector types and such.
7228 if (DCI.isBeforeLegalizeOps())
7230 // Transform a scalar conversion of a value from a lane extract into a
7231 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7232 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7233 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7235 // The second form interacts better with instruction selection and the
7236 // register allocator to avoid cross-class register copies that aren't
7237 // coalescable due to a lane reference.
7239 // Check the operand and see if it originates from a lane extract.
7240 SDValue Op1 = N->getOperand(1);
7241 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7242 // Yep, no additional predication needed. Perform the transform.
7243 SDValue IID = N->getOperand(0);
7244 SDValue Shift = N->getOperand(2);
7245 SDValue Vec = Op1.getOperand(0);
7246 SDValue Lane = Op1.getOperand(1);
7247 EVT ResTy = N->getValueType(0);
7251 // The vector width should be 128 bits by the time we get here, even
7252 // if it started as 64 bits (the extract_vector handling will have
7254 assert(Vec.getValueType().getSizeInBits() == 128 &&
7255 "unexpected vector size on extract_vector_elt!");
7256 if (Vec.getValueType() == MVT::v4i32)
7257 VecResTy = MVT::v4f32;
7258 else if (Vec.getValueType() == MVT::v2i64)
7259 VecResTy = MVT::v2f64;
7261 llvm_unreachable("unexpected vector type!");
7264 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7265 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7270 // AArch64 high-vector "long" operations are formed by performing the non-high
7271 // version on an extract_subvector of each operand which gets the high half:
7273 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7275 // However, there are cases which don't have an extract_high explicitly, but
7276 // have another operation that can be made compatible with one for free. For
7279 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7281 // This routine does the actual conversion of such DUPs, once outer routines
7282 // have determined that everything else is in order.
7283 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7284 // We can handle most types of duplicate, but the lane ones have an extra
7285 // operand saying *which* lane, so we need to know.
7287 switch (N.getOpcode()) {
7288 case AArch64ISD::DUP:
7291 case AArch64ISD::DUPLANE8:
7292 case AArch64ISD::DUPLANE16:
7293 case AArch64ISD::DUPLANE32:
7294 case AArch64ISD::DUPLANE64:
7301 MVT NarrowTy = N.getSimpleValueType();
7302 if (!NarrowTy.is64BitVector())
7305 MVT ElementTy = NarrowTy.getVectorElementType();
7306 unsigned NumElems = NarrowTy.getVectorNumElements();
7307 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7311 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7314 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7317 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7320 static bool isEssentiallyExtractSubvector(SDValue N) {
7321 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7324 return N.getOpcode() == ISD::BITCAST &&
7325 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7328 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7329 struct GenericSetCCInfo {
7330 const SDValue *Opnd0;
7331 const SDValue *Opnd1;
7335 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7336 struct AArch64SetCCInfo {
7338 AArch64CC::CondCode CC;
7341 /// \brief Helper structure to keep track of SetCC information.
7343 GenericSetCCInfo Generic;
7344 AArch64SetCCInfo AArch64;
7347 /// \brief Helper structure to be able to read SetCC information. If set to
7348 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7349 /// GenericSetCCInfo.
7350 struct SetCCInfoAndKind {
7355 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7357 /// AArch64 lowered one.
7358 /// \p SetCCInfo is filled accordingly.
7359 /// \post SetCCInfo is meanginfull only when this function returns true.
7360 /// \return True when Op is a kind of SET_CC operation.
7361 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7362 // If this is a setcc, this is straight forward.
7363 if (Op.getOpcode() == ISD::SETCC) {
7364 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7365 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7366 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7367 SetCCInfo.IsAArch64 = false;
7370 // Otherwise, check if this is a matching csel instruction.
7374 if (Op.getOpcode() != AArch64ISD::CSEL)
7376 // Set the information about the operands.
7377 // TODO: we want the operands of the Cmp not the csel
7378 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7379 SetCCInfo.IsAArch64 = true;
7380 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7381 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7383 // Check that the operands matches the constraints:
7384 // (1) Both operands must be constants.
7385 // (2) One must be 1 and the other must be 0.
7386 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7387 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7390 if (!TValue || !FValue)
7394 if (!TValue->isOne()) {
7395 // Update the comparison when we are interested in !cc.
7396 std::swap(TValue, FValue);
7397 SetCCInfo.Info.AArch64.CC =
7398 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7400 return TValue->isOne() && FValue->isNullValue();
7403 // Returns true if Op is setcc or zext of setcc.
7404 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7405 if (isSetCC(Op, Info))
7407 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7408 isSetCC(Op->getOperand(0), Info));
7411 // The folding we want to perform is:
7412 // (add x, [zext] (setcc cc ...) )
7414 // (csel x, (add x, 1), !cc ...)
7416 // The latter will get matched to a CSINC instruction.
7417 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7418 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7419 SDValue LHS = Op->getOperand(0);
7420 SDValue RHS = Op->getOperand(1);
7421 SetCCInfoAndKind InfoAndKind;
7423 // If neither operand is a SET_CC, give up.
7424 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7425 std::swap(LHS, RHS);
7426 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7430 // FIXME: This could be generatized to work for FP comparisons.
7431 EVT CmpVT = InfoAndKind.IsAArch64
7432 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7433 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7434 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7440 if (InfoAndKind.IsAArch64) {
7441 CCVal = DAG.getConstant(
7442 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7443 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7445 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7446 *InfoAndKind.Info.Generic.Opnd1,
7447 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7450 EVT VT = Op->getValueType(0);
7451 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7452 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7455 // The basic add/sub long vector instructions have variants with "2" on the end
7456 // which act on the high-half of their inputs. They are normally matched by
7459 // (add (zeroext (extract_high LHS)),
7460 // (zeroext (extract_high RHS)))
7461 // -> uaddl2 vD, vN, vM
7463 // However, if one of the extracts is something like a duplicate, this
7464 // instruction can still be used profitably. This function puts the DAG into a
7465 // more appropriate form for those patterns to trigger.
7466 static SDValue performAddSubLongCombine(SDNode *N,
7467 TargetLowering::DAGCombinerInfo &DCI,
7468 SelectionDAG &DAG) {
7469 if (DCI.isBeforeLegalizeOps())
7472 MVT VT = N->getSimpleValueType(0);
7473 if (!VT.is128BitVector()) {
7474 if (N->getOpcode() == ISD::ADD)
7475 return performSetccAddFolding(N, DAG);
7479 // Make sure both branches are extended in the same way.
7480 SDValue LHS = N->getOperand(0);
7481 SDValue RHS = N->getOperand(1);
7482 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7483 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7484 LHS.getOpcode() != RHS.getOpcode())
7487 unsigned ExtType = LHS.getOpcode();
7489 // It's not worth doing if at least one of the inputs isn't already an
7490 // extract, but we don't know which it'll be so we have to try both.
7491 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7492 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7496 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7497 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7498 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7502 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7505 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7508 // Massage DAGs which we can use the high-half "long" operations on into
7509 // something isel will recognize better. E.g.
7511 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7512 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7513 // (extract_high (v2i64 (dup128 scalar)))))
7515 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7516 TargetLowering::DAGCombinerInfo &DCI,
7517 SelectionDAG &DAG) {
7518 if (DCI.isBeforeLegalizeOps())
7521 SDValue LHS = N->getOperand(1);
7522 SDValue RHS = N->getOperand(2);
7523 assert(LHS.getValueType().is64BitVector() &&
7524 RHS.getValueType().is64BitVector() &&
7525 "unexpected shape for long operation");
7527 // Either node could be a DUP, but it's not worth doing both of them (you'd
7528 // just as well use the non-high version) so look for a corresponding extract
7529 // operation on the other "wing".
7530 if (isEssentiallyExtractSubvector(LHS)) {
7531 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7534 } else if (isEssentiallyExtractSubvector(RHS)) {
7535 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7540 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7541 N->getOperand(0), LHS, RHS);
7544 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7545 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7546 unsigned ElemBits = ElemTy.getSizeInBits();
7548 int64_t ShiftAmount;
7549 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7550 APInt SplatValue, SplatUndef;
7551 unsigned SplatBitSize;
7553 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7554 HasAnyUndefs, ElemBits) ||
7555 SplatBitSize != ElemBits)
7558 ShiftAmount = SplatValue.getSExtValue();
7559 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7560 ShiftAmount = CVN->getSExtValue();
7568 llvm_unreachable("Unknown shift intrinsic");
7569 case Intrinsic::aarch64_neon_sqshl:
7570 Opcode = AArch64ISD::SQSHL_I;
7571 IsRightShift = false;
7573 case Intrinsic::aarch64_neon_uqshl:
7574 Opcode = AArch64ISD::UQSHL_I;
7575 IsRightShift = false;
7577 case Intrinsic::aarch64_neon_srshl:
7578 Opcode = AArch64ISD::SRSHR_I;
7579 IsRightShift = true;
7581 case Intrinsic::aarch64_neon_urshl:
7582 Opcode = AArch64ISD::URSHR_I;
7583 IsRightShift = true;
7585 case Intrinsic::aarch64_neon_sqshlu:
7586 Opcode = AArch64ISD::SQSHLU_I;
7587 IsRightShift = false;
7591 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7592 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7593 DAG.getConstant(-ShiftAmount, MVT::i32));
7594 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7595 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7596 DAG.getConstant(ShiftAmount, MVT::i32));
7601 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7602 // the intrinsics must be legal and take an i32, this means there's almost
7603 // certainly going to be a zext in the DAG which we can eliminate.
7604 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7605 SDValue AndN = N->getOperand(2);
7606 if (AndN.getOpcode() != ISD::AND)
7609 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7610 if (!CMask || CMask->getZExtValue() != Mask)
7613 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7614 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7617 static SDValue performIntrinsicCombine(SDNode *N,
7618 TargetLowering::DAGCombinerInfo &DCI,
7619 const AArch64Subtarget *Subtarget) {
7620 SelectionDAG &DAG = DCI.DAG;
7621 unsigned IID = getIntrinsicID(N);
7625 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7626 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7627 return tryCombineFixedPointConvert(N, DCI, DAG);
7629 case Intrinsic::aarch64_neon_fmax:
7630 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7631 N->getOperand(1), N->getOperand(2));
7632 case Intrinsic::aarch64_neon_fmin:
7633 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7634 N->getOperand(1), N->getOperand(2));
7635 case Intrinsic::aarch64_neon_smull:
7636 case Intrinsic::aarch64_neon_umull:
7637 case Intrinsic::aarch64_neon_pmull:
7638 case Intrinsic::aarch64_neon_sqdmull:
7639 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7640 case Intrinsic::aarch64_neon_sqshl:
7641 case Intrinsic::aarch64_neon_uqshl:
7642 case Intrinsic::aarch64_neon_sqshlu:
7643 case Intrinsic::aarch64_neon_srshl:
7644 case Intrinsic::aarch64_neon_urshl:
7645 return tryCombineShiftImm(IID, N, DAG);
7646 case Intrinsic::aarch64_crc32b:
7647 case Intrinsic::aarch64_crc32cb:
7648 return tryCombineCRC32(0xff, N, DAG);
7649 case Intrinsic::aarch64_crc32h:
7650 case Intrinsic::aarch64_crc32ch:
7651 return tryCombineCRC32(0xffff, N, DAG);
7656 static SDValue performExtendCombine(SDNode *N,
7657 TargetLowering::DAGCombinerInfo &DCI,
7658 SelectionDAG &DAG) {
7659 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7660 // we can convert that DUP into another extract_high (of a bigger DUP), which
7661 // helps the backend to decide that an sabdl2 would be useful, saving a real
7662 // extract_high operation.
7663 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7664 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7665 SDNode *ABDNode = N->getOperand(0).getNode();
7666 unsigned IID = getIntrinsicID(ABDNode);
7667 if (IID == Intrinsic::aarch64_neon_sabd ||
7668 IID == Intrinsic::aarch64_neon_uabd) {
7669 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7670 if (!NewABD.getNode())
7673 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7678 // This is effectively a custom type legalization for AArch64.
7680 // Type legalization will split an extend of a small, legal, type to a larger
7681 // illegal type by first splitting the destination type, often creating
7682 // illegal source types, which then get legalized in isel-confusing ways,
7683 // leading to really terrible codegen. E.g.,
7684 // %result = v8i32 sext v8i8 %value
7686 // %losrc = extract_subreg %value, ...
7687 // %hisrc = extract_subreg %value, ...
7688 // %lo = v4i32 sext v4i8 %losrc
7689 // %hi = v4i32 sext v4i8 %hisrc
7690 // Things go rapidly downhill from there.
7692 // For AArch64, the [sz]ext vector instructions can only go up one element
7693 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7694 // take two instructions.
7696 // This implies that the most efficient way to do the extend from v8i8
7697 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7698 // the normal splitting to happen for the v8i16->v8i32.
7700 // This is pre-legalization to catch some cases where the default
7701 // type legalization will create ill-tempered code.
7702 if (!DCI.isBeforeLegalizeOps())
7705 // We're only interested in cleaning things up for non-legal vector types
7706 // here. If both the source and destination are legal, things will just
7707 // work naturally without any fiddling.
7708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7709 EVT ResVT = N->getValueType(0);
7710 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7712 // If the vector type isn't a simple VT, it's beyond the scope of what
7713 // we're worried about here. Let legalization do its thing and hope for
7715 SDValue Src = N->getOperand(0);
7716 EVT SrcVT = Src->getValueType(0);
7717 if (!ResVT.isSimple() || !SrcVT.isSimple())
7720 // If the source VT is a 64-bit vector, we can play games and get the
7721 // better results we want.
7722 if (SrcVT.getSizeInBits() != 64)
7725 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7726 unsigned ElementCount = SrcVT.getVectorNumElements();
7727 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7729 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7731 // Now split the rest of the operation into two halves, each with a 64
7735 unsigned NumElements = ResVT.getVectorNumElements();
7736 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7737 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7738 ResVT.getVectorElementType(), NumElements / 2);
7740 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7741 LoVT.getVectorNumElements());
7742 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7743 DAG.getConstant(0, MVT::i64));
7744 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7745 DAG.getConstant(InNVT.getVectorNumElements(), MVT::i64));
7746 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7747 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7749 // Now combine the parts back together so we still have a single result
7750 // like the combiner expects.
7751 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7754 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7755 /// value. The load store optimizer pass will merge them to store pair stores.
7756 /// This has better performance than a splat of the scalar followed by a split
7757 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7758 /// followed by an ext.b and two stores.
7759 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7760 SDValue StVal = St->getValue();
7761 EVT VT = StVal.getValueType();
7763 // Don't replace floating point stores, they possibly won't be transformed to
7764 // stp because of the store pair suppress pass.
7765 if (VT.isFloatingPoint())
7768 // Check for insert vector elements.
7769 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7772 // We can express a splat as store pair(s) for 2 or 4 elements.
7773 unsigned NumVecElts = VT.getVectorNumElements();
7774 if (NumVecElts != 4 && NumVecElts != 2)
7776 SDValue SplatVal = StVal.getOperand(1);
7777 unsigned RemainInsertElts = NumVecElts - 1;
7779 // Check that this is a splat.
7780 while (--RemainInsertElts) {
7781 SDValue NextInsertElt = StVal.getOperand(0);
7782 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7784 if (NextInsertElt.getOperand(1) != SplatVal)
7786 StVal = NextInsertElt;
7788 unsigned OrigAlignment = St->getAlignment();
7789 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7790 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7792 // Create scalar stores. This is at least as good as the code sequence for a
7793 // split unaligned store wich is a dup.s, ext.b, and two stores.
7794 // Most of the time the three stores should be replaced by store pair
7795 // instructions (stp).
7797 SDValue BasePtr = St->getBasePtr();
7799 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7800 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7802 unsigned Offset = EltOffset;
7803 while (--NumVecElts) {
7804 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7805 DAG.getConstant(Offset, MVT::i64));
7806 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7807 St->getPointerInfo(), St->isVolatile(),
7808 St->isNonTemporal(), Alignment);
7809 Offset += EltOffset;
7814 static SDValue performSTORECombine(SDNode *N,
7815 TargetLowering::DAGCombinerInfo &DCI,
7817 const AArch64Subtarget *Subtarget) {
7818 if (!DCI.isBeforeLegalize())
7821 StoreSDNode *S = cast<StoreSDNode>(N);
7822 if (S->isVolatile())
7825 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7826 // page boundaries. We want to split such stores.
7827 if (!Subtarget->isCyclone())
7830 // Don't split at Oz.
7831 MachineFunction &MF = DAG.getMachineFunction();
7832 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
7836 SDValue StVal = S->getValue();
7837 EVT VT = StVal.getValueType();
7839 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7840 // those up regresses performance on micro-benchmarks and olden/bh.
7841 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7844 // Split unaligned 16B stores. They are terrible for performance.
7845 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7846 // extensions can use this to mark that it does not want splitting to happen
7847 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7848 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7849 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7850 S->getAlignment() <= 2)
7853 // If we get a splat of a scalar convert this vector store to a store of
7854 // scalars. They will be merged into store pairs thereby removing two
7856 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7857 if (ReplacedSplat != SDValue())
7858 return ReplacedSplat;
7861 unsigned NumElts = VT.getVectorNumElements() / 2;
7862 // Split VT into two.
7864 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7865 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7866 DAG.getConstant(0, MVT::i64));
7867 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7868 DAG.getConstant(NumElts, MVT::i64));
7869 SDValue BasePtr = S->getBasePtr();
7871 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7872 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7873 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7874 DAG.getConstant(8, MVT::i64));
7875 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7876 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7880 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7881 /// post-increment LD1R.
7882 static SDValue performPostLD1Combine(SDNode *N,
7883 TargetLowering::DAGCombinerInfo &DCI,
7885 if (DCI.isBeforeLegalizeOps())
7888 SelectionDAG &DAG = DCI.DAG;
7889 EVT VT = N->getValueType(0);
7891 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7892 SDNode *LD = N->getOperand(LoadIdx).getNode();
7893 // If it is not LOAD, can not do such combine.
7894 if (LD->getOpcode() != ISD::LOAD)
7897 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7898 EVT MemVT = LoadSDN->getMemoryVT();
7899 // Check if memory operand is the same type as the vector element.
7900 if (MemVT != VT.getVectorElementType())
7903 // Check if there are other uses. If so, do not combine as it will introduce
7905 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7907 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7913 SDValue Addr = LD->getOperand(1);
7914 SDValue Vector = N->getOperand(0);
7915 // Search for a use of the address operand that is an increment.
7916 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7917 Addr.getNode()->use_end(); UI != UE; ++UI) {
7919 if (User->getOpcode() != ISD::ADD
7920 || UI.getUse().getResNo() != Addr.getResNo())
7923 // Check that the add is independent of the load. Otherwise, folding it
7924 // would create a cycle.
7925 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7927 // Also check that add is not used in the vector operand. This would also
7929 if (User->isPredecessorOf(Vector.getNode()))
7932 // If the increment is a constant, it must match the memory ref size.
7933 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7934 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7935 uint32_t IncVal = CInc->getZExtValue();
7936 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7937 if (IncVal != NumBytes)
7939 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7942 SmallVector<SDValue, 8> Ops;
7943 Ops.push_back(LD->getOperand(0)); // Chain
7945 Ops.push_back(Vector); // The vector to be inserted
7946 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7948 Ops.push_back(Addr);
7951 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7952 SDVTList SDTys = DAG.getVTList(Tys);
7953 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7954 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7956 LoadSDN->getMemOperand());
7959 SmallVector<SDValue, 2> NewResults;
7960 NewResults.push_back(SDValue(LD, 0)); // The result of load
7961 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7962 DCI.CombineTo(LD, NewResults);
7963 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7964 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7971 /// Target-specific DAG combine function for NEON load/store intrinsics
7972 /// to merge base address updates.
7973 static SDValue performNEONPostLDSTCombine(SDNode *N,
7974 TargetLowering::DAGCombinerInfo &DCI,
7975 SelectionDAG &DAG) {
7976 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7979 unsigned AddrOpIdx = N->getNumOperands() - 1;
7980 SDValue Addr = N->getOperand(AddrOpIdx);
7982 // Search for a use of the address operand that is an increment.
7983 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7984 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7986 if (User->getOpcode() != ISD::ADD ||
7987 UI.getUse().getResNo() != Addr.getResNo())
7990 // Check that the add is independent of the load/store. Otherwise, folding
7991 // it would create a cycle.
7992 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7995 // Find the new opcode for the updating load/store.
7996 bool IsStore = false;
7997 bool IsLaneOp = false;
7998 bool IsDupOp = false;
7999 unsigned NewOpc = 0;
8000 unsigned NumVecs = 0;
8001 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8003 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8004 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8006 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8008 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8010 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8011 NumVecs = 2; IsStore = true; break;
8012 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8013 NumVecs = 3; IsStore = true; break;
8014 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8015 NumVecs = 4; IsStore = true; break;
8016 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8018 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8020 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8022 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8023 NumVecs = 2; IsStore = true; break;
8024 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8025 NumVecs = 3; IsStore = true; break;
8026 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8027 NumVecs = 4; IsStore = true; break;
8028 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8029 NumVecs = 2; IsDupOp = true; break;
8030 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8031 NumVecs = 3; IsDupOp = true; break;
8032 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8033 NumVecs = 4; IsDupOp = true; break;
8034 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8035 NumVecs = 2; IsLaneOp = true; break;
8036 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8037 NumVecs = 3; IsLaneOp = true; break;
8038 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8039 NumVecs = 4; IsLaneOp = true; break;
8040 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8041 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8042 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8043 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8044 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8045 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8050 VecTy = N->getOperand(2).getValueType();
8052 VecTy = N->getValueType(0);
8054 // If the increment is a constant, it must match the memory ref size.
8055 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8056 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8057 uint32_t IncVal = CInc->getZExtValue();
8058 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8059 if (IsLaneOp || IsDupOp)
8060 NumBytes /= VecTy.getVectorNumElements();
8061 if (IncVal != NumBytes)
8063 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8065 SmallVector<SDValue, 8> Ops;
8066 Ops.push_back(N->getOperand(0)); // Incoming chain
8067 // Load lane and store have vector list as input.
8068 if (IsLaneOp || IsStore)
8069 for (unsigned i = 2; i < AddrOpIdx; ++i)
8070 Ops.push_back(N->getOperand(i));
8071 Ops.push_back(Addr); // Base register
8076 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8078 for (n = 0; n < NumResultVecs; ++n)
8080 Tys[n++] = MVT::i64; // Type of write back register
8081 Tys[n] = MVT::Other; // Type of the chain
8082 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8084 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8085 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8086 MemInt->getMemoryVT(),
8087 MemInt->getMemOperand());
8090 std::vector<SDValue> NewResults;
8091 for (unsigned i = 0; i < NumResultVecs; ++i) {
8092 NewResults.push_back(SDValue(UpdN.getNode(), i));
8094 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8095 DCI.CombineTo(N, NewResults);
8096 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8103 // Checks to see if the value is the prescribed width and returns information
8104 // about its extension mode.
8106 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8107 ExtType = ISD::NON_EXTLOAD;
8108 switch(V.getNode()->getOpcode()) {
8112 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8113 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8114 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8115 ExtType = LoadNode->getExtensionType();
8120 case ISD::AssertSext: {
8121 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8122 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8123 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8124 ExtType = ISD::SEXTLOAD;
8129 case ISD::AssertZext: {
8130 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8131 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8132 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8133 ExtType = ISD::ZEXTLOAD;
8139 case ISD::TargetConstant: {
8140 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8150 // This function does a whole lot of voodoo to determine if the tests are
8151 // equivalent without and with a mask. Essentially what happens is that given a
8154 // +-------------+ +-------------+ +-------------+ +-------------+
8155 // | Input | | AddConstant | | CompConstant| | CC |
8156 // +-------------+ +-------------+ +-------------+ +-------------+
8158 // V V | +----------+
8159 // +-------------+ +----+ | |
8160 // | ADD | |0xff| | |
8161 // +-------------+ +----+ | |
8164 // +-------------+ | |
8166 // +-------------+ | |
8175 // The AND node may be safely removed for some combinations of inputs. In
8176 // particular we need to take into account the extension type of the Input,
8177 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8178 // width of the input (this can work for any width inputs, the above graph is
8179 // specific to 8 bits.
8181 // The specific equations were worked out by generating output tables for each
8182 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8183 // problem was simplified by working with 4 bit inputs, which means we only
8184 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8185 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8186 // patterns present in both extensions (0,7). For every distinct set of
8187 // AddConstant and CompConstants bit patterns we can consider the masked and
8188 // unmasked versions to be equivalent if the result of this function is true for
8189 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8192 // and w10, w8, #0x0f
8194 // cset w9, AArch64CC
8196 // cset w11, AArch64CC
8201 // Since the above function shows when the outputs are equivalent it defines
8202 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8203 // would be expensive to run during compiles. The equations below were written
8204 // in a test harness that confirmed they gave equivalent outputs to the above
8205 // for all inputs function, so they can be used determine if the removal is
8208 // isEquivalentMaskless() is the code for testing if the AND can be removed
8209 // factored out of the DAG recognition as the DAG can take several forms.
8212 bool isEquivalentMaskless(unsigned CC, unsigned width,
8213 ISD::LoadExtType ExtType, signed AddConstant,
8214 signed CompConstant) {
8215 // By being careful about our equations and only writing the in term
8216 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8217 // make them generally applicable to all bit widths.
8218 signed MaxUInt = (1 << width);
8220 // For the purposes of these comparisons sign extending the type is
8221 // equivalent to zero extending the add and displacing it by half the integer
8222 // width. Provided we are careful and make sure our equations are valid over
8223 // the whole range we can just adjust the input and avoid writing equations
8224 // for sign extended inputs.
8225 if (ExtType == ISD::SEXTLOAD)
8226 AddConstant -= (1 << (width-1));
8230 case AArch64CC::GT: {
8231 if ((AddConstant == 0) ||
8232 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8233 (AddConstant >= 0 && CompConstant < 0) ||
8234 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8238 case AArch64CC::GE: {
8239 if ((AddConstant == 0) ||
8240 (AddConstant >= 0 && CompConstant <= 0) ||
8241 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8245 case AArch64CC::LS: {
8246 if ((AddConstant >= 0 && CompConstant < 0) ||
8247 (AddConstant <= 0 && CompConstant >= -1 &&
8248 CompConstant < AddConstant + MaxUInt))
8252 case AArch64CC::MI: {
8253 if ((AddConstant == 0) ||
8254 (AddConstant > 0 && CompConstant <= 0) ||
8255 (AddConstant < 0 && CompConstant <= AddConstant))
8259 case AArch64CC::HS: {
8260 if ((AddConstant >= 0 && CompConstant <= 0) ||
8261 (AddConstant <= 0 && CompConstant >= 0 &&
8262 CompConstant <= AddConstant + MaxUInt))
8266 case AArch64CC::NE: {
8267 if ((AddConstant > 0 && CompConstant < 0) ||
8268 (AddConstant < 0 && CompConstant >= 0 &&
8269 CompConstant < AddConstant + MaxUInt) ||
8270 (AddConstant >= 0 && CompConstant >= 0 &&
8271 CompConstant >= AddConstant) ||
8272 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8281 case AArch64CC::Invalid:
8289 SDValue performCONDCombine(SDNode *N,
8290 TargetLowering::DAGCombinerInfo &DCI,
8291 SelectionDAG &DAG, unsigned CCIndex,
8292 unsigned CmpIndex) {
8293 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8294 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8295 unsigned CondOpcode = SubsNode->getOpcode();
8297 if (CondOpcode != AArch64ISD::SUBS)
8300 // There is a SUBS feeding this condition. Is it fed by a mask we can
8303 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8304 unsigned MaskBits = 0;
8306 if (AndNode->getOpcode() != ISD::AND)
8309 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8310 uint32_t CNV = CN->getZExtValue();
8313 else if (CNV == 65535)
8320 SDValue AddValue = AndNode->getOperand(0);
8322 if (AddValue.getOpcode() != ISD::ADD)
8325 // The basic dag structure is correct, grab the inputs and validate them.
8327 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8328 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8329 SDValue SubsInputValue = SubsNode->getOperand(1);
8331 // The mask is present and the provenance of all the values is a smaller type,
8332 // lets see if the mask is superfluous.
8334 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8335 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8338 ISD::LoadExtType ExtType;
8340 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8341 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8342 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8345 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8346 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8347 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8350 // The AND is not necessary, remove it.
8352 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8353 SubsNode->getValueType(1));
8354 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8356 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8357 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8359 return SDValue(N, 0);
8362 // Optimize compare with zero and branch.
8363 static SDValue performBRCONDCombine(SDNode *N,
8364 TargetLowering::DAGCombinerInfo &DCI,
8365 SelectionDAG &DAG) {
8366 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8369 SDValue Chain = N->getOperand(0);
8370 SDValue Dest = N->getOperand(1);
8371 SDValue CCVal = N->getOperand(2);
8372 SDValue Cmp = N->getOperand(3);
8374 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8375 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8376 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8379 unsigned CmpOpc = Cmp.getOpcode();
8380 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8383 // Only attempt folding if there is only one use of the flag and no use of the
8385 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8388 SDValue LHS = Cmp.getOperand(0);
8389 SDValue RHS = Cmp.getOperand(1);
8391 assert(LHS.getValueType() == RHS.getValueType() &&
8392 "Expected the value type to be the same for both operands!");
8393 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8396 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8397 std::swap(LHS, RHS);
8399 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8402 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8403 LHS.getOpcode() == ISD::SRL)
8406 // Fold the compare into the branch instruction.
8408 if (CC == AArch64CC::EQ)
8409 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8411 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8413 // Do not add new nodes to DAG combiner worklist.
8414 DCI.CombineTo(N, BR, false);
8419 // vselect (v1i1 setcc) ->
8420 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8421 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8422 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8424 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8425 SDValue N0 = N->getOperand(0);
8426 EVT CCVT = N0.getValueType();
8428 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8429 CCVT.getVectorElementType() != MVT::i1)
8432 EVT ResVT = N->getValueType(0);
8433 EVT CmpVT = N0.getOperand(0).getValueType();
8434 // Only combine when the result type is of the same size as the compared
8436 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8439 SDValue IfTrue = N->getOperand(1);
8440 SDValue IfFalse = N->getOperand(2);
8442 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8443 N0.getOperand(0), N0.getOperand(1),
8444 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8445 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8449 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8450 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8451 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8452 /// with a vector one followed by a DUP shuffle on the result.
8453 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8454 SDValue N0 = N->getOperand(0);
8455 EVT ResVT = N->getValueType(0);
8457 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8460 // If NumMaskElts == 0, the comparison is larger than select result. The
8461 // largest real NEON comparison is 64-bits per lane, which means the result is
8462 // at most 32-bits and an illegal vector. Just bail out for now.
8463 EVT SrcVT = N0.getOperand(0).getValueType();
8465 // Don't try to do this optimization when the setcc itself has i1 operands.
8466 // There are no legal vectors of i1, so this would be pointless.
8467 if (SrcVT == MVT::i1)
8470 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8471 if (!ResVT.isVector() || NumMaskElts == 0)
8474 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8475 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8477 // First perform a vector comparison, where lane 0 is the one we're interested
8481 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8483 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8484 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8486 // Now duplicate the comparison mask we want across all other lanes.
8487 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8488 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8489 Mask = DAG.getNode(ISD::BITCAST, DL,
8490 ResVT.changeVectorElementTypeToInteger(), Mask);
8492 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8495 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8496 DAGCombinerInfo &DCI) const {
8497 SelectionDAG &DAG = DCI.DAG;
8498 switch (N->getOpcode()) {
8503 return performAddSubLongCombine(N, DCI, DAG);
8505 return performXorCombine(N, DAG, DCI, Subtarget);
8507 return performMulCombine(N, DAG, DCI, Subtarget);
8508 case ISD::SINT_TO_FP:
8509 case ISD::UINT_TO_FP:
8510 return performIntToFpCombine(N, DAG, Subtarget);
8512 return performORCombine(N, DCI, Subtarget);
8513 case ISD::INTRINSIC_WO_CHAIN:
8514 return performIntrinsicCombine(N, DCI, Subtarget);
8515 case ISD::ANY_EXTEND:
8516 case ISD::ZERO_EXTEND:
8517 case ISD::SIGN_EXTEND:
8518 return performExtendCombine(N, DCI, DAG);
8520 return performBitcastCombine(N, DCI, DAG);
8521 case ISD::CONCAT_VECTORS:
8522 return performConcatVectorsCombine(N, DCI, DAG);
8524 return performSelectCombine(N, DAG);
8526 return performVSelectCombine(N, DCI.DAG);
8528 return performSTORECombine(N, DCI, DAG, Subtarget);
8529 case AArch64ISD::BRCOND:
8530 return performBRCONDCombine(N, DCI, DAG);
8531 case AArch64ISD::CSEL:
8532 return performCONDCombine(N, DCI, DAG, 2, 3);
8533 case AArch64ISD::DUP:
8534 return performPostLD1Combine(N, DCI, false);
8535 case ISD::INSERT_VECTOR_ELT:
8536 return performPostLD1Combine(N, DCI, true);
8537 case ISD::INTRINSIC_VOID:
8538 case ISD::INTRINSIC_W_CHAIN:
8539 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8540 case Intrinsic::aarch64_neon_ld2:
8541 case Intrinsic::aarch64_neon_ld3:
8542 case Intrinsic::aarch64_neon_ld4:
8543 case Intrinsic::aarch64_neon_ld1x2:
8544 case Intrinsic::aarch64_neon_ld1x3:
8545 case Intrinsic::aarch64_neon_ld1x4:
8546 case Intrinsic::aarch64_neon_ld2lane:
8547 case Intrinsic::aarch64_neon_ld3lane:
8548 case Intrinsic::aarch64_neon_ld4lane:
8549 case Intrinsic::aarch64_neon_ld2r:
8550 case Intrinsic::aarch64_neon_ld3r:
8551 case Intrinsic::aarch64_neon_ld4r:
8552 case Intrinsic::aarch64_neon_st2:
8553 case Intrinsic::aarch64_neon_st3:
8554 case Intrinsic::aarch64_neon_st4:
8555 case Intrinsic::aarch64_neon_st1x2:
8556 case Intrinsic::aarch64_neon_st1x3:
8557 case Intrinsic::aarch64_neon_st1x4:
8558 case Intrinsic::aarch64_neon_st2lane:
8559 case Intrinsic::aarch64_neon_st3lane:
8560 case Intrinsic::aarch64_neon_st4lane:
8561 return performNEONPostLDSTCombine(N, DCI, DAG);
8569 // Check if the return value is used as only a return value, as otherwise
8570 // we can't perform a tail-call. In particular, we need to check for
8571 // target ISD nodes that are returns and any other "odd" constructs
8572 // that the generic analysis code won't necessarily catch.
8573 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8574 SDValue &Chain) const {
8575 if (N->getNumValues() != 1)
8577 if (!N->hasNUsesOfValue(1, 0))
8580 SDValue TCChain = Chain;
8581 SDNode *Copy = *N->use_begin();
8582 if (Copy->getOpcode() == ISD::CopyToReg) {
8583 // If the copy has a glue operand, we conservatively assume it isn't safe to
8584 // perform a tail call.
8585 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8588 TCChain = Copy->getOperand(0);
8589 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8592 bool HasRet = false;
8593 for (SDNode *Node : Copy->uses()) {
8594 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8606 // Return whether the an instruction can potentially be optimized to a tail
8607 // call. This will cause the optimizers to attempt to move, or duplicate,
8608 // return instructions to help enable tail call optimizations for this
8610 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8611 if (!CI->isTailCall())
8617 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8619 ISD::MemIndexedMode &AM,
8621 SelectionDAG &DAG) const {
8622 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8625 Base = Op->getOperand(0);
8626 // All of the indexed addressing mode instructions take a signed
8627 // 9 bit immediate offset.
8628 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8629 int64_t RHSC = (int64_t)RHS->getZExtValue();
8630 if (RHSC >= 256 || RHSC <= -256)
8632 IsInc = (Op->getOpcode() == ISD::ADD);
8633 Offset = Op->getOperand(1);
8639 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8641 ISD::MemIndexedMode &AM,
8642 SelectionDAG &DAG) const {
8645 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8646 VT = LD->getMemoryVT();
8647 Ptr = LD->getBasePtr();
8648 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8649 VT = ST->getMemoryVT();
8650 Ptr = ST->getBasePtr();
8655 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8657 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8661 bool AArch64TargetLowering::getPostIndexedAddressParts(
8662 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8663 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8666 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8667 VT = LD->getMemoryVT();
8668 Ptr = LD->getBasePtr();
8669 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8670 VT = ST->getMemoryVT();
8671 Ptr = ST->getBasePtr();
8676 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8678 // Post-indexing updates the base, so it's not a valid transform
8679 // if that's not the same as the load's pointer.
8682 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8686 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8687 SelectionDAG &DAG) {
8689 SDValue Op = N->getOperand(0);
8691 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8695 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8696 DAG.getUNDEF(MVT::i32), Op,
8697 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8699 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8700 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8703 void AArch64TargetLowering::ReplaceNodeResults(
8704 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8705 switch (N->getOpcode()) {
8707 llvm_unreachable("Don't know how to custom expand this");
8709 ReplaceBITCASTResults(N, Results, DAG);
8711 case ISD::FP_TO_UINT:
8712 case ISD::FP_TO_SINT:
8713 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8714 // Let normal code take care of it by not adding anything to Results.
8719 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8723 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8724 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8725 // reciprocal if there are three or more FDIVs.
8726 return NumUsers > 2;
8729 TargetLoweringBase::LegalizeTypeAction
8730 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8731 MVT SVT = VT.getSimpleVT();
8732 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8733 // v4i16, v2i32 instead of to promote.
8734 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8735 || SVT == MVT::v1f32)
8736 return TypeWidenVector;
8738 return TargetLoweringBase::getPreferredVectorAction(VT);
8741 // Loads and stores less than 128-bits are already atomic; ones above that
8742 // are doomed anyway, so defer to the default libcall and blame the OS when
8744 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8745 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8749 // Loads and stores less than 128-bits are already atomic; ones above that
8750 // are doomed anyway, so defer to the default libcall and blame the OS when
8752 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8753 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8757 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8758 bool AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8759 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8763 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8767 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8768 AtomicOrdering Ord) const {
8769 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8770 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8771 bool IsAcquire = isAtLeastAcquire(Ord);
8773 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8774 // intrinsic must return {i64, i64} and we have to recombine them into a
8775 // single i128 here.
8776 if (ValTy->getPrimitiveSizeInBits() == 128) {
8778 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8779 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8781 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8782 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8784 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8785 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8786 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8787 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8788 return Builder.CreateOr(
8789 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8792 Type *Tys[] = { Addr->getType() };
8794 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8795 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8797 return Builder.CreateTruncOrBitCast(
8798 Builder.CreateCall(Ldxr, Addr),
8799 cast<PointerType>(Addr->getType())->getElementType());
8802 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8803 Value *Val, Value *Addr,
8804 AtomicOrdering Ord) const {
8805 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8806 bool IsRelease = isAtLeastRelease(Ord);
8808 // Since the intrinsics must have legal type, the i128 intrinsics take two
8809 // parameters: "i64, i64". We must marshal Val into the appropriate form
8811 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8813 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8814 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8815 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8817 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8818 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8819 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8820 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8824 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8825 Type *Tys[] = { Addr->getType() };
8826 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8828 return Builder.CreateCall2(
8829 Stxr, Builder.CreateZExtOrBitCast(
8830 Val, Stxr->getFunctionType()->getParamType(0)),
8834 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
8835 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
8836 return Ty->isArrayTy();