1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
43 // Place holder until extr generation is tested fully.
45 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
46 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
50 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
51 cl::desc("Allow AArch64 SLI/SRI formation"),
54 // FIXME: The necessary dtprel relocations don't seem to be supported
55 // well in the GNU bfd and gold linkers at the moment. Therefore, by
56 // default, for now, fall back to GeneralDynamic code generation.
57 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
58 "aarch64-elf-ldtls-generation", cl::Hidden,
59 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
62 /// Value type used for condition codes.
63 static const MVT MVT_CC = MVT::i32;
65 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
66 const AArch64Subtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
70 // we have to make something up. Arbitrarily, choose ZeroOrOne.
71 setBooleanContents(ZeroOrOneBooleanContent);
72 // When comparing vectors the result sets the different elements in the
73 // vector to all-one or all-zero.
74 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
78 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
80 if (Subtarget->hasFPARMv8()) {
81 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
82 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
83 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
84 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
87 if (Subtarget->hasNEON()) {
88 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
89 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
90 // Someone set us up the NEON.
91 addDRTypeForNEON(MVT::v2f32);
92 addDRTypeForNEON(MVT::v8i8);
93 addDRTypeForNEON(MVT::v4i16);
94 addDRTypeForNEON(MVT::v2i32);
95 addDRTypeForNEON(MVT::v1i64);
96 addDRTypeForNEON(MVT::v1f64);
97 addDRTypeForNEON(MVT::v4f16);
99 addQRTypeForNEON(MVT::v4f32);
100 addQRTypeForNEON(MVT::v2f64);
101 addQRTypeForNEON(MVT::v16i8);
102 addQRTypeForNEON(MVT::v8i16);
103 addQRTypeForNEON(MVT::v4i32);
104 addQRTypeForNEON(MVT::v2i64);
105 addQRTypeForNEON(MVT::v8f16);
108 // Compute derived properties from the register classes
109 computeRegisterProperties(Subtarget->getRegisterInfo());
111 // Provide all sorts of operation actions
112 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
120 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
121 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
122 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
123 setOperationAction(ISD::SELECT, MVT::i32, Custom);
124 setOperationAction(ISD::SELECT, MVT::i64, Custom);
125 setOperationAction(ISD::SELECT, MVT::f32, Custom);
126 setOperationAction(ISD::SELECT, MVT::f64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
131 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
135 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
136 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Expand);
139 setOperationAction(ISD::FREM, MVT::f64, Expand);
140 setOperationAction(ISD::FREM, MVT::f80, Expand);
142 // Custom lowering hooks are needed for XOR
143 // to fold it into CSINC/CSINV.
144 setOperationAction(ISD::XOR, MVT::i32, Custom);
145 setOperationAction(ISD::XOR, MVT::i64, Custom);
147 // Virtually no operation on f128 is legal, but LLVM can't expand them when
148 // there's a valid register class, so we need custom operations in most cases.
149 setOperationAction(ISD::FABS, MVT::f128, Expand);
150 setOperationAction(ISD::FADD, MVT::f128, Custom);
151 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
152 setOperationAction(ISD::FCOS, MVT::f128, Expand);
153 setOperationAction(ISD::FDIV, MVT::f128, Custom);
154 setOperationAction(ISD::FMA, MVT::f128, Expand);
155 setOperationAction(ISD::FMUL, MVT::f128, Custom);
156 setOperationAction(ISD::FNEG, MVT::f128, Expand);
157 setOperationAction(ISD::FPOW, MVT::f128, Expand);
158 setOperationAction(ISD::FREM, MVT::f128, Expand);
159 setOperationAction(ISD::FRINT, MVT::f128, Expand);
160 setOperationAction(ISD::FSIN, MVT::f128, Expand);
161 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
162 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
163 setOperationAction(ISD::FSUB, MVT::f128, Custom);
164 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
166 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
167 setOperationAction(ISD::SELECT, MVT::f128, Custom);
168 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
169 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
171 // Lowering for many of the conversions is actually specified by the non-f128
172 // type. The LowerXXX function will be trivial when f128 isn't involved.
173 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
177 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
178 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
182 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
183 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
184 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
186 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
188 // Variable arguments.
189 setOperationAction(ISD::VASTART, MVT::Other, Custom);
190 setOperationAction(ISD::VAARG, MVT::Other, Custom);
191 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
192 setOperationAction(ISD::VAEND, MVT::Other, Expand);
194 // Variable-sized objects.
195 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
196 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
197 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
199 // Exception handling.
200 // FIXME: These are guesses. Has this been defined yet?
201 setExceptionPointerRegister(AArch64::X0);
202 setExceptionSelectorRegister(AArch64::X1);
204 // Constant pool entries
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
208 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
210 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
211 setOperationAction(ISD::ADDC, MVT::i32, Custom);
212 setOperationAction(ISD::ADDE, MVT::i32, Custom);
213 setOperationAction(ISD::SUBC, MVT::i32, Custom);
214 setOperationAction(ISD::SUBE, MVT::i32, Custom);
215 setOperationAction(ISD::ADDC, MVT::i64, Custom);
216 setOperationAction(ISD::ADDE, MVT::i64, Custom);
217 setOperationAction(ISD::SUBC, MVT::i64, Custom);
218 setOperationAction(ISD::SUBE, MVT::i64, Custom);
220 // AArch64 lacks both left-rotate and popcount instructions.
221 setOperationAction(ISD::ROTL, MVT::i32, Expand);
222 setOperationAction(ISD::ROTL, MVT::i64, Expand);
224 // AArch64 doesn't have {U|S}MUL_LOHI.
225 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
226 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
229 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
230 // counterparts, which AArch64 supports directly.
231 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
232 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
233 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
234 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
236 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
237 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
239 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
240 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
241 setOperationAction(ISD::SREM, MVT::i32, Expand);
242 setOperationAction(ISD::SREM, MVT::i64, Expand);
243 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
244 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
245 setOperationAction(ISD::UREM, MVT::i32, Expand);
246 setOperationAction(ISD::UREM, MVT::i64, Expand);
248 // Custom lower Add/Sub/Mul with overflow.
249 setOperationAction(ISD::SADDO, MVT::i32, Custom);
250 setOperationAction(ISD::SADDO, MVT::i64, Custom);
251 setOperationAction(ISD::UADDO, MVT::i32, Custom);
252 setOperationAction(ISD::UADDO, MVT::i64, Custom);
253 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
254 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
255 setOperationAction(ISD::USUBO, MVT::i32, Custom);
256 setOperationAction(ISD::USUBO, MVT::i64, Custom);
257 setOperationAction(ISD::SMULO, MVT::i32, Custom);
258 setOperationAction(ISD::SMULO, MVT::i64, Custom);
259 setOperationAction(ISD::UMULO, MVT::i32, Custom);
260 setOperationAction(ISD::UMULO, MVT::i64, Custom);
262 setOperationAction(ISD::FSIN, MVT::f32, Expand);
263 setOperationAction(ISD::FSIN, MVT::f64, Expand);
264 setOperationAction(ISD::FCOS, MVT::f32, Expand);
265 setOperationAction(ISD::FCOS, MVT::f64, Expand);
266 setOperationAction(ISD::FPOW, MVT::f32, Expand);
267 setOperationAction(ISD::FPOW, MVT::f64, Expand);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
269 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
271 // f16 is a storage-only type, always promote it to f32.
272 setOperationAction(ISD::SETCC, MVT::f16, Promote);
273 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
274 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
275 setOperationAction(ISD::SELECT, MVT::f16, Promote);
276 setOperationAction(ISD::FADD, MVT::f16, Promote);
277 setOperationAction(ISD::FSUB, MVT::f16, Promote);
278 setOperationAction(ISD::FMUL, MVT::f16, Promote);
279 setOperationAction(ISD::FDIV, MVT::f16, Promote);
280 setOperationAction(ISD::FREM, MVT::f16, Promote);
281 setOperationAction(ISD::FMA, MVT::f16, Promote);
282 setOperationAction(ISD::FNEG, MVT::f16, Promote);
283 setOperationAction(ISD::FABS, MVT::f16, Promote);
284 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
285 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
286 setOperationAction(ISD::FCOS, MVT::f16, Promote);
287 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
288 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
289 setOperationAction(ISD::FPOW, MVT::f16, Promote);
290 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
291 setOperationAction(ISD::FRINT, MVT::f16, Promote);
292 setOperationAction(ISD::FSIN, MVT::f16, Promote);
293 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
294 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
295 setOperationAction(ISD::FEXP, MVT::f16, Promote);
296 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
297 setOperationAction(ISD::FLOG, MVT::f16, Promote);
298 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
299 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
300 setOperationAction(ISD::FROUND, MVT::f16, Promote);
301 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
302 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
303 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
304 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
305 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
307 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
309 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
310 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
311 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
312 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
313 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
314 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
315 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
316 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
317 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
318 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
319 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
320 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
322 // Expand all other v4f16 operations.
323 // FIXME: We could generate better code by promoting some operations to
325 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
326 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
327 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
328 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
329 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
330 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
331 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
332 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
333 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
334 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
335 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
336 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
337 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
338 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
339 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
340 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
341 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
342 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
343 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
344 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
345 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
346 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
347 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
348 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
349 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
350 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
353 // v8f16 is also a storage-only type, so expand it.
354 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
355 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
356 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
357 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
358 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
359 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
360 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
361 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
362 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
363 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
364 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
365 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
366 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
367 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
368 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
369 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
370 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
371 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
372 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
373 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
374 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
375 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
376 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
377 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
378 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
379 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
380 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
381 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
382 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
383 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
384 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
386 // AArch64 has implementations of a lot of rounding-like FP operations.
387 for (MVT Ty : {MVT::f32, MVT::f64}) {
388 setOperationAction(ISD::FFLOOR, Ty, Legal);
389 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
390 setOperationAction(ISD::FCEIL, Ty, Legal);
391 setOperationAction(ISD::FRINT, Ty, Legal);
392 setOperationAction(ISD::FTRUNC, Ty, Legal);
393 setOperationAction(ISD::FROUND, Ty, Legal);
394 setOperationAction(ISD::FMINNUM, Ty, Legal);
395 setOperationAction(ISD::FMAXNUM, Ty, Legal);
396 setOperationAction(ISD::FMINNAN, Ty, Legal);
397 setOperationAction(ISD::FMAXNAN, Ty, Legal);
400 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
402 // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
403 // This requires the Performance Monitors extension.
404 if (Subtarget->hasPerfMon())
405 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
407 if (Subtarget->isTargetMachO()) {
408 // For iOS, we don't want to the normal expansion of a libcall to
409 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
411 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
412 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
414 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
415 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
418 // Make floating-point constants legal for the large code model, so they don't
419 // become loads from the constant pool.
420 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
421 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
422 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
425 // AArch64 does not have floating-point extending loads, i1 sign-extending
426 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
427 for (MVT VT : MVT::fp_valuetypes()) {
428 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
429 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
433 for (MVT VT : MVT::integer_valuetypes())
434 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
436 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
437 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
438 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
439 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
440 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
441 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
444 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
445 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
447 // Indexed loads and stores are supported.
448 for (unsigned im = (unsigned)ISD::PRE_INC;
449 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
450 setIndexedLoadAction(im, MVT::i8, Legal);
451 setIndexedLoadAction(im, MVT::i16, Legal);
452 setIndexedLoadAction(im, MVT::i32, Legal);
453 setIndexedLoadAction(im, MVT::i64, Legal);
454 setIndexedLoadAction(im, MVT::f64, Legal);
455 setIndexedLoadAction(im, MVT::f32, Legal);
456 setIndexedLoadAction(im, MVT::f16, Legal);
457 setIndexedStoreAction(im, MVT::i8, Legal);
458 setIndexedStoreAction(im, MVT::i16, Legal);
459 setIndexedStoreAction(im, MVT::i32, Legal);
460 setIndexedStoreAction(im, MVT::i64, Legal);
461 setIndexedStoreAction(im, MVT::f64, Legal);
462 setIndexedStoreAction(im, MVT::f32, Legal);
463 setIndexedStoreAction(im, MVT::f16, Legal);
467 setOperationAction(ISD::TRAP, MVT::Other, Legal);
469 // We combine OR nodes for bitfield operations.
470 setTargetDAGCombine(ISD::OR);
472 // Vector add and sub nodes may conceal a high-half opportunity.
473 // Also, try to fold ADD into CSINC/CSINV..
474 setTargetDAGCombine(ISD::ADD);
475 setTargetDAGCombine(ISD::SUB);
477 setTargetDAGCombine(ISD::XOR);
478 setTargetDAGCombine(ISD::SINT_TO_FP);
479 setTargetDAGCombine(ISD::UINT_TO_FP);
481 setTargetDAGCombine(ISD::FP_TO_SINT);
482 setTargetDAGCombine(ISD::FP_TO_UINT);
484 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
486 setTargetDAGCombine(ISD::ANY_EXTEND);
487 setTargetDAGCombine(ISD::ZERO_EXTEND);
488 setTargetDAGCombine(ISD::SIGN_EXTEND);
489 setTargetDAGCombine(ISD::BITCAST);
490 setTargetDAGCombine(ISD::CONCAT_VECTORS);
491 setTargetDAGCombine(ISD::STORE);
493 setTargetDAGCombine(ISD::MUL);
495 setTargetDAGCombine(ISD::SELECT);
496 setTargetDAGCombine(ISD::VSELECT);
498 setTargetDAGCombine(ISD::INTRINSIC_VOID);
499 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
500 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
501 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
503 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
504 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
505 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
507 setStackPointerRegisterToSaveRestore(AArch64::SP);
509 setSchedulingPreference(Sched::Hybrid);
512 MaskAndBranchFoldingIsLegal = true;
513 EnableExtLdPromotion = true;
515 setMinFunctionAlignment(2);
517 setHasExtractBitsInsn(true);
519 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
521 if (Subtarget->hasNEON()) {
522 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
523 // silliness like this:
524 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
525 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
526 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
527 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
528 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
529 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
530 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
531 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
532 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
533 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
534 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
535 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
536 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
537 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
538 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
539 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
540 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
541 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
542 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
543 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
544 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
545 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
546 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
547 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
548 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
550 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
551 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
552 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
553 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
554 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
556 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
558 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
559 // elements smaller than i32, so promote the input to i32 first.
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
561 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
562 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
563 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
564 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
565 // -> v8f16 conversions.
566 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
567 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
568 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
569 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
570 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
571 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
572 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
573 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
574 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
575 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
576 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
577 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
578 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
580 // AArch64 doesn't have MUL.2d:
581 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
582 // Custom handling for some quad-vector types to detect MULL.
583 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
584 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
585 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
587 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
588 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
589 // Likewise, narrowing and extending vector loads/stores aren't handled
591 for (MVT VT : MVT::vector_valuetypes()) {
592 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
594 setOperationAction(ISD::MULHS, VT, Expand);
595 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
596 setOperationAction(ISD::MULHU, VT, Expand);
597 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
599 setOperationAction(ISD::BSWAP, VT, Expand);
601 for (MVT InnerVT : MVT::vector_valuetypes()) {
602 setTruncStoreAction(VT, InnerVT, Expand);
603 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
604 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
605 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
609 // AArch64 has implementations of a lot of rounding-like FP operations.
610 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
611 setOperationAction(ISD::FFLOOR, Ty, Legal);
612 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
613 setOperationAction(ISD::FCEIL, Ty, Legal);
614 setOperationAction(ISD::FRINT, Ty, Legal);
615 setOperationAction(ISD::FTRUNC, Ty, Legal);
616 setOperationAction(ISD::FROUND, Ty, Legal);
620 // Prefer likely predicted branches to selects on out-of-order cores.
621 if (Subtarget->isCortexA57())
622 PredictableSelectIsExpensive = true;
625 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
626 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
627 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
628 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
630 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
631 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
632 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
633 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
634 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
636 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
637 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
640 // Mark vector float intrinsics as expand.
641 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
642 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
645 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
647 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
648 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
649 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
650 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
652 // But we do support custom-lowering for FCOPYSIGN.
653 setOperationAction(ISD::FCOPYSIGN, VT.getSimpleVT(), Custom);
656 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
661 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
662 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
663 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
664 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
665 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
666 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
667 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
669 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
670 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
671 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
672 for (MVT InnerVT : MVT::all_valuetypes())
673 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
675 // CNT supports only B element sizes.
676 if (VT != MVT::v8i8 && VT != MVT::v16i8)
677 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
679 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
680 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
681 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
682 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
683 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
685 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
686 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
688 // [SU][MIN|MAX] and [SU]ABSDIFF are available for all NEON types apart from
690 if (!VT.isFloatingPoint() &&
691 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
692 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
693 ISD::SABSDIFF, ISD::UABSDIFF})
694 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
696 // F[MIN|MAX][NUM|NAN] are available for all FP NEON types (not f16 though!).
697 if (VT.isFloatingPoint() && VT.getVectorElementType() != MVT::f16)
698 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
699 ISD::FMINNUM, ISD::FMAXNUM})
700 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
702 if (Subtarget->isLittleEndian()) {
703 for (unsigned im = (unsigned)ISD::PRE_INC;
704 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
705 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
706 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
711 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
712 addRegisterClass(VT, &AArch64::FPR64RegClass);
713 addTypeForNEON(VT, MVT::v2i32);
716 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
717 addRegisterClass(VT, &AArch64::FPR128RegClass);
718 addTypeForNEON(VT, MVT::v4i32);
721 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
725 return VT.changeVectorElementTypeToInteger();
728 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
729 /// Mask are known to be either zero or one and return them in the
730 /// KnownZero/KnownOne bitsets.
731 void AArch64TargetLowering::computeKnownBitsForTargetNode(
732 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
733 const SelectionDAG &DAG, unsigned Depth) const {
734 switch (Op.getOpcode()) {
737 case AArch64ISD::CSEL: {
738 APInt KnownZero2, KnownOne2;
739 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
740 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
741 KnownZero &= KnownZero2;
742 KnownOne &= KnownOne2;
745 case ISD::INTRINSIC_W_CHAIN: {
746 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
747 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
750 case Intrinsic::aarch64_ldaxr:
751 case Intrinsic::aarch64_ldxr: {
752 unsigned BitWidth = KnownOne.getBitWidth();
753 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
754 unsigned MemBits = VT.getScalarType().getSizeInBits();
755 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
761 case ISD::INTRINSIC_WO_CHAIN:
762 case ISD::INTRINSIC_VOID: {
763 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
767 case Intrinsic::aarch64_neon_umaxv:
768 case Intrinsic::aarch64_neon_uminv: {
769 // Figure out the datatype of the vector operand. The UMINV instruction
770 // will zero extend the result, so we can mark as known zero all the
771 // bits larger than the element datatype. 32-bit or larget doesn't need
772 // this as those are legal types and will be handled by isel directly.
773 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
774 unsigned BitWidth = KnownZero.getBitWidth();
775 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
776 assert(BitWidth >= 8 && "Unexpected width!");
777 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
779 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
780 assert(BitWidth >= 16 && "Unexpected width!");
781 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
791 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
796 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
800 if (Subtarget->requiresStrictAlign())
803 // FIXME: This is mostly true for Cyclone, but not necessarily others.
805 // FIXME: Define an attribute for slow unaligned accesses instead of
806 // relying on the CPU type as a proxy.
807 // On Cyclone, unaligned 128-bit stores are slow.
808 *Fast = !Subtarget->isCyclone() || VT.getStoreSize() != 16 ||
809 // See comments in performSTORECombine() for more details about
812 // Code that uses clang vector extensions can mark that it
813 // wants unaligned accesses to be treated as fast by
814 // underspecifying alignment to be 1 or 2.
817 // Disregard v2i64. Memcpy lowering produces those and splitting
818 // them regresses performance on micro-benchmarks and olden/bh.
825 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
826 const TargetLibraryInfo *libInfo) const {
827 return AArch64::createFastISel(funcInfo, libInfo);
830 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
831 switch ((AArch64ISD::NodeType)Opcode) {
832 case AArch64ISD::FIRST_NUMBER: break;
833 case AArch64ISD::CALL: return "AArch64ISD::CALL";
834 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
835 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
836 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
837 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
838 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
839 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
840 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
841 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
842 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
843 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
844 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
845 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
846 case AArch64ISD::ADC: return "AArch64ISD::ADC";
847 case AArch64ISD::SBC: return "AArch64ISD::SBC";
848 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
849 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
850 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
851 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
852 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
853 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
854 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
855 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
856 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
857 case AArch64ISD::DUP: return "AArch64ISD::DUP";
858 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
859 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
860 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
861 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
862 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
863 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
864 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
865 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
866 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
867 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
868 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
869 case AArch64ISD::BICi: return "AArch64ISD::BICi";
870 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
871 case AArch64ISD::BSL: return "AArch64ISD::BSL";
872 case AArch64ISD::NEG: return "AArch64ISD::NEG";
873 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
874 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
875 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
876 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
877 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
878 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
879 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
880 case AArch64ISD::REV16: return "AArch64ISD::REV16";
881 case AArch64ISD::REV32: return "AArch64ISD::REV32";
882 case AArch64ISD::REV64: return "AArch64ISD::REV64";
883 case AArch64ISD::EXT: return "AArch64ISD::EXT";
884 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
885 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
886 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
887 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
888 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
889 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
890 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
891 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
892 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
893 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
894 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
895 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
896 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
897 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
898 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
899 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
900 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
901 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
902 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
903 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
904 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
905 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
906 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
907 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
908 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
909 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
910 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
911 case AArch64ISD::NOT: return "AArch64ISD::NOT";
912 case AArch64ISD::BIT: return "AArch64ISD::BIT";
913 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
914 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
915 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
916 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
917 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
918 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
919 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
920 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
921 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
922 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
923 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
924 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
925 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
926 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
927 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
928 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
929 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
930 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
931 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
932 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
933 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
934 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
935 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
936 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
937 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
938 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
939 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
940 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
941 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
942 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
943 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
944 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
945 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
946 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
947 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
948 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
949 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
950 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
951 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
952 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
958 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
959 MachineBasicBlock *MBB) const {
960 // We materialise the F128CSEL pseudo-instruction as some control flow and a
964 // [... previous instrs leading to comparison ...]
970 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
972 MachineFunction *MF = MBB->getParent();
973 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
974 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
975 DebugLoc DL = MI->getDebugLoc();
976 MachineFunction::iterator It = MBB;
979 unsigned DestReg = MI->getOperand(0).getReg();
980 unsigned IfTrueReg = MI->getOperand(1).getReg();
981 unsigned IfFalseReg = MI->getOperand(2).getReg();
982 unsigned CondCode = MI->getOperand(3).getImm();
983 bool NZCVKilled = MI->getOperand(4).isKill();
985 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
986 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
987 MF->insert(It, TrueBB);
988 MF->insert(It, EndBB);
990 // Transfer rest of current basic-block to EndBB
991 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
993 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
995 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
996 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
997 MBB->addSuccessor(TrueBB);
998 MBB->addSuccessor(EndBB);
1000 // TrueBB falls through to the end.
1001 TrueBB->addSuccessor(EndBB);
1004 TrueBB->addLiveIn(AArch64::NZCV);
1005 EndBB->addLiveIn(AArch64::NZCV);
1008 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
1014 MI->eraseFromParent();
1019 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1020 MachineBasicBlock *BB) const {
1021 switch (MI->getOpcode()) {
1026 llvm_unreachable("Unexpected instruction for custom inserter!");
1028 case AArch64::F128CSEL:
1029 return EmitF128CSEL(MI, BB);
1031 case TargetOpcode::STACKMAP:
1032 case TargetOpcode::PATCHPOINT:
1033 return emitPatchPoint(MI, BB);
1037 //===----------------------------------------------------------------------===//
1038 // AArch64 Lowering private implementation.
1039 //===----------------------------------------------------------------------===//
1041 //===----------------------------------------------------------------------===//
1043 //===----------------------------------------------------------------------===//
1045 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1047 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1050 llvm_unreachable("Unknown condition code!");
1052 return AArch64CC::NE;
1054 return AArch64CC::EQ;
1056 return AArch64CC::GT;
1058 return AArch64CC::GE;
1060 return AArch64CC::LT;
1062 return AArch64CC::LE;
1064 return AArch64CC::HI;
1066 return AArch64CC::HS;
1068 return AArch64CC::LO;
1070 return AArch64CC::LS;
1074 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1075 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1076 AArch64CC::CondCode &CondCode,
1077 AArch64CC::CondCode &CondCode2) {
1078 CondCode2 = AArch64CC::AL;
1081 llvm_unreachable("Unknown FP condition!");
1084 CondCode = AArch64CC::EQ;
1088 CondCode = AArch64CC::GT;
1092 CondCode = AArch64CC::GE;
1095 CondCode = AArch64CC::MI;
1098 CondCode = AArch64CC::LS;
1101 CondCode = AArch64CC::MI;
1102 CondCode2 = AArch64CC::GT;
1105 CondCode = AArch64CC::VC;
1108 CondCode = AArch64CC::VS;
1111 CondCode = AArch64CC::EQ;
1112 CondCode2 = AArch64CC::VS;
1115 CondCode = AArch64CC::HI;
1118 CondCode = AArch64CC::PL;
1122 CondCode = AArch64CC::LT;
1126 CondCode = AArch64CC::LE;
1130 CondCode = AArch64CC::NE;
1135 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1136 /// CC usable with the vector instructions. Fewer operations are available
1137 /// without a real NZCV register, so we have to use less efficient combinations
1138 /// to get the same effect.
1139 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1140 AArch64CC::CondCode &CondCode,
1141 AArch64CC::CondCode &CondCode2,
1146 // Mostly the scalar mappings work fine.
1147 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1150 Invert = true; // Fallthrough
1152 CondCode = AArch64CC::MI;
1153 CondCode2 = AArch64CC::GE;
1160 // All of the compare-mask comparisons are ordered, but we can switch
1161 // between the two by a double inversion. E.g. ULE == !OGT.
1163 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1168 static bool isLegalArithImmed(uint64_t C) {
1169 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1170 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1173 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1174 SDLoc dl, SelectionDAG &DAG) {
1175 EVT VT = LHS.getValueType();
1177 if (VT.isFloatingPoint())
1178 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1180 // The CMP instruction is just an alias for SUBS, and representing it as
1181 // SUBS means that it's possible to get CSE with subtract operations.
1182 // A later phase can perform the optimization of setting the destination
1183 // register to WZR/XZR if it ends up being unused.
1184 unsigned Opcode = AArch64ISD::SUBS;
1186 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1187 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1188 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1189 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1190 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1191 // can be set differently by this operation. It comes down to whether
1192 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1193 // everything is fine. If not then the optimization is wrong. Thus general
1194 // comparisons are only valid if op2 != 0.
1196 // So, finally, the only LLVM-native comparisons that don't mention C and V
1197 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1198 // the absence of information about op2.
1199 Opcode = AArch64ISD::ADDS;
1200 RHS = RHS.getOperand(1);
1201 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1202 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1203 !isUnsignedIntSetCC(CC)) {
1204 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1205 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1206 // of the signed comparisons.
1207 Opcode = AArch64ISD::ANDS;
1208 RHS = LHS.getOperand(1);
1209 LHS = LHS.getOperand(0);
1212 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1216 /// \defgroup AArch64CCMP CMP;CCMP matching
1218 /// These functions deal with the formation of CMP;CCMP;... sequences.
1219 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1220 /// a comparison. They set the NZCV flags to a predefined value if their
1221 /// predicate is false. This allows to express arbitrary conjunctions, for
1222 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1225 /// ccmp B, inv(CB), CA
1226 /// check for CB flags
1228 /// In general we can create code for arbitrary "... (and (and A B) C)"
1229 /// sequences. We can also implement some "or" expressions, because "(or A B)"
1230 /// is equivalent to "not (and (not A) (not B))" and we can implement some
1231 /// negation operations:
1232 /// We can negate the results of a single comparison by inverting the flags
1233 /// used when the predicate fails and inverting the flags tested in the next
1234 /// instruction; We can also negate the results of the whole previous
1235 /// conditional compare sequence by inverting the flags tested in the next
1236 /// instruction. However there is no way to negate the result of a partial
1239 /// Therefore on encountering an "or" expression we can negate the subtree on
1240 /// one side and have to be able to push the negate to the leafs of the subtree
1241 /// on the other side (see also the comments in code). As complete example:
1242 /// "or (or (setCA (cmp A)) (setCB (cmp B)))
1243 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1244 /// is transformed to
1245 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1246 /// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1247 /// and implemented as:
1249 /// ccmp D, inv(CD), CC
1250 /// ccmp A, CA, inv(CD)
1251 /// ccmp B, CB, inv(CA)
1252 /// check for CB flags
1253 /// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1254 /// by conditional compare sequences.
1257 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1258 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1259 ISD::CondCode CC, SDValue CCOp,
1260 SDValue Condition, unsigned NZCV,
1261 SDLoc DL, SelectionDAG &DAG) {
1262 unsigned Opcode = 0;
1263 if (LHS.getValueType().isFloatingPoint())
1264 Opcode = AArch64ISD::FCCMP;
1265 else if (RHS.getOpcode() == ISD::SUB) {
1266 SDValue SubOp0 = RHS.getOperand(0);
1267 if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
1268 if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1269 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1270 Opcode = AArch64ISD::CCMN;
1271 RHS = RHS.getOperand(1);
1275 Opcode = AArch64ISD::CCMP;
1277 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1278 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1281 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1282 /// CanPushNegate is set to true if we can push a negate operation through
1283 /// the tree in a was that we are left with AND operations and negate operations
1284 /// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1285 /// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1286 /// brought into such a form.
1287 static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
1288 unsigned Depth = 0) {
1289 if (!Val.hasOneUse())
1291 unsigned Opcode = Val->getOpcode();
1292 if (Opcode == ISD::SETCC) {
1293 CanPushNegate = true;
1296 // Protect against stack overflow.
1299 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1300 SDValue O0 = Val->getOperand(0);
1301 SDValue O1 = Val->getOperand(1);
1302 bool CanPushNegateL;
1303 if (!isConjunctionDisjunctionTree(O0, CanPushNegateL, Depth+1))
1305 bool CanPushNegateR;
1306 if (!isConjunctionDisjunctionTree(O1, CanPushNegateR, Depth+1))
1308 // We cannot push a negate through an AND operation (it would become an OR),
1309 // we can however change a (not (or x y)) to (and (not x) (not y)) if we can
1310 // push the negate through the x/y subtrees.
1311 CanPushNegate = (Opcode == ISD::OR) && CanPushNegateL && CanPushNegateR;
1317 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1318 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1319 /// Tries to transform the given i1 producing node @p Val to a series compare
1320 /// and conditional compare operations. @returns an NZCV flags producing node
1321 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1322 /// transformation was not possible.
1323 /// On recursive invocations @p PushNegate may be set to true to have negation
1324 /// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1325 /// for the comparisons in the current subtree; @p Depth limits the search
1326 /// depth to avoid stack overflow.
1327 static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1328 AArch64CC::CondCode &OutCC, bool PushNegate = false,
1329 SDValue CCOp = SDValue(), AArch64CC::CondCode Predicate = AArch64CC::AL,
1330 unsigned Depth = 0) {
1331 // We're at a tree leaf, produce a conditional comparison operation.
1332 unsigned Opcode = Val->getOpcode();
1333 if (Opcode == ISD::SETCC) {
1334 SDValue LHS = Val->getOperand(0);
1335 SDValue RHS = Val->getOperand(1);
1336 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1337 bool isInteger = LHS.getValueType().isInteger();
1339 CC = getSetCCInverse(CC, isInteger);
1341 // Determine OutCC and handle FP special case.
1343 OutCC = changeIntCCToAArch64CC(CC);
1345 assert(LHS.getValueType().isFloatingPoint());
1346 AArch64CC::CondCode ExtraCC;
1347 changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
1348 // Surpisingly some floating point conditions can't be tested with a
1349 // single condition code. Construct an additional comparison in this case.
1350 // See comment below on how we deal with OR conditions.
1351 if (ExtraCC != AArch64CC::AL) {
1353 if (!CCOp.getNode())
1354 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1356 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1357 // Note that we want the inverse of ExtraCC, so NZCV is not inversed.
1358 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
1359 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
1363 Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
1364 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1368 // Produce a normal comparison if we are first in the chain
1369 if (!CCOp.getNode())
1370 return emitComparison(LHS, RHS, CC, DL, DAG);
1371 // Otherwise produce a ccmp.
1372 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1373 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1374 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1375 return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
1377 } else if ((Opcode != ISD::AND && Opcode != ISD::OR) || !Val->hasOneUse())
1380 assert((Opcode == ISD::OR || !PushNegate)
1381 && "Can only push negate through OR operation");
1383 // Check if both sides can be transformed.
1384 SDValue LHS = Val->getOperand(0);
1385 SDValue RHS = Val->getOperand(1);
1386 bool CanPushNegateL;
1387 if (!isConjunctionDisjunctionTree(LHS, CanPushNegateL, Depth+1))
1389 bool CanPushNegateR;
1390 if (!isConjunctionDisjunctionTree(RHS, CanPushNegateR, Depth+1))
1393 // Do we need to negate our operands?
1394 bool NegateOperands = Opcode == ISD::OR;
1395 // We can negate the results of all previous operations by inverting the
1396 // predicate flags giving us a free negation for one side. For the other side
1397 // we need to be able to push the negation to the leafs of the tree.
1398 if (NegateOperands) {
1399 if (!CanPushNegateL && !CanPushNegateR)
1401 // Order the side where we can push the negate through to LHS.
1402 if (!CanPushNegateL && CanPushNegateR)
1403 std::swap(LHS, RHS);
1405 bool NeedsNegOutL = LHS->getOpcode() == ISD::OR;
1406 bool NeedsNegOutR = RHS->getOpcode() == ISD::OR;
1407 if (NeedsNegOutL && NeedsNegOutR)
1409 // Order the side where we need to negate the output flags to RHS so it
1410 // gets emitted first.
1412 std::swap(LHS, RHS);
1415 // Emit RHS. If we want to negate the tree we only need to push a negate
1416 // through if we are already in a PushNegate case, otherwise we can negate
1417 // the "flags to test" afterwards.
1418 AArch64CC::CondCode RHSCC;
1419 SDValue CmpR = emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, PushNegate,
1420 CCOp, Predicate, Depth+1);
1421 if (NegateOperands && !PushNegate)
1422 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1423 // Emit LHS. We must push the negate through if we need to negate it.
1424 SDValue CmpL = emitConjunctionDisjunctionTree(DAG, LHS, OutCC, NegateOperands,
1425 CmpR, RHSCC, Depth+1);
1426 // If we transformed an OR to and AND then we have to negate the result
1427 // (or absorb a PushNegate resulting in a double negation).
1428 if (Opcode == ISD::OR && !PushNegate)
1429 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1435 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1436 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1437 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1438 EVT VT = RHS.getValueType();
1439 uint64_t C = RHSC->getZExtValue();
1440 if (!isLegalArithImmed(C)) {
1441 // Constant does not fit, try adjusting it by one?
1447 if ((VT == MVT::i32 && C != 0x80000000 &&
1448 isLegalArithImmed((uint32_t)(C - 1))) ||
1449 (VT == MVT::i64 && C != 0x80000000ULL &&
1450 isLegalArithImmed(C - 1ULL))) {
1451 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1452 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1453 RHS = DAG.getConstant(C, dl, VT);
1458 if ((VT == MVT::i32 && C != 0 &&
1459 isLegalArithImmed((uint32_t)(C - 1))) ||
1460 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1461 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1462 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1463 RHS = DAG.getConstant(C, dl, VT);
1468 if ((VT == MVT::i32 && C != INT32_MAX &&
1469 isLegalArithImmed((uint32_t)(C + 1))) ||
1470 (VT == MVT::i64 && C != INT64_MAX &&
1471 isLegalArithImmed(C + 1ULL))) {
1472 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1473 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1474 RHS = DAG.getConstant(C, dl, VT);
1479 if ((VT == MVT::i32 && C != UINT32_MAX &&
1480 isLegalArithImmed((uint32_t)(C + 1))) ||
1481 (VT == MVT::i64 && C != UINT64_MAX &&
1482 isLegalArithImmed(C + 1ULL))) {
1483 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1484 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1485 RHS = DAG.getConstant(C, dl, VT);
1492 AArch64CC::CondCode AArch64CC;
1493 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1494 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1496 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1497 // For the i8 operand, the largest immediate is 255, so this can be easily
1498 // encoded in the compare instruction. For the i16 operand, however, the
1499 // largest immediate cannot be encoded in the compare.
1500 // Therefore, use a sign extending load and cmn to avoid materializing the
1501 // -1 constant. For example,
1503 // ldrh w0, [x0, #0]
1506 // ldrsh w0, [x0, #0]
1508 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1509 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1510 // ensure both the LHS and RHS are truly zero extended and to make sure the
1511 // transformation is profitable.
1512 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1513 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1514 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1515 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1516 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1517 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1519 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1520 DAG.getValueType(MVT::i16));
1521 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1522 RHS.getValueType()),
1524 AArch64CC = changeIntCCToAArch64CC(CC);
1528 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1529 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1530 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1531 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1537 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1538 AArch64CC = changeIntCCToAArch64CC(CC);
1540 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1544 static std::pair<SDValue, SDValue>
1545 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1546 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1547 "Unsupported value type");
1548 SDValue Value, Overflow;
1550 SDValue LHS = Op.getOperand(0);
1551 SDValue RHS = Op.getOperand(1);
1553 switch (Op.getOpcode()) {
1555 llvm_unreachable("Unknown overflow instruction!");
1557 Opc = AArch64ISD::ADDS;
1561 Opc = AArch64ISD::ADDS;
1565 Opc = AArch64ISD::SUBS;
1569 Opc = AArch64ISD::SUBS;
1572 // Multiply needs a little bit extra work.
1576 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1577 if (Op.getValueType() == MVT::i32) {
1578 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1579 // For a 32 bit multiply with overflow check we want the instruction
1580 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1581 // need to generate the following pattern:
1582 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1583 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1584 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1585 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1586 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1587 DAG.getConstant(0, DL, MVT::i64));
1588 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1589 // operation. We need to clear out the upper 32 bits, because we used a
1590 // widening multiply that wrote all 64 bits. In the end this should be a
1592 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1594 // The signed overflow check requires more than just a simple check for
1595 // any bit set in the upper 32 bits of the result. These bits could be
1596 // just the sign bits of a negative number. To perform the overflow
1597 // check we have to arithmetic shift right the 32nd bit of the result by
1598 // 31 bits. Then we compare the result to the upper 32 bits.
1599 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1600 DAG.getConstant(32, DL, MVT::i64));
1601 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1602 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1603 DAG.getConstant(31, DL, MVT::i64));
1604 // It is important that LowerBits is last, otherwise the arithmetic
1605 // shift will not be folded into the compare (SUBS).
1606 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1607 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1610 // The overflow check for unsigned multiply is easy. We only need to
1611 // check if any of the upper 32 bits are set. This can be done with a
1612 // CMP (shifted register). For that we need to generate the following
1614 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1615 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1616 DAG.getConstant(32, DL, MVT::i64));
1617 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1619 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1620 DAG.getConstant(0, DL, MVT::i64),
1621 UpperBits).getValue(1);
1625 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1626 // For the 64 bit multiply
1627 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1629 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1630 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1631 DAG.getConstant(63, DL, MVT::i64));
1632 // It is important that LowerBits is last, otherwise the arithmetic
1633 // shift will not be folded into the compare (SUBS).
1634 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1635 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1638 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1639 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1641 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1642 DAG.getConstant(0, DL, MVT::i64),
1643 UpperBits).getValue(1);
1650 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1652 // Emit the AArch64 operation with overflow check.
1653 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1654 Overflow = Value.getValue(1);
1656 return std::make_pair(Value, Overflow);
1659 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1660 RTLIB::Libcall Call) const {
1661 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1662 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1666 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1667 SDValue Sel = Op.getOperand(0);
1668 SDValue Other = Op.getOperand(1);
1670 // If neither operand is a SELECT_CC, give up.
1671 if (Sel.getOpcode() != ISD::SELECT_CC)
1672 std::swap(Sel, Other);
1673 if (Sel.getOpcode() != ISD::SELECT_CC)
1676 // The folding we want to perform is:
1677 // (xor x, (select_cc a, b, cc, 0, -1) )
1679 // (csel x, (xor x, -1), cc ...)
1681 // The latter will get matched to a CSINV instruction.
1683 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1684 SDValue LHS = Sel.getOperand(0);
1685 SDValue RHS = Sel.getOperand(1);
1686 SDValue TVal = Sel.getOperand(2);
1687 SDValue FVal = Sel.getOperand(3);
1690 // FIXME: This could be generalized to non-integer comparisons.
1691 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1694 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1695 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1697 // The values aren't constants, this isn't the pattern we're looking for.
1698 if (!CFVal || !CTVal)
1701 // We can commute the SELECT_CC by inverting the condition. This
1702 // might be needed to make this fit into a CSINV pattern.
1703 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1704 std::swap(TVal, FVal);
1705 std::swap(CTVal, CFVal);
1706 CC = ISD::getSetCCInverse(CC, true);
1709 // If the constants line up, perform the transform!
1710 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1712 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1715 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1716 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1718 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1725 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1726 EVT VT = Op.getValueType();
1728 // Let legalize expand this if it isn't a legal type yet.
1729 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1732 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1735 bool ExtraOp = false;
1736 switch (Op.getOpcode()) {
1738 llvm_unreachable("Invalid code");
1740 Opc = AArch64ISD::ADDS;
1743 Opc = AArch64ISD::SUBS;
1746 Opc = AArch64ISD::ADCS;
1750 Opc = AArch64ISD::SBCS;
1756 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1757 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1761 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1762 // Let legalize expand this if it isn't a legal type yet.
1763 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1767 AArch64CC::CondCode CC;
1768 // The actual operation that sets the overflow or carry flag.
1769 SDValue Value, Overflow;
1770 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1772 // We use 0 and 1 as false and true values.
1773 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1774 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1776 // We use an inverted condition, because the conditional select is inverted
1777 // too. This will allow it to be selected to a single instruction:
1778 // CSINC Wd, WZR, WZR, invert(cond).
1779 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1780 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1783 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1784 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1787 // Prefetch operands are:
1788 // 1: Address to prefetch
1790 // 3: int locality (0 = no locality ... 3 = extreme locality)
1791 // 4: bool isDataCache
1792 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1794 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1795 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1796 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1798 bool IsStream = !Locality;
1799 // When the locality number is set
1801 // The front-end should have filtered out the out-of-range values
1802 assert(Locality <= 3 && "Prefetch locality out-of-range");
1803 // The locality degree is the opposite of the cache speed.
1804 // Put the number the other way around.
1805 // The encoding starts at 0 for level 1
1806 Locality = 3 - Locality;
1809 // built the mask value encoding the expected behavior.
1810 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1811 (!IsData << 3) | // IsDataCache bit
1812 (Locality << 1) | // Cache level bits
1813 (unsigned)IsStream; // Stream bit
1814 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1815 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1818 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1819 SelectionDAG &DAG) const {
1820 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1823 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1825 return LowerF128Call(Op, DAG, LC);
1828 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1829 SelectionDAG &DAG) const {
1830 if (Op.getOperand(0).getValueType() != MVT::f128) {
1831 // It's legal except when f128 is involved
1836 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1838 // FP_ROUND node has a second operand indicating whether it is known to be
1839 // precise. That doesn't take part in the LibCall so we can't directly use
1841 SDValue SrcVal = Op.getOperand(0);
1842 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1843 /*isSigned*/ false, SDLoc(Op)).first;
1846 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1847 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1848 // Any additional optimization in this function should be recorded
1849 // in the cost tables.
1850 EVT InVT = Op.getOperand(0).getValueType();
1851 EVT VT = Op.getValueType();
1853 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1856 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1858 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1861 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1864 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1865 VT.getVectorNumElements());
1866 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1867 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1870 // Type changing conversions are illegal.
1874 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1875 SelectionDAG &DAG) const {
1876 if (Op.getOperand(0).getValueType().isVector())
1877 return LowerVectorFP_TO_INT(Op, DAG);
1879 // f16 conversions are promoted to f32.
1880 if (Op.getOperand(0).getValueType() == MVT::f16) {
1883 Op.getOpcode(), dl, Op.getValueType(),
1884 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1887 if (Op.getOperand(0).getValueType() != MVT::f128) {
1888 // It's legal except when f128 is involved
1893 if (Op.getOpcode() == ISD::FP_TO_SINT)
1894 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1896 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1898 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1899 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1903 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1904 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1905 // Any additional optimization in this function should be recorded
1906 // in the cost tables.
1907 EVT VT = Op.getValueType();
1909 SDValue In = Op.getOperand(0);
1910 EVT InVT = In.getValueType();
1912 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1914 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1915 InVT.getVectorNumElements());
1916 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1917 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1920 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1922 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1923 EVT CastVT = VT.changeVectorElementTypeToInteger();
1924 In = DAG.getNode(CastOpc, dl, CastVT, In);
1925 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1931 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1932 SelectionDAG &DAG) const {
1933 if (Op.getValueType().isVector())
1934 return LowerVectorINT_TO_FP(Op, DAG);
1936 // f16 conversions are promoted to f32.
1937 if (Op.getValueType() == MVT::f16) {
1940 ISD::FP_ROUND, dl, MVT::f16,
1941 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1942 DAG.getIntPtrConstant(0, dl));
1945 // i128 conversions are libcalls.
1946 if (Op.getOperand(0).getValueType() == MVT::i128)
1949 // Other conversions are legal, unless it's to the completely software-based
1951 if (Op.getValueType() != MVT::f128)
1955 if (Op.getOpcode() == ISD::SINT_TO_FP)
1956 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1958 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1960 return LowerF128Call(Op, DAG, LC);
1963 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1964 SelectionDAG &DAG) const {
1965 // For iOS, we want to call an alternative entry point: __sincos_stret,
1966 // which returns the values in two S / D registers.
1968 SDValue Arg = Op.getOperand(0);
1969 EVT ArgVT = Arg.getValueType();
1970 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1977 Entry.isSExt = false;
1978 Entry.isZExt = false;
1979 Args.push_back(Entry);
1981 const char *LibcallName =
1982 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1984 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
1986 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1987 TargetLowering::CallLoweringInfo CLI(DAG);
1988 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1989 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1991 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1992 return CallResult.first;
1995 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1996 if (Op.getValueType() != MVT::f16)
1999 assert(Op.getOperand(0).getValueType() == MVT::i16);
2002 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
2003 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
2005 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
2006 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
2010 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
2011 if (OrigVT.getSizeInBits() >= 64)
2014 assert(OrigVT.isSimple() && "Expecting a simple value type");
2016 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
2017 switch (OrigSimpleTy) {
2018 default: llvm_unreachable("Unexpected Vector Type");
2027 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
2030 unsigned ExtOpcode) {
2031 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
2032 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
2033 // 64-bits we need to insert a new extension so that it will be 64-bits.
2034 assert(ExtTy.is128BitVector() && "Unexpected extension size");
2035 if (OrigTy.getSizeInBits() >= 64)
2038 // Must extend size to at least 64 bits to be used as an operand for VMULL.
2039 EVT NewVT = getExtensionTo64Bits(OrigTy);
2041 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
2044 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2046 EVT VT = N->getValueType(0);
2048 if (N->getOpcode() != ISD::BUILD_VECTOR)
2051 for (const SDValue &Elt : N->op_values()) {
2052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2054 unsigned HalfSize = EltSize / 2;
2056 if (!isIntN(HalfSize, C->getSExtValue()))
2059 if (!isUIntN(HalfSize, C->getZExtValue()))
2070 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2071 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2072 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2073 N->getOperand(0)->getValueType(0),
2077 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2078 EVT VT = N->getValueType(0);
2080 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
2081 unsigned NumElts = VT.getVectorNumElements();
2082 MVT TruncVT = MVT::getIntegerVT(EltSize);
2083 SmallVector<SDValue, 8> Ops;
2084 for (unsigned i = 0; i != NumElts; ++i) {
2085 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2086 const APInt &CInt = C->getAPIntValue();
2087 // Element types smaller than 32 bits are not legal, so use i32 elements.
2088 // The values are implicitly truncated so sext vs. zext doesn't matter.
2089 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2091 return DAG.getNode(ISD::BUILD_VECTOR, dl,
2092 MVT::getVectorVT(TruncVT, NumElts), Ops);
2095 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2096 if (N->getOpcode() == ISD::SIGN_EXTEND)
2098 if (isExtendedBUILD_VECTOR(N, DAG, true))
2103 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2104 if (N->getOpcode() == ISD::ZERO_EXTEND)
2106 if (isExtendedBUILD_VECTOR(N, DAG, false))
2111 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2112 unsigned Opcode = N->getOpcode();
2113 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2114 SDNode *N0 = N->getOperand(0).getNode();
2115 SDNode *N1 = N->getOperand(1).getNode();
2116 return N0->hasOneUse() && N1->hasOneUse() &&
2117 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2122 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2123 unsigned Opcode = N->getOpcode();
2124 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2125 SDNode *N0 = N->getOperand(0).getNode();
2126 SDNode *N1 = N->getOperand(1).getNode();
2127 return N0->hasOneUse() && N1->hasOneUse() &&
2128 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2133 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2134 // Multiplications are only custom-lowered for 128-bit vectors so that
2135 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2136 EVT VT = Op.getValueType();
2137 assert(VT.is128BitVector() && VT.isInteger() &&
2138 "unexpected type for custom-lowering ISD::MUL");
2139 SDNode *N0 = Op.getOperand(0).getNode();
2140 SDNode *N1 = Op.getOperand(1).getNode();
2141 unsigned NewOpc = 0;
2143 bool isN0SExt = isSignExtended(N0, DAG);
2144 bool isN1SExt = isSignExtended(N1, DAG);
2145 if (isN0SExt && isN1SExt)
2146 NewOpc = AArch64ISD::SMULL;
2148 bool isN0ZExt = isZeroExtended(N0, DAG);
2149 bool isN1ZExt = isZeroExtended(N1, DAG);
2150 if (isN0ZExt && isN1ZExt)
2151 NewOpc = AArch64ISD::UMULL;
2152 else if (isN1SExt || isN1ZExt) {
2153 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2154 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2155 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2156 NewOpc = AArch64ISD::SMULL;
2158 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2159 NewOpc = AArch64ISD::UMULL;
2161 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2163 NewOpc = AArch64ISD::UMULL;
2169 if (VT == MVT::v2i64)
2170 // Fall through to expand this. It is not legal.
2173 // Other vector multiplications are legal.
2178 // Legalize to a S/UMULL instruction
2181 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2183 Op0 = skipExtensionForVectorMULL(N0, DAG);
2184 assert(Op0.getValueType().is64BitVector() &&
2185 Op1.getValueType().is64BitVector() &&
2186 "unexpected types for extended operands to VMULL");
2187 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2189 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2190 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2191 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2192 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2193 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2194 EVT Op1VT = Op1.getValueType();
2195 return DAG.getNode(N0->getOpcode(), DL, VT,
2196 DAG.getNode(NewOpc, DL, VT,
2197 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2198 DAG.getNode(NewOpc, DL, VT,
2199 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2202 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2203 SelectionDAG &DAG) const {
2204 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2207 default: return SDValue(); // Don't custom lower most intrinsics.
2208 case Intrinsic::aarch64_thread_pointer: {
2209 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2210 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2212 case Intrinsic::aarch64_neon_smax:
2213 return DAG.getNode(ISD::SMAX, dl, Op.getValueType(),
2214 Op.getOperand(1), Op.getOperand(2));
2215 case Intrinsic::aarch64_neon_umax:
2216 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
2217 Op.getOperand(1), Op.getOperand(2));
2218 case Intrinsic::aarch64_neon_smin:
2219 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(),
2220 Op.getOperand(1), Op.getOperand(2));
2221 case Intrinsic::aarch64_neon_umin:
2222 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(),
2223 Op.getOperand(1), Op.getOperand(2));
2227 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2228 SelectionDAG &DAG) const {
2229 switch (Op.getOpcode()) {
2231 llvm_unreachable("unimplemented operand");
2234 return LowerBITCAST(Op, DAG);
2235 case ISD::GlobalAddress:
2236 return LowerGlobalAddress(Op, DAG);
2237 case ISD::GlobalTLSAddress:
2238 return LowerGlobalTLSAddress(Op, DAG);
2240 return LowerSETCC(Op, DAG);
2242 return LowerBR_CC(Op, DAG);
2244 return LowerSELECT(Op, DAG);
2245 case ISD::SELECT_CC:
2246 return LowerSELECT_CC(Op, DAG);
2247 case ISD::JumpTable:
2248 return LowerJumpTable(Op, DAG);
2249 case ISD::ConstantPool:
2250 return LowerConstantPool(Op, DAG);
2251 case ISD::BlockAddress:
2252 return LowerBlockAddress(Op, DAG);
2254 return LowerVASTART(Op, DAG);
2256 return LowerVACOPY(Op, DAG);
2258 return LowerVAARG(Op, DAG);
2263 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2270 return LowerXALUO(Op, DAG);
2272 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2274 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2276 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2278 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2280 return LowerFP_ROUND(Op, DAG);
2281 case ISD::FP_EXTEND:
2282 return LowerFP_EXTEND(Op, DAG);
2283 case ISD::FRAMEADDR:
2284 return LowerFRAMEADDR(Op, DAG);
2285 case ISD::RETURNADDR:
2286 return LowerRETURNADDR(Op, DAG);
2287 case ISD::INSERT_VECTOR_ELT:
2288 return LowerINSERT_VECTOR_ELT(Op, DAG);
2289 case ISD::EXTRACT_VECTOR_ELT:
2290 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2291 case ISD::BUILD_VECTOR:
2292 return LowerBUILD_VECTOR(Op, DAG);
2293 case ISD::VECTOR_SHUFFLE:
2294 return LowerVECTOR_SHUFFLE(Op, DAG);
2295 case ISD::EXTRACT_SUBVECTOR:
2296 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2300 return LowerVectorSRA_SRL_SHL(Op, DAG);
2301 case ISD::SHL_PARTS:
2302 return LowerShiftLeftParts(Op, DAG);
2303 case ISD::SRL_PARTS:
2304 case ISD::SRA_PARTS:
2305 return LowerShiftRightParts(Op, DAG);
2307 return LowerCTPOP(Op, DAG);
2308 case ISD::FCOPYSIGN:
2309 return LowerFCOPYSIGN(Op, DAG);
2311 return LowerVectorAND(Op, DAG);
2313 return LowerVectorOR(Op, DAG);
2315 return LowerXOR(Op, DAG);
2317 return LowerPREFETCH(Op, DAG);
2318 case ISD::SINT_TO_FP:
2319 case ISD::UINT_TO_FP:
2320 return LowerINT_TO_FP(Op, DAG);
2321 case ISD::FP_TO_SINT:
2322 case ISD::FP_TO_UINT:
2323 return LowerFP_TO_INT(Op, DAG);
2325 return LowerFSINCOS(Op, DAG);
2327 return LowerMUL(Op, DAG);
2328 case ISD::INTRINSIC_WO_CHAIN:
2329 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2333 /// getFunctionAlignment - Return the Log2 alignment of this function.
2334 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2338 //===----------------------------------------------------------------------===//
2339 // Calling Convention Implementation
2340 //===----------------------------------------------------------------------===//
2342 #include "AArch64GenCallingConv.inc"
2344 /// Selects the correct CCAssignFn for a given CallingConvention value.
2345 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2346 bool IsVarArg) const {
2349 llvm_unreachable("Unsupported calling convention.");
2350 case CallingConv::WebKit_JS:
2351 return CC_AArch64_WebKit_JS;
2352 case CallingConv::GHC:
2353 return CC_AArch64_GHC;
2354 case CallingConv::C:
2355 case CallingConv::Fast:
2356 if (!Subtarget->isTargetDarwin())
2357 return CC_AArch64_AAPCS;
2358 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2362 SDValue AArch64TargetLowering::LowerFormalArguments(
2363 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2364 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2365 SmallVectorImpl<SDValue> &InVals) const {
2366 MachineFunction &MF = DAG.getMachineFunction();
2367 MachineFrameInfo *MFI = MF.getFrameInfo();
2369 // Assign locations to all of the incoming arguments.
2370 SmallVector<CCValAssign, 16> ArgLocs;
2371 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2374 // At this point, Ins[].VT may already be promoted to i32. To correctly
2375 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2376 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2377 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2378 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2380 unsigned NumArgs = Ins.size();
2381 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2382 unsigned CurArgIdx = 0;
2383 for (unsigned i = 0; i != NumArgs; ++i) {
2384 MVT ValVT = Ins[i].VT;
2385 if (Ins[i].isOrigArg()) {
2386 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2387 CurArgIdx = Ins[i].getOrigArgIndex();
2389 // Get type of the original argument.
2390 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2391 /*AllowUnknown*/ true);
2392 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2393 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2394 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2396 else if (ActualMVT == MVT::i16)
2399 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2401 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2402 assert(!Res && "Call operand has unhandled type");
2405 assert(ArgLocs.size() == Ins.size());
2406 SmallVector<SDValue, 16> ArgValues;
2407 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2408 CCValAssign &VA = ArgLocs[i];
2410 if (Ins[i].Flags.isByVal()) {
2411 // Byval is used for HFAs in the PCS, but the system should work in a
2412 // non-compliant manner for larger structs.
2413 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2414 int Size = Ins[i].Flags.getByValSize();
2415 unsigned NumRegs = (Size + 7) / 8;
2417 // FIXME: This works on big-endian for composite byvals, which are the common
2418 // case. It should also work for fundamental types too.
2420 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2421 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2422 InVals.push_back(FrameIdxN);
2427 if (VA.isRegLoc()) {
2428 // Arguments stored in registers.
2429 EVT RegVT = VA.getLocVT();
2432 const TargetRegisterClass *RC;
2434 if (RegVT == MVT::i32)
2435 RC = &AArch64::GPR32RegClass;
2436 else if (RegVT == MVT::i64)
2437 RC = &AArch64::GPR64RegClass;
2438 else if (RegVT == MVT::f16)
2439 RC = &AArch64::FPR16RegClass;
2440 else if (RegVT == MVT::f32)
2441 RC = &AArch64::FPR32RegClass;
2442 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2443 RC = &AArch64::FPR64RegClass;
2444 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2445 RC = &AArch64::FPR128RegClass;
2447 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2449 // Transform the arguments in physical registers into virtual ones.
2450 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2451 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2453 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2454 // to 64 bits. Insert an assert[sz]ext to capture this, then
2455 // truncate to the right size.
2456 switch (VA.getLocInfo()) {
2458 llvm_unreachable("Unknown loc info!");
2459 case CCValAssign::Full:
2461 case CCValAssign::BCvt:
2462 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2464 case CCValAssign::AExt:
2465 case CCValAssign::SExt:
2466 case CCValAssign::ZExt:
2467 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2468 // nodes after our lowering.
2469 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2473 InVals.push_back(ArgValue);
2475 } else { // VA.isRegLoc()
2476 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2477 unsigned ArgOffset = VA.getLocMemOffset();
2478 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2480 uint32_t BEAlign = 0;
2481 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2482 !Ins[i].Flags.isInConsecutiveRegs())
2483 BEAlign = 8 - ArgSize;
2485 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2487 // Create load nodes to retrieve arguments from the stack.
2488 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2491 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2492 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2493 MVT MemVT = VA.getValVT();
2495 switch (VA.getLocInfo()) {
2498 case CCValAssign::BCvt:
2499 MemVT = VA.getLocVT();
2501 case CCValAssign::SExt:
2502 ExtType = ISD::SEXTLOAD;
2504 case CCValAssign::ZExt:
2505 ExtType = ISD::ZEXTLOAD;
2507 case CCValAssign::AExt:
2508 ExtType = ISD::EXTLOAD;
2512 ArgValue = DAG.getExtLoad(
2513 ExtType, DL, VA.getLocVT(), Chain, FIN,
2514 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
2515 MemVT, false, false, false, 0);
2517 InVals.push_back(ArgValue);
2523 if (!Subtarget->isTargetDarwin()) {
2524 // The AAPCS variadic function ABI is identical to the non-variadic
2525 // one. As a result there may be more arguments in registers and we should
2526 // save them for future reference.
2527 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2530 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2531 // This will point to the next argument passed via stack.
2532 unsigned StackOffset = CCInfo.getNextStackOffset();
2533 // We currently pass all varargs at 8-byte alignment.
2534 StackOffset = ((StackOffset + 7) & ~7);
2535 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2538 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2539 unsigned StackArgSize = CCInfo.getNextStackOffset();
2540 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2541 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2542 // This is a non-standard ABI so by fiat I say we're allowed to make full
2543 // use of the stack area to be popped, which must be aligned to 16 bytes in
2545 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2547 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2548 // a multiple of 16.
2549 FuncInfo->setArgumentStackToRestore(StackArgSize);
2551 // This realignment carries over to the available bytes below. Our own
2552 // callers will guarantee the space is free by giving an aligned value to
2555 // Even if we're not expected to free up the space, it's useful to know how
2556 // much is there while considering tail calls (because we can reuse it).
2557 FuncInfo->setBytesInStackArgArea(StackArgSize);
2562 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2563 SelectionDAG &DAG, SDLoc DL,
2564 SDValue &Chain) const {
2565 MachineFunction &MF = DAG.getMachineFunction();
2566 MachineFrameInfo *MFI = MF.getFrameInfo();
2567 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2568 auto PtrVT = getPointerTy(DAG.getDataLayout());
2570 SmallVector<SDValue, 8> MemOps;
2572 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2573 AArch64::X3, AArch64::X4, AArch64::X5,
2574 AArch64::X6, AArch64::X7 };
2575 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2576 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2578 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2580 if (GPRSaveSize != 0) {
2581 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2583 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2585 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2586 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2587 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2588 SDValue Store = DAG.getStore(
2589 Val.getValue(1), DL, Val, FIN,
2590 MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 8), false,
2592 MemOps.push_back(Store);
2594 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2597 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2598 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2600 if (Subtarget->hasFPARMv8()) {
2601 static const MCPhysReg FPRArgRegs[] = {
2602 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2603 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2604 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2605 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2607 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2609 if (FPRSaveSize != 0) {
2610 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2612 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2614 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2615 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2616 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2618 SDValue Store = DAG.getStore(
2619 Val.getValue(1), DL, Val, FIN,
2620 MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 16),
2622 MemOps.push_back(Store);
2623 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2624 DAG.getConstant(16, DL, PtrVT));
2627 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2628 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2631 if (!MemOps.empty()) {
2632 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2636 /// LowerCallResult - Lower the result values of a call into the
2637 /// appropriate copies out of appropriate physical registers.
2638 SDValue AArch64TargetLowering::LowerCallResult(
2639 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2640 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2641 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2642 SDValue ThisVal) const {
2643 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2644 ? RetCC_AArch64_WebKit_JS
2645 : RetCC_AArch64_AAPCS;
2646 // Assign locations to each value returned by this call.
2647 SmallVector<CCValAssign, 16> RVLocs;
2648 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2650 CCInfo.AnalyzeCallResult(Ins, RetCC);
2652 // Copy all of the result registers out of their specified physreg.
2653 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2654 CCValAssign VA = RVLocs[i];
2656 // Pass 'this' value directly from the argument to return value, to avoid
2657 // reg unit interference
2658 if (i == 0 && isThisReturn) {
2659 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2660 "unexpected return calling convention register assignment");
2661 InVals.push_back(ThisVal);
2666 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2667 Chain = Val.getValue(1);
2668 InFlag = Val.getValue(2);
2670 switch (VA.getLocInfo()) {
2672 llvm_unreachable("Unknown loc info!");
2673 case CCValAssign::Full:
2675 case CCValAssign::BCvt:
2676 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2680 InVals.push_back(Val);
2686 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2687 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2688 bool isCalleeStructRet, bool isCallerStructRet,
2689 const SmallVectorImpl<ISD::OutputArg> &Outs,
2690 const SmallVectorImpl<SDValue> &OutVals,
2691 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2692 // For CallingConv::C this function knows whether the ABI needs
2693 // changing. That's not true for other conventions so they will have to opt in
2695 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2698 const MachineFunction &MF = DAG.getMachineFunction();
2699 const Function *CallerF = MF.getFunction();
2700 CallingConv::ID CallerCC = CallerF->getCallingConv();
2701 bool CCMatch = CallerCC == CalleeCC;
2703 // Byval parameters hand the function a pointer directly into the stack area
2704 // we want to reuse during a tail call. Working around this *is* possible (see
2705 // X86) but less efficient and uglier in LowerCall.
2706 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2707 e = CallerF->arg_end();
2709 if (i->hasByValAttr())
2712 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2713 if (IsTailCallConvention(CalleeCC) && CCMatch)
2718 // Externally-defined functions with weak linkage should not be
2719 // tail-called on AArch64 when the OS does not support dynamic
2720 // pre-emption of symbols, as the AAELF spec requires normal calls
2721 // to undefined weak functions to be replaced with a NOP or jump to the
2722 // next instruction. The behaviour of branch instructions in this
2723 // situation (as used for tail calls) is implementation-defined, so we
2724 // cannot rely on the linker replacing the tail call with a return.
2725 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2726 const GlobalValue *GV = G->getGlobal();
2727 const Triple &TT = getTargetMachine().getTargetTriple();
2728 if (GV->hasExternalWeakLinkage() &&
2729 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2733 // Now we search for cases where we can use a tail call without changing the
2734 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2737 // I want anyone implementing a new calling convention to think long and hard
2738 // about this assert.
2739 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2740 "Unexpected variadic calling convention");
2742 if (isVarArg && !Outs.empty()) {
2743 // At least two cases here: if caller is fastcc then we can't have any
2744 // memory arguments (we'd be expected to clean up the stack afterwards). If
2745 // caller is C then we could potentially use its argument area.
2747 // FIXME: for now we take the most conservative of these in both cases:
2748 // disallow all variadic memory operands.
2749 SmallVector<CCValAssign, 16> ArgLocs;
2750 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2753 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2754 for (const CCValAssign &ArgLoc : ArgLocs)
2755 if (!ArgLoc.isRegLoc())
2759 // If the calling conventions do not match, then we'd better make sure the
2760 // results are returned in the same way as what the caller expects.
2762 SmallVector<CCValAssign, 16> RVLocs1;
2763 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2765 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2767 SmallVector<CCValAssign, 16> RVLocs2;
2768 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2770 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2772 if (RVLocs1.size() != RVLocs2.size())
2774 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2775 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2777 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2779 if (RVLocs1[i].isRegLoc()) {
2780 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2783 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2789 // Nothing more to check if the callee is taking no arguments
2793 SmallVector<CCValAssign, 16> ArgLocs;
2794 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2797 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2799 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2801 // If the stack arguments for this call would fit into our own save area then
2802 // the call can be made tail.
2803 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2806 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2808 MachineFrameInfo *MFI,
2809 int ClobberedFI) const {
2810 SmallVector<SDValue, 8> ArgChains;
2811 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2812 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2814 // Include the original chain at the beginning of the list. When this is
2815 // used by target LowerCall hooks, this helps legalize find the
2816 // CALLSEQ_BEGIN node.
2817 ArgChains.push_back(Chain);
2819 // Add a chain value for each stack argument corresponding
2820 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2821 UE = DAG.getEntryNode().getNode()->use_end();
2823 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2824 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2825 if (FI->getIndex() < 0) {
2826 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2827 int64_t InLastByte = InFirstByte;
2828 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2830 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2831 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2832 ArgChains.push_back(SDValue(L, 1));
2835 // Build a tokenfactor for all the chains.
2836 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2839 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2840 bool TailCallOpt) const {
2841 return CallCC == CallingConv::Fast && TailCallOpt;
2844 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2845 return CallCC == CallingConv::Fast;
2848 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2849 /// and add input and output parameter nodes.
2851 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2852 SmallVectorImpl<SDValue> &InVals) const {
2853 SelectionDAG &DAG = CLI.DAG;
2855 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2856 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2857 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2858 SDValue Chain = CLI.Chain;
2859 SDValue Callee = CLI.Callee;
2860 bool &IsTailCall = CLI.IsTailCall;
2861 CallingConv::ID CallConv = CLI.CallConv;
2862 bool IsVarArg = CLI.IsVarArg;
2864 MachineFunction &MF = DAG.getMachineFunction();
2865 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2866 bool IsThisReturn = false;
2868 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2869 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2870 bool IsSibCall = false;
2873 // Check if it's really possible to do a tail call.
2874 IsTailCall = isEligibleForTailCallOptimization(
2875 Callee, CallConv, IsVarArg, IsStructRet,
2876 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2877 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2878 report_fatal_error("failed to perform tail call elimination on a call "
2879 "site marked musttail");
2881 // A sibling call is one where we're under the usual C ABI and not planning
2882 // to change that but can still do a tail call:
2883 if (!TailCallOpt && IsTailCall)
2890 // Analyze operands of the call, assigning locations to each operand.
2891 SmallVector<CCValAssign, 16> ArgLocs;
2892 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2896 // Handle fixed and variable vector arguments differently.
2897 // Variable vector arguments always go into memory.
2898 unsigned NumArgs = Outs.size();
2900 for (unsigned i = 0; i != NumArgs; ++i) {
2901 MVT ArgVT = Outs[i].VT;
2902 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2903 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2904 /*IsVarArg=*/ !Outs[i].IsFixed);
2905 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2906 assert(!Res && "Call operand has unhandled type");
2910 // At this point, Outs[].VT may already be promoted to i32. To correctly
2911 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2912 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2913 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2914 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2916 unsigned NumArgs = Outs.size();
2917 for (unsigned i = 0; i != NumArgs; ++i) {
2918 MVT ValVT = Outs[i].VT;
2919 // Get type of the original argument.
2920 EVT ActualVT = getValueType(DAG.getDataLayout(),
2921 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2922 /*AllowUnknown*/ true);
2923 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2924 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2925 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2926 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2928 else if (ActualMVT == MVT::i16)
2931 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2932 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2933 assert(!Res && "Call operand has unhandled type");
2938 // Get a count of how many bytes are to be pushed on the stack.
2939 unsigned NumBytes = CCInfo.getNextStackOffset();
2942 // Since we're not changing the ABI to make this a tail call, the memory
2943 // operands are already available in the caller's incoming argument space.
2947 // FPDiff is the byte offset of the call's argument area from the callee's.
2948 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2949 // by this amount for a tail call. In a sibling call it must be 0 because the
2950 // caller will deallocate the entire stack and the callee still expects its
2951 // arguments to begin at SP+0. Completely unused for non-tail calls.
2954 if (IsTailCall && !IsSibCall) {
2955 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2957 // Since callee will pop argument stack as a tail call, we must keep the
2958 // popped size 16-byte aligned.
2959 NumBytes = RoundUpToAlignment(NumBytes, 16);
2961 // FPDiff will be negative if this tail call requires more space than we
2962 // would automatically have in our incoming argument space. Positive if we
2963 // can actually shrink the stack.
2964 FPDiff = NumReusableBytes - NumBytes;
2966 // The stack pointer must be 16-byte aligned at all times it's used for a
2967 // memory operation, which in practice means at *all* times and in
2968 // particular across call boundaries. Therefore our own arguments started at
2969 // a 16-byte aligned SP and the delta applied for the tail call should
2970 // satisfy the same constraint.
2971 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2974 // Adjust the stack pointer for the new arguments...
2975 // These operations are automatically eliminated by the prolog/epilog pass
2977 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2981 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
2982 getPointerTy(DAG.getDataLayout()));
2984 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2985 SmallVector<SDValue, 8> MemOpChains;
2986 auto PtrVT = getPointerTy(DAG.getDataLayout());
2988 // Walk the register/memloc assignments, inserting copies/loads.
2989 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2990 ++i, ++realArgIdx) {
2991 CCValAssign &VA = ArgLocs[i];
2992 SDValue Arg = OutVals[realArgIdx];
2993 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2995 // Promote the value if needed.
2996 switch (VA.getLocInfo()) {
2998 llvm_unreachable("Unknown loc info!");
2999 case CCValAssign::Full:
3001 case CCValAssign::SExt:
3002 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
3004 case CCValAssign::ZExt:
3005 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3007 case CCValAssign::AExt:
3008 if (Outs[realArgIdx].ArgVT == MVT::i1) {
3009 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
3010 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3011 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
3013 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
3015 case CCValAssign::BCvt:
3016 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3018 case CCValAssign::FPExt:
3019 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
3023 if (VA.isRegLoc()) {
3024 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
3025 assert(VA.getLocVT() == MVT::i64 &&
3026 "unexpected calling convention register assignment");
3027 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
3028 "unexpected use of 'returned'");
3029 IsThisReturn = true;
3031 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3033 assert(VA.isMemLoc());
3036 MachinePointerInfo DstInfo;
3038 // FIXME: This works on big-endian for composite byvals, which are the
3039 // common case. It should also work for fundamental types too.
3040 uint32_t BEAlign = 0;
3041 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
3042 : VA.getValVT().getSizeInBits();
3043 OpSize = (OpSize + 7) / 8;
3044 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
3045 !Flags.isInConsecutiveRegs()) {
3047 BEAlign = 8 - OpSize;
3049 unsigned LocMemOffset = VA.getLocMemOffset();
3050 int32_t Offset = LocMemOffset + BEAlign;
3051 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3052 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3055 Offset = Offset + FPDiff;
3056 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3058 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3060 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
3062 // Make sure any stack arguments overlapping with where we're storing
3063 // are loaded before this eventual operation. Otherwise they'll be
3065 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3067 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3069 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3070 DstInfo = MachinePointerInfo::getStack(DAG.getMachineFunction(),
3074 if (Outs[i].Flags.isByVal()) {
3076 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3077 SDValue Cpy = DAG.getMemcpy(
3078 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3079 /*isVol = */ false, /*AlwaysInline = */ false,
3080 /*isTailCall = */ false,
3081 DstInfo, MachinePointerInfo());
3083 MemOpChains.push_back(Cpy);
3085 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3086 // promoted to a legal register type i32, we should truncate Arg back to
3088 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3089 VA.getValVT() == MVT::i16)
3090 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3093 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
3094 MemOpChains.push_back(Store);
3099 if (!MemOpChains.empty())
3100 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3102 // Build a sequence of copy-to-reg nodes chained together with token chain
3103 // and flag operands which copy the outgoing args into the appropriate regs.
3105 for (auto &RegToPass : RegsToPass) {
3106 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3107 RegToPass.second, InFlag);
3108 InFlag = Chain.getValue(1);
3111 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3112 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3113 // node so that legalize doesn't hack it.
3114 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3115 Subtarget->isTargetMachO()) {
3116 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3117 const GlobalValue *GV = G->getGlobal();
3118 bool InternalLinkage = GV->hasInternalLinkage();
3119 if (InternalLinkage)
3120 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3123 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3124 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3126 } else if (ExternalSymbolSDNode *S =
3127 dyn_cast<ExternalSymbolSDNode>(Callee)) {
3128 const char *Sym = S->getSymbol();
3129 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3130 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3132 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3133 const GlobalValue *GV = G->getGlobal();
3134 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3135 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3136 const char *Sym = S->getSymbol();
3137 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3140 // We don't usually want to end the call-sequence here because we would tidy
3141 // the frame up *after* the call, however in the ABI-changing tail-call case
3142 // we've carefully laid out the parameters so that when sp is reset they'll be
3143 // in the correct location.
3144 if (IsTailCall && !IsSibCall) {
3145 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3146 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3147 InFlag = Chain.getValue(1);
3150 std::vector<SDValue> Ops;
3151 Ops.push_back(Chain);
3152 Ops.push_back(Callee);
3155 // Each tail call may have to adjust the stack by a different amount, so
3156 // this information must travel along with the operation for eventual
3157 // consumption by emitEpilogue.
3158 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3161 // Add argument registers to the end of the list so that they are known live
3163 for (auto &RegToPass : RegsToPass)
3164 Ops.push_back(DAG.getRegister(RegToPass.first,
3165 RegToPass.second.getValueType()));
3167 // Add a register mask operand representing the call-preserved registers.
3168 const uint32_t *Mask;
3169 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3171 // For 'this' returns, use the X0-preserving mask if applicable
3172 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3174 IsThisReturn = false;
3175 Mask = TRI->getCallPreservedMask(MF, CallConv);
3178 Mask = TRI->getCallPreservedMask(MF, CallConv);
3180 assert(Mask && "Missing call preserved mask for calling convention");
3181 Ops.push_back(DAG.getRegisterMask(Mask));
3183 if (InFlag.getNode())
3184 Ops.push_back(InFlag);
3186 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3188 // If we're doing a tall call, use a TC_RETURN here rather than an
3189 // actual call instruction.
3191 MF.getFrameInfo()->setHasTailCall();
3192 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3195 // Returns a chain and a flag for retval copy to use.
3196 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3197 InFlag = Chain.getValue(1);
3199 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
3200 ? RoundUpToAlignment(NumBytes, 16)
3203 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3204 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3207 InFlag = Chain.getValue(1);
3209 // Handle result values, copying them out of physregs into vregs that we
3211 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3212 InVals, IsThisReturn,
3213 IsThisReturn ? OutVals[0] : SDValue());
3216 bool AArch64TargetLowering::CanLowerReturn(
3217 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3218 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3219 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3220 ? RetCC_AArch64_WebKit_JS
3221 : RetCC_AArch64_AAPCS;
3222 SmallVector<CCValAssign, 16> RVLocs;
3223 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3224 return CCInfo.CheckReturn(Outs, RetCC);
3228 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3230 const SmallVectorImpl<ISD::OutputArg> &Outs,
3231 const SmallVectorImpl<SDValue> &OutVals,
3232 SDLoc DL, SelectionDAG &DAG) const {
3233 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3234 ? RetCC_AArch64_WebKit_JS
3235 : RetCC_AArch64_AAPCS;
3236 SmallVector<CCValAssign, 16> RVLocs;
3237 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3239 CCInfo.AnalyzeReturn(Outs, RetCC);
3241 // Copy the result values into the output registers.
3243 SmallVector<SDValue, 4> RetOps(1, Chain);
3244 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3245 ++i, ++realRVLocIdx) {
3246 CCValAssign &VA = RVLocs[i];
3247 assert(VA.isRegLoc() && "Can only return in registers!");
3248 SDValue Arg = OutVals[realRVLocIdx];
3250 switch (VA.getLocInfo()) {
3252 llvm_unreachable("Unknown loc info!");
3253 case CCValAssign::Full:
3254 if (Outs[i].ArgVT == MVT::i1) {
3255 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3256 // value. This is strictly redundant on Darwin (which uses "zeroext
3257 // i1"), but will be optimised out before ISel.
3258 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3259 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3262 case CCValAssign::BCvt:
3263 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3267 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3268 Flag = Chain.getValue(1);
3269 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3272 RetOps[0] = Chain; // Update chain.
3274 // Add the flag if we have it.
3276 RetOps.push_back(Flag);
3278 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3281 //===----------------------------------------------------------------------===//
3282 // Other Lowering Code
3283 //===----------------------------------------------------------------------===//
3285 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3286 SelectionDAG &DAG) const {
3287 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3289 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3290 const GlobalValue *GV = GN->getGlobal();
3291 unsigned char OpFlags =
3292 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3294 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
3295 "unexpected offset in global node");
3297 // This also catched the large code model case for Darwin.
3298 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3299 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
3300 // FIXME: Once remat is capable of dealing with instructions with register
3301 // operands, expand this into two nodes instead of using a wrapper node.
3302 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3305 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
3306 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3307 "use of MO_CONSTPOOL only supported on small model");
3308 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3309 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3310 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3311 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3312 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3313 SDValue GlobalAddr = DAG.getLoad(
3314 PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3315 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
3316 /*isVolatile=*/false,
3317 /*isNonTemporal=*/true,
3318 /*isInvariant=*/true, 8);
3319 if (GN->getOffset() != 0)
3320 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3321 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3325 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3326 const unsigned char MO_NC = AArch64II::MO_NC;
3328 AArch64ISD::WrapperLarge, DL, PtrVT,
3329 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3330 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3331 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3332 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3334 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3335 // the only correct model on Darwin.
3336 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3337 OpFlags | AArch64II::MO_PAGE);
3338 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3339 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3341 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3342 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3346 /// \brief Convert a TLS address reference into the correct sequence of loads
3347 /// and calls to compute the variable's address (for Darwin, currently) and
3348 /// return an SDValue containing the final node.
3350 /// Darwin only has one TLS scheme which must be capable of dealing with the
3351 /// fully general situation, in the worst case. This means:
3352 /// + "extern __thread" declaration.
3353 /// + Defined in a possibly unknown dynamic library.
3355 /// The general system is that each __thread variable has a [3 x i64] descriptor
3356 /// which contains information used by the runtime to calculate the address. The
3357 /// only part of this the compiler needs to know about is the first xword, which
3358 /// contains a function pointer that must be called with the address of the
3359 /// entire descriptor in "x0".
3361 /// Since this descriptor may be in a different unit, in general even the
3362 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3364 /// adrp x0, _var@TLVPPAGE
3365 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3366 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3367 /// ; the function pointer
3368 /// blr x1 ; Uses descriptor address in x0
3369 /// ; Address of _var is now in x0.
3371 /// If the address of _var's descriptor *is* known to the linker, then it can
3372 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3373 /// a slight efficiency gain.
3375 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3376 SelectionDAG &DAG) const {
3377 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3380 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3381 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3384 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3385 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3387 // The first entry in the descriptor is a function pointer that we must call
3388 // to obtain the address of the variable.
3389 SDValue Chain = DAG.getEntryNode();
3390 SDValue FuncTLVGet =
3391 DAG.getLoad(MVT::i64, DL, Chain, DescAddr,
3392 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false,
3394 Chain = FuncTLVGet.getValue(1);
3396 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3397 MFI->setAdjustsStack(true);
3399 // TLS calls preserve all registers except those that absolutely must be
3400 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3402 const uint32_t *Mask =
3403 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3405 // Finally, we can make the call. This is just a degenerate version of a
3406 // normal AArch64 call node: x0 takes the address of the descriptor, and
3407 // returns the address of the variable in this thread.
3408 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3410 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3411 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3412 DAG.getRegisterMask(Mask), Chain.getValue(1));
3413 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3416 /// When accessing thread-local variables under either the general-dynamic or
3417 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3418 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3419 /// is a function pointer to carry out the resolution.
3421 /// The sequence is:
3422 /// adrp x0, :tlsdesc:var
3423 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3424 /// add x0, x0, #:tlsdesc_lo12:var
3425 /// .tlsdesccall var
3427 /// (TPIDR_EL0 offset now in x0)
3429 /// The above sequence must be produced unscheduled, to enable the linker to
3430 /// optimize/relax this sequence.
3431 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3432 /// above sequence, and expanded really late in the compilation flow, to ensure
3433 /// the sequence is produced as per above.
3434 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3435 SelectionDAG &DAG) const {
3436 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3438 SDValue Chain = DAG.getEntryNode();
3439 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3441 SmallVector<SDValue, 2> Ops;
3442 Ops.push_back(Chain);
3443 Ops.push_back(SymAddr);
3445 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3446 SDValue Glue = Chain.getValue(1);
3448 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3452 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3453 SelectionDAG &DAG) const {
3454 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3455 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3456 "ELF TLS only supported in small memory model");
3457 // Different choices can be made for the maximum size of the TLS area for a
3458 // module. For the small address model, the default TLS size is 16MiB and the
3459 // maximum TLS size is 4GiB.
3460 // FIXME: add -mtls-size command line option and make it control the 16MiB
3461 // vs. 4GiB code sequence generation.
3462 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3464 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3466 if (DAG.getTarget().Options.EmulatedTLS)
3467 return LowerToTLSEmulatedModel(GA, DAG);
3469 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3470 if (Model == TLSModel::LocalDynamic)
3471 Model = TLSModel::GeneralDynamic;
3475 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3477 const GlobalValue *GV = GA->getGlobal();
3479 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3481 if (Model == TLSModel::LocalExec) {
3482 SDValue HiVar = DAG.getTargetGlobalAddress(
3483 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3484 SDValue LoVar = DAG.getTargetGlobalAddress(
3486 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3488 SDValue TPWithOff_lo =
3489 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3491 DAG.getTargetConstant(0, DL, MVT::i32)),
3494 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3496 DAG.getTargetConstant(0, DL, MVT::i32)),
3499 } else if (Model == TLSModel::InitialExec) {
3500 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3501 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3502 } else if (Model == TLSModel::LocalDynamic) {
3503 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3504 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3505 // the beginning of the module's TLS region, followed by a DTPREL offset
3508 // These accesses will need deduplicating if there's more than one.
3509 AArch64FunctionInfo *MFI =
3510 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3511 MFI->incNumLocalDynamicTLSAccesses();
3513 // The call needs a relocation too for linker relaxation. It doesn't make
3514 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3516 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3519 // Now we can calculate the offset from TPIDR_EL0 to this module's
3520 // thread-local area.
3521 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3523 // Now use :dtprel_whatever: operations to calculate this variable's offset
3524 // in its thread-storage area.
3525 SDValue HiVar = DAG.getTargetGlobalAddress(
3526 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3527 SDValue LoVar = DAG.getTargetGlobalAddress(
3528 GV, DL, MVT::i64, 0,
3529 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3531 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3532 DAG.getTargetConstant(0, DL, MVT::i32)),
3534 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3535 DAG.getTargetConstant(0, DL, MVT::i32)),
3537 } else if (Model == TLSModel::GeneralDynamic) {
3538 // The call needs a relocation too for linker relaxation. It doesn't make
3539 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3542 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3544 // Finally we can make a call to calculate the offset from tpidr_el0.
3545 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3547 llvm_unreachable("Unsupported ELF TLS access model");
3549 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3552 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3553 SelectionDAG &DAG) const {
3554 if (Subtarget->isTargetDarwin())
3555 return LowerDarwinGlobalTLSAddress(Op, DAG);
3556 else if (Subtarget->isTargetELF())
3557 return LowerELFGlobalTLSAddress(Op, DAG);
3559 llvm_unreachable("Unexpected platform trying to use TLS");
3561 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3562 SDValue Chain = Op.getOperand(0);
3563 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3564 SDValue LHS = Op.getOperand(2);
3565 SDValue RHS = Op.getOperand(3);
3566 SDValue Dest = Op.getOperand(4);
3569 // Handle f128 first, since lowering it will result in comparing the return
3570 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3571 // is expecting to deal with.
3572 if (LHS.getValueType() == MVT::f128) {
3573 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3575 // If softenSetCCOperands returned a scalar, we need to compare the result
3576 // against zero to select between true and false values.
3577 if (!RHS.getNode()) {
3578 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3583 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3585 unsigned Opc = LHS.getOpcode();
3586 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3587 cast<ConstantSDNode>(RHS)->isOne() &&
3588 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3589 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3590 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3591 "Unexpected condition code.");
3592 // Only lower legal XALUO ops.
3593 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3596 // The actual operation with overflow check.
3597 AArch64CC::CondCode OFCC;
3598 SDValue Value, Overflow;
3599 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3601 if (CC == ISD::SETNE)
3602 OFCC = getInvertedCondCode(OFCC);
3603 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3605 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3609 if (LHS.getValueType().isInteger()) {
3610 assert((LHS.getValueType() == RHS.getValueType()) &&
3611 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3613 // If the RHS of the comparison is zero, we can potentially fold this
3614 // to a specialized branch.
3615 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3616 if (RHSC && RHSC->getZExtValue() == 0) {
3617 if (CC == ISD::SETEQ) {
3618 // See if we can use a TBZ to fold in an AND as well.
3619 // TBZ has a smaller branch displacement than CBZ. If the offset is
3620 // out of bounds, a late MI-layer pass rewrites branches.
3621 // 403.gcc is an example that hits this case.
3622 if (LHS.getOpcode() == ISD::AND &&
3623 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3624 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3625 SDValue Test = LHS.getOperand(0);
3626 uint64_t Mask = LHS.getConstantOperandVal(1);
3627 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3628 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3632 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3633 } else if (CC == ISD::SETNE) {
3634 // See if we can use a TBZ to fold in an AND as well.
3635 // TBZ has a smaller branch displacement than CBZ. If the offset is
3636 // out of bounds, a late MI-layer pass rewrites branches.
3637 // 403.gcc is an example that hits this case.
3638 if (LHS.getOpcode() == ISD::AND &&
3639 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3640 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3641 SDValue Test = LHS.getOperand(0);
3642 uint64_t Mask = LHS.getConstantOperandVal(1);
3643 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3644 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3648 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3649 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3650 // Don't combine AND since emitComparison converts the AND to an ANDS
3651 // (a.k.a. TST) and the test in the test bit and branch instruction
3652 // becomes redundant. This would also increase register pressure.
3653 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3654 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3655 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3658 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3659 LHS.getOpcode() != ISD::AND) {
3660 // Don't combine AND since emitComparison converts the AND to an ANDS
3661 // (a.k.a. TST) and the test in the test bit and branch instruction
3662 // becomes redundant. This would also increase register pressure.
3663 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3664 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3665 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3669 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3670 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3674 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3676 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3677 // clean. Some of them require two branches to implement.
3678 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3679 AArch64CC::CondCode CC1, CC2;
3680 changeFPCCToAArch64CC(CC, CC1, CC2);
3681 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3683 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3684 if (CC2 != AArch64CC::AL) {
3685 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3686 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3693 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3694 SelectionDAG &DAG) const {
3695 EVT VT = Op.getValueType();
3698 SDValue In1 = Op.getOperand(0);
3699 SDValue In2 = Op.getOperand(1);
3700 EVT SrcVT = In2.getValueType();
3702 if (SrcVT.bitsLT(VT))
3703 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3704 else if (SrcVT.bitsGT(VT))
3705 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL));
3710 SDValue VecVal1, VecVal2;
3711 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3713 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
3714 EltMask = 0x80000000ULL;
3716 if (!VT.isVector()) {
3717 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3718 DAG.getUNDEF(VecVT), In1);
3719 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3720 DAG.getUNDEF(VecVT), In2);
3722 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3723 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3725 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3729 // We want to materialize a mask with the high bit set, but the AdvSIMD
3730 // immediate moves cannot materialize that in a single instruction for
3731 // 64-bit elements. Instead, materialize zero and then negate it.
3734 if (!VT.isVector()) {
3735 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3736 DAG.getUNDEF(VecVT), In1);
3737 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3738 DAG.getUNDEF(VecVT), In2);
3740 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3741 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3744 llvm_unreachable("Invalid type for copysign!");
3747 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3749 // If we couldn't materialize the mask above, then the mask vector will be
3750 // the zero vector, and we need to negate it here.
3751 if (VT == MVT::f64 || VT == MVT::v2f64) {
3752 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3753 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3754 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3758 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3761 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3762 else if (VT == MVT::f64)
3763 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3765 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3768 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3769 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3770 Attribute::NoImplicitFloat))
3773 if (!Subtarget->hasNEON())
3776 // While there is no integer popcount instruction, it can
3777 // be more efficiently lowered to the following sequence that uses
3778 // AdvSIMD registers/instructions as long as the copies to/from
3779 // the AdvSIMD registers are cheap.
3780 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3781 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3782 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3783 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3784 SDValue Val = Op.getOperand(0);
3786 EVT VT = Op.getValueType();
3789 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3790 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3792 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3793 SDValue UaddLV = DAG.getNode(
3794 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3795 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3798 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3802 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3804 if (Op.getValueType().isVector())
3805 return LowerVSETCC(Op, DAG);
3807 SDValue LHS = Op.getOperand(0);
3808 SDValue RHS = Op.getOperand(1);
3809 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3812 // We chose ZeroOrOneBooleanContents, so use zero and one.
3813 EVT VT = Op.getValueType();
3814 SDValue TVal = DAG.getConstant(1, dl, VT);
3815 SDValue FVal = DAG.getConstant(0, dl, VT);
3817 // Handle f128 first, since one possible outcome is a normal integer
3818 // comparison which gets picked up by the next if statement.
3819 if (LHS.getValueType() == MVT::f128) {
3820 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3822 // If softenSetCCOperands returned a scalar, use it.
3823 if (!RHS.getNode()) {
3824 assert(LHS.getValueType() == Op.getValueType() &&
3825 "Unexpected setcc expansion!");
3830 if (LHS.getValueType().isInteger()) {
3833 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3835 // Note that we inverted the condition above, so we reverse the order of
3836 // the true and false operands here. This will allow the setcc to be
3837 // matched to a single CSINC instruction.
3838 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3841 // Now we know we're dealing with FP values.
3842 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3844 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3845 // and do the comparison.
3846 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3848 AArch64CC::CondCode CC1, CC2;
3849 changeFPCCToAArch64CC(CC, CC1, CC2);
3850 if (CC2 == AArch64CC::AL) {
3851 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3852 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3854 // Note that we inverted the condition above, so we reverse the order of
3855 // the true and false operands here. This will allow the setcc to be
3856 // matched to a single CSINC instruction.
3857 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3859 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3860 // totally clean. Some of them require two CSELs to implement. As is in
3861 // this case, we emit the first CSEL and then emit a second using the output
3862 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3864 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3865 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3867 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3869 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3870 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3874 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3875 SDValue RHS, SDValue TVal,
3876 SDValue FVal, SDLoc dl,
3877 SelectionDAG &DAG) const {
3878 // Handle f128 first, because it will result in a comparison of some RTLIB
3879 // call result against zero.
3880 if (LHS.getValueType() == MVT::f128) {
3881 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3883 // If softenSetCCOperands returned a scalar, we need to compare the result
3884 // against zero to select between true and false values.
3885 if (!RHS.getNode()) {
3886 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3891 // Handle integers first.
3892 if (LHS.getValueType().isInteger()) {
3893 assert((LHS.getValueType() == RHS.getValueType()) &&
3894 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3896 unsigned Opcode = AArch64ISD::CSEL;
3898 // If both the TVal and the FVal are constants, see if we can swap them in
3899 // order to for a CSINV or CSINC out of them.
3900 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3901 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3903 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3904 std::swap(TVal, FVal);
3905 std::swap(CTVal, CFVal);
3906 CC = ISD::getSetCCInverse(CC, true);
3907 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3908 std::swap(TVal, FVal);
3909 std::swap(CTVal, CFVal);
3910 CC = ISD::getSetCCInverse(CC, true);
3911 } else if (TVal.getOpcode() == ISD::XOR) {
3912 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3913 // with a CSINV rather than a CSEL.
3914 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3916 if (CVal && CVal->isAllOnesValue()) {
3917 std::swap(TVal, FVal);
3918 std::swap(CTVal, CFVal);
3919 CC = ISD::getSetCCInverse(CC, true);
3921 } else if (TVal.getOpcode() == ISD::SUB) {
3922 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3923 // that we can match with a CSNEG rather than a CSEL.
3924 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3926 if (CVal && CVal->isNullValue()) {
3927 std::swap(TVal, FVal);
3928 std::swap(CTVal, CFVal);
3929 CC = ISD::getSetCCInverse(CC, true);
3931 } else if (CTVal && CFVal) {
3932 const int64_t TrueVal = CTVal->getSExtValue();
3933 const int64_t FalseVal = CFVal->getSExtValue();
3936 // If both TVal and FVal are constants, see if FVal is the
3937 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3938 // instead of a CSEL in that case.
3939 if (TrueVal == ~FalseVal) {
3940 Opcode = AArch64ISD::CSINV;
3941 } else if (TrueVal == -FalseVal) {
3942 Opcode = AArch64ISD::CSNEG;
3943 } else if (TVal.getValueType() == MVT::i32) {
3944 // If our operands are only 32-bit wide, make sure we use 32-bit
3945 // arithmetic for the check whether we can use CSINC. This ensures that
3946 // the addition in the check will wrap around properly in case there is
3947 // an overflow (which would not be the case if we do the check with
3948 // 64-bit arithmetic).
3949 const uint32_t TrueVal32 = CTVal->getZExtValue();
3950 const uint32_t FalseVal32 = CFVal->getZExtValue();
3952 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3953 Opcode = AArch64ISD::CSINC;
3955 if (TrueVal32 > FalseVal32) {
3959 // 64-bit check whether we can use CSINC.
3960 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3961 Opcode = AArch64ISD::CSINC;
3963 if (TrueVal > FalseVal) {
3968 // Swap TVal and FVal if necessary.
3970 std::swap(TVal, FVal);
3971 std::swap(CTVal, CFVal);
3972 CC = ISD::getSetCCInverse(CC, true);
3975 if (Opcode != AArch64ISD::CSEL) {
3976 // Drop FVal since we can get its value by simply inverting/negating
3983 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3985 EVT VT = TVal.getValueType();
3986 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3989 // Now we know we're dealing with FP values.
3990 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3991 assert(LHS.getValueType() == RHS.getValueType());
3992 EVT VT = TVal.getValueType();
3993 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3995 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3996 // clean. Some of them require two CSELs to implement.
3997 AArch64CC::CondCode CC1, CC2;
3998 changeFPCCToAArch64CC(CC, CC1, CC2);
3999 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
4000 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4002 // If we need a second CSEL, emit it, using the output of the first as the
4003 // RHS. We're effectively OR'ing the two CC's together.
4004 if (CC2 != AArch64CC::AL) {
4005 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
4006 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4009 // Otherwise, return the output of the first CSEL.
4013 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
4014 SelectionDAG &DAG) const {
4015 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4016 SDValue LHS = Op.getOperand(0);
4017 SDValue RHS = Op.getOperand(1);
4018 SDValue TVal = Op.getOperand(2);
4019 SDValue FVal = Op.getOperand(3);
4021 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4024 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
4025 SelectionDAG &DAG) const {
4026 SDValue CCVal = Op->getOperand(0);
4027 SDValue TVal = Op->getOperand(1);
4028 SDValue FVal = Op->getOperand(2);
4031 unsigned Opc = CCVal.getOpcode();
4032 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4034 if (CCVal.getResNo() == 1 &&
4035 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4036 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4037 // Only lower legal XALUO ops.
4038 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4041 AArch64CC::CondCode OFCC;
4042 SDValue Value, Overflow;
4043 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4044 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4046 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4050 // Lower it the same way as we would lower a SELECT_CC node.
4053 if (CCVal.getOpcode() == ISD::SETCC) {
4054 LHS = CCVal.getOperand(0);
4055 RHS = CCVal.getOperand(1);
4056 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4059 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4062 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4065 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4066 SelectionDAG &DAG) const {
4067 // Jump table entries as PC relative offsets. No additional tweaking
4068 // is necessary here. Just get the address of the jump table.
4069 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4070 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4073 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4074 !Subtarget->isTargetMachO()) {
4075 const unsigned char MO_NC = AArch64II::MO_NC;
4077 AArch64ISD::WrapperLarge, DL, PtrVT,
4078 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
4079 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
4080 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
4081 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4082 AArch64II::MO_G0 | MO_NC));
4086 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
4087 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4088 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4089 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4090 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4093 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4094 SelectionDAG &DAG) const {
4095 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4096 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4099 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4100 // Use the GOT for the large code model on iOS.
4101 if (Subtarget->isTargetMachO()) {
4102 SDValue GotAddr = DAG.getTargetConstantPool(
4103 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4105 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
4108 const unsigned char MO_NC = AArch64II::MO_NC;
4110 AArch64ISD::WrapperLarge, DL, PtrVT,
4111 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4112 CP->getOffset(), AArch64II::MO_G3),
4113 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4114 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
4115 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4116 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
4117 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4118 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
4120 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4121 // ELF, the only valid one on Darwin.
4123 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4124 CP->getOffset(), AArch64II::MO_PAGE);
4125 SDValue Lo = DAG.getTargetConstantPool(
4126 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4127 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4129 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4130 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4134 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4135 SelectionDAG &DAG) const {
4136 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4137 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4139 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4140 !Subtarget->isTargetMachO()) {
4141 const unsigned char MO_NC = AArch64II::MO_NC;
4143 AArch64ISD::WrapperLarge, DL, PtrVT,
4144 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
4145 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
4146 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
4147 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
4149 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
4150 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
4152 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4153 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4157 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4158 SelectionDAG &DAG) const {
4159 AArch64FunctionInfo *FuncInfo =
4160 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4163 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4164 getPointerTy(DAG.getDataLayout()));
4165 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4166 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4167 MachinePointerInfo(SV), false, false, 0);
4170 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4171 SelectionDAG &DAG) const {
4172 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4173 // Standard, section B.3.
4174 MachineFunction &MF = DAG.getMachineFunction();
4175 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4176 auto PtrVT = getPointerTy(DAG.getDataLayout());
4179 SDValue Chain = Op.getOperand(0);
4180 SDValue VAList = Op.getOperand(1);
4181 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4182 SmallVector<SDValue, 4> MemOps;
4184 // void *__stack at offset 0
4185 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4186 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4187 MachinePointerInfo(SV), false, false, 8));
4189 // void *__gr_top at offset 8
4190 int GPRSize = FuncInfo->getVarArgsGPRSize();
4192 SDValue GRTop, GRTopAddr;
4195 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4197 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4198 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4199 DAG.getConstant(GPRSize, DL, PtrVT));
4201 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4202 MachinePointerInfo(SV, 8), false, false, 8));
4205 // void *__vr_top at offset 16
4206 int FPRSize = FuncInfo->getVarArgsFPRSize();
4208 SDValue VRTop, VRTopAddr;
4209 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4210 DAG.getConstant(16, DL, PtrVT));
4212 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4213 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4214 DAG.getConstant(FPRSize, DL, PtrVT));
4216 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4217 MachinePointerInfo(SV, 16), false, false, 8));
4220 // int __gr_offs at offset 24
4221 SDValue GROffsAddr =
4222 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4223 MemOps.push_back(DAG.getStore(Chain, DL,
4224 DAG.getConstant(-GPRSize, DL, MVT::i32),
4225 GROffsAddr, MachinePointerInfo(SV, 24), false,
4228 // int __vr_offs at offset 28
4229 SDValue VROffsAddr =
4230 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4231 MemOps.push_back(DAG.getStore(Chain, DL,
4232 DAG.getConstant(-FPRSize, DL, MVT::i32),
4233 VROffsAddr, MachinePointerInfo(SV, 28), false,
4236 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4239 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4240 SelectionDAG &DAG) const {
4241 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
4242 : LowerAAPCS_VASTART(Op, DAG);
4245 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4246 SelectionDAG &DAG) const {
4247 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4250 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
4251 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4252 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4254 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4256 DAG.getConstant(VaListSize, DL, MVT::i32),
4257 8, false, false, false, MachinePointerInfo(DestSV),
4258 MachinePointerInfo(SrcSV));
4261 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4262 assert(Subtarget->isTargetDarwin() &&
4263 "automatic va_arg instruction only works on Darwin");
4265 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4266 EVT VT = Op.getValueType();
4268 SDValue Chain = Op.getOperand(0);
4269 SDValue Addr = Op.getOperand(1);
4270 unsigned Align = Op.getConstantOperandVal(3);
4271 auto PtrVT = getPointerTy(DAG.getDataLayout());
4273 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V),
4274 false, false, false, 0);
4275 Chain = VAList.getValue(1);
4278 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4279 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4280 DAG.getConstant(Align - 1, DL, PtrVT));
4281 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4282 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4285 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4286 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4288 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4289 // up to 64 bits. At the very least, we have to increase the striding of the
4290 // vaargs list to match this, and for FP values we need to introduce
4291 // FP_ROUND nodes as well.
4292 if (VT.isInteger() && !VT.isVector())
4294 bool NeedFPTrunc = false;
4295 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4300 // Increment the pointer, VAList, to the next vaarg
4301 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4302 DAG.getConstant(ArgSize, DL, PtrVT));
4303 // Store the incremented VAList to the legalized pointer
4304 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4307 // Load the actual argument out of the pointer VAList
4309 // Load the value as an f64.
4310 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4311 MachinePointerInfo(), false, false, false, 0);
4312 // Round the value down to an f32.
4313 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4314 DAG.getIntPtrConstant(1, DL));
4315 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4316 // Merge the rounded value with the chain output of the load.
4317 return DAG.getMergeValues(Ops, DL);
4320 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4324 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4325 SelectionDAG &DAG) const {
4326 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4327 MFI->setFrameAddressIsTaken(true);
4329 EVT VT = Op.getValueType();
4331 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4333 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4335 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4336 MachinePointerInfo(), false, false, false, 0);
4340 // FIXME? Maybe this could be a TableGen attribute on some registers and
4341 // this table could be generated automatically from RegInfo.
4342 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4343 SelectionDAG &DAG) const {
4344 unsigned Reg = StringSwitch<unsigned>(RegName)
4345 .Case("sp", AArch64::SP)
4349 report_fatal_error(Twine("Invalid register name \""
4350 + StringRef(RegName) + "\"."));
4353 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4354 SelectionDAG &DAG) const {
4355 MachineFunction &MF = DAG.getMachineFunction();
4356 MachineFrameInfo *MFI = MF.getFrameInfo();
4357 MFI->setReturnAddressIsTaken(true);
4359 EVT VT = Op.getValueType();
4361 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4363 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4364 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4365 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4366 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4367 MachinePointerInfo(), false, false, false, 0);
4370 // Return LR, which contains the return address. Mark it an implicit live-in.
4371 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4372 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4375 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4376 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4377 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4378 SelectionDAG &DAG) const {
4379 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4380 EVT VT = Op.getValueType();
4381 unsigned VTBits = VT.getSizeInBits();
4383 SDValue ShOpLo = Op.getOperand(0);
4384 SDValue ShOpHi = Op.getOperand(1);
4385 SDValue ShAmt = Op.getOperand(2);
4387 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4389 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4391 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4392 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4393 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4394 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4395 DAG.getConstant(VTBits, dl, MVT::i64));
4396 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4398 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4399 ISD::SETGE, dl, DAG);
4400 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4402 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4403 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4405 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4407 // AArch64 shifts larger than the register width are wrapped rather than
4408 // clamped, so we can't just emit "hi >> x".
4409 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4410 SDValue TrueValHi = Opc == ISD::SRA
4411 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4412 DAG.getConstant(VTBits - 1, dl,
4414 : DAG.getConstant(0, dl, VT);
4416 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4418 SDValue Ops[2] = { Lo, Hi };
4419 return DAG.getMergeValues(Ops, dl);
4422 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4423 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4424 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4425 SelectionDAG &DAG) const {
4426 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4427 EVT VT = Op.getValueType();
4428 unsigned VTBits = VT.getSizeInBits();
4430 SDValue ShOpLo = Op.getOperand(0);
4431 SDValue ShOpHi = Op.getOperand(1);
4432 SDValue ShAmt = Op.getOperand(2);
4435 assert(Op.getOpcode() == ISD::SHL_PARTS);
4436 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4437 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4438 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4439 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4440 DAG.getConstant(VTBits, dl, MVT::i64));
4441 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4442 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4444 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4446 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4447 ISD::SETGE, dl, DAG);
4448 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4450 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4452 // AArch64 shifts of larger than register sizes are wrapped rather than
4453 // clamped, so we can't just emit "lo << a" if a is too big.
4454 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4455 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4457 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4459 SDValue Ops[2] = { Lo, Hi };
4460 return DAG.getMergeValues(Ops, dl);
4463 bool AArch64TargetLowering::isOffsetFoldingLegal(
4464 const GlobalAddressSDNode *GA) const {
4465 // The AArch64 target doesn't support folding offsets into global addresses.
4469 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4470 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4471 // FIXME: We should be able to handle f128 as well with a clever lowering.
4472 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4476 return AArch64_AM::getFP64Imm(Imm) != -1;
4477 else if (VT == MVT::f32)
4478 return AArch64_AM::getFP32Imm(Imm) != -1;
4482 //===----------------------------------------------------------------------===//
4483 // AArch64 Optimization Hooks
4484 //===----------------------------------------------------------------------===//
4486 //===----------------------------------------------------------------------===//
4487 // AArch64 Inline Assembly Support
4488 //===----------------------------------------------------------------------===//
4490 // Table of Constraints
4491 // TODO: This is the current set of constraints supported by ARM for the
4492 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4494 // r - A general register
4495 // w - An FP/SIMD register of some size in the range v0-v31
4496 // x - An FP/SIMD register of some size in the range v0-v15
4497 // I - Constant that can be used with an ADD instruction
4498 // J - Constant that can be used with a SUB instruction
4499 // K - Constant that can be used with a 32-bit logical instruction
4500 // L - Constant that can be used with a 64-bit logical instruction
4501 // M - Constant that can be used as a 32-bit MOV immediate
4502 // N - Constant that can be used as a 64-bit MOV immediate
4503 // Q - A memory reference with base register and no offset
4504 // S - A symbolic address
4505 // Y - Floating point constant zero
4506 // Z - Integer constant zero
4508 // Note that general register operands will be output using their 64-bit x
4509 // register name, whatever the size of the variable, unless the asm operand
4510 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4511 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4514 /// getConstraintType - Given a constraint letter, return the type of
4515 /// constraint it is for this target.
4516 AArch64TargetLowering::ConstraintType
4517 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4518 if (Constraint.size() == 1) {
4519 switch (Constraint[0]) {
4526 return C_RegisterClass;
4527 // An address with a single base register. Due to the way we
4528 // currently handle addresses it is the same as 'r'.
4533 return TargetLowering::getConstraintType(Constraint);
4536 /// Examine constraint type and operand type and determine a weight value.
4537 /// This object must already have been set up with the operand type
4538 /// and the current alternative constraint selected.
4539 TargetLowering::ConstraintWeight
4540 AArch64TargetLowering::getSingleConstraintMatchWeight(
4541 AsmOperandInfo &info, const char *constraint) const {
4542 ConstraintWeight weight = CW_Invalid;
4543 Value *CallOperandVal = info.CallOperandVal;
4544 // If we don't have a value, we can't do a match,
4545 // but allow it at the lowest weight.
4546 if (!CallOperandVal)
4548 Type *type = CallOperandVal->getType();
4549 // Look at the constraint type.
4550 switch (*constraint) {
4552 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4556 if (type->isFloatingPointTy() || type->isVectorTy())
4557 weight = CW_Register;
4560 weight = CW_Constant;
4566 std::pair<unsigned, const TargetRegisterClass *>
4567 AArch64TargetLowering::getRegForInlineAsmConstraint(
4568 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4569 if (Constraint.size() == 1) {
4570 switch (Constraint[0]) {
4572 if (VT.getSizeInBits() == 64)
4573 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4574 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4577 return std::make_pair(0U, &AArch64::FPR32RegClass);
4578 if (VT.getSizeInBits() == 64)
4579 return std::make_pair(0U, &AArch64::FPR64RegClass);
4580 if (VT.getSizeInBits() == 128)
4581 return std::make_pair(0U, &AArch64::FPR128RegClass);
4583 // The instructions that this constraint is designed for can
4584 // only take 128-bit registers so just use that regclass.
4586 if (VT.getSizeInBits() == 128)
4587 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4591 if (StringRef("{cc}").equals_lower(Constraint))
4592 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4594 // Use the default implementation in TargetLowering to convert the register
4595 // constraint into a member of a register class.
4596 std::pair<unsigned, const TargetRegisterClass *> Res;
4597 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4599 // Not found as a standard register?
4601 unsigned Size = Constraint.size();
4602 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4603 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4605 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4606 if (!Failed && RegNo >= 0 && RegNo <= 31) {
4607 // v0 - v31 are aliases of q0 - q31.
4608 // By default we'll emit v0-v31 for this unless there's a modifier where
4609 // we'll emit the correct register as well.
4610 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4611 Res.second = &AArch64::FPR128RegClass;
4619 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4620 /// vector. If it is invalid, don't add anything to Ops.
4621 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4622 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4623 SelectionDAG &DAG) const {
4626 // Currently only support length 1 constraints.
4627 if (Constraint.length() != 1)
4630 char ConstraintLetter = Constraint[0];
4631 switch (ConstraintLetter) {
4635 // This set of constraints deal with valid constants for various instructions.
4636 // Validate and return a target constant for them if we can.
4638 // 'z' maps to xzr or wzr so it needs an input of 0.
4639 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4640 if (!C || C->getZExtValue() != 0)
4643 if (Op.getValueType() == MVT::i64)
4644 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4646 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4656 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4660 // Grab the value and do some validation.
4661 uint64_t CVal = C->getZExtValue();
4662 switch (ConstraintLetter) {
4663 // The I constraint applies only to simple ADD or SUB immediate operands:
4664 // i.e. 0 to 4095 with optional shift by 12
4665 // The J constraint applies only to ADD or SUB immediates that would be
4666 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4667 // instruction [or vice versa], in other words -1 to -4095 with optional
4668 // left shift by 12.
4670 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4674 uint64_t NVal = -C->getSExtValue();
4675 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4676 CVal = C->getSExtValue();
4681 // The K and L constraints apply *only* to logical immediates, including
4682 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4683 // been removed and MOV should be used). So these constraints have to
4684 // distinguish between bit patterns that are valid 32-bit or 64-bit
4685 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4686 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4689 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4693 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4696 // The M and N constraints are a superset of K and L respectively, for use
4697 // with the MOV (immediate) alias. As well as the logical immediates they
4698 // also match 32 or 64-bit immediates that can be loaded either using a
4699 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4700 // (M) or 64-bit 0x1234000000000000 (N) etc.
4701 // As a note some of this code is liberally stolen from the asm parser.
4703 if (!isUInt<32>(CVal))
4705 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4707 if ((CVal & 0xFFFF) == CVal)
4709 if ((CVal & 0xFFFF0000ULL) == CVal)
4711 uint64_t NCVal = ~(uint32_t)CVal;
4712 if ((NCVal & 0xFFFFULL) == NCVal)
4714 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4719 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4721 if ((CVal & 0xFFFFULL) == CVal)
4723 if ((CVal & 0xFFFF0000ULL) == CVal)
4725 if ((CVal & 0xFFFF00000000ULL) == CVal)
4727 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4729 uint64_t NCVal = ~CVal;
4730 if ((NCVal & 0xFFFFULL) == NCVal)
4732 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4734 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4736 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4744 // All assembler immediates are 64-bit integers.
4745 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4749 if (Result.getNode()) {
4750 Ops.push_back(Result);
4754 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4757 //===----------------------------------------------------------------------===//
4758 // AArch64 Advanced SIMD Support
4759 //===----------------------------------------------------------------------===//
4761 /// WidenVector - Given a value in the V64 register class, produce the
4762 /// equivalent value in the V128 register class.
4763 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4764 EVT VT = V64Reg.getValueType();
4765 unsigned NarrowSize = VT.getVectorNumElements();
4766 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4767 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4770 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4771 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4774 /// getExtFactor - Determine the adjustment factor for the position when
4775 /// generating an "extract from vector registers" instruction.
4776 static unsigned getExtFactor(SDValue &V) {
4777 EVT EltType = V.getValueType().getVectorElementType();
4778 return EltType.getSizeInBits() / 8;
4781 /// NarrowVector - Given a value in the V128 register class, produce the
4782 /// equivalent value in the V64 register class.
4783 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4784 EVT VT = V128Reg.getValueType();
4785 unsigned WideSize = VT.getVectorNumElements();
4786 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4787 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4790 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4793 // Gather data to see if the operation can be modelled as a
4794 // shuffle in combination with VEXTs.
4795 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4796 SelectionDAG &DAG) const {
4797 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4799 EVT VT = Op.getValueType();
4800 unsigned NumElts = VT.getVectorNumElements();
4802 struct ShuffleSourceInfo {
4807 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4808 // be compatible with the shuffle we intend to construct. As a result
4809 // ShuffleVec will be some sliding window into the original Vec.
4812 // Code should guarantee that element i in Vec starts at element "WindowBase
4813 // + i * WindowScale in ShuffleVec".
4817 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4818 ShuffleSourceInfo(SDValue Vec)
4819 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4823 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4825 SmallVector<ShuffleSourceInfo, 2> Sources;
4826 for (unsigned i = 0; i < NumElts; ++i) {
4827 SDValue V = Op.getOperand(i);
4828 if (V.getOpcode() == ISD::UNDEF)
4830 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4831 // A shuffle can only come from building a vector from various
4832 // elements of other vectors.
4836 // Add this element source to the list if it's not already there.
4837 SDValue SourceVec = V.getOperand(0);
4838 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4839 if (Source == Sources.end())
4840 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4842 // Update the minimum and maximum lane number seen.
4843 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4844 Source->MinElt = std::min(Source->MinElt, EltNo);
4845 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4848 // Currently only do something sane when at most two source vectors
4850 if (Sources.size() > 2)
4853 // Find out the smallest element size among result and two sources, and use
4854 // it as element size to build the shuffle_vector.
4855 EVT SmallestEltTy = VT.getVectorElementType();
4856 for (auto &Source : Sources) {
4857 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4858 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4859 SmallestEltTy = SrcEltTy;
4862 unsigned ResMultiplier =
4863 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4864 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4865 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4867 // If the source vector is too wide or too narrow, we may nevertheless be able
4868 // to construct a compatible shuffle either by concatenating it with UNDEF or
4869 // extracting a suitable range of elements.
4870 for (auto &Src : Sources) {
4871 EVT SrcVT = Src.ShuffleVec.getValueType();
4873 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4876 // This stage of the search produces a source with the same element type as
4877 // the original, but with a total width matching the BUILD_VECTOR output.
4878 EVT EltVT = SrcVT.getVectorElementType();
4879 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4880 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4882 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4883 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4884 // We can pad out the smaller vector for free, so if it's part of a
4887 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4888 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4892 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4894 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4895 // Span too large for a VEXT to cope
4899 if (Src.MinElt >= NumSrcElts) {
4900 // The extraction can just take the second half
4902 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4903 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4904 Src.WindowBase = -NumSrcElts;
4905 } else if (Src.MaxElt < NumSrcElts) {
4906 // The extraction can just take the first half
4908 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4909 DAG.getConstant(0, dl, MVT::i64));
4911 // An actual VEXT is needed
4913 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4914 DAG.getConstant(0, dl, MVT::i64));
4916 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4917 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4918 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4920 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4922 DAG.getConstant(Imm, dl, MVT::i32));
4923 Src.WindowBase = -Src.MinElt;
4927 // Another possible incompatibility occurs from the vector element types. We
4928 // can fix this by bitcasting the source vectors to the same type we intend
4930 for (auto &Src : Sources) {
4931 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4932 if (SrcEltTy == SmallestEltTy)
4934 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4935 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4936 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4937 Src.WindowBase *= Src.WindowScale;
4940 // Final sanity check before we try to actually produce a shuffle.
4942 for (auto Src : Sources)
4943 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4946 // The stars all align, our next step is to produce the mask for the shuffle.
4947 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4948 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4949 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4950 SDValue Entry = Op.getOperand(i);
4951 if (Entry.getOpcode() == ISD::UNDEF)
4954 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4955 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4957 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4958 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4960 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4961 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4962 VT.getVectorElementType().getSizeInBits());
4963 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4965 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4966 // starting at the appropriate offset.
4967 int *LaneMask = &Mask[i * ResMultiplier];
4969 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4970 ExtractBase += NumElts * (Src - Sources.begin());
4971 for (int j = 0; j < LanesDefined; ++j)
4972 LaneMask[j] = ExtractBase + j;
4975 // Final check before we try to produce nonsense...
4976 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4979 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4980 for (unsigned i = 0; i < Sources.size(); ++i)
4981 ShuffleOps[i] = Sources[i].ShuffleVec;
4983 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4984 ShuffleOps[1], &Mask[0]);
4985 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4988 // check if an EXT instruction can handle the shuffle mask when the
4989 // vector sources of the shuffle are the same.
4990 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4991 unsigned NumElts = VT.getVectorNumElements();
4993 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4999 // If this is a VEXT shuffle, the immediate value is the index of the first
5000 // element. The other shuffle indices must be the successive elements after
5002 unsigned ExpectedElt = Imm;
5003 for (unsigned i = 1; i < NumElts; ++i) {
5004 // Increment the expected index. If it wraps around, just follow it
5005 // back to index zero and keep going.
5007 if (ExpectedElt == NumElts)
5011 continue; // ignore UNDEF indices
5012 if (ExpectedElt != static_cast<unsigned>(M[i]))
5019 // check if an EXT instruction can handle the shuffle mask when the
5020 // vector sources of the shuffle are different.
5021 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
5023 // Look for the first non-undef element.
5024 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
5025 [](int Elt) {return Elt >= 0;});
5027 // Benefit form APInt to handle overflow when calculating expected element.
5028 unsigned NumElts = VT.getVectorNumElements();
5029 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
5030 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
5031 // The following shuffle indices must be the successive elements after the
5032 // first real element.
5033 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5034 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5035 if (FirstWrongElt != M.end())
5038 // The index of an EXT is the first element if it is not UNDEF.
5039 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5040 // value of the first element. E.g.
5041 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5042 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5043 // ExpectedElt is the last mask index plus 1.
5044 Imm = ExpectedElt.getZExtValue();
5046 // There are two difference cases requiring to reverse input vectors.
5047 // For example, for vector <4 x i32> we have the following cases,
5048 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5049 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5050 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5051 // to reverse two input vectors.
5060 /// isREVMask - Check if a vector shuffle corresponds to a REV
5061 /// instruction with the specified blocksize. (The order of the elements
5062 /// within each block of the vector is reversed.)
5063 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5064 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
5065 "Only possible block sizes for REV are: 16, 32, 64");
5067 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5071 unsigned NumElts = VT.getVectorNumElements();
5072 unsigned BlockElts = M[0] + 1;
5073 // If the first shuffle index is UNDEF, be optimistic.
5075 BlockElts = BlockSize / EltSz;
5077 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5080 for (unsigned i = 0; i < NumElts; ++i) {
5082 continue; // ignore UNDEF indices
5083 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5090 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5091 unsigned NumElts = VT.getVectorNumElements();
5092 WhichResult = (M[0] == 0 ? 0 : 1);
5093 unsigned Idx = WhichResult * NumElts / 2;
5094 for (unsigned i = 0; i != NumElts; i += 2) {
5095 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5096 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5104 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5105 unsigned NumElts = VT.getVectorNumElements();
5106 WhichResult = (M[0] == 0 ? 0 : 1);
5107 for (unsigned i = 0; i != NumElts; ++i) {
5109 continue; // ignore UNDEF indices
5110 if ((unsigned)M[i] != 2 * i + WhichResult)
5117 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5118 unsigned NumElts = VT.getVectorNumElements();
5119 WhichResult = (M[0] == 0 ? 0 : 1);
5120 for (unsigned i = 0; i < NumElts; i += 2) {
5121 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5122 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5128 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5129 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5130 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5131 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5132 unsigned NumElts = VT.getVectorNumElements();
5133 WhichResult = (M[0] == 0 ? 0 : 1);
5134 unsigned Idx = WhichResult * NumElts / 2;
5135 for (unsigned i = 0; i != NumElts; i += 2) {
5136 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5137 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5145 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5146 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5147 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5148 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5149 unsigned Half = VT.getVectorNumElements() / 2;
5150 WhichResult = (M[0] == 0 ? 0 : 1);
5151 for (unsigned j = 0; j != 2; ++j) {
5152 unsigned Idx = WhichResult;
5153 for (unsigned i = 0; i != Half; ++i) {
5154 int MIdx = M[i + j * Half];
5155 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5164 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5165 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5166 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5167 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5168 unsigned NumElts = VT.getVectorNumElements();
5169 WhichResult = (M[0] == 0 ? 0 : 1);
5170 for (unsigned i = 0; i < NumElts; i += 2) {
5171 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5172 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5178 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5179 bool &DstIsLeft, int &Anomaly) {
5180 if (M.size() != static_cast<size_t>(NumInputElements))
5183 int NumLHSMatch = 0, NumRHSMatch = 0;
5184 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5186 for (int i = 0; i < NumInputElements; ++i) {
5196 LastLHSMismatch = i;
5198 if (M[i] == i + NumInputElements)
5201 LastRHSMismatch = i;
5204 if (NumLHSMatch == NumInputElements - 1) {
5206 Anomaly = LastLHSMismatch;
5208 } else if (NumRHSMatch == NumInputElements - 1) {
5210 Anomaly = LastRHSMismatch;
5217 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5218 if (VT.getSizeInBits() != 128)
5221 unsigned NumElts = VT.getVectorNumElements();
5223 for (int I = 0, E = NumElts / 2; I != E; I++) {
5228 int Offset = NumElts / 2;
5229 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5230 if (Mask[I] != I + SplitLHS * Offset)
5237 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5239 EVT VT = Op.getValueType();
5240 SDValue V0 = Op.getOperand(0);
5241 SDValue V1 = Op.getOperand(1);
5242 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5244 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5245 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5248 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
5250 if (!isConcatMask(Mask, VT, SplitV0))
5253 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5254 VT.getVectorNumElements() / 2);
5256 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5257 DAG.getConstant(0, DL, MVT::i64));
5259 if (V1.getValueType().getSizeInBits() == 128) {
5260 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5261 DAG.getConstant(0, DL, MVT::i64));
5263 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5266 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5267 /// the specified operations to build the shuffle.
5268 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5269 SDValue RHS, SelectionDAG &DAG,
5271 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5272 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5273 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5276 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5285 OP_VUZPL, // VUZP, left result
5286 OP_VUZPR, // VUZP, right result
5287 OP_VZIPL, // VZIP, left result
5288 OP_VZIPR, // VZIP, right result
5289 OP_VTRNL, // VTRN, left result
5290 OP_VTRNR // VTRN, right result
5293 if (OpNum == OP_COPY) {
5294 if (LHSID == (1 * 9 + 2) * 9 + 3)
5296 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5300 SDValue OpLHS, OpRHS;
5301 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5302 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5303 EVT VT = OpLHS.getValueType();
5307 llvm_unreachable("Unknown shuffle opcode!");
5309 // VREV divides the vector in half and swaps within the half.
5310 if (VT.getVectorElementType() == MVT::i32 ||
5311 VT.getVectorElementType() == MVT::f32)
5312 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5313 // vrev <4 x i16> -> REV32
5314 if (VT.getVectorElementType() == MVT::i16 ||
5315 VT.getVectorElementType() == MVT::f16)
5316 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5317 // vrev <4 x i8> -> REV16
5318 assert(VT.getVectorElementType() == MVT::i8);
5319 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5324 EVT EltTy = VT.getVectorElementType();
5326 if (EltTy == MVT::i8)
5327 Opcode = AArch64ISD::DUPLANE8;
5328 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5329 Opcode = AArch64ISD::DUPLANE16;
5330 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5331 Opcode = AArch64ISD::DUPLANE32;
5332 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5333 Opcode = AArch64ISD::DUPLANE64;
5335 llvm_unreachable("Invalid vector element type?");
5337 if (VT.getSizeInBits() == 64)
5338 OpLHS = WidenVector(OpLHS, DAG);
5339 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5340 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5345 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5346 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5347 DAG.getConstant(Imm, dl, MVT::i32));
5350 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5353 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5356 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5359 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5362 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5365 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5370 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5371 SelectionDAG &DAG) {
5372 // Check to see if we can use the TBL instruction.
5373 SDValue V1 = Op.getOperand(0);
5374 SDValue V2 = Op.getOperand(1);
5377 EVT EltVT = Op.getValueType().getVectorElementType();
5378 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5380 SmallVector<SDValue, 8> TBLMask;
5381 for (int Val : ShuffleMask) {
5382 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5383 unsigned Offset = Byte + Val * BytesPerElt;
5384 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5388 MVT IndexVT = MVT::v8i8;
5389 unsigned IndexLen = 8;
5390 if (Op.getValueType().getSizeInBits() == 128) {
5391 IndexVT = MVT::v16i8;
5395 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5396 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5399 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5401 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5402 Shuffle = DAG.getNode(
5403 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5404 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5405 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5406 makeArrayRef(TBLMask.data(), IndexLen)));
5408 if (IndexLen == 8) {
5409 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5410 Shuffle = DAG.getNode(
5411 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5412 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5413 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5414 makeArrayRef(TBLMask.data(), IndexLen)));
5416 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5417 // cannot currently represent the register constraints on the input
5419 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5420 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5421 // &TBLMask[0], IndexLen));
5422 Shuffle = DAG.getNode(
5423 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5424 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5426 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5427 makeArrayRef(TBLMask.data(), IndexLen)));
5430 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5433 static unsigned getDUPLANEOp(EVT EltType) {
5434 if (EltType == MVT::i8)
5435 return AArch64ISD::DUPLANE8;
5436 if (EltType == MVT::i16 || EltType == MVT::f16)
5437 return AArch64ISD::DUPLANE16;
5438 if (EltType == MVT::i32 || EltType == MVT::f32)
5439 return AArch64ISD::DUPLANE32;
5440 if (EltType == MVT::i64 || EltType == MVT::f64)
5441 return AArch64ISD::DUPLANE64;
5443 llvm_unreachable("Invalid vector element type?");
5446 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5447 SelectionDAG &DAG) const {
5449 EVT VT = Op.getValueType();
5451 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5453 // Convert shuffles that are directly supported on NEON to target-specific
5454 // DAG nodes, instead of keeping them as shuffles and matching them again
5455 // during code selection. This is more efficient and avoids the possibility
5456 // of inconsistencies between legalization and selection.
5457 ArrayRef<int> ShuffleMask = SVN->getMask();
5459 SDValue V1 = Op.getOperand(0);
5460 SDValue V2 = Op.getOperand(1);
5462 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5463 V1.getValueType().getSimpleVT())) {
5464 int Lane = SVN->getSplatIndex();
5465 // If this is undef splat, generate it via "just" vdup, if possible.
5469 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5470 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5472 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5473 // constant. If so, we can just reference the lane's definition directly.
5474 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5475 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5476 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5478 // Otherwise, duplicate from the lane of the input vector.
5479 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5481 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5482 // to make a vector of the same size as this SHUFFLE. We can ignore the
5483 // extract entirely, and canonicalise the concat using WidenVector.
5484 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5485 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5486 V1 = V1.getOperand(0);
5487 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5488 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5489 Lane -= Idx * VT.getVectorNumElements() / 2;
5490 V1 = WidenVector(V1.getOperand(Idx), DAG);
5491 } else if (VT.getSizeInBits() == 64)
5492 V1 = WidenVector(V1, DAG);
5494 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5497 if (isREVMask(ShuffleMask, VT, 64))
5498 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5499 if (isREVMask(ShuffleMask, VT, 32))
5500 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5501 if (isREVMask(ShuffleMask, VT, 16))
5502 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5504 bool ReverseEXT = false;
5506 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5509 Imm *= getExtFactor(V1);
5510 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5511 DAG.getConstant(Imm, dl, MVT::i32));
5512 } else if (V2->getOpcode() == ISD::UNDEF &&
5513 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5514 Imm *= getExtFactor(V1);
5515 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5516 DAG.getConstant(Imm, dl, MVT::i32));
5519 unsigned WhichResult;
5520 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5521 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5522 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5524 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5525 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5526 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5528 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5529 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5530 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5533 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5534 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5535 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5537 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5538 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5539 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5541 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5542 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5543 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5546 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5547 if (Concat.getNode())
5552 int NumInputElements = V1.getValueType().getVectorNumElements();
5553 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5554 SDValue DstVec = DstIsLeft ? V1 : V2;
5555 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5557 SDValue SrcVec = V1;
5558 int SrcLane = ShuffleMask[Anomaly];
5559 if (SrcLane >= NumInputElements) {
5561 SrcLane -= VT.getVectorNumElements();
5563 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5565 EVT ScalarVT = VT.getVectorElementType();
5567 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5568 ScalarVT = MVT::i32;
5571 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5572 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5576 // If the shuffle is not directly supported and it has 4 elements, use
5577 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5578 unsigned NumElts = VT.getVectorNumElements();
5580 unsigned PFIndexes[4];
5581 for (unsigned i = 0; i != 4; ++i) {
5582 if (ShuffleMask[i] < 0)
5585 PFIndexes[i] = ShuffleMask[i];
5588 // Compute the index in the perfect shuffle table.
5589 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5590 PFIndexes[2] * 9 + PFIndexes[3];
5591 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5592 unsigned Cost = (PFEntry >> 30);
5595 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5598 return GenerateTBL(Op, ShuffleMask, DAG);
5601 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5603 EVT VT = BVN->getValueType(0);
5604 APInt SplatBits, SplatUndef;
5605 unsigned SplatBitSize;
5607 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5608 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5610 for (unsigned i = 0; i < NumSplats; ++i) {
5611 CnstBits <<= SplatBitSize;
5612 UndefBits <<= SplatBitSize;
5613 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5614 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5623 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5624 SelectionDAG &DAG) const {
5625 BuildVectorSDNode *BVN =
5626 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5627 SDValue LHS = Op.getOperand(0);
5629 EVT VT = Op.getValueType();
5634 APInt CnstBits(VT.getSizeInBits(), 0);
5635 APInt UndefBits(VT.getSizeInBits(), 0);
5636 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5637 // We only have BIC vector immediate instruction, which is and-not.
5638 CnstBits = ~CnstBits;
5640 // We make use of a little bit of goto ickiness in order to avoid having to
5641 // duplicate the immediate matching logic for the undef toggled case.
5642 bool SecondTry = false;
5645 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5646 CnstBits = CnstBits.zextOrTrunc(64);
5647 uint64_t CnstVal = CnstBits.getZExtValue();
5649 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5650 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5651 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5652 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5653 DAG.getConstant(CnstVal, dl, MVT::i32),
5654 DAG.getConstant(0, dl, MVT::i32));
5655 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5658 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5659 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5660 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5661 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5662 DAG.getConstant(CnstVal, dl, MVT::i32),
5663 DAG.getConstant(8, dl, MVT::i32));
5664 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5667 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5668 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5669 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5670 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5671 DAG.getConstant(CnstVal, dl, MVT::i32),
5672 DAG.getConstant(16, dl, MVT::i32));
5673 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5676 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5677 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5678 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5679 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5680 DAG.getConstant(CnstVal, dl, MVT::i32),
5681 DAG.getConstant(24, dl, MVT::i32));
5682 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5685 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5686 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5687 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5688 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5689 DAG.getConstant(CnstVal, dl, MVT::i32),
5690 DAG.getConstant(0, dl, MVT::i32));
5691 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5694 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5695 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5696 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5697 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5698 DAG.getConstant(CnstVal, dl, MVT::i32),
5699 DAG.getConstant(8, dl, MVT::i32));
5700 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5707 CnstBits = ~UndefBits;
5711 // We can always fall back to a non-immediate AND.
5716 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5717 // consists of only the same constant int value, returned in reference arg
5719 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5720 uint64_t &ConstVal) {
5721 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5724 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5727 EVT VT = Bvec->getValueType(0);
5728 unsigned NumElts = VT.getVectorNumElements();
5729 for (unsigned i = 1; i < NumElts; ++i)
5730 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5732 ConstVal = FirstElt->getZExtValue();
5736 static unsigned getIntrinsicID(const SDNode *N) {
5737 unsigned Opcode = N->getOpcode();
5740 return Intrinsic::not_intrinsic;
5741 case ISD::INTRINSIC_WO_CHAIN: {
5742 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5743 if (IID < Intrinsic::num_intrinsics)
5745 return Intrinsic::not_intrinsic;
5750 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5751 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5752 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5753 // Also, logical shift right -> sri, with the same structure.
5754 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5755 EVT VT = N->getValueType(0);
5762 // Is the first op an AND?
5763 const SDValue And = N->getOperand(0);
5764 if (And.getOpcode() != ISD::AND)
5767 // Is the second op an shl or lshr?
5768 SDValue Shift = N->getOperand(1);
5769 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5770 // or AArch64ISD::VLSHR vector, #shift
5771 unsigned ShiftOpc = Shift.getOpcode();
5772 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5774 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5776 // Is the shift amount constant?
5777 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5781 // Is the and mask vector all constant?
5783 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5786 // Is C1 == ~C2, taking into account how much one can shift elements of a
5788 uint64_t C2 = C2node->getZExtValue();
5789 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5790 if (C2 > ElemSizeInBits)
5792 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5793 if ((C1 & ElemMask) != (~C2 & ElemMask))
5796 SDValue X = And.getOperand(0);
5797 SDValue Y = Shift.getOperand(0);
5800 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5802 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5803 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5804 Shift.getOperand(1));
5806 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5807 DEBUG(N->dump(&DAG));
5808 DEBUG(dbgs() << "into: \n");
5809 DEBUG(ResultSLI->dump(&DAG));
5815 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5816 SelectionDAG &DAG) const {
5817 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5818 if (EnableAArch64SlrGeneration) {
5819 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5824 BuildVectorSDNode *BVN =
5825 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5826 SDValue LHS = Op.getOperand(1);
5828 EVT VT = Op.getValueType();
5830 // OR commutes, so try swapping the operands.
5832 LHS = Op.getOperand(0);
5833 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5838 APInt CnstBits(VT.getSizeInBits(), 0);
5839 APInt UndefBits(VT.getSizeInBits(), 0);
5840 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5841 // We make use of a little bit of goto ickiness in order to avoid having to
5842 // duplicate the immediate matching logic for the undef toggled case.
5843 bool SecondTry = false;
5846 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5847 CnstBits = CnstBits.zextOrTrunc(64);
5848 uint64_t CnstVal = CnstBits.getZExtValue();
5850 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5851 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5852 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5853 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5854 DAG.getConstant(CnstVal, dl, MVT::i32),
5855 DAG.getConstant(0, dl, MVT::i32));
5856 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5859 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5860 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5861 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5862 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5863 DAG.getConstant(CnstVal, dl, MVT::i32),
5864 DAG.getConstant(8, dl, MVT::i32));
5865 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5868 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5869 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5870 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5871 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5872 DAG.getConstant(CnstVal, dl, MVT::i32),
5873 DAG.getConstant(16, dl, MVT::i32));
5874 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5877 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5878 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5879 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5880 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5881 DAG.getConstant(CnstVal, dl, MVT::i32),
5882 DAG.getConstant(24, dl, MVT::i32));
5883 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5886 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5887 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5888 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5889 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5890 DAG.getConstant(CnstVal, dl, MVT::i32),
5891 DAG.getConstant(0, dl, MVT::i32));
5892 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5895 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5896 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5897 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5898 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5899 DAG.getConstant(CnstVal, dl, MVT::i32),
5900 DAG.getConstant(8, dl, MVT::i32));
5901 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5908 CnstBits = UndefBits;
5912 // We can always fall back to a non-immediate OR.
5917 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5918 // be truncated to fit element width.
5919 static SDValue NormalizeBuildVector(SDValue Op,
5920 SelectionDAG &DAG) {
5921 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5923 EVT VT = Op.getValueType();
5924 EVT EltTy= VT.getVectorElementType();
5926 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5929 SmallVector<SDValue, 16> Ops;
5930 for (SDValue Lane : Op->ops()) {
5931 if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
5932 APInt LowBits(EltTy.getSizeInBits(),
5933 CstLane->getZExtValue());
5934 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5936 Ops.push_back(Lane);
5938 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5941 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5942 SelectionDAG &DAG) const {
5944 EVT VT = Op.getValueType();
5945 Op = NormalizeBuildVector(Op, DAG);
5946 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5948 APInt CnstBits(VT.getSizeInBits(), 0);
5949 APInt UndefBits(VT.getSizeInBits(), 0);
5950 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5951 // We make use of a little bit of goto ickiness in order to avoid having to
5952 // duplicate the immediate matching logic for the undef toggled case.
5953 bool SecondTry = false;
5956 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5957 CnstBits = CnstBits.zextOrTrunc(64);
5958 uint64_t CnstVal = CnstBits.getZExtValue();
5960 // Certain magic vector constants (used to express things like NOT
5961 // and NEG) are passed through unmodified. This allows codegen patterns
5962 // for these operations to match. Special-purpose patterns will lower
5963 // these immediates to MOVIs if it proves necessary.
5964 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5967 // The many faces of MOVI...
5968 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5969 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5970 if (VT.getSizeInBits() == 128) {
5971 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5972 DAG.getConstant(CnstVal, dl, MVT::i32));
5973 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5976 // Support the V64 version via subregister insertion.
5977 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5978 DAG.getConstant(CnstVal, dl, MVT::i32));
5979 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5982 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5983 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5984 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5985 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5986 DAG.getConstant(CnstVal, dl, MVT::i32),
5987 DAG.getConstant(0, dl, MVT::i32));
5988 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5991 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5992 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5993 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5994 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5995 DAG.getConstant(CnstVal, dl, MVT::i32),
5996 DAG.getConstant(8, dl, MVT::i32));
5997 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6000 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6001 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6002 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6003 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6004 DAG.getConstant(CnstVal, dl, MVT::i32),
6005 DAG.getConstant(16, dl, MVT::i32));
6006 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6009 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6010 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6011 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6012 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6013 DAG.getConstant(CnstVal, dl, MVT::i32),
6014 DAG.getConstant(24, dl, MVT::i32));
6015 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6018 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6019 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6020 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6021 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6022 DAG.getConstant(CnstVal, dl, MVT::i32),
6023 DAG.getConstant(0, dl, MVT::i32));
6024 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6027 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6028 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6029 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6030 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6031 DAG.getConstant(CnstVal, dl, MVT::i32),
6032 DAG.getConstant(8, dl, MVT::i32));
6033 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6036 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6037 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6038 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6039 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6040 DAG.getConstant(CnstVal, dl, MVT::i32),
6041 DAG.getConstant(264, dl, MVT::i32));
6042 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6045 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6046 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6047 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6048 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6049 DAG.getConstant(CnstVal, dl, MVT::i32),
6050 DAG.getConstant(272, dl, MVT::i32));
6051 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6054 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
6055 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
6056 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6057 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
6058 DAG.getConstant(CnstVal, dl, MVT::i32));
6059 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6062 // The few faces of FMOV...
6063 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
6064 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
6065 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6066 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
6067 DAG.getConstant(CnstVal, dl, MVT::i32));
6068 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6071 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
6072 VT.getSizeInBits() == 128) {
6073 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
6074 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
6075 DAG.getConstant(CnstVal, dl, MVT::i32));
6076 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6079 // The many faces of MVNI...
6081 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6082 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6083 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6084 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6085 DAG.getConstant(CnstVal, dl, MVT::i32),
6086 DAG.getConstant(0, dl, MVT::i32));
6087 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6090 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6091 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6092 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6093 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6094 DAG.getConstant(CnstVal, dl, MVT::i32),
6095 DAG.getConstant(8, dl, MVT::i32));
6096 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6099 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6100 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6101 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6102 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6103 DAG.getConstant(CnstVal, dl, MVT::i32),
6104 DAG.getConstant(16, dl, MVT::i32));
6105 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6108 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6109 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6110 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6111 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6112 DAG.getConstant(CnstVal, dl, MVT::i32),
6113 DAG.getConstant(24, dl, MVT::i32));
6114 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6117 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6118 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6119 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6120 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6121 DAG.getConstant(CnstVal, dl, MVT::i32),
6122 DAG.getConstant(0, dl, MVT::i32));
6123 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6126 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6127 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6128 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6129 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6130 DAG.getConstant(CnstVal, dl, MVT::i32),
6131 DAG.getConstant(8, dl, MVT::i32));
6132 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6135 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6136 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6137 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6138 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6139 DAG.getConstant(CnstVal, dl, MVT::i32),
6140 DAG.getConstant(264, dl, MVT::i32));
6141 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6144 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6145 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6146 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6147 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6148 DAG.getConstant(CnstVal, dl, MVT::i32),
6149 DAG.getConstant(272, dl, MVT::i32));
6150 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6157 CnstBits = UndefBits;
6162 // Scan through the operands to find some interesting properties we can
6164 // 1) If only one value is used, we can use a DUP, or
6165 // 2) if only the low element is not undef, we can just insert that, or
6166 // 3) if only one constant value is used (w/ some non-constant lanes),
6167 // we can splat the constant value into the whole vector then fill
6168 // in the non-constant lanes.
6169 // 4) FIXME: If different constant values are used, but we can intelligently
6170 // select the values we'll be overwriting for the non-constant
6171 // lanes such that we can directly materialize the vector
6172 // some other way (MOVI, e.g.), we can be sneaky.
6173 unsigned NumElts = VT.getVectorNumElements();
6174 bool isOnlyLowElement = true;
6175 bool usesOnlyOneValue = true;
6176 bool usesOnlyOneConstantValue = true;
6177 bool isConstant = true;
6178 unsigned NumConstantLanes = 0;
6180 SDValue ConstantValue;
6181 for (unsigned i = 0; i < NumElts; ++i) {
6182 SDValue V = Op.getOperand(i);
6183 if (V.getOpcode() == ISD::UNDEF)
6186 isOnlyLowElement = false;
6187 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6190 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
6192 if (!ConstantValue.getNode())
6194 else if (ConstantValue != V)
6195 usesOnlyOneConstantValue = false;
6198 if (!Value.getNode())
6200 else if (V != Value)
6201 usesOnlyOneValue = false;
6204 if (!Value.getNode())
6205 return DAG.getUNDEF(VT);
6207 if (isOnlyLowElement)
6208 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6210 // Use DUP for non-constant splats. For f32 constant splats, reduce to
6211 // i32 and try again.
6212 if (usesOnlyOneValue) {
6214 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6215 Value.getValueType() != VT)
6216 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6218 // This is actually a DUPLANExx operation, which keeps everything vectory.
6220 // DUPLANE works on 128-bit vectors, widen it if necessary.
6221 SDValue Lane = Value.getOperand(1);
6222 Value = Value.getOperand(0);
6223 if (Value.getValueType().getSizeInBits() == 64)
6224 Value = WidenVector(Value, DAG);
6226 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6227 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6230 if (VT.getVectorElementType().isFloatingPoint()) {
6231 SmallVector<SDValue, 8> Ops;
6232 EVT EltTy = VT.getVectorElementType();
6233 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
6234 "Unsupported floating-point vector type");
6235 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
6236 for (unsigned i = 0; i < NumElts; ++i)
6237 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
6238 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
6239 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
6240 Val = LowerBUILD_VECTOR(Val, DAG);
6242 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6246 // If there was only one constant value used and for more than one lane,
6247 // start by splatting that value, then replace the non-constant lanes. This
6248 // is better than the default, which will perform a separate initialization
6250 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6251 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6252 // Now insert the non-constant lanes.
6253 for (unsigned i = 0; i < NumElts; ++i) {
6254 SDValue V = Op.getOperand(i);
6255 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6256 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6257 // Note that type legalization likely mucked about with the VT of the
6258 // source operand, so we may have to convert it here before inserting.
6259 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6265 // If all elements are constants and the case above didn't get hit, fall back
6266 // to the default expansion, which will generate a load from the constant
6271 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6273 if (SDValue shuffle = ReconstructShuffle(Op, DAG))
6277 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6278 // know the default expansion would otherwise fall back on something even
6279 // worse. For a vector with one or two non-undef values, that's
6280 // scalar_to_vector for the elements followed by a shuffle (provided the
6281 // shuffle is valid for the target) and materialization element by element
6282 // on the stack followed by a load for everything else.
6283 if (!isConstant && !usesOnlyOneValue) {
6284 SDValue Vec = DAG.getUNDEF(VT);
6285 SDValue Op0 = Op.getOperand(0);
6286 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6288 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6289 // a) Avoid a RMW dependency on the full vector register, and
6290 // b) Allow the register coalescer to fold away the copy if the
6291 // value is already in an S or D register.
6292 // Do not do this for UNDEF/LOAD nodes because we have better patterns
6293 // for those avoiding the SCALAR_TO_VECTOR/BUILD_VECTOR.
6294 if (Op0.getOpcode() != ISD::UNDEF && Op0.getOpcode() != ISD::LOAD &&
6295 (ElemSize == 32 || ElemSize == 64)) {
6296 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6298 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6299 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6300 Vec = SDValue(N, 0);
6303 for (; i < NumElts; ++i) {
6304 SDValue V = Op.getOperand(i);
6305 if (V.getOpcode() == ISD::UNDEF)
6307 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6308 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6313 // Just use the default expansion. We failed to find a better alternative.
6317 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6318 SelectionDAG &DAG) const {
6319 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6321 // Check for non-constant or out of range lane.
6322 EVT VT = Op.getOperand(0).getValueType();
6323 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6324 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6328 // Insertion/extraction are legal for V128 types.
6329 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6330 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6334 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6335 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6338 // For V64 types, we perform insertion by expanding the value
6339 // to a V128 type and perform the insertion on that.
6341 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6342 EVT WideTy = WideVec.getValueType();
6344 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6345 Op.getOperand(1), Op.getOperand(2));
6346 // Re-narrow the resultant vector.
6347 return NarrowVector(Node, DAG);
6351 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6352 SelectionDAG &DAG) const {
6353 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6355 // Check for non-constant or out of range lane.
6356 EVT VT = Op.getOperand(0).getValueType();
6357 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6358 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6362 // Insertion/extraction are legal for V128 types.
6363 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6364 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6368 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6369 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6372 // For V64 types, we perform extraction by expanding the value
6373 // to a V128 type and perform the extraction on that.
6375 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6376 EVT WideTy = WideVec.getValueType();
6378 EVT ExtrTy = WideTy.getVectorElementType();
6379 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6382 // For extractions, we just return the result directly.
6383 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6387 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6388 SelectionDAG &DAG) const {
6389 EVT VT = Op.getOperand(0).getValueType();
6395 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6398 unsigned Val = Cst->getZExtValue();
6400 unsigned Size = Op.getValueType().getSizeInBits();
6404 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6407 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6410 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6413 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6416 llvm_unreachable("Unexpected vector type in extract_subvector!");
6419 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6421 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6427 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6429 if (VT.getVectorNumElements() == 4 &&
6430 (VT.is128BitVector() || VT.is64BitVector())) {
6431 unsigned PFIndexes[4];
6432 for (unsigned i = 0; i != 4; ++i) {
6436 PFIndexes[i] = M[i];
6439 // Compute the index in the perfect shuffle table.
6440 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6441 PFIndexes[2] * 9 + PFIndexes[3];
6442 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6443 unsigned Cost = (PFEntry >> 30);
6451 unsigned DummyUnsigned;
6453 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6454 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6455 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6456 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6457 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6458 isZIPMask(M, VT, DummyUnsigned) ||
6459 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6460 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6461 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6462 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6463 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6466 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6467 /// operand of a vector shift operation, where all the elements of the
6468 /// build_vector must have the same constant integer value.
6469 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6470 // Ignore bit_converts.
6471 while (Op.getOpcode() == ISD::BITCAST)
6472 Op = Op.getOperand(0);
6473 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6474 APInt SplatBits, SplatUndef;
6475 unsigned SplatBitSize;
6477 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6478 HasAnyUndefs, ElementBits) ||
6479 SplatBitSize > ElementBits)
6481 Cnt = SplatBits.getSExtValue();
6485 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6486 /// operand of a vector shift left operation. That value must be in the range:
6487 /// 0 <= Value < ElementBits for a left shift; or
6488 /// 0 <= Value <= ElementBits for a long left shift.
6489 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6490 assert(VT.isVector() && "vector shift count is not a vector type");
6491 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6492 if (!getVShiftImm(Op, ElementBits, Cnt))
6494 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6497 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6498 /// operand of a vector shift right operation. The value must be in the range:
6499 /// 1 <= Value <= ElementBits for a right shift; or
6500 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6501 assert(VT.isVector() && "vector shift count is not a vector type");
6502 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6503 if (!getVShiftImm(Op, ElementBits, Cnt))
6505 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6508 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6509 SelectionDAG &DAG) const {
6510 EVT VT = Op.getValueType();
6514 if (!Op.getOperand(1).getValueType().isVector())
6516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6518 switch (Op.getOpcode()) {
6520 llvm_unreachable("unexpected shift opcode");
6523 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6524 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6525 DAG.getConstant(Cnt, DL, MVT::i32));
6526 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6527 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6529 Op.getOperand(0), Op.getOperand(1));
6532 // Right shift immediate
6533 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6535 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6536 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6537 DAG.getConstant(Cnt, DL, MVT::i32));
6540 // Right shift register. Note, there is not a shift right register
6541 // instruction, but the shift left register instruction takes a signed
6542 // value, where negative numbers specify a right shift.
6543 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6544 : Intrinsic::aarch64_neon_ushl;
6545 // negate the shift amount
6546 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6547 SDValue NegShiftLeft =
6548 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6549 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6551 return NegShiftLeft;
6557 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6558 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6559 SDLoc dl, SelectionDAG &DAG) {
6560 EVT SrcVT = LHS.getValueType();
6561 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6562 "function only supposed to emit natural comparisons");
6564 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6565 APInt CnstBits(VT.getSizeInBits(), 0);
6566 APInt UndefBits(VT.getSizeInBits(), 0);
6567 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6568 bool IsZero = IsCnst && (CnstBits == 0);
6570 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6574 case AArch64CC::NE: {
6577 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6579 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6580 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6584 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6585 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6588 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6589 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6592 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6593 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6596 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6597 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6601 // If we ignore NaNs then we can use to the MI implementation.
6605 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6606 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6613 case AArch64CC::NE: {
6616 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6618 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6619 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6623 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6624 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6627 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6628 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6631 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6632 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6635 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6636 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6638 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6640 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6643 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6644 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6646 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6648 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6652 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6653 SelectionDAG &DAG) const {
6654 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6655 SDValue LHS = Op.getOperand(0);
6656 SDValue RHS = Op.getOperand(1);
6657 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6660 if (LHS.getValueType().getVectorElementType().isInteger()) {
6661 assert(LHS.getValueType() == RHS.getValueType());
6662 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6664 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6665 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6668 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6669 LHS.getValueType().getVectorElementType() == MVT::f64);
6671 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6672 // clean. Some of them require two branches to implement.
6673 AArch64CC::CondCode CC1, CC2;
6675 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6677 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6679 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6683 if (CC2 != AArch64CC::AL) {
6685 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6686 if (!Cmp2.getNode())
6689 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6692 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6695 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6700 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6701 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6702 /// specified in the intrinsic calls.
6703 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6705 unsigned Intrinsic) const {
6706 auto &DL = I.getModule()->getDataLayout();
6707 switch (Intrinsic) {
6708 case Intrinsic::aarch64_neon_ld2:
6709 case Intrinsic::aarch64_neon_ld3:
6710 case Intrinsic::aarch64_neon_ld4:
6711 case Intrinsic::aarch64_neon_ld1x2:
6712 case Intrinsic::aarch64_neon_ld1x3:
6713 case Intrinsic::aarch64_neon_ld1x4:
6714 case Intrinsic::aarch64_neon_ld2lane:
6715 case Intrinsic::aarch64_neon_ld3lane:
6716 case Intrinsic::aarch64_neon_ld4lane:
6717 case Intrinsic::aarch64_neon_ld2r:
6718 case Intrinsic::aarch64_neon_ld3r:
6719 case Intrinsic::aarch64_neon_ld4r: {
6720 Info.opc = ISD::INTRINSIC_W_CHAIN;
6721 // Conservatively set memVT to the entire set of vectors loaded.
6722 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
6723 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6724 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6727 Info.vol = false; // volatile loads with NEON intrinsics not supported
6728 Info.readMem = true;
6729 Info.writeMem = false;
6732 case Intrinsic::aarch64_neon_st2:
6733 case Intrinsic::aarch64_neon_st3:
6734 case Intrinsic::aarch64_neon_st4:
6735 case Intrinsic::aarch64_neon_st1x2:
6736 case Intrinsic::aarch64_neon_st1x3:
6737 case Intrinsic::aarch64_neon_st1x4:
6738 case Intrinsic::aarch64_neon_st2lane:
6739 case Intrinsic::aarch64_neon_st3lane:
6740 case Intrinsic::aarch64_neon_st4lane: {
6741 Info.opc = ISD::INTRINSIC_VOID;
6742 // Conservatively set memVT to the entire set of vectors stored.
6743 unsigned NumElts = 0;
6744 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6745 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6746 if (!ArgTy->isVectorTy())
6748 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
6750 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6751 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6754 Info.vol = false; // volatile stores with NEON intrinsics not supported
6755 Info.readMem = false;
6756 Info.writeMem = true;
6759 case Intrinsic::aarch64_ldaxr:
6760 case Intrinsic::aarch64_ldxr: {
6761 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6762 Info.opc = ISD::INTRINSIC_W_CHAIN;
6763 Info.memVT = MVT::getVT(PtrTy->getElementType());
6764 Info.ptrVal = I.getArgOperand(0);
6766 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6768 Info.readMem = true;
6769 Info.writeMem = false;
6772 case Intrinsic::aarch64_stlxr:
6773 case Intrinsic::aarch64_stxr: {
6774 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6775 Info.opc = ISD::INTRINSIC_W_CHAIN;
6776 Info.memVT = MVT::getVT(PtrTy->getElementType());
6777 Info.ptrVal = I.getArgOperand(1);
6779 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6781 Info.readMem = false;
6782 Info.writeMem = true;
6785 case Intrinsic::aarch64_ldaxp:
6786 case Intrinsic::aarch64_ldxp: {
6787 Info.opc = ISD::INTRINSIC_W_CHAIN;
6788 Info.memVT = MVT::i128;
6789 Info.ptrVal = I.getArgOperand(0);
6793 Info.readMem = true;
6794 Info.writeMem = false;
6797 case Intrinsic::aarch64_stlxp:
6798 case Intrinsic::aarch64_stxp: {
6799 Info.opc = ISD::INTRINSIC_W_CHAIN;
6800 Info.memVT = MVT::i128;
6801 Info.ptrVal = I.getArgOperand(2);
6805 Info.readMem = false;
6806 Info.writeMem = true;
6816 // Truncations from 64-bit GPR to 32-bit GPR is free.
6817 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6818 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6820 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6821 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6822 return NumBits1 > NumBits2;
6824 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6825 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6827 unsigned NumBits1 = VT1.getSizeInBits();
6828 unsigned NumBits2 = VT2.getSizeInBits();
6829 return NumBits1 > NumBits2;
6832 /// Check if it is profitable to hoist instruction in then/else to if.
6833 /// Not profitable if I and it's user can form a FMA instruction
6834 /// because we prefer FMSUB/FMADD.
6835 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6836 if (I->getOpcode() != Instruction::FMul)
6839 if (I->getNumUses() != 1)
6842 Instruction *User = I->user_back();
6845 !(User->getOpcode() == Instruction::FSub ||
6846 User->getOpcode() == Instruction::FAdd))
6849 const TargetOptions &Options = getTargetMachine().Options;
6850 const DataLayout &DL = I->getModule()->getDataLayout();
6851 EVT VT = getValueType(DL, User->getOperand(0)->getType());
6853 if (isFMAFasterThanFMulAndFAdd(VT) &&
6854 isOperationLegalOrCustom(ISD::FMA, VT) &&
6855 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6861 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6863 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6864 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6866 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6867 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6868 return NumBits1 == 32 && NumBits2 == 64;
6870 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6871 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6873 unsigned NumBits1 = VT1.getSizeInBits();
6874 unsigned NumBits2 = VT2.getSizeInBits();
6875 return NumBits1 == 32 && NumBits2 == 64;
6878 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6879 EVT VT1 = Val.getValueType();
6880 if (isZExtFree(VT1, VT2)) {
6884 if (Val.getOpcode() != ISD::LOAD)
6887 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6888 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6889 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6890 VT1.getSizeInBits() <= 32);
6893 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6894 if (isa<FPExtInst>(Ext))
6897 // Vector types are next free.
6898 if (Ext->getType()->isVectorTy())
6901 for (const Use &U : Ext->uses()) {
6902 // The extension is free if we can fold it with a left shift in an
6903 // addressing mode or an arithmetic operation: add, sub, and cmp.
6905 // Is there a shift?
6906 const Instruction *Instr = cast<Instruction>(U.getUser());
6908 // Is this a constant shift?
6909 switch (Instr->getOpcode()) {
6910 case Instruction::Shl:
6911 if (!isa<ConstantInt>(Instr->getOperand(1)))
6914 case Instruction::GetElementPtr: {
6915 gep_type_iterator GTI = gep_type_begin(Instr);
6916 auto &DL = Ext->getModule()->getDataLayout();
6917 std::advance(GTI, U.getOperandNo());
6919 // This extension will end up with a shift because of the scaling factor.
6920 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6921 // Get the shift amount based on the scaling factor:
6922 // log2(sizeof(IdxTy)) - log2(8).
6924 countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy)) - 3;
6925 // Is the constant foldable in the shift of the addressing mode?
6926 // I.e., shift amount is between 1 and 4 inclusive.
6927 if (ShiftAmt == 0 || ShiftAmt > 4)
6931 case Instruction::Trunc:
6932 // Check if this is a noop.
6933 // trunc(sext ty1 to ty2) to ty1.
6934 if (Instr->getType() == Ext->getOperand(0)->getType())
6941 // At this point we can use the bfm family, so this extension is free
6947 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6948 unsigned &RequiredAligment) const {
6949 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6951 // Cyclone supports unaligned accesses.
6952 RequiredAligment = 0;
6953 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6954 return NumBits == 32 || NumBits == 64;
6957 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6958 unsigned &RequiredAligment) const {
6959 if (!LoadedType.isSimple() ||
6960 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6962 // Cyclone supports unaligned accesses.
6963 RequiredAligment = 0;
6964 unsigned NumBits = LoadedType.getSizeInBits();
6965 return NumBits == 32 || NumBits == 64;
6968 /// \brief Lower an interleaved load into a ldN intrinsic.
6970 /// E.g. Lower an interleaved load (Factor = 2):
6971 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6972 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6973 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6976 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6977 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6978 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6979 bool AArch64TargetLowering::lowerInterleavedLoad(
6980 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6981 ArrayRef<unsigned> Indices, unsigned Factor) const {
6982 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6983 "Invalid interleave factor");
6984 assert(!Shuffles.empty() && "Empty shufflevector input");
6985 assert(Shuffles.size() == Indices.size() &&
6986 "Unmatched number of shufflevectors and indices");
6988 const DataLayout &DL = LI->getModule()->getDataLayout();
6990 VectorType *VecTy = Shuffles[0]->getType();
6991 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
6993 // Skip if we do not have NEON and skip illegal vector types.
6994 if (!Subtarget->hasNEON() || (VecSize != 64 && VecSize != 128))
6997 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6998 // load integer vectors first and then convert to pointer vectors.
6999 Type *EltTy = VecTy->getVectorElementType();
7000 if (EltTy->isPointerTy())
7002 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
7004 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
7005 Type *Tys[2] = {VecTy, PtrTy};
7006 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
7007 Intrinsic::aarch64_neon_ld3,
7008 Intrinsic::aarch64_neon_ld4};
7010 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
7012 IRBuilder<> Builder(LI);
7013 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
7015 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
7017 // Replace uses of each shufflevector with the corresponding vector loaded
7019 for (unsigned i = 0; i < Shuffles.size(); i++) {
7020 ShuffleVectorInst *SVI = Shuffles[i];
7021 unsigned Index = Indices[i];
7023 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
7025 // Convert the integer vector to pointer vector if the element is pointer.
7026 if (EltTy->isPointerTy())
7027 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
7029 SVI->replaceAllUsesWith(SubVec);
7035 /// \brief Get a mask consisting of sequential integers starting from \p Start.
7037 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
7038 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
7040 SmallVector<Constant *, 16> Mask;
7041 for (unsigned i = 0; i < NumElts; i++)
7042 Mask.push_back(Builder.getInt32(Start + i));
7044 return ConstantVector::get(Mask);
7047 /// \brief Lower an interleaved store into a stN intrinsic.
7049 /// E.g. Lower an interleaved store (Factor = 3):
7050 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7051 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
7052 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7055 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7056 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7057 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7058 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7060 /// Note that the new shufflevectors will be removed and we'll only generate one
7061 /// st3 instruction in CodeGen.
7062 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7063 ShuffleVectorInst *SVI,
7064 unsigned Factor) const {
7065 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7066 "Invalid interleave factor");
7068 VectorType *VecTy = SVI->getType();
7069 assert(VecTy->getVectorNumElements() % Factor == 0 &&
7070 "Invalid interleaved store");
7072 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
7073 Type *EltTy = VecTy->getVectorElementType();
7074 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
7076 const DataLayout &DL = SI->getModule()->getDataLayout();
7077 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
7079 // Skip if we do not have NEON and skip illegal vector types.
7080 if (!Subtarget->hasNEON() || (SubVecSize != 64 && SubVecSize != 128))
7083 Value *Op0 = SVI->getOperand(0);
7084 Value *Op1 = SVI->getOperand(1);
7085 IRBuilder<> Builder(SI);
7087 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
7088 // vectors to integer vectors.
7089 if (EltTy->isPointerTy()) {
7090 Type *IntTy = DL.getIntPtrType(EltTy);
7091 unsigned NumOpElts =
7092 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
7094 // Convert to the corresponding integer vector.
7095 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
7096 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
7097 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
7099 SubVecTy = VectorType::get(IntTy, NumSubElts);
7102 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
7103 Type *Tys[2] = {SubVecTy, PtrTy};
7104 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
7105 Intrinsic::aarch64_neon_st3,
7106 Intrinsic::aarch64_neon_st4};
7108 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
7110 SmallVector<Value *, 5> Ops;
7112 // Split the shufflevector operands into sub vectors for the new stN call.
7113 for (unsigned i = 0; i < Factor; i++)
7114 Ops.push_back(Builder.CreateShuffleVector(
7115 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
7117 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
7118 Builder.CreateCall(StNFunc, Ops);
7122 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
7123 unsigned AlignCheck) {
7124 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
7125 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7128 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7129 unsigned SrcAlign, bool IsMemset,
7132 MachineFunction &MF) const {
7133 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
7134 // instruction to materialize the v2i64 zero and one store (with restrictive
7135 // addressing mode). Just do two i64 store of zero-registers.
7137 const Function *F = MF.getFunction();
7138 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
7139 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
7140 (memOpAlign(SrcAlign, DstAlign, 16) ||
7141 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
7145 (memOpAlign(SrcAlign, DstAlign, 8) ||
7146 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
7150 (memOpAlign(SrcAlign, DstAlign, 4) ||
7151 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
7157 // 12-bit optionally shifted immediates are legal for adds.
7158 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7159 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
7164 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
7165 // immediates is the same as for an add or a sub.
7166 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7169 return isLegalAddImmediate(Immed);
7172 /// isLegalAddressingMode - Return true if the addressing mode represented
7173 /// by AM is legal for this target, for a load/store of the specified type.
7174 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7175 const AddrMode &AM, Type *Ty,
7176 unsigned AS) const {
7177 // AArch64 has five basic addressing modes:
7179 // reg + 9-bit signed offset
7180 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
7182 // reg + SIZE_IN_BYTES * reg
7184 // No global is ever allowed as a base.
7188 // No reg+reg+imm addressing.
7189 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
7192 // check reg + imm case:
7193 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
7194 uint64_t NumBytes = 0;
7195 if (Ty->isSized()) {
7196 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
7197 NumBytes = NumBits / 8;
7198 if (!isPowerOf2_64(NumBits))
7203 int64_t Offset = AM.BaseOffs;
7205 // 9-bit signed offset
7206 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
7209 // 12-bit unsigned offset
7210 unsigned shift = Log2_64(NumBytes);
7211 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
7212 // Must be a multiple of NumBytes (NumBytes is a power of 2)
7213 (Offset >> shift) << shift == Offset)
7218 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
7220 if (!AM.Scale || AM.Scale == 1 ||
7221 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
7226 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7227 const AddrMode &AM, Type *Ty,
7228 unsigned AS) const {
7229 // Scaling factors are not free at all.
7230 // Operands | Rt Latency
7231 // -------------------------------------------
7233 // -------------------------------------------
7234 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
7235 // Rt, [Xn, Wm, <extend> #imm] |
7236 if (isLegalAddressingMode(DL, AM, Ty, AS))
7237 // Scale represents reg2 * scale, thus account for 1 if
7238 // it is not equal to 0 or 1.
7239 return AM.Scale != 0 && AM.Scale != 1;
7243 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7244 VT = VT.getScalarType();
7249 switch (VT.getSimpleVT().SimpleTy) {
7261 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7262 // LR is a callee-save register, but we must treat it as clobbered by any call
7263 // site. Hence we include LR in the scratch registers, which are in turn added
7264 // as implicit-defs for stackmaps and patchpoints.
7265 static const MCPhysReg ScratchRegs[] = {
7266 AArch64::X16, AArch64::X17, AArch64::LR, 0
7272 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7273 EVT VT = N->getValueType(0);
7274 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
7275 // it with shift to let it be lowered to UBFX.
7276 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7277 isa<ConstantSDNode>(N->getOperand(1))) {
7278 uint64_t TruncMask = N->getConstantOperandVal(1);
7279 if (isMask_64(TruncMask) &&
7280 N->getOperand(0).getOpcode() == ISD::SRL &&
7281 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7287 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7289 assert(Ty->isIntegerTy());
7291 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7295 int64_t Val = Imm.getSExtValue();
7296 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7299 if ((int64_t)Val < 0)
7302 Val &= (1LL << 32) - 1;
7304 unsigned LZ = countLeadingZeros((uint64_t)Val);
7305 unsigned Shift = (63 - LZ) / 16;
7306 // MOVZ is free so return true for one or fewer MOVK.
7310 // Generate SUBS and CSEL for integer abs.
7311 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7312 EVT VT = N->getValueType(0);
7314 SDValue N0 = N->getOperand(0);
7315 SDValue N1 = N->getOperand(1);
7318 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7319 // and change it to SUB and CSEL.
7320 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7321 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7322 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7323 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7324 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7325 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7327 // Generate SUBS & CSEL.
7329 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7330 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7331 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7332 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7333 SDValue(Cmp.getNode(), 1));
7338 // performXorCombine - Attempts to handle integer ABS.
7339 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7340 TargetLowering::DAGCombinerInfo &DCI,
7341 const AArch64Subtarget *Subtarget) {
7342 if (DCI.isBeforeLegalizeOps())
7345 return performIntegerAbsCombine(N, DAG);
7349 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7351 std::vector<SDNode *> *Created) const {
7352 // fold (sdiv X, pow2)
7353 EVT VT = N->getValueType(0);
7354 if ((VT != MVT::i32 && VT != MVT::i64) ||
7355 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7359 SDValue N0 = N->getOperand(0);
7360 unsigned Lg2 = Divisor.countTrailingZeros();
7361 SDValue Zero = DAG.getConstant(0, DL, VT);
7362 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7364 // Add (N0 < 0) ? Pow2 - 1 : 0;
7366 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7367 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7368 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7371 Created->push_back(Cmp.getNode());
7372 Created->push_back(Add.getNode());
7373 Created->push_back(CSel.getNode());
7378 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7380 // If we're dividing by a positive value, we're done. Otherwise, we must
7381 // negate the result.
7382 if (Divisor.isNonNegative())
7386 Created->push_back(SRA.getNode());
7387 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7390 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7391 TargetLowering::DAGCombinerInfo &DCI,
7392 const AArch64Subtarget *Subtarget) {
7393 if (DCI.isBeforeLegalizeOps())
7396 // Multiplication of a power of two plus/minus one can be done more
7397 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7398 // future CPUs have a cheaper MADD instruction, this may need to be
7399 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7400 // 64-bit is 5 cycles, so this is always a win.
7401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7402 APInt Value = C->getAPIntValue();
7403 EVT VT = N->getValueType(0);
7405 if (Value.isNonNegative()) {
7406 // (mul x, 2^N + 1) => (add (shl x, N), x)
7407 APInt VM1 = Value - 1;
7408 if (VM1.isPowerOf2()) {
7409 SDValue ShiftedVal =
7410 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7411 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7412 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7415 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7416 APInt VP1 = Value + 1;
7417 if (VP1.isPowerOf2()) {
7418 SDValue ShiftedVal =
7419 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7420 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7421 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7425 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7426 APInt VNP1 = -Value + 1;
7427 if (VNP1.isPowerOf2()) {
7428 SDValue ShiftedVal =
7429 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7430 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7431 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7434 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7435 APInt VNM1 = -Value - 1;
7436 if (VNM1.isPowerOf2()) {
7437 SDValue ShiftedVal =
7438 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7439 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7441 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7442 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7449 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7450 SelectionDAG &DAG) {
7451 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7452 // optimize away operation when it's from a constant.
7454 // The general transformation is:
7455 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7456 // AND(VECTOR_CMP(x,y), constant2)
7457 // constant2 = UNARYOP(constant)
7459 // Early exit if this isn't a vector operation, the operand of the
7460 // unary operation isn't a bitwise AND, or if the sizes of the operations
7462 EVT VT = N->getValueType(0);
7463 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7464 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7465 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7468 // Now check that the other operand of the AND is a constant. We could
7469 // make the transformation for non-constant splats as well, but it's unclear
7470 // that would be a benefit as it would not eliminate any operations, just
7471 // perform one more step in scalar code before moving to the vector unit.
7472 if (BuildVectorSDNode *BV =
7473 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7474 // Bail out if the vector isn't a constant.
7475 if (!BV->isConstant())
7478 // Everything checks out. Build up the new and improved node.
7480 EVT IntVT = BV->getValueType(0);
7481 // Create a new constant of the appropriate type for the transformed
7483 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7484 // The AND node needs bitcasts to/from an integer vector type around it.
7485 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7486 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7487 N->getOperand(0)->getOperand(0), MaskConst);
7488 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7495 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7496 const AArch64Subtarget *Subtarget) {
7497 // First try to optimize away the conversion when it's conditionally from
7498 // a constant. Vectors only.
7499 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
7502 EVT VT = N->getValueType(0);
7503 if (VT != MVT::f32 && VT != MVT::f64)
7506 // Only optimize when the source and destination types have the same width.
7507 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7510 // If the result of an integer load is only used by an integer-to-float
7511 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7512 // This eliminates an "integer-to-vector-move" UOP and improves throughput.
7513 SDValue N0 = N->getOperand(0);
7514 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7515 // Do not change the width of a volatile load.
7516 !cast<LoadSDNode>(N0)->isVolatile()) {
7517 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7518 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7519 LN0->getPointerInfo(), LN0->isVolatile(),
7520 LN0->isNonTemporal(), LN0->isInvariant(),
7521 LN0->getAlignment());
7523 // Make sure successors of the original load stay after it by updating them
7524 // to use the new Chain.
7525 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7528 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7529 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7535 /// Fold a floating-point multiply by power of two into floating-point to
7536 /// fixed-point conversion.
7537 static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
7538 const AArch64Subtarget *Subtarget) {
7539 if (!Subtarget->hasNEON())
7542 SDValue Op = N->getOperand(0);
7543 if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
7546 SDValue ConstVec = Op->getOperand(1);
7547 if (!isa<BuildVectorSDNode>(ConstVec))
7550 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
7551 uint32_t FloatBits = FloatTy.getSizeInBits();
7552 if (FloatBits != 32 && FloatBits != 64)
7555 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
7556 uint32_t IntBits = IntTy.getSizeInBits();
7557 if (IntBits != 16 && IntBits != 32 && IntBits != 64)
7560 // Avoid conversions where iN is larger than the float (e.g., float -> i64).
7561 if (IntBits > FloatBits)
7564 BitVector UndefElements;
7565 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
7566 int32_t Bits = IntBits == 64 ? 64 : 32;
7567 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, Bits + 1);
7568 if (C == -1 || C == 0 || C > Bits)
7572 unsigned NumLanes = Op.getValueType().getVectorNumElements();
7577 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
7585 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
7586 unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs
7587 : Intrinsic::aarch64_neon_vcvtfp2fxu;
7589 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ResTy,
7590 DAG.getConstant(IntrinsicOpcode, DL, MVT::i32),
7591 Op->getOperand(0), DAG.getConstant(C, DL, MVT::i32));
7592 // We can handle smaller integers by generating an extra trunc.
7593 if (IntBits < FloatBits)
7594 FixConv = DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), FixConv);
7599 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7600 /// searches for and classifies those shifts.
7601 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7603 if (N.getOpcode() == ISD::SHL)
7605 else if (N.getOpcode() == ISD::SRL)
7610 if (!isa<ConstantSDNode>(N.getOperand(1)))
7613 ShiftAmount = N->getConstantOperandVal(1);
7614 Src = N->getOperand(0);
7618 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7619 /// registers viewed as a high/low pair. This function looks for the pattern:
7620 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7621 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7623 static SDValue tryCombineToEXTR(SDNode *N,
7624 TargetLowering::DAGCombinerInfo &DCI) {
7625 SelectionDAG &DAG = DCI.DAG;
7627 EVT VT = N->getValueType(0);
7629 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7631 if (VT != MVT::i32 && VT != MVT::i64)
7635 uint32_t ShiftLHS = 0;
7637 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7641 uint32_t ShiftRHS = 0;
7643 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7646 // If they're both trying to come from the high part of the register, they're
7647 // not really an EXTR.
7648 if (LHSFromHi == RHSFromHi)
7651 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7655 std::swap(LHS, RHS);
7656 std::swap(ShiftLHS, ShiftRHS);
7659 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7660 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7663 static SDValue tryCombineToBSL(SDNode *N,
7664 TargetLowering::DAGCombinerInfo &DCI) {
7665 EVT VT = N->getValueType(0);
7666 SelectionDAG &DAG = DCI.DAG;
7672 SDValue N0 = N->getOperand(0);
7673 if (N0.getOpcode() != ISD::AND)
7676 SDValue N1 = N->getOperand(1);
7677 if (N1.getOpcode() != ISD::AND)
7680 // We only have to look for constant vectors here since the general, variable
7681 // case can be handled in TableGen.
7682 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7683 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7684 for (int i = 1; i >= 0; --i)
7685 for (int j = 1; j >= 0; --j) {
7686 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7687 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7691 bool FoundMatch = true;
7692 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7693 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7694 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7696 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7703 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7704 N0->getOperand(1 - i), N1->getOperand(1 - j));
7710 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7711 const AArch64Subtarget *Subtarget) {
7712 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7713 if (!EnableAArch64ExtrGeneration)
7715 SelectionDAG &DAG = DCI.DAG;
7716 EVT VT = N->getValueType(0);
7718 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7721 SDValue Res = tryCombineToEXTR(N, DCI);
7725 Res = tryCombineToBSL(N, DCI);
7732 static SDValue performBitcastCombine(SDNode *N,
7733 TargetLowering::DAGCombinerInfo &DCI,
7734 SelectionDAG &DAG) {
7735 // Wait 'til after everything is legalized to try this. That way we have
7736 // legal vector types and such.
7737 if (DCI.isBeforeLegalizeOps())
7740 // Remove extraneous bitcasts around an extract_subvector.
7742 // (v4i16 (bitconvert
7743 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7745 // (extract_subvector ((v8i16 ...), (i64 4)))
7747 // Only interested in 64-bit vectors as the ultimate result.
7748 EVT VT = N->getValueType(0);
7751 if (VT.getSimpleVT().getSizeInBits() != 64)
7753 // Is the operand an extract_subvector starting at the beginning or halfway
7754 // point of the vector? A low half may also come through as an
7755 // EXTRACT_SUBREG, so look for that, too.
7756 SDValue Op0 = N->getOperand(0);
7757 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7758 !(Op0->isMachineOpcode() &&
7759 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7761 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7762 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7763 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7765 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7766 if (idx != AArch64::dsub)
7768 // The dsub reference is equivalent to a lane zero subvector reference.
7771 // Look through the bitcast of the input to the extract.
7772 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7774 SDValue Source = Op0->getOperand(0)->getOperand(0);
7775 // If the source type has twice the number of elements as our destination
7776 // type, we know this is an extract of the high or low half of the vector.
7777 EVT SVT = Source->getValueType(0);
7778 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7781 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7783 // Create the simplified form to just extract the low or high half of the
7784 // vector directly rather than bothering with the bitcasts.
7786 unsigned NumElements = VT.getVectorNumElements();
7788 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7789 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7791 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7792 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7798 static SDValue performConcatVectorsCombine(SDNode *N,
7799 TargetLowering::DAGCombinerInfo &DCI,
7800 SelectionDAG &DAG) {
7802 EVT VT = N->getValueType(0);
7803 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7805 // Optimize concat_vectors of truncated vectors, where the intermediate
7806 // type is illegal, to avoid said illegality, e.g.,
7807 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7808 // (v2i16 (truncate (v2i64)))))
7810 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7811 // (v4i32 (bitcast (v2i64))),
7813 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7814 // on both input and result type, so we might generate worse code.
7815 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7816 if (N->getNumOperands() == 2 &&
7817 N0->getOpcode() == ISD::TRUNCATE &&
7818 N1->getOpcode() == ISD::TRUNCATE) {
7819 SDValue N00 = N0->getOperand(0);
7820 SDValue N10 = N1->getOperand(0);
7821 EVT N00VT = N00.getValueType();
7823 if (N00VT == N10.getValueType() &&
7824 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7825 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7826 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7827 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7828 for (size_t i = 0; i < Mask.size(); ++i)
7830 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7831 DAG.getVectorShuffle(
7833 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7834 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7838 // Wait 'til after everything is legalized to try this. That way we have
7839 // legal vector types and such.
7840 if (DCI.isBeforeLegalizeOps())
7843 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7844 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7845 // canonicalise to that.
7846 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7847 assert(VT.getVectorElementType().getSizeInBits() == 64);
7848 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7849 DAG.getConstant(0, dl, MVT::i64));
7852 // Canonicalise concat_vectors so that the right-hand vector has as few
7853 // bit-casts as possible before its real operation. The primary matching
7854 // destination for these operations will be the narrowing "2" instructions,
7855 // which depend on the operation being performed on this right-hand vector.
7857 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7859 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7861 if (N1->getOpcode() != ISD::BITCAST)
7863 SDValue RHS = N1->getOperand(0);
7864 MVT RHSTy = RHS.getValueType().getSimpleVT();
7865 // If the RHS is not a vector, this is not the pattern we're looking for.
7866 if (!RHSTy.isVector())
7869 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7871 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7872 RHSTy.getVectorNumElements() * 2);
7873 return DAG.getNode(ISD::BITCAST, dl, VT,
7874 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7875 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7879 static SDValue tryCombineFixedPointConvert(SDNode *N,
7880 TargetLowering::DAGCombinerInfo &DCI,
7881 SelectionDAG &DAG) {
7882 // Wait 'til after everything is legalized to try this. That way we have
7883 // legal vector types and such.
7884 if (DCI.isBeforeLegalizeOps())
7886 // Transform a scalar conversion of a value from a lane extract into a
7887 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7888 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7889 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7891 // The second form interacts better with instruction selection and the
7892 // register allocator to avoid cross-class register copies that aren't
7893 // coalescable due to a lane reference.
7895 // Check the operand and see if it originates from a lane extract.
7896 SDValue Op1 = N->getOperand(1);
7897 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7898 // Yep, no additional predication needed. Perform the transform.
7899 SDValue IID = N->getOperand(0);
7900 SDValue Shift = N->getOperand(2);
7901 SDValue Vec = Op1.getOperand(0);
7902 SDValue Lane = Op1.getOperand(1);
7903 EVT ResTy = N->getValueType(0);
7907 // The vector width should be 128 bits by the time we get here, even
7908 // if it started as 64 bits (the extract_vector handling will have
7910 assert(Vec.getValueType().getSizeInBits() == 128 &&
7911 "unexpected vector size on extract_vector_elt!");
7912 if (Vec.getValueType() == MVT::v4i32)
7913 VecResTy = MVT::v4f32;
7914 else if (Vec.getValueType() == MVT::v2i64)
7915 VecResTy = MVT::v2f64;
7917 llvm_unreachable("unexpected vector type!");
7920 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7921 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7926 // AArch64 high-vector "long" operations are formed by performing the non-high
7927 // version on an extract_subvector of each operand which gets the high half:
7929 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7931 // However, there are cases which don't have an extract_high explicitly, but
7932 // have another operation that can be made compatible with one for free. For
7935 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7937 // This routine does the actual conversion of such DUPs, once outer routines
7938 // have determined that everything else is in order.
7939 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7941 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7942 switch (N.getOpcode()) {
7943 case AArch64ISD::DUP:
7944 case AArch64ISD::DUPLANE8:
7945 case AArch64ISD::DUPLANE16:
7946 case AArch64ISD::DUPLANE32:
7947 case AArch64ISD::DUPLANE64:
7948 case AArch64ISD::MOVI:
7949 case AArch64ISD::MOVIshift:
7950 case AArch64ISD::MOVIedit:
7951 case AArch64ISD::MOVImsl:
7952 case AArch64ISD::MVNIshift:
7953 case AArch64ISD::MVNImsl:
7956 // FMOV could be supported, but isn't very useful, as it would only occur
7957 // if you passed a bitcast' floating point immediate to an eligible long
7958 // integer op (addl, smull, ...).
7962 MVT NarrowTy = N.getSimpleValueType();
7963 if (!NarrowTy.is64BitVector())
7966 MVT ElementTy = NarrowTy.getVectorElementType();
7967 unsigned NumElems = NarrowTy.getVectorNumElements();
7968 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7971 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7972 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7973 DAG.getConstant(NumElems, dl, MVT::i64));
7976 static bool isEssentiallyExtractSubvector(SDValue N) {
7977 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7980 return N.getOpcode() == ISD::BITCAST &&
7981 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7984 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7985 struct GenericSetCCInfo {
7986 const SDValue *Opnd0;
7987 const SDValue *Opnd1;
7991 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7992 struct AArch64SetCCInfo {
7994 AArch64CC::CondCode CC;
7997 /// \brief Helper structure to keep track of SetCC information.
7999 GenericSetCCInfo Generic;
8000 AArch64SetCCInfo AArch64;
8003 /// \brief Helper structure to be able to read SetCC information. If set to
8004 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
8005 /// GenericSetCCInfo.
8006 struct SetCCInfoAndKind {
8011 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
8013 /// AArch64 lowered one.
8014 /// \p SetCCInfo is filled accordingly.
8015 /// \post SetCCInfo is meanginfull only when this function returns true.
8016 /// \return True when Op is a kind of SET_CC operation.
8017 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
8018 // If this is a setcc, this is straight forward.
8019 if (Op.getOpcode() == ISD::SETCC) {
8020 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
8021 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
8022 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8023 SetCCInfo.IsAArch64 = false;
8026 // Otherwise, check if this is a matching csel instruction.
8030 if (Op.getOpcode() != AArch64ISD::CSEL)
8032 // Set the information about the operands.
8033 // TODO: we want the operands of the Cmp not the csel
8034 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
8035 SetCCInfo.IsAArch64 = true;
8036 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
8037 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
8039 // Check that the operands matches the constraints:
8040 // (1) Both operands must be constants.
8041 // (2) One must be 1 and the other must be 0.
8042 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
8043 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8046 if (!TValue || !FValue)
8050 if (!TValue->isOne()) {
8051 // Update the comparison when we are interested in !cc.
8052 std::swap(TValue, FValue);
8053 SetCCInfo.Info.AArch64.CC =
8054 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
8056 return TValue->isOne() && FValue->isNullValue();
8059 // Returns true if Op is setcc or zext of setcc.
8060 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
8061 if (isSetCC(Op, Info))
8063 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
8064 isSetCC(Op->getOperand(0), Info));
8067 // The folding we want to perform is:
8068 // (add x, [zext] (setcc cc ...) )
8070 // (csel x, (add x, 1), !cc ...)
8072 // The latter will get matched to a CSINC instruction.
8073 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
8074 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
8075 SDValue LHS = Op->getOperand(0);
8076 SDValue RHS = Op->getOperand(1);
8077 SetCCInfoAndKind InfoAndKind;
8079 // If neither operand is a SET_CC, give up.
8080 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
8081 std::swap(LHS, RHS);
8082 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
8086 // FIXME: This could be generatized to work for FP comparisons.
8087 EVT CmpVT = InfoAndKind.IsAArch64
8088 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
8089 : InfoAndKind.Info.Generic.Opnd0->getValueType();
8090 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
8096 if (InfoAndKind.IsAArch64) {
8097 CCVal = DAG.getConstant(
8098 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8100 Cmp = *InfoAndKind.Info.AArch64.Cmp;
8102 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
8103 *InfoAndKind.Info.Generic.Opnd1,
8104 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
8107 EVT VT = Op->getValueType(0);
8108 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8109 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8112 // The basic add/sub long vector instructions have variants with "2" on the end
8113 // which act on the high-half of their inputs. They are normally matched by
8116 // (add (zeroext (extract_high LHS)),
8117 // (zeroext (extract_high RHS)))
8118 // -> uaddl2 vD, vN, vM
8120 // However, if one of the extracts is something like a duplicate, this
8121 // instruction can still be used profitably. This function puts the DAG into a
8122 // more appropriate form for those patterns to trigger.
8123 static SDValue performAddSubLongCombine(SDNode *N,
8124 TargetLowering::DAGCombinerInfo &DCI,
8125 SelectionDAG &DAG) {
8126 if (DCI.isBeforeLegalizeOps())
8129 MVT VT = N->getSimpleValueType(0);
8130 if (!VT.is128BitVector()) {
8131 if (N->getOpcode() == ISD::ADD)
8132 return performSetccAddFolding(N, DAG);
8136 // Make sure both branches are extended in the same way.
8137 SDValue LHS = N->getOperand(0);
8138 SDValue RHS = N->getOperand(1);
8139 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8140 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8141 LHS.getOpcode() != RHS.getOpcode())
8144 unsigned ExtType = LHS.getOpcode();
8146 // It's not worth doing if at least one of the inputs isn't already an
8147 // extract, but we don't know which it'll be so we have to try both.
8148 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
8149 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
8153 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8154 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
8155 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
8159 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8162 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8165 // Massage DAGs which we can use the high-half "long" operations on into
8166 // something isel will recognize better. E.g.
8168 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
8169 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8170 // (extract_high (v2i64 (dup128 scalar)))))
8172 static SDValue tryCombineLongOpWithDup(SDNode *N,
8173 TargetLowering::DAGCombinerInfo &DCI,
8174 SelectionDAG &DAG) {
8175 if (DCI.isBeforeLegalizeOps())
8178 bool IsIntrinsic = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
8179 SDValue LHS = N->getOperand(IsIntrinsic ? 1 : 0);
8180 SDValue RHS = N->getOperand(IsIntrinsic ? 2 : 1);
8181 assert(LHS.getValueType().is64BitVector() &&
8182 RHS.getValueType().is64BitVector() &&
8183 "unexpected shape for long operation");
8185 // Either node could be a DUP, but it's not worth doing both of them (you'd
8186 // just as well use the non-high version) so look for a corresponding extract
8187 // operation on the other "wing".
8188 if (isEssentiallyExtractSubvector(LHS)) {
8189 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
8192 } else if (isEssentiallyExtractSubvector(RHS)) {
8193 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
8198 // N could either be an intrinsic or a sabsdiff/uabsdiff node.
8200 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
8201 N->getOperand(0), LHS, RHS);
8203 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
8207 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
8208 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
8209 unsigned ElemBits = ElemTy.getSizeInBits();
8211 int64_t ShiftAmount;
8212 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
8213 APInt SplatValue, SplatUndef;
8214 unsigned SplatBitSize;
8216 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
8217 HasAnyUndefs, ElemBits) ||
8218 SplatBitSize != ElemBits)
8221 ShiftAmount = SplatValue.getSExtValue();
8222 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
8223 ShiftAmount = CVN->getSExtValue();
8231 llvm_unreachable("Unknown shift intrinsic");
8232 case Intrinsic::aarch64_neon_sqshl:
8233 Opcode = AArch64ISD::SQSHL_I;
8234 IsRightShift = false;
8236 case Intrinsic::aarch64_neon_uqshl:
8237 Opcode = AArch64ISD::UQSHL_I;
8238 IsRightShift = false;
8240 case Intrinsic::aarch64_neon_srshl:
8241 Opcode = AArch64ISD::SRSHR_I;
8242 IsRightShift = true;
8244 case Intrinsic::aarch64_neon_urshl:
8245 Opcode = AArch64ISD::URSHR_I;
8246 IsRightShift = true;
8248 case Intrinsic::aarch64_neon_sqshlu:
8249 Opcode = AArch64ISD::SQSHLU_I;
8250 IsRightShift = false;
8254 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8256 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8257 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8258 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
8260 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8261 DAG.getConstant(ShiftAmount, dl, MVT::i32));
8267 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
8268 // the intrinsics must be legal and take an i32, this means there's almost
8269 // certainly going to be a zext in the DAG which we can eliminate.
8270 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
8271 SDValue AndN = N->getOperand(2);
8272 if (AndN.getOpcode() != ISD::AND)
8275 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
8276 if (!CMask || CMask->getZExtValue() != Mask)
8279 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
8280 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
8283 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
8284 SelectionDAG &DAG) {
8286 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
8287 DAG.getNode(Opc, dl,
8288 N->getOperand(1).getSimpleValueType(),
8290 DAG.getConstant(0, dl, MVT::i64));
8293 static SDValue performIntrinsicCombine(SDNode *N,
8294 TargetLowering::DAGCombinerInfo &DCI,
8295 const AArch64Subtarget *Subtarget) {
8296 SelectionDAG &DAG = DCI.DAG;
8297 unsigned IID = getIntrinsicID(N);
8301 case Intrinsic::aarch64_neon_vcvtfxs2fp:
8302 case Intrinsic::aarch64_neon_vcvtfxu2fp:
8303 return tryCombineFixedPointConvert(N, DCI, DAG);
8304 case Intrinsic::aarch64_neon_saddv:
8305 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
8306 case Intrinsic::aarch64_neon_uaddv:
8307 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
8308 case Intrinsic::aarch64_neon_sminv:
8309 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
8310 case Intrinsic::aarch64_neon_uminv:
8311 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
8312 case Intrinsic::aarch64_neon_smaxv:
8313 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
8314 case Intrinsic::aarch64_neon_umaxv:
8315 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
8316 case Intrinsic::aarch64_neon_fmax:
8317 return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),
8318 N->getOperand(1), N->getOperand(2));
8319 case Intrinsic::aarch64_neon_fmin:
8320 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),
8321 N->getOperand(1), N->getOperand(2));
8322 case Intrinsic::aarch64_neon_sabd:
8323 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
8324 N->getOperand(1), N->getOperand(2));
8325 case Intrinsic::aarch64_neon_uabd:
8326 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
8327 N->getOperand(1), N->getOperand(2));
8328 case Intrinsic::aarch64_neon_fmaxnm:
8329 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),
8330 N->getOperand(1), N->getOperand(2));
8331 case Intrinsic::aarch64_neon_fminnm:
8332 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0),
8333 N->getOperand(1), N->getOperand(2));
8334 case Intrinsic::aarch64_neon_smull:
8335 case Intrinsic::aarch64_neon_umull:
8336 case Intrinsic::aarch64_neon_pmull:
8337 case Intrinsic::aarch64_neon_sqdmull:
8338 return tryCombineLongOpWithDup(N, DCI, DAG);
8339 case Intrinsic::aarch64_neon_sqshl:
8340 case Intrinsic::aarch64_neon_uqshl:
8341 case Intrinsic::aarch64_neon_sqshlu:
8342 case Intrinsic::aarch64_neon_srshl:
8343 case Intrinsic::aarch64_neon_urshl:
8344 return tryCombineShiftImm(IID, N, DAG);
8345 case Intrinsic::aarch64_crc32b:
8346 case Intrinsic::aarch64_crc32cb:
8347 return tryCombineCRC32(0xff, N, DAG);
8348 case Intrinsic::aarch64_crc32h:
8349 case Intrinsic::aarch64_crc32ch:
8350 return tryCombineCRC32(0xffff, N, DAG);
8355 static SDValue performExtendCombine(SDNode *N,
8356 TargetLowering::DAGCombinerInfo &DCI,
8357 SelectionDAG &DAG) {
8358 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8359 // we can convert that DUP into another extract_high (of a bigger DUP), which
8360 // helps the backend to decide that an sabdl2 would be useful, saving a real
8361 // extract_high operation.
8362 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8363 (N->getOperand(0).getOpcode() == ISD::SABSDIFF ||
8364 N->getOperand(0).getOpcode() == ISD::UABSDIFF)) {
8365 SDNode *ABDNode = N->getOperand(0).getNode();
8366 SDValue NewABD = tryCombineLongOpWithDup(ABDNode, DCI, DAG);
8367 if (!NewABD.getNode())
8370 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8374 // This is effectively a custom type legalization for AArch64.
8376 // Type legalization will split an extend of a small, legal, type to a larger
8377 // illegal type by first splitting the destination type, often creating
8378 // illegal source types, which then get legalized in isel-confusing ways,
8379 // leading to really terrible codegen. E.g.,
8380 // %result = v8i32 sext v8i8 %value
8382 // %losrc = extract_subreg %value, ...
8383 // %hisrc = extract_subreg %value, ...
8384 // %lo = v4i32 sext v4i8 %losrc
8385 // %hi = v4i32 sext v4i8 %hisrc
8386 // Things go rapidly downhill from there.
8388 // For AArch64, the [sz]ext vector instructions can only go up one element
8389 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8390 // take two instructions.
8392 // This implies that the most efficient way to do the extend from v8i8
8393 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8394 // the normal splitting to happen for the v8i16->v8i32.
8396 // This is pre-legalization to catch some cases where the default
8397 // type legalization will create ill-tempered code.
8398 if (!DCI.isBeforeLegalizeOps())
8401 // We're only interested in cleaning things up for non-legal vector types
8402 // here. If both the source and destination are legal, things will just
8403 // work naturally without any fiddling.
8404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8405 EVT ResVT = N->getValueType(0);
8406 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8408 // If the vector type isn't a simple VT, it's beyond the scope of what
8409 // we're worried about here. Let legalization do its thing and hope for
8411 SDValue Src = N->getOperand(0);
8412 EVT SrcVT = Src->getValueType(0);
8413 if (!ResVT.isSimple() || !SrcVT.isSimple())
8416 // If the source VT is a 64-bit vector, we can play games and get the
8417 // better results we want.
8418 if (SrcVT.getSizeInBits() != 64)
8421 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8422 unsigned ElementCount = SrcVT.getVectorNumElements();
8423 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8425 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8427 // Now split the rest of the operation into two halves, each with a 64
8431 unsigned NumElements = ResVT.getVectorNumElements();
8432 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8433 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8434 ResVT.getVectorElementType(), NumElements / 2);
8436 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8437 LoVT.getVectorNumElements());
8438 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8439 DAG.getConstant(0, DL, MVT::i64));
8440 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8441 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8442 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8443 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8445 // Now combine the parts back together so we still have a single result
8446 // like the combiner expects.
8447 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8450 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8451 /// value. The load store optimizer pass will merge them to store pair stores.
8452 /// This has better performance than a splat of the scalar followed by a split
8453 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8454 /// followed by an ext.b and two stores.
8455 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8456 SDValue StVal = St->getValue();
8457 EVT VT = StVal.getValueType();
8459 // Don't replace floating point stores, they possibly won't be transformed to
8460 // stp because of the store pair suppress pass.
8461 if (VT.isFloatingPoint())
8464 // Check for insert vector elements.
8465 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8468 // We can express a splat as store pair(s) for 2 or 4 elements.
8469 unsigned NumVecElts = VT.getVectorNumElements();
8470 if (NumVecElts != 4 && NumVecElts != 2)
8472 SDValue SplatVal = StVal.getOperand(1);
8473 unsigned RemainInsertElts = NumVecElts - 1;
8475 // Check that this is a splat.
8476 while (--RemainInsertElts) {
8477 SDValue NextInsertElt = StVal.getOperand(0);
8478 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8480 if (NextInsertElt.getOperand(1) != SplatVal)
8482 StVal = NextInsertElt;
8484 unsigned OrigAlignment = St->getAlignment();
8485 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8486 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8488 // Create scalar stores. This is at least as good as the code sequence for a
8489 // split unaligned store which is a dup.s, ext.b, and two stores.
8490 // Most of the time the three stores should be replaced by store pair
8491 // instructions (stp).
8493 SDValue BasePtr = St->getBasePtr();
8495 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8496 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8498 unsigned Offset = EltOffset;
8499 while (--NumVecElts) {
8500 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8501 DAG.getConstant(Offset, DL, MVT::i64));
8502 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8503 St->getPointerInfo(), St->isVolatile(),
8504 St->isNonTemporal(), Alignment);
8505 Offset += EltOffset;
8510 static SDValue performSTORECombine(SDNode *N,
8511 TargetLowering::DAGCombinerInfo &DCI,
8513 const AArch64Subtarget *Subtarget) {
8514 if (!DCI.isBeforeLegalize())
8517 StoreSDNode *S = cast<StoreSDNode>(N);
8518 if (S->isVolatile())
8521 // FIXME: The logic for deciding if an unaligned store should be split should
8522 // be included in TLI.allowsMisalignedMemoryAccesses(), and there should be
8523 // a call to that function here.
8525 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8526 // page boundaries. We want to split such stores.
8527 if (!Subtarget->isCyclone())
8530 // Don't split at -Oz.
8531 if (DAG.getMachineFunction().getFunction()->optForMinSize())
8534 SDValue StVal = S->getValue();
8535 EVT VT = StVal.getValueType();
8537 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8538 // those up regresses performance on micro-benchmarks and olden/bh.
8539 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8542 // Split unaligned 16B stores. They are terrible for performance.
8543 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8544 // extensions can use this to mark that it does not want splitting to happen
8545 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8546 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8547 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8548 S->getAlignment() <= 2)
8551 // If we get a splat of a scalar convert this vector store to a store of
8552 // scalars. They will be merged into store pairs thereby removing two
8554 if (SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S))
8555 return ReplacedSplat;
8558 unsigned NumElts = VT.getVectorNumElements() / 2;
8559 // Split VT into two.
8561 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8562 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8563 DAG.getConstant(0, DL, MVT::i64));
8564 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8565 DAG.getConstant(NumElts, DL, MVT::i64));
8566 SDValue BasePtr = S->getBasePtr();
8568 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8569 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8570 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8571 DAG.getConstant(8, DL, MVT::i64));
8572 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8573 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8577 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8578 /// post-increment LD1R.
8579 static SDValue performPostLD1Combine(SDNode *N,
8580 TargetLowering::DAGCombinerInfo &DCI,
8582 if (DCI.isBeforeLegalizeOps())
8585 SelectionDAG &DAG = DCI.DAG;
8586 EVT VT = N->getValueType(0);
8588 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8589 SDNode *LD = N->getOperand(LoadIdx).getNode();
8590 // If it is not LOAD, can not do such combine.
8591 if (LD->getOpcode() != ISD::LOAD)
8594 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8595 EVT MemVT = LoadSDN->getMemoryVT();
8596 // Check if memory operand is the same type as the vector element.
8597 if (MemVT != VT.getVectorElementType())
8600 // Check if there are other uses. If so, do not combine as it will introduce
8602 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8604 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8610 SDValue Addr = LD->getOperand(1);
8611 SDValue Vector = N->getOperand(0);
8612 // Search for a use of the address operand that is an increment.
8613 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8614 Addr.getNode()->use_end(); UI != UE; ++UI) {
8616 if (User->getOpcode() != ISD::ADD
8617 || UI.getUse().getResNo() != Addr.getResNo())
8620 // Check that the add is independent of the load. Otherwise, folding it
8621 // would create a cycle.
8622 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8624 // Also check that add is not used in the vector operand. This would also
8626 if (User->isPredecessorOf(Vector.getNode()))
8629 // If the increment is a constant, it must match the memory ref size.
8630 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8631 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8632 uint32_t IncVal = CInc->getZExtValue();
8633 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8634 if (IncVal != NumBytes)
8636 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8639 // Finally, check that the vector doesn't depend on the load.
8640 // Again, this would create a cycle.
8641 // The load depending on the vector is fine, as that's the case for the
8642 // LD1*post we'll eventually generate anyway.
8643 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8646 SmallVector<SDValue, 8> Ops;
8647 Ops.push_back(LD->getOperand(0)); // Chain
8649 Ops.push_back(Vector); // The vector to be inserted
8650 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8652 Ops.push_back(Addr);
8655 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8656 SDVTList SDTys = DAG.getVTList(Tys);
8657 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8658 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8660 LoadSDN->getMemOperand());
8663 SmallVector<SDValue, 2> NewResults;
8664 NewResults.push_back(SDValue(LD, 0)); // The result of load
8665 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8666 DCI.CombineTo(LD, NewResults);
8667 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8668 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8675 /// This function handles the log2-shuffle pattern produced by the
8676 /// LoopVectorizer for the across vector reduction. It consists of
8677 /// log2(NumVectorElements) steps and, in each step, 2^(s) elements
8678 /// are reduced, where s is an induction variable from 0 to
8679 /// log2(NumVectorElements).
8680 static SDValue tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV,
8682 SelectionDAG &DAG) {
8683 EVT VTy = OpV->getOperand(0).getValueType();
8684 if (!VTy.isVector())
8687 int NumVecElts = VTy.getVectorNumElements();
8688 if (NumVecElts != 4 && NumVecElts != 8 && NumVecElts != 16)
8691 int NumExpectedSteps = APInt(8, NumVecElts).logBase2();
8692 SDValue PreOp = OpV;
8693 // Iterate over each step of the across vector reduction.
8694 for (int CurStep = 0; CurStep != NumExpectedSteps; ++CurStep) {
8695 SDValue CurOp = PreOp.getOperand(0);
8696 SDValue Shuffle = PreOp.getOperand(1);
8697 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE) {
8698 // Try to swap the 1st and 2nd operand as add and min/max instructions
8700 CurOp = PreOp.getOperand(1);
8701 Shuffle = PreOp.getOperand(0);
8702 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
8706 // Check if the input vector is fed by the operator we want to handle,
8707 // except the last step; the very first input vector is not necessarily
8708 // the same operator we are handling.
8709 if (CurOp.getOpcode() != Op && (CurStep != (NumExpectedSteps - 1)))
8712 // Check if it forms one step of the across vector reduction.
8714 // %cur = add %1, %0
8715 // %shuffle = vector_shuffle %cur, <2, 3, u, u>
8716 // %pre = add %cur, %shuffle
8717 if (Shuffle.getOperand(0) != CurOp)
8720 int NumMaskElts = 1 << CurStep;
8721 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Shuffle)->getMask();
8722 // Check mask values in each step.
8723 // We expect the shuffle mask in each step follows a specific pattern
8724 // denoted here by the <M, U> form, where M is a sequence of integers
8725 // starting from NumMaskElts, increasing by 1, and the number integers
8726 // in M should be NumMaskElts. U is a sequence of UNDEFs and the number
8727 // of undef in U should be NumVecElts - NumMaskElts.
8728 // E.g., for <8 x i16>, mask values in each step should be :
8729 // step 0 : <1,u,u,u,u,u,u,u>
8730 // step 1 : <2,3,u,u,u,u,u,u>
8731 // step 2 : <4,5,6,7,u,u,u,u>
8732 for (int i = 0; i < NumVecElts; ++i)
8733 if ((i < NumMaskElts && Mask[i] != (NumMaskElts + i)) ||
8734 (i >= NumMaskElts && !(Mask[i] < 0)))
8742 llvm_unreachable("Unexpected operator for across vector reduction");
8744 Opcode = AArch64ISD::UADDV;
8747 Opcode = AArch64ISD::SMAXV;
8750 Opcode = AArch64ISD::UMAXV;
8753 Opcode = AArch64ISD::SMINV;
8756 Opcode = AArch64ISD::UMINV;
8760 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0),
8761 DAG.getNode(Opcode, DL, PreOp.getSimpleValueType(), PreOp),
8762 DAG.getConstant(0, DL, MVT::i64));
8765 /// Target-specific DAG combine for the across vector min/max reductions.
8766 /// This function specifically handles the final clean-up step of the vector
8767 /// min/max reductions produced by the LoopVectorizer. It is the log2-shuffle
8768 /// pattern, which narrows down and finds the final min/max value from all
8769 /// elements of the vector.
8770 /// For example, for a <16 x i8> vector :
8771 /// svn0 = vector_shuffle %0, undef<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u>
8772 /// %smax0 = smax %arr, svn0
8773 /// %svn1 = vector_shuffle %smax0, undef<4,5,6,7,u,u,u,u,u,u,u,u,u,u,u,u>
8774 /// %smax1 = smax %smax0, %svn1
8775 /// %svn2 = vector_shuffle %smax1, undef<2,3,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
8776 /// %smax2 = smax %smax1, svn2
8777 /// %svn3 = vector_shuffle %smax2, undef<1,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
8778 /// %sc = setcc %smax2, %svn3, gt
8779 /// %n0 = extract_vector_elt %sc, #0
8780 /// %n1 = extract_vector_elt %smax2, #0
8781 /// %n2 = extract_vector_elt $smax2, #1
8782 /// %result = select %n0, %n1, n2
8785 /// %result = extract_vector_elt %1, 0
8786 /// FIXME: Currently this function matches only SMAXV, UMAXV, SMINV, and UMINV.
8787 /// We could also support other types of across lane reduction available
8788 /// in AArch64, including FMAXNMV, FMAXV, FMINNMV, and FMINV.
8790 performAcrossLaneMinMaxReductionCombine(SDNode *N, SelectionDAG &DAG,
8791 const AArch64Subtarget *Subtarget) {
8792 if (!Subtarget->hasNEON())
8795 SDValue N0 = N->getOperand(0);
8796 SDValue IfTrue = N->getOperand(1);
8797 SDValue IfFalse = N->getOperand(2);
8799 // Check if the SELECT merges up the final result of the min/max
8801 if (N0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8802 IfTrue.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8803 IfFalse.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8806 // Expect N0 is fed by SETCC.
8807 SDValue SetCC = N0.getOperand(0);
8808 EVT SetCCVT = SetCC.getValueType();
8809 if (SetCC.getOpcode() != ISD::SETCC || !SetCCVT.isVector() ||
8810 SetCCVT.getVectorElementType() != MVT::i1)
8813 SDValue VectorOp = SetCC.getOperand(0);
8814 unsigned Op = VectorOp->getOpcode();
8815 // Check if the input vector is fed by the operator we want to handle.
8816 if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN && Op != ISD::UMIN)
8819 EVT VTy = VectorOp.getValueType();
8820 if (!VTy.isVector())
8823 EVT EltTy = VTy.getVectorElementType();
8824 if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
8827 // Check if extracting from the same vector.
8829 // %sc = setcc %vector, %svn1, gt
8830 // %n0 = extract_vector_elt %sc, #0
8831 // %n1 = extract_vector_elt %vector, #0
8832 // %n2 = extract_vector_elt $vector, #1
8833 if (!(VectorOp == IfTrue->getOperand(0) &&
8834 VectorOp == IfFalse->getOperand(0)))
8837 // Check if the condition code is matched with the operator type.
8838 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
8839 if ((Op == ISD::SMAX && CC != ISD::SETGT && CC != ISD::SETGE) ||
8840 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) ||
8841 (Op == ISD::SMIN && CC != ISD::SETLT && CC != ISD::SETLE) ||
8842 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE))
8845 // Expect to check only lane 0 from the vector SETCC.
8846 if (!isa<ConstantSDNode>(N0.getOperand(1)) ||
8847 cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue() != 0)
8850 // Expect to extract the true value from lane 0.
8851 if (!isa<ConstantSDNode>(IfTrue.getOperand(1)) ||
8852 cast<ConstantSDNode>(IfTrue.getOperand(1))->getZExtValue() != 0)
8855 // Expect to extract the false value from lane 1.
8856 if (!isa<ConstantSDNode>(IfFalse.getOperand(1)) ||
8857 cast<ConstantSDNode>(IfFalse.getOperand(1))->getZExtValue() != 1)
8860 return tryMatchAcrossLaneShuffleForReduction(N, SetCC, Op, DAG);
8863 /// Target-specific DAG combine for the across vector add reduction.
8864 /// This function specifically handles the final clean-up step of the vector
8865 /// add reduction produced by the LoopVectorizer. It is the log2-shuffle
8866 /// pattern, which adds all elements of a vector together.
8867 /// For example, for a <4 x i32> vector :
8868 /// %1 = vector_shuffle %0, <2,3,u,u>
8870 /// %3 = vector_shuffle %2, <1,u,u,u>
8872 /// %result = extract_vector_elt %4, 0
8875 /// %result = extract_vector_elt %0, 0
8877 performAcrossLaneAddReductionCombine(SDNode *N, SelectionDAG &DAG,
8878 const AArch64Subtarget *Subtarget) {
8879 if (!Subtarget->hasNEON())
8881 SDValue N0 = N->getOperand(0);
8882 SDValue N1 = N->getOperand(1);
8884 // Check if the input vector is fed by the ADD.
8885 if (N0->getOpcode() != ISD::ADD)
8888 // The vector extract idx must constant zero because we only expect the final
8889 // result of the reduction is placed in lane 0.
8890 if (!isa<ConstantSDNode>(N1) || cast<ConstantSDNode>(N1)->getZExtValue() != 0)
8893 EVT VTy = N0.getValueType();
8894 if (!VTy.isVector())
8897 EVT EltTy = VTy.getVectorElementType();
8898 if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
8901 return tryMatchAcrossLaneShuffleForReduction(N, N0, ISD::ADD, DAG);
8904 /// Target-specific DAG combine function for NEON load/store intrinsics
8905 /// to merge base address updates.
8906 static SDValue performNEONPostLDSTCombine(SDNode *N,
8907 TargetLowering::DAGCombinerInfo &DCI,
8908 SelectionDAG &DAG) {
8909 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8912 unsigned AddrOpIdx = N->getNumOperands() - 1;
8913 SDValue Addr = N->getOperand(AddrOpIdx);
8915 // Search for a use of the address operand that is an increment.
8916 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8917 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8919 if (User->getOpcode() != ISD::ADD ||
8920 UI.getUse().getResNo() != Addr.getResNo())
8923 // Check that the add is independent of the load/store. Otherwise, folding
8924 // it would create a cycle.
8925 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8928 // Find the new opcode for the updating load/store.
8929 bool IsStore = false;
8930 bool IsLaneOp = false;
8931 bool IsDupOp = false;
8932 unsigned NewOpc = 0;
8933 unsigned NumVecs = 0;
8934 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8936 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8937 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8939 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8941 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8943 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8944 NumVecs = 2; IsStore = true; break;
8945 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8946 NumVecs = 3; IsStore = true; break;
8947 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8948 NumVecs = 4; IsStore = true; break;
8949 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8951 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8953 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8955 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8956 NumVecs = 2; IsStore = true; break;
8957 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8958 NumVecs = 3; IsStore = true; break;
8959 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8960 NumVecs = 4; IsStore = true; break;
8961 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8962 NumVecs = 2; IsDupOp = true; break;
8963 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8964 NumVecs = 3; IsDupOp = true; break;
8965 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8966 NumVecs = 4; IsDupOp = true; break;
8967 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8968 NumVecs = 2; IsLaneOp = true; break;
8969 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8970 NumVecs = 3; IsLaneOp = true; break;
8971 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8972 NumVecs = 4; IsLaneOp = true; break;
8973 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8974 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8975 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8976 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8977 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8978 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8983 VecTy = N->getOperand(2).getValueType();
8985 VecTy = N->getValueType(0);
8987 // If the increment is a constant, it must match the memory ref size.
8988 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8989 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8990 uint32_t IncVal = CInc->getZExtValue();
8991 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8992 if (IsLaneOp || IsDupOp)
8993 NumBytes /= VecTy.getVectorNumElements();
8994 if (IncVal != NumBytes)
8996 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8998 SmallVector<SDValue, 8> Ops;
8999 Ops.push_back(N->getOperand(0)); // Incoming chain
9000 // Load lane and store have vector list as input.
9001 if (IsLaneOp || IsStore)
9002 for (unsigned i = 2; i < AddrOpIdx; ++i)
9003 Ops.push_back(N->getOperand(i));
9004 Ops.push_back(Addr); // Base register
9009 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
9011 for (n = 0; n < NumResultVecs; ++n)
9013 Tys[n++] = MVT::i64; // Type of write back register
9014 Tys[n] = MVT::Other; // Type of the chain
9015 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
9017 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9018 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
9019 MemInt->getMemoryVT(),
9020 MemInt->getMemOperand());
9023 std::vector<SDValue> NewResults;
9024 for (unsigned i = 0; i < NumResultVecs; ++i) {
9025 NewResults.push_back(SDValue(UpdN.getNode(), i));
9027 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
9028 DCI.CombineTo(N, NewResults);
9029 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9036 // Checks to see if the value is the prescribed width and returns information
9037 // about its extension mode.
9039 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
9040 ExtType = ISD::NON_EXTLOAD;
9041 switch(V.getNode()->getOpcode()) {
9045 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
9046 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
9047 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
9048 ExtType = LoadNode->getExtensionType();
9053 case ISD::AssertSext: {
9054 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
9055 if ((TypeNode->getVT() == MVT::i8 && width == 8)
9056 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
9057 ExtType = ISD::SEXTLOAD;
9062 case ISD::AssertZext: {
9063 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
9064 if ((TypeNode->getVT() == MVT::i8 && width == 8)
9065 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
9066 ExtType = ISD::ZEXTLOAD;
9072 case ISD::TargetConstant: {
9073 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
9083 // This function does a whole lot of voodoo to determine if the tests are
9084 // equivalent without and with a mask. Essentially what happens is that given a
9087 // +-------------+ +-------------+ +-------------+ +-------------+
9088 // | Input | | AddConstant | | CompConstant| | CC |
9089 // +-------------+ +-------------+ +-------------+ +-------------+
9091 // V V | +----------+
9092 // +-------------+ +----+ | |
9093 // | ADD | |0xff| | |
9094 // +-------------+ +----+ | |
9097 // +-------------+ | |
9099 // +-------------+ | |
9108 // The AND node may be safely removed for some combinations of inputs. In
9109 // particular we need to take into account the extension type of the Input,
9110 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
9111 // width of the input (this can work for any width inputs, the above graph is
9112 // specific to 8 bits.
9114 // The specific equations were worked out by generating output tables for each
9115 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
9116 // problem was simplified by working with 4 bit inputs, which means we only
9117 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
9118 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
9119 // patterns present in both extensions (0,7). For every distinct set of
9120 // AddConstant and CompConstants bit patterns we can consider the masked and
9121 // unmasked versions to be equivalent if the result of this function is true for
9122 // all 16 distinct bit patterns of for the current extension type of Input (w0).
9125 // and w10, w8, #0x0f
9127 // cset w9, AArch64CC
9129 // cset w11, AArch64CC
9134 // Since the above function shows when the outputs are equivalent it defines
9135 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
9136 // would be expensive to run during compiles. The equations below were written
9137 // in a test harness that confirmed they gave equivalent outputs to the above
9138 // for all inputs function, so they can be used determine if the removal is
9141 // isEquivalentMaskless() is the code for testing if the AND can be removed
9142 // factored out of the DAG recognition as the DAG can take several forms.
9145 bool isEquivalentMaskless(unsigned CC, unsigned width,
9146 ISD::LoadExtType ExtType, signed AddConstant,
9147 signed CompConstant) {
9148 // By being careful about our equations and only writing the in term
9149 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
9150 // make them generally applicable to all bit widths.
9151 signed MaxUInt = (1 << width);
9153 // For the purposes of these comparisons sign extending the type is
9154 // equivalent to zero extending the add and displacing it by half the integer
9155 // width. Provided we are careful and make sure our equations are valid over
9156 // the whole range we can just adjust the input and avoid writing equations
9157 // for sign extended inputs.
9158 if (ExtType == ISD::SEXTLOAD)
9159 AddConstant -= (1 << (width-1));
9163 case AArch64CC::GT: {
9164 if ((AddConstant == 0) ||
9165 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
9166 (AddConstant >= 0 && CompConstant < 0) ||
9167 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
9171 case AArch64CC::GE: {
9172 if ((AddConstant == 0) ||
9173 (AddConstant >= 0 && CompConstant <= 0) ||
9174 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
9178 case AArch64CC::LS: {
9179 if ((AddConstant >= 0 && CompConstant < 0) ||
9180 (AddConstant <= 0 && CompConstant >= -1 &&
9181 CompConstant < AddConstant + MaxUInt))
9185 case AArch64CC::MI: {
9186 if ((AddConstant == 0) ||
9187 (AddConstant > 0 && CompConstant <= 0) ||
9188 (AddConstant < 0 && CompConstant <= AddConstant))
9192 case AArch64CC::HS: {
9193 if ((AddConstant >= 0 && CompConstant <= 0) ||
9194 (AddConstant <= 0 && CompConstant >= 0 &&
9195 CompConstant <= AddConstant + MaxUInt))
9199 case AArch64CC::NE: {
9200 if ((AddConstant > 0 && CompConstant < 0) ||
9201 (AddConstant < 0 && CompConstant >= 0 &&
9202 CompConstant < AddConstant + MaxUInt) ||
9203 (AddConstant >= 0 && CompConstant >= 0 &&
9204 CompConstant >= AddConstant) ||
9205 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
9214 case AArch64CC::Invalid:
9222 SDValue performCONDCombine(SDNode *N,
9223 TargetLowering::DAGCombinerInfo &DCI,
9224 SelectionDAG &DAG, unsigned CCIndex,
9225 unsigned CmpIndex) {
9226 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
9227 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
9228 unsigned CondOpcode = SubsNode->getOpcode();
9230 if (CondOpcode != AArch64ISD::SUBS)
9233 // There is a SUBS feeding this condition. Is it fed by a mask we can
9236 SDNode *AndNode = SubsNode->getOperand(0).getNode();
9237 unsigned MaskBits = 0;
9239 if (AndNode->getOpcode() != ISD::AND)
9242 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
9243 uint32_t CNV = CN->getZExtValue();
9246 else if (CNV == 65535)
9253 SDValue AddValue = AndNode->getOperand(0);
9255 if (AddValue.getOpcode() != ISD::ADD)
9258 // The basic dag structure is correct, grab the inputs and validate them.
9260 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
9261 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
9262 SDValue SubsInputValue = SubsNode->getOperand(1);
9264 // The mask is present and the provenance of all the values is a smaller type,
9265 // lets see if the mask is superfluous.
9267 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
9268 !isa<ConstantSDNode>(SubsInputValue.getNode()))
9271 ISD::LoadExtType ExtType;
9273 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
9274 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
9275 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
9278 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
9279 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
9280 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
9283 // The AND is not necessary, remove it.
9285 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
9286 SubsNode->getValueType(1));
9287 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
9289 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
9290 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
9292 return SDValue(N, 0);
9295 // Optimize compare with zero and branch.
9296 static SDValue performBRCONDCombine(SDNode *N,
9297 TargetLowering::DAGCombinerInfo &DCI,
9298 SelectionDAG &DAG) {
9299 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
9302 SDValue Chain = N->getOperand(0);
9303 SDValue Dest = N->getOperand(1);
9304 SDValue CCVal = N->getOperand(2);
9305 SDValue Cmp = N->getOperand(3);
9307 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
9308 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
9309 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
9312 unsigned CmpOpc = Cmp.getOpcode();
9313 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
9316 // Only attempt folding if there is only one use of the flag and no use of the
9318 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
9321 SDValue LHS = Cmp.getOperand(0);
9322 SDValue RHS = Cmp.getOperand(1);
9324 assert(LHS.getValueType() == RHS.getValueType() &&
9325 "Expected the value type to be the same for both operands!");
9326 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
9329 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
9330 std::swap(LHS, RHS);
9332 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
9335 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9336 LHS.getOpcode() == ISD::SRL)
9339 // Fold the compare into the branch instruction.
9341 if (CC == AArch64CC::EQ)
9342 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9344 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9346 // Do not add new nodes to DAG combiner worklist.
9347 DCI.CombineTo(N, BR, false);
9352 // vselect (v1i1 setcc) ->
9353 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
9354 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
9355 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
9357 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
9358 SDValue N0 = N->getOperand(0);
9359 EVT CCVT = N0.getValueType();
9361 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9362 CCVT.getVectorElementType() != MVT::i1)
9365 EVT ResVT = N->getValueType(0);
9366 EVT CmpVT = N0.getOperand(0).getValueType();
9367 // Only combine when the result type is of the same size as the compared
9369 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
9372 SDValue IfTrue = N->getOperand(1);
9373 SDValue IfFalse = N->getOperand(2);
9375 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
9376 N0.getOperand(0), N0.getOperand(1),
9377 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9378 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
9382 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
9383 /// the compare-mask instructions rather than going via NZCV, even if LHS and
9384 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
9385 /// with a vector one followed by a DUP shuffle on the result.
9386 static SDValue performSelectCombine(SDNode *N,
9387 TargetLowering::DAGCombinerInfo &DCI) {
9388 SelectionDAG &DAG = DCI.DAG;
9389 SDValue N0 = N->getOperand(0);
9390 EVT ResVT = N->getValueType(0);
9392 if (N0.getOpcode() != ISD::SETCC)
9395 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
9396 // scalar SetCCResultType. We also don't expect vectors, because we assume
9397 // that selects fed by vector SETCCs are canonicalized to VSELECT.
9398 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
9399 "Scalar-SETCC feeding SELECT has unexpected result type!");
9401 // If NumMaskElts == 0, the comparison is larger than select result. The
9402 // largest real NEON comparison is 64-bits per lane, which means the result is
9403 // at most 32-bits and an illegal vector. Just bail out for now.
9404 EVT SrcVT = N0.getOperand(0).getValueType();
9406 // Don't try to do this optimization when the setcc itself has i1 operands.
9407 // There are no legal vectors of i1, so this would be pointless.
9408 if (SrcVT == MVT::i1)
9411 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
9412 if (!ResVT.isVector() || NumMaskElts == 0)
9415 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
9416 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
9418 // Also bail out if the vector CCVT isn't the same size as ResVT.
9419 // This can happen if the SETCC operand size doesn't divide the ResVT size
9420 // (e.g., f64 vs v3f32).
9421 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
9424 // Make sure we didn't create illegal types, if we're not supposed to.
9425 assert(DCI.isBeforeLegalize() ||
9426 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
9428 // First perform a vector comparison, where lane 0 is the one we're interested
9432 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
9434 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
9435 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
9437 // Now duplicate the comparison mask we want across all other lanes.
9438 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
9439 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
9440 Mask = DAG.getNode(ISD::BITCAST, DL,
9441 ResVT.changeVectorElementTypeToInteger(), Mask);
9443 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
9446 /// Get rid of unnecessary NVCASTs (that don't change the type).
9447 static SDValue performNVCASTCombine(SDNode *N) {
9448 if (N->getValueType(0) == N->getOperand(0).getValueType())
9449 return N->getOperand(0);
9454 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
9455 DAGCombinerInfo &DCI) const {
9456 SelectionDAG &DAG = DCI.DAG;
9457 switch (N->getOpcode()) {
9462 return performAddSubLongCombine(N, DCI, DAG);
9464 return performXorCombine(N, DAG, DCI, Subtarget);
9466 return performMulCombine(N, DAG, DCI, Subtarget);
9467 case ISD::SINT_TO_FP:
9468 case ISD::UINT_TO_FP:
9469 return performIntToFpCombine(N, DAG, Subtarget);
9470 case ISD::FP_TO_SINT:
9471 case ISD::FP_TO_UINT:
9472 return performFpToIntCombine(N, DAG, Subtarget);
9474 return performORCombine(N, DCI, Subtarget);
9475 case ISD::INTRINSIC_WO_CHAIN:
9476 return performIntrinsicCombine(N, DCI, Subtarget);
9477 case ISD::ANY_EXTEND:
9478 case ISD::ZERO_EXTEND:
9479 case ISD::SIGN_EXTEND:
9480 return performExtendCombine(N, DCI, DAG);
9482 return performBitcastCombine(N, DCI, DAG);
9483 case ISD::CONCAT_VECTORS:
9484 return performConcatVectorsCombine(N, DCI, DAG);
9486 SDValue RV = performSelectCombine(N, DCI);
9488 RV = performAcrossLaneMinMaxReductionCombine(N, DAG, Subtarget);
9492 return performVSelectCombine(N, DCI.DAG);
9494 return performSTORECombine(N, DCI, DAG, Subtarget);
9495 case AArch64ISD::BRCOND:
9496 return performBRCONDCombine(N, DCI, DAG);
9497 case AArch64ISD::CSEL:
9498 return performCONDCombine(N, DCI, DAG, 2, 3);
9499 case AArch64ISD::DUP:
9500 return performPostLD1Combine(N, DCI, false);
9501 case AArch64ISD::NVCAST:
9502 return performNVCASTCombine(N);
9503 case ISD::INSERT_VECTOR_ELT:
9504 return performPostLD1Combine(N, DCI, true);
9505 case ISD::EXTRACT_VECTOR_ELT:
9506 return performAcrossLaneAddReductionCombine(N, DAG, Subtarget);
9507 case ISD::INTRINSIC_VOID:
9508 case ISD::INTRINSIC_W_CHAIN:
9509 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9510 case Intrinsic::aarch64_neon_ld2:
9511 case Intrinsic::aarch64_neon_ld3:
9512 case Intrinsic::aarch64_neon_ld4:
9513 case Intrinsic::aarch64_neon_ld1x2:
9514 case Intrinsic::aarch64_neon_ld1x3:
9515 case Intrinsic::aarch64_neon_ld1x4:
9516 case Intrinsic::aarch64_neon_ld2lane:
9517 case Intrinsic::aarch64_neon_ld3lane:
9518 case Intrinsic::aarch64_neon_ld4lane:
9519 case Intrinsic::aarch64_neon_ld2r:
9520 case Intrinsic::aarch64_neon_ld3r:
9521 case Intrinsic::aarch64_neon_ld4r:
9522 case Intrinsic::aarch64_neon_st2:
9523 case Intrinsic::aarch64_neon_st3:
9524 case Intrinsic::aarch64_neon_st4:
9525 case Intrinsic::aarch64_neon_st1x2:
9526 case Intrinsic::aarch64_neon_st1x3:
9527 case Intrinsic::aarch64_neon_st1x4:
9528 case Intrinsic::aarch64_neon_st2lane:
9529 case Intrinsic::aarch64_neon_st3lane:
9530 case Intrinsic::aarch64_neon_st4lane:
9531 return performNEONPostLDSTCombine(N, DCI, DAG);
9539 // Check if the return value is used as only a return value, as otherwise
9540 // we can't perform a tail-call. In particular, we need to check for
9541 // target ISD nodes that are returns and any other "odd" constructs
9542 // that the generic analysis code won't necessarily catch.
9543 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9544 SDValue &Chain) const {
9545 if (N->getNumValues() != 1)
9547 if (!N->hasNUsesOfValue(1, 0))
9550 SDValue TCChain = Chain;
9551 SDNode *Copy = *N->use_begin();
9552 if (Copy->getOpcode() == ISD::CopyToReg) {
9553 // If the copy has a glue operand, we conservatively assume it isn't safe to
9554 // perform a tail call.
9555 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9558 TCChain = Copy->getOperand(0);
9559 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9562 bool HasRet = false;
9563 for (SDNode *Node : Copy->uses()) {
9564 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9576 // Return whether the an instruction can potentially be optimized to a tail
9577 // call. This will cause the optimizers to attempt to move, or duplicate,
9578 // return instructions to help enable tail call optimizations for this
9580 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9581 if (!CI->isTailCall())
9587 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9589 ISD::MemIndexedMode &AM,
9591 SelectionDAG &DAG) const {
9592 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9595 Base = Op->getOperand(0);
9596 // All of the indexed addressing mode instructions take a signed
9597 // 9 bit immediate offset.
9598 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9599 int64_t RHSC = (int64_t)RHS->getZExtValue();
9600 if (RHSC >= 256 || RHSC <= -256)
9602 IsInc = (Op->getOpcode() == ISD::ADD);
9603 Offset = Op->getOperand(1);
9609 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9611 ISD::MemIndexedMode &AM,
9612 SelectionDAG &DAG) const {
9615 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9616 VT = LD->getMemoryVT();
9617 Ptr = LD->getBasePtr();
9618 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9619 VT = ST->getMemoryVT();
9620 Ptr = ST->getBasePtr();
9625 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9627 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9631 bool AArch64TargetLowering::getPostIndexedAddressParts(
9632 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9633 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9636 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9637 VT = LD->getMemoryVT();
9638 Ptr = LD->getBasePtr();
9639 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9640 VT = ST->getMemoryVT();
9641 Ptr = ST->getBasePtr();
9646 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9648 // Post-indexing updates the base, so it's not a valid transform
9649 // if that's not the same as the load's pointer.
9652 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9656 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9657 SelectionDAG &DAG) {
9659 SDValue Op = N->getOperand(0);
9661 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9665 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9666 DAG.getUNDEF(MVT::i32), Op,
9667 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9669 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9670 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9673 void AArch64TargetLowering::ReplaceNodeResults(
9674 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9675 switch (N->getOpcode()) {
9677 llvm_unreachable("Don't know how to custom expand this");
9679 ReplaceBITCASTResults(N, Results, DAG);
9681 case ISD::FP_TO_UINT:
9682 case ISD::FP_TO_SINT:
9683 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9684 // Let normal code take care of it by not adding anything to Results.
9689 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9693 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
9694 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9695 // reciprocal if there are three or more FDIVs.
9699 TargetLoweringBase::LegalizeTypeAction
9700 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9701 MVT SVT = VT.getSimpleVT();
9702 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9703 // v4i16, v2i32 instead of to promote.
9704 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9705 || SVT == MVT::v1f32)
9706 return TypeWidenVector;
9708 return TargetLoweringBase::getPreferredVectorAction(VT);
9711 // Loads and stores less than 128-bits are already atomic; ones above that
9712 // are doomed anyway, so defer to the default libcall and blame the OS when
9714 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9715 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9719 // Loads and stores less than 128-bits are already atomic; ones above that
9720 // are doomed anyway, so defer to the default libcall and blame the OS when
9722 TargetLowering::AtomicExpansionKind
9723 AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9724 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9725 return Size == 128 ? AtomicExpansionKind::LLSC : AtomicExpansionKind::None;
9728 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9729 TargetLowering::AtomicExpansionKind
9730 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9731 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9732 return Size <= 128 ? AtomicExpansionKind::LLSC : AtomicExpansionKind::None;
9735 bool AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
9736 AtomicCmpXchgInst *AI) const {
9740 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9741 AtomicOrdering Ord) const {
9742 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9743 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9744 bool IsAcquire = isAtLeastAcquire(Ord);
9746 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9747 // intrinsic must return {i64, i64} and we have to recombine them into a
9748 // single i128 here.
9749 if (ValTy->getPrimitiveSizeInBits() == 128) {
9751 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9752 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9754 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9755 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9757 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9758 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9759 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9760 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9761 return Builder.CreateOr(
9762 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9765 Type *Tys[] = { Addr->getType() };
9767 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9768 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9770 return Builder.CreateTruncOrBitCast(
9771 Builder.CreateCall(Ldxr, Addr),
9772 cast<PointerType>(Addr->getType())->getElementType());
9775 void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
9776 IRBuilder<> &Builder) const {
9777 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9779 llvm::Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex));
9782 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9783 Value *Val, Value *Addr,
9784 AtomicOrdering Ord) const {
9785 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9786 bool IsRelease = isAtLeastRelease(Ord);
9788 // Since the intrinsics must have legal type, the i128 intrinsics take two
9789 // parameters: "i64, i64". We must marshal Val into the appropriate form
9791 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9793 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9794 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9795 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9797 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9798 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9799 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9800 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9804 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9805 Type *Tys[] = { Addr->getType() };
9806 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9808 return Builder.CreateCall(Stxr,
9809 {Builder.CreateZExtOrBitCast(
9810 Val, Stxr->getFunctionType()->getParamType(0)),
9814 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9815 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9816 return Ty->isArrayTy();
9819 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,