1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/Support/MathExtras.h"
33 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
34 assert (TM.getSubtarget<AArch64Subtarget>().isTargetELF() &&
35 "unknown subtarget type");
36 return new AArch64ElfTargetObjectFile();
39 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
40 : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
42 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
44 // SIMD compares set the entire lane's bits to 1
45 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
47 // Scalar register <-> type mapping
48 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
49 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
51 if (Subtarget->hasFPARMv8()) {
52 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
53 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
54 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
55 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
58 if (Subtarget->hasNEON()) {
60 addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass);
61 addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass);
62 addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass);
63 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
64 addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
65 addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
66 addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
67 addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass);
68 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
69 addRegisterClass(MVT::v2f32, &AArch64::FPR64RegClass);
70 addRegisterClass(MVT::v16i8, &AArch64::FPR128RegClass);
71 addRegisterClass(MVT::v8i16, &AArch64::FPR128RegClass);
72 addRegisterClass(MVT::v4i32, &AArch64::FPR128RegClass);
73 addRegisterClass(MVT::v2i64, &AArch64::FPR128RegClass);
74 addRegisterClass(MVT::v4f32, &AArch64::FPR128RegClass);
75 addRegisterClass(MVT::v2f64, &AArch64::FPR128RegClass);
78 computeRegisterProperties();
80 // We combine OR nodes for bitfield and NEON BSL operations.
81 setTargetDAGCombine(ISD::OR);
83 setTargetDAGCombine(ISD::AND);
84 setTargetDAGCombine(ISD::SRA);
85 setTargetDAGCombine(ISD::SRL);
86 setTargetDAGCombine(ISD::SHL);
88 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
89 setTargetDAGCombine(ISD::INTRINSIC_VOID);
90 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
92 // AArch64 does not have i1 loads, or much of anything for i1 really.
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
95 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
97 setStackPointerRegisterToSaveRestore(AArch64::XSP);
98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
99 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
100 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
102 // We'll lower globals to wrappers for selection.
103 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
104 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
106 // A64 instructions have the comparison predicate attached to the user of the
107 // result, but having a separate comparison is valuable for matching.
108 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
109 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
110 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
111 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
113 setOperationAction(ISD::SELECT, MVT::i32, Custom);
114 setOperationAction(ISD::SELECT, MVT::i64, Custom);
115 setOperationAction(ISD::SELECT, MVT::f32, Custom);
116 setOperationAction(ISD::SELECT, MVT::f64, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
121 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
123 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
125 setOperationAction(ISD::SETCC, MVT::i32, Custom);
126 setOperationAction(ISD::SETCC, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::f32, Custom);
128 setOperationAction(ISD::SETCC, MVT::f64, Custom);
130 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
131 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::VASTART, MVT::Other, Custom);
135 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
136 setOperationAction(ISD::VAEND, MVT::Other, Expand);
137 setOperationAction(ISD::VAARG, MVT::Other, Expand);
139 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
140 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
142 setOperationAction(ISD::ROTL, MVT::i32, Expand);
143 setOperationAction(ISD::ROTL, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i32, Expand);
146 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
148 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
150 setOperationAction(ISD::SREM, MVT::i32, Expand);
151 setOperationAction(ISD::SREM, MVT::i64, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
160 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
161 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
163 // Legal floating-point operations.
164 setOperationAction(ISD::FABS, MVT::f32, Legal);
165 setOperationAction(ISD::FABS, MVT::f64, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
170 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
171 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
173 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
174 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
176 setOperationAction(ISD::FNEG, MVT::f32, Legal);
177 setOperationAction(ISD::FNEG, MVT::f64, Legal);
179 setOperationAction(ISD::FRINT, MVT::f32, Legal);
180 setOperationAction(ISD::FRINT, MVT::f64, Legal);
182 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
183 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
185 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
186 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
188 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
189 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
190 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
192 // Illegal floating-point operations.
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
196 setOperationAction(ISD::FCOS, MVT::f32, Expand);
197 setOperationAction(ISD::FCOS, MVT::f64, Expand);
199 setOperationAction(ISD::FEXP, MVT::f32, Expand);
200 setOperationAction(ISD::FEXP, MVT::f64, Expand);
202 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
203 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
205 setOperationAction(ISD::FLOG, MVT::f32, Expand);
206 setOperationAction(ISD::FLOG, MVT::f64, Expand);
208 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
209 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
211 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
212 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
214 setOperationAction(ISD::FPOW, MVT::f32, Expand);
215 setOperationAction(ISD::FPOW, MVT::f64, Expand);
217 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
218 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
220 setOperationAction(ISD::FREM, MVT::f32, Expand);
221 setOperationAction(ISD::FREM, MVT::f64, Expand);
223 setOperationAction(ISD::FSIN, MVT::f32, Expand);
224 setOperationAction(ISD::FSIN, MVT::f64, Expand);
226 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
227 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
229 // Virtually no operation on f128 is legal, but LLVM can't expand them when
230 // there's a valid register class, so we need custom operations in most cases.
231 setOperationAction(ISD::FABS, MVT::f128, Expand);
232 setOperationAction(ISD::FADD, MVT::f128, Custom);
233 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
234 setOperationAction(ISD::FCOS, MVT::f128, Expand);
235 setOperationAction(ISD::FDIV, MVT::f128, Custom);
236 setOperationAction(ISD::FMA, MVT::f128, Expand);
237 setOperationAction(ISD::FMUL, MVT::f128, Custom);
238 setOperationAction(ISD::FNEG, MVT::f128, Expand);
239 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
240 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
241 setOperationAction(ISD::FPOW, MVT::f128, Expand);
242 setOperationAction(ISD::FREM, MVT::f128, Expand);
243 setOperationAction(ISD::FRINT, MVT::f128, Expand);
244 setOperationAction(ISD::FSIN, MVT::f128, Expand);
245 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
246 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
247 setOperationAction(ISD::FSUB, MVT::f128, Custom);
248 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
249 setOperationAction(ISD::SETCC, MVT::f128, Custom);
250 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
251 setOperationAction(ISD::SELECT, MVT::f128, Expand);
252 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
253 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
255 // Lowering for many of the conversions is actually specified by the non-f128
256 // type. The LowerXXX function will be trivial when f128 isn't involved.
257 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
259 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
260 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
261 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
262 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
263 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
265 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
266 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
267 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
268 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
269 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
270 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
272 // i128 shift operation support
273 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
274 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
275 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
277 // This prevents LLVM trying to compress double constants into a floating
278 // constant-pool entry and trying to load from there. It's of doubtful benefit
279 // for A64: we'd need LDR followed by FCVT, I believe.
280 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
281 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
282 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
284 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
285 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
286 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
287 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
288 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
289 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
291 setExceptionPointerRegister(AArch64::X0);
292 setExceptionSelectorRegister(AArch64::X1);
294 if (Subtarget->hasNEON()) {
295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Expand);
296 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
297 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
298 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v1i64, Expand);
299 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v16i8, Expand);
300 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Expand);
301 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
302 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Expand);
304 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i8, Custom);
305 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
306 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
307 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i16, Custom);
308 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
309 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
310 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i32, Custom);
311 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
314 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
315 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
316 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
317 setOperationAction(ISD::BUILD_VECTOR, MVT::v1f64, Custom);
318 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
320 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
321 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
322 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
323 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
324 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
325 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
326 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
327 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
328 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom);
329 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
330 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom);
331 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
333 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32, Legal);
334 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal);
335 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
336 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
337 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
338 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal);
339 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal);
341 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i8, Custom);
342 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i16, Custom);
343 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
344 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
345 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
347 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
348 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
349 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
350 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
351 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
352 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
353 setOperationAction(ISD::SETCC, MVT::v1i64, Custom);
354 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
355 setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
356 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
357 setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
358 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
360 setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
361 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
362 setOperationAction(ISD::FFLOOR, MVT::v1f64, Legal);
363 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
365 setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
366 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
367 setOperationAction(ISD::FCEIL, MVT::v1f64, Legal);
368 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
370 setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
371 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
372 setOperationAction(ISD::FTRUNC, MVT::v1f64, Legal);
373 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
375 setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
376 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
377 setOperationAction(ISD::FRINT, MVT::v1f64, Legal);
378 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
380 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal);
381 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
382 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Legal);
383 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
385 setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
386 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
387 setOperationAction(ISD::FROUND, MVT::v1f64, Legal);
388 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
390 setOperationAction(ISD::SINT_TO_FP, MVT::v1i8, Custom);
391 setOperationAction(ISD::SINT_TO_FP, MVT::v1i16, Custom);
392 setOperationAction(ISD::SINT_TO_FP, MVT::v1i32, Custom);
393 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
394 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
395 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
397 setOperationAction(ISD::UINT_TO_FP, MVT::v1i8, Custom);
398 setOperationAction(ISD::UINT_TO_FP, MVT::v1i16, Custom);
399 setOperationAction(ISD::UINT_TO_FP, MVT::v1i32, Custom);
400 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
401 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
402 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
404 setOperationAction(ISD::FP_TO_SINT, MVT::v1i8, Custom);
405 setOperationAction(ISD::FP_TO_SINT, MVT::v1i16, Custom);
406 setOperationAction(ISD::FP_TO_SINT, MVT::v1i32, Custom);
407 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
408 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
409 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Custom);
411 setOperationAction(ISD::FP_TO_UINT, MVT::v1i8, Custom);
412 setOperationAction(ISD::FP_TO_UINT, MVT::v1i16, Custom);
413 setOperationAction(ISD::FP_TO_UINT, MVT::v1i32, Custom);
414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
416 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Custom);
418 // Neon does not support vector divide/remainder operations except
419 // floating-point divide.
420 setOperationAction(ISD::SDIV, MVT::v1i8, Expand);
421 setOperationAction(ISD::SDIV, MVT::v8i8, Expand);
422 setOperationAction(ISD::SDIV, MVT::v16i8, Expand);
423 setOperationAction(ISD::SDIV, MVT::v1i16, Expand);
424 setOperationAction(ISD::SDIV, MVT::v4i16, Expand);
425 setOperationAction(ISD::SDIV, MVT::v8i16, Expand);
426 setOperationAction(ISD::SDIV, MVT::v1i32, Expand);
427 setOperationAction(ISD::SDIV, MVT::v2i32, Expand);
428 setOperationAction(ISD::SDIV, MVT::v4i32, Expand);
429 setOperationAction(ISD::SDIV, MVT::v1i64, Expand);
430 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
432 setOperationAction(ISD::UDIV, MVT::v1i8, Expand);
433 setOperationAction(ISD::UDIV, MVT::v8i8, Expand);
434 setOperationAction(ISD::UDIV, MVT::v16i8, Expand);
435 setOperationAction(ISD::UDIV, MVT::v1i16, Expand);
436 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
437 setOperationAction(ISD::UDIV, MVT::v8i16, Expand);
438 setOperationAction(ISD::UDIV, MVT::v1i32, Expand);
439 setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
440 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
441 setOperationAction(ISD::UDIV, MVT::v1i64, Expand);
442 setOperationAction(ISD::UDIV, MVT::v2i64, Expand);
444 setOperationAction(ISD::SREM, MVT::v1i8, Expand);
445 setOperationAction(ISD::SREM, MVT::v8i8, Expand);
446 setOperationAction(ISD::SREM, MVT::v16i8, Expand);
447 setOperationAction(ISD::SREM, MVT::v1i16, Expand);
448 setOperationAction(ISD::SREM, MVT::v4i16, Expand);
449 setOperationAction(ISD::SREM, MVT::v8i16, Expand);
450 setOperationAction(ISD::SREM, MVT::v1i32, Expand);
451 setOperationAction(ISD::SREM, MVT::v2i32, Expand);
452 setOperationAction(ISD::SREM, MVT::v4i32, Expand);
453 setOperationAction(ISD::SREM, MVT::v1i64, Expand);
454 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
456 setOperationAction(ISD::UREM, MVT::v1i8, Expand);
457 setOperationAction(ISD::UREM, MVT::v8i8, Expand);
458 setOperationAction(ISD::UREM, MVT::v16i8, Expand);
459 setOperationAction(ISD::UREM, MVT::v1i16, Expand);
460 setOperationAction(ISD::UREM, MVT::v4i16, Expand);
461 setOperationAction(ISD::UREM, MVT::v8i16, Expand);
462 setOperationAction(ISD::UREM, MVT::v1i32, Expand);
463 setOperationAction(ISD::UREM, MVT::v2i32, Expand);
464 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
465 setOperationAction(ISD::UREM, MVT::v1i64, Expand);
466 setOperationAction(ISD::UREM, MVT::v2i64, Expand);
468 setOperationAction(ISD::FREM, MVT::v2f32, Expand);
469 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
470 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
471 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
473 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
474 setOperationAction(ISD::SELECT, MVT::v16i8, Expand);
475 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
476 setOperationAction(ISD::SELECT, MVT::v8i16, Expand);
477 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
478 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
479 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
480 setOperationAction(ISD::SELECT, MVT::v2i64, Expand);
481 setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
482 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
483 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
484 setOperationAction(ISD::SELECT, MVT::v2f64, Expand);
486 setOperationAction(ISD::SELECT_CC, MVT::v8i8, Custom);
487 setOperationAction(ISD::SELECT_CC, MVT::v16i8, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::v4i16, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::v8i16, Custom);
490 setOperationAction(ISD::SELECT_CC, MVT::v2i32, Custom);
491 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Custom);
492 setOperationAction(ISD::SELECT_CC, MVT::v1i64, Custom);
493 setOperationAction(ISD::SELECT_CC, MVT::v2i64, Custom);
494 setOperationAction(ISD::SELECT_CC, MVT::v2f32, Custom);
495 setOperationAction(ISD::SELECT_CC, MVT::v4f32, Custom);
496 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Custom);
497 setOperationAction(ISD::SELECT_CC, MVT::v2f64, Custom);
499 // Vector ExtLoad and TruncStore are expanded.
500 for (unsigned I = MVT::FIRST_VECTOR_VALUETYPE;
501 I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
502 MVT VT = (MVT::SimpleValueType) I;
503 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
504 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
505 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
506 for (unsigned II = MVT::FIRST_VECTOR_VALUETYPE;
507 II <= MVT::LAST_VECTOR_VALUETYPE; ++II) {
508 MVT VT1 = (MVT::SimpleValueType) II;
509 // A TruncStore has two vector types of the same number of elements
510 // and different element sizes.
511 if (VT.getVectorNumElements() == VT1.getVectorNumElements() &&
512 VT.getVectorElementType().getSizeInBits()
513 > VT1.getVectorElementType().getSizeInBits())
514 setTruncStoreAction(VT, VT1, Expand);
518 // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
519 // FIXME: For a v2i64 multiply, we copy VPR to GPR and do 2 i64 multiplies,
520 // and then copy back to VPR. This solution may be optimized by Following 3
521 // NEON instructions:
522 // pmull v2.1q, v0.1d, v1.1d
523 // pmull2 v3.1q, v0.2d, v1.2d
524 // ins v2.d[1], v3.d[0]
525 // As currently we can't verify the correctness of such assumption, we can
526 // do such optimization in the future.
527 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
528 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
530 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
531 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
532 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
533 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
534 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
535 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
536 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
537 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
538 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
541 setTargetDAGCombine(ISD::SIGN_EXTEND);
542 setTargetDAGCombine(ISD::VSELECT);
545 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
546 // It's reasonably important that this value matches the "natural" legal
547 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
548 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
549 if (!VT.isVector()) return MVT::i32;
550 return VT.changeVectorElementTypeToInteger();
553 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
556 static const unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
557 AArch64::LDXR_word, AArch64::LDXR_dword};
558 static const unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
559 AArch64::LDAXR_word, AArch64::LDAXR_dword};
560 static const unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
561 AArch64::STXR_word, AArch64::STXR_dword};
562 static const unsigned StoreRels[] = {AArch64::STLXR_byte,AArch64::STLXR_hword,
563 AArch64::STLXR_word, AArch64::STLXR_dword};
565 const unsigned *LoadOps, *StoreOps;
566 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
571 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
572 StoreOps = StoreRels;
574 StoreOps = StoreBares;
576 assert(isPowerOf2_32(Size) && Size <= 8 &&
577 "unsupported size for atomic binary op!");
579 LdrOpc = LoadOps[Log2_32(Size)];
580 StrOpc = StoreOps[Log2_32(Size)];
583 // FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really
584 // have value type mapped, and they are both being defined as MVT::untyped.
585 // Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost
586 // would fail to figure out the register pressure correctly.
587 std::pair<const TargetRegisterClass*, uint8_t>
588 AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
589 const TargetRegisterClass *RRC = 0;
591 switch (VT.SimpleTy) {
593 return TargetLowering::findRepresentativeClass(VT);
595 RRC = &AArch64::QPairRegClass;
599 RRC = &AArch64::QQuadRegClass;
603 return std::make_pair(RRC, Cost);
607 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
609 unsigned BinOpcode) const {
610 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
611 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
613 const BasicBlock *LLVM_BB = BB->getBasicBlock();
614 MachineFunction *MF = BB->getParent();
615 MachineFunction::iterator It = BB;
618 unsigned dest = MI->getOperand(0).getReg();
619 unsigned ptr = MI->getOperand(1).getReg();
620 unsigned incr = MI->getOperand(2).getReg();
621 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
622 DebugLoc dl = MI->getDebugLoc();
624 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
626 unsigned ldrOpc, strOpc;
627 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
629 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
630 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
631 MF->insert(It, loopMBB);
632 MF->insert(It, exitMBB);
634 // Transfer the remainder of BB and its successor edges to exitMBB.
635 exitMBB->splice(exitMBB->begin(), BB,
636 std::next(MachineBasicBlock::iterator(MI)), BB->end());
637 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
639 const TargetRegisterClass *TRC
640 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
641 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
645 // fallthrough --> loopMBB
646 BB->addSuccessor(loopMBB);
650 // <binop> scratch, dest, incr
651 // stxr stxr_status, scratch, ptr
652 // cbnz stxr_status, loopMBB
653 // fallthrough --> exitMBB
655 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
657 // All arithmetic operations we'll be creating are designed to take an extra
658 // shift or extend operand, which we can conveniently set to zero.
660 // Operand order needs to go the other way for NAND.
661 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
662 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
663 .addReg(incr).addReg(dest).addImm(0);
665 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
666 .addReg(dest).addReg(incr).addImm(0);
669 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
670 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
671 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
673 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
674 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
675 .addReg(stxr_status).addMBB(loopMBB);
677 BB->addSuccessor(loopMBB);
678 BB->addSuccessor(exitMBB);
684 MI->eraseFromParent(); // The instruction is gone now.
690 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
691 MachineBasicBlock *BB,
694 A64CC::CondCodes Cond) const {
695 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
697 const BasicBlock *LLVM_BB = BB->getBasicBlock();
698 MachineFunction *MF = BB->getParent();
699 MachineFunction::iterator It = BB;
702 unsigned dest = MI->getOperand(0).getReg();
703 unsigned ptr = MI->getOperand(1).getReg();
704 unsigned incr = MI->getOperand(2).getReg();
705 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
707 unsigned oldval = dest;
708 DebugLoc dl = MI->getDebugLoc();
710 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
711 const TargetRegisterClass *TRC, *TRCsp;
713 TRC = &AArch64::GPR64RegClass;
714 TRCsp = &AArch64::GPR64xspRegClass;
716 TRC = &AArch64::GPR32RegClass;
717 TRCsp = &AArch64::GPR32wspRegClass;
720 unsigned ldrOpc, strOpc;
721 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
723 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
724 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
725 MF->insert(It, loopMBB);
726 MF->insert(It, exitMBB);
728 // Transfer the remainder of BB and its successor edges to exitMBB.
729 exitMBB->splice(exitMBB->begin(), BB,
730 std::next(MachineBasicBlock::iterator(MI)), BB->end());
731 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
733 unsigned scratch = MRI.createVirtualRegister(TRC);
734 MRI.constrainRegClass(scratch, TRCsp);
738 // fallthrough --> loopMBB
739 BB->addSuccessor(loopMBB);
743 // cmp incr, dest (, sign extend if necessary)
744 // csel scratch, dest, incr, cond
745 // stxr stxr_status, scratch, ptr
746 // cbnz stxr_status, loopMBB
747 // fallthrough --> exitMBB
749 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
751 // Build compare and cmov instructions.
752 MRI.constrainRegClass(incr, TRCsp);
753 BuildMI(BB, dl, TII->get(CmpOp))
754 .addReg(incr).addReg(oldval).addImm(0);
756 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
758 .addReg(oldval).addReg(incr).addImm(Cond);
760 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
761 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
763 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
764 .addReg(scratch).addReg(ptr);
765 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
766 .addReg(stxr_status).addMBB(loopMBB);
768 BB->addSuccessor(loopMBB);
769 BB->addSuccessor(exitMBB);
775 MI->eraseFromParent(); // The instruction is gone now.
781 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
782 MachineBasicBlock *BB,
783 unsigned Size) const {
784 unsigned dest = MI->getOperand(0).getReg();
785 unsigned ptr = MI->getOperand(1).getReg();
786 unsigned oldval = MI->getOperand(2).getReg();
787 unsigned newval = MI->getOperand(3).getReg();
788 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
789 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
790 DebugLoc dl = MI->getDebugLoc();
792 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
793 const TargetRegisterClass *TRCsp;
794 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
796 unsigned ldrOpc, strOpc;
797 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
799 MachineFunction *MF = BB->getParent();
800 const BasicBlock *LLVM_BB = BB->getBasicBlock();
801 MachineFunction::iterator It = BB;
802 ++It; // insert the new blocks after the current block
804 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
805 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
806 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
807 MF->insert(It, loop1MBB);
808 MF->insert(It, loop2MBB);
809 MF->insert(It, exitMBB);
811 // Transfer the remainder of BB and its successor edges to exitMBB.
812 exitMBB->splice(exitMBB->begin(), BB,
813 std::next(MachineBasicBlock::iterator(MI)), BB->end());
814 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
818 // fallthrough --> loop1MBB
819 BB->addSuccessor(loop1MBB);
826 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
828 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
829 MRI.constrainRegClass(dest, TRCsp);
830 BuildMI(BB, dl, TII->get(CmpOp))
831 .addReg(dest).addReg(oldval).addImm(0);
832 BuildMI(BB, dl, TII->get(AArch64::Bcc))
833 .addImm(A64CC::NE).addMBB(exitMBB);
834 BB->addSuccessor(loop2MBB);
835 BB->addSuccessor(exitMBB);
838 // strex stxr_status, newval, [ptr]
839 // cbnz stxr_status, loop1MBB
841 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
842 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
844 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
845 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
846 .addReg(stxr_status).addMBB(loop1MBB);
847 BB->addSuccessor(loop1MBB);
848 BB->addSuccessor(exitMBB);
854 MI->eraseFromParent(); // The instruction is gone now.
860 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
861 MachineBasicBlock *MBB) const {
862 // We materialise the F128CSEL pseudo-instruction using conditional branches
863 // and loads, giving an instruciton sequence like:
872 // Using virtual registers would probably not be beneficial since COPY
873 // instructions are expensive for f128 (there's no actual instruction to
876 // An alternative would be to do an integer-CSEL on some address. E.g.:
881 // csel x0, x0, x1, ne
884 // It's unclear which approach is actually optimal.
885 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
886 MachineFunction *MF = MBB->getParent();
887 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
888 DebugLoc DL = MI->getDebugLoc();
889 MachineFunction::iterator It = MBB;
892 unsigned DestReg = MI->getOperand(0).getReg();
893 unsigned IfTrueReg = MI->getOperand(1).getReg();
894 unsigned IfFalseReg = MI->getOperand(2).getReg();
895 unsigned CondCode = MI->getOperand(3).getImm();
896 bool NZCVKilled = MI->getOperand(4).isKill();
898 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
899 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
900 MF->insert(It, TrueBB);
901 MF->insert(It, EndBB);
903 // Transfer rest of current basic-block to EndBB
904 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
906 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
908 // We need somewhere to store the f128 value needed.
909 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
911 // [... start of incoming MBB ...]
912 // str qIFFALSE, [sp]
915 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
917 .addFrameIndex(ScratchFI)
919 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
922 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
924 MBB->addSuccessor(TrueBB);
925 MBB->addSuccessor(EndBB);
928 // NZCV is live-through TrueBB.
929 TrueBB->addLiveIn(AArch64::NZCV);
930 EndBB->addLiveIn(AArch64::NZCV);
935 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
937 .addFrameIndex(ScratchFI)
940 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
942 TrueBB->addSuccessor(EndBB);
946 // [... rest of incoming MBB ...]
947 MachineInstr *StartOfEnd = EndBB->begin();
948 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
949 .addFrameIndex(ScratchFI)
952 MI->eraseFromParent();
957 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
958 MachineBasicBlock *MBB) const {
959 switch (MI->getOpcode()) {
960 default: llvm_unreachable("Unhandled instruction with custom inserter");
961 case AArch64::F128CSEL:
962 return EmitF128CSEL(MI, MBB);
963 case AArch64::ATOMIC_LOAD_ADD_I8:
964 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
965 case AArch64::ATOMIC_LOAD_ADD_I16:
966 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
967 case AArch64::ATOMIC_LOAD_ADD_I32:
968 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
969 case AArch64::ATOMIC_LOAD_ADD_I64:
970 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
972 case AArch64::ATOMIC_LOAD_SUB_I8:
973 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
974 case AArch64::ATOMIC_LOAD_SUB_I16:
975 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
976 case AArch64::ATOMIC_LOAD_SUB_I32:
977 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
978 case AArch64::ATOMIC_LOAD_SUB_I64:
979 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
981 case AArch64::ATOMIC_LOAD_AND_I8:
982 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
983 case AArch64::ATOMIC_LOAD_AND_I16:
984 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
985 case AArch64::ATOMIC_LOAD_AND_I32:
986 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
987 case AArch64::ATOMIC_LOAD_AND_I64:
988 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
990 case AArch64::ATOMIC_LOAD_OR_I8:
991 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
992 case AArch64::ATOMIC_LOAD_OR_I16:
993 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
994 case AArch64::ATOMIC_LOAD_OR_I32:
995 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
996 case AArch64::ATOMIC_LOAD_OR_I64:
997 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
999 case AArch64::ATOMIC_LOAD_XOR_I8:
1000 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
1001 case AArch64::ATOMIC_LOAD_XOR_I16:
1002 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
1003 case AArch64::ATOMIC_LOAD_XOR_I32:
1004 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
1005 case AArch64::ATOMIC_LOAD_XOR_I64:
1006 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
1008 case AArch64::ATOMIC_LOAD_NAND_I8:
1009 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
1010 case AArch64::ATOMIC_LOAD_NAND_I16:
1011 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
1012 case AArch64::ATOMIC_LOAD_NAND_I32:
1013 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
1014 case AArch64::ATOMIC_LOAD_NAND_I64:
1015 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
1017 case AArch64::ATOMIC_LOAD_MIN_I8:
1018 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
1019 case AArch64::ATOMIC_LOAD_MIN_I16:
1020 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
1021 case AArch64::ATOMIC_LOAD_MIN_I32:
1022 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
1023 case AArch64::ATOMIC_LOAD_MIN_I64:
1024 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
1026 case AArch64::ATOMIC_LOAD_MAX_I8:
1027 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
1028 case AArch64::ATOMIC_LOAD_MAX_I16:
1029 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
1030 case AArch64::ATOMIC_LOAD_MAX_I32:
1031 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
1032 case AArch64::ATOMIC_LOAD_MAX_I64:
1033 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
1035 case AArch64::ATOMIC_LOAD_UMIN_I8:
1036 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
1037 case AArch64::ATOMIC_LOAD_UMIN_I16:
1038 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
1039 case AArch64::ATOMIC_LOAD_UMIN_I32:
1040 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
1041 case AArch64::ATOMIC_LOAD_UMIN_I64:
1042 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
1044 case AArch64::ATOMIC_LOAD_UMAX_I8:
1045 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
1046 case AArch64::ATOMIC_LOAD_UMAX_I16:
1047 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
1048 case AArch64::ATOMIC_LOAD_UMAX_I32:
1049 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
1050 case AArch64::ATOMIC_LOAD_UMAX_I64:
1051 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
1053 case AArch64::ATOMIC_SWAP_I8:
1054 return emitAtomicBinary(MI, MBB, 1, 0);
1055 case AArch64::ATOMIC_SWAP_I16:
1056 return emitAtomicBinary(MI, MBB, 2, 0);
1057 case AArch64::ATOMIC_SWAP_I32:
1058 return emitAtomicBinary(MI, MBB, 4, 0);
1059 case AArch64::ATOMIC_SWAP_I64:
1060 return emitAtomicBinary(MI, MBB, 8, 0);
1062 case AArch64::ATOMIC_CMP_SWAP_I8:
1063 return emitAtomicCmpSwap(MI, MBB, 1);
1064 case AArch64::ATOMIC_CMP_SWAP_I16:
1065 return emitAtomicCmpSwap(MI, MBB, 2);
1066 case AArch64::ATOMIC_CMP_SWAP_I32:
1067 return emitAtomicCmpSwap(MI, MBB, 4);
1068 case AArch64::ATOMIC_CMP_SWAP_I64:
1069 return emitAtomicCmpSwap(MI, MBB, 8);
1074 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
1076 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
1077 case AArch64ISD::Call: return "AArch64ISD::Call";
1078 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
1079 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
1080 case AArch64ISD::BFI: return "AArch64ISD::BFI";
1081 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
1082 case AArch64ISD::Ret: return "AArch64ISD::Ret";
1083 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
1084 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
1085 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
1086 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
1087 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
1088 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
1089 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
1090 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
1092 case AArch64ISD::NEON_MOVIMM:
1093 return "AArch64ISD::NEON_MOVIMM";
1094 case AArch64ISD::NEON_MVNIMM:
1095 return "AArch64ISD::NEON_MVNIMM";
1096 case AArch64ISD::NEON_FMOVIMM:
1097 return "AArch64ISD::NEON_FMOVIMM";
1098 case AArch64ISD::NEON_CMP:
1099 return "AArch64ISD::NEON_CMP";
1100 case AArch64ISD::NEON_CMPZ:
1101 return "AArch64ISD::NEON_CMPZ";
1102 case AArch64ISD::NEON_TST:
1103 return "AArch64ISD::NEON_TST";
1104 case AArch64ISD::NEON_QSHLs:
1105 return "AArch64ISD::NEON_QSHLs";
1106 case AArch64ISD::NEON_QSHLu:
1107 return "AArch64ISD::NEON_QSHLu";
1108 case AArch64ISD::NEON_VDUP:
1109 return "AArch64ISD::NEON_VDUP";
1110 case AArch64ISD::NEON_VDUPLANE:
1111 return "AArch64ISD::NEON_VDUPLANE";
1112 case AArch64ISD::NEON_REV16:
1113 return "AArch64ISD::NEON_REV16";
1114 case AArch64ISD::NEON_REV32:
1115 return "AArch64ISD::NEON_REV32";
1116 case AArch64ISD::NEON_REV64:
1117 return "AArch64ISD::NEON_REV64";
1118 case AArch64ISD::NEON_UZP1:
1119 return "AArch64ISD::NEON_UZP1";
1120 case AArch64ISD::NEON_UZP2:
1121 return "AArch64ISD::NEON_UZP2";
1122 case AArch64ISD::NEON_ZIP1:
1123 return "AArch64ISD::NEON_ZIP1";
1124 case AArch64ISD::NEON_ZIP2:
1125 return "AArch64ISD::NEON_ZIP2";
1126 case AArch64ISD::NEON_TRN1:
1127 return "AArch64ISD::NEON_TRN1";
1128 case AArch64ISD::NEON_TRN2:
1129 return "AArch64ISD::NEON_TRN2";
1130 case AArch64ISD::NEON_LD1_UPD:
1131 return "AArch64ISD::NEON_LD1_UPD";
1132 case AArch64ISD::NEON_LD2_UPD:
1133 return "AArch64ISD::NEON_LD2_UPD";
1134 case AArch64ISD::NEON_LD3_UPD:
1135 return "AArch64ISD::NEON_LD3_UPD";
1136 case AArch64ISD::NEON_LD4_UPD:
1137 return "AArch64ISD::NEON_LD4_UPD";
1138 case AArch64ISD::NEON_ST1_UPD:
1139 return "AArch64ISD::NEON_ST1_UPD";
1140 case AArch64ISD::NEON_ST2_UPD:
1141 return "AArch64ISD::NEON_ST2_UPD";
1142 case AArch64ISD::NEON_ST3_UPD:
1143 return "AArch64ISD::NEON_ST3_UPD";
1144 case AArch64ISD::NEON_ST4_UPD:
1145 return "AArch64ISD::NEON_ST4_UPD";
1146 case AArch64ISD::NEON_LD1x2_UPD:
1147 return "AArch64ISD::NEON_LD1x2_UPD";
1148 case AArch64ISD::NEON_LD1x3_UPD:
1149 return "AArch64ISD::NEON_LD1x3_UPD";
1150 case AArch64ISD::NEON_LD1x4_UPD:
1151 return "AArch64ISD::NEON_LD1x4_UPD";
1152 case AArch64ISD::NEON_ST1x2_UPD:
1153 return "AArch64ISD::NEON_ST1x2_UPD";
1154 case AArch64ISD::NEON_ST1x3_UPD:
1155 return "AArch64ISD::NEON_ST1x3_UPD";
1156 case AArch64ISD::NEON_ST1x4_UPD:
1157 return "AArch64ISD::NEON_ST1x4_UPD";
1158 case AArch64ISD::NEON_LD2DUP:
1159 return "AArch64ISD::NEON_LD2DUP";
1160 case AArch64ISD::NEON_LD3DUP:
1161 return "AArch64ISD::NEON_LD3DUP";
1162 case AArch64ISD::NEON_LD4DUP:
1163 return "AArch64ISD::NEON_LD4DUP";
1164 case AArch64ISD::NEON_LD2DUP_UPD:
1165 return "AArch64ISD::NEON_LD2DUP_UPD";
1166 case AArch64ISD::NEON_LD3DUP_UPD:
1167 return "AArch64ISD::NEON_LD3DUP_UPD";
1168 case AArch64ISD::NEON_LD4DUP_UPD:
1169 return "AArch64ISD::NEON_LD4DUP_UPD";
1170 case AArch64ISD::NEON_LD2LN_UPD:
1171 return "AArch64ISD::NEON_LD2LN_UPD";
1172 case AArch64ISD::NEON_LD3LN_UPD:
1173 return "AArch64ISD::NEON_LD3LN_UPD";
1174 case AArch64ISD::NEON_LD4LN_UPD:
1175 return "AArch64ISD::NEON_LD4LN_UPD";
1176 case AArch64ISD::NEON_ST2LN_UPD:
1177 return "AArch64ISD::NEON_ST2LN_UPD";
1178 case AArch64ISD::NEON_ST3LN_UPD:
1179 return "AArch64ISD::NEON_ST3LN_UPD";
1180 case AArch64ISD::NEON_ST4LN_UPD:
1181 return "AArch64ISD::NEON_ST4LN_UPD";
1182 case AArch64ISD::NEON_VEXTRACT:
1183 return "AArch64ISD::NEON_VEXTRACT";
1189 static const MCPhysReg AArch64FPRArgRegs[] = {
1190 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1191 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1193 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
1195 static const MCPhysReg AArch64ArgRegs[] = {
1196 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
1197 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1199 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
1201 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
1202 CCValAssign::LocInfo LocInfo,
1203 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1204 // Mark all remaining general purpose registers as allocated. We don't
1205 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
1206 // i64 will go in registers (C.11).
1207 for (unsigned i = 0; i < NumArgRegs; ++i)
1208 State.AllocateReg(AArch64ArgRegs[i]);
1213 #include "AArch64GenCallingConv.inc"
1215 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1218 default: llvm_unreachable("Unsupported calling convention");
1219 case CallingConv::Fast:
1220 case CallingConv::C:
1226 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
1227 SDLoc DL, SDValue &Chain) const {
1228 MachineFunction &MF = DAG.getMachineFunction();
1229 MachineFrameInfo *MFI = MF.getFrameInfo();
1230 AArch64MachineFunctionInfo *FuncInfo
1231 = MF.getInfo<AArch64MachineFunctionInfo>();
1233 SmallVector<SDValue, 8> MemOps;
1235 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
1237 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
1240 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
1242 if (GPRSaveSize != 0) {
1243 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1245 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1247 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
1248 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
1249 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1250 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1251 MachinePointerInfo::getStack(i * 8),
1253 MemOps.push_back(Store);
1254 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1255 DAG.getConstant(8, getPointerTy()));
1259 if (getSubtarget()->hasFPARMv8()) {
1260 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1262 // According to the AArch64 Procedure Call Standard, section B.1/B.3, we
1263 // can omit a register save area if we know we'll never use registers of
1265 if (FPRSaveSize != 0) {
1266 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1268 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1270 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1271 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
1272 &AArch64::FPR128RegClass);
1273 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1274 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1275 MachinePointerInfo::getStack(i * 16),
1277 MemOps.push_back(Store);
1278 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1279 DAG.getConstant(16, getPointerTy()));
1282 FuncInfo->setVariadicFPRIdx(FPRIdx);
1283 FuncInfo->setVariadicFPRSize(FPRSaveSize);
1286 unsigned StackOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), 8);
1287 int StackIdx = MFI->CreateFixedObject(8, StackOffset, true);
1289 FuncInfo->setVariadicStackIdx(StackIdx);
1290 FuncInfo->setVariadicGPRIdx(GPRIdx);
1291 FuncInfo->setVariadicGPRSize(GPRSaveSize);
1293 if (!MemOps.empty()) {
1294 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
1301 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
1302 CallingConv::ID CallConv, bool isVarArg,
1303 const SmallVectorImpl<ISD::InputArg> &Ins,
1304 SDLoc dl, SelectionDAG &DAG,
1305 SmallVectorImpl<SDValue> &InVals) const {
1306 MachineFunction &MF = DAG.getMachineFunction();
1307 AArch64MachineFunctionInfo *FuncInfo
1308 = MF.getInfo<AArch64MachineFunctionInfo>();
1309 MachineFrameInfo *MFI = MF.getFrameInfo();
1310 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1312 SmallVector<CCValAssign, 16> ArgLocs;
1313 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1314 getTargetMachine(), ArgLocs, *DAG.getContext());
1315 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1317 SmallVector<SDValue, 16> ArgValues;
1320 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1321 CCValAssign &VA = ArgLocs[i];
1322 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1324 if (Flags.isByVal()) {
1325 // Byval is used for small structs and HFAs in the PCS, but the system
1326 // should work in a non-compliant manner for larger structs.
1327 EVT PtrTy = getPointerTy();
1328 int Size = Flags.getByValSize();
1329 unsigned NumRegs = (Size + 7) / 8;
1331 uint32_t BEAlign = 0;
1332 if (Size < 8 && !getSubtarget()->isLittle())
1334 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
1335 VA.getLocMemOffset() + BEAlign,
1337 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1338 InVals.push_back(FrameIdxN);
1341 } else if (VA.isRegLoc()) {
1342 MVT RegVT = VA.getLocVT();
1343 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1344 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1346 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1347 } else { // VA.isRegLoc()
1348 assert(VA.isMemLoc());
1350 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
1351 VA.getLocMemOffset(), true);
1353 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1354 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1355 MachinePointerInfo::getFixedStack(FI),
1356 false, false, false, 0);
1361 switch (VA.getLocInfo()) {
1362 default: llvm_unreachable("Unknown loc info!");
1363 case CCValAssign::Full: break;
1364 case CCValAssign::BCvt:
1365 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
1367 case CCValAssign::SExt:
1368 case CCValAssign::ZExt:
1369 case CCValAssign::AExt:
1370 case CCValAssign::FPExt: {
1371 unsigned DestSize = VA.getValVT().getSizeInBits();
1372 unsigned DestSubReg;
1375 case 8: DestSubReg = AArch64::sub_8; break;
1376 case 16: DestSubReg = AArch64::sub_16; break;
1377 case 32: DestSubReg = AArch64::sub_32; break;
1378 case 64: DestSubReg = AArch64::sub_64; break;
1379 default: llvm_unreachable("Unexpected argument promotion");
1382 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
1383 VA.getValVT(), ArgValue,
1384 DAG.getTargetConstant(DestSubReg, MVT::i32)),
1390 InVals.push_back(ArgValue);
1394 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
1396 unsigned StackArgSize = CCInfo.getNextStackOffset();
1397 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1398 // This is a non-standard ABI so by fiat I say we're allowed to make full
1399 // use of the stack area to be popped, which must be aligned to 16 bytes in
1401 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1403 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1404 // a multiple of 16.
1405 FuncInfo->setArgumentStackToRestore(StackArgSize);
1407 // This realignment carries over to the available bytes below. Our own
1408 // callers will guarantee the space is free by giving an aligned value to
1411 // Even if we're not expected to free up the space, it's useful to know how
1412 // much is there while considering tail calls (because we can reuse it).
1413 FuncInfo->setBytesInStackArgArea(StackArgSize);
1419 AArch64TargetLowering::LowerReturn(SDValue Chain,
1420 CallingConv::ID CallConv, bool isVarArg,
1421 const SmallVectorImpl<ISD::OutputArg> &Outs,
1422 const SmallVectorImpl<SDValue> &OutVals,
1423 SDLoc dl, SelectionDAG &DAG) const {
1424 // CCValAssign - represent the assignment of the return value to a location.
1425 SmallVector<CCValAssign, 16> RVLocs;
1427 // CCState - Info about the registers and stack slots.
1428 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1429 getTargetMachine(), RVLocs, *DAG.getContext());
1431 // Analyze outgoing return values.
1432 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1435 SmallVector<SDValue, 4> RetOps(1, Chain);
1437 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1438 // PCS: "If the type, T, of the result of a function is such that
1439 // void func(T arg) would require that arg be passed as a value in a
1440 // register (or set of registers) according to the rules in 5.4, then the
1441 // result is returned in the same registers as would be used for such an
1444 // Otherwise, the caller shall reserve a block of memory of sufficient
1445 // size and alignment to hold the result. The address of the memory block
1446 // shall be passed as an additional argument to the function in x8."
1448 // This is implemented in two places. The register-return values are dealt
1449 // with here, more complex returns are passed as an sret parameter, which
1450 // means we don't have to worry about it during actual return.
1451 CCValAssign &VA = RVLocs[i];
1452 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1455 SDValue Arg = OutVals[i];
1457 // There's no convenient note in the ABI about this as there is for normal
1458 // arguments, but it says return values are passed in the same registers as
1459 // an argument would be. I believe that includes the comments about
1460 // unspecified higher bits, putting the burden of widening on the *caller*
1461 // for return values.
1462 switch (VA.getLocInfo()) {
1463 default: llvm_unreachable("Unknown loc info");
1464 case CCValAssign::Full: break;
1465 case CCValAssign::SExt:
1466 case CCValAssign::ZExt:
1467 case CCValAssign::AExt:
1468 // Floating-point values should only be extended when they're going into
1469 // memory, which can't happen here so an integer extend is acceptable.
1470 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1472 case CCValAssign::BCvt:
1473 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1477 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1478 Flag = Chain.getValue(1);
1479 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1482 RetOps[0] = Chain; // Update chain.
1484 // Add the flag if we have it.
1486 RetOps.push_back(Flag);
1488 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1489 &RetOps[0], RetOps.size());
1492 unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
1493 // This is a new backend. For anything more precise than this a FE should
1494 // set an explicit alignment.
1499 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1500 SmallVectorImpl<SDValue> &InVals) const {
1501 SelectionDAG &DAG = CLI.DAG;
1503 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1504 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1505 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1506 SDValue Chain = CLI.Chain;
1507 SDValue Callee = CLI.Callee;
1508 bool &IsTailCall = CLI.IsTailCall;
1509 CallingConv::ID CallConv = CLI.CallConv;
1510 bool IsVarArg = CLI.IsVarArg;
1512 MachineFunction &MF = DAG.getMachineFunction();
1513 AArch64MachineFunctionInfo *FuncInfo
1514 = MF.getInfo<AArch64MachineFunctionInfo>();
1515 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1516 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1517 bool IsSibCall = false;
1520 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1521 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1522 Outs, OutVals, Ins, DAG);
1524 // A sibling call is one where we're under the usual C ABI and not planning
1525 // to change that but can still do a tail call:
1526 if (!TailCallOpt && IsTailCall)
1530 SmallVector<CCValAssign, 16> ArgLocs;
1531 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1532 getTargetMachine(), ArgLocs, *DAG.getContext());
1533 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1535 // On AArch64 (and all other architectures I'm aware of) the most this has to
1536 // do is adjust the stack pointer.
1537 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1539 // Since we're not changing the ABI to make this a tail call, the memory
1540 // operands are already available in the caller's incoming argument space.
1544 // FPDiff is the byte offset of the call's argument area from the callee's.
1545 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1546 // by this amount for a tail call. In a sibling call it must be 0 because the
1547 // caller will deallocate the entire stack and the callee still expects its
1548 // arguments to begin at SP+0. Completely unused for non-tail calls.
1551 if (IsTailCall && !IsSibCall) {
1552 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1554 // FPDiff will be negative if this tail call requires more space than we
1555 // would automatically have in our incoming argument space. Positive if we
1556 // can actually shrink the stack.
1557 FPDiff = NumReusableBytes - NumBytes;
1559 // The stack pointer must be 16-byte aligned at all times it's used for a
1560 // memory operation, which in practice means at *all* times and in
1561 // particular across call boundaries. Therefore our own arguments started at
1562 // a 16-byte aligned SP and the delta applied for the tail call should
1563 // satisfy the same constraint.
1564 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1568 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1571 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1574 SmallVector<SDValue, 8> MemOpChains;
1575 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1577 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1578 CCValAssign &VA = ArgLocs[i];
1579 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1580 SDValue Arg = OutVals[i];
1582 // Callee does the actual widening, so all extensions just use an implicit
1583 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1584 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1585 // alternative works on integer types too.
1586 switch (VA.getLocInfo()) {
1587 default: llvm_unreachable("Unknown loc info!");
1588 case CCValAssign::Full: break;
1589 case CCValAssign::SExt:
1590 case CCValAssign::ZExt:
1591 case CCValAssign::AExt:
1592 case CCValAssign::FPExt: {
1593 unsigned SrcSize = VA.getValVT().getSizeInBits();
1597 case 8: SrcSubReg = AArch64::sub_8; break;
1598 case 16: SrcSubReg = AArch64::sub_16; break;
1599 case 32: SrcSubReg = AArch64::sub_32; break;
1600 case 64: SrcSubReg = AArch64::sub_64; break;
1601 default: llvm_unreachable("Unexpected argument promotion");
1604 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1606 DAG.getUNDEF(VA.getLocVT()),
1608 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1613 case CCValAssign::BCvt:
1614 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1618 if (VA.isRegLoc()) {
1619 // A normal register (sub-) argument. For now we just note it down because
1620 // we want to copy things into registers as late as possible to avoid
1621 // register-pressure (and possibly worse).
1622 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1626 assert(VA.isMemLoc() && "unexpected argument location");
1629 MachinePointerInfo DstInfo;
1631 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1632 VA.getLocVT().getSizeInBits();
1633 OpSize = (OpSize + 7) / 8;
1634 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1635 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1637 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1638 DstInfo = MachinePointerInfo::getFixedStack(FI);
1640 // Make sure any stack arguments overlapping with where we're storing are
1641 // loaded before this eventual operation. Otherwise they'll be clobbered.
1642 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1644 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize()*8 :
1645 VA.getLocVT().getSizeInBits();
1646 OpSize = (OpSize + 7) / 8;
1647 uint32_t BEAlign = 0;
1648 if (OpSize < 8 && !getSubtarget()->isLittle())
1650 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + BEAlign);
1652 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1653 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1656 if (Flags.isByVal()) {
1657 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1658 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1659 Flags.getByValAlign(),
1660 /*isVolatile = */ false,
1661 /*alwaysInline = */ false,
1662 DstInfo, MachinePointerInfo(0));
1663 MemOpChains.push_back(Cpy);
1665 // Normal stack argument, put it where it's needed.
1666 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1668 MemOpChains.push_back(Store);
1672 // The loads and stores generated above shouldn't clash with each
1673 // other. Combining them with this TokenFactor notes that fact for the rest of
1675 if (!MemOpChains.empty())
1676 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1677 &MemOpChains[0], MemOpChains.size());
1679 // Most of the rest of the instructions need to be glued together; we don't
1680 // want assignments to actual registers used by a call to be rearranged by a
1681 // well-meaning scheduler.
1684 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1685 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1686 RegsToPass[i].second, InFlag);
1687 InFlag = Chain.getValue(1);
1690 // The linker is responsible for inserting veneers when necessary to put a
1691 // function call destination in range, so we don't need to bother with a
1693 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1694 const GlobalValue *GV = G->getGlobal();
1695 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1696 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1697 const char *Sym = S->getSymbol();
1698 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1701 // We don't usually want to end the call-sequence here because we would tidy
1702 // the frame up *after* the call, however in the ABI-changing tail-call case
1703 // we've carefully laid out the parameters so that when sp is reset they'll be
1704 // in the correct location.
1705 if (IsTailCall && !IsSibCall) {
1706 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1707 DAG.getIntPtrConstant(0, true), InFlag, dl);
1708 InFlag = Chain.getValue(1);
1711 // We produce the following DAG scheme for the actual call instruction:
1712 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1714 // Most arguments aren't going to be used and just keep the values live as
1715 // far as LLVM is concerned. It's expected to be selected as simply "bl
1716 // callee" (for a direct, non-tail call).
1717 std::vector<SDValue> Ops;
1718 Ops.push_back(Chain);
1719 Ops.push_back(Callee);
1722 // Each tail call may have to adjust the stack by a different amount, so
1723 // this information must travel along with the operation for eventual
1724 // consumption by emitEpilogue.
1725 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1728 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1729 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1730 RegsToPass[i].second.getValueType()));
1733 // Add a register mask operand representing the call-preserved registers. This
1734 // is used later in codegen to constrain register-allocation.
1735 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1736 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1737 assert(Mask && "Missing call preserved mask for calling convention");
1738 Ops.push_back(DAG.getRegisterMask(Mask));
1740 // If we needed glue, put it in as the last argument.
1741 if (InFlag.getNode())
1742 Ops.push_back(InFlag);
1744 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1747 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1750 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1751 InFlag = Chain.getValue(1);
1753 // Now we can reclaim the stack, just as well do it before working out where
1754 // our return value is.
1756 uint64_t CalleePopBytes
1757 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1759 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1760 DAG.getIntPtrConstant(CalleePopBytes, true),
1762 InFlag = Chain.getValue(1);
1765 return LowerCallResult(Chain, InFlag, CallConv,
1766 IsVarArg, Ins, dl, DAG, InVals);
1770 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1771 CallingConv::ID CallConv, bool IsVarArg,
1772 const SmallVectorImpl<ISD::InputArg> &Ins,
1773 SDLoc dl, SelectionDAG &DAG,
1774 SmallVectorImpl<SDValue> &InVals) const {
1775 // Assign locations to each value returned by this call.
1776 SmallVector<CCValAssign, 16> RVLocs;
1777 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1778 getTargetMachine(), RVLocs, *DAG.getContext());
1779 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1781 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1782 CCValAssign VA = RVLocs[i];
1784 // Return values that are too big to fit into registers should use an sret
1785 // pointer, so this can be a lot simpler than the main argument code.
1786 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1788 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1790 Chain = Val.getValue(1);
1791 InFlag = Val.getValue(2);
1793 switch (VA.getLocInfo()) {
1794 default: llvm_unreachable("Unknown loc info!");
1795 case CCValAssign::Full: break;
1796 case CCValAssign::BCvt:
1797 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1799 case CCValAssign::ZExt:
1800 case CCValAssign::SExt:
1801 case CCValAssign::AExt:
1802 // Floating-point arguments only get extended/truncated if they're going
1803 // in memory, so using the integer operation is acceptable here.
1804 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1808 InVals.push_back(Val);
1815 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1816 CallingConv::ID CalleeCC,
1818 bool IsCalleeStructRet,
1819 bool IsCallerStructRet,
1820 const SmallVectorImpl<ISD::OutputArg> &Outs,
1821 const SmallVectorImpl<SDValue> &OutVals,
1822 const SmallVectorImpl<ISD::InputArg> &Ins,
1823 SelectionDAG& DAG) const {
1825 // For CallingConv::C this function knows whether the ABI needs
1826 // changing. That's not true for other conventions so they will have to opt in
1828 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1831 const MachineFunction &MF = DAG.getMachineFunction();
1832 const Function *CallerF = MF.getFunction();
1833 CallingConv::ID CallerCC = CallerF->getCallingConv();
1834 bool CCMatch = CallerCC == CalleeCC;
1836 // Byval parameters hand the function a pointer directly into the stack area
1837 // we want to reuse during a tail call. Working around this *is* possible (see
1838 // X86) but less efficient and uglier in LowerCall.
1839 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1840 e = CallerF->arg_end(); i != e; ++i)
1841 if (i->hasByValAttr())
1844 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1845 if (IsTailCallConvention(CalleeCC) && CCMatch)
1850 // Now we search for cases where we can use a tail call without changing the
1851 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1854 // I want anyone implementing a new calling convention to think long and hard
1855 // about this assert.
1856 assert((!IsVarArg || CalleeCC == CallingConv::C)
1857 && "Unexpected variadic calling convention");
1859 if (IsVarArg && !Outs.empty()) {
1860 // At least two cases here: if caller is fastcc then we can't have any
1861 // memory arguments (we'd be expected to clean up the stack afterwards). If
1862 // caller is C then we could potentially use its argument area.
1864 // FIXME: for now we take the most conservative of these in both cases:
1865 // disallow all variadic memory operands.
1866 SmallVector<CCValAssign, 16> ArgLocs;
1867 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1868 getTargetMachine(), ArgLocs, *DAG.getContext());
1870 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1871 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1872 if (!ArgLocs[i].isRegLoc())
1876 // If the calling conventions do not match, then we'd better make sure the
1877 // results are returned in the same way as what the caller expects.
1879 SmallVector<CCValAssign, 16> RVLocs1;
1880 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1881 getTargetMachine(), RVLocs1, *DAG.getContext());
1882 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1884 SmallVector<CCValAssign, 16> RVLocs2;
1885 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1886 getTargetMachine(), RVLocs2, *DAG.getContext());
1887 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1889 if (RVLocs1.size() != RVLocs2.size())
1891 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1892 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1894 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1896 if (RVLocs1[i].isRegLoc()) {
1897 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1900 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1906 // Nothing more to check if the callee is taking no arguments
1910 SmallVector<CCValAssign, 16> ArgLocs;
1911 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1912 getTargetMachine(), ArgLocs, *DAG.getContext());
1914 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1916 const AArch64MachineFunctionInfo *FuncInfo
1917 = MF.getInfo<AArch64MachineFunctionInfo>();
1919 // If the stack arguments for this call would fit into our own save area then
1920 // the call can be made tail.
1921 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1924 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1925 bool TailCallOpt) const {
1926 return CallCC == CallingConv::Fast && TailCallOpt;
1929 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1930 return CallCC == CallingConv::Fast;
1933 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1935 MachineFrameInfo *MFI,
1936 int ClobberedFI) const {
1937 SmallVector<SDValue, 8> ArgChains;
1938 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1939 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1941 // Include the original chain at the beginning of the list. When this is
1942 // used by target LowerCall hooks, this helps legalize find the
1943 // CALLSEQ_BEGIN node.
1944 ArgChains.push_back(Chain);
1946 // Add a chain value for each stack argument corresponding
1947 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1948 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1949 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1950 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1951 if (FI->getIndex() < 0) {
1952 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1953 int64_t InLastByte = InFirstByte;
1954 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1956 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1957 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1958 ArgChains.push_back(SDValue(L, 1));
1961 // Build a tokenfactor for all the chains.
1962 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1963 &ArgChains[0], ArgChains.size());
1966 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1968 case ISD::SETEQ: return A64CC::EQ;
1969 case ISD::SETGT: return A64CC::GT;
1970 case ISD::SETGE: return A64CC::GE;
1971 case ISD::SETLT: return A64CC::LT;
1972 case ISD::SETLE: return A64CC::LE;
1973 case ISD::SETNE: return A64CC::NE;
1974 case ISD::SETUGT: return A64CC::HI;
1975 case ISD::SETUGE: return A64CC::HS;
1976 case ISD::SETULT: return A64CC::LO;
1977 case ISD::SETULE: return A64CC::LS;
1978 default: llvm_unreachable("Unexpected condition code");
1982 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1983 // icmp is implemented using adds/subs immediate, which take an unsigned
1984 // 12-bit immediate, optionally shifted left by 12 bits.
1986 // Symmetric by using adds/subs
1990 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1993 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1994 ISD::CondCode CC, SDValue &A64cc,
1995 SelectionDAG &DAG, SDLoc &dl) const {
1996 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1998 EVT VT = RHSC->getValueType(0);
1999 bool knownInvalid = false;
2001 // I'm not convinced the rest of LLVM handles these edge cases properly, but
2002 // we can at least get it right.
2003 if (isSignedIntSetCC(CC)) {
2004 C = RHSC->getSExtValue();
2005 } else if (RHSC->getZExtValue() > INT64_MAX) {
2006 // A 64-bit constant not representable by a signed 64-bit integer is far
2007 // too big to fit into a SUBS immediate anyway.
2008 knownInvalid = true;
2010 C = RHSC->getZExtValue();
2013 if (!knownInvalid && !isLegalICmpImmediate(C)) {
2014 // Constant does not fit, try adjusting it by one?
2019 if (isLegalICmpImmediate(C-1)) {
2020 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2021 RHS = DAG.getConstant(C-1, VT);
2026 if (isLegalICmpImmediate(C-1)) {
2027 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2028 RHS = DAG.getConstant(C-1, VT);
2033 if (isLegalICmpImmediate(C+1)) {
2034 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2035 RHS = DAG.getConstant(C+1, VT);
2040 if (isLegalICmpImmediate(C+1)) {
2041 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2042 RHS = DAG.getConstant(C+1, VT);
2049 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
2050 A64cc = DAG.getConstant(CondCode, MVT::i32);
2051 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2052 DAG.getCondCode(CC));
2055 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
2056 A64CC::CondCodes &Alternative) {
2057 A64CC::CondCodes CondCode = A64CC::Invalid;
2058 Alternative = A64CC::Invalid;
2061 default: llvm_unreachable("Unknown FP condition!");
2063 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
2065 case ISD::SETOGT: CondCode = A64CC::GT; break;
2067 case ISD::SETOGE: CondCode = A64CC::GE; break;
2068 case ISD::SETOLT: CondCode = A64CC::MI; break;
2069 case ISD::SETOLE: CondCode = A64CC::LS; break;
2070 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
2071 case ISD::SETO: CondCode = A64CC::VC; break;
2072 case ISD::SETUO: CondCode = A64CC::VS; break;
2073 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
2074 case ISD::SETUGT: CondCode = A64CC::HI; break;
2075 case ISD::SETUGE: CondCode = A64CC::PL; break;
2077 case ISD::SETULT: CondCode = A64CC::LT; break;
2079 case ISD::SETULE: CondCode = A64CC::LE; break;
2081 case ISD::SETUNE: CondCode = A64CC::NE; break;
2087 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
2089 EVT PtrVT = getPointerTy();
2090 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2092 switch(getTargetMachine().getCodeModel()) {
2093 case CodeModel::Small:
2094 // The most efficient code is PC-relative anyway for the small memory model,
2095 // so we don't need to worry about relocation model.
2096 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2097 DAG.getTargetBlockAddress(BA, PtrVT, 0,
2098 AArch64II::MO_NO_FLAG),
2099 DAG.getTargetBlockAddress(BA, PtrVT, 0,
2100 AArch64II::MO_LO12),
2101 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
2102 case CodeModel::Large:
2104 AArch64ISD::WrapperLarge, DL, PtrVT,
2105 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3),
2106 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2107 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2108 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2110 llvm_unreachable("Only small and large code models supported now");
2115 // (BRCOND chain, val, dest)
2117 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2119 SDValue Chain = Op.getOperand(0);
2120 SDValue TheBit = Op.getOperand(1);
2121 SDValue DestBB = Op.getOperand(2);
2123 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2124 // that as the consumer we are responsible for ignoring rubbish in higher
2126 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2127 DAG.getConstant(1, MVT::i32));
2129 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2130 DAG.getConstant(0, TheBit.getValueType()),
2131 DAG.getCondCode(ISD::SETNE));
2133 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
2134 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
2138 // (BR_CC chain, condcode, lhs, rhs, dest)
2140 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2142 SDValue Chain = Op.getOperand(0);
2143 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2144 SDValue LHS = Op.getOperand(2);
2145 SDValue RHS = Op.getOperand(3);
2146 SDValue DestBB = Op.getOperand(4);
2148 if (LHS.getValueType() == MVT::f128) {
2149 // f128 comparisons are lowered to runtime calls by a routine which sets
2150 // LHS, RHS and CC appropriately for the rest of this function to continue.
2151 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2153 // If softenSetCCOperands returned a scalar, we need to compare the result
2154 // against zero to select between true and false values.
2155 if (RHS.getNode() == 0) {
2156 RHS = DAG.getConstant(0, LHS.getValueType());
2161 if (LHS.getValueType().isInteger()) {
2164 // Integers are handled in a separate function because the combinations of
2165 // immediates and tests can get hairy and we may want to fiddle things.
2166 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2168 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2169 Chain, CmpOp, A64cc, DestBB);
2172 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2173 // conditional branch, hence FPCCToA64CC can set a second test, where either
2174 // passing is sufficient.
2175 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2176 CondCode = FPCCToA64CC(CC, Alternative);
2177 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2178 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2179 DAG.getCondCode(CC));
2180 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2181 Chain, SetCC, A64cc, DestBB);
2183 if (Alternative != A64CC::Invalid) {
2184 A64cc = DAG.getConstant(Alternative, MVT::i32);
2185 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2186 A64BR_CC, SetCC, A64cc, DestBB);
2194 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
2195 RTLIB::Libcall Call) const {
2198 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
2199 EVT ArgVT = Op.getOperand(i).getValueType();
2200 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2201 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
2202 Entry.isSExt = false;
2203 Entry.isZExt = false;
2204 Args.push_back(Entry);
2206 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
2208 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2210 // By default, the input chain to this libcall is the entry node of the
2211 // function. If the libcall is going to be emitted as a tail call then
2212 // isUsedByReturnOnly will change it to the right chain if the return
2213 // node which is being folded has a non-entry input chain.
2214 SDValue InChain = DAG.getEntryNode();
2216 // isTailCall may be true since the callee does not reference caller stack
2217 // frame. Check if it's in the right position.
2218 SDValue TCChain = InChain;
2219 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
2224 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
2225 0, getLibcallCallingConv(Call), isTailCall,
2226 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2227 Callee, Args, DAG, SDLoc(Op));
2228 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2230 if (!CallInfo.second.getNode())
2231 // It's a tailcall, return the chain (which is the DAG root).
2232 return DAG.getRoot();
2234 return CallInfo.first;
2238 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
2239 if (Op.getOperand(0).getValueType() != MVT::f128) {
2240 // It's legal except when f128 is involved
2245 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
2247 SDValue SrcVal = Op.getOperand(0);
2248 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
2249 /*isSigned*/ false, SDLoc(Op)).first;
2253 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
2254 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
2257 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
2259 return LowerF128ToCall(Op, DAG, LC);
2262 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2265 EVT VT = Op.getValueType();
2266 SDValue Vec = Op.getOperand(0);
2267 EVT OpVT = Vec.getValueType();
2268 unsigned Opc = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
2270 if (VT.getVectorNumElements() == 1) {
2271 assert(OpVT == MVT::v1f64 && "Unexpected vector type!");
2272 if (VT.getSizeInBits() == OpVT.getSizeInBits())
2274 return DAG.UnrollVectorOp(Op.getNode());
2277 if (VT.getSizeInBits() > OpVT.getSizeInBits()) {
2278 assert(Vec.getValueType() == MVT::v2f32 && VT == MVT::v2i64 &&
2279 "Unexpected vector type!");
2280 Vec = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Vec);
2281 return DAG.getNode(Opc, dl, VT, Vec);
2282 } else if (VT.getSizeInBits() < OpVT.getSizeInBits()) {
2283 EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
2284 OpVT.getVectorElementType().getSizeInBits());
2286 EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
2287 Vec = DAG.getNode(Opc, dl, CastVT, Vec);
2288 return DAG.getNode(ISD::TRUNCATE, dl, VT, Vec);
2290 return DAG.getNode(Opc, dl, VT, Vec);
2293 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2294 // We custom lower concat_vectors with 4, 8, or 16 operands that are all the
2295 // same operand and of type v1* using the DUP instruction.
2296 unsigned NumOps = Op->getNumOperands();
2298 assert(Op.getValueType().getSizeInBits() == 128 && "unexpected concat");
2302 if (NumOps != 4 && NumOps != 8 && NumOps != 16)
2305 // Must be a single value for VDUP.
2306 SDValue Op0 = Op.getOperand(0);
2307 for (unsigned i = 1; i < NumOps; ++i) {
2308 SDValue OpN = Op.getOperand(i);
2313 // Verify the value type.
2314 EVT EltVT = Op0.getValueType();
2316 default: llvm_unreachable("Unexpected number of operands");
2318 if (EltVT != MVT::v1i16 && EltVT != MVT::v1i32)
2322 if (EltVT != MVT::v1i8 && EltVT != MVT::v1i16)
2326 if (EltVT != MVT::v1i8)
2332 EVT VT = Op.getValueType();
2333 // VDUP produces better code for constants.
2334 if (Op0->getOpcode() == ISD::BUILD_VECTOR)
2335 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Op0->getOperand(0));
2336 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, Op0,
2337 DAG.getConstant(0, MVT::i64));
2341 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2342 bool IsSigned) const {
2343 if (Op.getValueType().isVector())
2344 return LowerVectorFP_TO_INT(Op, DAG, IsSigned);
2345 if (Op.getOperand(0).getValueType() != MVT::f128) {
2346 // It's legal except when f128 is involved
2352 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2354 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2356 return LowerF128ToCall(Op, DAG, LC);
2359 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2360 MachineFunction &MF = DAG.getMachineFunction();
2361 MachineFrameInfo *MFI = MF.getFrameInfo();
2362 MFI->setReturnAddressIsTaken(true);
2364 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2367 EVT VT = Op.getValueType();
2369 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2371 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2372 SDValue Offset = DAG.getConstant(8, MVT::i64);
2373 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2374 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2375 MachinePointerInfo(), false, false, false, 0);
2378 // Return X30, which contains the return address. Mark it an implicit live-in.
2379 unsigned Reg = MF.addLiveIn(AArch64::X30, getRegClassFor(MVT::i64));
2380 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, MVT::i64);
2384 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
2386 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2387 MFI->setFrameAddressIsTaken(true);
2389 EVT VT = Op.getValueType();
2391 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2392 unsigned FrameReg = AArch64::X29;
2393 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2395 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2396 MachinePointerInfo(),
2397 false, false, false, 0);
2402 AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op,
2403 SelectionDAG &DAG) const {
2404 assert(getTargetMachine().getCodeModel() == CodeModel::Large);
2405 assert(getTargetMachine().getRelocationModel() == Reloc::Static);
2407 EVT PtrVT = getPointerTy();
2409 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2410 const GlobalValue *GV = GN->getGlobal();
2412 SDValue GlobalAddr = DAG.getNode(
2413 AArch64ISD::WrapperLarge, dl, PtrVT,
2414 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3),
2415 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2416 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2417 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2419 if (GN->getOffset() != 0)
2420 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2421 DAG.getConstant(GN->getOffset(), PtrVT));
2427 AArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op,
2428 SelectionDAG &DAG) const {
2429 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
2431 EVT PtrVT = getPointerTy();
2433 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2434 const GlobalValue *GV = GN->getGlobal();
2435 unsigned Alignment = GV->getAlignment();
2436 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2437 if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) {
2438 // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate
2439 // to zero when they remain undefined. In PIC mode the GOT can take care of
2440 // this, but in absolute mode we use a constant pool load.
2442 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2443 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2444 AArch64II::MO_NO_FLAG),
2445 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2446 AArch64II::MO_LO12),
2447 DAG.getConstant(8, MVT::i32));
2448 SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
2449 MachinePointerInfo::getConstantPool(),
2450 /*isVolatile=*/ false,
2451 /*isNonTemporal=*/ true,
2452 /*isInvariant=*/ true, 8);
2453 if (GN->getOffset() != 0)
2454 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2455 DAG.getConstant(GN->getOffset(), PtrVT));
2460 if (Alignment == 0) {
2461 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
2462 if (GVPtrTy->getElementType()->isSized()) {
2464 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
2466 // Be conservative if we can't guess, not that it really matters:
2467 // functions and labels aren't valid for loads, and the methods used to
2468 // actually calculate an address work with any alignment.
2473 unsigned char HiFixup, LoFixup;
2474 bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM);
2477 HiFixup = AArch64II::MO_GOT;
2478 LoFixup = AArch64II::MO_GOT_LO12;
2481 HiFixup = AArch64II::MO_NO_FLAG;
2482 LoFixup = AArch64II::MO_LO12;
2485 // AArch64's small model demands the following sequence:
2486 // ADRP x0, somewhere
2487 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
2488 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2489 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2491 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2493 DAG.getConstant(Alignment, MVT::i32));
2496 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
2500 if (GN->getOffset() != 0)
2501 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
2502 DAG.getConstant(GN->getOffset(), PtrVT));
2508 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
2509 SelectionDAG &DAG) const {
2510 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
2511 // we make those distinctions here.
2513 switch (getTargetMachine().getCodeModel()) {
2514 case CodeModel::Small:
2515 return LowerGlobalAddressELFSmall(Op, DAG);
2516 case CodeModel::Large:
2517 return LowerGlobalAddressELFLarge(Op, DAG);
2519 llvm_unreachable("Only small and large code models supported now");
2524 AArch64TargetLowering::LowerConstantPool(SDValue Op,
2525 SelectionDAG &DAG) const {
2527 EVT PtrVT = getPointerTy();
2528 ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Op);
2529 const Constant *C = CN->getConstVal();
2531 switch(getTargetMachine().getCodeModel()) {
2532 case CodeModel::Small:
2533 // The most efficient code is PC-relative anyway for the small memory model,
2534 // so we don't need to worry about relocation model.
2535 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2536 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2537 AArch64II::MO_NO_FLAG),
2538 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2539 AArch64II::MO_LO12),
2540 DAG.getConstant(CN->getAlignment(), MVT::i32));
2541 case CodeModel::Large:
2543 AArch64ISD::WrapperLarge, DL, PtrVT,
2544 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
2545 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
2546 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
2547 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC));
2549 llvm_unreachable("Only small and large code models supported now");
2553 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
2556 SelectionDAG &DAG) const {
2557 EVT PtrVT = getPointerTy();
2559 // The function we need to call is simply the first entry in the GOT for this
2560 // descriptor, load it in preparation.
2561 SDValue Func, Chain;
2562 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2565 // The function takes only one argument: the address of the descriptor itself
2568 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2569 Glue = Chain.getValue(1);
2571 // Finally, there's a special calling-convention which means that the lookup
2572 // must preserve all registers (except X0, obviously).
2573 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2574 const AArch64RegisterInfo *A64RI
2575 = static_cast<const AArch64RegisterInfo *>(TRI);
2576 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
2578 // We're now ready to populate the argument list, as with a normal call:
2579 std::vector<SDValue> Ops;
2580 Ops.push_back(Chain);
2581 Ops.push_back(Func);
2582 Ops.push_back(SymAddr);
2583 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2584 Ops.push_back(DAG.getRegisterMask(Mask));
2585 Ops.push_back(Glue);
2587 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2588 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
2590 Glue = Chain.getValue(1);
2592 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
2593 // back to the generic handling code.
2594 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2598 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2599 SelectionDAG &DAG) const {
2600 assert(getSubtarget()->isTargetELF() &&
2601 "TLS not implemented for non-ELF targets");
2602 assert(getTargetMachine().getCodeModel() == CodeModel::Small
2603 && "TLS only supported in small memory model");
2604 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2606 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2609 EVT PtrVT = getPointerTy();
2611 const GlobalValue *GV = GA->getGlobal();
2613 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2615 if (Model == TLSModel::InitialExec) {
2616 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2617 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2618 AArch64II::MO_GOTTPREL),
2619 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2620 AArch64II::MO_GOTTPREL_LO12),
2621 DAG.getConstant(8, MVT::i32));
2622 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2624 } else if (Model == TLSModel::LocalExec) {
2625 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2626 AArch64II::MO_TPREL_G1);
2627 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2628 AArch64II::MO_TPREL_G0_NC);
2630 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2631 DAG.getTargetConstant(1, MVT::i32)), 0);
2632 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2634 DAG.getTargetConstant(0, MVT::i32)), 0);
2635 } else if (Model == TLSModel::GeneralDynamic) {
2636 // Accesses used in this sequence go via the TLS descriptor which lives in
2637 // the GOT. Prepare an address we can use to handle this.
2638 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2639 AArch64II::MO_TLSDESC);
2640 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2641 AArch64II::MO_TLSDESC_LO12);
2642 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2644 DAG.getConstant(8, MVT::i32));
2645 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2647 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2648 } else if (Model == TLSModel::LocalDynamic) {
2649 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2650 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2651 // the beginning of the module's TLS region, followed by a DTPREL offset
2654 // These accesses will need deduplicating if there's more than one.
2655 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2656 .getInfo<AArch64MachineFunctionInfo>();
2657 MFI->incNumLocalDynamicTLSAccesses();
2660 // Get the location of _TLS_MODULE_BASE_:
2661 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2662 AArch64II::MO_TLSDESC);
2663 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2664 AArch64II::MO_TLSDESC_LO12);
2665 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2667 DAG.getConstant(8, MVT::i32));
2668 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2670 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2672 // Get the variable's offset from _TLS_MODULE_BASE_
2673 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2674 AArch64II::MO_DTPREL_G1);
2675 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2676 AArch64II::MO_DTPREL_G0_NC);
2678 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2679 DAG.getTargetConstant(0, MVT::i32)), 0);
2680 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2682 DAG.getTargetConstant(0, MVT::i32)), 0);
2684 llvm_unreachable("Unsupported TLS access model");
2687 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2690 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2693 EVT VT = Op.getValueType();
2694 SDValue Vec = Op.getOperand(0);
2695 unsigned Opc = IsSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
2697 if (VT.getVectorNumElements() == 1) {
2698 assert(VT == MVT::v1f64 && "Unexpected vector type!");
2699 if (VT.getSizeInBits() == Vec.getValueSizeInBits())
2701 return DAG.UnrollVectorOp(Op.getNode());
2704 if (VT.getSizeInBits() < Vec.getValueSizeInBits()) {
2705 assert(Vec.getValueType() == MVT::v2i64 && VT == MVT::v2f32 &&
2706 "Unexpected vector type!");
2707 Vec = DAG.getNode(Opc, dl, MVT::v2f64, Vec);
2708 return DAG.getNode(ISD::FP_ROUND, dl, VT, Vec, DAG.getIntPtrConstant(0));
2709 } else if (VT.getSizeInBits() > Vec.getValueSizeInBits()) {
2710 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2711 EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
2712 VT.getVectorElementType().getSizeInBits());
2714 EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
2715 Vec = DAG.getNode(CastOpc, dl, CastVT, Vec);
2718 return DAG.getNode(Opc, dl, VT, Vec);
2722 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2723 bool IsSigned) const {
2724 if (Op.getValueType().isVector())
2725 return LowerVectorINT_TO_FP(Op, DAG, IsSigned);
2726 if (Op.getValueType() != MVT::f128) {
2727 // Legal for everything except f128.
2733 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2735 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2737 return LowerF128ToCall(Op, DAG, LC);
2742 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2743 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2745 EVT PtrVT = getPointerTy();
2747 // When compiling PIC, jump tables get put in the code section so a static
2748 // relocation-style is acceptable for both cases.
2749 switch (getTargetMachine().getCodeModel()) {
2750 case CodeModel::Small:
2751 return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2752 DAG.getTargetJumpTable(JT->getIndex(), PtrVT),
2753 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2754 AArch64II::MO_LO12),
2755 DAG.getConstant(1, MVT::i32));
2756 case CodeModel::Large:
2758 AArch64ISD::WrapperLarge, dl, PtrVT,
2759 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3),
2760 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC),
2761 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC),
2762 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC));
2764 llvm_unreachable("Only small and large code models supported now");
2768 // (SELECT testbit, iftrue, iffalse)
2770 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2772 SDValue TheBit = Op.getOperand(0);
2773 SDValue IfTrue = Op.getOperand(1);
2774 SDValue IfFalse = Op.getOperand(2);
2776 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2777 // that as the consumer we are responsible for ignoring rubbish in higher
2779 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2780 DAG.getConstant(1, MVT::i32));
2781 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2782 DAG.getConstant(0, TheBit.getValueType()),
2783 DAG.getCondCode(ISD::SETNE));
2785 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2786 A64CMP, IfTrue, IfFalse,
2787 DAG.getConstant(A64CC::NE, MVT::i32));
2790 static SDValue LowerVectorSETCC(SDValue Op, SelectionDAG &DAG) {
2792 SDValue LHS = Op.getOperand(0);
2793 SDValue RHS = Op.getOperand(1);
2794 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2795 EVT VT = Op.getValueType();
2796 bool Invert = false;
2800 if (LHS.getValueType().isInteger()) {
2802 // Attempt to use Vector Integer Compare Mask Test instruction.
2803 // TST = icmp ne (and (op0, op1), zero).
2804 if (CC == ISD::SETNE) {
2805 if (((LHS.getOpcode() == ISD::AND) &&
2806 ISD::isBuildVectorAllZeros(RHS.getNode())) ||
2807 ((RHS.getOpcode() == ISD::AND) &&
2808 ISD::isBuildVectorAllZeros(LHS.getNode()))) {
2810 SDValue AndOp = (LHS.getOpcode() == ISD::AND) ? LHS : RHS;
2811 SDValue NewLHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(0));
2812 SDValue NewRHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(1));
2813 return DAG.getNode(AArch64ISD::NEON_TST, DL, VT, NewLHS, NewRHS);
2817 // Attempt to use Vector Integer Compare Mask against Zero instr (Signed).
2818 // Note: Compare against Zero does not support unsigned predicates.
2819 if ((ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2820 ISD::isBuildVectorAllZeros(LHS.getNode())) &&
2821 !isUnsignedIntSetCC(CC)) {
2823 // If LHS is the zero value, swap operands and CondCode.
2824 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2825 CC = getSetCCSwappedOperands(CC);
2830 // Ensure valid CondCode for Compare Mask against Zero instruction:
2831 // EQ, GE, GT, LE, LT.
2832 if (ISD::SETNE == CC) {
2837 // Using constant type to differentiate integer and FP compares with zero.
2838 Op1 = DAG.getConstant(0, MVT::i32);
2839 Opcode = AArch64ISD::NEON_CMPZ;
2842 // Attempt to use Vector Integer Compare Mask instr (Signed/Unsigned).
2843 // Ensure valid CondCode for Compare Mask instr: EQ, GE, GT, UGE, UGT.
2847 llvm_unreachable("Illegal integer comparison.");
2863 CC = getSetCCSwappedOperands(CC);
2867 std::swap(LHS, RHS);
2869 Opcode = AArch64ISD::NEON_CMP;
2874 // Generate Compare Mask instr or Compare Mask against Zero instr.
2876 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2879 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2884 // Now handle Floating Point cases.
2885 // Attempt to use Vector Floating Point Compare Mask against Zero instruction.
2886 if (ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2887 ISD::isBuildVectorAllZeros(LHS.getNode())) {
2889 // If LHS is the zero value, swap operands and CondCode.
2890 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2891 CC = getSetCCSwappedOperands(CC);
2896 // Using constant type to differentiate integer and FP compares with zero.
2897 Op1 = DAG.getConstantFP(0, MVT::f32);
2898 Opcode = AArch64ISD::NEON_CMPZ;
2900 // Attempt to use Vector Floating Point Compare Mask instruction.
2903 Opcode = AArch64ISD::NEON_CMP;
2907 // Some register compares have to be implemented with swapped CC and operands,
2908 // e.g.: OLT implemented as OGT with swapped operands.
2909 bool SwapIfRegArgs = false;
2911 // Ensure valid CondCode for FP Compare Mask against Zero instruction:
2912 // EQ, GE, GT, LE, LT.
2913 // And ensure valid CondCode for FP Compare Mask instruction: EQ, GE, GT.
2916 llvm_unreachable("Illegal FP comparison");
2919 Invert = true; // Fallthrough
2927 SwapIfRegArgs = true;
2936 SwapIfRegArgs = true;
2945 SwapIfRegArgs = true;
2954 SwapIfRegArgs = true;
2961 Invert = true; // Fallthrough
2963 // Expand this to (OGT |OLT).
2965 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT));
2967 SwapIfRegArgs = true;
2970 Invert = true; // Fallthrough
2972 // Expand this to (OGE | OLT).
2974 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE));
2976 SwapIfRegArgs = true;
2980 if (Opcode == AArch64ISD::NEON_CMP && SwapIfRegArgs) {
2981 CC = getSetCCSwappedOperands(CC);
2982 std::swap(Op0, Op1);
2985 // Generate FP Compare Mask instr or FP Compare Mask against Zero instr
2986 SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2988 if (NeonCmpAlt.getNode())
2989 NeonCmp = DAG.getNode(ISD::OR, DL, VT, NeonCmp, NeonCmpAlt);
2992 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2997 // (SETCC lhs, rhs, condcode)
2999 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3001 SDValue LHS = Op.getOperand(0);
3002 SDValue RHS = Op.getOperand(1);
3003 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3004 EVT VT = Op.getValueType();
3007 return LowerVectorSETCC(Op, DAG);
3009 if (LHS.getValueType() == MVT::f128) {
3010 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
3011 // for the rest of the function (some i32 or i64 values).
3012 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3014 // If softenSetCCOperands returned a scalar, use it.
3015 if (RHS.getNode() == 0) {
3016 assert(LHS.getValueType() == Op.getValueType() &&
3017 "Unexpected setcc expansion!");
3022 if (LHS.getValueType().isInteger()) {
3025 // Integers are handled in a separate function because the combinations of
3026 // immediates and tests can get hairy and we may want to fiddle things.
3027 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
3029 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
3030 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3034 // Note that some LLVM floating-point CondCodes can't be lowered to a single
3035 // conditional branch, hence FPCCToA64CC can set a second test, where either
3036 // passing is sufficient.
3037 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3038 CondCode = FPCCToA64CC(CC, Alternative);
3039 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3040 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3041 DAG.getCondCode(CC));
3042 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
3043 CmpOp, DAG.getConstant(1, VT),
3044 DAG.getConstant(0, VT), A64cc);
3046 if (Alternative != A64CC::Invalid) {
3047 A64cc = DAG.getConstant(Alternative, MVT::i32);
3048 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
3049 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
3052 return A64SELECT_CC;
3055 static SDValue LowerVectorSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3057 SDValue LHS = Op.getOperand(0);
3058 SDValue RHS = Op.getOperand(1);
3059 SDValue IfTrue = Op.getOperand(2);
3060 SDValue IfFalse = Op.getOperand(3);
3061 EVT IfTrueVT = IfTrue.getValueType();
3062 EVT CondVT = IfTrueVT.changeVectorElementTypeToInteger();
3063 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3065 // If LHS & RHS are floating point and IfTrue & IfFalse are vectors, we will
3066 // use NEON compare.
3067 if ((LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64)) {
3068 EVT EltVT = LHS.getValueType();
3069 unsigned EltNum = 128 / EltVT.getSizeInBits();
3070 EVT VT = EVT::getVectorVT(*DAG.getContext(), EltVT, EltNum);
3071 unsigned SubConstant =
3072 (LHS.getValueType() == MVT::f32) ? AArch64::sub_32 :AArch64::sub_64;
3073 EVT CEltT = (LHS.getValueType() == MVT::f32) ? MVT::i32 : MVT::i64;
3074 EVT CVT = EVT::getVectorVT(*DAG.getContext(), CEltT, EltNum);
3077 = SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
3078 VT, DAG.getTargetConstant(0, MVT::i32), LHS,
3079 DAG.getTargetConstant(SubConstant, MVT::i32)), 0);
3081 = SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
3082 VT, DAG.getTargetConstant(0, MVT::i32), RHS,
3083 DAG.getTargetConstant(SubConstant, MVT::i32)), 0);
3085 SDValue VSetCC = DAG.getSetCC(dl, CVT, LHS, RHS, CC);
3086 SDValue ResCC = LowerVectorSETCC(VSetCC, DAG);
3087 if (CEltT.getSizeInBits() < IfTrueVT.getSizeInBits()) {
3089 EVT::getVectorVT(*DAG.getContext(), CEltT,
3090 IfTrueVT.getSizeInBits() / CEltT.getSizeInBits());
3091 ResCC = DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, DUPVT, ResCC,
3092 DAG.getConstant(0, MVT::i64, false));
3094 ResCC = DAG.getNode(ISD::BITCAST, dl, CondVT, ResCC);
3096 // FIXME: If IfTrue & IfFalse hold v1i8, v1i16 or v1i32, this function
3097 // can't handle them and will hit this assert.
3098 assert(CEltT.getSizeInBits() == IfTrueVT.getSizeInBits() &&
3099 "Vector of IfTrue & IfFalse is too small.");
3102 EltNum * IfTrueVT.getSizeInBits() / ResCC.getValueSizeInBits();
3103 EVT ExVT = EVT::getVectorVT(*DAG.getContext(), CEltT, ExEltNum);
3104 ResCC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ExVT, ResCC,
3105 DAG.getConstant(0, MVT::i64, false));
3106 ResCC = DAG.getNode(ISD::BITCAST, dl, CondVT, ResCC);
3108 SDValue VSelect = DAG.getNode(ISD::VSELECT, dl, IfTrue.getValueType(),
3109 ResCC, IfTrue, IfFalse);
3113 // Here we handle the case that LHS & RHS are integer and IfTrue & IfFalse are
3115 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3116 CondCode = FPCCToA64CC(CC, Alternative);
3117 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3118 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3119 DAG.getCondCode(CC));
3120 EVT SEVT = MVT::i32;
3121 if (IfTrue.getValueType().getVectorElementType().getSizeInBits() > 32)
3123 SDValue AllOne = DAG.getConstant(-1, SEVT);
3124 SDValue AllZero = DAG.getConstant(0, SEVT);
3125 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, SEVT, SetCC,
3126 AllOne, AllZero, A64cc);
3128 if (Alternative != A64CC::Invalid) {
3129 A64cc = DAG.getConstant(Alternative, MVT::i32);
3130 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
3131 SetCC, AllOne, A64SELECT_CC, A64cc);
3134 if (IfTrue.getValueType().getVectorNumElements() == 1)
3135 VDup = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, CondVT, A64SELECT_CC);
3137 VDup = DAG.getNode(AArch64ISD::NEON_VDUP, dl, CondVT, A64SELECT_CC);
3138 SDValue VSelect = DAG.getNode(ISD::VSELECT, dl, IfTrue.getValueType(),
3139 VDup, IfTrue, IfFalse);
3143 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
3145 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3147 SDValue LHS = Op.getOperand(0);
3148 SDValue RHS = Op.getOperand(1);
3149 SDValue IfTrue = Op.getOperand(2);
3150 SDValue IfFalse = Op.getOperand(3);
3151 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3153 if (IfTrue.getValueType().isVector())
3154 return LowerVectorSELECT_CC(Op, DAG);
3156 if (LHS.getValueType() == MVT::f128) {
3157 // f128 comparisons are lowered to libcalls, but slot in nicely here
3159 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3161 // If softenSetCCOperands returned a scalar, we need to compare the result
3162 // against zero to select between true and false values.
3163 if (RHS.getNode() == 0) {
3164 RHS = DAG.getConstant(0, LHS.getValueType());
3169 if (LHS.getValueType().isInteger()) {
3172 // Integers are handled in a separate function because the combinations of
3173 // immediates and tests can get hairy and we may want to fiddle things.
3174 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
3176 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), CmpOp,
3177 IfTrue, IfFalse, A64cc);
3180 // Note that some LLVM floating-point CondCodes can't be lowered to a single
3181 // conditional branch, hence FPCCToA64CC can set a second test, where either
3182 // passing is sufficient.
3183 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3184 CondCode = FPCCToA64CC(CC, Alternative);
3185 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3186 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3187 DAG.getCondCode(CC));
3188 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
3190 SetCC, IfTrue, IfFalse, A64cc);
3192 if (Alternative != A64CC::Invalid) {
3193 A64cc = DAG.getConstant(Alternative, MVT::i32);
3194 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
3195 SetCC, IfTrue, A64SELECT_CC, A64cc);
3199 return A64SELECT_CC;
3203 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3204 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3205 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3207 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
3208 // rather than just 8.
3209 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op),
3210 Op.getOperand(1), Op.getOperand(2),
3211 DAG.getConstant(32, MVT::i32), 8, false, false,
3212 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
3216 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3217 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3218 // Standard, section B.3.
3219 MachineFunction &MF = DAG.getMachineFunction();
3220 AArch64MachineFunctionInfo *FuncInfo
3221 = MF.getInfo<AArch64MachineFunctionInfo>();
3224 SDValue Chain = Op.getOperand(0);
3225 SDValue VAList = Op.getOperand(1);
3226 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3227 SmallVector<SDValue, 4> MemOps;
3229 // void *__stack at offset 0
3230 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
3232 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3233 MachinePointerInfo(SV), false, false, 0));
3235 // void *__gr_top at offset 8
3236 int GPRSize = FuncInfo->getVariadicGPRSize();
3238 SDValue GRTop, GRTopAddr;
3240 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3241 DAG.getConstant(8, getPointerTy()));
3243 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
3244 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3245 DAG.getConstant(GPRSize, getPointerTy()));
3247 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3248 MachinePointerInfo(SV, 8),
3252 // void *__vr_top at offset 16
3253 int FPRSize = FuncInfo->getVariadicFPRSize();
3255 SDValue VRTop, VRTopAddr;
3256 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3257 DAG.getConstant(16, getPointerTy()));
3259 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
3260 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3261 DAG.getConstant(FPRSize, getPointerTy()));
3263 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3264 MachinePointerInfo(SV, 16),
3268 // int __gr_offs at offset 24
3269 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3270 DAG.getConstant(24, getPointerTy()));
3271 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3272 GROffsAddr, MachinePointerInfo(SV, 24),
3275 // int __vr_offs at offset 28
3276 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3277 DAG.getConstant(28, getPointerTy()));
3278 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3279 VROffsAddr, MachinePointerInfo(SV, 28),
3282 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
3287 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3288 switch (Op.getOpcode()) {
3289 default: llvm_unreachable("Don't know how to custom lower this!");
3290 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
3291 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
3292 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
3293 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
3294 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
3295 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
3296 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
3297 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
3298 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
3299 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
3300 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3301 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3303 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3304 case ISD::SRL_PARTS:
3305 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3307 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3308 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3309 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3310 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
3311 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3312 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3313 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3314 case ISD::SELECT: return LowerSELECT(Op, DAG);
3315 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3316 case ISD::SETCC: return LowerSETCC(Op, DAG);
3317 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3318 case ISD::VASTART: return LowerVASTART(Op, DAG);
3319 case ISD::BUILD_VECTOR:
3320 return LowerBUILD_VECTOR(Op, DAG, getSubtarget());
3321 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3322 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3328 /// Check if the specified splat value corresponds to a valid vector constant
3329 /// for a Neon instruction with a "modified immediate" operand (e.g., MOVI). If
3330 /// so, return the encoded 8-bit immediate and the OpCmode instruction fields
3332 static bool isNeonModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3333 unsigned SplatBitSize, SelectionDAG &DAG,
3334 bool is128Bits, NeonModImmType type, EVT &VT,
3335 unsigned &Imm, unsigned &OpCmode) {
3336 switch (SplatBitSize) {
3338 llvm_unreachable("unexpected size for isNeonModifiedImm");
3340 if (type != Neon_Mov_Imm)
3342 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3343 // Neon movi per byte: Op=0, Cmode=1110.
3346 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3350 // Neon move inst per halfword
3351 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3352 if ((SplatBits & ~0xff) == 0) {
3353 // Value = 0x00nn is 0x00nn LSL 0
3354 // movi: Op=0, Cmode=1000; mvni: Op=1, Cmode=1000
3355 // bic: Op=1, Cmode=1001; orr: Op=0, Cmode=1001
3361 if ((SplatBits & ~0xff00) == 0) {
3362 // Value = 0xnn00 is 0x00nn LSL 8
3363 // movi: Op=0, Cmode=1010; mvni: Op=1, Cmode=1010
3364 // bic: Op=1, Cmode=1011; orr: Op=0, Cmode=1011
3366 Imm = SplatBits >> 8;
3370 // can't handle any other
3375 // First the LSL variants (MSL is unusable by some interested instructions).
3377 // Neon move instr per word, shift zeros
3378 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3379 if ((SplatBits & ~0xff) == 0) {
3380 // Value = 0x000000nn is 0x000000nn LSL 0
3381 // movi: Op=0, Cmode= 0000; mvni: Op=1, Cmode= 0000
3382 // bic: Op=1, Cmode= 0001; orr: Op=0, Cmode= 0001
3388 if ((SplatBits & ~0xff00) == 0) {
3389 // Value = 0x0000nn00 is 0x000000nn LSL 8
3390 // movi: Op=0, Cmode= 0010; mvni: Op=1, Cmode= 0010
3391 // bic: Op=1, Cmode= 0011; orr : Op=0, Cmode= 0011
3393 Imm = SplatBits >> 8;
3397 if ((SplatBits & ~0xff0000) == 0) {
3398 // Value = 0x00nn0000 is 0x000000nn LSL 16
3399 // movi: Op=0, Cmode= 0100; mvni: Op=1, Cmode= 0100
3400 // bic: Op=1, Cmode= 0101; orr: Op=0, Cmode= 0101
3402 Imm = SplatBits >> 16;
3406 if ((SplatBits & ~0xff000000) == 0) {
3407 // Value = 0xnn000000 is 0x000000nn LSL 24
3408 // movi: Op=0, Cmode= 0110; mvni: Op=1, Cmode= 0110
3409 // bic: Op=1, Cmode= 0111; orr: Op=0, Cmode= 0111
3411 Imm = SplatBits >> 24;
3416 // Now the MSL immediates.
3418 // Neon move instr per word, shift ones
3419 if ((SplatBits & ~0xffff) == 0 &&
3420 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3421 // Value = 0x0000nnff is 0x000000nn MSL 8
3422 // movi: Op=0, Cmode= 1100; mvni: Op=1, Cmode= 1100
3424 Imm = SplatBits >> 8;
3428 if ((SplatBits & ~0xffffff) == 0 &&
3429 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3430 // Value = 0x00nnffff is 0x000000nn MSL 16
3431 // movi: Op=1, Cmode= 1101; mvni: Op=1, Cmode= 1101
3433 Imm = SplatBits >> 16;
3437 // can't handle any other
3442 if (type != Neon_Mov_Imm)
3444 // Neon move instr bytemask, where each byte is either 0x00 or 0xff.
3445 // movi Op=1, Cmode=1110.
3447 uint64_t BitMask = 0xff;
3449 unsigned ImmMask = 1;
3451 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3452 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3455 } else if ((SplatBits & BitMask) != 0) {
3462 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3470 static SDValue PerformANDCombine(SDNode *N,
3471 TargetLowering::DAGCombinerInfo &DCI) {
3473 SelectionDAG &DAG = DCI.DAG;
3475 EVT VT = N->getValueType(0);
3477 // We're looking for an SRA/SHL pair which form an SBFX.
3479 if (VT != MVT::i32 && VT != MVT::i64)
3482 if (!isa<ConstantSDNode>(N->getOperand(1)))
3485 uint64_t TruncMask = N->getConstantOperandVal(1);
3486 if (!isMask_64(TruncMask))
3489 uint64_t Width = CountPopulation_64(TruncMask);
3490 SDValue Shift = N->getOperand(0);
3492 if (Shift.getOpcode() != ISD::SRL)
3495 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3497 uint64_t LSB = Shift->getConstantOperandVal(1);
3499 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3502 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
3503 DAG.getConstant(LSB, MVT::i64),
3504 DAG.getConstant(LSB + Width - 1, MVT::i64));
3507 /// For a true bitfield insert, the bits getting into that contiguous mask
3508 /// should come from the low part of an existing value: they must be formed from
3509 /// a compatible SHL operation (unless they're already low). This function
3510 /// checks that condition and returns the least-significant bit that's
3511 /// intended. If the operation not a field preparation, -1 is returned.
3512 static int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT,
3513 SDValue &MaskedVal, uint64_t Mask) {
3514 if (!isShiftedMask_64(Mask))
3517 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
3518 // instruction. BFI will do a left-shift by LSB before applying the mask we've
3519 // spotted, so in general we should pre-emptively "undo" that by making sure
3520 // the incoming bits have had a right-shift applied to them.
3522 // This right shift, however, will combine with existing left/right shifts. In
3523 // the simplest case of a completely straight bitfield operation, it will be
3524 // expected to completely cancel out with an existing SHL. More complicated
3525 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
3528 uint64_t LSB = countTrailingZeros(Mask);
3529 int64_t ShiftRightRequired = LSB;
3530 if (MaskedVal.getOpcode() == ISD::SHL &&
3531 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3532 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
3533 MaskedVal = MaskedVal.getOperand(0);
3534 } else if (MaskedVal.getOpcode() == ISD::SRL &&
3535 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3536 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
3537 MaskedVal = MaskedVal.getOperand(0);
3540 if (ShiftRightRequired > 0)
3541 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
3542 DAG.getConstant(ShiftRightRequired, MVT::i64));
3543 else if (ShiftRightRequired < 0) {
3544 // We could actually end up with a residual left shift, for example with
3545 // "struc.bitfield = val << 1".
3546 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
3547 DAG.getConstant(-ShiftRightRequired, MVT::i64));
3553 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
3554 /// a mask and an extension. Returns true if a BFI was found and provides
3555 /// information on its surroundings.
3556 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
3559 if (N.getOpcode() == ISD::ZERO_EXTEND) {
3561 N = N.getOperand(0);
3564 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
3565 Mask = N->getConstantOperandVal(1);
3566 N = N.getOperand(0);
3568 // Mask is the whole width.
3569 Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
3572 if (N.getOpcode() == AArch64ISD::BFI) {
3580 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
3581 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
3582 /// can often be further combined with a larger mask. Ultimately, we want mask
3583 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
3584 static SDValue tryCombineToBFI(SDNode *N,
3585 TargetLowering::DAGCombinerInfo &DCI,
3586 const AArch64Subtarget *Subtarget) {
3587 SelectionDAG &DAG = DCI.DAG;
3589 EVT VT = N->getValueType(0);
3591 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3593 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
3594 // abandon the effort.
3595 SDValue LHS = N->getOperand(0);
3596 if (LHS.getOpcode() != ISD::AND)
3600 if (isa<ConstantSDNode>(LHS.getOperand(1)))
3601 LHSMask = LHS->getConstantOperandVal(1);
3605 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
3606 // is or abandon the effort.
3607 SDValue RHS = N->getOperand(1);
3608 if (RHS.getOpcode() != ISD::AND)
3612 if (isa<ConstantSDNode>(RHS.getOperand(1)))
3613 RHSMask = RHS->getConstantOperandVal(1);
3617 // Can't do anything if the masks are incompatible.
3618 if (LHSMask & RHSMask)
3621 // Now we need one of the masks to be a contiguous field. Without loss of
3622 // generality that should be the RHS one.
3623 SDValue Bitfield = LHS.getOperand(0);
3624 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
3625 // We know that LHS is a candidate new value, and RHS isn't already a better
3627 std::swap(LHS, RHS);
3628 std::swap(LHSMask, RHSMask);
3631 // We've done our best to put the right operands in the right places, all we
3632 // can do now is check whether a BFI exists.
3633 Bitfield = RHS.getOperand(0);
3634 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
3638 uint32_t Width = CountPopulation_64(RHSMask);
3639 assert(Width && "Expected non-zero bitfield width");
3641 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3642 LHS.getOperand(0), Bitfield,
3643 DAG.getConstant(LSB, MVT::i64),
3644 DAG.getConstant(Width, MVT::i64));
3647 if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3650 return DAG.getNode(ISD::AND, DL, VT, BFI,
3651 DAG.getConstant(LHSMask | RHSMask, VT));
3654 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
3655 /// original input. This is surprisingly common because SROA splits things up
3656 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
3657 /// on the low (say) byte of a word. This is then orred into the rest of the
3658 /// word afterwards.
3660 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
3662 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
3663 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
3665 static SDValue tryCombineToLargerBFI(SDNode *N,
3666 TargetLowering::DAGCombinerInfo &DCI,
3667 const AArch64Subtarget *Subtarget) {
3668 SelectionDAG &DAG = DCI.DAG;
3670 EVT VT = N->getValueType(0);
3672 // First job is to hunt for a MaskedBFI on either the left or right. Swap
3673 // operands if it's actually on the right.
3675 SDValue PossExtraMask;
3676 uint64_t ExistingMask = 0;
3677 bool Extended = false;
3678 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
3679 PossExtraMask = N->getOperand(1);
3680 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
3681 PossExtraMask = N->getOperand(0);
3685 // We can only combine a BFI with another compatible mask.
3686 if (PossExtraMask.getOpcode() != ISD::AND ||
3687 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
3690 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
3692 // Masks must be compatible.
3693 if (ExtraMask & ExistingMask)
3696 SDValue OldBFIVal = BFI.getOperand(0);
3697 SDValue NewBFIVal = BFI.getOperand(1);
3699 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
3700 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
3701 // need to be made compatible.
3702 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
3703 && "Invalid types for BFI");
3704 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
3705 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
3708 // We need the MaskedBFI to be combined with a mask of the *same* value.
3709 if (PossExtraMask.getOperand(0) != OldBFIVal)
3712 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3713 OldBFIVal, NewBFIVal,
3714 BFI.getOperand(2), BFI.getOperand(3));
3716 // If the masking is trivial, we don't need to create it.
3717 if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3720 return DAG.getNode(ISD::AND, DL, VT, BFI,
3721 DAG.getConstant(ExtraMask | ExistingMask, VT));
3724 /// An EXTR instruction is made up of two shifts, ORed together. This helper
3725 /// searches for and classifies those shifts.
3726 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
3728 if (N.getOpcode() == ISD::SHL)
3730 else if (N.getOpcode() == ISD::SRL)
3735 if (!isa<ConstantSDNode>(N.getOperand(1)))
3738 ShiftAmount = N->getConstantOperandVal(1);
3739 Src = N->getOperand(0);
3743 /// EXTR instruction extracts a contiguous chunk of bits from two existing
3744 /// registers viewed as a high/low pair. This function looks for the pattern:
3745 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
3746 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
3748 static SDValue tryCombineToEXTR(SDNode *N,
3749 TargetLowering::DAGCombinerInfo &DCI) {
3750 SelectionDAG &DAG = DCI.DAG;
3752 EVT VT = N->getValueType(0);
3754 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3756 if (VT != MVT::i32 && VT != MVT::i64)
3760 uint32_t ShiftLHS = 0;
3762 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
3766 uint32_t ShiftRHS = 0;
3768 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
3771 // If they're both trying to come from the high part of the register, they're
3772 // not really an EXTR.
3773 if (LHSFromHi == RHSFromHi)
3776 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
3780 std::swap(LHS, RHS);
3781 std::swap(ShiftLHS, ShiftRHS);
3784 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
3786 DAG.getConstant(ShiftRHS, MVT::i64));
3789 /// Target-specific dag combine xforms for ISD::OR
3790 static SDValue PerformORCombine(SDNode *N,
3791 TargetLowering::DAGCombinerInfo &DCI,
3792 const AArch64Subtarget *Subtarget) {
3794 SelectionDAG &DAG = DCI.DAG;
3796 EVT VT = N->getValueType(0);
3798 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3801 // Attempt to recognise bitfield-insert operations.
3802 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
3806 // Attempt to combine an existing MaskedBFI operation into one with a larger
3808 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
3812 Res = tryCombineToEXTR(N, DCI);
3816 if (!Subtarget->hasNEON())
3819 // Attempt to use vector immediate-form BSL
3820 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
3822 SDValue N0 = N->getOperand(0);
3823 if (N0.getOpcode() != ISD::AND)
3826 SDValue N1 = N->getOperand(1);
3827 if (N1.getOpcode() != ISD::AND)
3830 if (VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
3832 unsigned SplatBitSize;
3834 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
3836 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
3839 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
3841 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
3842 HasAnyUndefs) && !HasAnyUndefs &&
3843 SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
3844 SplatBits0 == ~SplatBits1) {
3846 return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1),
3847 N0->getOperand(0), N1->getOperand(0));
3855 /// Target-specific dag combine xforms for ISD::SRA
3856 static SDValue PerformSRACombine(SDNode *N,
3857 TargetLowering::DAGCombinerInfo &DCI) {
3859 SelectionDAG &DAG = DCI.DAG;
3861 EVT VT = N->getValueType(0);
3863 // We're looking for an SRA/SHL pair which form an SBFX.
3865 if (VT != MVT::i32 && VT != MVT::i64)
3868 if (!isa<ConstantSDNode>(N->getOperand(1)))
3871 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
3872 SDValue Shift = N->getOperand(0);
3874 if (Shift.getOpcode() != ISD::SHL)
3877 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3880 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
3881 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
3882 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
3884 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3887 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
3888 DAG.getConstant(LSB, MVT::i64),
3889 DAG.getConstant(LSB + Width - 1, MVT::i64));
3892 /// Check if this is a valid build_vector for the immediate operand of
3893 /// a vector shift operation, where all the elements of the build_vector
3894 /// must have the same constant integer value.
3895 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3896 // Ignore bit_converts.
3897 while (Op.getOpcode() == ISD::BITCAST)
3898 Op = Op.getOperand(0);
3899 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3900 APInt SplatBits, SplatUndef;
3901 unsigned SplatBitSize;
3903 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3904 HasAnyUndefs, ElementBits) ||
3905 SplatBitSize > ElementBits)
3907 Cnt = SplatBits.getSExtValue();
3911 /// Check if this is a valid build_vector for the immediate operand of
3912 /// a vector shift left operation. That value must be in the range:
3913 /// 0 <= Value < ElementBits
3914 static bool isVShiftLImm(SDValue Op, EVT VT, int64_t &Cnt) {
3915 assert(VT.isVector() && "vector shift count is not a vector type");
3916 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3917 if (!getVShiftImm(Op, ElementBits, Cnt))
3919 return (Cnt >= 0 && Cnt < ElementBits);
3922 /// Check if this is a valid build_vector for the immediate operand of a
3923 /// vector shift right operation. The value must be in the range:
3924 /// 1 <= Value <= ElementBits
3925 static bool isVShiftRImm(SDValue Op, EVT VT, int64_t &Cnt) {
3926 assert(VT.isVector() && "vector shift count is not a vector type");
3927 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3928 if (!getVShiftImm(Op, ElementBits, Cnt))
3930 return (Cnt >= 1 && Cnt <= ElementBits);
3933 static SDValue GenForSextInreg(SDNode *N,
3934 TargetLowering::DAGCombinerInfo &DCI,
3935 EVT SrcVT, EVT DestVT, EVT SubRegVT,
3936 const int *Mask, SDValue Src) {
3937 SelectionDAG &DAG = DCI.DAG;
3939 = DAG.getNode(ISD::BITCAST, SDLoc(N), SrcVT, Src);
3941 = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), DestVT, Bitcast);
3943 = DAG.getVectorShuffle(DestVT, SDLoc(N), Sext, DAG.getUNDEF(DestVT), Mask);
3944 SDValue ExtractSubreg
3945 = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N),
3946 SubRegVT, ShuffleVec,
3947 DAG.getTargetConstant(AArch64::sub_64, MVT::i32)), 0);
3948 return ExtractSubreg;
3951 /// Checks for vector shifts and lowers them.
3952 static SDValue PerformShiftCombine(SDNode *N,
3953 TargetLowering::DAGCombinerInfo &DCI,
3954 const AArch64Subtarget *ST) {
3955 SelectionDAG &DAG = DCI.DAG;
3956 EVT VT = N->getValueType(0);
3957 if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64))
3958 return PerformSRACombine(N, DCI);
3960 // We're looking for an SRA/SHL pair to help generating instruction
3961 // sshll v0.8h, v0.8b, #0
3962 // The instruction STXL is also the alias of this instruction.
3964 // For example, for DAG like below,
3965 // v2i32 = sra (v2i32 (shl v2i32, 16)), 16
3966 // we can transform it into
3967 // v2i32 = EXTRACT_SUBREG
3968 // (v4i32 (suffle_vector
3969 // (v4i32 (sext (v4i16 (bitcast v2i32))),
3970 // undef, (0, 2, u, u)),
3973 // With this transformation we expect to generate "SSHLL + UZIP1"
3974 // Sometimes UZIP1 can be optimized away by combining with other context.
3975 int64_t ShrCnt, ShlCnt;
3976 if (N->getOpcode() == ISD::SRA
3977 && (VT == MVT::v2i32 || VT == MVT::v4i16)
3978 && isVShiftRImm(N->getOperand(1), VT, ShrCnt)
3979 && N->getOperand(0).getOpcode() == ISD::SHL
3980 && isVShiftRImm(N->getOperand(0).getOperand(1), VT, ShlCnt)) {
3981 SDValue Src = N->getOperand(0).getOperand(0);
3982 if (VT == MVT::v2i32 && ShrCnt == 16 && ShlCnt == 16) {
3983 // sext_inreg(v2i32, v2i16)
3984 // We essentially only care the Mask {0, 2, u, u}
3985 int Mask[4] = {0, 2, 4, 6};
3986 return GenForSextInreg(N, DCI, MVT::v4i16, MVT::v4i32, MVT::v2i32,
3989 else if (VT == MVT::v2i32 && ShrCnt == 24 && ShlCnt == 24) {
3990 // sext_inreg(v2i16, v2i8)
3991 // We essentially only care the Mask {0, u, 4, u, u, u, u, u, u, u, u, u}
3992 int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
3993 return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v2i32,
3996 else if (VT == MVT::v4i16 && ShrCnt == 8 && ShlCnt == 8) {
3997 // sext_inreg(v4i16, v4i8)
3998 // We essentially only care the Mask {0, 2, 4, 6, u, u, u, u, u, u, u, u}
3999 int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
4000 return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v4i16,
4005 // Nothing to be done for scalar shifts.
4006 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4007 if (!VT.isVector() || !TLI.isTypeLegal(VT))
4010 assert(ST->hasNEON() && "unexpected vector shift");
4013 switch (N->getOpcode()) {
4015 llvm_unreachable("unexpected shift opcode");
4018 if (isVShiftLImm(N->getOperand(1), VT, Cnt)) {
4020 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
4021 DAG.getConstant(Cnt, MVT::i32));
4022 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), RHS);
4028 if (isVShiftRImm(N->getOperand(1), VT, Cnt)) {
4030 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
4031 DAG.getConstant(Cnt, MVT::i32));
4032 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N->getOperand(0), RHS);
4040 /// ARM-specific DAG combining for intrinsics.
4041 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4042 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4046 // Don't do anything for most intrinsics.
4049 case Intrinsic::arm_neon_vqshifts:
4050 case Intrinsic::arm_neon_vqshiftu:
4051 EVT VT = N->getOperand(1).getValueType();
4053 if (!isVShiftLImm(N->getOperand(2), VT, Cnt))
4055 unsigned VShiftOpc = (IntNo == Intrinsic::arm_neon_vqshifts)
4056 ? AArch64ISD::NEON_QSHLs
4057 : AArch64ISD::NEON_QSHLu;
4058 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
4059 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4065 /// Target-specific DAG combine function for NEON load/store intrinsics
4066 /// to merge base address updates.
4067 static SDValue CombineBaseUpdate(SDNode *N,
4068 TargetLowering::DAGCombinerInfo &DCI) {
4069 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4072 SelectionDAG &DAG = DCI.DAG;
4073 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
4074 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
4075 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
4076 SDValue Addr = N->getOperand(AddrOpIdx);
4078 // Search for a use of the address operand that is an increment.
4079 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
4080 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
4082 if (User->getOpcode() != ISD::ADD ||
4083 UI.getUse().getResNo() != Addr.getResNo())
4086 // Check that the add is independent of the load/store. Otherwise, folding
4087 // it would create a cycle.
4088 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
4091 // Find the new opcode for the updating load/store.
4093 bool isLaneOp = false;
4094 unsigned NewOpc = 0;
4095 unsigned NumVecs = 0;
4097 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
4099 default: llvm_unreachable("unexpected intrinsic for Neon base update");
4100 case Intrinsic::arm_neon_vld1: NewOpc = AArch64ISD::NEON_LD1_UPD;
4102 case Intrinsic::arm_neon_vld2: NewOpc = AArch64ISD::NEON_LD2_UPD;
4104 case Intrinsic::arm_neon_vld3: NewOpc = AArch64ISD::NEON_LD3_UPD;
4106 case Intrinsic::arm_neon_vld4: NewOpc = AArch64ISD::NEON_LD4_UPD;
4108 case Intrinsic::arm_neon_vst1: NewOpc = AArch64ISD::NEON_ST1_UPD;
4109 NumVecs = 1; isLoad = false; break;
4110 case Intrinsic::arm_neon_vst2: NewOpc = AArch64ISD::NEON_ST2_UPD;
4111 NumVecs = 2; isLoad = false; break;
4112 case Intrinsic::arm_neon_vst3: NewOpc = AArch64ISD::NEON_ST3_UPD;
4113 NumVecs = 3; isLoad = false; break;
4114 case Intrinsic::arm_neon_vst4: NewOpc = AArch64ISD::NEON_ST4_UPD;
4115 NumVecs = 4; isLoad = false; break;
4116 case Intrinsic::aarch64_neon_vld1x2: NewOpc = AArch64ISD::NEON_LD1x2_UPD;
4118 case Intrinsic::aarch64_neon_vld1x3: NewOpc = AArch64ISD::NEON_LD1x3_UPD;
4120 case Intrinsic::aarch64_neon_vld1x4: NewOpc = AArch64ISD::NEON_LD1x4_UPD;
4122 case Intrinsic::aarch64_neon_vst1x2: NewOpc = AArch64ISD::NEON_ST1x2_UPD;
4123 NumVecs = 2; isLoad = false; break;
4124 case Intrinsic::aarch64_neon_vst1x3: NewOpc = AArch64ISD::NEON_ST1x3_UPD;
4125 NumVecs = 3; isLoad = false; break;
4126 case Intrinsic::aarch64_neon_vst1x4: NewOpc = AArch64ISD::NEON_ST1x4_UPD;
4127 NumVecs = 4; isLoad = false; break;
4128 case Intrinsic::arm_neon_vld2lane: NewOpc = AArch64ISD::NEON_LD2LN_UPD;
4129 NumVecs = 2; isLaneOp = true; break;
4130 case Intrinsic::arm_neon_vld3lane: NewOpc = AArch64ISD::NEON_LD3LN_UPD;
4131 NumVecs = 3; isLaneOp = true; break;
4132 case Intrinsic::arm_neon_vld4lane: NewOpc = AArch64ISD::NEON_LD4LN_UPD;
4133 NumVecs = 4; isLaneOp = true; break;
4134 case Intrinsic::arm_neon_vst2lane: NewOpc = AArch64ISD::NEON_ST2LN_UPD;
4135 NumVecs = 2; isLoad = false; isLaneOp = true; break;
4136 case Intrinsic::arm_neon_vst3lane: NewOpc = AArch64ISD::NEON_ST3LN_UPD;
4137 NumVecs = 3; isLoad = false; isLaneOp = true; break;
4138 case Intrinsic::arm_neon_vst4lane: NewOpc = AArch64ISD::NEON_ST4LN_UPD;
4139 NumVecs = 4; isLoad = false; isLaneOp = true; break;
4143 switch (N->getOpcode()) {
4144 default: llvm_unreachable("unexpected opcode for Neon base update");
4145 case AArch64ISD::NEON_LD2DUP: NewOpc = AArch64ISD::NEON_LD2DUP_UPD;
4147 case AArch64ISD::NEON_LD3DUP: NewOpc = AArch64ISD::NEON_LD3DUP_UPD;
4149 case AArch64ISD::NEON_LD4DUP: NewOpc = AArch64ISD::NEON_LD4DUP_UPD;
4154 // Find the size of memory referenced by the load/store.
4157 VecTy = N->getValueType(0);
4159 VecTy = N->getOperand(AddrOpIdx + 1).getValueType();
4160 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
4162 NumBytes /= VecTy.getVectorNumElements();
4164 // If the increment is a constant, it must match the memory ref size.
4165 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
4166 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
4167 uint32_t IncVal = CInc->getZExtValue();
4168 if (IncVal != NumBytes)
4170 Inc = DAG.getTargetConstant(IncVal, MVT::i32);
4173 // Create the new updating load/store node.
4175 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
4177 for (n = 0; n < NumResultVecs; ++n)
4179 Tys[n++] = MVT::i64;
4180 Tys[n] = MVT::Other;
4181 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs + 2);
4182 SmallVector<SDValue, 8> Ops;
4183 Ops.push_back(N->getOperand(0)); // incoming chain
4184 Ops.push_back(N->getOperand(AddrOpIdx));
4186 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
4187 Ops.push_back(N->getOperand(i));
4189 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
4190 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
4191 Ops.data(), Ops.size(),
4192 MemInt->getMemoryVT(),
4193 MemInt->getMemOperand());
4196 std::vector<SDValue> NewResults;
4197 for (unsigned i = 0; i < NumResultVecs; ++i) {
4198 NewResults.push_back(SDValue(UpdN.getNode(), i));
4200 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); // chain
4201 DCI.CombineTo(N, NewResults);
4202 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
4209 /// For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1)
4210 /// intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
4211 /// If so, combine them to a vldN-dup operation and return true.
4212 static SDValue CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
4213 SelectionDAG &DAG = DCI.DAG;
4214 EVT VT = N->getValueType(0);
4216 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
4217 SDNode *VLD = N->getOperand(0).getNode();
4218 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
4220 unsigned NumVecs = 0;
4221 unsigned NewOpc = 0;
4222 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
4223 if (IntNo == Intrinsic::arm_neon_vld2lane) {
4225 NewOpc = AArch64ISD::NEON_LD2DUP;
4226 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
4228 NewOpc = AArch64ISD::NEON_LD3DUP;
4229 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
4231 NewOpc = AArch64ISD::NEON_LD4DUP;
4236 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
4237 // numbers match the load.
4238 unsigned VLDLaneNo =
4239 cast<ConstantSDNode>(VLD->getOperand(NumVecs + 3))->getZExtValue();
4240 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4242 // Ignore uses of the chain result.
4243 if (UI.getUse().getResNo() == NumVecs)
4246 if (User->getOpcode() != AArch64ISD::NEON_VDUPLANE ||
4247 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
4251 // Create the vldN-dup node.
4254 for (n = 0; n < NumVecs; ++n)
4256 Tys[n] = MVT::Other;
4257 SDVTList SDTys = DAG.getVTList(Tys, NumVecs + 1);
4258 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
4259 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
4260 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, Ops, 2,
4261 VLDMemInt->getMemoryVT(),
4262 VLDMemInt->getMemOperand());
4265 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4267 unsigned ResNo = UI.getUse().getResNo();
4268 // Ignore uses of the chain result.
4269 if (ResNo == NumVecs)
4272 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
4275 // Now the vldN-lane intrinsic is dead except for its chain result.
4276 // Update uses of the chain.
4277 std::vector<SDValue> VLDDupResults;
4278 for (unsigned n = 0; n < NumVecs; ++n)
4279 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
4280 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
4281 DCI.CombineTo(VLD, VLDDupResults);
4283 return SDValue(N, 0);
4286 // vselect (v1i1 setcc) ->
4287 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
4288 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
4289 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
4291 static SDValue PerformVSelectCombine(SDNode *N, SelectionDAG &DAG) {
4292 SDValue N0 = N->getOperand(0);
4293 EVT CCVT = N0.getValueType();
4295 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
4296 CCVT.getVectorElementType() != MVT::i1)
4299 EVT ResVT = N->getValueType(0);
4300 EVT CmpVT = N0.getOperand(0).getValueType();
4301 // Only combine when the result type is of the same size as the compared
4303 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
4306 SDValue IfTrue = N->getOperand(1);
4307 SDValue IfFalse = N->getOperand(2);
4309 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
4310 N0.getOperand(0), N0.getOperand(1),
4311 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4312 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
4316 // sign_extend (extract_vector_elt (v1i1 setcc)) ->
4317 // extract_vector_elt (v1iXX setcc)
4318 // (XX is the size of the compared operand type)
4319 static SDValue PerformSignExtendCombine(SDNode *N, SelectionDAG &DAG) {
4320 SDValue N0 = N->getOperand(0);
4321 SDValue Vec = N0.getOperand(0);
4323 if (N0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4324 Vec.getOpcode() != ISD::SETCC)
4327 EVT ResVT = N->getValueType(0);
4328 EVT CmpVT = Vec.getOperand(0).getValueType();
4329 // Only optimize when the result type is of the same size as the element
4330 // type of the compared operand.
4331 if (ResVT.getSizeInBits() != CmpVT.getVectorElementType().getSizeInBits())
4334 SDValue Lane = N0.getOperand(1);
4336 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
4337 Vec.getOperand(0), Vec.getOperand(1),
4338 cast<CondCodeSDNode>(Vec.getOperand(2))->get());
4339 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ResVT,
4344 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
4345 DAGCombinerInfo &DCI) const {
4346 switch (N->getOpcode()) {
4348 case ISD::AND: return PerformANDCombine(N, DCI);
4349 case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
4353 return PerformShiftCombine(N, DCI, getSubtarget());
4354 case ISD::VSELECT: return PerformVSelectCombine(N, DCI.DAG);
4355 case ISD::SIGN_EXTEND: return PerformSignExtendCombine(N, DCI.DAG);
4356 case ISD::INTRINSIC_WO_CHAIN:
4357 return PerformIntrinsicCombine(N, DCI.DAG);
4358 case AArch64ISD::NEON_VDUPLANE:
4359 return CombineVLDDUP(N, DCI);
4360 case AArch64ISD::NEON_LD2DUP:
4361 case AArch64ISD::NEON_LD3DUP:
4362 case AArch64ISD::NEON_LD4DUP:
4363 return CombineBaseUpdate(N, DCI);
4364 case ISD::INTRINSIC_VOID:
4365 case ISD::INTRINSIC_W_CHAIN:
4366 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
4367 case Intrinsic::arm_neon_vld1:
4368 case Intrinsic::arm_neon_vld2:
4369 case Intrinsic::arm_neon_vld3:
4370 case Intrinsic::arm_neon_vld4:
4371 case Intrinsic::arm_neon_vst1:
4372 case Intrinsic::arm_neon_vst2:
4373 case Intrinsic::arm_neon_vst3:
4374 case Intrinsic::arm_neon_vst4:
4375 case Intrinsic::arm_neon_vld2lane:
4376 case Intrinsic::arm_neon_vld3lane:
4377 case Intrinsic::arm_neon_vld4lane:
4378 case Intrinsic::aarch64_neon_vld1x2:
4379 case Intrinsic::aarch64_neon_vld1x3:
4380 case Intrinsic::aarch64_neon_vld1x4:
4381 case Intrinsic::aarch64_neon_vst1x2:
4382 case Intrinsic::aarch64_neon_vst1x3:
4383 case Intrinsic::aarch64_neon_vst1x4:
4384 case Intrinsic::arm_neon_vst2lane:
4385 case Intrinsic::arm_neon_vst3lane:
4386 case Intrinsic::arm_neon_vst4lane:
4387 return CombineBaseUpdate(N, DCI);
4396 AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
4397 VT = VT.getScalarType();
4402 switch (VT.getSimpleVT().SimpleTy) {
4415 // Check whether a shuffle_vector could be presented as concat_vector.
4416 bool AArch64TargetLowering::isConcatVector(SDValue Op, SelectionDAG &DAG,
4417 SDValue V0, SDValue V1,
4419 SDValue &Res) const {
4421 EVT VT = Op.getValueType();
4422 if (VT.getSizeInBits() != 128)
4424 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4425 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4428 unsigned NumElts = VT.getVectorNumElements();
4429 bool isContactVector = true;
4430 bool splitV0 = false;
4431 if (V0.getValueType().getSizeInBits() == 128)
4434 for (int I = 0, E = NumElts / 2; I != E; I++) {
4436 isContactVector = false;
4441 if (isContactVector) {
4442 int offset = NumElts / 2;
4443 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4444 if (Mask[I] != I + splitV0 * offset) {
4445 isContactVector = false;
4451 if (isContactVector) {
4452 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4455 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4456 DAG.getConstant(0, MVT::i64));
4458 if (V1.getValueType().getSizeInBits() == 128) {
4459 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4460 DAG.getConstant(0, MVT::i64));
4462 Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4468 // Check whether a Build Vector could be presented as Shuffle Vector.
4469 // This Shuffle Vector maybe not legalized, so the length of its operand and
4470 // the length of result may not equal.
4471 bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
4472 SDValue &V0, SDValue &V1,
4475 EVT VT = Op.getValueType();
4476 unsigned NumElts = VT.getVectorNumElements();
4477 unsigned V0NumElts = 0;
4479 // Check if all elements are extracted from less than 3 vectors.
4480 for (unsigned i = 0; i < NumElts; ++i) {
4481 SDValue Elt = Op.getOperand(i);
4482 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4483 Elt.getOperand(0).getValueType().getVectorElementType() !=
4484 VT.getVectorElementType())
4487 if (V0.getNode() == 0) {
4488 V0 = Elt.getOperand(0);
4489 V0NumElts = V0.getValueType().getVectorNumElements();
4491 if (Elt.getOperand(0) == V0) {
4492 Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue());
4494 } else if (V1.getNode() == 0) {
4495 V1 = Elt.getOperand(0);
4497 if (Elt.getOperand(0) == V1) {
4498 unsigned Lane = cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue();
4499 Mask[i] = (Lane + V0NumElts);
4508 // LowerShiftRightParts - Lower SRL_PARTS and SRA_PARTS, which returns two
4509 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4510 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4511 SelectionDAG &DAG) const {
4512 assert(Op.getNumOperands() == 3 && "Not a quad-shift!");
4513 EVT VT = Op.getValueType();
4514 unsigned VTBits = VT.getSizeInBits();
4516 SDValue ShOpLo = Op.getOperand(0);
4517 SDValue ShOpHi = Op.getOperand(1);
4518 SDValue ShAmt = Op.getOperand(2);
4519 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4521 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4522 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4523 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4524 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4525 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4526 DAG.getConstant(VTBits, MVT::i64));
4527 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4528 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4529 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4530 SDValue Tmp3 = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4533 SDValue CmpOp = getSelectableIntSetCC(ExtraShAmt,
4534 DAG.getConstant(0, MVT::i64),
4538 SDValue Hi = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
4539 DAG.getConstant(0, Tmp3.getValueType()), Tmp3,
4541 SDValue Lo = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
4542 TrueVal, FalseVal, A64cc);
4544 SDValue Ops[2] = { Lo, Hi };
4545 return DAG.getMergeValues(Ops, 2, dl);
4548 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4549 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4550 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4551 SelectionDAG &DAG) const {
4552 assert(Op.getNumOperands() == 3 && "Not a quad-shift!");
4553 EVT VT = Op.getValueType();
4554 unsigned VTBits = VT.getSizeInBits();
4556 SDValue ShOpLo = Op.getOperand(0);
4557 SDValue ShOpHi = Op.getOperand(1);
4558 SDValue ShAmt = Op.getOperand(2);
4560 assert(Op.getOpcode() == ISD::SHL_PARTS);
4561 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4562 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4563 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4564 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4565 DAG.getConstant(VTBits, MVT::i64));
4566 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4567 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4568 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4569 SDValue Tmp4 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4572 SDValue CmpOp = getSelectableIntSetCC(ExtraShAmt,
4573 DAG.getConstant(0, MVT::i64),
4577 SDValue Lo = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
4578 DAG.getConstant(0, Tmp4.getValueType()), Tmp4,
4580 SDValue Hi = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
4581 Tmp3, FalseVal, A64cc);
4583 SDValue Ops[2] = { Lo, Hi };
4584 return DAG.getMergeValues(Ops, 2, dl);
4587 // If this is a case we can't handle, return null and let the default
4588 // expansion code take care of it.
4590 AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4591 const AArch64Subtarget *ST) const {
4593 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4595 EVT VT = Op.getValueType();
4597 APInt SplatBits, SplatUndef;
4598 unsigned SplatBitSize;
4601 unsigned UseNeonMov = VT.getSizeInBits() >= 64;
4603 // Note we favor lowering MOVI over MVNI.
4604 // This has implications on the definition of patterns in TableGen to select
4605 // BIC immediate instructions but not ORR immediate instructions.
4606 // If this lowering order is changed, TableGen patterns for BIC immediate and
4607 // ORR immediate instructions have to be updated.
4609 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4610 if (SplatBitSize <= 64) {
4611 // First attempt to use vector immediate-form MOVI
4614 unsigned OpCmode = 0;
4616 if (isNeonModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
4617 SplatBitSize, DAG, VT.is128BitVector(),
4618 Neon_Mov_Imm, NeonMovVT, Imm, OpCmode)) {
4619 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4620 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4622 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4623 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MOVIMM, DL, NeonMovVT,
4624 ImmVal, OpCmodeVal);
4625 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4629 // Then attempt to use vector immediate-form MVNI
4630 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4631 if (isNeonModifiedImm(NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
4632 DAG, VT.is128BitVector(), Neon_Mvn_Imm, NeonMovVT,
4634 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4635 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4636 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4637 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MVNIMM, DL, NeonMovVT,
4638 ImmVal, OpCmodeVal);
4639 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4643 // Attempt to use vector immediate-form FMOV
4644 if (((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) ||
4645 (VT == MVT::v2f64 && SplatBitSize == 64)) {
4647 SplatBitSize == 32 ? APFloat::IEEEsingle : APFloat::IEEEdouble,
4650 if (A64Imms::isFPImm(RealVal, ImmVal)) {
4651 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4652 return DAG.getNode(AArch64ISD::NEON_FMOVIMM, DL, VT, Val);
4658 unsigned NumElts = VT.getVectorNumElements();
4659 bool isOnlyLowElement = true;
4660 bool usesOnlyOneValue = true;
4661 bool hasDominantValue = false;
4662 bool isConstant = true;
4664 // Map of the number of times a particular SDValue appears in the
4666 DenseMap<SDValue, unsigned> ValueCounts;
4668 for (unsigned i = 0; i < NumElts; ++i) {
4669 SDValue V = Op.getOperand(i);
4670 if (V.getOpcode() == ISD::UNDEF)
4673 isOnlyLowElement = false;
4674 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4677 ValueCounts.insert(std::make_pair(V, 0));
4678 unsigned &Count = ValueCounts[V];
4680 // Is this value dominant? (takes up more than half of the lanes)
4681 if (++Count > (NumElts / 2)) {
4682 hasDominantValue = true;
4686 if (ValueCounts.size() != 1)
4687 usesOnlyOneValue = false;
4688 if (!Value.getNode() && ValueCounts.size() > 0)
4689 Value = ValueCounts.begin()->first;
4691 if (ValueCounts.size() == 0)
4692 return DAG.getUNDEF(VT);
4694 if (isOnlyLowElement)
4695 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4697 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4698 if (hasDominantValue && EltSize <= 64) {
4699 // Use VDUP for non-constant splats.
4703 // If we are DUPing a value that comes directly from a vector, we could
4704 // just use DUPLANE. We can only do this if the lane being extracted
4705 // is at a constant index, as the DUP from lane instructions only have
4706 // constant-index forms.
4708 // If there is a TRUNCATE between EXTRACT_VECTOR_ELT and DUP, we can
4709 // remove TRUNCATE for DUPLANE by apdating the source vector to
4710 // appropriate vector type and lane index.
4712 // FIXME: for now we have v1i8, v1i16, v1i32 legal vector types, if they
4713 // are not legal any more, no need to check the type size in bits should
4714 // be large than 64.
4716 if (Value->getOpcode() == ISD::TRUNCATE)
4717 V = Value->getOperand(0);
4718 if (V->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4719 isa<ConstantSDNode>(V->getOperand(1)) &&
4720 V->getOperand(0).getValueType().getSizeInBits() >= 64) {
4722 // If the element size of source vector is larger than DUPLANE
4723 // element size, we can do transformation by,
4724 // 1) bitcasting source register to smaller element vector
4725 // 2) mutiplying the lane index by SrcEltSize/ResEltSize
4726 // For example, we can lower
4727 // "v8i16 vdup_lane(v4i32, 1)"
4729 // "v8i16 vdup_lane(v8i16 bitcast(v4i32), 2)".
4730 SDValue SrcVec = V->getOperand(0);
4731 unsigned SrcEltSize =
4732 SrcVec.getValueType().getVectorElementType().getSizeInBits();
4733 unsigned ResEltSize = VT.getVectorElementType().getSizeInBits();
4734 if (SrcEltSize > ResEltSize) {
4735 assert((SrcEltSize % ResEltSize == 0) && "Invalid element size");
4737 unsigned SrcSize = SrcVec.getValueType().getSizeInBits();
4738 unsigned ResSize = VT.getSizeInBits();
4740 if (SrcSize > ResSize) {
4741 assert((SrcSize % ResSize == 0) && "Invalid vector size");
4743 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4744 SrcSize / ResEltSize);
4745 BitCast = DAG.getNode(ISD::BITCAST, DL, CastVT, SrcVec);
4747 assert((SrcSize == ResSize) && "Invalid vector size of source vec");
4748 BitCast = DAG.getNode(ISD::BITCAST, DL, VT, SrcVec);
4751 unsigned LaneIdx = V->getConstantOperandVal(1);
4753 DAG.getConstant((SrcEltSize / ResEltSize) * LaneIdx, MVT::i64);
4754 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, BitCast, Lane);
4756 assert((SrcEltSize == ResEltSize) &&
4757 "Invalid element size of source vec");
4758 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, V->getOperand(0),
4762 N = DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4764 if (!usesOnlyOneValue) {
4765 // The dominant value was splatted as 'N', but we now have to insert
4766 // all differing elements.
4767 for (unsigned I = 0; I < NumElts; ++I) {
4768 if (Op.getOperand(I) == Value)
4770 SmallVector<SDValue, 3> Ops;
4772 Ops.push_back(Op.getOperand(I));
4773 Ops.push_back(DAG.getConstant(I, MVT::i64));
4774 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
4779 if (usesOnlyOneValue && isConstant) {
4780 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4783 // If all elements are constants and the case above didn't get hit, fall back
4784 // to the default expansion, which will generate a load from the constant
4789 // Try to lower this in lowering ShuffleVector way.
4792 if (isKnownShuffleVector(Op, DAG, V0, V1, Mask)) {
4793 unsigned V0NumElts = V0.getValueType().getVectorNumElements();
4794 if (!V1.getNode() && V0NumElts == NumElts * 2) {
4795 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
4796 DAG.getConstant(NumElts, MVT::i64));
4797 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
4798 DAG.getConstant(0, MVT::i64));
4799 V0NumElts = V0.getValueType().getVectorNumElements();
4802 if (V1.getNode() && NumElts == V0NumElts &&
4803 V0NumElts == V1.getValueType().getVectorNumElements()) {
4804 SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
4805 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
4808 return LowerVECTOR_SHUFFLE(Shuffle, DAG);
4811 if (isConcatVector(Op, DAG, V0, V1, Mask, Res))
4816 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4817 // know the default expansion would otherwise fall back on something even
4818 // worse. For a vector with one or two non-undef values, that's
4819 // scalar_to_vector for the elements followed by a shuffle (provided the
4820 // shuffle is valid for the target) and materialization element by element
4821 // on the stack followed by a load for everything else.
4822 if (!isConstant && !usesOnlyOneValue) {
4823 SDValue Vec = DAG.getUNDEF(VT);
4824 for (unsigned i = 0 ; i < NumElts; ++i) {
4825 SDValue V = Op.getOperand(i);
4826 if (V.getOpcode() == ISD::UNDEF)
4828 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
4829 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, LaneIdx);
4836 /// isREVMask - Check if a vector shuffle corresponds to a REV
4837 /// instruction with the specified blocksize. (The order of the elements
4838 /// within each block of the vector is reversed.)
4839 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4840 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4841 "Only possible block sizes for REV are: 16, 32, 64");
4843 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4847 unsigned NumElts = VT.getVectorNumElements();
4848 unsigned BlockElts = M[0] + 1;
4849 // If the first shuffle index is UNDEF, be optimistic.
4851 BlockElts = BlockSize / EltSz;
4853 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4856 for (unsigned i = 0; i < NumElts; ++i) {
4858 continue; // ignore UNDEF indices
4859 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4866 // isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
4868 static unsigned isPermuteMask(ArrayRef<int> M, EVT VT, bool isV2undef) {
4869 unsigned NumElts = VT.getVectorNumElements();
4873 bool ismatch = true;
4876 for (unsigned i = 0; i < NumElts; ++i) {
4877 unsigned answer = i * 2;
4878 if (isV2undef && answer >= NumElts)
4880 if (M[i] != -1 && (unsigned)M[i] != answer) {
4886 return AArch64ISD::NEON_UZP1;
4890 for (unsigned i = 0; i < NumElts; ++i) {
4891 unsigned answer = i * 2 + 1;
4892 if (isV2undef && answer >= NumElts)
4894 if (M[i] != -1 && (unsigned)M[i] != answer) {
4900 return AArch64ISD::NEON_UZP2;
4904 for (unsigned i = 0; i < NumElts; ++i) {
4905 unsigned answer = i / 2 + NumElts * (i % 2);
4906 if (isV2undef && answer >= NumElts)
4908 if (M[i] != -1 && (unsigned)M[i] != answer) {
4914 return AArch64ISD::NEON_ZIP1;
4918 for (unsigned i = 0; i < NumElts; ++i) {
4919 unsigned answer = (NumElts + i) / 2 + NumElts * (i % 2);
4920 if (isV2undef && answer >= NumElts)
4922 if (M[i] != -1 && (unsigned)M[i] != answer) {
4928 return AArch64ISD::NEON_ZIP2;
4932 for (unsigned i = 0; i < NumElts; ++i) {
4933 unsigned answer = i + (NumElts - 1) * (i % 2);
4934 if (isV2undef && answer >= NumElts)
4936 if (M[i] != -1 && (unsigned)M[i] != answer) {
4942 return AArch64ISD::NEON_TRN1;
4946 for (unsigned i = 0; i < NumElts; ++i) {
4947 unsigned answer = 1 + i + (NumElts - 1) * (i % 2);
4948 if (isV2undef && answer >= NumElts)
4950 if (M[i] != -1 && (unsigned)M[i] != answer) {
4956 return AArch64ISD::NEON_TRN2;
4962 AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4963 SelectionDAG &DAG) const {
4964 SDValue V1 = Op.getOperand(0);
4965 SDValue V2 = Op.getOperand(1);
4967 EVT VT = Op.getValueType();
4968 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4970 // Convert shuffles that are directly supported on NEON to target-specific
4971 // DAG nodes, instead of keeping them as shuffles and matching them again
4972 // during code selection. This is more efficient and avoids the possibility
4973 // of inconsistencies between legalization and selection.
4974 ArrayRef<int> ShuffleMask = SVN->getMask();
4976 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4980 if (isREVMask(ShuffleMask, VT, 64))
4981 return DAG.getNode(AArch64ISD::NEON_REV64, dl, VT, V1);
4982 if (isREVMask(ShuffleMask, VT, 32))
4983 return DAG.getNode(AArch64ISD::NEON_REV32, dl, VT, V1);
4984 if (isREVMask(ShuffleMask, VT, 16))
4985 return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1);
4988 if (V2.getOpcode() == ISD::UNDEF)
4989 ISDNo = isPermuteMask(ShuffleMask, VT, true);
4991 ISDNo = isPermuteMask(ShuffleMask, VT, false);
4994 if (V2.getOpcode() == ISD::UNDEF)
4995 return DAG.getNode(ISDNo, dl, VT, V1, V1);
4997 return DAG.getNode(ISDNo, dl, VT, V1, V2);
5001 if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
5004 // If the element of shuffle mask are all the same constant, we can
5005 // transform it into either NEON_VDUP or NEON_VDUPLANE
5006 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5007 int Lane = SVN->getSplatIndex();
5008 // If this is undef splat, generate it via "just" vdup, if possible.
5009 if (Lane == -1) Lane = 0;
5011 // Test if V1 is a SCALAR_TO_VECTOR.
5012 if (V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5013 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(0));
5015 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR.
5016 if (V1.getOpcode() == ISD::BUILD_VECTOR) {
5017 bool IsScalarToVector = true;
5018 for (unsigned i = 0, e = V1.getNumOperands(); i != e; ++i)
5019 if (V1.getOperand(i).getOpcode() != ISD::UNDEF &&
5020 i != (unsigned)Lane) {
5021 IsScalarToVector = false;
5024 if (IsScalarToVector)
5025 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT,
5026 V1.getOperand(Lane));
5029 // Test if V1 is a EXTRACT_SUBVECTOR.
5030 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5031 int ExtLane = cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5032 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
5033 DAG.getConstant(Lane + ExtLane, MVT::i64));
5035 // Test if V1 is a CONCAT_VECTORS.
5036 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
5037 V1.getOperand(1).getOpcode() == ISD::UNDEF) {
5038 SDValue Op0 = V1.getOperand(0);
5039 assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
5040 "Invalid vector lane access");
5041 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
5042 DAG.getConstant(Lane, MVT::i64));
5045 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,
5046 DAG.getConstant(Lane, MVT::i64));
5049 int Length = ShuffleMask.size();
5050 int V1EltNum = V1.getValueType().getVectorNumElements();
5052 // If the number of v1 elements is the same as the number of shuffle mask
5053 // element and the shuffle masks are sequential values, we can transform
5054 // it into NEON_VEXTRACT.
5055 if (V1EltNum == Length) {
5056 // Check if the shuffle mask is sequential.
5058 while (ShuffleMask[SkipUndef] == -1) {
5061 int CurMask = ShuffleMask[SkipUndef];
5062 if (CurMask >= SkipUndef) {
5063 bool IsSequential = true;
5064 for (int I = SkipUndef; I < Length; ++I) {
5065 if (ShuffleMask[I] != -1 && ShuffleMask[I] != CurMask) {
5066 IsSequential = false;
5072 assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect");
5073 unsigned VecSize = EltSize * V1EltNum;
5074 unsigned Index = (EltSize / 8) * (ShuffleMask[SkipUndef] - SkipUndef);
5075 if (VecSize == 64 || VecSize == 128)
5076 return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2,
5077 DAG.getConstant(Index, MVT::i64));
5082 // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert
5083 // by element from V2 to V1 .
5084 // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a
5085 // better choice to be inserted than V1 as less insert needed, so we count
5086 // element to be inserted for both V1 and V2, and select less one as insert
5089 // Collect elements need to be inserted and their index.
5090 SmallVector<int, 8> NV1Elt;
5091 SmallVector<int, 8> N1Index;
5092 SmallVector<int, 8> NV2Elt;
5093 SmallVector<int, 8> N2Index;
5094 for (int I = 0; I != Length; ++I) {
5095 if (ShuffleMask[I] != I) {
5096 NV1Elt.push_back(ShuffleMask[I]);
5097 N1Index.push_back(I);
5100 for (int I = 0; I != Length; ++I) {
5101 if (ShuffleMask[I] != (I + V1EltNum)) {
5102 NV2Elt.push_back(ShuffleMask[I]);
5103 N2Index.push_back(I);
5107 // Decide which to be inserted. If all lanes mismatch, neither V1 nor V2
5108 // will be inserted.
5110 SmallVector<int, 8> InsMasks = NV1Elt;
5111 SmallVector<int, 8> InsIndex = N1Index;
5112 if ((int)NV1Elt.size() != Length || (int)NV2Elt.size() != Length) {
5113 if (NV1Elt.size() > NV2Elt.size()) {
5119 InsV = DAG.getNode(ISD::UNDEF, dl, VT);
5122 for (int I = 0, E = InsMasks.size(); I != E; ++I) {
5124 int Mask = InsMasks[I];
5125 if (Mask >= V1EltNum) {
5129 // Any value type smaller than i32 is illegal in AArch64, and this lower
5130 // function is called after legalize pass, so we need to legalize
5133 if (VT.getVectorElementType().isFloatingPoint())
5134 EltVT = (EltSize == 64) ? MVT::f64 : MVT::f32;
5136 EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32;
5139 ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
5140 DAG.getConstant(Mask, MVT::i64));
5141 InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV,
5142 DAG.getConstant(InsIndex[I], MVT::i64));
5148 AArch64TargetLowering::ConstraintType
5149 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
5150 if (Constraint.size() == 1) {
5151 switch (Constraint[0]) {
5153 case 'w': // An FP/SIMD vector register
5154 return C_RegisterClass;
5155 case 'I': // Constant that can be used with an ADD instruction
5156 case 'J': // Constant that can be used with a SUB instruction
5157 case 'K': // Constant that can be used with a 32-bit logical instruction
5158 case 'L': // Constant that can be used with a 64-bit logical instruction
5159 case 'M': // Constant that can be used as a 32-bit MOV immediate
5160 case 'N': // Constant that can be used as a 64-bit MOV immediate
5161 case 'Y': // Floating point constant zero
5162 case 'Z': // Integer constant zero
5164 case 'Q': // A memory reference with base register and no offset
5166 case 'S': // A symbolic address
5171 // FIXME: Ump, Utf, Usa, Ush
5172 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
5173 // whatever they may be
5174 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
5175 // Usa: An absolute symbolic address
5176 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
5177 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
5178 && Constraint != "Ush" && "Unimplemented constraints");
5180 return TargetLowering::getConstraintType(Constraint);
5183 TargetLowering::ConstraintWeight
5184 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
5185 const char *Constraint) const {
5187 llvm_unreachable("Constraint weight unimplemented");
5191 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5192 std::string &Constraint,
5193 std::vector<SDValue> &Ops,
5194 SelectionDAG &DAG) const {
5195 SDValue Result(0, 0);
5197 // Only length 1 constraints are C_Other.
5198 if (Constraint.size() != 1) return;
5200 // Only C_Other constraints get lowered like this. That means constants for us
5201 // so return early if there's no hope the constraint can be lowered.
5203 switch(Constraint[0]) {
5205 case 'I': case 'J': case 'K': case 'L':
5206 case 'M': case 'N': case 'Z': {
5207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5211 uint64_t CVal = C->getZExtValue();
5214 switch (Constraint[0]) {
5216 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
5217 // is a peculiarly useless SUB constraint.
5218 llvm_unreachable("Unimplemented C_Other constraint");
5224 if (A64Imms::isLogicalImm(32, CVal, Bits))
5228 if (A64Imms::isLogicalImm(64, CVal, Bits))
5237 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5241 // An absolute symbolic address or label reference.
5242 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
5243 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
5244 GA->getValueType(0));
5245 } else if (const BlockAddressSDNode *BA
5246 = dyn_cast<BlockAddressSDNode>(Op)) {
5247 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
5248 BA->getValueType(0));
5249 } else if (const ExternalSymbolSDNode *ES
5250 = dyn_cast<ExternalSymbolSDNode>(Op)) {
5251 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
5252 ES->getValueType(0));
5258 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
5259 if (CFP->isExactlyValue(0.0)) {
5260 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
5267 if (Result.getNode()) {
5268 Ops.push_back(Result);
5272 // It's an unknown constraint for us. Let generic code have a go.
5273 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5276 std::pair<unsigned, const TargetRegisterClass*>
5277 AArch64TargetLowering::getRegForInlineAsmConstraint(
5278 const std::string &Constraint,
5280 if (Constraint.size() == 1) {
5281 switch (Constraint[0]) {
5283 if (VT.getSizeInBits() <= 32)
5284 return std::make_pair(0U, &AArch64::GPR32RegClass);
5285 else if (VT == MVT::i64)
5286 return std::make_pair(0U, &AArch64::GPR64RegClass);
5290 return std::make_pair(0U, &AArch64::FPR16RegClass);
5291 else if (VT == MVT::f32)
5292 return std::make_pair(0U, &AArch64::FPR32RegClass);
5293 else if (VT.getSizeInBits() == 64)
5294 return std::make_pair(0U, &AArch64::FPR64RegClass);
5295 else if (VT.getSizeInBits() == 128)
5296 return std::make_pair(0U, &AArch64::FPR128RegClass);
5301 // Use the default implementation in TargetLowering to convert the register
5302 // constraint into a member of a register class.
5303 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5306 /// Represent NEON load and store intrinsics as MemIntrinsicNodes.
5307 /// The associated MachineMemOperands record the alignment specified
5308 /// in the intrinsic calls.
5309 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5311 unsigned Intrinsic) const {
5312 switch (Intrinsic) {
5313 case Intrinsic::arm_neon_vld1:
5314 case Intrinsic::arm_neon_vld2:
5315 case Intrinsic::arm_neon_vld3:
5316 case Intrinsic::arm_neon_vld4:
5317 case Intrinsic::aarch64_neon_vld1x2:
5318 case Intrinsic::aarch64_neon_vld1x3:
5319 case Intrinsic::aarch64_neon_vld1x4:
5320 case Intrinsic::arm_neon_vld2lane:
5321 case Intrinsic::arm_neon_vld3lane:
5322 case Intrinsic::arm_neon_vld4lane: {
5323 Info.opc = ISD::INTRINSIC_W_CHAIN;
5324 // Conservatively set memVT to the entire set of vectors loaded.
5325 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5326 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5327 Info.ptrVal = I.getArgOperand(0);
5329 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5330 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5331 Info.vol = false; // volatile loads with NEON intrinsics not supported
5332 Info.readMem = true;
5333 Info.writeMem = false;
5336 case Intrinsic::arm_neon_vst1:
5337 case Intrinsic::arm_neon_vst2:
5338 case Intrinsic::arm_neon_vst3:
5339 case Intrinsic::arm_neon_vst4:
5340 case Intrinsic::aarch64_neon_vst1x2:
5341 case Intrinsic::aarch64_neon_vst1x3:
5342 case Intrinsic::aarch64_neon_vst1x4:
5343 case Intrinsic::arm_neon_vst2lane:
5344 case Intrinsic::arm_neon_vst3lane:
5345 case Intrinsic::arm_neon_vst4lane: {
5346 Info.opc = ISD::INTRINSIC_VOID;
5347 // Conservatively set memVT to the entire set of vectors stored.
5348 unsigned NumElts = 0;
5349 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5350 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5351 if (!ArgTy->isVectorTy())
5353 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5355 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5356 Info.ptrVal = I.getArgOperand(0);
5358 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5359 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5360 Info.vol = false; // volatile stores with NEON intrinsics not supported
5361 Info.readMem = false;
5362 Info.writeMem = true;
5372 // Truncations from 64-bit GPR to 32-bit GPR is free.
5373 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
5374 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
5376 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5377 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5378 if (NumBits1 <= NumBits2)
5383 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
5384 if (!VT1.isInteger() || !VT2.isInteger())
5386 unsigned NumBits1 = VT1.getSizeInBits();
5387 unsigned NumBits2 = VT2.getSizeInBits();
5388 if (NumBits1 <= NumBits2)
5393 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
5395 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
5396 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
5398 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5399 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5400 if (NumBits1 == 32 && NumBits2 == 64)
5405 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
5406 if (!VT1.isInteger() || !VT2.isInteger())
5408 unsigned NumBits1 = VT1.getSizeInBits();
5409 unsigned NumBits2 = VT2.getSizeInBits();
5410 if (NumBits1 == 32 && NumBits2 == 64)
5415 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
5416 EVT VT1 = Val.getValueType();
5417 if (isZExtFree(VT1, VT2)) {
5421 if (Val.getOpcode() != ISD::LOAD)
5424 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
5425 return (VT1.isSimple() && VT1.isInteger() && VT2.isSimple() &&
5426 VT2.isInteger() && VT1.getSizeInBits() <= 32);
5429 // isLegalAddressingMode - Return true if the addressing mode represented
5430 /// by AM is legal for this target, for a load/store of the specified type.
5431 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5433 // AArch64 has five basic addressing modes:
5435 // reg + 9-bit signed offset
5436 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
5438 // reg + SIZE_IN_BYTES * reg
5440 // No global is ever allowed as a base.
5444 // No reg+reg+imm addressing.
5445 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
5448 // check reg + imm case:
5449 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
5450 uint64_t NumBytes = 0;
5451 if (Ty->isSized()) {
5452 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
5453 NumBytes = NumBits / 8;
5454 if (!isPowerOf2_64(NumBits))
5459 int64_t Offset = AM.BaseOffs;
5461 // 9-bit signed offset
5462 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
5465 // 12-bit unsigned offset
5466 unsigned shift = Log2_64(NumBytes);
5467 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
5468 // Must be a multiple of NumBytes (NumBytes is a power of 2)
5469 (Offset >> shift) << shift == Offset)
5473 if (!AM.Scale || AM.Scale == 1 ||
5474 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
5479 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
5481 // Scaling factors are not free at all.
5482 // Operands | Rt Latency
5483 // -------------------------------------------
5485 // -------------------------------------------
5486 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
5487 // Rt, [Xn, Wm, <extend> #imm] |
5488 if (isLegalAddressingMode(AM, Ty))
5489 // Scale represents reg2 * scale, thus account for 1 if
5490 // it is not equal to 0 or 1.
5491 return AM.Scale != 0 && AM.Scale != 1;