1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
32 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
33 assert (TM.getSubtarget<AArch64Subtarget>().isTargetELF() &&
34 "unknown subtarget type");
35 return new AArch64ElfTargetObjectFile();
38 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
39 : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
41 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
43 // SIMD compares set the entire lane's bits to 1
44 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
46 // Scalar register <-> type mapping
47 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
48 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
50 if (Subtarget->hasFPARMv8()) {
51 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
52 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
53 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
54 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
57 if (Subtarget->hasNEON()) {
59 addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass);
60 addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass);
61 addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass);
62 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
63 addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
64 addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
65 addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
66 addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass);
67 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
68 addRegisterClass(MVT::v2f32, &AArch64::FPR64RegClass);
69 addRegisterClass(MVT::v16i8, &AArch64::FPR128RegClass);
70 addRegisterClass(MVT::v8i16, &AArch64::FPR128RegClass);
71 addRegisterClass(MVT::v4i32, &AArch64::FPR128RegClass);
72 addRegisterClass(MVT::v2i64, &AArch64::FPR128RegClass);
73 addRegisterClass(MVT::v4f32, &AArch64::FPR128RegClass);
74 addRegisterClass(MVT::v2f64, &AArch64::FPR128RegClass);
77 computeRegisterProperties();
79 // We combine OR nodes for bitfield and NEON BSL operations.
80 setTargetDAGCombine(ISD::OR);
82 setTargetDAGCombine(ISD::AND);
83 setTargetDAGCombine(ISD::SRA);
84 setTargetDAGCombine(ISD::SRL);
85 setTargetDAGCombine(ISD::SHL);
87 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
88 setTargetDAGCombine(ISD::INTRINSIC_VOID);
89 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
91 // AArch64 does not have i1 loads, or much of anything for i1 really.
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
96 setStackPointerRegisterToSaveRestore(AArch64::XSP);
97 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
98 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
99 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
101 // We'll lower globals to wrappers for selection.
102 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
103 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
105 // A64 instructions have the comparison predicate attached to the user of the
106 // result, but having a separate comparison is valuable for matching.
107 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
108 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
109 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
110 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
112 setOperationAction(ISD::SELECT, MVT::i32, Custom);
113 setOperationAction(ISD::SELECT, MVT::i64, Custom);
114 setOperationAction(ISD::SELECT, MVT::f32, Custom);
115 setOperationAction(ISD::SELECT, MVT::f64, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
122 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
129 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
131 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
133 setOperationAction(ISD::VASTART, MVT::Other, Custom);
134 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
135 setOperationAction(ISD::VAEND, MVT::Other, Expand);
136 setOperationAction(ISD::VAARG, MVT::Other, Expand);
138 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
139 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
141 setOperationAction(ISD::ROTL, MVT::i32, Expand);
142 setOperationAction(ISD::ROTL, MVT::i64, Expand);
144 setOperationAction(ISD::UREM, MVT::i32, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
146 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
147 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
149 setOperationAction(ISD::SREM, MVT::i32, Expand);
150 setOperationAction(ISD::SREM, MVT::i64, Expand);
151 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
154 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
155 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
157 // Legal floating-point operations.
158 setOperationAction(ISD::FABS, MVT::f32, Legal);
159 setOperationAction(ISD::FABS, MVT::f64, Legal);
161 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
164 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
165 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
167 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
168 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
170 setOperationAction(ISD::FNEG, MVT::f32, Legal);
171 setOperationAction(ISD::FNEG, MVT::f64, Legal);
173 setOperationAction(ISD::FRINT, MVT::f32, Legal);
174 setOperationAction(ISD::FRINT, MVT::f64, Legal);
176 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
177 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
179 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
180 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
182 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
183 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
184 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
186 // Illegal floating-point operations.
187 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
190 setOperationAction(ISD::FCOS, MVT::f32, Expand);
191 setOperationAction(ISD::FCOS, MVT::f64, Expand);
193 setOperationAction(ISD::FEXP, MVT::f32, Expand);
194 setOperationAction(ISD::FEXP, MVT::f64, Expand);
196 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
197 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
199 setOperationAction(ISD::FLOG, MVT::f32, Expand);
200 setOperationAction(ISD::FLOG, MVT::f64, Expand);
202 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
203 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
205 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
206 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
208 setOperationAction(ISD::FPOW, MVT::f32, Expand);
209 setOperationAction(ISD::FPOW, MVT::f64, Expand);
211 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
212 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
214 setOperationAction(ISD::FREM, MVT::f32, Expand);
215 setOperationAction(ISD::FREM, MVT::f64, Expand);
217 setOperationAction(ISD::FSIN, MVT::f32, Expand);
218 setOperationAction(ISD::FSIN, MVT::f64, Expand);
220 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
221 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
223 // Virtually no operation on f128 is legal, but LLVM can't expand them when
224 // there's a valid register class, so we need custom operations in most cases.
225 setOperationAction(ISD::FABS, MVT::f128, Expand);
226 setOperationAction(ISD::FADD, MVT::f128, Custom);
227 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
228 setOperationAction(ISD::FCOS, MVT::f128, Expand);
229 setOperationAction(ISD::FDIV, MVT::f128, Custom);
230 setOperationAction(ISD::FMA, MVT::f128, Expand);
231 setOperationAction(ISD::FMUL, MVT::f128, Custom);
232 setOperationAction(ISD::FNEG, MVT::f128, Expand);
233 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
234 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
235 setOperationAction(ISD::FPOW, MVT::f128, Expand);
236 setOperationAction(ISD::FREM, MVT::f128, Expand);
237 setOperationAction(ISD::FRINT, MVT::f128, Expand);
238 setOperationAction(ISD::FSIN, MVT::f128, Expand);
239 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
240 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
241 setOperationAction(ISD::FSUB, MVT::f128, Custom);
242 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
243 setOperationAction(ISD::SETCC, MVT::f128, Custom);
244 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
245 setOperationAction(ISD::SELECT, MVT::f128, Expand);
246 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
247 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
249 // Lowering for many of the conversions is actually specified by the non-f128
250 // type. The LowerXXX function will be trivial when f128 isn't involved.
251 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
252 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
253 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
254 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
255 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
256 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
258 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
259 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
260 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
261 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
262 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
263 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
264 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
266 // This prevents LLVM trying to compress double constants into a floating
267 // constant-pool entry and trying to load from there. It's of doubtful benefit
268 // for A64: we'd need LDR followed by FCVT, I believe.
269 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
270 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
271 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
273 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
274 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
275 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
276 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
277 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
278 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
280 setExceptionPointerRegister(AArch64::X0);
281 setExceptionSelectorRegister(AArch64::X1);
283 if (Subtarget->hasNEON()) {
284 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i8, Custom);
285 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
286 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
287 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i16, Custom);
288 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
289 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
290 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i32, Custom);
291 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
292 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
293 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
294 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
295 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
296 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
297 setOperationAction(ISD::BUILD_VECTOR, MVT::v1f64, Custom);
298 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
300 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
301 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
302 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
303 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
304 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
305 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
306 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
307 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
308 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom);
309 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom);
311 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
313 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal);
314 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
315 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
316 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
317 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
318 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
319 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
320 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal);
321 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal);
323 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
324 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
325 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
326 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
327 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
328 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
329 setOperationAction(ISD::SETCC, MVT::v1i64, Custom);
330 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
331 setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
332 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
333 setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
334 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
336 setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
337 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
338 setOperationAction(ISD::FFLOOR, MVT::v1f64, Legal);
339 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
341 setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
342 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
343 setOperationAction(ISD::FCEIL, MVT::v1f64, Legal);
344 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
346 setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
347 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
348 setOperationAction(ISD::FTRUNC, MVT::v1f64, Legal);
349 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
351 setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
352 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
353 setOperationAction(ISD::FRINT, MVT::v1f64, Legal);
354 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
356 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal);
357 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
358 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Legal);
359 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
361 setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
362 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
363 setOperationAction(ISD::FROUND, MVT::v1f64, Legal);
364 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
366 // Vector ExtLoad and TruncStore are expanded.
367 for (unsigned I = MVT::FIRST_VECTOR_VALUETYPE;
368 I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
369 MVT VT = (MVT::SimpleValueType) I;
370 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
371 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
372 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
373 for (unsigned II = MVT::FIRST_VECTOR_VALUETYPE;
374 II <= MVT::LAST_VECTOR_VALUETYPE; ++II) {
375 MVT VT1 = (MVT::SimpleValueType) II;
376 // A TruncStore has two vector types of the same number of elements
377 // and different element sizes.
378 if (VT.getVectorNumElements() == VT1.getVectorNumElements() &&
379 VT.getVectorElementType().getSizeInBits()
380 > VT1.getVectorElementType().getSizeInBits())
381 setTruncStoreAction(VT, VT1, Expand);
385 // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
386 // FIXME: For a v2i64 multiply, we copy VPR to GPR and do 2 i64 multiplies,
387 // and then copy back to VPR. This solution may be optimized by Following 3
388 // NEON instructions:
389 // pmull v2.1q, v0.1d, v1.1d
390 // pmull2 v3.1q, v0.2d, v1.2d
391 // ins v2.d[1], v3.d[0]
392 // As currently we can't verify the correctness of such assumption, we can
393 // do such optimization in the future.
394 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
395 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
399 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
400 // It's reasonably important that this value matches the "natural" legal
401 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
402 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
403 if (!VT.isVector()) return MVT::i32;
404 return VT.changeVectorElementTypeToInteger();
407 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
410 static const unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
411 AArch64::LDXR_word, AArch64::LDXR_dword};
412 static const unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
413 AArch64::LDAXR_word, AArch64::LDAXR_dword};
414 static const unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
415 AArch64::STXR_word, AArch64::STXR_dword};
416 static const unsigned StoreRels[] = {AArch64::STLXR_byte,AArch64::STLXR_hword,
417 AArch64::STLXR_word, AArch64::STLXR_dword};
419 const unsigned *LoadOps, *StoreOps;
420 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
425 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
426 StoreOps = StoreRels;
428 StoreOps = StoreBares;
430 assert(isPowerOf2_32(Size) && Size <= 8 &&
431 "unsupported size for atomic binary op!");
433 LdrOpc = LoadOps[Log2_32(Size)];
434 StrOpc = StoreOps[Log2_32(Size)];
437 // FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really
438 // have value type mapped, and they are both being defined as MVT::untyped.
439 // Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost
440 // would fail to figure out the register pressure correctly.
441 std::pair<const TargetRegisterClass*, uint8_t>
442 AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
443 const TargetRegisterClass *RRC = 0;
445 switch (VT.SimpleTy) {
447 return TargetLowering::findRepresentativeClass(VT);
449 RRC = &AArch64::QPairRegClass;
453 RRC = &AArch64::QQuadRegClass;
457 return std::make_pair(RRC, Cost);
461 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
463 unsigned BinOpcode) const {
464 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
467 const BasicBlock *LLVM_BB = BB->getBasicBlock();
468 MachineFunction *MF = BB->getParent();
469 MachineFunction::iterator It = BB;
472 unsigned dest = MI->getOperand(0).getReg();
473 unsigned ptr = MI->getOperand(1).getReg();
474 unsigned incr = MI->getOperand(2).getReg();
475 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
476 DebugLoc dl = MI->getDebugLoc();
478 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
480 unsigned ldrOpc, strOpc;
481 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
483 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
484 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
485 MF->insert(It, loopMBB);
486 MF->insert(It, exitMBB);
488 // Transfer the remainder of BB and its successor edges to exitMBB.
489 exitMBB->splice(exitMBB->begin(), BB,
490 llvm::next(MachineBasicBlock::iterator(MI)),
492 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
494 const TargetRegisterClass *TRC
495 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
496 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
500 // fallthrough --> loopMBB
501 BB->addSuccessor(loopMBB);
505 // <binop> scratch, dest, incr
506 // stxr stxr_status, scratch, ptr
507 // cbnz stxr_status, loopMBB
508 // fallthrough --> exitMBB
510 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
512 // All arithmetic operations we'll be creating are designed to take an extra
513 // shift or extend operand, which we can conveniently set to zero.
515 // Operand order needs to go the other way for NAND.
516 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
517 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
518 .addReg(incr).addReg(dest).addImm(0);
520 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
521 .addReg(dest).addReg(incr).addImm(0);
524 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
525 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
526 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
528 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
529 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
530 .addReg(stxr_status).addMBB(loopMBB);
532 BB->addSuccessor(loopMBB);
533 BB->addSuccessor(exitMBB);
539 MI->eraseFromParent(); // The instruction is gone now.
545 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
546 MachineBasicBlock *BB,
549 A64CC::CondCodes Cond) const {
550 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
552 const BasicBlock *LLVM_BB = BB->getBasicBlock();
553 MachineFunction *MF = BB->getParent();
554 MachineFunction::iterator It = BB;
557 unsigned dest = MI->getOperand(0).getReg();
558 unsigned ptr = MI->getOperand(1).getReg();
559 unsigned incr = MI->getOperand(2).getReg();
560 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
562 unsigned oldval = dest;
563 DebugLoc dl = MI->getDebugLoc();
565 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
566 const TargetRegisterClass *TRC, *TRCsp;
568 TRC = &AArch64::GPR64RegClass;
569 TRCsp = &AArch64::GPR64xspRegClass;
571 TRC = &AArch64::GPR32RegClass;
572 TRCsp = &AArch64::GPR32wspRegClass;
575 unsigned ldrOpc, strOpc;
576 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
578 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
579 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
580 MF->insert(It, loopMBB);
581 MF->insert(It, exitMBB);
583 // Transfer the remainder of BB and its successor edges to exitMBB.
584 exitMBB->splice(exitMBB->begin(), BB,
585 llvm::next(MachineBasicBlock::iterator(MI)),
587 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
589 unsigned scratch = MRI.createVirtualRegister(TRC);
590 MRI.constrainRegClass(scratch, TRCsp);
594 // fallthrough --> loopMBB
595 BB->addSuccessor(loopMBB);
599 // cmp incr, dest (, sign extend if necessary)
600 // csel scratch, dest, incr, cond
601 // stxr stxr_status, scratch, ptr
602 // cbnz stxr_status, loopMBB
603 // fallthrough --> exitMBB
605 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
607 // Build compare and cmov instructions.
608 MRI.constrainRegClass(incr, TRCsp);
609 BuildMI(BB, dl, TII->get(CmpOp))
610 .addReg(incr).addReg(oldval).addImm(0);
612 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
614 .addReg(oldval).addReg(incr).addImm(Cond);
616 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
617 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
619 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
620 .addReg(scratch).addReg(ptr);
621 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
622 .addReg(stxr_status).addMBB(loopMBB);
624 BB->addSuccessor(loopMBB);
625 BB->addSuccessor(exitMBB);
631 MI->eraseFromParent(); // The instruction is gone now.
637 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
638 MachineBasicBlock *BB,
639 unsigned Size) const {
640 unsigned dest = MI->getOperand(0).getReg();
641 unsigned ptr = MI->getOperand(1).getReg();
642 unsigned oldval = MI->getOperand(2).getReg();
643 unsigned newval = MI->getOperand(3).getReg();
644 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
645 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
646 DebugLoc dl = MI->getDebugLoc();
648 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
649 const TargetRegisterClass *TRCsp;
650 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
652 unsigned ldrOpc, strOpc;
653 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
655 MachineFunction *MF = BB->getParent();
656 const BasicBlock *LLVM_BB = BB->getBasicBlock();
657 MachineFunction::iterator It = BB;
658 ++It; // insert the new blocks after the current block
660 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
661 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
662 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
663 MF->insert(It, loop1MBB);
664 MF->insert(It, loop2MBB);
665 MF->insert(It, exitMBB);
667 // Transfer the remainder of BB and its successor edges to exitMBB.
668 exitMBB->splice(exitMBB->begin(), BB,
669 llvm::next(MachineBasicBlock::iterator(MI)),
671 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
675 // fallthrough --> loop1MBB
676 BB->addSuccessor(loop1MBB);
683 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
685 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
686 MRI.constrainRegClass(dest, TRCsp);
687 BuildMI(BB, dl, TII->get(CmpOp))
688 .addReg(dest).addReg(oldval).addImm(0);
689 BuildMI(BB, dl, TII->get(AArch64::Bcc))
690 .addImm(A64CC::NE).addMBB(exitMBB);
691 BB->addSuccessor(loop2MBB);
692 BB->addSuccessor(exitMBB);
695 // strex stxr_status, newval, [ptr]
696 // cbnz stxr_status, loop1MBB
698 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
699 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
701 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
702 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
703 .addReg(stxr_status).addMBB(loop1MBB);
704 BB->addSuccessor(loop1MBB);
705 BB->addSuccessor(exitMBB);
711 MI->eraseFromParent(); // The instruction is gone now.
717 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
718 MachineBasicBlock *MBB) const {
719 // We materialise the F128CSEL pseudo-instruction using conditional branches
720 // and loads, giving an instruciton sequence like:
729 // Using virtual registers would probably not be beneficial since COPY
730 // instructions are expensive for f128 (there's no actual instruction to
733 // An alternative would be to do an integer-CSEL on some address. E.g.:
738 // csel x0, x0, x1, ne
741 // It's unclear which approach is actually optimal.
742 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
743 MachineFunction *MF = MBB->getParent();
744 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
745 DebugLoc DL = MI->getDebugLoc();
746 MachineFunction::iterator It = MBB;
749 unsigned DestReg = MI->getOperand(0).getReg();
750 unsigned IfTrueReg = MI->getOperand(1).getReg();
751 unsigned IfFalseReg = MI->getOperand(2).getReg();
752 unsigned CondCode = MI->getOperand(3).getImm();
753 bool NZCVKilled = MI->getOperand(4).isKill();
755 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
756 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
757 MF->insert(It, TrueBB);
758 MF->insert(It, EndBB);
760 // Transfer rest of current basic-block to EndBB
761 EndBB->splice(EndBB->begin(), MBB,
762 llvm::next(MachineBasicBlock::iterator(MI)),
764 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
766 // We need somewhere to store the f128 value needed.
767 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
769 // [... start of incoming MBB ...]
770 // str qIFFALSE, [sp]
773 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
775 .addFrameIndex(ScratchFI)
777 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
780 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
782 MBB->addSuccessor(TrueBB);
783 MBB->addSuccessor(EndBB);
786 // NZCV is live-through TrueBB.
787 TrueBB->addLiveIn(AArch64::NZCV);
788 EndBB->addLiveIn(AArch64::NZCV);
793 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
795 .addFrameIndex(ScratchFI)
798 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
800 TrueBB->addSuccessor(EndBB);
804 // [... rest of incoming MBB ...]
805 MachineInstr *StartOfEnd = EndBB->begin();
806 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
807 .addFrameIndex(ScratchFI)
810 MI->eraseFromParent();
815 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
816 MachineBasicBlock *MBB) const {
817 switch (MI->getOpcode()) {
818 default: llvm_unreachable("Unhandled instruction with custom inserter");
819 case AArch64::F128CSEL:
820 return EmitF128CSEL(MI, MBB);
821 case AArch64::ATOMIC_LOAD_ADD_I8:
822 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
823 case AArch64::ATOMIC_LOAD_ADD_I16:
824 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
825 case AArch64::ATOMIC_LOAD_ADD_I32:
826 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
827 case AArch64::ATOMIC_LOAD_ADD_I64:
828 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
830 case AArch64::ATOMIC_LOAD_SUB_I8:
831 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
832 case AArch64::ATOMIC_LOAD_SUB_I16:
833 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
834 case AArch64::ATOMIC_LOAD_SUB_I32:
835 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
836 case AArch64::ATOMIC_LOAD_SUB_I64:
837 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
839 case AArch64::ATOMIC_LOAD_AND_I8:
840 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
841 case AArch64::ATOMIC_LOAD_AND_I16:
842 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
843 case AArch64::ATOMIC_LOAD_AND_I32:
844 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
845 case AArch64::ATOMIC_LOAD_AND_I64:
846 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
848 case AArch64::ATOMIC_LOAD_OR_I8:
849 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
850 case AArch64::ATOMIC_LOAD_OR_I16:
851 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
852 case AArch64::ATOMIC_LOAD_OR_I32:
853 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
854 case AArch64::ATOMIC_LOAD_OR_I64:
855 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
857 case AArch64::ATOMIC_LOAD_XOR_I8:
858 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
859 case AArch64::ATOMIC_LOAD_XOR_I16:
860 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
861 case AArch64::ATOMIC_LOAD_XOR_I32:
862 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
863 case AArch64::ATOMIC_LOAD_XOR_I64:
864 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
866 case AArch64::ATOMIC_LOAD_NAND_I8:
867 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
868 case AArch64::ATOMIC_LOAD_NAND_I16:
869 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
870 case AArch64::ATOMIC_LOAD_NAND_I32:
871 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
872 case AArch64::ATOMIC_LOAD_NAND_I64:
873 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
875 case AArch64::ATOMIC_LOAD_MIN_I8:
876 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
877 case AArch64::ATOMIC_LOAD_MIN_I16:
878 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
879 case AArch64::ATOMIC_LOAD_MIN_I32:
880 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
881 case AArch64::ATOMIC_LOAD_MIN_I64:
882 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
884 case AArch64::ATOMIC_LOAD_MAX_I8:
885 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
886 case AArch64::ATOMIC_LOAD_MAX_I16:
887 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
888 case AArch64::ATOMIC_LOAD_MAX_I32:
889 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
890 case AArch64::ATOMIC_LOAD_MAX_I64:
891 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
893 case AArch64::ATOMIC_LOAD_UMIN_I8:
894 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
895 case AArch64::ATOMIC_LOAD_UMIN_I16:
896 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
897 case AArch64::ATOMIC_LOAD_UMIN_I32:
898 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
899 case AArch64::ATOMIC_LOAD_UMIN_I64:
900 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
902 case AArch64::ATOMIC_LOAD_UMAX_I8:
903 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
904 case AArch64::ATOMIC_LOAD_UMAX_I16:
905 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
906 case AArch64::ATOMIC_LOAD_UMAX_I32:
907 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
908 case AArch64::ATOMIC_LOAD_UMAX_I64:
909 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
911 case AArch64::ATOMIC_SWAP_I8:
912 return emitAtomicBinary(MI, MBB, 1, 0);
913 case AArch64::ATOMIC_SWAP_I16:
914 return emitAtomicBinary(MI, MBB, 2, 0);
915 case AArch64::ATOMIC_SWAP_I32:
916 return emitAtomicBinary(MI, MBB, 4, 0);
917 case AArch64::ATOMIC_SWAP_I64:
918 return emitAtomicBinary(MI, MBB, 8, 0);
920 case AArch64::ATOMIC_CMP_SWAP_I8:
921 return emitAtomicCmpSwap(MI, MBB, 1);
922 case AArch64::ATOMIC_CMP_SWAP_I16:
923 return emitAtomicCmpSwap(MI, MBB, 2);
924 case AArch64::ATOMIC_CMP_SWAP_I32:
925 return emitAtomicCmpSwap(MI, MBB, 4);
926 case AArch64::ATOMIC_CMP_SWAP_I64:
927 return emitAtomicCmpSwap(MI, MBB, 8);
932 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
934 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
935 case AArch64ISD::Call: return "AArch64ISD::Call";
936 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
937 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
938 case AArch64ISD::BFI: return "AArch64ISD::BFI";
939 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
940 case AArch64ISD::Ret: return "AArch64ISD::Ret";
941 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
942 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
943 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
944 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
945 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
946 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
947 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
948 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
950 case AArch64ISD::NEON_MOVIMM:
951 return "AArch64ISD::NEON_MOVIMM";
952 case AArch64ISD::NEON_MVNIMM:
953 return "AArch64ISD::NEON_MVNIMM";
954 case AArch64ISD::NEON_FMOVIMM:
955 return "AArch64ISD::NEON_FMOVIMM";
956 case AArch64ISD::NEON_CMP:
957 return "AArch64ISD::NEON_CMP";
958 case AArch64ISD::NEON_CMPZ:
959 return "AArch64ISD::NEON_CMPZ";
960 case AArch64ISD::NEON_TST:
961 return "AArch64ISD::NEON_TST";
962 case AArch64ISD::NEON_QSHLs:
963 return "AArch64ISD::NEON_QSHLs";
964 case AArch64ISD::NEON_QSHLu:
965 return "AArch64ISD::NEON_QSHLu";
966 case AArch64ISD::NEON_VDUP:
967 return "AArch64ISD::NEON_VDUP";
968 case AArch64ISD::NEON_VDUPLANE:
969 return "AArch64ISD::NEON_VDUPLANE";
970 case AArch64ISD::NEON_REV16:
971 return "AArch64ISD::NEON_REV16";
972 case AArch64ISD::NEON_REV32:
973 return "AArch64ISD::NEON_REV32";
974 case AArch64ISD::NEON_REV64:
975 return "AArch64ISD::NEON_REV64";
976 case AArch64ISD::NEON_UZP1:
977 return "AArch64ISD::NEON_UZP1";
978 case AArch64ISD::NEON_UZP2:
979 return "AArch64ISD::NEON_UZP2";
980 case AArch64ISD::NEON_ZIP1:
981 return "AArch64ISD::NEON_ZIP1";
982 case AArch64ISD::NEON_ZIP2:
983 return "AArch64ISD::NEON_ZIP2";
984 case AArch64ISD::NEON_TRN1:
985 return "AArch64ISD::NEON_TRN1";
986 case AArch64ISD::NEON_TRN2:
987 return "AArch64ISD::NEON_TRN2";
988 case AArch64ISD::NEON_LD1_UPD:
989 return "AArch64ISD::NEON_LD1_UPD";
990 case AArch64ISD::NEON_LD2_UPD:
991 return "AArch64ISD::NEON_LD2_UPD";
992 case AArch64ISD::NEON_LD3_UPD:
993 return "AArch64ISD::NEON_LD3_UPD";
994 case AArch64ISD::NEON_LD4_UPD:
995 return "AArch64ISD::NEON_LD4_UPD";
996 case AArch64ISD::NEON_ST1_UPD:
997 return "AArch64ISD::NEON_ST1_UPD";
998 case AArch64ISD::NEON_ST2_UPD:
999 return "AArch64ISD::NEON_ST2_UPD";
1000 case AArch64ISD::NEON_ST3_UPD:
1001 return "AArch64ISD::NEON_ST3_UPD";
1002 case AArch64ISD::NEON_ST4_UPD:
1003 return "AArch64ISD::NEON_ST4_UPD";
1004 case AArch64ISD::NEON_LD1x2_UPD:
1005 return "AArch64ISD::NEON_LD1x2_UPD";
1006 case AArch64ISD::NEON_LD1x3_UPD:
1007 return "AArch64ISD::NEON_LD1x3_UPD";
1008 case AArch64ISD::NEON_LD1x4_UPD:
1009 return "AArch64ISD::NEON_LD1x4_UPD";
1010 case AArch64ISD::NEON_ST1x2_UPD:
1011 return "AArch64ISD::NEON_ST1x2_UPD";
1012 case AArch64ISD::NEON_ST1x3_UPD:
1013 return "AArch64ISD::NEON_ST1x3_UPD";
1014 case AArch64ISD::NEON_ST1x4_UPD:
1015 return "AArch64ISD::NEON_ST1x4_UPD";
1016 case AArch64ISD::NEON_LD2DUP:
1017 return "AArch64ISD::NEON_LD2DUP";
1018 case AArch64ISD::NEON_LD3DUP:
1019 return "AArch64ISD::NEON_LD3DUP";
1020 case AArch64ISD::NEON_LD4DUP:
1021 return "AArch64ISD::NEON_LD4DUP";
1022 case AArch64ISD::NEON_LD2DUP_UPD:
1023 return "AArch64ISD::NEON_LD2DUP_UPD";
1024 case AArch64ISD::NEON_LD3DUP_UPD:
1025 return "AArch64ISD::NEON_LD3DUP_UPD";
1026 case AArch64ISD::NEON_LD4DUP_UPD:
1027 return "AArch64ISD::NEON_LD4DUP_UPD";
1028 case AArch64ISD::NEON_LD2LN_UPD:
1029 return "AArch64ISD::NEON_LD2LN_UPD";
1030 case AArch64ISD::NEON_LD3LN_UPD:
1031 return "AArch64ISD::NEON_LD3LN_UPD";
1032 case AArch64ISD::NEON_LD4LN_UPD:
1033 return "AArch64ISD::NEON_LD4LN_UPD";
1034 case AArch64ISD::NEON_ST2LN_UPD:
1035 return "AArch64ISD::NEON_ST2LN_UPD";
1036 case AArch64ISD::NEON_ST3LN_UPD:
1037 return "AArch64ISD::NEON_ST3LN_UPD";
1038 case AArch64ISD::NEON_ST4LN_UPD:
1039 return "AArch64ISD::NEON_ST4LN_UPD";
1040 case AArch64ISD::NEON_VEXTRACT:
1041 return "AArch64ISD::NEON_VEXTRACT";
1047 static const uint16_t AArch64FPRArgRegs[] = {
1048 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1049 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1051 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
1053 static const uint16_t AArch64ArgRegs[] = {
1054 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
1055 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1057 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
1059 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
1060 CCValAssign::LocInfo LocInfo,
1061 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1062 // Mark all remaining general purpose registers as allocated. We don't
1063 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
1064 // i64 will go in registers (C.11).
1065 for (unsigned i = 0; i < NumArgRegs; ++i)
1066 State.AllocateReg(AArch64ArgRegs[i]);
1071 #include "AArch64GenCallingConv.inc"
1073 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1076 default: llvm_unreachable("Unsupported calling convention");
1077 case CallingConv::Fast:
1078 case CallingConv::C:
1084 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
1085 SDLoc DL, SDValue &Chain) const {
1086 MachineFunction &MF = DAG.getMachineFunction();
1087 MachineFrameInfo *MFI = MF.getFrameInfo();
1088 AArch64MachineFunctionInfo *FuncInfo
1089 = MF.getInfo<AArch64MachineFunctionInfo>();
1091 SmallVector<SDValue, 8> MemOps;
1093 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
1095 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
1098 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
1100 if (GPRSaveSize != 0) {
1101 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1103 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1105 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
1106 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
1107 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1108 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1109 MachinePointerInfo::getStack(i * 8),
1111 MemOps.push_back(Store);
1112 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1113 DAG.getConstant(8, getPointerTy()));
1117 if (getSubtarget()->hasFPARMv8()) {
1118 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1120 // According to the AArch64 Procedure Call Standard, section B.1/B.3, we
1121 // can omit a register save area if we know we'll never use registers of
1123 if (FPRSaveSize != 0) {
1124 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1126 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1128 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1129 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
1130 &AArch64::FPR128RegClass);
1131 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1132 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1133 MachinePointerInfo::getStack(i * 16),
1135 MemOps.push_back(Store);
1136 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1137 DAG.getConstant(16, getPointerTy()));
1140 FuncInfo->setVariadicFPRIdx(FPRIdx);
1141 FuncInfo->setVariadicFPRSize(FPRSaveSize);
1144 int StackIdx = MFI->CreateFixedObject(8, CCInfo.getNextStackOffset(), true);
1146 FuncInfo->setVariadicStackIdx(StackIdx);
1147 FuncInfo->setVariadicGPRIdx(GPRIdx);
1148 FuncInfo->setVariadicGPRSize(GPRSaveSize);
1150 if (!MemOps.empty()) {
1151 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
1158 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
1159 CallingConv::ID CallConv, bool isVarArg,
1160 const SmallVectorImpl<ISD::InputArg> &Ins,
1161 SDLoc dl, SelectionDAG &DAG,
1162 SmallVectorImpl<SDValue> &InVals) const {
1163 MachineFunction &MF = DAG.getMachineFunction();
1164 AArch64MachineFunctionInfo *FuncInfo
1165 = MF.getInfo<AArch64MachineFunctionInfo>();
1166 MachineFrameInfo *MFI = MF.getFrameInfo();
1167 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1169 SmallVector<CCValAssign, 16> ArgLocs;
1170 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1171 getTargetMachine(), ArgLocs, *DAG.getContext());
1172 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1174 SmallVector<SDValue, 16> ArgValues;
1177 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1178 CCValAssign &VA = ArgLocs[i];
1179 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1181 if (Flags.isByVal()) {
1182 // Byval is used for small structs and HFAs in the PCS, but the system
1183 // should work in a non-compliant manner for larger structs.
1184 EVT PtrTy = getPointerTy();
1185 int Size = Flags.getByValSize();
1186 unsigned NumRegs = (Size + 7) / 8;
1188 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
1189 VA.getLocMemOffset(),
1191 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1192 InVals.push_back(FrameIdxN);
1195 } else if (VA.isRegLoc()) {
1196 MVT RegVT = VA.getLocVT();
1197 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1198 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1200 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1201 } else { // VA.isRegLoc()
1202 assert(VA.isMemLoc());
1204 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
1205 VA.getLocMemOffset(), true);
1207 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1208 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1209 MachinePointerInfo::getFixedStack(FI),
1210 false, false, false, 0);
1215 switch (VA.getLocInfo()) {
1216 default: llvm_unreachable("Unknown loc info!");
1217 case CCValAssign::Full: break;
1218 case CCValAssign::BCvt:
1219 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
1221 case CCValAssign::SExt:
1222 case CCValAssign::ZExt:
1223 case CCValAssign::AExt: {
1224 unsigned DestSize = VA.getValVT().getSizeInBits();
1225 unsigned DestSubReg;
1228 case 8: DestSubReg = AArch64::sub_8; break;
1229 case 16: DestSubReg = AArch64::sub_16; break;
1230 case 32: DestSubReg = AArch64::sub_32; break;
1231 case 64: DestSubReg = AArch64::sub_64; break;
1232 default: llvm_unreachable("Unexpected argument promotion");
1235 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
1236 VA.getValVT(), ArgValue,
1237 DAG.getTargetConstant(DestSubReg, MVT::i32)),
1243 InVals.push_back(ArgValue);
1247 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
1249 unsigned StackArgSize = CCInfo.getNextStackOffset();
1250 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1251 // This is a non-standard ABI so by fiat I say we're allowed to make full
1252 // use of the stack area to be popped, which must be aligned to 16 bytes in
1254 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1256 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1257 // a multiple of 16.
1258 FuncInfo->setArgumentStackToRestore(StackArgSize);
1260 // This realignment carries over to the available bytes below. Our own
1261 // callers will guarantee the space is free by giving an aligned value to
1264 // Even if we're not expected to free up the space, it's useful to know how
1265 // much is there while considering tail calls (because we can reuse it).
1266 FuncInfo->setBytesInStackArgArea(StackArgSize);
1272 AArch64TargetLowering::LowerReturn(SDValue Chain,
1273 CallingConv::ID CallConv, bool isVarArg,
1274 const SmallVectorImpl<ISD::OutputArg> &Outs,
1275 const SmallVectorImpl<SDValue> &OutVals,
1276 SDLoc dl, SelectionDAG &DAG) const {
1277 // CCValAssign - represent the assignment of the return value to a location.
1278 SmallVector<CCValAssign, 16> RVLocs;
1280 // CCState - Info about the registers and stack slots.
1281 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1282 getTargetMachine(), RVLocs, *DAG.getContext());
1284 // Analyze outgoing return values.
1285 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1288 SmallVector<SDValue, 4> RetOps(1, Chain);
1290 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1291 // PCS: "If the type, T, of the result of a function is such that
1292 // void func(T arg) would require that arg be passed as a value in a
1293 // register (or set of registers) according to the rules in 5.4, then the
1294 // result is returned in the same registers as would be used for such an
1297 // Otherwise, the caller shall reserve a block of memory of sufficient
1298 // size and alignment to hold the result. The address of the memory block
1299 // shall be passed as an additional argument to the function in x8."
1301 // This is implemented in two places. The register-return values are dealt
1302 // with here, more complex returns are passed as an sret parameter, which
1303 // means we don't have to worry about it during actual return.
1304 CCValAssign &VA = RVLocs[i];
1305 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1308 SDValue Arg = OutVals[i];
1310 // There's no convenient note in the ABI about this as there is for normal
1311 // arguments, but it says return values are passed in the same registers as
1312 // an argument would be. I believe that includes the comments about
1313 // unspecified higher bits, putting the burden of widening on the *caller*
1314 // for return values.
1315 switch (VA.getLocInfo()) {
1316 default: llvm_unreachable("Unknown loc info");
1317 case CCValAssign::Full: break;
1318 case CCValAssign::SExt:
1319 case CCValAssign::ZExt:
1320 case CCValAssign::AExt:
1321 // Floating-point values should only be extended when they're going into
1322 // memory, which can't happen here so an integer extend is acceptable.
1323 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1325 case CCValAssign::BCvt:
1326 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1330 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1331 Flag = Chain.getValue(1);
1332 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1335 RetOps[0] = Chain; // Update chain.
1337 // Add the flag if we have it.
1339 RetOps.push_back(Flag);
1341 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1342 &RetOps[0], RetOps.size());
1345 unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
1346 // This is a new backend. For anything more precise than this a FE should
1347 // set an explicit alignment.
1352 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1353 SmallVectorImpl<SDValue> &InVals) const {
1354 SelectionDAG &DAG = CLI.DAG;
1356 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1357 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1358 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1359 SDValue Chain = CLI.Chain;
1360 SDValue Callee = CLI.Callee;
1361 bool &IsTailCall = CLI.IsTailCall;
1362 CallingConv::ID CallConv = CLI.CallConv;
1363 bool IsVarArg = CLI.IsVarArg;
1365 MachineFunction &MF = DAG.getMachineFunction();
1366 AArch64MachineFunctionInfo *FuncInfo
1367 = MF.getInfo<AArch64MachineFunctionInfo>();
1368 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1369 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1370 bool IsSibCall = false;
1373 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1374 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1375 Outs, OutVals, Ins, DAG);
1377 // A sibling call is one where we're under the usual C ABI and not planning
1378 // to change that but can still do a tail call:
1379 if (!TailCallOpt && IsTailCall)
1383 SmallVector<CCValAssign, 16> ArgLocs;
1384 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1385 getTargetMachine(), ArgLocs, *DAG.getContext());
1386 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1388 // On AArch64 (and all other architectures I'm aware of) the most this has to
1389 // do is adjust the stack pointer.
1390 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1392 // Since we're not changing the ABI to make this a tail call, the memory
1393 // operands are already available in the caller's incoming argument space.
1397 // FPDiff is the byte offset of the call's argument area from the callee's.
1398 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1399 // by this amount for a tail call. In a sibling call it must be 0 because the
1400 // caller will deallocate the entire stack and the callee still expects its
1401 // arguments to begin at SP+0. Completely unused for non-tail calls.
1404 if (IsTailCall && !IsSibCall) {
1405 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1407 // FPDiff will be negative if this tail call requires more space than we
1408 // would automatically have in our incoming argument space. Positive if we
1409 // can actually shrink the stack.
1410 FPDiff = NumReusableBytes - NumBytes;
1412 // The stack pointer must be 16-byte aligned at all times it's used for a
1413 // memory operation, which in practice means at *all* times and in
1414 // particular across call boundaries. Therefore our own arguments started at
1415 // a 16-byte aligned SP and the delta applied for the tail call should
1416 // satisfy the same constraint.
1417 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1421 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1424 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1427 SmallVector<SDValue, 8> MemOpChains;
1428 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1431 CCValAssign &VA = ArgLocs[i];
1432 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1433 SDValue Arg = OutVals[i];
1435 // Callee does the actual widening, so all extensions just use an implicit
1436 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1437 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1438 // alternative works on integer types too.
1439 switch (VA.getLocInfo()) {
1440 default: llvm_unreachable("Unknown loc info!");
1441 case CCValAssign::Full: break;
1442 case CCValAssign::SExt:
1443 case CCValAssign::ZExt:
1444 case CCValAssign::AExt: {
1445 unsigned SrcSize = VA.getValVT().getSizeInBits();
1449 case 8: SrcSubReg = AArch64::sub_8; break;
1450 case 16: SrcSubReg = AArch64::sub_16; break;
1451 case 32: SrcSubReg = AArch64::sub_32; break;
1452 case 64: SrcSubReg = AArch64::sub_64; break;
1453 default: llvm_unreachable("Unexpected argument promotion");
1456 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1458 DAG.getUNDEF(VA.getLocVT()),
1460 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1465 case CCValAssign::BCvt:
1466 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1470 if (VA.isRegLoc()) {
1471 // A normal register (sub-) argument. For now we just note it down because
1472 // we want to copy things into registers as late as possible to avoid
1473 // register-pressure (and possibly worse).
1474 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1478 assert(VA.isMemLoc() && "unexpected argument location");
1481 MachinePointerInfo DstInfo;
1483 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1484 VA.getLocVT().getSizeInBits();
1485 OpSize = (OpSize + 7) / 8;
1486 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1487 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1489 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1490 DstInfo = MachinePointerInfo::getFixedStack(FI);
1492 // Make sure any stack arguments overlapping with where we're storing are
1493 // loaded before this eventual operation. Otherwise they'll be clobbered.
1494 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1496 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1498 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1499 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1502 if (Flags.isByVal()) {
1503 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1504 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1505 Flags.getByValAlign(),
1506 /*isVolatile = */ false,
1507 /*alwaysInline = */ false,
1508 DstInfo, MachinePointerInfo(0));
1509 MemOpChains.push_back(Cpy);
1511 // Normal stack argument, put it where it's needed.
1512 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1514 MemOpChains.push_back(Store);
1518 // The loads and stores generated above shouldn't clash with each
1519 // other. Combining them with this TokenFactor notes that fact for the rest of
1521 if (!MemOpChains.empty())
1522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1523 &MemOpChains[0], MemOpChains.size());
1525 // Most of the rest of the instructions need to be glued together; we don't
1526 // want assignments to actual registers used by a call to be rearranged by a
1527 // well-meaning scheduler.
1530 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1531 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1532 RegsToPass[i].second, InFlag);
1533 InFlag = Chain.getValue(1);
1536 // The linker is responsible for inserting veneers when necessary to put a
1537 // function call destination in range, so we don't need to bother with a
1539 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1540 const GlobalValue *GV = G->getGlobal();
1541 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1542 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1543 const char *Sym = S->getSymbol();
1544 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1547 // We don't usually want to end the call-sequence here because we would tidy
1548 // the frame up *after* the call, however in the ABI-changing tail-call case
1549 // we've carefully laid out the parameters so that when sp is reset they'll be
1550 // in the correct location.
1551 if (IsTailCall && !IsSibCall) {
1552 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1553 DAG.getIntPtrConstant(0, true), InFlag, dl);
1554 InFlag = Chain.getValue(1);
1557 // We produce the following DAG scheme for the actual call instruction:
1558 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1560 // Most arguments aren't going to be used and just keep the values live as
1561 // far as LLVM is concerned. It's expected to be selected as simply "bl
1562 // callee" (for a direct, non-tail call).
1563 std::vector<SDValue> Ops;
1564 Ops.push_back(Chain);
1565 Ops.push_back(Callee);
1568 // Each tail call may have to adjust the stack by a different amount, so
1569 // this information must travel along with the operation for eventual
1570 // consumption by emitEpilogue.
1571 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1574 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1575 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1576 RegsToPass[i].second.getValueType()));
1579 // Add a register mask operand representing the call-preserved registers. This
1580 // is used later in codegen to constrain register-allocation.
1581 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1582 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1583 assert(Mask && "Missing call preserved mask for calling convention");
1584 Ops.push_back(DAG.getRegisterMask(Mask));
1586 // If we needed glue, put it in as the last argument.
1587 if (InFlag.getNode())
1588 Ops.push_back(InFlag);
1590 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1593 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1596 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1597 InFlag = Chain.getValue(1);
1599 // Now we can reclaim the stack, just as well do it before working out where
1600 // our return value is.
1602 uint64_t CalleePopBytes
1603 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1605 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1606 DAG.getIntPtrConstant(CalleePopBytes, true),
1608 InFlag = Chain.getValue(1);
1611 return LowerCallResult(Chain, InFlag, CallConv,
1612 IsVarArg, Ins, dl, DAG, InVals);
1616 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1617 CallingConv::ID CallConv, bool IsVarArg,
1618 const SmallVectorImpl<ISD::InputArg> &Ins,
1619 SDLoc dl, SelectionDAG &DAG,
1620 SmallVectorImpl<SDValue> &InVals) const {
1621 // Assign locations to each value returned by this call.
1622 SmallVector<CCValAssign, 16> RVLocs;
1623 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1624 getTargetMachine(), RVLocs, *DAG.getContext());
1625 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1627 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1628 CCValAssign VA = RVLocs[i];
1630 // Return values that are too big to fit into registers should use an sret
1631 // pointer, so this can be a lot simpler than the main argument code.
1632 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1634 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1636 Chain = Val.getValue(1);
1637 InFlag = Val.getValue(2);
1639 switch (VA.getLocInfo()) {
1640 default: llvm_unreachable("Unknown loc info!");
1641 case CCValAssign::Full: break;
1642 case CCValAssign::BCvt:
1643 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1645 case CCValAssign::ZExt:
1646 case CCValAssign::SExt:
1647 case CCValAssign::AExt:
1648 // Floating-point arguments only get extended/truncated if they're going
1649 // in memory, so using the integer operation is acceptable here.
1650 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1654 InVals.push_back(Val);
1661 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1662 CallingConv::ID CalleeCC,
1664 bool IsCalleeStructRet,
1665 bool IsCallerStructRet,
1666 const SmallVectorImpl<ISD::OutputArg> &Outs,
1667 const SmallVectorImpl<SDValue> &OutVals,
1668 const SmallVectorImpl<ISD::InputArg> &Ins,
1669 SelectionDAG& DAG) const {
1671 // For CallingConv::C this function knows whether the ABI needs
1672 // changing. That's not true for other conventions so they will have to opt in
1674 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1677 const MachineFunction &MF = DAG.getMachineFunction();
1678 const Function *CallerF = MF.getFunction();
1679 CallingConv::ID CallerCC = CallerF->getCallingConv();
1680 bool CCMatch = CallerCC == CalleeCC;
1682 // Byval parameters hand the function a pointer directly into the stack area
1683 // we want to reuse during a tail call. Working around this *is* possible (see
1684 // X86) but less efficient and uglier in LowerCall.
1685 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1686 e = CallerF->arg_end(); i != e; ++i)
1687 if (i->hasByValAttr())
1690 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1691 if (IsTailCallConvention(CalleeCC) && CCMatch)
1696 // Now we search for cases where we can use a tail call without changing the
1697 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1700 // I want anyone implementing a new calling convention to think long and hard
1701 // about this assert.
1702 assert((!IsVarArg || CalleeCC == CallingConv::C)
1703 && "Unexpected variadic calling convention");
1705 if (IsVarArg && !Outs.empty()) {
1706 // At least two cases here: if caller is fastcc then we can't have any
1707 // memory arguments (we'd be expected to clean up the stack afterwards). If
1708 // caller is C then we could potentially use its argument area.
1710 // FIXME: for now we take the most conservative of these in both cases:
1711 // disallow all variadic memory operands.
1712 SmallVector<CCValAssign, 16> ArgLocs;
1713 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1714 getTargetMachine(), ArgLocs, *DAG.getContext());
1716 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1717 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1718 if (!ArgLocs[i].isRegLoc())
1722 // If the calling conventions do not match, then we'd better make sure the
1723 // results are returned in the same way as what the caller expects.
1725 SmallVector<CCValAssign, 16> RVLocs1;
1726 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1727 getTargetMachine(), RVLocs1, *DAG.getContext());
1728 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1730 SmallVector<CCValAssign, 16> RVLocs2;
1731 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1732 getTargetMachine(), RVLocs2, *DAG.getContext());
1733 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1735 if (RVLocs1.size() != RVLocs2.size())
1737 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1738 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1740 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1742 if (RVLocs1[i].isRegLoc()) {
1743 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1746 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1752 // Nothing more to check if the callee is taking no arguments
1756 SmallVector<CCValAssign, 16> ArgLocs;
1757 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1758 getTargetMachine(), ArgLocs, *DAG.getContext());
1760 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1762 const AArch64MachineFunctionInfo *FuncInfo
1763 = MF.getInfo<AArch64MachineFunctionInfo>();
1765 // If the stack arguments for this call would fit into our own save area then
1766 // the call can be made tail.
1767 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1770 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1771 bool TailCallOpt) const {
1772 return CallCC == CallingConv::Fast && TailCallOpt;
1775 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1776 return CallCC == CallingConv::Fast;
1779 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1781 MachineFrameInfo *MFI,
1782 int ClobberedFI) const {
1783 SmallVector<SDValue, 8> ArgChains;
1784 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1785 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1787 // Include the original chain at the beginning of the list. When this is
1788 // used by target LowerCall hooks, this helps legalize find the
1789 // CALLSEQ_BEGIN node.
1790 ArgChains.push_back(Chain);
1792 // Add a chain value for each stack argument corresponding
1793 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1794 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1795 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1796 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1797 if (FI->getIndex() < 0) {
1798 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1799 int64_t InLastByte = InFirstByte;
1800 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1802 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1803 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1804 ArgChains.push_back(SDValue(L, 1));
1807 // Build a tokenfactor for all the chains.
1808 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1809 &ArgChains[0], ArgChains.size());
1812 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1814 case ISD::SETEQ: return A64CC::EQ;
1815 case ISD::SETGT: return A64CC::GT;
1816 case ISD::SETGE: return A64CC::GE;
1817 case ISD::SETLT: return A64CC::LT;
1818 case ISD::SETLE: return A64CC::LE;
1819 case ISD::SETNE: return A64CC::NE;
1820 case ISD::SETUGT: return A64CC::HI;
1821 case ISD::SETUGE: return A64CC::HS;
1822 case ISD::SETULT: return A64CC::LO;
1823 case ISD::SETULE: return A64CC::LS;
1824 default: llvm_unreachable("Unexpected condition code");
1828 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1829 // icmp is implemented using adds/subs immediate, which take an unsigned
1830 // 12-bit immediate, optionally shifted left by 12 bits.
1832 // Symmetric by using adds/subs
1836 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1839 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1840 ISD::CondCode CC, SDValue &A64cc,
1841 SelectionDAG &DAG, SDLoc &dl) const {
1842 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1844 EVT VT = RHSC->getValueType(0);
1845 bool knownInvalid = false;
1847 // I'm not convinced the rest of LLVM handles these edge cases properly, but
1848 // we can at least get it right.
1849 if (isSignedIntSetCC(CC)) {
1850 C = RHSC->getSExtValue();
1851 } else if (RHSC->getZExtValue() > INT64_MAX) {
1852 // A 64-bit constant not representable by a signed 64-bit integer is far
1853 // too big to fit into a SUBS immediate anyway.
1854 knownInvalid = true;
1856 C = RHSC->getZExtValue();
1859 if (!knownInvalid && !isLegalICmpImmediate(C)) {
1860 // Constant does not fit, try adjusting it by one?
1865 if (isLegalICmpImmediate(C-1)) {
1866 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1867 RHS = DAG.getConstant(C-1, VT);
1872 if (isLegalICmpImmediate(C-1)) {
1873 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1874 RHS = DAG.getConstant(C-1, VT);
1879 if (isLegalICmpImmediate(C+1)) {
1880 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1881 RHS = DAG.getConstant(C+1, VT);
1886 if (isLegalICmpImmediate(C+1)) {
1887 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1888 RHS = DAG.getConstant(C+1, VT);
1895 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
1896 A64cc = DAG.getConstant(CondCode, MVT::i32);
1897 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1898 DAG.getCondCode(CC));
1901 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1902 A64CC::CondCodes &Alternative) {
1903 A64CC::CondCodes CondCode = A64CC::Invalid;
1904 Alternative = A64CC::Invalid;
1907 default: llvm_unreachable("Unknown FP condition!");
1909 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
1911 case ISD::SETOGT: CondCode = A64CC::GT; break;
1913 case ISD::SETOGE: CondCode = A64CC::GE; break;
1914 case ISD::SETOLT: CondCode = A64CC::MI; break;
1915 case ISD::SETOLE: CondCode = A64CC::LS; break;
1916 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
1917 case ISD::SETO: CondCode = A64CC::VC; break;
1918 case ISD::SETUO: CondCode = A64CC::VS; break;
1919 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
1920 case ISD::SETUGT: CondCode = A64CC::HI; break;
1921 case ISD::SETUGE: CondCode = A64CC::PL; break;
1923 case ISD::SETULT: CondCode = A64CC::LT; break;
1925 case ISD::SETULE: CondCode = A64CC::LE; break;
1927 case ISD::SETUNE: CondCode = A64CC::NE; break;
1933 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1935 EVT PtrVT = getPointerTy();
1936 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1938 switch(getTargetMachine().getCodeModel()) {
1939 case CodeModel::Small:
1940 // The most efficient code is PC-relative anyway for the small memory model,
1941 // so we don't need to worry about relocation model.
1942 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
1943 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1944 AArch64II::MO_NO_FLAG),
1945 DAG.getTargetBlockAddress(BA, PtrVT, 0,
1946 AArch64II::MO_LO12),
1947 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
1948 case CodeModel::Large:
1950 AArch64ISD::WrapperLarge, DL, PtrVT,
1951 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3),
1952 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
1953 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
1954 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
1956 llvm_unreachable("Only small and large code models supported now");
1961 // (BRCOND chain, val, dest)
1963 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1965 SDValue Chain = Op.getOperand(0);
1966 SDValue TheBit = Op.getOperand(1);
1967 SDValue DestBB = Op.getOperand(2);
1969 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
1970 // that as the consumer we are responsible for ignoring rubbish in higher
1972 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
1973 DAG.getConstant(1, MVT::i32));
1975 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
1976 DAG.getConstant(0, TheBit.getValueType()),
1977 DAG.getCondCode(ISD::SETNE));
1979 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
1980 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
1984 // (BR_CC chain, condcode, lhs, rhs, dest)
1986 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1988 SDValue Chain = Op.getOperand(0);
1989 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1990 SDValue LHS = Op.getOperand(2);
1991 SDValue RHS = Op.getOperand(3);
1992 SDValue DestBB = Op.getOperand(4);
1994 if (LHS.getValueType() == MVT::f128) {
1995 // f128 comparisons are lowered to runtime calls by a routine which sets
1996 // LHS, RHS and CC appropriately for the rest of this function to continue.
1997 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
1999 // If softenSetCCOperands returned a scalar, we need to compare the result
2000 // against zero to select between true and false values.
2001 if (RHS.getNode() == 0) {
2002 RHS = DAG.getConstant(0, LHS.getValueType());
2007 if (LHS.getValueType().isInteger()) {
2010 // Integers are handled in a separate function because the combinations of
2011 // immediates and tests can get hairy and we may want to fiddle things.
2012 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2014 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2015 Chain, CmpOp, A64cc, DestBB);
2018 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2019 // conditional branch, hence FPCCToA64CC can set a second test, where either
2020 // passing is sufficient.
2021 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2022 CondCode = FPCCToA64CC(CC, Alternative);
2023 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2024 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2025 DAG.getCondCode(CC));
2026 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2027 Chain, SetCC, A64cc, DestBB);
2029 if (Alternative != A64CC::Invalid) {
2030 A64cc = DAG.getConstant(Alternative, MVT::i32);
2031 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2032 A64BR_CC, SetCC, A64cc, DestBB);
2040 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
2041 RTLIB::Libcall Call) const {
2044 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
2045 EVT ArgVT = Op.getOperand(i).getValueType();
2046 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2047 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
2048 Entry.isSExt = false;
2049 Entry.isZExt = false;
2050 Args.push_back(Entry);
2052 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
2054 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2056 // By default, the input chain to this libcall is the entry node of the
2057 // function. If the libcall is going to be emitted as a tail call then
2058 // isUsedByReturnOnly will change it to the right chain if the return
2059 // node which is being folded has a non-entry input chain.
2060 SDValue InChain = DAG.getEntryNode();
2062 // isTailCall may be true since the callee does not reference caller stack
2063 // frame. Check if it's in the right position.
2064 SDValue TCChain = InChain;
2065 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
2070 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
2071 0, getLibcallCallingConv(Call), isTailCall,
2072 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2073 Callee, Args, DAG, SDLoc(Op));
2074 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2076 if (!CallInfo.second.getNode())
2077 // It's a tailcall, return the chain (which is the DAG root).
2078 return DAG.getRoot();
2080 return CallInfo.first;
2084 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
2085 if (Op.getOperand(0).getValueType() != MVT::f128) {
2086 // It's legal except when f128 is involved
2091 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
2093 SDValue SrcVal = Op.getOperand(0);
2094 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
2095 /*isSigned*/ false, SDLoc(Op)).first;
2099 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
2100 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
2103 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
2105 return LowerF128ToCall(Op, DAG, LC);
2109 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2110 bool IsSigned) const {
2111 if (Op.getOperand(0).getValueType() != MVT::f128) {
2112 // It's legal except when f128 is involved
2118 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2120 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2122 return LowerF128ToCall(Op, DAG, LC);
2125 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2126 MachineFunction &MF = DAG.getMachineFunction();
2127 MachineFrameInfo *MFI = MF.getFrameInfo();
2128 MFI->setReturnAddressIsTaken(true);
2130 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2133 EVT VT = Op.getValueType();
2135 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2137 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2138 SDValue Offset = DAG.getConstant(8, MVT::i64);
2139 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2140 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2141 MachinePointerInfo(), false, false, false, 0);
2144 // Return X30, which contains the return address. Mark it an implicit live-in.
2145 unsigned Reg = MF.addLiveIn(AArch64::X30, getRegClassFor(MVT::i64));
2146 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, MVT::i64);
2150 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
2152 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2153 MFI->setFrameAddressIsTaken(true);
2155 EVT VT = Op.getValueType();
2157 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2158 unsigned FrameReg = AArch64::X29;
2159 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2161 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2162 MachinePointerInfo(),
2163 false, false, false, 0);
2168 AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op,
2169 SelectionDAG &DAG) const {
2170 assert(getTargetMachine().getCodeModel() == CodeModel::Large);
2171 assert(getTargetMachine().getRelocationModel() == Reloc::Static);
2173 EVT PtrVT = getPointerTy();
2175 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2176 const GlobalValue *GV = GN->getGlobal();
2178 SDValue GlobalAddr = DAG.getNode(
2179 AArch64ISD::WrapperLarge, dl, PtrVT,
2180 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3),
2181 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2182 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2183 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2185 if (GN->getOffset() != 0)
2186 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2187 DAG.getConstant(GN->getOffset(), PtrVT));
2193 AArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op,
2194 SelectionDAG &DAG) const {
2195 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
2197 EVT PtrVT = getPointerTy();
2199 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2200 const GlobalValue *GV = GN->getGlobal();
2201 unsigned Alignment = GV->getAlignment();
2202 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2203 if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) {
2204 // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate
2205 // to zero when they remain undefined. In PIC mode the GOT can take care of
2206 // this, but in absolute mode we use a constant pool load.
2208 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2209 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2210 AArch64II::MO_NO_FLAG),
2211 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2212 AArch64II::MO_LO12),
2213 DAG.getConstant(8, MVT::i32));
2214 SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
2215 MachinePointerInfo::getConstantPool(),
2216 /*isVolatile=*/ false,
2217 /*isNonTemporal=*/ true,
2218 /*isInvariant=*/ true, 8);
2219 if (GN->getOffset() != 0)
2220 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2221 DAG.getConstant(GN->getOffset(), PtrVT));
2226 if (Alignment == 0) {
2227 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
2228 if (GVPtrTy->getElementType()->isSized()) {
2230 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
2232 // Be conservative if we can't guess, not that it really matters:
2233 // functions and labels aren't valid for loads, and the methods used to
2234 // actually calculate an address work with any alignment.
2239 unsigned char HiFixup, LoFixup;
2240 bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM);
2243 HiFixup = AArch64II::MO_GOT;
2244 LoFixup = AArch64II::MO_GOT_LO12;
2247 HiFixup = AArch64II::MO_NO_FLAG;
2248 LoFixup = AArch64II::MO_LO12;
2251 // AArch64's small model demands the following sequence:
2252 // ADRP x0, somewhere
2253 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
2254 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2255 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2257 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2259 DAG.getConstant(Alignment, MVT::i32));
2262 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
2266 if (GN->getOffset() != 0)
2267 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
2268 DAG.getConstant(GN->getOffset(), PtrVT));
2274 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
2275 SelectionDAG &DAG) const {
2276 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
2277 // we make those distinctions here.
2279 switch (getTargetMachine().getCodeModel()) {
2280 case CodeModel::Small:
2281 return LowerGlobalAddressELFSmall(Op, DAG);
2282 case CodeModel::Large:
2283 return LowerGlobalAddressELFLarge(Op, DAG);
2285 llvm_unreachable("Only small and large code models supported now");
2290 AArch64TargetLowering::LowerConstantPool(SDValue Op,
2291 SelectionDAG &DAG) const {
2293 EVT PtrVT = getPointerTy();
2294 ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Op);
2295 const Constant *C = CN->getConstVal();
2297 switch(getTargetMachine().getCodeModel()) {
2298 case CodeModel::Small:
2299 // The most efficient code is PC-relative anyway for the small memory model,
2300 // so we don't need to worry about relocation model.
2301 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2302 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2303 AArch64II::MO_NO_FLAG),
2304 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2305 AArch64II::MO_LO12),
2306 DAG.getConstant(CN->getAlignment(), MVT::i32));
2307 case CodeModel::Large:
2309 AArch64ISD::WrapperLarge, DL, PtrVT,
2310 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
2311 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
2312 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
2313 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC));
2315 llvm_unreachable("Only small and large code models supported now");
2319 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
2322 SelectionDAG &DAG) const {
2323 EVT PtrVT = getPointerTy();
2325 // The function we need to call is simply the first entry in the GOT for this
2326 // descriptor, load it in preparation.
2327 SDValue Func, Chain;
2328 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2331 // The function takes only one argument: the address of the descriptor itself
2334 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2335 Glue = Chain.getValue(1);
2337 // Finally, there's a special calling-convention which means that the lookup
2338 // must preserve all registers (except X0, obviously).
2339 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2340 const AArch64RegisterInfo *A64RI
2341 = static_cast<const AArch64RegisterInfo *>(TRI);
2342 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
2344 // We're now ready to populate the argument list, as with a normal call:
2345 std::vector<SDValue> Ops;
2346 Ops.push_back(Chain);
2347 Ops.push_back(Func);
2348 Ops.push_back(SymAddr);
2349 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2350 Ops.push_back(DAG.getRegisterMask(Mask));
2351 Ops.push_back(Glue);
2353 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2354 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
2356 Glue = Chain.getValue(1);
2358 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
2359 // back to the generic handling code.
2360 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2364 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2365 SelectionDAG &DAG) const {
2366 assert(getSubtarget()->isTargetELF() &&
2367 "TLS not implemented for non-ELF targets");
2368 assert(getTargetMachine().getCodeModel() == CodeModel::Small
2369 && "TLS only supported in small memory model");
2370 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2372 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2375 EVT PtrVT = getPointerTy();
2377 const GlobalValue *GV = GA->getGlobal();
2379 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2381 if (Model == TLSModel::InitialExec) {
2382 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2383 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2384 AArch64II::MO_GOTTPREL),
2385 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2386 AArch64II::MO_GOTTPREL_LO12),
2387 DAG.getConstant(8, MVT::i32));
2388 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2390 } else if (Model == TLSModel::LocalExec) {
2391 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2392 AArch64II::MO_TPREL_G1);
2393 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2394 AArch64II::MO_TPREL_G0_NC);
2396 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2397 DAG.getTargetConstant(1, MVT::i32)), 0);
2398 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2400 DAG.getTargetConstant(0, MVT::i32)), 0);
2401 } else if (Model == TLSModel::GeneralDynamic) {
2402 // Accesses used in this sequence go via the TLS descriptor which lives in
2403 // the GOT. Prepare an address we can use to handle this.
2404 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2405 AArch64II::MO_TLSDESC);
2406 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2407 AArch64II::MO_TLSDESC_LO12);
2408 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2410 DAG.getConstant(8, MVT::i32));
2411 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2413 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2414 } else if (Model == TLSModel::LocalDynamic) {
2415 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2416 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2417 // the beginning of the module's TLS region, followed by a DTPREL offset
2420 // These accesses will need deduplicating if there's more than one.
2421 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2422 .getInfo<AArch64MachineFunctionInfo>();
2423 MFI->incNumLocalDynamicTLSAccesses();
2426 // Get the location of _TLS_MODULE_BASE_:
2427 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2428 AArch64II::MO_TLSDESC);
2429 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2430 AArch64II::MO_TLSDESC_LO12);
2431 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2433 DAG.getConstant(8, MVT::i32));
2434 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2436 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2438 // Get the variable's offset from _TLS_MODULE_BASE_
2439 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2440 AArch64II::MO_DTPREL_G1);
2441 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2442 AArch64II::MO_DTPREL_G0_NC);
2444 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2445 DAG.getTargetConstant(0, MVT::i32)), 0);
2446 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2448 DAG.getTargetConstant(0, MVT::i32)), 0);
2450 llvm_unreachable("Unsupported TLS access model");
2453 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2457 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2458 bool IsSigned) const {
2459 if (Op.getValueType() != MVT::f128) {
2460 // Legal for everything except f128.
2466 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2468 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2470 return LowerF128ToCall(Op, DAG, LC);
2475 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2476 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2478 EVT PtrVT = getPointerTy();
2480 // When compiling PIC, jump tables get put in the code section so a static
2481 // relocation-style is acceptable for both cases.
2482 switch (getTargetMachine().getCodeModel()) {
2483 case CodeModel::Small:
2484 return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2485 DAG.getTargetJumpTable(JT->getIndex(), PtrVT),
2486 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2487 AArch64II::MO_LO12),
2488 DAG.getConstant(1, MVT::i32));
2489 case CodeModel::Large:
2491 AArch64ISD::WrapperLarge, dl, PtrVT,
2492 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3),
2493 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC),
2494 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC),
2495 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC));
2497 llvm_unreachable("Only small and large code models supported now");
2501 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
2503 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2505 SDValue LHS = Op.getOperand(0);
2506 SDValue RHS = Op.getOperand(1);
2507 SDValue IfTrue = Op.getOperand(2);
2508 SDValue IfFalse = Op.getOperand(3);
2509 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2511 if (LHS.getValueType() == MVT::f128) {
2512 // f128 comparisons are lowered to libcalls, but slot in nicely here
2514 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2516 // If softenSetCCOperands returned a scalar, we need to compare the result
2517 // against zero to select between true and false values.
2518 if (RHS.getNode() == 0) {
2519 RHS = DAG.getConstant(0, LHS.getValueType());
2524 if (LHS.getValueType().isInteger()) {
2527 // Integers are handled in a separate function because the combinations of
2528 // immediates and tests can get hairy and we may want to fiddle things.
2529 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2531 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2532 CmpOp, IfTrue, IfFalse, A64cc);
2535 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2536 // conditional branch, hence FPCCToA64CC can set a second test, where either
2537 // passing is sufficient.
2538 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2539 CondCode = FPCCToA64CC(CC, Alternative);
2540 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2541 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2542 DAG.getCondCode(CC));
2543 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
2545 SetCC, IfTrue, IfFalse, A64cc);
2547 if (Alternative != A64CC::Invalid) {
2548 A64cc = DAG.getConstant(Alternative, MVT::i32);
2549 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2550 SetCC, IfTrue, A64SELECT_CC, A64cc);
2554 return A64SELECT_CC;
2557 // (SELECT testbit, iftrue, iffalse)
2559 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2561 SDValue TheBit = Op.getOperand(0);
2562 SDValue IfTrue = Op.getOperand(1);
2563 SDValue IfFalse = Op.getOperand(2);
2565 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2566 // that as the consumer we are responsible for ignoring rubbish in higher
2568 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2569 DAG.getConstant(1, MVT::i32));
2570 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2571 DAG.getConstant(0, TheBit.getValueType()),
2572 DAG.getCondCode(ISD::SETNE));
2574 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2575 A64CMP, IfTrue, IfFalse,
2576 DAG.getConstant(A64CC::NE, MVT::i32));
2579 static SDValue LowerVectorSETCC(SDValue Op, SelectionDAG &DAG) {
2581 SDValue LHS = Op.getOperand(0);
2582 SDValue RHS = Op.getOperand(1);
2583 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2584 EVT VT = Op.getValueType();
2585 bool Invert = false;
2589 if (LHS.getValueType().isInteger()) {
2591 // Attempt to use Vector Integer Compare Mask Test instruction.
2592 // TST = icmp ne (and (op0, op1), zero).
2593 if (CC == ISD::SETNE) {
2594 if (((LHS.getOpcode() == ISD::AND) &&
2595 ISD::isBuildVectorAllZeros(RHS.getNode())) ||
2596 ((RHS.getOpcode() == ISD::AND) &&
2597 ISD::isBuildVectorAllZeros(LHS.getNode()))) {
2599 SDValue AndOp = (LHS.getOpcode() == ISD::AND) ? LHS : RHS;
2600 SDValue NewLHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(0));
2601 SDValue NewRHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(1));
2602 return DAG.getNode(AArch64ISD::NEON_TST, DL, VT, NewLHS, NewRHS);
2606 // Attempt to use Vector Integer Compare Mask against Zero instr (Signed).
2607 // Note: Compare against Zero does not support unsigned predicates.
2608 if ((ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2609 ISD::isBuildVectorAllZeros(LHS.getNode())) &&
2610 !isUnsignedIntSetCC(CC)) {
2612 // If LHS is the zero value, swap operands and CondCode.
2613 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2614 CC = getSetCCSwappedOperands(CC);
2619 // Ensure valid CondCode for Compare Mask against Zero instruction:
2620 // EQ, GE, GT, LE, LT.
2621 if (ISD::SETNE == CC) {
2626 // Using constant type to differentiate integer and FP compares with zero.
2627 Op1 = DAG.getConstant(0, MVT::i32);
2628 Opcode = AArch64ISD::NEON_CMPZ;
2631 // Attempt to use Vector Integer Compare Mask instr (Signed/Unsigned).
2632 // Ensure valid CondCode for Compare Mask instr: EQ, GE, GT, UGE, UGT.
2636 llvm_unreachable("Illegal integer comparison.");
2652 CC = getSetCCSwappedOperands(CC);
2656 std::swap(LHS, RHS);
2658 Opcode = AArch64ISD::NEON_CMP;
2663 // Generate Compare Mask instr or Compare Mask against Zero instr.
2665 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2668 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2673 // Now handle Floating Point cases.
2674 // Attempt to use Vector Floating Point Compare Mask against Zero instruction.
2675 if (ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2676 ISD::isBuildVectorAllZeros(LHS.getNode())) {
2678 // If LHS is the zero value, swap operands and CondCode.
2679 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2680 CC = getSetCCSwappedOperands(CC);
2685 // Using constant type to differentiate integer and FP compares with zero.
2686 Op1 = DAG.getConstantFP(0, MVT::f32);
2687 Opcode = AArch64ISD::NEON_CMPZ;
2689 // Attempt to use Vector Floating Point Compare Mask instruction.
2692 Opcode = AArch64ISD::NEON_CMP;
2696 // Some register compares have to be implemented with swapped CC and operands,
2697 // e.g.: OLT implemented as OGT with swapped operands.
2698 bool SwapIfRegArgs = false;
2700 // Ensure valid CondCode for FP Compare Mask against Zero instruction:
2701 // EQ, GE, GT, LE, LT.
2702 // And ensure valid CondCode for FP Compare Mask instruction: EQ, GE, GT.
2705 llvm_unreachable("Illegal FP comparison");
2708 Invert = true; // Fallthrough
2716 SwapIfRegArgs = true;
2725 SwapIfRegArgs = true;
2734 SwapIfRegArgs = true;
2743 SwapIfRegArgs = true;
2750 Invert = true; // Fallthrough
2752 // Expand this to (OGT |OLT).
2754 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT));
2756 SwapIfRegArgs = true;
2759 Invert = true; // Fallthrough
2761 // Expand this to (OGE | OLT).
2763 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE));
2765 SwapIfRegArgs = true;
2769 if (Opcode == AArch64ISD::NEON_CMP && SwapIfRegArgs) {
2770 CC = getSetCCSwappedOperands(CC);
2771 std::swap(Op0, Op1);
2774 // Generate FP Compare Mask instr or FP Compare Mask against Zero instr
2775 SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2777 if (NeonCmpAlt.getNode())
2778 NeonCmp = DAG.getNode(ISD::OR, DL, VT, NeonCmp, NeonCmpAlt);
2781 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2786 // (SETCC lhs, rhs, condcode)
2788 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2790 SDValue LHS = Op.getOperand(0);
2791 SDValue RHS = Op.getOperand(1);
2792 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2793 EVT VT = Op.getValueType();
2796 return LowerVectorSETCC(Op, DAG);
2798 if (LHS.getValueType() == MVT::f128) {
2799 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
2800 // for the rest of the function (some i32 or i64 values).
2801 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2803 // If softenSetCCOperands returned a scalar, use it.
2804 if (RHS.getNode() == 0) {
2805 assert(LHS.getValueType() == Op.getValueType() &&
2806 "Unexpected setcc expansion!");
2811 if (LHS.getValueType().isInteger()) {
2814 // Integers are handled in a separate function because the combinations of
2815 // immediates and tests can get hairy and we may want to fiddle things.
2816 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2818 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2819 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2823 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2824 // conditional branch, hence FPCCToA64CC can set a second test, where either
2825 // passing is sufficient.
2826 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2827 CondCode = FPCCToA64CC(CC, Alternative);
2828 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2829 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2830 DAG.getCondCode(CC));
2831 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
2832 CmpOp, DAG.getConstant(1, VT),
2833 DAG.getConstant(0, VT), A64cc);
2835 if (Alternative != A64CC::Invalid) {
2836 A64cc = DAG.getConstant(Alternative, MVT::i32);
2837 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
2838 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
2841 return A64SELECT_CC;
2845 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2846 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2847 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2849 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
2850 // rather than just 8.
2851 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op),
2852 Op.getOperand(1), Op.getOperand(2),
2853 DAG.getConstant(32, MVT::i32), 8, false, false,
2854 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
2858 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2859 // The layout of the va_list struct is specified in the AArch64 Procedure Call
2860 // Standard, section B.3.
2861 MachineFunction &MF = DAG.getMachineFunction();
2862 AArch64MachineFunctionInfo *FuncInfo
2863 = MF.getInfo<AArch64MachineFunctionInfo>();
2866 SDValue Chain = Op.getOperand(0);
2867 SDValue VAList = Op.getOperand(1);
2868 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2869 SmallVector<SDValue, 4> MemOps;
2871 // void *__stack at offset 0
2872 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
2874 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
2875 MachinePointerInfo(SV), false, false, 0));
2877 // void *__gr_top at offset 8
2878 int GPRSize = FuncInfo->getVariadicGPRSize();
2880 SDValue GRTop, GRTopAddr;
2882 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2883 DAG.getConstant(8, getPointerTy()));
2885 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
2886 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
2887 DAG.getConstant(GPRSize, getPointerTy()));
2889 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
2890 MachinePointerInfo(SV, 8),
2894 // void *__vr_top at offset 16
2895 int FPRSize = FuncInfo->getVariadicFPRSize();
2897 SDValue VRTop, VRTopAddr;
2898 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2899 DAG.getConstant(16, getPointerTy()));
2901 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
2902 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
2903 DAG.getConstant(FPRSize, getPointerTy()));
2905 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
2906 MachinePointerInfo(SV, 16),
2910 // int __gr_offs at offset 24
2911 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2912 DAG.getConstant(24, getPointerTy()));
2913 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
2914 GROffsAddr, MachinePointerInfo(SV, 24),
2917 // int __vr_offs at offset 28
2918 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2919 DAG.getConstant(28, getPointerTy()));
2920 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
2921 VROffsAddr, MachinePointerInfo(SV, 28),
2924 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
2929 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2930 switch (Op.getOpcode()) {
2931 default: llvm_unreachable("Don't know how to custom lower this!");
2932 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
2933 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
2934 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
2935 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
2936 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
2937 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
2938 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
2939 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
2940 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
2941 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
2942 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2943 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2945 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2946 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
2947 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2948 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
2949 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2950 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2951 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2952 case ISD::SELECT: return LowerSELECT(Op, DAG);
2953 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2954 case ISD::SETCC: return LowerSETCC(Op, DAG);
2955 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
2956 case ISD::VASTART: return LowerVASTART(Op, DAG);
2957 case ISD::BUILD_VECTOR:
2958 return LowerBUILD_VECTOR(Op, DAG, getSubtarget());
2959 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2965 /// Check if the specified splat value corresponds to a valid vector constant
2966 /// for a Neon instruction with a "modified immediate" operand (e.g., MOVI). If
2967 /// so, return the encoded 8-bit immediate and the OpCmode instruction fields
2969 static bool isNeonModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2970 unsigned SplatBitSize, SelectionDAG &DAG,
2971 bool is128Bits, NeonModImmType type, EVT &VT,
2972 unsigned &Imm, unsigned &OpCmode) {
2973 switch (SplatBitSize) {
2975 llvm_unreachable("unexpected size for isNeonModifiedImm");
2977 if (type != Neon_Mov_Imm)
2979 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2980 // Neon movi per byte: Op=0, Cmode=1110.
2983 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
2987 // Neon move inst per halfword
2988 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
2989 if ((SplatBits & ~0xff) == 0) {
2990 // Value = 0x00nn is 0x00nn LSL 0
2991 // movi: Op=0, Cmode=1000; mvni: Op=1, Cmode=1000
2992 // bic: Op=1, Cmode=1001; orr: Op=0, Cmode=1001
2998 if ((SplatBits & ~0xff00) == 0) {
2999 // Value = 0xnn00 is 0x00nn LSL 8
3000 // movi: Op=0, Cmode=1010; mvni: Op=1, Cmode=1010
3001 // bic: Op=1, Cmode=1011; orr: Op=0, Cmode=1011
3003 Imm = SplatBits >> 8;
3007 // can't handle any other
3012 // First the LSL variants (MSL is unusable by some interested instructions).
3014 // Neon move instr per word, shift zeros
3015 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3016 if ((SplatBits & ~0xff) == 0) {
3017 // Value = 0x000000nn is 0x000000nn LSL 0
3018 // movi: Op=0, Cmode= 0000; mvni: Op=1, Cmode= 0000
3019 // bic: Op=1, Cmode= 0001; orr: Op=0, Cmode= 0001
3025 if ((SplatBits & ~0xff00) == 0) {
3026 // Value = 0x0000nn00 is 0x000000nn LSL 8
3027 // movi: Op=0, Cmode= 0010; mvni: Op=1, Cmode= 0010
3028 // bic: Op=1, Cmode= 0011; orr : Op=0, Cmode= 0011
3030 Imm = SplatBits >> 8;
3034 if ((SplatBits & ~0xff0000) == 0) {
3035 // Value = 0x00nn0000 is 0x000000nn LSL 16
3036 // movi: Op=0, Cmode= 0100; mvni: Op=1, Cmode= 0100
3037 // bic: Op=1, Cmode= 0101; orr: Op=0, Cmode= 0101
3039 Imm = SplatBits >> 16;
3043 if ((SplatBits & ~0xff000000) == 0) {
3044 // Value = 0xnn000000 is 0x000000nn LSL 24
3045 // movi: Op=0, Cmode= 0110; mvni: Op=1, Cmode= 0110
3046 // bic: Op=1, Cmode= 0111; orr: Op=0, Cmode= 0111
3048 Imm = SplatBits >> 24;
3053 // Now the MSL immediates.
3055 // Neon move instr per word, shift ones
3056 if ((SplatBits & ~0xffff) == 0 &&
3057 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3058 // Value = 0x0000nnff is 0x000000nn MSL 8
3059 // movi: Op=0, Cmode= 1100; mvni: Op=1, Cmode= 1100
3061 Imm = SplatBits >> 8;
3065 if ((SplatBits & ~0xffffff) == 0 &&
3066 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3067 // Value = 0x00nnffff is 0x000000nn MSL 16
3068 // movi: Op=1, Cmode= 1101; mvni: Op=1, Cmode= 1101
3070 Imm = SplatBits >> 16;
3074 // can't handle any other
3079 if (type != Neon_Mov_Imm)
3081 // Neon move instr bytemask, where each byte is either 0x00 or 0xff.
3082 // movi Op=1, Cmode=1110.
3084 uint64_t BitMask = 0xff;
3086 unsigned ImmMask = 1;
3088 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3089 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3092 } else if ((SplatBits & BitMask) != 0) {
3099 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3107 static SDValue PerformANDCombine(SDNode *N,
3108 TargetLowering::DAGCombinerInfo &DCI) {
3110 SelectionDAG &DAG = DCI.DAG;
3112 EVT VT = N->getValueType(0);
3114 // We're looking for an SRA/SHL pair which form an SBFX.
3116 if (VT != MVT::i32 && VT != MVT::i64)
3119 if (!isa<ConstantSDNode>(N->getOperand(1)))
3122 uint64_t TruncMask = N->getConstantOperandVal(1);
3123 if (!isMask_64(TruncMask))
3126 uint64_t Width = CountPopulation_64(TruncMask);
3127 SDValue Shift = N->getOperand(0);
3129 if (Shift.getOpcode() != ISD::SRL)
3132 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3134 uint64_t LSB = Shift->getConstantOperandVal(1);
3136 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3139 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
3140 DAG.getConstant(LSB, MVT::i64),
3141 DAG.getConstant(LSB + Width - 1, MVT::i64));
3144 /// For a true bitfield insert, the bits getting into that contiguous mask
3145 /// should come from the low part of an existing value: they must be formed from
3146 /// a compatible SHL operation (unless they're already low). This function
3147 /// checks that condition and returns the least-significant bit that's
3148 /// intended. If the operation not a field preparation, -1 is returned.
3149 static int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT,
3150 SDValue &MaskedVal, uint64_t Mask) {
3151 if (!isShiftedMask_64(Mask))
3154 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
3155 // instruction. BFI will do a left-shift by LSB before applying the mask we've
3156 // spotted, so in general we should pre-emptively "undo" that by making sure
3157 // the incoming bits have had a right-shift applied to them.
3159 // This right shift, however, will combine with existing left/right shifts. In
3160 // the simplest case of a completely straight bitfield operation, it will be
3161 // expected to completely cancel out with an existing SHL. More complicated
3162 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
3165 uint64_t LSB = countTrailingZeros(Mask);
3166 int64_t ShiftRightRequired = LSB;
3167 if (MaskedVal.getOpcode() == ISD::SHL &&
3168 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3169 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
3170 MaskedVal = MaskedVal.getOperand(0);
3171 } else if (MaskedVal.getOpcode() == ISD::SRL &&
3172 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3173 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
3174 MaskedVal = MaskedVal.getOperand(0);
3177 if (ShiftRightRequired > 0)
3178 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
3179 DAG.getConstant(ShiftRightRequired, MVT::i64));
3180 else if (ShiftRightRequired < 0) {
3181 // We could actually end up with a residual left shift, for example with
3182 // "struc.bitfield = val << 1".
3183 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
3184 DAG.getConstant(-ShiftRightRequired, MVT::i64));
3190 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
3191 /// a mask and an extension. Returns true if a BFI was found and provides
3192 /// information on its surroundings.
3193 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
3196 if (N.getOpcode() == ISD::ZERO_EXTEND) {
3198 N = N.getOperand(0);
3201 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
3202 Mask = N->getConstantOperandVal(1);
3203 N = N.getOperand(0);
3205 // Mask is the whole width.
3206 Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
3209 if (N.getOpcode() == AArch64ISD::BFI) {
3217 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
3218 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
3219 /// can often be further combined with a larger mask. Ultimately, we want mask
3220 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
3221 static SDValue tryCombineToBFI(SDNode *N,
3222 TargetLowering::DAGCombinerInfo &DCI,
3223 const AArch64Subtarget *Subtarget) {
3224 SelectionDAG &DAG = DCI.DAG;
3226 EVT VT = N->getValueType(0);
3228 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3230 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
3231 // abandon the effort.
3232 SDValue LHS = N->getOperand(0);
3233 if (LHS.getOpcode() != ISD::AND)
3237 if (isa<ConstantSDNode>(LHS.getOperand(1)))
3238 LHSMask = LHS->getConstantOperandVal(1);
3242 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
3243 // is or abandon the effort.
3244 SDValue RHS = N->getOperand(1);
3245 if (RHS.getOpcode() != ISD::AND)
3249 if (isa<ConstantSDNode>(RHS.getOperand(1)))
3250 RHSMask = RHS->getConstantOperandVal(1);
3254 // Can't do anything if the masks are incompatible.
3255 if (LHSMask & RHSMask)
3258 // Now we need one of the masks to be a contiguous field. Without loss of
3259 // generality that should be the RHS one.
3260 SDValue Bitfield = LHS.getOperand(0);
3261 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
3262 // We know that LHS is a candidate new value, and RHS isn't already a better
3264 std::swap(LHS, RHS);
3265 std::swap(LHSMask, RHSMask);
3268 // We've done our best to put the right operands in the right places, all we
3269 // can do now is check whether a BFI exists.
3270 Bitfield = RHS.getOperand(0);
3271 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
3275 uint32_t Width = CountPopulation_64(RHSMask);
3276 assert(Width && "Expected non-zero bitfield width");
3278 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3279 LHS.getOperand(0), Bitfield,
3280 DAG.getConstant(LSB, MVT::i64),
3281 DAG.getConstant(Width, MVT::i64));
3284 if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3287 return DAG.getNode(ISD::AND, DL, VT, BFI,
3288 DAG.getConstant(LHSMask | RHSMask, VT));
3291 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
3292 /// original input. This is surprisingly common because SROA splits things up
3293 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
3294 /// on the low (say) byte of a word. This is then orred into the rest of the
3295 /// word afterwards.
3297 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
3299 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
3300 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
3302 static SDValue tryCombineToLargerBFI(SDNode *N,
3303 TargetLowering::DAGCombinerInfo &DCI,
3304 const AArch64Subtarget *Subtarget) {
3305 SelectionDAG &DAG = DCI.DAG;
3307 EVT VT = N->getValueType(0);
3309 // First job is to hunt for a MaskedBFI on either the left or right. Swap
3310 // operands if it's actually on the right.
3312 SDValue PossExtraMask;
3313 uint64_t ExistingMask = 0;
3314 bool Extended = false;
3315 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
3316 PossExtraMask = N->getOperand(1);
3317 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
3318 PossExtraMask = N->getOperand(0);
3322 // We can only combine a BFI with another compatible mask.
3323 if (PossExtraMask.getOpcode() != ISD::AND ||
3324 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
3327 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
3329 // Masks must be compatible.
3330 if (ExtraMask & ExistingMask)
3333 SDValue OldBFIVal = BFI.getOperand(0);
3334 SDValue NewBFIVal = BFI.getOperand(1);
3336 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
3337 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
3338 // need to be made compatible.
3339 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
3340 && "Invalid types for BFI");
3341 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
3342 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
3345 // We need the MaskedBFI to be combined with a mask of the *same* value.
3346 if (PossExtraMask.getOperand(0) != OldBFIVal)
3349 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3350 OldBFIVal, NewBFIVal,
3351 BFI.getOperand(2), BFI.getOperand(3));
3353 // If the masking is trivial, we don't need to create it.
3354 if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3357 return DAG.getNode(ISD::AND, DL, VT, BFI,
3358 DAG.getConstant(ExtraMask | ExistingMask, VT));
3361 /// An EXTR instruction is made up of two shifts, ORed together. This helper
3362 /// searches for and classifies those shifts.
3363 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
3365 if (N.getOpcode() == ISD::SHL)
3367 else if (N.getOpcode() == ISD::SRL)
3372 if (!isa<ConstantSDNode>(N.getOperand(1)))
3375 ShiftAmount = N->getConstantOperandVal(1);
3376 Src = N->getOperand(0);
3380 /// EXTR instruction extracts a contiguous chunk of bits from two existing
3381 /// registers viewed as a high/low pair. This function looks for the pattern:
3382 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
3383 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
3385 static SDValue tryCombineToEXTR(SDNode *N,
3386 TargetLowering::DAGCombinerInfo &DCI) {
3387 SelectionDAG &DAG = DCI.DAG;
3389 EVT VT = N->getValueType(0);
3391 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3393 if (VT != MVT::i32 && VT != MVT::i64)
3397 uint32_t ShiftLHS = 0;
3399 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
3403 uint32_t ShiftRHS = 0;
3405 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
3408 // If they're both trying to come from the high part of the register, they're
3409 // not really an EXTR.
3410 if (LHSFromHi == RHSFromHi)
3413 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
3417 std::swap(LHS, RHS);
3418 std::swap(ShiftLHS, ShiftRHS);
3421 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
3423 DAG.getConstant(ShiftRHS, MVT::i64));
3426 /// Target-specific dag combine xforms for ISD::OR
3427 static SDValue PerformORCombine(SDNode *N,
3428 TargetLowering::DAGCombinerInfo &DCI,
3429 const AArch64Subtarget *Subtarget) {
3431 SelectionDAG &DAG = DCI.DAG;
3433 EVT VT = N->getValueType(0);
3435 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3438 // Attempt to recognise bitfield-insert operations.
3439 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
3443 // Attempt to combine an existing MaskedBFI operation into one with a larger
3445 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
3449 Res = tryCombineToEXTR(N, DCI);
3453 if (!Subtarget->hasNEON())
3456 // Attempt to use vector immediate-form BSL
3457 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
3459 SDValue N0 = N->getOperand(0);
3460 if (N0.getOpcode() != ISD::AND)
3463 SDValue N1 = N->getOperand(1);
3464 if (N1.getOpcode() != ISD::AND)
3467 if (VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
3469 unsigned SplatBitSize;
3471 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
3473 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
3476 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
3478 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
3480 !HasAnyUndefs && SplatBits0 == ~SplatBits1) {
3482 return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1),
3483 N0->getOperand(0), N1->getOperand(0));
3491 /// Target-specific dag combine xforms for ISD::SRA
3492 static SDValue PerformSRACombine(SDNode *N,
3493 TargetLowering::DAGCombinerInfo &DCI) {
3495 SelectionDAG &DAG = DCI.DAG;
3497 EVT VT = N->getValueType(0);
3499 // We're looking for an SRA/SHL pair which form an SBFX.
3501 if (VT != MVT::i32 && VT != MVT::i64)
3504 if (!isa<ConstantSDNode>(N->getOperand(1)))
3507 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
3508 SDValue Shift = N->getOperand(0);
3510 if (Shift.getOpcode() != ISD::SHL)
3513 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3516 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
3517 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
3518 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
3520 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3523 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
3524 DAG.getConstant(LSB, MVT::i64),
3525 DAG.getConstant(LSB + Width - 1, MVT::i64));
3528 /// Check if this is a valid build_vector for the immediate operand of
3529 /// a vector shift operation, where all the elements of the build_vector
3530 /// must have the same constant integer value.
3531 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3532 // Ignore bit_converts.
3533 while (Op.getOpcode() == ISD::BITCAST)
3534 Op = Op.getOperand(0);
3535 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3536 APInt SplatBits, SplatUndef;
3537 unsigned SplatBitSize;
3539 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3540 HasAnyUndefs, ElementBits) ||
3541 SplatBitSize > ElementBits)
3543 Cnt = SplatBits.getSExtValue();
3547 /// Check if this is a valid build_vector for the immediate operand of
3548 /// a vector shift left operation. That value must be in the range:
3549 /// 0 <= Value < ElementBits
3550 static bool isVShiftLImm(SDValue Op, EVT VT, int64_t &Cnt) {
3551 assert(VT.isVector() && "vector shift count is not a vector type");
3552 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3553 if (!getVShiftImm(Op, ElementBits, Cnt))
3555 return (Cnt >= 0 && Cnt < ElementBits);
3558 /// Check if this is a valid build_vector for the immediate operand of a
3559 /// vector shift right operation. The value must be in the range:
3560 /// 1 <= Value <= ElementBits
3561 static bool isVShiftRImm(SDValue Op, EVT VT, int64_t &Cnt) {
3562 assert(VT.isVector() && "vector shift count is not a vector type");
3563 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3564 if (!getVShiftImm(Op, ElementBits, Cnt))
3566 return (Cnt >= 1 && Cnt <= ElementBits);
3569 /// Checks for immediate versions of vector shifts and lowers them.
3570 static SDValue PerformShiftCombine(SDNode *N,
3571 TargetLowering::DAGCombinerInfo &DCI,
3572 const AArch64Subtarget *ST) {
3573 SelectionDAG &DAG = DCI.DAG;
3574 EVT VT = N->getValueType(0);
3575 if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64))
3576 return PerformSRACombine(N, DCI);
3578 // Nothing to be done for scalar shifts.
3579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3580 if (!VT.isVector() || !TLI.isTypeLegal(VT))
3583 assert(ST->hasNEON() && "unexpected vector shift");
3586 switch (N->getOpcode()) {
3588 llvm_unreachable("unexpected shift opcode");
3591 if (isVShiftLImm(N->getOperand(1), VT, Cnt)) {
3593 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
3594 DAG.getConstant(Cnt, MVT::i32));
3595 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), RHS);
3601 if (isVShiftRImm(N->getOperand(1), VT, Cnt)) {
3603 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
3604 DAG.getConstant(Cnt, MVT::i32));
3605 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N->getOperand(0), RHS);
3613 /// ARM-specific DAG combining for intrinsics.
3614 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3615 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3619 // Don't do anything for most intrinsics.
3622 case Intrinsic::arm_neon_vqshifts:
3623 case Intrinsic::arm_neon_vqshiftu:
3624 EVT VT = N->getOperand(1).getValueType();
3626 if (!isVShiftLImm(N->getOperand(2), VT, Cnt))
3628 unsigned VShiftOpc = (IntNo == Intrinsic::arm_neon_vqshifts)
3629 ? AArch64ISD::NEON_QSHLs
3630 : AArch64ISD::NEON_QSHLu;
3631 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
3632 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3638 /// Target-specific DAG combine function for NEON load/store intrinsics
3639 /// to merge base address updates.
3640 static SDValue CombineBaseUpdate(SDNode *N,
3641 TargetLowering::DAGCombinerInfo &DCI) {
3642 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
3645 SelectionDAG &DAG = DCI.DAG;
3646 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
3647 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
3648 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
3649 SDValue Addr = N->getOperand(AddrOpIdx);
3651 // Search for a use of the address operand that is an increment.
3652 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
3653 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
3655 if (User->getOpcode() != ISD::ADD ||
3656 UI.getUse().getResNo() != Addr.getResNo())
3659 // Check that the add is independent of the load/store. Otherwise, folding
3660 // it would create a cycle.
3661 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
3664 // Find the new opcode for the updating load/store.
3666 bool isLaneOp = false;
3667 unsigned NewOpc = 0;
3668 unsigned NumVecs = 0;
3670 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3672 default: llvm_unreachable("unexpected intrinsic for Neon base update");
3673 case Intrinsic::arm_neon_vld1: NewOpc = AArch64ISD::NEON_LD1_UPD;
3675 case Intrinsic::arm_neon_vld2: NewOpc = AArch64ISD::NEON_LD2_UPD;
3677 case Intrinsic::arm_neon_vld3: NewOpc = AArch64ISD::NEON_LD3_UPD;
3679 case Intrinsic::arm_neon_vld4: NewOpc = AArch64ISD::NEON_LD4_UPD;
3681 case Intrinsic::arm_neon_vst1: NewOpc = AArch64ISD::NEON_ST1_UPD;
3682 NumVecs = 1; isLoad = false; break;
3683 case Intrinsic::arm_neon_vst2: NewOpc = AArch64ISD::NEON_ST2_UPD;
3684 NumVecs = 2; isLoad = false; break;
3685 case Intrinsic::arm_neon_vst3: NewOpc = AArch64ISD::NEON_ST3_UPD;
3686 NumVecs = 3; isLoad = false; break;
3687 case Intrinsic::arm_neon_vst4: NewOpc = AArch64ISD::NEON_ST4_UPD;
3688 NumVecs = 4; isLoad = false; break;
3689 case Intrinsic::aarch64_neon_vld1x2: NewOpc = AArch64ISD::NEON_LD1x2_UPD;
3691 case Intrinsic::aarch64_neon_vld1x3: NewOpc = AArch64ISD::NEON_LD1x3_UPD;
3693 case Intrinsic::aarch64_neon_vld1x4: NewOpc = AArch64ISD::NEON_LD1x4_UPD;
3695 case Intrinsic::aarch64_neon_vst1x2: NewOpc = AArch64ISD::NEON_ST1x2_UPD;
3696 NumVecs = 2; isLoad = false; break;
3697 case Intrinsic::aarch64_neon_vst1x3: NewOpc = AArch64ISD::NEON_ST1x3_UPD;
3698 NumVecs = 3; isLoad = false; break;
3699 case Intrinsic::aarch64_neon_vst1x4: NewOpc = AArch64ISD::NEON_ST1x4_UPD;
3700 NumVecs = 4; isLoad = false; break;
3701 case Intrinsic::arm_neon_vld2lane: NewOpc = AArch64ISD::NEON_LD2LN_UPD;
3702 NumVecs = 2; isLaneOp = true; break;
3703 case Intrinsic::arm_neon_vld3lane: NewOpc = AArch64ISD::NEON_LD3LN_UPD;
3704 NumVecs = 3; isLaneOp = true; break;
3705 case Intrinsic::arm_neon_vld4lane: NewOpc = AArch64ISD::NEON_LD4LN_UPD;
3706 NumVecs = 4; isLaneOp = true; break;
3707 case Intrinsic::arm_neon_vst2lane: NewOpc = AArch64ISD::NEON_ST2LN_UPD;
3708 NumVecs = 2; isLoad = false; isLaneOp = true; break;
3709 case Intrinsic::arm_neon_vst3lane: NewOpc = AArch64ISD::NEON_ST3LN_UPD;
3710 NumVecs = 3; isLoad = false; isLaneOp = true; break;
3711 case Intrinsic::arm_neon_vst4lane: NewOpc = AArch64ISD::NEON_ST4LN_UPD;
3712 NumVecs = 4; isLoad = false; isLaneOp = true; break;
3716 switch (N->getOpcode()) {
3717 default: llvm_unreachable("unexpected opcode for Neon base update");
3718 case AArch64ISD::NEON_LD2DUP: NewOpc = AArch64ISD::NEON_LD2DUP_UPD;
3720 case AArch64ISD::NEON_LD3DUP: NewOpc = AArch64ISD::NEON_LD3DUP_UPD;
3722 case AArch64ISD::NEON_LD4DUP: NewOpc = AArch64ISD::NEON_LD4DUP_UPD;
3727 // Find the size of memory referenced by the load/store.
3730 VecTy = N->getValueType(0);
3732 VecTy = N->getOperand(AddrOpIdx + 1).getValueType();
3733 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
3735 NumBytes /= VecTy.getVectorNumElements();
3737 // If the increment is a constant, it must match the memory ref size.
3738 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
3739 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
3740 uint32_t IncVal = CInc->getZExtValue();
3741 if (IncVal != NumBytes)
3743 Inc = DAG.getTargetConstant(IncVal, MVT::i32);
3746 // Create the new updating load/store node.
3748 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
3750 for (n = 0; n < NumResultVecs; ++n)
3752 Tys[n++] = MVT::i64;
3753 Tys[n] = MVT::Other;
3754 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs + 2);
3755 SmallVector<SDValue, 8> Ops;
3756 Ops.push_back(N->getOperand(0)); // incoming chain
3757 Ops.push_back(N->getOperand(AddrOpIdx));
3759 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
3760 Ops.push_back(N->getOperand(i));
3762 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
3763 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
3764 Ops.data(), Ops.size(),
3765 MemInt->getMemoryVT(),
3766 MemInt->getMemOperand());
3769 std::vector<SDValue> NewResults;
3770 for (unsigned i = 0; i < NumResultVecs; ++i) {
3771 NewResults.push_back(SDValue(UpdN.getNode(), i));
3773 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); // chain
3774 DCI.CombineTo(N, NewResults);
3775 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
3782 /// For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1)
3783 /// intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
3784 /// If so, combine them to a vldN-dup operation and return true.
3785 static SDValue CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
3786 SelectionDAG &DAG = DCI.DAG;
3787 EVT VT = N->getValueType(0);
3789 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
3790 SDNode *VLD = N->getOperand(0).getNode();
3791 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
3793 unsigned NumVecs = 0;
3794 unsigned NewOpc = 0;
3795 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
3796 if (IntNo == Intrinsic::arm_neon_vld2lane) {
3798 NewOpc = AArch64ISD::NEON_LD2DUP;
3799 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
3801 NewOpc = AArch64ISD::NEON_LD3DUP;
3802 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
3804 NewOpc = AArch64ISD::NEON_LD4DUP;
3809 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
3810 // numbers match the load.
3811 unsigned VLDLaneNo =
3812 cast<ConstantSDNode>(VLD->getOperand(NumVecs + 3))->getZExtValue();
3813 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
3815 // Ignore uses of the chain result.
3816 if (UI.getUse().getResNo() == NumVecs)
3819 if (User->getOpcode() != AArch64ISD::NEON_VDUPLANE ||
3820 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
3824 // Create the vldN-dup node.
3827 for (n = 0; n < NumVecs; ++n)
3829 Tys[n] = MVT::Other;
3830 SDVTList SDTys = DAG.getVTList(Tys, NumVecs + 1);
3831 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
3832 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
3833 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, Ops, 2,
3834 VLDMemInt->getMemoryVT(),
3835 VLDMemInt->getMemOperand());
3838 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
3840 unsigned ResNo = UI.getUse().getResNo();
3841 // Ignore uses of the chain result.
3842 if (ResNo == NumVecs)
3845 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
3848 // Now the vldN-lane intrinsic is dead except for its chain result.
3849 // Update uses of the chain.
3850 std::vector<SDValue> VLDDupResults;
3851 for (unsigned n = 0; n < NumVecs; ++n)
3852 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
3853 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
3854 DCI.CombineTo(VLD, VLDDupResults);
3856 return SDValue(N, 0);
3860 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
3861 DAGCombinerInfo &DCI) const {
3862 switch (N->getOpcode()) {
3864 case ISD::AND: return PerformANDCombine(N, DCI);
3865 case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
3869 return PerformShiftCombine(N, DCI, getSubtarget());
3870 case ISD::INTRINSIC_WO_CHAIN:
3871 return PerformIntrinsicCombine(N, DCI.DAG);
3872 case AArch64ISD::NEON_VDUPLANE:
3873 return CombineVLDDUP(N, DCI);
3874 case AArch64ISD::NEON_LD2DUP:
3875 case AArch64ISD::NEON_LD3DUP:
3876 case AArch64ISD::NEON_LD4DUP:
3877 return CombineBaseUpdate(N, DCI);
3878 case ISD::INTRINSIC_VOID:
3879 case ISD::INTRINSIC_W_CHAIN:
3880 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
3881 case Intrinsic::arm_neon_vld1:
3882 case Intrinsic::arm_neon_vld2:
3883 case Intrinsic::arm_neon_vld3:
3884 case Intrinsic::arm_neon_vld4:
3885 case Intrinsic::arm_neon_vst1:
3886 case Intrinsic::arm_neon_vst2:
3887 case Intrinsic::arm_neon_vst3:
3888 case Intrinsic::arm_neon_vst4:
3889 case Intrinsic::arm_neon_vld2lane:
3890 case Intrinsic::arm_neon_vld3lane:
3891 case Intrinsic::arm_neon_vld4lane:
3892 case Intrinsic::aarch64_neon_vld1x2:
3893 case Intrinsic::aarch64_neon_vld1x3:
3894 case Intrinsic::aarch64_neon_vld1x4:
3895 case Intrinsic::aarch64_neon_vst1x2:
3896 case Intrinsic::aarch64_neon_vst1x3:
3897 case Intrinsic::aarch64_neon_vst1x4:
3898 case Intrinsic::arm_neon_vst2lane:
3899 case Intrinsic::arm_neon_vst3lane:
3900 case Intrinsic::arm_neon_vst4lane:
3901 return CombineBaseUpdate(N, DCI);
3910 AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
3911 VT = VT.getScalarType();
3916 switch (VT.getSimpleVT().SimpleTy) {
3930 // Check whether a Build Vector could be presented as Shuffle Vector. If yes,
3931 // try to call LowerVECTOR_SHUFFLE to lower it.
3932 bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
3933 SDValue &Res) const {
3935 EVT VT = Op.getValueType();
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned V0NumElts = 0;
3941 // Check if all elements are extracted from less than 3 vectors.
3942 for (unsigned i = 0; i < NumElts; ++i) {
3943 SDValue Elt = Op.getOperand(i);
3944 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
3947 if (V0.getNode() == 0) {
3948 V0 = Elt.getOperand(0);
3949 V0NumElts = V0.getValueType().getVectorNumElements();
3951 if (Elt.getOperand(0) == V0) {
3952 Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue());
3954 } else if (V1.getNode() == 0) {
3955 V1 = Elt.getOperand(0);
3957 if (Elt.getOperand(0) == V1) {
3958 unsigned Lane = cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue();
3959 Mask[i] = (Lane + V0NumElts);
3966 if (!V1.getNode() && V0NumElts == NumElts * 2) {
3967 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
3968 DAG.getConstant(NumElts, MVT::i64));
3969 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
3970 DAG.getConstant(0, MVT::i64));
3971 V0NumElts = V0.getValueType().getVectorNumElements();
3974 if (V1.getNode() && NumElts == V0NumElts &&
3975 V0NumElts == V1.getValueType().getVectorNumElements()) {
3976 SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
3977 if(Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
3980 Res = LowerVECTOR_SHUFFLE(Shuffle, DAG);
3986 // If this is a case we can't handle, return null and let the default
3987 // expansion code take care of it.
3989 AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3990 const AArch64Subtarget *ST) const {
3992 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3994 EVT VT = Op.getValueType();
3996 APInt SplatBits, SplatUndef;
3997 unsigned SplatBitSize;
4000 unsigned UseNeonMov = VT.getSizeInBits() >= 64;
4002 // Note we favor lowering MOVI over MVNI.
4003 // This has implications on the definition of patterns in TableGen to select
4004 // BIC immediate instructions but not ORR immediate instructions.
4005 // If this lowering order is changed, TableGen patterns for BIC immediate and
4006 // ORR immediate instructions have to be updated.
4008 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4009 if (SplatBitSize <= 64) {
4010 // First attempt to use vector immediate-form MOVI
4013 unsigned OpCmode = 0;
4015 if (isNeonModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
4016 SplatBitSize, DAG, VT.is128BitVector(),
4017 Neon_Mov_Imm, NeonMovVT, Imm, OpCmode)) {
4018 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4019 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4021 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4022 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MOVIMM, DL, NeonMovVT,
4023 ImmVal, OpCmodeVal);
4024 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4028 // Then attempt to use vector immediate-form MVNI
4029 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4030 if (isNeonModifiedImm(NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
4031 DAG, VT.is128BitVector(), Neon_Mvn_Imm, NeonMovVT,
4033 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4034 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4035 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4036 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MVNIMM, DL, NeonMovVT,
4037 ImmVal, OpCmodeVal);
4038 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4042 // Attempt to use vector immediate-form FMOV
4043 if (((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) ||
4044 (VT == MVT::v2f64 && SplatBitSize == 64)) {
4046 SplatBitSize == 32 ? APFloat::IEEEsingle : APFloat::IEEEdouble,
4049 if (A64Imms::isFPImm(RealVal, ImmVal)) {
4050 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4051 return DAG.getNode(AArch64ISD::NEON_FMOVIMM, DL, VT, Val);
4057 unsigned NumElts = VT.getVectorNumElements();
4058 bool isOnlyLowElement = true;
4059 bool usesOnlyOneValue = true;
4060 bool hasDominantValue = false;
4061 bool isConstant = true;
4063 // Map of the number of times a particular SDValue appears in the
4065 DenseMap<SDValue, unsigned> ValueCounts;
4067 for (unsigned i = 0; i < NumElts; ++i) {
4068 SDValue V = Op.getOperand(i);
4069 if (V.getOpcode() == ISD::UNDEF)
4072 isOnlyLowElement = false;
4073 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4076 ValueCounts.insert(std::make_pair(V, 0));
4077 unsigned &Count = ValueCounts[V];
4079 // Is this value dominant? (takes up more than half of the lanes)
4080 if (++Count > (NumElts / 2)) {
4081 hasDominantValue = true;
4085 if (ValueCounts.size() != 1)
4086 usesOnlyOneValue = false;
4087 if (!Value.getNode() && ValueCounts.size() > 0)
4088 Value = ValueCounts.begin()->first;
4090 if (ValueCounts.size() == 0)
4091 return DAG.getUNDEF(VT);
4093 if (isOnlyLowElement)
4094 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4096 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4097 if (hasDominantValue && EltSize <= 64) {
4098 // Use VDUP for non-constant splats.
4102 // If we are DUPing a value that comes directly from a vector, we could
4103 // just use DUPLANE. We can only do this if the lane being extracted
4104 // is at a constant index, as the DUP from lane instructions only have
4105 // constant-index forms.
4107 // If there is a TRUNCATE between EXTRACT_VECTOR_ELT and DUP, we can
4108 // remove TRUNCATE for DUPLANE by apdating the source vector to
4109 // appropriate vector type and lane index.
4111 // FIXME: for now we have v1i8, v1i16, v1i32 legal vector types, if they
4112 // are not legal any more, no need to check the type size in bits should
4113 // be large than 64.
4115 if (Value->getOpcode() == ISD::TRUNCATE)
4116 V = Value->getOperand(0);
4117 if (V->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4118 isa<ConstantSDNode>(V->getOperand(1)) &&
4119 V->getOperand(0).getValueType().getSizeInBits() >= 64) {
4121 // If the element size of source vector is larger than DUPLANE
4122 // element size, we can do transformation by,
4123 // 1) bitcasting source register to smaller element vector
4124 // 2) mutiplying the lane index by SrcEltSize/ResEltSize
4125 // For example, we can lower
4126 // "v8i16 vdup_lane(v4i32, 1)"
4128 // "v8i16 vdup_lane(v8i16 bitcast(v4i32), 2)".
4129 SDValue SrcVec = V->getOperand(0);
4130 unsigned SrcEltSize =
4131 SrcVec.getValueType().getVectorElementType().getSizeInBits();
4132 unsigned ResEltSize = VT.getVectorElementType().getSizeInBits();
4133 if (SrcEltSize > ResEltSize) {
4134 assert((SrcEltSize % ResEltSize == 0) && "Invalid element size");
4136 unsigned SrcSize = SrcVec.getValueType().getSizeInBits();
4137 unsigned ResSize = VT.getSizeInBits();
4139 if (SrcSize > ResSize) {
4140 assert((SrcSize % ResSize == 0) && "Invalid vector size");
4142 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4143 SrcSize / ResEltSize);
4144 BitCast = DAG.getNode(ISD::BITCAST, DL, CastVT, SrcVec);
4146 assert((SrcSize == ResSize) && "Invalid vector size of source vec");
4147 BitCast = DAG.getNode(ISD::BITCAST, DL, VT, SrcVec);
4150 unsigned LaneIdx = V->getConstantOperandVal(1);
4152 DAG.getConstant((SrcEltSize / ResEltSize) * LaneIdx, MVT::i64);
4153 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, BitCast, Lane);
4155 assert((SrcEltSize == ResEltSize) &&
4156 "Invalid element size of source vec");
4157 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, V->getOperand(0),
4161 N = DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4163 if (!usesOnlyOneValue) {
4164 // The dominant value was splatted as 'N', but we now have to insert
4165 // all differing elements.
4166 for (unsigned I = 0; I < NumElts; ++I) {
4167 if (Op.getOperand(I) == Value)
4169 SmallVector<SDValue, 3> Ops;
4171 Ops.push_back(Op.getOperand(I));
4172 Ops.push_back(DAG.getConstant(I, MVT::i64));
4173 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
4178 if (usesOnlyOneValue && isConstant) {
4179 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4182 // If all elements are constants and the case above didn't get hit, fall back
4183 // to the default expansion, which will generate a load from the constant
4188 // Try to lower this in lowering ShuffleVector way.
4190 if (isKnownShuffleVector(Op, DAG, Shuf))
4193 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4194 // know the default expansion would otherwise fall back on something even
4195 // worse. For a vector with one or two non-undef values, that's
4196 // scalar_to_vector for the elements followed by a shuffle (provided the
4197 // shuffle is valid for the target) and materialization element by element
4198 // on the stack followed by a load for everything else.
4199 if (!isConstant && !usesOnlyOneValue) {
4200 SDValue Vec = DAG.getUNDEF(VT);
4201 for (unsigned i = 0 ; i < NumElts; ++i) {
4202 SDValue V = Op.getOperand(i);
4203 if (V.getOpcode() == ISD::UNDEF)
4205 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
4206 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, LaneIdx);
4213 /// isREVMask - Check if a vector shuffle corresponds to a REV
4214 /// instruction with the specified blocksize. (The order of the elements
4215 /// within each block of the vector is reversed.)
4216 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4217 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4218 "Only possible block sizes for REV are: 16, 32, 64");
4220 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4224 unsigned NumElts = VT.getVectorNumElements();
4225 unsigned BlockElts = M[0] + 1;
4226 // If the first shuffle index is UNDEF, be optimistic.
4228 BlockElts = BlockSize / EltSz;
4230 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4233 for (unsigned i = 0; i < NumElts; ++i) {
4235 continue; // ignore UNDEF indices
4236 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4243 // isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
4245 static unsigned isPermuteMask(ArrayRef<int> M, EVT VT) {
4246 unsigned NumElts = VT.getVectorNumElements();
4250 bool ismatch = true;
4253 for (unsigned i = 0; i < NumElts; ++i) {
4254 if ((unsigned)M[i] != i * 2) {
4260 return AArch64ISD::NEON_UZP1;
4264 for (unsigned i = 0; i < NumElts; ++i) {
4265 if ((unsigned)M[i] != i * 2 + 1) {
4271 return AArch64ISD::NEON_UZP2;
4275 for (unsigned i = 0; i < NumElts; ++i) {
4276 if ((unsigned)M[i] != i / 2 + NumElts * (i % 2)) {
4282 return AArch64ISD::NEON_ZIP1;
4286 for (unsigned i = 0; i < NumElts; ++i) {
4287 if ((unsigned)M[i] != (NumElts + i) / 2 + NumElts * (i % 2)) {
4293 return AArch64ISD::NEON_ZIP2;
4297 for (unsigned i = 0; i < NumElts; ++i) {
4298 if ((unsigned)M[i] != i + (NumElts - 1) * (i % 2)) {
4304 return AArch64ISD::NEON_TRN1;
4308 for (unsigned i = 0; i < NumElts; ++i) {
4309 if ((unsigned)M[i] != 1 + i + (NumElts - 1) * (i % 2)) {
4315 return AArch64ISD::NEON_TRN2;
4321 AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4322 SelectionDAG &DAG) const {
4323 SDValue V1 = Op.getOperand(0);
4324 SDValue V2 = Op.getOperand(1);
4326 EVT VT = Op.getValueType();
4327 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4329 // Convert shuffles that are directly supported on NEON to target-specific
4330 // DAG nodes, instead of keeping them as shuffles and matching them again
4331 // during code selection. This is more efficient and avoids the possibility
4332 // of inconsistencies between legalization and selection.
4333 ArrayRef<int> ShuffleMask = SVN->getMask();
4335 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4339 if (isREVMask(ShuffleMask, VT, 64))
4340 return DAG.getNode(AArch64ISD::NEON_REV64, dl, VT, V1);
4341 if (isREVMask(ShuffleMask, VT, 32))
4342 return DAG.getNode(AArch64ISD::NEON_REV32, dl, VT, V1);
4343 if (isREVMask(ShuffleMask, VT, 16))
4344 return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1);
4346 unsigned ISDNo = isPermuteMask(ShuffleMask, VT);
4348 return DAG.getNode(ISDNo, dl, VT, V1, V2);
4350 // If the element of shuffle mask are all the same constant, we can
4351 // transform it into either NEON_VDUP or NEON_VDUPLANE
4352 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4353 int Lane = SVN->getSplatIndex();
4354 // If this is undef splat, generate it via "just" vdup, if possible.
4355 if (Lane == -1) Lane = 0;
4357 // Test if V1 is a SCALAR_TO_VECTOR.
4358 if (V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4359 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(0));
4361 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR.
4362 if (V1.getOpcode() == ISD::BUILD_VECTOR) {
4363 bool IsScalarToVector = true;
4364 for (unsigned i = 0, e = V1.getNumOperands(); i != e; ++i)
4365 if (V1.getOperand(i).getOpcode() != ISD::UNDEF &&
4366 i != (unsigned)Lane) {
4367 IsScalarToVector = false;
4370 if (IsScalarToVector)
4371 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT,
4372 V1.getOperand(Lane));
4375 // Test if V1 is a EXTRACT_SUBVECTOR.
4376 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4377 int ExtLane = cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4378 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
4379 DAG.getConstant(Lane + ExtLane, MVT::i64));
4381 // Test if V1 is a CONCAT_VECTORS.
4382 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
4383 V1.getOperand(1).getOpcode() == ISD::UNDEF) {
4384 SDValue Op0 = V1.getOperand(0);
4385 assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
4386 "Invalid vector lane access");
4387 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
4388 DAG.getConstant(Lane, MVT::i64));
4391 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,
4392 DAG.getConstant(Lane, MVT::i64));
4395 int Length = ShuffleMask.size();
4396 int V1EltNum = V1.getValueType().getVectorNumElements();
4398 // If the number of v1 elements is the same as the number of shuffle mask
4399 // element and the shuffle masks are sequential values, we can transform
4400 // it into NEON_VEXTRACT.
4401 if (V1EltNum == Length) {
4402 // Check if the shuffle mask is sequential.
4403 bool IsSequential = true;
4404 int CurMask = ShuffleMask[0];
4405 for (int I = 0; I < Length; ++I) {
4406 if (ShuffleMask[I] != CurMask) {
4407 IsSequential = false;
4413 assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect");
4414 unsigned VecSize = EltSize * V1EltNum;
4415 unsigned Index = (EltSize/8) * ShuffleMask[0];
4416 if (VecSize == 64 || VecSize == 128)
4417 return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2,
4418 DAG.getConstant(Index, MVT::i64));
4422 // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert
4423 // by element from V2 to V1 .
4424 // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a
4425 // better choice to be inserted than V1 as less insert needed, so we count
4426 // element to be inserted for both V1 and V2, and select less one as insert
4429 // Collect elements need to be inserted and their index.
4430 SmallVector<int, 8> NV1Elt;
4431 SmallVector<int, 8> N1Index;
4432 SmallVector<int, 8> NV2Elt;
4433 SmallVector<int, 8> N2Index;
4434 for (int I = 0; I != Length; ++I) {
4435 if (ShuffleMask[I] != I) {
4436 NV1Elt.push_back(ShuffleMask[I]);
4437 N1Index.push_back(I);
4440 for (int I = 0; I != Length; ++I) {
4441 if (ShuffleMask[I] != (I + V1EltNum)) {
4442 NV2Elt.push_back(ShuffleMask[I]);
4443 N2Index.push_back(I);
4447 // Decide which to be inserted. If all lanes mismatch, neither V1 nor V2
4448 // will be inserted.
4450 SmallVector<int, 8> InsMasks = NV1Elt;
4451 SmallVector<int, 8> InsIndex = N1Index;
4452 if ((int)NV1Elt.size() != Length || (int)NV2Elt.size() != Length) {
4453 if (NV1Elt.size() > NV2Elt.size()) {
4459 InsV = DAG.getNode(ISD::UNDEF, dl, VT);
4462 for (int I = 0, E = InsMasks.size(); I != E; ++I) {
4464 int Mask = InsMasks[I];
4465 if (Mask >= V1EltNum) {
4469 // Any value type smaller than i32 is illegal in AArch64, and this lower
4470 // function is called after legalize pass, so we need to legalize
4473 if (VT.getVectorElementType().isFloatingPoint())
4474 EltVT = (EltSize == 64) ? MVT::f64 : MVT::f32;
4476 EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32;
4479 ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
4480 DAG.getConstant(Mask, MVT::i64));
4481 InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV,
4482 DAG.getConstant(InsIndex[I], MVT::i64));
4488 AArch64TargetLowering::ConstraintType
4489 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4490 if (Constraint.size() == 1) {
4491 switch (Constraint[0]) {
4493 case 'w': // An FP/SIMD vector register
4494 return C_RegisterClass;
4495 case 'I': // Constant that can be used with an ADD instruction
4496 case 'J': // Constant that can be used with a SUB instruction
4497 case 'K': // Constant that can be used with a 32-bit logical instruction
4498 case 'L': // Constant that can be used with a 64-bit logical instruction
4499 case 'M': // Constant that can be used as a 32-bit MOV immediate
4500 case 'N': // Constant that can be used as a 64-bit MOV immediate
4501 case 'Y': // Floating point constant zero
4502 case 'Z': // Integer constant zero
4504 case 'Q': // A memory reference with base register and no offset
4506 case 'S': // A symbolic address
4511 // FIXME: Ump, Utf, Usa, Ush
4512 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
4513 // whatever they may be
4514 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
4515 // Usa: An absolute symbolic address
4516 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
4517 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
4518 && Constraint != "Ush" && "Unimplemented constraints");
4520 return TargetLowering::getConstraintType(Constraint);
4523 TargetLowering::ConstraintWeight
4524 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
4525 const char *Constraint) const {
4527 llvm_unreachable("Constraint weight unimplemented");
4531 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4532 std::string &Constraint,
4533 std::vector<SDValue> &Ops,
4534 SelectionDAG &DAG) const {
4535 SDValue Result(0, 0);
4537 // Only length 1 constraints are C_Other.
4538 if (Constraint.size() != 1) return;
4540 // Only C_Other constraints get lowered like this. That means constants for us
4541 // so return early if there's no hope the constraint can be lowered.
4543 switch(Constraint[0]) {
4545 case 'I': case 'J': case 'K': case 'L':
4546 case 'M': case 'N': case 'Z': {
4547 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4551 uint64_t CVal = C->getZExtValue();
4554 switch (Constraint[0]) {
4556 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
4557 // is a peculiarly useless SUB constraint.
4558 llvm_unreachable("Unimplemented C_Other constraint");
4564 if (A64Imms::isLogicalImm(32, CVal, Bits))
4568 if (A64Imms::isLogicalImm(64, CVal, Bits))
4577 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4581 // An absolute symbolic address or label reference.
4582 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4583 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
4584 GA->getValueType(0));
4585 } else if (const BlockAddressSDNode *BA
4586 = dyn_cast<BlockAddressSDNode>(Op)) {
4587 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
4588 BA->getValueType(0));
4589 } else if (const ExternalSymbolSDNode *ES
4590 = dyn_cast<ExternalSymbolSDNode>(Op)) {
4591 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
4592 ES->getValueType(0));
4598 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
4599 if (CFP->isExactlyValue(0.0)) {
4600 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
4607 if (Result.getNode()) {
4608 Ops.push_back(Result);
4612 // It's an unknown constraint for us. Let generic code have a go.
4613 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4616 std::pair<unsigned, const TargetRegisterClass*>
4617 AArch64TargetLowering::getRegForInlineAsmConstraint(
4618 const std::string &Constraint,
4620 if (Constraint.size() == 1) {
4621 switch (Constraint[0]) {
4623 if (VT.getSizeInBits() <= 32)
4624 return std::make_pair(0U, &AArch64::GPR32RegClass);
4625 else if (VT == MVT::i64)
4626 return std::make_pair(0U, &AArch64::GPR64RegClass);
4630 return std::make_pair(0U, &AArch64::FPR16RegClass);
4631 else if (VT == MVT::f32)
4632 return std::make_pair(0U, &AArch64::FPR32RegClass);
4633 else if (VT.getSizeInBits() == 64)
4634 return std::make_pair(0U, &AArch64::FPR64RegClass);
4635 else if (VT.getSizeInBits() == 128)
4636 return std::make_pair(0U, &AArch64::FPR128RegClass);
4641 // Use the default implementation in TargetLowering to convert the register
4642 // constraint into a member of a register class.
4643 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4646 /// Represent NEON load and store intrinsics as MemIntrinsicNodes.
4647 /// The associated MachineMemOperands record the alignment specified
4648 /// in the intrinsic calls.
4649 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
4651 unsigned Intrinsic) const {
4652 switch (Intrinsic) {
4653 case Intrinsic::arm_neon_vld1:
4654 case Intrinsic::arm_neon_vld2:
4655 case Intrinsic::arm_neon_vld3:
4656 case Intrinsic::arm_neon_vld4:
4657 case Intrinsic::aarch64_neon_vld1x2:
4658 case Intrinsic::aarch64_neon_vld1x3:
4659 case Intrinsic::aarch64_neon_vld1x4:
4660 case Intrinsic::arm_neon_vld2lane:
4661 case Intrinsic::arm_neon_vld3lane:
4662 case Intrinsic::arm_neon_vld4lane: {
4663 Info.opc = ISD::INTRINSIC_W_CHAIN;
4664 // Conservatively set memVT to the entire set of vectors loaded.
4665 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
4666 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
4667 Info.ptrVal = I.getArgOperand(0);
4669 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
4670 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
4671 Info.vol = false; // volatile loads with NEON intrinsics not supported
4672 Info.readMem = true;
4673 Info.writeMem = false;
4676 case Intrinsic::arm_neon_vst1:
4677 case Intrinsic::arm_neon_vst2:
4678 case Intrinsic::arm_neon_vst3:
4679 case Intrinsic::arm_neon_vst4:
4680 case Intrinsic::aarch64_neon_vst1x2:
4681 case Intrinsic::aarch64_neon_vst1x3:
4682 case Intrinsic::aarch64_neon_vst1x4:
4683 case Intrinsic::arm_neon_vst2lane:
4684 case Intrinsic::arm_neon_vst3lane:
4685 case Intrinsic::arm_neon_vst4lane: {
4686 Info.opc = ISD::INTRINSIC_VOID;
4687 // Conservatively set memVT to the entire set of vectors stored.
4688 unsigned NumElts = 0;
4689 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
4690 Type *ArgTy = I.getArgOperand(ArgI)->getType();
4691 if (!ArgTy->isVectorTy())
4693 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
4695 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
4696 Info.ptrVal = I.getArgOperand(0);
4698 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
4699 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
4700 Info.vol = false; // volatile stores with NEON intrinsics not supported
4701 Info.readMem = false;
4702 Info.writeMem = true;