1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
43 // Place holder until extr generation is tested fully.
45 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
46 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
50 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
51 cl::desc("Allow AArch64 SLI/SRI formation"),
54 // FIXME: The necessary dtprel relocations don't seem to be supported
55 // well in the GNU bfd and gold linkers at the moment. Therefore, by
56 // default, for now, fall back to GeneralDynamic code generation.
57 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
58 "aarch64-elf-ldtls-generation", cl::Hidden,
59 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
62 /// Value type used for condition codes.
63 static const MVT MVT_CC = MVT::i32;
65 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
66 const AArch64Subtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
70 // we have to make something up. Arbitrarily, choose ZeroOrOne.
71 setBooleanContents(ZeroOrOneBooleanContent);
72 // When comparing vectors the result sets the different elements in the
73 // vector to all-one or all-zero.
74 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
78 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
80 if (Subtarget->hasFPARMv8()) {
81 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
82 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
83 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
84 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
87 if (Subtarget->hasNEON()) {
88 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
89 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
90 // Someone set us up the NEON.
91 addDRTypeForNEON(MVT::v2f32);
92 addDRTypeForNEON(MVT::v8i8);
93 addDRTypeForNEON(MVT::v4i16);
94 addDRTypeForNEON(MVT::v2i32);
95 addDRTypeForNEON(MVT::v1i64);
96 addDRTypeForNEON(MVT::v1f64);
97 addDRTypeForNEON(MVT::v4f16);
99 addQRTypeForNEON(MVT::v4f32);
100 addQRTypeForNEON(MVT::v2f64);
101 addQRTypeForNEON(MVT::v16i8);
102 addQRTypeForNEON(MVT::v8i16);
103 addQRTypeForNEON(MVT::v4i32);
104 addQRTypeForNEON(MVT::v2i64);
105 addQRTypeForNEON(MVT::v8f16);
108 // Compute derived properties from the register classes
109 computeRegisterProperties(Subtarget->getRegisterInfo());
111 // Provide all sorts of operation actions
112 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
120 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
121 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
122 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
123 setOperationAction(ISD::SELECT, MVT::i32, Custom);
124 setOperationAction(ISD::SELECT, MVT::i64, Custom);
125 setOperationAction(ISD::SELECT, MVT::f32, Custom);
126 setOperationAction(ISD::SELECT, MVT::f64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
131 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
135 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
136 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Expand);
139 setOperationAction(ISD::FREM, MVT::f64, Expand);
140 setOperationAction(ISD::FREM, MVT::f80, Expand);
142 // Custom lowering hooks are needed for XOR
143 // to fold it into CSINC/CSINV.
144 setOperationAction(ISD::XOR, MVT::i32, Custom);
145 setOperationAction(ISD::XOR, MVT::i64, Custom);
147 // Virtually no operation on f128 is legal, but LLVM can't expand them when
148 // there's a valid register class, so we need custom operations in most cases.
149 setOperationAction(ISD::FABS, MVT::f128, Expand);
150 setOperationAction(ISD::FADD, MVT::f128, Custom);
151 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
152 setOperationAction(ISD::FCOS, MVT::f128, Expand);
153 setOperationAction(ISD::FDIV, MVT::f128, Custom);
154 setOperationAction(ISD::FMA, MVT::f128, Expand);
155 setOperationAction(ISD::FMUL, MVT::f128, Custom);
156 setOperationAction(ISD::FNEG, MVT::f128, Expand);
157 setOperationAction(ISD::FPOW, MVT::f128, Expand);
158 setOperationAction(ISD::FREM, MVT::f128, Expand);
159 setOperationAction(ISD::FRINT, MVT::f128, Expand);
160 setOperationAction(ISD::FSIN, MVT::f128, Expand);
161 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
162 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
163 setOperationAction(ISD::FSUB, MVT::f128, Custom);
164 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
166 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
167 setOperationAction(ISD::SELECT, MVT::f128, Custom);
168 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
169 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
171 // Lowering for many of the conversions is actually specified by the non-f128
172 // type. The LowerXXX function will be trivial when f128 isn't involved.
173 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
177 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
178 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
182 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
183 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
184 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
186 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
188 // Variable arguments.
189 setOperationAction(ISD::VASTART, MVT::Other, Custom);
190 setOperationAction(ISD::VAARG, MVT::Other, Custom);
191 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
192 setOperationAction(ISD::VAEND, MVT::Other, Expand);
194 // Variable-sized objects.
195 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
196 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
197 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
199 // Exception handling.
200 // FIXME: These are guesses. Has this been defined yet?
201 setExceptionPointerRegister(AArch64::X0);
202 setExceptionSelectorRegister(AArch64::X1);
204 // Constant pool entries
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
208 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
210 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
211 setOperationAction(ISD::ADDC, MVT::i32, Custom);
212 setOperationAction(ISD::ADDE, MVT::i32, Custom);
213 setOperationAction(ISD::SUBC, MVT::i32, Custom);
214 setOperationAction(ISD::SUBE, MVT::i32, Custom);
215 setOperationAction(ISD::ADDC, MVT::i64, Custom);
216 setOperationAction(ISD::ADDE, MVT::i64, Custom);
217 setOperationAction(ISD::SUBC, MVT::i64, Custom);
218 setOperationAction(ISD::SUBE, MVT::i64, Custom);
220 // AArch64 lacks both left-rotate and popcount instructions.
221 setOperationAction(ISD::ROTL, MVT::i32, Expand);
222 setOperationAction(ISD::ROTL, MVT::i64, Expand);
224 // AArch64 doesn't have {U|S}MUL_LOHI.
225 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
226 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
229 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
230 // counterparts, which AArch64 supports directly.
231 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
232 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
233 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
234 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
236 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
237 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
239 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
240 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
241 setOperationAction(ISD::SREM, MVT::i32, Expand);
242 setOperationAction(ISD::SREM, MVT::i64, Expand);
243 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
244 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
245 setOperationAction(ISD::UREM, MVT::i32, Expand);
246 setOperationAction(ISD::UREM, MVT::i64, Expand);
248 // Custom lower Add/Sub/Mul with overflow.
249 setOperationAction(ISD::SADDO, MVT::i32, Custom);
250 setOperationAction(ISD::SADDO, MVT::i64, Custom);
251 setOperationAction(ISD::UADDO, MVT::i32, Custom);
252 setOperationAction(ISD::UADDO, MVT::i64, Custom);
253 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
254 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
255 setOperationAction(ISD::USUBO, MVT::i32, Custom);
256 setOperationAction(ISD::USUBO, MVT::i64, Custom);
257 setOperationAction(ISD::SMULO, MVT::i32, Custom);
258 setOperationAction(ISD::SMULO, MVT::i64, Custom);
259 setOperationAction(ISD::UMULO, MVT::i32, Custom);
260 setOperationAction(ISD::UMULO, MVT::i64, Custom);
262 setOperationAction(ISD::FSIN, MVT::f32, Expand);
263 setOperationAction(ISD::FSIN, MVT::f64, Expand);
264 setOperationAction(ISD::FCOS, MVT::f32, Expand);
265 setOperationAction(ISD::FCOS, MVT::f64, Expand);
266 setOperationAction(ISD::FPOW, MVT::f32, Expand);
267 setOperationAction(ISD::FPOW, MVT::f64, Expand);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
269 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
271 // f16 is a storage-only type, always promote it to f32.
272 setOperationAction(ISD::SETCC, MVT::f16, Promote);
273 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
274 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
275 setOperationAction(ISD::SELECT, MVT::f16, Promote);
276 setOperationAction(ISD::FADD, MVT::f16, Promote);
277 setOperationAction(ISD::FSUB, MVT::f16, Promote);
278 setOperationAction(ISD::FMUL, MVT::f16, Promote);
279 setOperationAction(ISD::FDIV, MVT::f16, Promote);
280 setOperationAction(ISD::FREM, MVT::f16, Promote);
281 setOperationAction(ISD::FMA, MVT::f16, Promote);
282 setOperationAction(ISD::FNEG, MVT::f16, Promote);
283 setOperationAction(ISD::FABS, MVT::f16, Promote);
284 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
285 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
286 setOperationAction(ISD::FCOS, MVT::f16, Promote);
287 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
288 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
289 setOperationAction(ISD::FPOW, MVT::f16, Promote);
290 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
291 setOperationAction(ISD::FRINT, MVT::f16, Promote);
292 setOperationAction(ISD::FSIN, MVT::f16, Promote);
293 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
294 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
295 setOperationAction(ISD::FEXP, MVT::f16, Promote);
296 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
297 setOperationAction(ISD::FLOG, MVT::f16, Promote);
298 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
299 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
300 setOperationAction(ISD::FROUND, MVT::f16, Promote);
301 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
302 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
303 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
305 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
307 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
308 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
309 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
310 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
311 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
312 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
313 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
314 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
315 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
316 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
317 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
318 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
320 // Expand all other v4f16 operations.
321 // FIXME: We could generate better code by promoting some operations to
323 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
324 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
325 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
326 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
327 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
328 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
329 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
330 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
331 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
332 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
333 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
334 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
335 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
336 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
337 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
338 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
339 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
340 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
341 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
342 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
343 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
344 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
345 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
346 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
347 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
348 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
351 // v8f16 is also a storage-only type, so expand it.
352 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
353 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
354 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
355 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
356 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
357 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
358 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
359 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
360 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
361 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
362 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
363 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
364 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
365 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
366 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
367 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
368 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
371 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
372 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
373 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
374 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
375 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
376 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
377 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
378 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
379 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
380 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
381 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
382 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
384 // AArch64 has implementations of a lot of rounding-like FP operations.
385 for (MVT Ty : {MVT::f32, MVT::f64}) {
386 setOperationAction(ISD::FFLOOR, Ty, Legal);
387 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
388 setOperationAction(ISD::FCEIL, Ty, Legal);
389 setOperationAction(ISD::FRINT, Ty, Legal);
390 setOperationAction(ISD::FTRUNC, Ty, Legal);
391 setOperationAction(ISD::FROUND, Ty, Legal);
394 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
396 if (Subtarget->isTargetMachO()) {
397 // For iOS, we don't want to the normal expansion of a libcall to
398 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
400 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
401 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
403 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
404 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
407 // Make floating-point constants legal for the large code model, so they don't
408 // become loads from the constant pool.
409 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
410 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
411 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
414 // AArch64 does not have floating-point extending loads, i1 sign-extending
415 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
416 for (MVT VT : MVT::fp_valuetypes()) {
417 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
418 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
419 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
420 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
422 for (MVT VT : MVT::integer_valuetypes())
423 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
425 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
426 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
427 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
428 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
429 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
430 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
431 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
433 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
434 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
436 // Indexed loads and stores are supported.
437 for (unsigned im = (unsigned)ISD::PRE_INC;
438 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
439 setIndexedLoadAction(im, MVT::i8, Legal);
440 setIndexedLoadAction(im, MVT::i16, Legal);
441 setIndexedLoadAction(im, MVT::i32, Legal);
442 setIndexedLoadAction(im, MVT::i64, Legal);
443 setIndexedLoadAction(im, MVT::f64, Legal);
444 setIndexedLoadAction(im, MVT::f32, Legal);
445 setIndexedStoreAction(im, MVT::i8, Legal);
446 setIndexedStoreAction(im, MVT::i16, Legal);
447 setIndexedStoreAction(im, MVT::i32, Legal);
448 setIndexedStoreAction(im, MVT::i64, Legal);
449 setIndexedStoreAction(im, MVT::f64, Legal);
450 setIndexedStoreAction(im, MVT::f32, Legal);
454 setOperationAction(ISD::TRAP, MVT::Other, Legal);
456 // We combine OR nodes for bitfield operations.
457 setTargetDAGCombine(ISD::OR);
459 // Vector add and sub nodes may conceal a high-half opportunity.
460 // Also, try to fold ADD into CSINC/CSINV..
461 setTargetDAGCombine(ISD::ADD);
462 setTargetDAGCombine(ISD::SUB);
464 setTargetDAGCombine(ISD::XOR);
465 setTargetDAGCombine(ISD::SINT_TO_FP);
466 setTargetDAGCombine(ISD::UINT_TO_FP);
468 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
470 setTargetDAGCombine(ISD::ANY_EXTEND);
471 setTargetDAGCombine(ISD::ZERO_EXTEND);
472 setTargetDAGCombine(ISD::SIGN_EXTEND);
473 setTargetDAGCombine(ISD::BITCAST);
474 setTargetDAGCombine(ISD::CONCAT_VECTORS);
475 setTargetDAGCombine(ISD::STORE);
477 setTargetDAGCombine(ISD::MUL);
479 setTargetDAGCombine(ISD::SELECT);
480 setTargetDAGCombine(ISD::VSELECT);
481 setTargetDAGCombine(ISD::SELECT_CC);
483 setTargetDAGCombine(ISD::INTRINSIC_VOID);
484 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
485 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
487 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
488 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
489 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
491 setStackPointerRegisterToSaveRestore(AArch64::SP);
493 setSchedulingPreference(Sched::Hybrid);
496 MaskAndBranchFoldingIsLegal = true;
497 EnableExtLdPromotion = true;
499 setMinFunctionAlignment(2);
501 setHasExtractBitsInsn(true);
503 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
505 if (Subtarget->hasNEON()) {
506 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
507 // silliness like this:
508 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
509 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
510 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
512 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
513 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
514 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
515 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
516 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
517 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
518 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
519 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
520 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
521 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
522 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
523 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
524 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
525 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
526 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
527 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
528 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
529 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
530 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
531 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
532 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
534 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
535 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
536 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
537 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
538 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
540 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
542 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
543 // elements smaller than i32, so promote the input to i32 first.
544 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
545 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
546 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
547 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
548 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
549 // -> v8f16 conversions.
550 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
551 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
552 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
553 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
554 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
555 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
556 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
557 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
559 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
560 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
561 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
562 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
564 // AArch64 doesn't have MUL.2d:
565 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
566 // Custom handling for some quad-vector types to detect MULL.
567 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
568 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
569 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
571 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
572 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
573 // Likewise, narrowing and extending vector loads/stores aren't handled
575 for (MVT VT : MVT::vector_valuetypes()) {
576 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
578 setOperationAction(ISD::MULHS, VT, Expand);
579 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
580 setOperationAction(ISD::MULHU, VT, Expand);
581 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
583 setOperationAction(ISD::BSWAP, VT, Expand);
585 for (MVT InnerVT : MVT::vector_valuetypes()) {
586 setTruncStoreAction(VT, InnerVT, Expand);
587 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
588 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
589 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
593 // AArch64 has implementations of a lot of rounding-like FP operations.
594 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
595 setOperationAction(ISD::FFLOOR, Ty, Legal);
596 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
597 setOperationAction(ISD::FCEIL, Ty, Legal);
598 setOperationAction(ISD::FRINT, Ty, Legal);
599 setOperationAction(ISD::FTRUNC, Ty, Legal);
600 setOperationAction(ISD::FROUND, Ty, Legal);
604 // Prefer likely predicted branches to selects on out-of-order cores.
605 if (Subtarget->isCortexA57())
606 PredictableSelectIsExpensive = true;
609 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
610 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
611 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
612 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
614 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
615 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
616 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
617 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
618 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
620 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
621 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
624 // Mark vector float intrinsics as expand.
625 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
626 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
627 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
633 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
637 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
638 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
639 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
640 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
641 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
642 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
643 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
644 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
645 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
646 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
647 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
648 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
650 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
651 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
652 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
653 for (MVT InnerVT : MVT::all_valuetypes())
654 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
656 // CNT supports only B element sizes.
657 if (VT != MVT::v8i8 && VT != MVT::v16i8)
658 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
660 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
661 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
662 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
663 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
664 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
666 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
667 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
669 // [SU][MIN|MAX] and [SU]ABSDIFF are available for all NEON types apart from
671 if (!VT.isFloatingPoint() &&
672 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
673 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
674 ISD::SABSDIFF, ISD::UABSDIFF})
675 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
677 if (Subtarget->isLittleEndian()) {
678 for (unsigned im = (unsigned)ISD::PRE_INC;
679 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
680 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
681 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
686 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
687 addRegisterClass(VT, &AArch64::FPR64RegClass);
688 addTypeForNEON(VT, MVT::v2i32);
691 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
692 addRegisterClass(VT, &AArch64::FPR128RegClass);
693 addTypeForNEON(VT, MVT::v4i32);
696 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
700 return VT.changeVectorElementTypeToInteger();
703 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
704 /// Mask are known to be either zero or one and return them in the
705 /// KnownZero/KnownOne bitsets.
706 void AArch64TargetLowering::computeKnownBitsForTargetNode(
707 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
708 const SelectionDAG &DAG, unsigned Depth) const {
709 switch (Op.getOpcode()) {
712 case AArch64ISD::CSEL: {
713 APInt KnownZero2, KnownOne2;
714 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
715 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
716 KnownZero &= KnownZero2;
717 KnownOne &= KnownOne2;
720 case ISD::INTRINSIC_W_CHAIN: {
721 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
722 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
725 case Intrinsic::aarch64_ldaxr:
726 case Intrinsic::aarch64_ldxr: {
727 unsigned BitWidth = KnownOne.getBitWidth();
728 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
729 unsigned MemBits = VT.getScalarType().getSizeInBits();
730 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
736 case ISD::INTRINSIC_WO_CHAIN:
737 case ISD::INTRINSIC_VOID: {
738 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
742 case Intrinsic::aarch64_neon_umaxv:
743 case Intrinsic::aarch64_neon_uminv: {
744 // Figure out the datatype of the vector operand. The UMINV instruction
745 // will zero extend the result, so we can mark as known zero all the
746 // bits larger than the element datatype. 32-bit or larget doesn't need
747 // this as those are legal types and will be handled by isel directly.
748 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
749 unsigned BitWidth = KnownZero.getBitWidth();
750 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
751 assert(BitWidth >= 8 && "Unexpected width!");
752 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
754 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
755 assert(BitWidth >= 16 && "Unexpected width!");
756 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
766 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
771 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
775 if (Subtarget->requiresStrictAlign())
777 // FIXME: True for Cyclone, but not necessary others.
784 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
785 const TargetLibraryInfo *libInfo) const {
786 return AArch64::createFastISel(funcInfo, libInfo);
789 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
790 switch ((AArch64ISD::NodeType)Opcode) {
791 case AArch64ISD::FIRST_NUMBER: break;
792 case AArch64ISD::CALL: return "AArch64ISD::CALL";
793 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
794 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
795 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
796 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
797 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
798 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
799 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
800 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
801 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
802 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
803 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
804 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
805 case AArch64ISD::ADC: return "AArch64ISD::ADC";
806 case AArch64ISD::SBC: return "AArch64ISD::SBC";
807 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
808 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
809 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
810 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
811 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
812 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
813 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
814 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
815 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
816 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
817 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
818 case AArch64ISD::DUP: return "AArch64ISD::DUP";
819 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
820 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
821 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
822 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
823 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
824 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
825 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
826 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
827 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
828 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
829 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
830 case AArch64ISD::BICi: return "AArch64ISD::BICi";
831 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
832 case AArch64ISD::BSL: return "AArch64ISD::BSL";
833 case AArch64ISD::NEG: return "AArch64ISD::NEG";
834 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
835 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
836 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
837 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
838 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
839 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
840 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
841 case AArch64ISD::REV16: return "AArch64ISD::REV16";
842 case AArch64ISD::REV32: return "AArch64ISD::REV32";
843 case AArch64ISD::REV64: return "AArch64ISD::REV64";
844 case AArch64ISD::EXT: return "AArch64ISD::EXT";
845 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
846 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
847 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
848 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
849 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
850 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
851 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
852 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
853 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
854 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
855 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
856 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
857 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
858 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
859 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
860 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
861 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
862 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
863 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
864 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
865 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
866 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
867 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
868 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
869 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
870 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
871 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
872 case AArch64ISD::NOT: return "AArch64ISD::NOT";
873 case AArch64ISD::BIT: return "AArch64ISD::BIT";
874 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
875 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
876 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
877 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
878 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
879 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
880 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
881 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
882 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
883 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
884 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
885 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
886 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
887 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
888 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
889 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
890 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
891 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
892 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
893 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
894 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
895 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
896 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
897 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
898 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
899 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
900 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
901 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
902 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
903 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
904 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
905 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
906 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
907 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
908 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
909 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
910 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
911 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
912 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
913 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
919 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
920 MachineBasicBlock *MBB) const {
921 // We materialise the F128CSEL pseudo-instruction as some control flow and a
925 // [... previous instrs leading to comparison ...]
931 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
933 MachineFunction *MF = MBB->getParent();
934 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
935 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
936 DebugLoc DL = MI->getDebugLoc();
937 MachineFunction::iterator It = MBB;
940 unsigned DestReg = MI->getOperand(0).getReg();
941 unsigned IfTrueReg = MI->getOperand(1).getReg();
942 unsigned IfFalseReg = MI->getOperand(2).getReg();
943 unsigned CondCode = MI->getOperand(3).getImm();
944 bool NZCVKilled = MI->getOperand(4).isKill();
946 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
947 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
948 MF->insert(It, TrueBB);
949 MF->insert(It, EndBB);
951 // Transfer rest of current basic-block to EndBB
952 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
954 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
956 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
957 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
958 MBB->addSuccessor(TrueBB);
959 MBB->addSuccessor(EndBB);
961 // TrueBB falls through to the end.
962 TrueBB->addSuccessor(EndBB);
965 TrueBB->addLiveIn(AArch64::NZCV);
966 EndBB->addLiveIn(AArch64::NZCV);
969 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
975 MI->eraseFromParent();
980 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
981 MachineBasicBlock *BB) const {
982 switch (MI->getOpcode()) {
987 llvm_unreachable("Unexpected instruction for custom inserter!");
989 case AArch64::F128CSEL:
990 return EmitF128CSEL(MI, BB);
992 case TargetOpcode::STACKMAP:
993 case TargetOpcode::PATCHPOINT:
994 return emitPatchPoint(MI, BB);
998 //===----------------------------------------------------------------------===//
999 // AArch64 Lowering private implementation.
1000 //===----------------------------------------------------------------------===//
1002 //===----------------------------------------------------------------------===//
1004 //===----------------------------------------------------------------------===//
1006 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1008 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1011 llvm_unreachable("Unknown condition code!");
1013 return AArch64CC::NE;
1015 return AArch64CC::EQ;
1017 return AArch64CC::GT;
1019 return AArch64CC::GE;
1021 return AArch64CC::LT;
1023 return AArch64CC::LE;
1025 return AArch64CC::HI;
1027 return AArch64CC::HS;
1029 return AArch64CC::LO;
1031 return AArch64CC::LS;
1035 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1036 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1037 AArch64CC::CondCode &CondCode,
1038 AArch64CC::CondCode &CondCode2) {
1039 CondCode2 = AArch64CC::AL;
1042 llvm_unreachable("Unknown FP condition!");
1045 CondCode = AArch64CC::EQ;
1049 CondCode = AArch64CC::GT;
1053 CondCode = AArch64CC::GE;
1056 CondCode = AArch64CC::MI;
1059 CondCode = AArch64CC::LS;
1062 CondCode = AArch64CC::MI;
1063 CondCode2 = AArch64CC::GT;
1066 CondCode = AArch64CC::VC;
1069 CondCode = AArch64CC::VS;
1072 CondCode = AArch64CC::EQ;
1073 CondCode2 = AArch64CC::VS;
1076 CondCode = AArch64CC::HI;
1079 CondCode = AArch64CC::PL;
1083 CondCode = AArch64CC::LT;
1087 CondCode = AArch64CC::LE;
1091 CondCode = AArch64CC::NE;
1096 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1097 /// CC usable with the vector instructions. Fewer operations are available
1098 /// without a real NZCV register, so we have to use less efficient combinations
1099 /// to get the same effect.
1100 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1101 AArch64CC::CondCode &CondCode,
1102 AArch64CC::CondCode &CondCode2,
1107 // Mostly the scalar mappings work fine.
1108 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1111 Invert = true; // Fallthrough
1113 CondCode = AArch64CC::MI;
1114 CondCode2 = AArch64CC::GE;
1121 // All of the compare-mask comparisons are ordered, but we can switch
1122 // between the two by a double inversion. E.g. ULE == !OGT.
1124 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1129 static bool isLegalArithImmed(uint64_t C) {
1130 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1131 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1134 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1135 SDLoc dl, SelectionDAG &DAG) {
1136 EVT VT = LHS.getValueType();
1138 if (VT.isFloatingPoint())
1139 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1141 // The CMP instruction is just an alias for SUBS, and representing it as
1142 // SUBS means that it's possible to get CSE with subtract operations.
1143 // A later phase can perform the optimization of setting the destination
1144 // register to WZR/XZR if it ends up being unused.
1145 unsigned Opcode = AArch64ISD::SUBS;
1147 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1148 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1149 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1150 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1151 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1152 // can be set differently by this operation. It comes down to whether
1153 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1154 // everything is fine. If not then the optimization is wrong. Thus general
1155 // comparisons are only valid if op2 != 0.
1157 // So, finally, the only LLVM-native comparisons that don't mention C and V
1158 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1159 // the absence of information about op2.
1160 Opcode = AArch64ISD::ADDS;
1161 RHS = RHS.getOperand(1);
1162 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1163 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1164 !isUnsignedIntSetCC(CC)) {
1165 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1166 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1167 // of the signed comparisons.
1168 Opcode = AArch64ISD::ANDS;
1169 RHS = LHS.getOperand(1);
1170 LHS = LHS.getOperand(0);
1173 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1177 /// \defgroup AArch64CCMP CMP;CCMP matching
1179 /// These functions deal with the formation of CMP;CCMP;... sequences.
1180 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1181 /// a comparison. They set the NZCV flags to a predefined value if their
1182 /// predicate is false. This allows to express arbitrary conjunctions, for
1183 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1186 /// ccmp B, inv(CB), CA
1187 /// check for CB flags
1189 /// In general we can create code for arbitrary "... (and (and A B) C)"
1190 /// sequences. We can also implement some "or" expressions, because "(or A B)"
1191 /// is equivalent to "not (and (not A) (not B))" and we can implement some
1192 /// negation operations:
1193 /// We can negate the results of a single comparison by inverting the flags
1194 /// used when the predicate fails and inverting the flags tested in the next
1195 /// instruction; We can also negate the results of the whole previous
1196 /// conditional compare sequence by inverting the flags tested in the next
1197 /// instruction. However there is no way to negate the result of a partial
1200 /// Therefore on encountering an "or" expression we can negate the subtree on
1201 /// one side and have to be able to push the negate to the leafs of the subtree
1202 /// on the other side (see also the comments in code). As complete example:
1203 /// "or (or (setCA (cmp A)) (setCB (cmp B)))
1204 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1205 /// is transformed to
1206 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1207 /// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1208 /// and implemented as:
1210 /// ccmp D, inv(CD), CC
1211 /// ccmp A, CA, inv(CD)
1212 /// ccmp B, CB, inv(CA)
1213 /// check for CB flags
1214 /// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1215 /// by conditional compare sequences.
1218 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1219 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1220 ISD::CondCode CC, SDValue CCOp,
1221 SDValue Condition, unsigned NZCV,
1222 SDLoc DL, SelectionDAG &DAG) {
1223 unsigned Opcode = 0;
1224 if (LHS.getValueType().isFloatingPoint())
1225 Opcode = AArch64ISD::FCCMP;
1226 else if (RHS.getOpcode() == ISD::SUB) {
1227 SDValue SubOp0 = RHS.getOperand(0);
1228 if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
1229 if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1230 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1231 Opcode = AArch64ISD::CCMN;
1232 RHS = RHS.getOperand(1);
1236 Opcode = AArch64ISD::CCMP;
1238 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1239 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1242 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1243 /// CanPushNegate is set to true if we can push a negate operation through
1244 /// the tree in a was that we are left with AND operations and negate operations
1245 /// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1246 /// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1247 /// brought into such a form.
1248 static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
1249 unsigned Depth = 0) {
1250 if (!Val.hasOneUse())
1252 unsigned Opcode = Val->getOpcode();
1253 if (Opcode == ISD::SETCC) {
1254 CanPushNegate = true;
1257 // Protect against stack overflow.
1260 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1261 SDValue O0 = Val->getOperand(0);
1262 SDValue O1 = Val->getOperand(1);
1263 bool CanPushNegateL;
1264 if (!isConjunctionDisjunctionTree(O0, CanPushNegateL, Depth+1))
1266 bool CanPushNegateR;
1267 if (!isConjunctionDisjunctionTree(O1, CanPushNegateR, Depth+1))
1269 // We cannot push a negate through an AND operation (it would become an OR),
1270 // we can however change a (not (or x y)) to (and (not x) (not y)) if we can
1271 // push the negate through the x/y subtrees.
1272 CanPushNegate = (Opcode == ISD::OR) && CanPushNegateL && CanPushNegateR;
1278 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1279 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1280 /// Tries to transform the given i1 producing node @p Val to a series compare
1281 /// and conditional compare operations. @returns an NZCV flags producing node
1282 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1283 /// transformation was not possible.
1284 /// On recursive invocations @p PushNegate may be set to true to have negation
1285 /// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1286 /// for the comparisons in the current subtree; @p Depth limits the search
1287 /// depth to avoid stack overflow.
1288 static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1289 AArch64CC::CondCode &OutCC, bool PushNegate = false,
1290 SDValue CCOp = SDValue(), AArch64CC::CondCode Predicate = AArch64CC::AL,
1291 unsigned Depth = 0) {
1292 // We're at a tree leaf, produce a conditional comparison operation.
1293 unsigned Opcode = Val->getOpcode();
1294 if (Opcode == ISD::SETCC) {
1295 SDValue LHS = Val->getOperand(0);
1296 SDValue RHS = Val->getOperand(1);
1297 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1298 bool isInteger = LHS.getValueType().isInteger();
1300 CC = getSetCCInverse(CC, isInteger);
1302 // Determine OutCC and handle FP special case.
1304 OutCC = changeIntCCToAArch64CC(CC);
1306 assert(LHS.getValueType().isFloatingPoint());
1307 AArch64CC::CondCode ExtraCC;
1308 changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
1309 // Surpisingly some floating point conditions can't be tested with a
1310 // single condition code. Construct an additional comparison in this case.
1311 // See comment below on how we deal with OR conditions.
1312 if (ExtraCC != AArch64CC::AL) {
1314 if (!CCOp.getNode())
1315 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1317 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1318 // Note that we want the inverse of ExtraCC, so NZCV is not inversed.
1319 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
1320 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
1324 Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
1325 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1329 // Produce a normal comparison if we are first in the chain
1330 if (!CCOp.getNode())
1331 return emitComparison(LHS, RHS, CC, DL, DAG);
1332 // Otherwise produce a ccmp.
1333 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1334 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1335 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1336 return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
1338 } else if (Opcode != ISD::AND && Opcode != ISD::OR)
1341 assert((Opcode == ISD::OR || !PushNegate)
1342 && "Can only push negate through OR operation");
1344 // Check if both sides can be transformed.
1345 SDValue LHS = Val->getOperand(0);
1346 SDValue RHS = Val->getOperand(1);
1347 bool CanPushNegateL;
1348 if (!isConjunctionDisjunctionTree(LHS, CanPushNegateL, Depth+1))
1350 bool CanPushNegateR;
1351 if (!isConjunctionDisjunctionTree(RHS, CanPushNegateR, Depth+1))
1354 // Do we need to negate our operands?
1355 bool NegateOperands = Opcode == ISD::OR;
1356 // We can negate the results of all previous operations by inverting the
1357 // predicate flags giving us a free negation for one side. For the other side
1358 // we need to be able to push the negation to the leafs of the tree.
1359 if (NegateOperands) {
1360 if (!CanPushNegateL && !CanPushNegateR)
1362 // Order the side where we can push the negate through to LHS.
1363 if (!CanPushNegateL && CanPushNegateR) {
1364 std::swap(LHS, RHS);
1365 CanPushNegateL = true;
1369 // Emit RHS. If we want to negate the tree we only need to push a negate
1370 // through if we are already in a PushNegate case, otherwise we can negate
1371 // the "flags to test" afterwards.
1372 AArch64CC::CondCode RHSCC;
1373 SDValue CmpR = emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, PushNegate,
1374 CCOp, Predicate, Depth+1);
1375 if (NegateOperands && !PushNegate)
1376 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1377 // Emit LHS. We must push the negate through if we need to negate it.
1378 SDValue CmpL = emitConjunctionDisjunctionTree(DAG, LHS, OutCC, NegateOperands,
1379 CmpR, RHSCC, Depth+1);
1380 // If we transformed an OR to and AND then we have to negate the result
1381 // (or absorb a PushNegate resulting in a double negation).
1382 if (Opcode == ISD::OR && !PushNegate)
1383 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1389 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1390 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1391 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1392 EVT VT = RHS.getValueType();
1393 uint64_t C = RHSC->getZExtValue();
1394 if (!isLegalArithImmed(C)) {
1395 // Constant does not fit, try adjusting it by one?
1401 if ((VT == MVT::i32 && C != 0x80000000 &&
1402 isLegalArithImmed((uint32_t)(C - 1))) ||
1403 (VT == MVT::i64 && C != 0x80000000ULL &&
1404 isLegalArithImmed(C - 1ULL))) {
1405 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1406 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1407 RHS = DAG.getConstant(C, dl, VT);
1412 if ((VT == MVT::i32 && C != 0 &&
1413 isLegalArithImmed((uint32_t)(C - 1))) ||
1414 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1415 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1416 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1417 RHS = DAG.getConstant(C, dl, VT);
1422 if ((VT == MVT::i32 && C != INT32_MAX &&
1423 isLegalArithImmed((uint32_t)(C + 1))) ||
1424 (VT == MVT::i64 && C != INT64_MAX &&
1425 isLegalArithImmed(C + 1ULL))) {
1426 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1427 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1428 RHS = DAG.getConstant(C, dl, VT);
1433 if ((VT == MVT::i32 && C != UINT32_MAX &&
1434 isLegalArithImmed((uint32_t)(C + 1))) ||
1435 (VT == MVT::i64 && C != UINT64_MAX &&
1436 isLegalArithImmed(C + 1ULL))) {
1437 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1438 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1439 RHS = DAG.getConstant(C, dl, VT);
1446 AArch64CC::CondCode AArch64CC;
1447 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1448 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1450 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1451 // For the i8 operand, the largest immediate is 255, so this can be easily
1452 // encoded in the compare instruction. For the i16 operand, however, the
1453 // largest immediate cannot be encoded in the compare.
1454 // Therefore, use a sign extending load and cmn to avoid materializing the
1455 // -1 constant. For example,
1457 // ldrh w0, [x0, #0]
1460 // ldrsh w0, [x0, #0]
1462 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1463 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1464 // ensure both the LHS and RHS are truely zero extended and to make sure the
1465 // transformation is profitable.
1466 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1467 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1468 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1469 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1470 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1471 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1473 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1474 DAG.getValueType(MVT::i16));
1475 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1476 RHS.getValueType()),
1478 AArch64CC = changeIntCCToAArch64CC(CC);
1482 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1483 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1484 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1485 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1491 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1492 AArch64CC = changeIntCCToAArch64CC(CC);
1494 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1498 static std::pair<SDValue, SDValue>
1499 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1500 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1501 "Unsupported value type");
1502 SDValue Value, Overflow;
1504 SDValue LHS = Op.getOperand(0);
1505 SDValue RHS = Op.getOperand(1);
1507 switch (Op.getOpcode()) {
1509 llvm_unreachable("Unknown overflow instruction!");
1511 Opc = AArch64ISD::ADDS;
1515 Opc = AArch64ISD::ADDS;
1519 Opc = AArch64ISD::SUBS;
1523 Opc = AArch64ISD::SUBS;
1526 // Multiply needs a little bit extra work.
1530 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1531 if (Op.getValueType() == MVT::i32) {
1532 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1533 // For a 32 bit multiply with overflow check we want the instruction
1534 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1535 // need to generate the following pattern:
1536 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1537 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1538 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1539 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1540 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1541 DAG.getConstant(0, DL, MVT::i64));
1542 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1543 // operation. We need to clear out the upper 32 bits, because we used a
1544 // widening multiply that wrote all 64 bits. In the end this should be a
1546 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1548 // The signed overflow check requires more than just a simple check for
1549 // any bit set in the upper 32 bits of the result. These bits could be
1550 // just the sign bits of a negative number. To perform the overflow
1551 // check we have to arithmetic shift right the 32nd bit of the result by
1552 // 31 bits. Then we compare the result to the upper 32 bits.
1553 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1554 DAG.getConstant(32, DL, MVT::i64));
1555 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1556 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1557 DAG.getConstant(31, DL, MVT::i64));
1558 // It is important that LowerBits is last, otherwise the arithmetic
1559 // shift will not be folded into the compare (SUBS).
1560 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1561 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1564 // The overflow check for unsigned multiply is easy. We only need to
1565 // check if any of the upper 32 bits are set. This can be done with a
1566 // CMP (shifted register). For that we need to generate the following
1568 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1569 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1570 DAG.getConstant(32, DL, MVT::i64));
1571 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1573 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1574 DAG.getConstant(0, DL, MVT::i64),
1575 UpperBits).getValue(1);
1579 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1580 // For the 64 bit multiply
1581 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1583 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1584 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1585 DAG.getConstant(63, DL, MVT::i64));
1586 // It is important that LowerBits is last, otherwise the arithmetic
1587 // shift will not be folded into the compare (SUBS).
1588 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1589 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1592 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1593 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1595 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1596 DAG.getConstant(0, DL, MVT::i64),
1597 UpperBits).getValue(1);
1604 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1606 // Emit the AArch64 operation with overflow check.
1607 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1608 Overflow = Value.getValue(1);
1610 return std::make_pair(Value, Overflow);
1613 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1614 RTLIB::Libcall Call) const {
1615 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1616 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1620 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1621 SDValue Sel = Op.getOperand(0);
1622 SDValue Other = Op.getOperand(1);
1624 // If neither operand is a SELECT_CC, give up.
1625 if (Sel.getOpcode() != ISD::SELECT_CC)
1626 std::swap(Sel, Other);
1627 if (Sel.getOpcode() != ISD::SELECT_CC)
1630 // The folding we want to perform is:
1631 // (xor x, (select_cc a, b, cc, 0, -1) )
1633 // (csel x, (xor x, -1), cc ...)
1635 // The latter will get matched to a CSINV instruction.
1637 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1638 SDValue LHS = Sel.getOperand(0);
1639 SDValue RHS = Sel.getOperand(1);
1640 SDValue TVal = Sel.getOperand(2);
1641 SDValue FVal = Sel.getOperand(3);
1644 // FIXME: This could be generalized to non-integer comparisons.
1645 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1648 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1649 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1651 // The values aren't constants, this isn't the pattern we're looking for.
1652 if (!CFVal || !CTVal)
1655 // We can commute the SELECT_CC by inverting the condition. This
1656 // might be needed to make this fit into a CSINV pattern.
1657 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1658 std::swap(TVal, FVal);
1659 std::swap(CTVal, CFVal);
1660 CC = ISD::getSetCCInverse(CC, true);
1663 // If the constants line up, perform the transform!
1664 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1666 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1669 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1670 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1672 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1679 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1680 EVT VT = Op.getValueType();
1682 // Let legalize expand this if it isn't a legal type yet.
1683 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1686 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1689 bool ExtraOp = false;
1690 switch (Op.getOpcode()) {
1692 llvm_unreachable("Invalid code");
1694 Opc = AArch64ISD::ADDS;
1697 Opc = AArch64ISD::SUBS;
1700 Opc = AArch64ISD::ADCS;
1704 Opc = AArch64ISD::SBCS;
1710 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1711 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1715 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1716 // Let legalize expand this if it isn't a legal type yet.
1717 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1721 AArch64CC::CondCode CC;
1722 // The actual operation that sets the overflow or carry flag.
1723 SDValue Value, Overflow;
1724 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1726 // We use 0 and 1 as false and true values.
1727 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1728 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1730 // We use an inverted condition, because the conditional select is inverted
1731 // too. This will allow it to be selected to a single instruction:
1732 // CSINC Wd, WZR, WZR, invert(cond).
1733 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1734 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1737 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1738 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1741 // Prefetch operands are:
1742 // 1: Address to prefetch
1744 // 3: int locality (0 = no locality ... 3 = extreme locality)
1745 // 4: bool isDataCache
1746 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1748 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1749 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1750 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1752 bool IsStream = !Locality;
1753 // When the locality number is set
1755 // The front-end should have filtered out the out-of-range values
1756 assert(Locality <= 3 && "Prefetch locality out-of-range");
1757 // The locality degree is the opposite of the cache speed.
1758 // Put the number the other way around.
1759 // The encoding starts at 0 for level 1
1760 Locality = 3 - Locality;
1763 // built the mask value encoding the expected behavior.
1764 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1765 (!IsData << 3) | // IsDataCache bit
1766 (Locality << 1) | // Cache level bits
1767 (unsigned)IsStream; // Stream bit
1768 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1769 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1772 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1773 SelectionDAG &DAG) const {
1774 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1777 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1779 return LowerF128Call(Op, DAG, LC);
1782 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1783 SelectionDAG &DAG) const {
1784 if (Op.getOperand(0).getValueType() != MVT::f128) {
1785 // It's legal except when f128 is involved
1790 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1792 // FP_ROUND node has a second operand indicating whether it is known to be
1793 // precise. That doesn't take part in the LibCall so we can't directly use
1795 SDValue SrcVal = Op.getOperand(0);
1796 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1797 /*isSigned*/ false, SDLoc(Op)).first;
1800 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1801 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1802 // Any additional optimization in this function should be recorded
1803 // in the cost tables.
1804 EVT InVT = Op.getOperand(0).getValueType();
1805 EVT VT = Op.getValueType();
1807 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1810 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1812 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1815 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1818 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1819 VT.getVectorNumElements());
1820 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1821 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1824 // Type changing conversions are illegal.
1828 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1829 SelectionDAG &DAG) const {
1830 if (Op.getOperand(0).getValueType().isVector())
1831 return LowerVectorFP_TO_INT(Op, DAG);
1833 // f16 conversions are promoted to f32.
1834 if (Op.getOperand(0).getValueType() == MVT::f16) {
1837 Op.getOpcode(), dl, Op.getValueType(),
1838 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1841 if (Op.getOperand(0).getValueType() != MVT::f128) {
1842 // It's legal except when f128 is involved
1847 if (Op.getOpcode() == ISD::FP_TO_SINT)
1848 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1850 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1852 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1853 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1857 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1858 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1859 // Any additional optimization in this function should be recorded
1860 // in the cost tables.
1861 EVT VT = Op.getValueType();
1863 SDValue In = Op.getOperand(0);
1864 EVT InVT = In.getValueType();
1866 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1868 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1869 InVT.getVectorNumElements());
1870 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1871 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1874 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1876 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1877 EVT CastVT = VT.changeVectorElementTypeToInteger();
1878 In = DAG.getNode(CastOpc, dl, CastVT, In);
1879 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1885 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1886 SelectionDAG &DAG) const {
1887 if (Op.getValueType().isVector())
1888 return LowerVectorINT_TO_FP(Op, DAG);
1890 // f16 conversions are promoted to f32.
1891 if (Op.getValueType() == MVT::f16) {
1894 ISD::FP_ROUND, dl, MVT::f16,
1895 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1896 DAG.getIntPtrConstant(0, dl));
1899 // i128 conversions are libcalls.
1900 if (Op.getOperand(0).getValueType() == MVT::i128)
1903 // Other conversions are legal, unless it's to the completely software-based
1905 if (Op.getValueType() != MVT::f128)
1909 if (Op.getOpcode() == ISD::SINT_TO_FP)
1910 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1912 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1914 return LowerF128Call(Op, DAG, LC);
1917 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1918 SelectionDAG &DAG) const {
1919 // For iOS, we want to call an alternative entry point: __sincos_stret,
1920 // which returns the values in two S / D registers.
1922 SDValue Arg = Op.getOperand(0);
1923 EVT ArgVT = Arg.getValueType();
1924 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1931 Entry.isSExt = false;
1932 Entry.isZExt = false;
1933 Args.push_back(Entry);
1935 const char *LibcallName =
1936 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1938 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
1940 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1941 TargetLowering::CallLoweringInfo CLI(DAG);
1942 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1943 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1945 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1946 return CallResult.first;
1949 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1950 if (Op.getValueType() != MVT::f16)
1953 assert(Op.getOperand(0).getValueType() == MVT::i16);
1956 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1957 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1959 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1960 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1964 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1965 if (OrigVT.getSizeInBits() >= 64)
1968 assert(OrigVT.isSimple() && "Expecting a simple value type");
1970 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1971 switch (OrigSimpleTy) {
1972 default: llvm_unreachable("Unexpected Vector Type");
1981 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1984 unsigned ExtOpcode) {
1985 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1986 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1987 // 64-bits we need to insert a new extension so that it will be 64-bits.
1988 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1989 if (OrigTy.getSizeInBits() >= 64)
1992 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1993 EVT NewVT = getExtensionTo64Bits(OrigTy);
1995 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1998 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2000 EVT VT = N->getValueType(0);
2002 if (N->getOpcode() != ISD::BUILD_VECTOR)
2005 for (const SDValue &Elt : N->op_values()) {
2006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2007 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2008 unsigned HalfSize = EltSize / 2;
2010 if (!isIntN(HalfSize, C->getSExtValue()))
2013 if (!isUIntN(HalfSize, C->getZExtValue()))
2024 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2025 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2026 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2027 N->getOperand(0)->getValueType(0),
2031 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2032 EVT VT = N->getValueType(0);
2034 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
2035 unsigned NumElts = VT.getVectorNumElements();
2036 MVT TruncVT = MVT::getIntegerVT(EltSize);
2037 SmallVector<SDValue, 8> Ops;
2038 for (unsigned i = 0; i != NumElts; ++i) {
2039 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2040 const APInt &CInt = C->getAPIntValue();
2041 // Element types smaller than 32 bits are not legal, so use i32 elements.
2042 // The values are implicitly truncated so sext vs. zext doesn't matter.
2043 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2045 return DAG.getNode(ISD::BUILD_VECTOR, dl,
2046 MVT::getVectorVT(TruncVT, NumElts), Ops);
2049 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2050 if (N->getOpcode() == ISD::SIGN_EXTEND)
2052 if (isExtendedBUILD_VECTOR(N, DAG, true))
2057 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2058 if (N->getOpcode() == ISD::ZERO_EXTEND)
2060 if (isExtendedBUILD_VECTOR(N, DAG, false))
2065 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2066 unsigned Opcode = N->getOpcode();
2067 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2068 SDNode *N0 = N->getOperand(0).getNode();
2069 SDNode *N1 = N->getOperand(1).getNode();
2070 return N0->hasOneUse() && N1->hasOneUse() &&
2071 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2076 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2077 unsigned Opcode = N->getOpcode();
2078 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2079 SDNode *N0 = N->getOperand(0).getNode();
2080 SDNode *N1 = N->getOperand(1).getNode();
2081 return N0->hasOneUse() && N1->hasOneUse() &&
2082 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2087 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2088 // Multiplications are only custom-lowered for 128-bit vectors so that
2089 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2090 EVT VT = Op.getValueType();
2091 assert(VT.is128BitVector() && VT.isInteger() &&
2092 "unexpected type for custom-lowering ISD::MUL");
2093 SDNode *N0 = Op.getOperand(0).getNode();
2094 SDNode *N1 = Op.getOperand(1).getNode();
2095 unsigned NewOpc = 0;
2097 bool isN0SExt = isSignExtended(N0, DAG);
2098 bool isN1SExt = isSignExtended(N1, DAG);
2099 if (isN0SExt && isN1SExt)
2100 NewOpc = AArch64ISD::SMULL;
2102 bool isN0ZExt = isZeroExtended(N0, DAG);
2103 bool isN1ZExt = isZeroExtended(N1, DAG);
2104 if (isN0ZExt && isN1ZExt)
2105 NewOpc = AArch64ISD::UMULL;
2106 else if (isN1SExt || isN1ZExt) {
2107 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2108 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2109 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2110 NewOpc = AArch64ISD::SMULL;
2112 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2113 NewOpc = AArch64ISD::UMULL;
2115 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2117 NewOpc = AArch64ISD::UMULL;
2123 if (VT == MVT::v2i64)
2124 // Fall through to expand this. It is not legal.
2127 // Other vector multiplications are legal.
2132 // Legalize to a S/UMULL instruction
2135 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2137 Op0 = skipExtensionForVectorMULL(N0, DAG);
2138 assert(Op0.getValueType().is64BitVector() &&
2139 Op1.getValueType().is64BitVector() &&
2140 "unexpected types for extended operands to VMULL");
2141 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2143 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2144 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2145 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2146 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2147 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2148 EVT Op1VT = Op1.getValueType();
2149 return DAG.getNode(N0->getOpcode(), DL, VT,
2150 DAG.getNode(NewOpc, DL, VT,
2151 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2152 DAG.getNode(NewOpc, DL, VT,
2153 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2156 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2157 SelectionDAG &DAG) const {
2158 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2161 default: return SDValue(); // Don't custom lower most intrinsics.
2162 case Intrinsic::aarch64_thread_pointer: {
2163 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2164 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2169 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2170 SelectionDAG &DAG) const {
2171 switch (Op.getOpcode()) {
2173 llvm_unreachable("unimplemented operand");
2176 return LowerBITCAST(Op, DAG);
2177 case ISD::GlobalAddress:
2178 return LowerGlobalAddress(Op, DAG);
2179 case ISD::GlobalTLSAddress:
2180 return LowerGlobalTLSAddress(Op, DAG);
2182 return LowerSETCC(Op, DAG);
2184 return LowerBR_CC(Op, DAG);
2186 return LowerSELECT(Op, DAG);
2187 case ISD::SELECT_CC:
2188 return LowerSELECT_CC(Op, DAG);
2189 case ISD::JumpTable:
2190 return LowerJumpTable(Op, DAG);
2191 case ISD::ConstantPool:
2192 return LowerConstantPool(Op, DAG);
2193 case ISD::BlockAddress:
2194 return LowerBlockAddress(Op, DAG);
2196 return LowerVASTART(Op, DAG);
2198 return LowerVACOPY(Op, DAG);
2200 return LowerVAARG(Op, DAG);
2205 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2212 return LowerXALUO(Op, DAG);
2214 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2216 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2218 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2220 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2222 return LowerFP_ROUND(Op, DAG);
2223 case ISD::FP_EXTEND:
2224 return LowerFP_EXTEND(Op, DAG);
2225 case ISD::FRAMEADDR:
2226 return LowerFRAMEADDR(Op, DAG);
2227 case ISD::RETURNADDR:
2228 return LowerRETURNADDR(Op, DAG);
2229 case ISD::INSERT_VECTOR_ELT:
2230 return LowerINSERT_VECTOR_ELT(Op, DAG);
2231 case ISD::EXTRACT_VECTOR_ELT:
2232 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2233 case ISD::BUILD_VECTOR:
2234 return LowerBUILD_VECTOR(Op, DAG);
2235 case ISD::VECTOR_SHUFFLE:
2236 return LowerVECTOR_SHUFFLE(Op, DAG);
2237 case ISD::EXTRACT_SUBVECTOR:
2238 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2242 return LowerVectorSRA_SRL_SHL(Op, DAG);
2243 case ISD::SHL_PARTS:
2244 return LowerShiftLeftParts(Op, DAG);
2245 case ISD::SRL_PARTS:
2246 case ISD::SRA_PARTS:
2247 return LowerShiftRightParts(Op, DAG);
2249 return LowerCTPOP(Op, DAG);
2250 case ISD::FCOPYSIGN:
2251 return LowerFCOPYSIGN(Op, DAG);
2253 return LowerVectorAND(Op, DAG);
2255 return LowerVectorOR(Op, DAG);
2257 return LowerXOR(Op, DAG);
2259 return LowerPREFETCH(Op, DAG);
2260 case ISD::SINT_TO_FP:
2261 case ISD::UINT_TO_FP:
2262 return LowerINT_TO_FP(Op, DAG);
2263 case ISD::FP_TO_SINT:
2264 case ISD::FP_TO_UINT:
2265 return LowerFP_TO_INT(Op, DAG);
2267 return LowerFSINCOS(Op, DAG);
2269 return LowerMUL(Op, DAG);
2270 case ISD::INTRINSIC_WO_CHAIN:
2271 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2275 /// getFunctionAlignment - Return the Log2 alignment of this function.
2276 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2280 //===----------------------------------------------------------------------===//
2281 // Calling Convention Implementation
2282 //===----------------------------------------------------------------------===//
2284 #include "AArch64GenCallingConv.inc"
2286 /// Selects the correct CCAssignFn for a given CallingConvention value.
2287 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2288 bool IsVarArg) const {
2291 llvm_unreachable("Unsupported calling convention.");
2292 case CallingConv::WebKit_JS:
2293 return CC_AArch64_WebKit_JS;
2294 case CallingConv::GHC:
2295 return CC_AArch64_GHC;
2296 case CallingConv::C:
2297 case CallingConv::Fast:
2298 if (!Subtarget->isTargetDarwin())
2299 return CC_AArch64_AAPCS;
2300 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2304 SDValue AArch64TargetLowering::LowerFormalArguments(
2305 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2306 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2307 SmallVectorImpl<SDValue> &InVals) const {
2308 MachineFunction &MF = DAG.getMachineFunction();
2309 MachineFrameInfo *MFI = MF.getFrameInfo();
2311 // Assign locations to all of the incoming arguments.
2312 SmallVector<CCValAssign, 16> ArgLocs;
2313 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2316 // At this point, Ins[].VT may already be promoted to i32. To correctly
2317 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2318 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2319 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2320 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2322 unsigned NumArgs = Ins.size();
2323 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2324 unsigned CurArgIdx = 0;
2325 for (unsigned i = 0; i != NumArgs; ++i) {
2326 MVT ValVT = Ins[i].VT;
2327 if (Ins[i].isOrigArg()) {
2328 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2329 CurArgIdx = Ins[i].getOrigArgIndex();
2331 // Get type of the original argument.
2332 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2333 /*AllowUnknown*/ true);
2334 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2335 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2336 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2338 else if (ActualMVT == MVT::i16)
2341 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2343 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2344 assert(!Res && "Call operand has unhandled type");
2347 assert(ArgLocs.size() == Ins.size());
2348 SmallVector<SDValue, 16> ArgValues;
2349 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2350 CCValAssign &VA = ArgLocs[i];
2352 if (Ins[i].Flags.isByVal()) {
2353 // Byval is used for HFAs in the PCS, but the system should work in a
2354 // non-compliant manner for larger structs.
2355 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2356 int Size = Ins[i].Flags.getByValSize();
2357 unsigned NumRegs = (Size + 7) / 8;
2359 // FIXME: This works on big-endian for composite byvals, which are the common
2360 // case. It should also work for fundamental types too.
2362 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2363 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2364 InVals.push_back(FrameIdxN);
2369 if (VA.isRegLoc()) {
2370 // Arguments stored in registers.
2371 EVT RegVT = VA.getLocVT();
2374 const TargetRegisterClass *RC;
2376 if (RegVT == MVT::i32)
2377 RC = &AArch64::GPR32RegClass;
2378 else if (RegVT == MVT::i64)
2379 RC = &AArch64::GPR64RegClass;
2380 else if (RegVT == MVT::f16)
2381 RC = &AArch64::FPR16RegClass;
2382 else if (RegVT == MVT::f32)
2383 RC = &AArch64::FPR32RegClass;
2384 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2385 RC = &AArch64::FPR64RegClass;
2386 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2387 RC = &AArch64::FPR128RegClass;
2389 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2391 // Transform the arguments in physical registers into virtual ones.
2392 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2393 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2395 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2396 // to 64 bits. Insert an assert[sz]ext to capture this, then
2397 // truncate to the right size.
2398 switch (VA.getLocInfo()) {
2400 llvm_unreachable("Unknown loc info!");
2401 case CCValAssign::Full:
2403 case CCValAssign::BCvt:
2404 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2406 case CCValAssign::AExt:
2407 case CCValAssign::SExt:
2408 case CCValAssign::ZExt:
2409 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2410 // nodes after our lowering.
2411 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2415 InVals.push_back(ArgValue);
2417 } else { // VA.isRegLoc()
2418 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2419 unsigned ArgOffset = VA.getLocMemOffset();
2420 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2422 uint32_t BEAlign = 0;
2423 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2424 !Ins[i].Flags.isInConsecutiveRegs())
2425 BEAlign = 8 - ArgSize;
2427 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2429 // Create load nodes to retrieve arguments from the stack.
2430 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2433 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2434 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2435 MVT MemVT = VA.getValVT();
2437 switch (VA.getLocInfo()) {
2440 case CCValAssign::BCvt:
2441 MemVT = VA.getLocVT();
2443 case CCValAssign::SExt:
2444 ExtType = ISD::SEXTLOAD;
2446 case CCValAssign::ZExt:
2447 ExtType = ISD::ZEXTLOAD;
2449 case CCValAssign::AExt:
2450 ExtType = ISD::EXTLOAD;
2454 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2455 MachinePointerInfo::getFixedStack(FI),
2456 MemVT, false, false, false, 0);
2458 InVals.push_back(ArgValue);
2464 if (!Subtarget->isTargetDarwin()) {
2465 // The AAPCS variadic function ABI is identical to the non-variadic
2466 // one. As a result there may be more arguments in registers and we should
2467 // save them for future reference.
2468 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2471 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2472 // This will point to the next argument passed via stack.
2473 unsigned StackOffset = CCInfo.getNextStackOffset();
2474 // We currently pass all varargs at 8-byte alignment.
2475 StackOffset = ((StackOffset + 7) & ~7);
2476 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2479 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2480 unsigned StackArgSize = CCInfo.getNextStackOffset();
2481 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2482 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2483 // This is a non-standard ABI so by fiat I say we're allowed to make full
2484 // use of the stack area to be popped, which must be aligned to 16 bytes in
2486 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2488 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2489 // a multiple of 16.
2490 FuncInfo->setArgumentStackToRestore(StackArgSize);
2492 // This realignment carries over to the available bytes below. Our own
2493 // callers will guarantee the space is free by giving an aligned value to
2496 // Even if we're not expected to free up the space, it's useful to know how
2497 // much is there while considering tail calls (because we can reuse it).
2498 FuncInfo->setBytesInStackArgArea(StackArgSize);
2503 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2504 SelectionDAG &DAG, SDLoc DL,
2505 SDValue &Chain) const {
2506 MachineFunction &MF = DAG.getMachineFunction();
2507 MachineFrameInfo *MFI = MF.getFrameInfo();
2508 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2509 auto PtrVT = getPointerTy(DAG.getDataLayout());
2511 SmallVector<SDValue, 8> MemOps;
2513 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2514 AArch64::X3, AArch64::X4, AArch64::X5,
2515 AArch64::X6, AArch64::X7 };
2516 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2517 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2519 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2521 if (GPRSaveSize != 0) {
2522 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2524 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2526 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2527 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2528 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2530 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2531 MachinePointerInfo::getStack(i * 8), false, false, 0);
2532 MemOps.push_back(Store);
2534 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2537 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2538 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2540 if (Subtarget->hasFPARMv8()) {
2541 static const MCPhysReg FPRArgRegs[] = {
2542 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2543 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2544 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2545 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2547 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2549 if (FPRSaveSize != 0) {
2550 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2552 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2554 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2555 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2556 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2559 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2560 MachinePointerInfo::getStack(i * 16), false, false, 0);
2561 MemOps.push_back(Store);
2562 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2563 DAG.getConstant(16, DL, PtrVT));
2566 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2567 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2570 if (!MemOps.empty()) {
2571 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2575 /// LowerCallResult - Lower the result values of a call into the
2576 /// appropriate copies out of appropriate physical registers.
2577 SDValue AArch64TargetLowering::LowerCallResult(
2578 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2579 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2580 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2581 SDValue ThisVal) const {
2582 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2583 ? RetCC_AArch64_WebKit_JS
2584 : RetCC_AArch64_AAPCS;
2585 // Assign locations to each value returned by this call.
2586 SmallVector<CCValAssign, 16> RVLocs;
2587 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2589 CCInfo.AnalyzeCallResult(Ins, RetCC);
2591 // Copy all of the result registers out of their specified physreg.
2592 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2593 CCValAssign VA = RVLocs[i];
2595 // Pass 'this' value directly from the argument to return value, to avoid
2596 // reg unit interference
2597 if (i == 0 && isThisReturn) {
2598 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2599 "unexpected return calling convention register assignment");
2600 InVals.push_back(ThisVal);
2605 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2606 Chain = Val.getValue(1);
2607 InFlag = Val.getValue(2);
2609 switch (VA.getLocInfo()) {
2611 llvm_unreachable("Unknown loc info!");
2612 case CCValAssign::Full:
2614 case CCValAssign::BCvt:
2615 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2619 InVals.push_back(Val);
2625 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2626 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2627 bool isCalleeStructRet, bool isCallerStructRet,
2628 const SmallVectorImpl<ISD::OutputArg> &Outs,
2629 const SmallVectorImpl<SDValue> &OutVals,
2630 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2631 // For CallingConv::C this function knows whether the ABI needs
2632 // changing. That's not true for other conventions so they will have to opt in
2634 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2637 const MachineFunction &MF = DAG.getMachineFunction();
2638 const Function *CallerF = MF.getFunction();
2639 CallingConv::ID CallerCC = CallerF->getCallingConv();
2640 bool CCMatch = CallerCC == CalleeCC;
2642 // Byval parameters hand the function a pointer directly into the stack area
2643 // we want to reuse during a tail call. Working around this *is* possible (see
2644 // X86) but less efficient and uglier in LowerCall.
2645 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2646 e = CallerF->arg_end();
2648 if (i->hasByValAttr())
2651 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2652 if (IsTailCallConvention(CalleeCC) && CCMatch)
2657 // Externally-defined functions with weak linkage should not be
2658 // tail-called on AArch64 when the OS does not support dynamic
2659 // pre-emption of symbols, as the AAELF spec requires normal calls
2660 // to undefined weak functions to be replaced with a NOP or jump to the
2661 // next instruction. The behaviour of branch instructions in this
2662 // situation (as used for tail calls) is implementation-defined, so we
2663 // cannot rely on the linker replacing the tail call with a return.
2664 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2665 const GlobalValue *GV = G->getGlobal();
2666 const Triple &TT = getTargetMachine().getTargetTriple();
2667 if (GV->hasExternalWeakLinkage() &&
2668 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2672 // Now we search for cases where we can use a tail call without changing the
2673 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2676 // I want anyone implementing a new calling convention to think long and hard
2677 // about this assert.
2678 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2679 "Unexpected variadic calling convention");
2681 if (isVarArg && !Outs.empty()) {
2682 // At least two cases here: if caller is fastcc then we can't have any
2683 // memory arguments (we'd be expected to clean up the stack afterwards). If
2684 // caller is C then we could potentially use its argument area.
2686 // FIXME: for now we take the most conservative of these in both cases:
2687 // disallow all variadic memory operands.
2688 SmallVector<CCValAssign, 16> ArgLocs;
2689 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2692 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2693 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2694 if (!ArgLocs[i].isRegLoc())
2698 // If the calling conventions do not match, then we'd better make sure the
2699 // results are returned in the same way as what the caller expects.
2701 SmallVector<CCValAssign, 16> RVLocs1;
2702 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2704 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2706 SmallVector<CCValAssign, 16> RVLocs2;
2707 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2709 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2711 if (RVLocs1.size() != RVLocs2.size())
2713 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2714 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2716 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2718 if (RVLocs1[i].isRegLoc()) {
2719 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2722 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2728 // Nothing more to check if the callee is taking no arguments
2732 SmallVector<CCValAssign, 16> ArgLocs;
2733 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2736 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2738 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2740 // If the stack arguments for this call would fit into our own save area then
2741 // the call can be made tail.
2742 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2745 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2747 MachineFrameInfo *MFI,
2748 int ClobberedFI) const {
2749 SmallVector<SDValue, 8> ArgChains;
2750 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2751 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2753 // Include the original chain at the beginning of the list. When this is
2754 // used by target LowerCall hooks, this helps legalize find the
2755 // CALLSEQ_BEGIN node.
2756 ArgChains.push_back(Chain);
2758 // Add a chain value for each stack argument corresponding
2759 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2760 UE = DAG.getEntryNode().getNode()->use_end();
2762 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2763 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2764 if (FI->getIndex() < 0) {
2765 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2766 int64_t InLastByte = InFirstByte;
2767 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2769 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2770 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2771 ArgChains.push_back(SDValue(L, 1));
2774 // Build a tokenfactor for all the chains.
2775 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2778 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2779 bool TailCallOpt) const {
2780 return CallCC == CallingConv::Fast && TailCallOpt;
2783 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2784 return CallCC == CallingConv::Fast;
2787 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2788 /// and add input and output parameter nodes.
2790 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2791 SmallVectorImpl<SDValue> &InVals) const {
2792 SelectionDAG &DAG = CLI.DAG;
2794 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2795 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2796 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2797 SDValue Chain = CLI.Chain;
2798 SDValue Callee = CLI.Callee;
2799 bool &IsTailCall = CLI.IsTailCall;
2800 CallingConv::ID CallConv = CLI.CallConv;
2801 bool IsVarArg = CLI.IsVarArg;
2803 MachineFunction &MF = DAG.getMachineFunction();
2804 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2805 bool IsThisReturn = false;
2807 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2808 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2809 bool IsSibCall = false;
2812 // Check if it's really possible to do a tail call.
2813 IsTailCall = isEligibleForTailCallOptimization(
2814 Callee, CallConv, IsVarArg, IsStructRet,
2815 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2816 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2817 report_fatal_error("failed to perform tail call elimination on a call "
2818 "site marked musttail");
2820 // A sibling call is one where we're under the usual C ABI and not planning
2821 // to change that but can still do a tail call:
2822 if (!TailCallOpt && IsTailCall)
2829 // Analyze operands of the call, assigning locations to each operand.
2830 SmallVector<CCValAssign, 16> ArgLocs;
2831 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2835 // Handle fixed and variable vector arguments differently.
2836 // Variable vector arguments always go into memory.
2837 unsigned NumArgs = Outs.size();
2839 for (unsigned i = 0; i != NumArgs; ++i) {
2840 MVT ArgVT = Outs[i].VT;
2841 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2842 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2843 /*IsVarArg=*/ !Outs[i].IsFixed);
2844 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2845 assert(!Res && "Call operand has unhandled type");
2849 // At this point, Outs[].VT may already be promoted to i32. To correctly
2850 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2851 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2852 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2853 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2855 unsigned NumArgs = Outs.size();
2856 for (unsigned i = 0; i != NumArgs; ++i) {
2857 MVT ValVT = Outs[i].VT;
2858 // Get type of the original argument.
2859 EVT ActualVT = getValueType(DAG.getDataLayout(),
2860 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2861 /*AllowUnknown*/ true);
2862 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2863 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2864 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2865 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2867 else if (ActualMVT == MVT::i16)
2870 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2871 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2872 assert(!Res && "Call operand has unhandled type");
2877 // Get a count of how many bytes are to be pushed on the stack.
2878 unsigned NumBytes = CCInfo.getNextStackOffset();
2881 // Since we're not changing the ABI to make this a tail call, the memory
2882 // operands are already available in the caller's incoming argument space.
2886 // FPDiff is the byte offset of the call's argument area from the callee's.
2887 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2888 // by this amount for a tail call. In a sibling call it must be 0 because the
2889 // caller will deallocate the entire stack and the callee still expects its
2890 // arguments to begin at SP+0. Completely unused for non-tail calls.
2893 if (IsTailCall && !IsSibCall) {
2894 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2896 // Since callee will pop argument stack as a tail call, we must keep the
2897 // popped size 16-byte aligned.
2898 NumBytes = RoundUpToAlignment(NumBytes, 16);
2900 // FPDiff will be negative if this tail call requires more space than we
2901 // would automatically have in our incoming argument space. Positive if we
2902 // can actually shrink the stack.
2903 FPDiff = NumReusableBytes - NumBytes;
2905 // The stack pointer must be 16-byte aligned at all times it's used for a
2906 // memory operation, which in practice means at *all* times and in
2907 // particular across call boundaries. Therefore our own arguments started at
2908 // a 16-byte aligned SP and the delta applied for the tail call should
2909 // satisfy the same constraint.
2910 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2913 // Adjust the stack pointer for the new arguments...
2914 // These operations are automatically eliminated by the prolog/epilog pass
2916 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2920 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
2921 getPointerTy(DAG.getDataLayout()));
2923 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2924 SmallVector<SDValue, 8> MemOpChains;
2925 auto PtrVT = getPointerTy(DAG.getDataLayout());
2927 // Walk the register/memloc assignments, inserting copies/loads.
2928 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2929 ++i, ++realArgIdx) {
2930 CCValAssign &VA = ArgLocs[i];
2931 SDValue Arg = OutVals[realArgIdx];
2932 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2934 // Promote the value if needed.
2935 switch (VA.getLocInfo()) {
2937 llvm_unreachable("Unknown loc info!");
2938 case CCValAssign::Full:
2940 case CCValAssign::SExt:
2941 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2943 case CCValAssign::ZExt:
2944 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2946 case CCValAssign::AExt:
2947 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2948 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2949 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2950 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2952 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2954 case CCValAssign::BCvt:
2955 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2957 case CCValAssign::FPExt:
2958 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2962 if (VA.isRegLoc()) {
2963 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2964 assert(VA.getLocVT() == MVT::i64 &&
2965 "unexpected calling convention register assignment");
2966 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2967 "unexpected use of 'returned'");
2968 IsThisReturn = true;
2970 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2972 assert(VA.isMemLoc());
2975 MachinePointerInfo DstInfo;
2977 // FIXME: This works on big-endian for composite byvals, which are the
2978 // common case. It should also work for fundamental types too.
2979 uint32_t BEAlign = 0;
2980 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2981 : VA.getValVT().getSizeInBits();
2982 OpSize = (OpSize + 7) / 8;
2983 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2984 !Flags.isInConsecutiveRegs()) {
2986 BEAlign = 8 - OpSize;
2988 unsigned LocMemOffset = VA.getLocMemOffset();
2989 int32_t Offset = LocMemOffset + BEAlign;
2990 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2991 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
2994 Offset = Offset + FPDiff;
2995 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2997 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2998 DstInfo = MachinePointerInfo::getFixedStack(FI);
3000 // Make sure any stack arguments overlapping with where we're storing
3001 // are loaded before this eventual operation. Otherwise they'll be
3003 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3005 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3007 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3008 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
3011 if (Outs[i].Flags.isByVal()) {
3013 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3014 SDValue Cpy = DAG.getMemcpy(
3015 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3016 /*isVol = */ false, /*AlwaysInline = */ false,
3017 /*isTailCall = */ false,
3018 DstInfo, MachinePointerInfo());
3020 MemOpChains.push_back(Cpy);
3022 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3023 // promoted to a legal register type i32, we should truncate Arg back to
3025 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3026 VA.getValVT() == MVT::i16)
3027 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3030 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
3031 MemOpChains.push_back(Store);
3036 if (!MemOpChains.empty())
3037 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3039 // Build a sequence of copy-to-reg nodes chained together with token chain
3040 // and flag operands which copy the outgoing args into the appropriate regs.
3042 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3043 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
3044 RegsToPass[i].second, InFlag);
3045 InFlag = Chain.getValue(1);
3048 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3049 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3050 // node so that legalize doesn't hack it.
3051 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3052 Subtarget->isTargetMachO()) {
3053 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3054 const GlobalValue *GV = G->getGlobal();
3055 bool InternalLinkage = GV->hasInternalLinkage();
3056 if (InternalLinkage)
3057 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3060 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3061 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3063 } else if (ExternalSymbolSDNode *S =
3064 dyn_cast<ExternalSymbolSDNode>(Callee)) {
3065 const char *Sym = S->getSymbol();
3066 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3067 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3069 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3070 const GlobalValue *GV = G->getGlobal();
3071 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3072 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3073 const char *Sym = S->getSymbol();
3074 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3077 // We don't usually want to end the call-sequence here because we would tidy
3078 // the frame up *after* the call, however in the ABI-changing tail-call case
3079 // we've carefully laid out the parameters so that when sp is reset they'll be
3080 // in the correct location.
3081 if (IsTailCall && !IsSibCall) {
3082 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3083 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3084 InFlag = Chain.getValue(1);
3087 std::vector<SDValue> Ops;
3088 Ops.push_back(Chain);
3089 Ops.push_back(Callee);
3092 // Each tail call may have to adjust the stack by a different amount, so
3093 // this information must travel along with the operation for eventual
3094 // consumption by emitEpilogue.
3095 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3098 // Add argument registers to the end of the list so that they are known live
3100 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3101 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3102 RegsToPass[i].second.getValueType()));
3104 // Add a register mask operand representing the call-preserved registers.
3105 const uint32_t *Mask;
3106 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3108 // For 'this' returns, use the X0-preserving mask if applicable
3109 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3111 IsThisReturn = false;
3112 Mask = TRI->getCallPreservedMask(MF, CallConv);
3115 Mask = TRI->getCallPreservedMask(MF, CallConv);
3117 assert(Mask && "Missing call preserved mask for calling convention");
3118 Ops.push_back(DAG.getRegisterMask(Mask));
3120 if (InFlag.getNode())
3121 Ops.push_back(InFlag);
3123 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3125 // If we're doing a tall call, use a TC_RETURN here rather than an
3126 // actual call instruction.
3128 MF.getFrameInfo()->setHasTailCall();
3129 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3132 // Returns a chain and a flag for retval copy to use.
3133 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3134 InFlag = Chain.getValue(1);
3136 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
3137 ? RoundUpToAlignment(NumBytes, 16)
3140 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3141 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3144 InFlag = Chain.getValue(1);
3146 // Handle result values, copying them out of physregs into vregs that we
3148 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3149 InVals, IsThisReturn,
3150 IsThisReturn ? OutVals[0] : SDValue());
3153 bool AArch64TargetLowering::CanLowerReturn(
3154 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3155 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3156 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3157 ? RetCC_AArch64_WebKit_JS
3158 : RetCC_AArch64_AAPCS;
3159 SmallVector<CCValAssign, 16> RVLocs;
3160 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3161 return CCInfo.CheckReturn(Outs, RetCC);
3165 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3167 const SmallVectorImpl<ISD::OutputArg> &Outs,
3168 const SmallVectorImpl<SDValue> &OutVals,
3169 SDLoc DL, SelectionDAG &DAG) const {
3170 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3171 ? RetCC_AArch64_WebKit_JS
3172 : RetCC_AArch64_AAPCS;
3173 SmallVector<CCValAssign, 16> RVLocs;
3174 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3176 CCInfo.AnalyzeReturn(Outs, RetCC);
3178 // Copy the result values into the output registers.
3180 SmallVector<SDValue, 4> RetOps(1, Chain);
3181 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3182 ++i, ++realRVLocIdx) {
3183 CCValAssign &VA = RVLocs[i];
3184 assert(VA.isRegLoc() && "Can only return in registers!");
3185 SDValue Arg = OutVals[realRVLocIdx];
3187 switch (VA.getLocInfo()) {
3189 llvm_unreachable("Unknown loc info!");
3190 case CCValAssign::Full:
3191 if (Outs[i].ArgVT == MVT::i1) {
3192 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3193 // value. This is strictly redundant on Darwin (which uses "zeroext
3194 // i1"), but will be optimised out before ISel.
3195 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3196 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3199 case CCValAssign::BCvt:
3200 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3204 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3205 Flag = Chain.getValue(1);
3206 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3209 RetOps[0] = Chain; // Update chain.
3211 // Add the flag if we have it.
3213 RetOps.push_back(Flag);
3215 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3218 //===----------------------------------------------------------------------===//
3219 // Other Lowering Code
3220 //===----------------------------------------------------------------------===//
3222 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3223 SelectionDAG &DAG) const {
3224 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3226 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3227 const GlobalValue *GV = GN->getGlobal();
3228 unsigned char OpFlags =
3229 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3231 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
3232 "unexpected offset in global node");
3234 // This also catched the large code model case for Darwin.
3235 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3236 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
3237 // FIXME: Once remat is capable of dealing with instructions with register
3238 // operands, expand this into two nodes instead of using a wrapper node.
3239 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3242 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
3243 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3244 "use of MO_CONSTPOOL only supported on small model");
3245 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3246 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3247 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3248 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3249 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3250 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3251 MachinePointerInfo::getConstantPool(),
3252 /*isVolatile=*/ false,
3253 /*isNonTemporal=*/ true,
3254 /*isInvariant=*/ true, 8);
3255 if (GN->getOffset() != 0)
3256 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3257 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3261 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3262 const unsigned char MO_NC = AArch64II::MO_NC;
3264 AArch64ISD::WrapperLarge, DL, PtrVT,
3265 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3266 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3267 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3268 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3270 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3271 // the only correct model on Darwin.
3272 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3273 OpFlags | AArch64II::MO_PAGE);
3274 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3275 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3277 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3278 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3282 /// \brief Convert a TLS address reference into the correct sequence of loads
3283 /// and calls to compute the variable's address (for Darwin, currently) and
3284 /// return an SDValue containing the final node.
3286 /// Darwin only has one TLS scheme which must be capable of dealing with the
3287 /// fully general situation, in the worst case. This means:
3288 /// + "extern __thread" declaration.
3289 /// + Defined in a possibly unknown dynamic library.
3291 /// The general system is that each __thread variable has a [3 x i64] descriptor
3292 /// which contains information used by the runtime to calculate the address. The
3293 /// only part of this the compiler needs to know about is the first xword, which
3294 /// contains a function pointer that must be called with the address of the
3295 /// entire descriptor in "x0".
3297 /// Since this descriptor may be in a different unit, in general even the
3298 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3300 /// adrp x0, _var@TLVPPAGE
3301 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3302 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3303 /// ; the function pointer
3304 /// blr x1 ; Uses descriptor address in x0
3305 /// ; Address of _var is now in x0.
3307 /// If the address of _var's descriptor *is* known to the linker, then it can
3308 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3309 /// a slight efficiency gain.
3311 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3312 SelectionDAG &DAG) const {
3313 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3316 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3317 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3320 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3321 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3323 // The first entry in the descriptor is a function pointer that we must call
3324 // to obtain the address of the variable.
3325 SDValue Chain = DAG.getEntryNode();
3326 SDValue FuncTLVGet =
3327 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3328 false, true, true, 8);
3329 Chain = FuncTLVGet.getValue(1);
3331 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3332 MFI->setAdjustsStack(true);
3334 // TLS calls preserve all registers except those that absolutely must be
3335 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3337 const uint32_t *Mask =
3338 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3340 // Finally, we can make the call. This is just a degenerate version of a
3341 // normal AArch64 call node: x0 takes the address of the descriptor, and
3342 // returns the address of the variable in this thread.
3343 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3345 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3346 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3347 DAG.getRegisterMask(Mask), Chain.getValue(1));
3348 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3351 /// When accessing thread-local variables under either the general-dynamic or
3352 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3353 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3354 /// is a function pointer to carry out the resolution.
3356 /// The sequence is:
3357 /// adrp x0, :tlsdesc:var
3358 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3359 /// add x0, x0, #:tlsdesc_lo12:var
3360 /// .tlsdesccall var
3362 /// (TPIDR_EL0 offset now in x0)
3364 /// The above sequence must be produced unscheduled, to enable the linker to
3365 /// optimize/relax this sequence.
3366 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3367 /// above sequence, and expanded really late in the compilation flow, to ensure
3368 /// the sequence is produced as per above.
3369 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3370 SelectionDAG &DAG) const {
3371 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3373 SDValue Chain = DAG.getEntryNode();
3374 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3376 SmallVector<SDValue, 2> Ops;
3377 Ops.push_back(Chain);
3378 Ops.push_back(SymAddr);
3380 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3381 SDValue Glue = Chain.getValue(1);
3383 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3387 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3388 SelectionDAG &DAG) const {
3389 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3390 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3391 "ELF TLS only supported in small memory model");
3392 // Different choices can be made for the maximum size of the TLS area for a
3393 // module. For the small address model, the default TLS size is 16MiB and the
3394 // maximum TLS size is 4GiB.
3395 // FIXME: add -mtls-size command line option and make it control the 16MiB
3396 // vs. 4GiB code sequence generation.
3397 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3399 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3401 if (DAG.getTarget().Options.EmulatedTLS)
3402 return LowerToTLSEmulatedModel(GA, DAG);
3404 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3405 if (Model == TLSModel::LocalDynamic)
3406 Model = TLSModel::GeneralDynamic;
3410 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3412 const GlobalValue *GV = GA->getGlobal();
3414 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3416 if (Model == TLSModel::LocalExec) {
3417 SDValue HiVar = DAG.getTargetGlobalAddress(
3418 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3419 SDValue LoVar = DAG.getTargetGlobalAddress(
3421 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3423 SDValue TPWithOff_lo =
3424 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3426 DAG.getTargetConstant(0, DL, MVT::i32)),
3429 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3431 DAG.getTargetConstant(0, DL, MVT::i32)),
3434 } else if (Model == TLSModel::InitialExec) {
3435 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3436 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3437 } else if (Model == TLSModel::LocalDynamic) {
3438 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3439 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3440 // the beginning of the module's TLS region, followed by a DTPREL offset
3443 // These accesses will need deduplicating if there's more than one.
3444 AArch64FunctionInfo *MFI =
3445 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3446 MFI->incNumLocalDynamicTLSAccesses();
3448 // The call needs a relocation too for linker relaxation. It doesn't make
3449 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3451 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3454 // Now we can calculate the offset from TPIDR_EL0 to this module's
3455 // thread-local area.
3456 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3458 // Now use :dtprel_whatever: operations to calculate this variable's offset
3459 // in its thread-storage area.
3460 SDValue HiVar = DAG.getTargetGlobalAddress(
3461 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3462 SDValue LoVar = DAG.getTargetGlobalAddress(
3463 GV, DL, MVT::i64, 0,
3464 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3466 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3467 DAG.getTargetConstant(0, DL, MVT::i32)),
3469 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3470 DAG.getTargetConstant(0, DL, MVT::i32)),
3472 } else if (Model == TLSModel::GeneralDynamic) {
3473 // The call needs a relocation too for linker relaxation. It doesn't make
3474 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3477 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3479 // Finally we can make a call to calculate the offset from tpidr_el0.
3480 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3482 llvm_unreachable("Unsupported ELF TLS access model");
3484 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3487 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3488 SelectionDAG &DAG) const {
3489 if (Subtarget->isTargetDarwin())
3490 return LowerDarwinGlobalTLSAddress(Op, DAG);
3491 else if (Subtarget->isTargetELF())
3492 return LowerELFGlobalTLSAddress(Op, DAG);
3494 llvm_unreachable("Unexpected platform trying to use TLS");
3496 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3497 SDValue Chain = Op.getOperand(0);
3498 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3499 SDValue LHS = Op.getOperand(2);
3500 SDValue RHS = Op.getOperand(3);
3501 SDValue Dest = Op.getOperand(4);
3504 // Handle f128 first, since lowering it will result in comparing the return
3505 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3506 // is expecting to deal with.
3507 if (LHS.getValueType() == MVT::f128) {
3508 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3510 // If softenSetCCOperands returned a scalar, we need to compare the result
3511 // against zero to select between true and false values.
3512 if (!RHS.getNode()) {
3513 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3518 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3520 unsigned Opc = LHS.getOpcode();
3521 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3522 cast<ConstantSDNode>(RHS)->isOne() &&
3523 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3524 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3525 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3526 "Unexpected condition code.");
3527 // Only lower legal XALUO ops.
3528 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3531 // The actual operation with overflow check.
3532 AArch64CC::CondCode OFCC;
3533 SDValue Value, Overflow;
3534 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3536 if (CC == ISD::SETNE)
3537 OFCC = getInvertedCondCode(OFCC);
3538 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3540 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3544 if (LHS.getValueType().isInteger()) {
3545 assert((LHS.getValueType() == RHS.getValueType()) &&
3546 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3548 // If the RHS of the comparison is zero, we can potentially fold this
3549 // to a specialized branch.
3550 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3551 if (RHSC && RHSC->getZExtValue() == 0) {
3552 if (CC == ISD::SETEQ) {
3553 // See if we can use a TBZ to fold in an AND as well.
3554 // TBZ has a smaller branch displacement than CBZ. If the offset is
3555 // out of bounds, a late MI-layer pass rewrites branches.
3556 // 403.gcc is an example that hits this case.
3557 if (LHS.getOpcode() == ISD::AND &&
3558 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3559 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3560 SDValue Test = LHS.getOperand(0);
3561 uint64_t Mask = LHS.getConstantOperandVal(1);
3562 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3563 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3567 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3568 } else if (CC == ISD::SETNE) {
3569 // See if we can use a TBZ to fold in an AND as well.
3570 // TBZ has a smaller branch displacement than CBZ. If the offset is
3571 // out of bounds, a late MI-layer pass rewrites branches.
3572 // 403.gcc is an example that hits this case.
3573 if (LHS.getOpcode() == ISD::AND &&
3574 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3575 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3576 SDValue Test = LHS.getOperand(0);
3577 uint64_t Mask = LHS.getConstantOperandVal(1);
3578 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3579 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3583 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3584 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3585 // Don't combine AND since emitComparison converts the AND to an ANDS
3586 // (a.k.a. TST) and the test in the test bit and branch instruction
3587 // becomes redundant. This would also increase register pressure.
3588 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3589 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3590 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3593 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3594 LHS.getOpcode() != ISD::AND) {
3595 // Don't combine AND since emitComparison converts the AND to an ANDS
3596 // (a.k.a. TST) and the test in the test bit and branch instruction
3597 // becomes redundant. This would also increase register pressure.
3598 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3599 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3600 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3604 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3605 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3609 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3611 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3612 // clean. Some of them require two branches to implement.
3613 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3614 AArch64CC::CondCode CC1, CC2;
3615 changeFPCCToAArch64CC(CC, CC1, CC2);
3616 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3618 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3619 if (CC2 != AArch64CC::AL) {
3620 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3621 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3628 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3629 SelectionDAG &DAG) const {
3630 EVT VT = Op.getValueType();
3633 SDValue In1 = Op.getOperand(0);
3634 SDValue In2 = Op.getOperand(1);
3635 EVT SrcVT = In2.getValueType();
3637 if (SrcVT == MVT::f32 && VT == MVT::f64)
3638 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3639 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3640 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3641 DAG.getIntPtrConstant(0, DL));
3643 // FIXME: Src type is different, bail out for now. Can VT really be a
3651 SDValue VecVal1, VecVal2;
3652 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3655 EltMask = 0x80000000ULL;
3657 if (!VT.isVector()) {
3658 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3659 DAG.getUNDEF(VecVT), In1);
3660 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3661 DAG.getUNDEF(VecVT), In2);
3663 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3664 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3666 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3670 // We want to materialize a mask with the high bit set, but the AdvSIMD
3671 // immediate moves cannot materialize that in a single instruction for
3672 // 64-bit elements. Instead, materialize zero and then negate it.
3675 if (!VT.isVector()) {
3676 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3677 DAG.getUNDEF(VecVT), In1);
3678 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3679 DAG.getUNDEF(VecVT), In2);
3681 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3682 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3685 llvm_unreachable("Invalid type for copysign!");
3688 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3690 // If we couldn't materialize the mask above, then the mask vector will be
3691 // the zero vector, and we need to negate it here.
3692 if (VT == MVT::f64 || VT == MVT::v2f64) {
3693 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3694 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3695 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3699 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3702 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3703 else if (VT == MVT::f64)
3704 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3706 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3709 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3710 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3711 Attribute::NoImplicitFloat))
3714 if (!Subtarget->hasNEON())
3717 // While there is no integer popcount instruction, it can
3718 // be more efficiently lowered to the following sequence that uses
3719 // AdvSIMD registers/instructions as long as the copies to/from
3720 // the AdvSIMD registers are cheap.
3721 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3722 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3723 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3724 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3725 SDValue Val = Op.getOperand(0);
3727 EVT VT = Op.getValueType();
3730 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3731 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3733 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3734 SDValue UaddLV = DAG.getNode(
3735 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3736 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3739 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3743 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3745 if (Op.getValueType().isVector())
3746 return LowerVSETCC(Op, DAG);
3748 SDValue LHS = Op.getOperand(0);
3749 SDValue RHS = Op.getOperand(1);
3750 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3753 // We chose ZeroOrOneBooleanContents, so use zero and one.
3754 EVT VT = Op.getValueType();
3755 SDValue TVal = DAG.getConstant(1, dl, VT);
3756 SDValue FVal = DAG.getConstant(0, dl, VT);
3758 // Handle f128 first, since one possible outcome is a normal integer
3759 // comparison which gets picked up by the next if statement.
3760 if (LHS.getValueType() == MVT::f128) {
3761 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3763 // If softenSetCCOperands returned a scalar, use it.
3764 if (!RHS.getNode()) {
3765 assert(LHS.getValueType() == Op.getValueType() &&
3766 "Unexpected setcc expansion!");
3771 if (LHS.getValueType().isInteger()) {
3774 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3776 // Note that we inverted the condition above, so we reverse the order of
3777 // the true and false operands here. This will allow the setcc to be
3778 // matched to a single CSINC instruction.
3779 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3782 // Now we know we're dealing with FP values.
3783 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3785 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3786 // and do the comparison.
3787 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3789 AArch64CC::CondCode CC1, CC2;
3790 changeFPCCToAArch64CC(CC, CC1, CC2);
3791 if (CC2 == AArch64CC::AL) {
3792 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3793 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3795 // Note that we inverted the condition above, so we reverse the order of
3796 // the true and false operands here. This will allow the setcc to be
3797 // matched to a single CSINC instruction.
3798 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3800 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3801 // totally clean. Some of them require two CSELs to implement. As is in
3802 // this case, we emit the first CSEL and then emit a second using the output
3803 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3805 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3806 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3808 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3810 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3811 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3815 /// A SELECT_CC operation is really some kind of max or min if both values being
3816 /// compared are, in some sense, equal to the results in either case. However,
3817 /// it is permissible to compare f32 values and produce directly extended f64
3820 /// Extending the comparison operands would also be allowed, but is less likely
3821 /// to happen in practice since their use is right here. Note that truncate
3822 /// operations would *not* be semantically equivalent.
3823 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3825 return (Cmp.getValueType() == MVT::f32 ||
3826 Cmp.getValueType() == MVT::f64);
3828 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3829 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3830 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3831 Result.getValueType() == MVT::f64) {
3833 APFloat CmpVal = CCmp->getValueAPF();
3834 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3835 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3838 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3841 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3842 SDValue RHS, SDValue TVal,
3843 SDValue FVal, SDLoc dl,
3844 SelectionDAG &DAG) const {
3845 // Handle f128 first, because it will result in a comparison of some RTLIB
3846 // call result against zero.
3847 if (LHS.getValueType() == MVT::f128) {
3848 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3850 // If softenSetCCOperands returned a scalar, we need to compare the result
3851 // against zero to select between true and false values.
3852 if (!RHS.getNode()) {
3853 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3858 // Handle integers first.
3859 if (LHS.getValueType().isInteger()) {
3860 assert((LHS.getValueType() == RHS.getValueType()) &&
3861 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3863 unsigned Opcode = AArch64ISD::CSEL;
3865 // If both the TVal and the FVal are constants, see if we can swap them in
3866 // order to for a CSINV or CSINC out of them.
3867 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3868 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3870 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3871 std::swap(TVal, FVal);
3872 std::swap(CTVal, CFVal);
3873 CC = ISD::getSetCCInverse(CC, true);
3874 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3875 std::swap(TVal, FVal);
3876 std::swap(CTVal, CFVal);
3877 CC = ISD::getSetCCInverse(CC, true);
3878 } else if (TVal.getOpcode() == ISD::XOR) {
3879 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3880 // with a CSINV rather than a CSEL.
3881 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3883 if (CVal && CVal->isAllOnesValue()) {
3884 std::swap(TVal, FVal);
3885 std::swap(CTVal, CFVal);
3886 CC = ISD::getSetCCInverse(CC, true);
3888 } else if (TVal.getOpcode() == ISD::SUB) {
3889 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3890 // that we can match with a CSNEG rather than a CSEL.
3891 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3893 if (CVal && CVal->isNullValue()) {
3894 std::swap(TVal, FVal);
3895 std::swap(CTVal, CFVal);
3896 CC = ISD::getSetCCInverse(CC, true);
3898 } else if (CTVal && CFVal) {
3899 const int64_t TrueVal = CTVal->getSExtValue();
3900 const int64_t FalseVal = CFVal->getSExtValue();
3903 // If both TVal and FVal are constants, see if FVal is the
3904 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3905 // instead of a CSEL in that case.
3906 if (TrueVal == ~FalseVal) {
3907 Opcode = AArch64ISD::CSINV;
3908 } else if (TrueVal == -FalseVal) {
3909 Opcode = AArch64ISD::CSNEG;
3910 } else if (TVal.getValueType() == MVT::i32) {
3911 // If our operands are only 32-bit wide, make sure we use 32-bit
3912 // arithmetic for the check whether we can use CSINC. This ensures that
3913 // the addition in the check will wrap around properly in case there is
3914 // an overflow (which would not be the case if we do the check with
3915 // 64-bit arithmetic).
3916 const uint32_t TrueVal32 = CTVal->getZExtValue();
3917 const uint32_t FalseVal32 = CFVal->getZExtValue();
3919 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3920 Opcode = AArch64ISD::CSINC;
3922 if (TrueVal32 > FalseVal32) {
3926 // 64-bit check whether we can use CSINC.
3927 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3928 Opcode = AArch64ISD::CSINC;
3930 if (TrueVal > FalseVal) {
3935 // Swap TVal and FVal if necessary.
3937 std::swap(TVal, FVal);
3938 std::swap(CTVal, CFVal);
3939 CC = ISD::getSetCCInverse(CC, true);
3942 if (Opcode != AArch64ISD::CSEL) {
3943 // Drop FVal since we can get its value by simply inverting/negating
3950 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3952 EVT VT = TVal.getValueType();
3953 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3956 // Now we know we're dealing with FP values.
3957 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3958 assert(LHS.getValueType() == RHS.getValueType());
3959 EVT VT = TVal.getValueType();
3960 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3962 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3963 // clean. Some of them require two CSELs to implement.
3964 AArch64CC::CondCode CC1, CC2;
3965 changeFPCCToAArch64CC(CC, CC1, CC2);
3966 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3967 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3969 // If we need a second CSEL, emit it, using the output of the first as the
3970 // RHS. We're effectively OR'ing the two CC's together.
3971 if (CC2 != AArch64CC::AL) {
3972 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3973 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3976 // Otherwise, return the output of the first CSEL.
3980 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3981 SelectionDAG &DAG) const {
3982 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3983 SDValue LHS = Op.getOperand(0);
3984 SDValue RHS = Op.getOperand(1);
3985 SDValue TVal = Op.getOperand(2);
3986 SDValue FVal = Op.getOperand(3);
3988 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3991 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3992 SelectionDAG &DAG) const {
3993 SDValue CCVal = Op->getOperand(0);
3994 SDValue TVal = Op->getOperand(1);
3995 SDValue FVal = Op->getOperand(2);
3998 unsigned Opc = CCVal.getOpcode();
3999 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4001 if (CCVal.getResNo() == 1 &&
4002 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4003 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4004 // Only lower legal XALUO ops.
4005 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4008 AArch64CC::CondCode OFCC;
4009 SDValue Value, Overflow;
4010 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4011 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4013 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4017 // Lower it the same way as we would lower a SELECT_CC node.
4020 if (CCVal.getOpcode() == ISD::SETCC) {
4021 LHS = CCVal.getOperand(0);
4022 RHS = CCVal.getOperand(1);
4023 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4026 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4029 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4032 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4033 SelectionDAG &DAG) const {
4034 // Jump table entries as PC relative offsets. No additional tweaking
4035 // is necessary here. Just get the address of the jump table.
4036 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4037 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4040 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4041 !Subtarget->isTargetMachO()) {
4042 const unsigned char MO_NC = AArch64II::MO_NC;
4044 AArch64ISD::WrapperLarge, DL, PtrVT,
4045 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
4046 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
4047 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
4048 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4049 AArch64II::MO_G0 | MO_NC));
4053 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
4054 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4055 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4056 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4057 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4060 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4061 SelectionDAG &DAG) const {
4062 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4063 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4066 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4067 // Use the GOT for the large code model on iOS.
4068 if (Subtarget->isTargetMachO()) {
4069 SDValue GotAddr = DAG.getTargetConstantPool(
4070 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4072 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
4075 const unsigned char MO_NC = AArch64II::MO_NC;
4077 AArch64ISD::WrapperLarge, DL, PtrVT,
4078 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4079 CP->getOffset(), AArch64II::MO_G3),
4080 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4081 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
4082 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4083 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
4084 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4085 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
4087 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4088 // ELF, the only valid one on Darwin.
4090 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4091 CP->getOffset(), AArch64II::MO_PAGE);
4092 SDValue Lo = DAG.getTargetConstantPool(
4093 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4094 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4096 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4097 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4101 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4102 SelectionDAG &DAG) const {
4103 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4104 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4106 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4107 !Subtarget->isTargetMachO()) {
4108 const unsigned char MO_NC = AArch64II::MO_NC;
4110 AArch64ISD::WrapperLarge, DL, PtrVT,
4111 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
4112 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
4113 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
4114 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
4116 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
4117 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
4119 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4120 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4124 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4125 SelectionDAG &DAG) const {
4126 AArch64FunctionInfo *FuncInfo =
4127 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4130 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4131 getPointerTy(DAG.getDataLayout()));
4132 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4133 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4134 MachinePointerInfo(SV), false, false, 0);
4137 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4138 SelectionDAG &DAG) const {
4139 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4140 // Standard, section B.3.
4141 MachineFunction &MF = DAG.getMachineFunction();
4142 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4143 auto PtrVT = getPointerTy(DAG.getDataLayout());
4146 SDValue Chain = Op.getOperand(0);
4147 SDValue VAList = Op.getOperand(1);
4148 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4149 SmallVector<SDValue, 4> MemOps;
4151 // void *__stack at offset 0
4152 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4153 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4154 MachinePointerInfo(SV), false, false, 8));
4156 // void *__gr_top at offset 8
4157 int GPRSize = FuncInfo->getVarArgsGPRSize();
4159 SDValue GRTop, GRTopAddr;
4162 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4164 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4165 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4166 DAG.getConstant(GPRSize, DL, PtrVT));
4168 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4169 MachinePointerInfo(SV, 8), false, false, 8));
4172 // void *__vr_top at offset 16
4173 int FPRSize = FuncInfo->getVarArgsFPRSize();
4175 SDValue VRTop, VRTopAddr;
4176 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4177 DAG.getConstant(16, DL, PtrVT));
4179 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4180 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4181 DAG.getConstant(FPRSize, DL, PtrVT));
4183 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4184 MachinePointerInfo(SV, 16), false, false, 8));
4187 // int __gr_offs at offset 24
4188 SDValue GROffsAddr =
4189 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4190 MemOps.push_back(DAG.getStore(Chain, DL,
4191 DAG.getConstant(-GPRSize, DL, MVT::i32),
4192 GROffsAddr, MachinePointerInfo(SV, 24), false,
4195 // int __vr_offs at offset 28
4196 SDValue VROffsAddr =
4197 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4198 MemOps.push_back(DAG.getStore(Chain, DL,
4199 DAG.getConstant(-FPRSize, DL, MVT::i32),
4200 VROffsAddr, MachinePointerInfo(SV, 28), false,
4203 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4206 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4207 SelectionDAG &DAG) const {
4208 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
4209 : LowerAAPCS_VASTART(Op, DAG);
4212 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4213 SelectionDAG &DAG) const {
4214 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4217 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
4218 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4219 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4221 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4223 DAG.getConstant(VaListSize, DL, MVT::i32),
4224 8, false, false, false, MachinePointerInfo(DestSV),
4225 MachinePointerInfo(SrcSV));
4228 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4229 assert(Subtarget->isTargetDarwin() &&
4230 "automatic va_arg instruction only works on Darwin");
4232 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4233 EVT VT = Op.getValueType();
4235 SDValue Chain = Op.getOperand(0);
4236 SDValue Addr = Op.getOperand(1);
4237 unsigned Align = Op.getConstantOperandVal(3);
4238 auto PtrVT = getPointerTy(DAG.getDataLayout());
4240 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V),
4241 false, false, false, 0);
4242 Chain = VAList.getValue(1);
4245 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4246 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4247 DAG.getConstant(Align - 1, DL, PtrVT));
4248 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4249 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4252 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4253 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4255 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4256 // up to 64 bits. At the very least, we have to increase the striding of the
4257 // vaargs list to match this, and for FP values we need to introduce
4258 // FP_ROUND nodes as well.
4259 if (VT.isInteger() && !VT.isVector())
4261 bool NeedFPTrunc = false;
4262 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4267 // Increment the pointer, VAList, to the next vaarg
4268 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4269 DAG.getConstant(ArgSize, DL, PtrVT));
4270 // Store the incremented VAList to the legalized pointer
4271 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4274 // Load the actual argument out of the pointer VAList
4276 // Load the value as an f64.
4277 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4278 MachinePointerInfo(), false, false, false, 0);
4279 // Round the value down to an f32.
4280 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4281 DAG.getIntPtrConstant(1, DL));
4282 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4283 // Merge the rounded value with the chain output of the load.
4284 return DAG.getMergeValues(Ops, DL);
4287 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4291 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4292 SelectionDAG &DAG) const {
4293 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4294 MFI->setFrameAddressIsTaken(true);
4296 EVT VT = Op.getValueType();
4298 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4300 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4302 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4303 MachinePointerInfo(), false, false, false, 0);
4307 // FIXME? Maybe this could be a TableGen attribute on some registers and
4308 // this table could be generated automatically from RegInfo.
4309 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4310 SelectionDAG &DAG) const {
4311 unsigned Reg = StringSwitch<unsigned>(RegName)
4312 .Case("sp", AArch64::SP)
4316 report_fatal_error(Twine("Invalid register name \""
4317 + StringRef(RegName) + "\"."));
4320 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4321 SelectionDAG &DAG) const {
4322 MachineFunction &MF = DAG.getMachineFunction();
4323 MachineFrameInfo *MFI = MF.getFrameInfo();
4324 MFI->setReturnAddressIsTaken(true);
4326 EVT VT = Op.getValueType();
4328 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4330 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4331 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4332 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4333 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4334 MachinePointerInfo(), false, false, false, 0);
4337 // Return LR, which contains the return address. Mark it an implicit live-in.
4338 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4339 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4342 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4343 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4344 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4345 SelectionDAG &DAG) const {
4346 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4347 EVT VT = Op.getValueType();
4348 unsigned VTBits = VT.getSizeInBits();
4350 SDValue ShOpLo = Op.getOperand(0);
4351 SDValue ShOpHi = Op.getOperand(1);
4352 SDValue ShAmt = Op.getOperand(2);
4354 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4356 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4358 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4359 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4360 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4361 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4362 DAG.getConstant(VTBits, dl, MVT::i64));
4363 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4365 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4366 ISD::SETGE, dl, DAG);
4367 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4369 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4370 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4372 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4374 // AArch64 shifts larger than the register width are wrapped rather than
4375 // clamped, so we can't just emit "hi >> x".
4376 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4377 SDValue TrueValHi = Opc == ISD::SRA
4378 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4379 DAG.getConstant(VTBits - 1, dl,
4381 : DAG.getConstant(0, dl, VT);
4383 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4385 SDValue Ops[2] = { Lo, Hi };
4386 return DAG.getMergeValues(Ops, dl);
4389 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4390 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4391 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4392 SelectionDAG &DAG) const {
4393 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4394 EVT VT = Op.getValueType();
4395 unsigned VTBits = VT.getSizeInBits();
4397 SDValue ShOpLo = Op.getOperand(0);
4398 SDValue ShOpHi = Op.getOperand(1);
4399 SDValue ShAmt = Op.getOperand(2);
4402 assert(Op.getOpcode() == ISD::SHL_PARTS);
4403 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4404 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4405 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4406 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4407 DAG.getConstant(VTBits, dl, MVT::i64));
4408 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4409 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4411 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4413 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4414 ISD::SETGE, dl, DAG);
4415 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4417 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4419 // AArch64 shifts of larger than register sizes are wrapped rather than
4420 // clamped, so we can't just emit "lo << a" if a is too big.
4421 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4422 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4424 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4426 SDValue Ops[2] = { Lo, Hi };
4427 return DAG.getMergeValues(Ops, dl);
4430 bool AArch64TargetLowering::isOffsetFoldingLegal(
4431 const GlobalAddressSDNode *GA) const {
4432 // The AArch64 target doesn't support folding offsets into global addresses.
4436 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4437 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4438 // FIXME: We should be able to handle f128 as well with a clever lowering.
4439 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4443 return AArch64_AM::getFP64Imm(Imm) != -1;
4444 else if (VT == MVT::f32)
4445 return AArch64_AM::getFP32Imm(Imm) != -1;
4449 //===----------------------------------------------------------------------===//
4450 // AArch64 Optimization Hooks
4451 //===----------------------------------------------------------------------===//
4453 //===----------------------------------------------------------------------===//
4454 // AArch64 Inline Assembly Support
4455 //===----------------------------------------------------------------------===//
4457 // Table of Constraints
4458 // TODO: This is the current set of constraints supported by ARM for the
4459 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4461 // r - A general register
4462 // w - An FP/SIMD register of some size in the range v0-v31
4463 // x - An FP/SIMD register of some size in the range v0-v15
4464 // I - Constant that can be used with an ADD instruction
4465 // J - Constant that can be used with a SUB instruction
4466 // K - Constant that can be used with a 32-bit logical instruction
4467 // L - Constant that can be used with a 64-bit logical instruction
4468 // M - Constant that can be used as a 32-bit MOV immediate
4469 // N - Constant that can be used as a 64-bit MOV immediate
4470 // Q - A memory reference with base register and no offset
4471 // S - A symbolic address
4472 // Y - Floating point constant zero
4473 // Z - Integer constant zero
4475 // Note that general register operands will be output using their 64-bit x
4476 // register name, whatever the size of the variable, unless the asm operand
4477 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4478 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4481 /// getConstraintType - Given a constraint letter, return the type of
4482 /// constraint it is for this target.
4483 AArch64TargetLowering::ConstraintType
4484 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4485 if (Constraint.size() == 1) {
4486 switch (Constraint[0]) {
4493 return C_RegisterClass;
4494 // An address with a single base register. Due to the way we
4495 // currently handle addresses it is the same as 'r'.
4500 return TargetLowering::getConstraintType(Constraint);
4503 /// Examine constraint type and operand type and determine a weight value.
4504 /// This object must already have been set up with the operand type
4505 /// and the current alternative constraint selected.
4506 TargetLowering::ConstraintWeight
4507 AArch64TargetLowering::getSingleConstraintMatchWeight(
4508 AsmOperandInfo &info, const char *constraint) const {
4509 ConstraintWeight weight = CW_Invalid;
4510 Value *CallOperandVal = info.CallOperandVal;
4511 // If we don't have a value, we can't do a match,
4512 // but allow it at the lowest weight.
4513 if (!CallOperandVal)
4515 Type *type = CallOperandVal->getType();
4516 // Look at the constraint type.
4517 switch (*constraint) {
4519 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4523 if (type->isFloatingPointTy() || type->isVectorTy())
4524 weight = CW_Register;
4527 weight = CW_Constant;
4533 std::pair<unsigned, const TargetRegisterClass *>
4534 AArch64TargetLowering::getRegForInlineAsmConstraint(
4535 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4536 if (Constraint.size() == 1) {
4537 switch (Constraint[0]) {
4539 if (VT.getSizeInBits() == 64)
4540 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4541 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4544 return std::make_pair(0U, &AArch64::FPR32RegClass);
4545 if (VT.getSizeInBits() == 64)
4546 return std::make_pair(0U, &AArch64::FPR64RegClass);
4547 if (VT.getSizeInBits() == 128)
4548 return std::make_pair(0U, &AArch64::FPR128RegClass);
4550 // The instructions that this constraint is designed for can
4551 // only take 128-bit registers so just use that regclass.
4553 if (VT.getSizeInBits() == 128)
4554 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4558 if (StringRef("{cc}").equals_lower(Constraint))
4559 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4561 // Use the default implementation in TargetLowering to convert the register
4562 // constraint into a member of a register class.
4563 std::pair<unsigned, const TargetRegisterClass *> Res;
4564 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4566 // Not found as a standard register?
4568 unsigned Size = Constraint.size();
4569 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4570 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4572 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4573 if (!Failed && RegNo >= 0 && RegNo <= 31) {
4574 // v0 - v31 are aliases of q0 - q31.
4575 // By default we'll emit v0-v31 for this unless there's a modifier where
4576 // we'll emit the correct register as well.
4577 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4578 Res.second = &AArch64::FPR128RegClass;
4586 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4587 /// vector. If it is invalid, don't add anything to Ops.
4588 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4589 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4590 SelectionDAG &DAG) const {
4593 // Currently only support length 1 constraints.
4594 if (Constraint.length() != 1)
4597 char ConstraintLetter = Constraint[0];
4598 switch (ConstraintLetter) {
4602 // This set of constraints deal with valid constants for various instructions.
4603 // Validate and return a target constant for them if we can.
4605 // 'z' maps to xzr or wzr so it needs an input of 0.
4606 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4607 if (!C || C->getZExtValue() != 0)
4610 if (Op.getValueType() == MVT::i64)
4611 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4613 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4623 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4627 // Grab the value and do some validation.
4628 uint64_t CVal = C->getZExtValue();
4629 switch (ConstraintLetter) {
4630 // The I constraint applies only to simple ADD or SUB immediate operands:
4631 // i.e. 0 to 4095 with optional shift by 12
4632 // The J constraint applies only to ADD or SUB immediates that would be
4633 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4634 // instruction [or vice versa], in other words -1 to -4095 with optional
4635 // left shift by 12.
4637 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4641 uint64_t NVal = -C->getSExtValue();
4642 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4643 CVal = C->getSExtValue();
4648 // The K and L constraints apply *only* to logical immediates, including
4649 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4650 // been removed and MOV should be used). So these constraints have to
4651 // distinguish between bit patterns that are valid 32-bit or 64-bit
4652 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4653 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4656 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4660 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4663 // The M and N constraints are a superset of K and L respectively, for use
4664 // with the MOV (immediate) alias. As well as the logical immediates they
4665 // also match 32 or 64-bit immediates that can be loaded either using a
4666 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4667 // (M) or 64-bit 0x1234000000000000 (N) etc.
4668 // As a note some of this code is liberally stolen from the asm parser.
4670 if (!isUInt<32>(CVal))
4672 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4674 if ((CVal & 0xFFFF) == CVal)
4676 if ((CVal & 0xFFFF0000ULL) == CVal)
4678 uint64_t NCVal = ~(uint32_t)CVal;
4679 if ((NCVal & 0xFFFFULL) == NCVal)
4681 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4686 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4688 if ((CVal & 0xFFFFULL) == CVal)
4690 if ((CVal & 0xFFFF0000ULL) == CVal)
4692 if ((CVal & 0xFFFF00000000ULL) == CVal)
4694 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4696 uint64_t NCVal = ~CVal;
4697 if ((NCVal & 0xFFFFULL) == NCVal)
4699 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4701 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4703 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4711 // All assembler immediates are 64-bit integers.
4712 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4716 if (Result.getNode()) {
4717 Ops.push_back(Result);
4721 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4724 //===----------------------------------------------------------------------===//
4725 // AArch64 Advanced SIMD Support
4726 //===----------------------------------------------------------------------===//
4728 /// WidenVector - Given a value in the V64 register class, produce the
4729 /// equivalent value in the V128 register class.
4730 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4731 EVT VT = V64Reg.getValueType();
4732 unsigned NarrowSize = VT.getVectorNumElements();
4733 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4734 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4737 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4738 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4741 /// getExtFactor - Determine the adjustment factor for the position when
4742 /// generating an "extract from vector registers" instruction.
4743 static unsigned getExtFactor(SDValue &V) {
4744 EVT EltType = V.getValueType().getVectorElementType();
4745 return EltType.getSizeInBits() / 8;
4748 /// NarrowVector - Given a value in the V128 register class, produce the
4749 /// equivalent value in the V64 register class.
4750 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4751 EVT VT = V128Reg.getValueType();
4752 unsigned WideSize = VT.getVectorNumElements();
4753 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4754 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4757 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4760 // Gather data to see if the operation can be modelled as a
4761 // shuffle in combination with VEXTs.
4762 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4763 SelectionDAG &DAG) const {
4764 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4766 EVT VT = Op.getValueType();
4767 unsigned NumElts = VT.getVectorNumElements();
4769 struct ShuffleSourceInfo {
4774 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4775 // be compatible with the shuffle we intend to construct. As a result
4776 // ShuffleVec will be some sliding window into the original Vec.
4779 // Code should guarantee that element i in Vec starts at element "WindowBase
4780 // + i * WindowScale in ShuffleVec".
4784 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4785 ShuffleSourceInfo(SDValue Vec)
4786 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4790 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4792 SmallVector<ShuffleSourceInfo, 2> Sources;
4793 for (unsigned i = 0; i < NumElts; ++i) {
4794 SDValue V = Op.getOperand(i);
4795 if (V.getOpcode() == ISD::UNDEF)
4797 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4798 // A shuffle can only come from building a vector from various
4799 // elements of other vectors.
4803 // Add this element source to the list if it's not already there.
4804 SDValue SourceVec = V.getOperand(0);
4805 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4806 if (Source == Sources.end())
4807 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4809 // Update the minimum and maximum lane number seen.
4810 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4811 Source->MinElt = std::min(Source->MinElt, EltNo);
4812 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4815 // Currently only do something sane when at most two source vectors
4817 if (Sources.size() > 2)
4820 // Find out the smallest element size among result and two sources, and use
4821 // it as element size to build the shuffle_vector.
4822 EVT SmallestEltTy = VT.getVectorElementType();
4823 for (auto &Source : Sources) {
4824 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4825 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4826 SmallestEltTy = SrcEltTy;
4829 unsigned ResMultiplier =
4830 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4831 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4832 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4834 // If the source vector is too wide or too narrow, we may nevertheless be able
4835 // to construct a compatible shuffle either by concatenating it with UNDEF or
4836 // extracting a suitable range of elements.
4837 for (auto &Src : Sources) {
4838 EVT SrcVT = Src.ShuffleVec.getValueType();
4840 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4843 // This stage of the search produces a source with the same element type as
4844 // the original, but with a total width matching the BUILD_VECTOR output.
4845 EVT EltVT = SrcVT.getVectorElementType();
4846 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4847 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4849 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4850 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4851 // We can pad out the smaller vector for free, so if it's part of a
4854 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4855 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4859 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4861 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4862 // Span too large for a VEXT to cope
4866 if (Src.MinElt >= NumSrcElts) {
4867 // The extraction can just take the second half
4869 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4870 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4871 Src.WindowBase = -NumSrcElts;
4872 } else if (Src.MaxElt < NumSrcElts) {
4873 // The extraction can just take the first half
4875 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4876 DAG.getConstant(0, dl, MVT::i64));
4878 // An actual VEXT is needed
4880 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4881 DAG.getConstant(0, dl, MVT::i64));
4883 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4884 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4885 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4887 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4889 DAG.getConstant(Imm, dl, MVT::i32));
4890 Src.WindowBase = -Src.MinElt;
4894 // Another possible incompatibility occurs from the vector element types. We
4895 // can fix this by bitcasting the source vectors to the same type we intend
4897 for (auto &Src : Sources) {
4898 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4899 if (SrcEltTy == SmallestEltTy)
4901 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4902 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4903 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4904 Src.WindowBase *= Src.WindowScale;
4907 // Final sanity check before we try to actually produce a shuffle.
4909 for (auto Src : Sources)
4910 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4913 // The stars all align, our next step is to produce the mask for the shuffle.
4914 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4915 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4916 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4917 SDValue Entry = Op.getOperand(i);
4918 if (Entry.getOpcode() == ISD::UNDEF)
4921 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4922 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4924 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4925 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4927 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4928 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4929 VT.getVectorElementType().getSizeInBits());
4930 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4932 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4933 // starting at the appropriate offset.
4934 int *LaneMask = &Mask[i * ResMultiplier];
4936 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4937 ExtractBase += NumElts * (Src - Sources.begin());
4938 for (int j = 0; j < LanesDefined; ++j)
4939 LaneMask[j] = ExtractBase + j;
4942 // Final check before we try to produce nonsense...
4943 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4946 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4947 for (unsigned i = 0; i < Sources.size(); ++i)
4948 ShuffleOps[i] = Sources[i].ShuffleVec;
4950 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4951 ShuffleOps[1], &Mask[0]);
4952 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4955 // check if an EXT instruction can handle the shuffle mask when the
4956 // vector sources of the shuffle are the same.
4957 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4958 unsigned NumElts = VT.getVectorNumElements();
4960 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4966 // If this is a VEXT shuffle, the immediate value is the index of the first
4967 // element. The other shuffle indices must be the successive elements after
4969 unsigned ExpectedElt = Imm;
4970 for (unsigned i = 1; i < NumElts; ++i) {
4971 // Increment the expected index. If it wraps around, just follow it
4972 // back to index zero and keep going.
4974 if (ExpectedElt == NumElts)
4978 continue; // ignore UNDEF indices
4979 if (ExpectedElt != static_cast<unsigned>(M[i]))
4986 // check if an EXT instruction can handle the shuffle mask when the
4987 // vector sources of the shuffle are different.
4988 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4990 // Look for the first non-undef element.
4991 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4992 [](int Elt) {return Elt >= 0;});
4994 // Benefit form APInt to handle overflow when calculating expected element.
4995 unsigned NumElts = VT.getVectorNumElements();
4996 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4997 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4998 // The following shuffle indices must be the successive elements after the
4999 // first real element.
5000 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5001 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5002 if (FirstWrongElt != M.end())
5005 // The index of an EXT is the first element if it is not UNDEF.
5006 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5007 // value of the first element. E.g.
5008 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5009 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5010 // ExpectedElt is the last mask index plus 1.
5011 Imm = ExpectedElt.getZExtValue();
5013 // There are two difference cases requiring to reverse input vectors.
5014 // For example, for vector <4 x i32> we have the following cases,
5015 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5016 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5017 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5018 // to reverse two input vectors.
5027 /// isREVMask - Check if a vector shuffle corresponds to a REV
5028 /// instruction with the specified blocksize. (The order of the elements
5029 /// within each block of the vector is reversed.)
5030 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5031 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
5032 "Only possible block sizes for REV are: 16, 32, 64");
5034 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5038 unsigned NumElts = VT.getVectorNumElements();
5039 unsigned BlockElts = M[0] + 1;
5040 // If the first shuffle index is UNDEF, be optimistic.
5042 BlockElts = BlockSize / EltSz;
5044 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5047 for (unsigned i = 0; i < NumElts; ++i) {
5049 continue; // ignore UNDEF indices
5050 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5057 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5058 unsigned NumElts = VT.getVectorNumElements();
5059 WhichResult = (M[0] == 0 ? 0 : 1);
5060 unsigned Idx = WhichResult * NumElts / 2;
5061 for (unsigned i = 0; i != NumElts; i += 2) {
5062 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5063 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5071 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5072 unsigned NumElts = VT.getVectorNumElements();
5073 WhichResult = (M[0] == 0 ? 0 : 1);
5074 for (unsigned i = 0; i != NumElts; ++i) {
5076 continue; // ignore UNDEF indices
5077 if ((unsigned)M[i] != 2 * i + WhichResult)
5084 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5085 unsigned NumElts = VT.getVectorNumElements();
5086 WhichResult = (M[0] == 0 ? 0 : 1);
5087 for (unsigned i = 0; i < NumElts; i += 2) {
5088 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5089 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5095 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5096 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5097 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5098 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5099 unsigned NumElts = VT.getVectorNumElements();
5100 WhichResult = (M[0] == 0 ? 0 : 1);
5101 unsigned Idx = WhichResult * NumElts / 2;
5102 for (unsigned i = 0; i != NumElts; i += 2) {
5103 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5104 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5112 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5113 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5114 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5115 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5116 unsigned Half = VT.getVectorNumElements() / 2;
5117 WhichResult = (M[0] == 0 ? 0 : 1);
5118 for (unsigned j = 0; j != 2; ++j) {
5119 unsigned Idx = WhichResult;
5120 for (unsigned i = 0; i != Half; ++i) {
5121 int MIdx = M[i + j * Half];
5122 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5131 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5132 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5133 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5134 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5135 unsigned NumElts = VT.getVectorNumElements();
5136 WhichResult = (M[0] == 0 ? 0 : 1);
5137 for (unsigned i = 0; i < NumElts; i += 2) {
5138 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5139 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5145 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5146 bool &DstIsLeft, int &Anomaly) {
5147 if (M.size() != static_cast<size_t>(NumInputElements))
5150 int NumLHSMatch = 0, NumRHSMatch = 0;
5151 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5153 for (int i = 0; i < NumInputElements; ++i) {
5163 LastLHSMismatch = i;
5165 if (M[i] == i + NumInputElements)
5168 LastRHSMismatch = i;
5171 if (NumLHSMatch == NumInputElements - 1) {
5173 Anomaly = LastLHSMismatch;
5175 } else if (NumRHSMatch == NumInputElements - 1) {
5177 Anomaly = LastRHSMismatch;
5184 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5185 if (VT.getSizeInBits() != 128)
5188 unsigned NumElts = VT.getVectorNumElements();
5190 for (int I = 0, E = NumElts / 2; I != E; I++) {
5195 int Offset = NumElts / 2;
5196 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5197 if (Mask[I] != I + SplitLHS * Offset)
5204 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5206 EVT VT = Op.getValueType();
5207 SDValue V0 = Op.getOperand(0);
5208 SDValue V1 = Op.getOperand(1);
5209 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5211 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5212 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5215 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
5217 if (!isConcatMask(Mask, VT, SplitV0))
5220 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5221 VT.getVectorNumElements() / 2);
5223 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5224 DAG.getConstant(0, DL, MVT::i64));
5226 if (V1.getValueType().getSizeInBits() == 128) {
5227 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5228 DAG.getConstant(0, DL, MVT::i64));
5230 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5233 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5234 /// the specified operations to build the shuffle.
5235 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5236 SDValue RHS, SelectionDAG &DAG,
5238 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5239 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5240 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5243 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5252 OP_VUZPL, // VUZP, left result
5253 OP_VUZPR, // VUZP, right result
5254 OP_VZIPL, // VZIP, left result
5255 OP_VZIPR, // VZIP, right result
5256 OP_VTRNL, // VTRN, left result
5257 OP_VTRNR // VTRN, right result
5260 if (OpNum == OP_COPY) {
5261 if (LHSID == (1 * 9 + 2) * 9 + 3)
5263 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5267 SDValue OpLHS, OpRHS;
5268 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5269 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5270 EVT VT = OpLHS.getValueType();
5274 llvm_unreachable("Unknown shuffle opcode!");
5276 // VREV divides the vector in half and swaps within the half.
5277 if (VT.getVectorElementType() == MVT::i32 ||
5278 VT.getVectorElementType() == MVT::f32)
5279 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5280 // vrev <4 x i16> -> REV32
5281 if (VT.getVectorElementType() == MVT::i16 ||
5282 VT.getVectorElementType() == MVT::f16)
5283 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5284 // vrev <4 x i8> -> REV16
5285 assert(VT.getVectorElementType() == MVT::i8);
5286 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5291 EVT EltTy = VT.getVectorElementType();
5293 if (EltTy == MVT::i8)
5294 Opcode = AArch64ISD::DUPLANE8;
5295 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5296 Opcode = AArch64ISD::DUPLANE16;
5297 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5298 Opcode = AArch64ISD::DUPLANE32;
5299 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5300 Opcode = AArch64ISD::DUPLANE64;
5302 llvm_unreachable("Invalid vector element type?");
5304 if (VT.getSizeInBits() == 64)
5305 OpLHS = WidenVector(OpLHS, DAG);
5306 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5307 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5312 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5313 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5314 DAG.getConstant(Imm, dl, MVT::i32));
5317 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5320 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5323 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5326 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5329 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5332 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5337 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5338 SelectionDAG &DAG) {
5339 // Check to see if we can use the TBL instruction.
5340 SDValue V1 = Op.getOperand(0);
5341 SDValue V2 = Op.getOperand(1);
5344 EVT EltVT = Op.getValueType().getVectorElementType();
5345 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5347 SmallVector<SDValue, 8> TBLMask;
5348 for (int Val : ShuffleMask) {
5349 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5350 unsigned Offset = Byte + Val * BytesPerElt;
5351 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5355 MVT IndexVT = MVT::v8i8;
5356 unsigned IndexLen = 8;
5357 if (Op.getValueType().getSizeInBits() == 128) {
5358 IndexVT = MVT::v16i8;
5362 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5363 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5366 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5368 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5369 Shuffle = DAG.getNode(
5370 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5371 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5372 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5373 makeArrayRef(TBLMask.data(), IndexLen)));
5375 if (IndexLen == 8) {
5376 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5377 Shuffle = DAG.getNode(
5378 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5379 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5380 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5381 makeArrayRef(TBLMask.data(), IndexLen)));
5383 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5384 // cannot currently represent the register constraints on the input
5386 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5387 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5388 // &TBLMask[0], IndexLen));
5389 Shuffle = DAG.getNode(
5390 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5391 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5393 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5394 makeArrayRef(TBLMask.data(), IndexLen)));
5397 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5400 static unsigned getDUPLANEOp(EVT EltType) {
5401 if (EltType == MVT::i8)
5402 return AArch64ISD::DUPLANE8;
5403 if (EltType == MVT::i16 || EltType == MVT::f16)
5404 return AArch64ISD::DUPLANE16;
5405 if (EltType == MVT::i32 || EltType == MVT::f32)
5406 return AArch64ISD::DUPLANE32;
5407 if (EltType == MVT::i64 || EltType == MVT::f64)
5408 return AArch64ISD::DUPLANE64;
5410 llvm_unreachable("Invalid vector element type?");
5413 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5414 SelectionDAG &DAG) const {
5416 EVT VT = Op.getValueType();
5418 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5420 // Convert shuffles that are directly supported on NEON to target-specific
5421 // DAG nodes, instead of keeping them as shuffles and matching them again
5422 // during code selection. This is more efficient and avoids the possibility
5423 // of inconsistencies between legalization and selection.
5424 ArrayRef<int> ShuffleMask = SVN->getMask();
5426 SDValue V1 = Op.getOperand(0);
5427 SDValue V2 = Op.getOperand(1);
5429 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5430 V1.getValueType().getSimpleVT())) {
5431 int Lane = SVN->getSplatIndex();
5432 // If this is undef splat, generate it via "just" vdup, if possible.
5436 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5437 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5439 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5440 // constant. If so, we can just reference the lane's definition directly.
5441 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5442 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5443 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5445 // Otherwise, duplicate from the lane of the input vector.
5446 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5448 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5449 // to make a vector of the same size as this SHUFFLE. We can ignore the
5450 // extract entirely, and canonicalise the concat using WidenVector.
5451 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5452 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5453 V1 = V1.getOperand(0);
5454 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5455 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5456 Lane -= Idx * VT.getVectorNumElements() / 2;
5457 V1 = WidenVector(V1.getOperand(Idx), DAG);
5458 } else if (VT.getSizeInBits() == 64)
5459 V1 = WidenVector(V1, DAG);
5461 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5464 if (isREVMask(ShuffleMask, VT, 64))
5465 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5466 if (isREVMask(ShuffleMask, VT, 32))
5467 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5468 if (isREVMask(ShuffleMask, VT, 16))
5469 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5471 bool ReverseEXT = false;
5473 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5476 Imm *= getExtFactor(V1);
5477 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5478 DAG.getConstant(Imm, dl, MVT::i32));
5479 } else if (V2->getOpcode() == ISD::UNDEF &&
5480 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5481 Imm *= getExtFactor(V1);
5482 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5483 DAG.getConstant(Imm, dl, MVT::i32));
5486 unsigned WhichResult;
5487 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5488 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5489 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5491 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5492 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5493 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5495 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5496 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5497 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5500 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5501 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5502 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5504 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5505 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5506 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5508 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5509 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5510 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5513 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5514 if (Concat.getNode())
5519 int NumInputElements = V1.getValueType().getVectorNumElements();
5520 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5521 SDValue DstVec = DstIsLeft ? V1 : V2;
5522 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5524 SDValue SrcVec = V1;
5525 int SrcLane = ShuffleMask[Anomaly];
5526 if (SrcLane >= NumInputElements) {
5528 SrcLane -= VT.getVectorNumElements();
5530 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5532 EVT ScalarVT = VT.getVectorElementType();
5534 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5535 ScalarVT = MVT::i32;
5538 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5539 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5543 // If the shuffle is not directly supported and it has 4 elements, use
5544 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5545 unsigned NumElts = VT.getVectorNumElements();
5547 unsigned PFIndexes[4];
5548 for (unsigned i = 0; i != 4; ++i) {
5549 if (ShuffleMask[i] < 0)
5552 PFIndexes[i] = ShuffleMask[i];
5555 // Compute the index in the perfect shuffle table.
5556 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5557 PFIndexes[2] * 9 + PFIndexes[3];
5558 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5559 unsigned Cost = (PFEntry >> 30);
5562 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5565 return GenerateTBL(Op, ShuffleMask, DAG);
5568 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5570 EVT VT = BVN->getValueType(0);
5571 APInt SplatBits, SplatUndef;
5572 unsigned SplatBitSize;
5574 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5575 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5577 for (unsigned i = 0; i < NumSplats; ++i) {
5578 CnstBits <<= SplatBitSize;
5579 UndefBits <<= SplatBitSize;
5580 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5581 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5590 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5591 SelectionDAG &DAG) const {
5592 BuildVectorSDNode *BVN =
5593 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5594 SDValue LHS = Op.getOperand(0);
5596 EVT VT = Op.getValueType();
5601 APInt CnstBits(VT.getSizeInBits(), 0);
5602 APInt UndefBits(VT.getSizeInBits(), 0);
5603 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5604 // We only have BIC vector immediate instruction, which is and-not.
5605 CnstBits = ~CnstBits;
5607 // We make use of a little bit of goto ickiness in order to avoid having to
5608 // duplicate the immediate matching logic for the undef toggled case.
5609 bool SecondTry = false;
5612 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5613 CnstBits = CnstBits.zextOrTrunc(64);
5614 uint64_t CnstVal = CnstBits.getZExtValue();
5616 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5617 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5618 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5619 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5620 DAG.getConstant(CnstVal, dl, MVT::i32),
5621 DAG.getConstant(0, dl, MVT::i32));
5622 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5625 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5626 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5627 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5628 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5629 DAG.getConstant(CnstVal, dl, MVT::i32),
5630 DAG.getConstant(8, dl, MVT::i32));
5631 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5634 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5635 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5636 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5637 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5638 DAG.getConstant(CnstVal, dl, MVT::i32),
5639 DAG.getConstant(16, dl, MVT::i32));
5640 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5643 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5644 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5645 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5646 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5647 DAG.getConstant(CnstVal, dl, MVT::i32),
5648 DAG.getConstant(24, dl, MVT::i32));
5649 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5652 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5653 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5654 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5655 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5656 DAG.getConstant(CnstVal, dl, MVT::i32),
5657 DAG.getConstant(0, dl, MVT::i32));
5658 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5661 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5662 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5663 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5664 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5665 DAG.getConstant(CnstVal, dl, MVT::i32),
5666 DAG.getConstant(8, dl, MVT::i32));
5667 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5674 CnstBits = ~UndefBits;
5678 // We can always fall back to a non-immediate AND.
5683 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5684 // consists of only the same constant int value, returned in reference arg
5686 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5687 uint64_t &ConstVal) {
5688 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5691 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5694 EVT VT = Bvec->getValueType(0);
5695 unsigned NumElts = VT.getVectorNumElements();
5696 for (unsigned i = 1; i < NumElts; ++i)
5697 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5699 ConstVal = FirstElt->getZExtValue();
5703 static unsigned getIntrinsicID(const SDNode *N) {
5704 unsigned Opcode = N->getOpcode();
5707 return Intrinsic::not_intrinsic;
5708 case ISD::INTRINSIC_WO_CHAIN: {
5709 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5710 if (IID < Intrinsic::num_intrinsics)
5712 return Intrinsic::not_intrinsic;
5717 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5718 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5719 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5720 // Also, logical shift right -> sri, with the same structure.
5721 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5722 EVT VT = N->getValueType(0);
5729 // Is the first op an AND?
5730 const SDValue And = N->getOperand(0);
5731 if (And.getOpcode() != ISD::AND)
5734 // Is the second op an shl or lshr?
5735 SDValue Shift = N->getOperand(1);
5736 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5737 // or AArch64ISD::VLSHR vector, #shift
5738 unsigned ShiftOpc = Shift.getOpcode();
5739 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5741 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5743 // Is the shift amount constant?
5744 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5748 // Is the and mask vector all constant?
5750 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5753 // Is C1 == ~C2, taking into account how much one can shift elements of a
5755 uint64_t C2 = C2node->getZExtValue();
5756 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5757 if (C2 > ElemSizeInBits)
5759 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5760 if ((C1 & ElemMask) != (~C2 & ElemMask))
5763 SDValue X = And.getOperand(0);
5764 SDValue Y = Shift.getOperand(0);
5767 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5769 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5770 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5771 Shift.getOperand(1));
5773 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5774 DEBUG(N->dump(&DAG));
5775 DEBUG(dbgs() << "into: \n");
5776 DEBUG(ResultSLI->dump(&DAG));
5782 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5783 SelectionDAG &DAG) const {
5784 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5785 if (EnableAArch64SlrGeneration) {
5786 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5791 BuildVectorSDNode *BVN =
5792 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5793 SDValue LHS = Op.getOperand(1);
5795 EVT VT = Op.getValueType();
5797 // OR commutes, so try swapping the operands.
5799 LHS = Op.getOperand(0);
5800 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5805 APInt CnstBits(VT.getSizeInBits(), 0);
5806 APInt UndefBits(VT.getSizeInBits(), 0);
5807 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5808 // We make use of a little bit of goto ickiness in order to avoid having to
5809 // duplicate the immediate matching logic for the undef toggled case.
5810 bool SecondTry = false;
5813 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5814 CnstBits = CnstBits.zextOrTrunc(64);
5815 uint64_t CnstVal = CnstBits.getZExtValue();
5817 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5818 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5819 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5820 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5821 DAG.getConstant(CnstVal, dl, MVT::i32),
5822 DAG.getConstant(0, dl, MVT::i32));
5823 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5826 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5827 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5828 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5829 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5830 DAG.getConstant(CnstVal, dl, MVT::i32),
5831 DAG.getConstant(8, dl, MVT::i32));
5832 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5835 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5836 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5837 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5838 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5839 DAG.getConstant(CnstVal, dl, MVT::i32),
5840 DAG.getConstant(16, dl, MVT::i32));
5841 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5844 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5845 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5846 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5847 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5848 DAG.getConstant(CnstVal, dl, MVT::i32),
5849 DAG.getConstant(24, dl, MVT::i32));
5850 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5853 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5854 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5855 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5856 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5857 DAG.getConstant(CnstVal, dl, MVT::i32),
5858 DAG.getConstant(0, dl, MVT::i32));
5859 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5862 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5863 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5864 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5865 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5866 DAG.getConstant(CnstVal, dl, MVT::i32),
5867 DAG.getConstant(8, dl, MVT::i32));
5868 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5875 CnstBits = UndefBits;
5879 // We can always fall back to a non-immediate OR.
5884 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5885 // be truncated to fit element width.
5886 static SDValue NormalizeBuildVector(SDValue Op,
5887 SelectionDAG &DAG) {
5888 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5890 EVT VT = Op.getValueType();
5891 EVT EltTy= VT.getVectorElementType();
5893 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5896 SmallVector<SDValue, 16> Ops;
5897 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5898 SDValue Lane = Op.getOperand(I);
5899 if (Lane.getOpcode() == ISD::Constant) {
5900 APInt LowBits(EltTy.getSizeInBits(),
5901 cast<ConstantSDNode>(Lane)->getZExtValue());
5902 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5904 Ops.push_back(Lane);
5906 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5909 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5910 SelectionDAG &DAG) const {
5912 EVT VT = Op.getValueType();
5913 Op = NormalizeBuildVector(Op, DAG);
5914 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5916 APInt CnstBits(VT.getSizeInBits(), 0);
5917 APInt UndefBits(VT.getSizeInBits(), 0);
5918 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5919 // We make use of a little bit of goto ickiness in order to avoid having to
5920 // duplicate the immediate matching logic for the undef toggled case.
5921 bool SecondTry = false;
5924 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5925 CnstBits = CnstBits.zextOrTrunc(64);
5926 uint64_t CnstVal = CnstBits.getZExtValue();
5928 // Certain magic vector constants (used to express things like NOT
5929 // and NEG) are passed through unmodified. This allows codegen patterns
5930 // for these operations to match. Special-purpose patterns will lower
5931 // these immediates to MOVIs if it proves necessary.
5932 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5935 // The many faces of MOVI...
5936 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5937 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5938 if (VT.getSizeInBits() == 128) {
5939 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5940 DAG.getConstant(CnstVal, dl, MVT::i32));
5941 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5944 // Support the V64 version via subregister insertion.
5945 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5946 DAG.getConstant(CnstVal, dl, MVT::i32));
5947 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5950 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5951 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5952 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5953 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5954 DAG.getConstant(CnstVal, dl, MVT::i32),
5955 DAG.getConstant(0, dl, MVT::i32));
5956 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5959 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5960 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5961 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5962 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5963 DAG.getConstant(CnstVal, dl, MVT::i32),
5964 DAG.getConstant(8, dl, MVT::i32));
5965 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5968 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5969 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5970 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5971 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5972 DAG.getConstant(CnstVal, dl, MVT::i32),
5973 DAG.getConstant(16, dl, MVT::i32));
5974 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5977 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5978 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5979 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5980 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5981 DAG.getConstant(CnstVal, dl, MVT::i32),
5982 DAG.getConstant(24, dl, MVT::i32));
5983 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5986 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5987 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5988 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5989 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5990 DAG.getConstant(CnstVal, dl, MVT::i32),
5991 DAG.getConstant(0, dl, MVT::i32));
5992 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5995 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5996 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5997 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5998 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5999 DAG.getConstant(CnstVal, dl, MVT::i32),
6000 DAG.getConstant(8, dl, MVT::i32));
6001 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6004 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6005 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6006 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6007 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6008 DAG.getConstant(CnstVal, dl, MVT::i32),
6009 DAG.getConstant(264, dl, MVT::i32));
6010 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6013 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6014 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6015 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6016 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6017 DAG.getConstant(CnstVal, dl, MVT::i32),
6018 DAG.getConstant(272, dl, MVT::i32));
6019 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6022 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
6023 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
6024 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6025 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
6026 DAG.getConstant(CnstVal, dl, MVT::i32));
6027 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6030 // The few faces of FMOV...
6031 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
6032 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
6033 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6034 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
6035 DAG.getConstant(CnstVal, dl, MVT::i32));
6036 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6039 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
6040 VT.getSizeInBits() == 128) {
6041 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
6042 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
6043 DAG.getConstant(CnstVal, dl, MVT::i32));
6044 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6047 // The many faces of MVNI...
6049 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6050 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6051 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6052 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6053 DAG.getConstant(CnstVal, dl, MVT::i32),
6054 DAG.getConstant(0, dl, MVT::i32));
6055 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6058 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6059 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6060 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6061 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6062 DAG.getConstant(CnstVal, dl, MVT::i32),
6063 DAG.getConstant(8, dl, MVT::i32));
6064 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6067 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6068 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6069 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6070 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6071 DAG.getConstant(CnstVal, dl, MVT::i32),
6072 DAG.getConstant(16, dl, MVT::i32));
6073 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6076 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6077 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6078 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6079 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6080 DAG.getConstant(CnstVal, dl, MVT::i32),
6081 DAG.getConstant(24, dl, MVT::i32));
6082 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6085 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6086 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6087 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6088 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6089 DAG.getConstant(CnstVal, dl, MVT::i32),
6090 DAG.getConstant(0, dl, MVT::i32));
6091 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6094 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6095 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6096 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6097 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6098 DAG.getConstant(CnstVal, dl, MVT::i32),
6099 DAG.getConstant(8, dl, MVT::i32));
6100 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6103 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6104 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6105 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6106 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6107 DAG.getConstant(CnstVal, dl, MVT::i32),
6108 DAG.getConstant(264, dl, MVT::i32));
6109 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6112 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6113 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6114 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6115 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6116 DAG.getConstant(CnstVal, dl, MVT::i32),
6117 DAG.getConstant(272, dl, MVT::i32));
6118 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6125 CnstBits = UndefBits;
6130 // Scan through the operands to find some interesting properties we can
6132 // 1) If only one value is used, we can use a DUP, or
6133 // 2) if only the low element is not undef, we can just insert that, or
6134 // 3) if only one constant value is used (w/ some non-constant lanes),
6135 // we can splat the constant value into the whole vector then fill
6136 // in the non-constant lanes.
6137 // 4) FIXME: If different constant values are used, but we can intelligently
6138 // select the values we'll be overwriting for the non-constant
6139 // lanes such that we can directly materialize the vector
6140 // some other way (MOVI, e.g.), we can be sneaky.
6141 unsigned NumElts = VT.getVectorNumElements();
6142 bool isOnlyLowElement = true;
6143 bool usesOnlyOneValue = true;
6144 bool usesOnlyOneConstantValue = true;
6145 bool isConstant = true;
6146 unsigned NumConstantLanes = 0;
6148 SDValue ConstantValue;
6149 for (unsigned i = 0; i < NumElts; ++i) {
6150 SDValue V = Op.getOperand(i);
6151 if (V.getOpcode() == ISD::UNDEF)
6154 isOnlyLowElement = false;
6155 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6158 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
6160 if (!ConstantValue.getNode())
6162 else if (ConstantValue != V)
6163 usesOnlyOneConstantValue = false;
6166 if (!Value.getNode())
6168 else if (V != Value)
6169 usesOnlyOneValue = false;
6172 if (!Value.getNode())
6173 return DAG.getUNDEF(VT);
6175 if (isOnlyLowElement)
6176 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6178 // Use DUP for non-constant splats. For f32 constant splats, reduce to
6179 // i32 and try again.
6180 if (usesOnlyOneValue) {
6182 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6183 Value.getValueType() != VT)
6184 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6186 // This is actually a DUPLANExx operation, which keeps everything vectory.
6188 // DUPLANE works on 128-bit vectors, widen it if necessary.
6189 SDValue Lane = Value.getOperand(1);
6190 Value = Value.getOperand(0);
6191 if (Value.getValueType().getSizeInBits() == 64)
6192 Value = WidenVector(Value, DAG);
6194 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6195 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6198 if (VT.getVectorElementType().isFloatingPoint()) {
6199 SmallVector<SDValue, 8> Ops;
6200 EVT EltTy = VT.getVectorElementType();
6201 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
6202 "Unsupported floating-point vector type");
6203 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
6204 for (unsigned i = 0; i < NumElts; ++i)
6205 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
6206 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
6207 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
6208 Val = LowerBUILD_VECTOR(Val, DAG);
6210 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6214 // If there was only one constant value used and for more than one lane,
6215 // start by splatting that value, then replace the non-constant lanes. This
6216 // is better than the default, which will perform a separate initialization
6218 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6219 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6220 // Now insert the non-constant lanes.
6221 for (unsigned i = 0; i < NumElts; ++i) {
6222 SDValue V = Op.getOperand(i);
6223 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6224 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6225 // Note that type legalization likely mucked about with the VT of the
6226 // source operand, so we may have to convert it here before inserting.
6227 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6233 // If all elements are constants and the case above didn't get hit, fall back
6234 // to the default expansion, which will generate a load from the constant
6239 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6241 SDValue shuffle = ReconstructShuffle(Op, DAG);
6242 if (shuffle != SDValue())
6246 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6247 // know the default expansion would otherwise fall back on something even
6248 // worse. For a vector with one or two non-undef values, that's
6249 // scalar_to_vector for the elements followed by a shuffle (provided the
6250 // shuffle is valid for the target) and materialization element by element
6251 // on the stack followed by a load for everything else.
6252 if (!isConstant && !usesOnlyOneValue) {
6253 SDValue Vec = DAG.getUNDEF(VT);
6254 SDValue Op0 = Op.getOperand(0);
6255 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6257 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6258 // a) Avoid a RMW dependency on the full vector register, and
6259 // b) Allow the register coalescer to fold away the copy if the
6260 // value is already in an S or D register.
6261 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6262 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6264 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6265 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6266 Vec = SDValue(N, 0);
6269 for (; i < NumElts; ++i) {
6270 SDValue V = Op.getOperand(i);
6271 if (V.getOpcode() == ISD::UNDEF)
6273 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6274 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6279 // Just use the default expansion. We failed to find a better alternative.
6283 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6284 SelectionDAG &DAG) const {
6285 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6287 // Check for non-constant or out of range lane.
6288 EVT VT = Op.getOperand(0).getValueType();
6289 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6290 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6294 // Insertion/extraction are legal for V128 types.
6295 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6296 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6300 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6301 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6304 // For V64 types, we perform insertion by expanding the value
6305 // to a V128 type and perform the insertion on that.
6307 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6308 EVT WideTy = WideVec.getValueType();
6310 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6311 Op.getOperand(1), Op.getOperand(2));
6312 // Re-narrow the resultant vector.
6313 return NarrowVector(Node, DAG);
6317 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6318 SelectionDAG &DAG) const {
6319 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6321 // Check for non-constant or out of range lane.
6322 EVT VT = Op.getOperand(0).getValueType();
6323 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6324 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6328 // Insertion/extraction are legal for V128 types.
6329 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6330 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6334 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6335 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6338 // For V64 types, we perform extraction by expanding the value
6339 // to a V128 type and perform the extraction on that.
6341 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6342 EVT WideTy = WideVec.getValueType();
6344 EVT ExtrTy = WideTy.getVectorElementType();
6345 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6348 // For extractions, we just return the result directly.
6349 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6353 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6354 SelectionDAG &DAG) const {
6355 EVT VT = Op.getOperand(0).getValueType();
6361 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6364 unsigned Val = Cst->getZExtValue();
6366 unsigned Size = Op.getValueType().getSizeInBits();
6370 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6373 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6376 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6379 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6382 llvm_unreachable("Unexpected vector type in extract_subvector!");
6385 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6387 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6393 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6395 if (VT.getVectorNumElements() == 4 &&
6396 (VT.is128BitVector() || VT.is64BitVector())) {
6397 unsigned PFIndexes[4];
6398 for (unsigned i = 0; i != 4; ++i) {
6402 PFIndexes[i] = M[i];
6405 // Compute the index in the perfect shuffle table.
6406 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6407 PFIndexes[2] * 9 + PFIndexes[3];
6408 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6409 unsigned Cost = (PFEntry >> 30);
6417 unsigned DummyUnsigned;
6419 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6420 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6421 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6422 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6423 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6424 isZIPMask(M, VT, DummyUnsigned) ||
6425 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6426 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6427 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6428 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6429 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6432 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6433 /// operand of a vector shift operation, where all the elements of the
6434 /// build_vector must have the same constant integer value.
6435 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6436 // Ignore bit_converts.
6437 while (Op.getOpcode() == ISD::BITCAST)
6438 Op = Op.getOperand(0);
6439 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6440 APInt SplatBits, SplatUndef;
6441 unsigned SplatBitSize;
6443 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6444 HasAnyUndefs, ElementBits) ||
6445 SplatBitSize > ElementBits)
6447 Cnt = SplatBits.getSExtValue();
6451 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6452 /// operand of a vector shift left operation. That value must be in the range:
6453 /// 0 <= Value < ElementBits for a left shift; or
6454 /// 0 <= Value <= ElementBits for a long left shift.
6455 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6456 assert(VT.isVector() && "vector shift count is not a vector type");
6457 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6458 if (!getVShiftImm(Op, ElementBits, Cnt))
6460 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6463 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6464 /// operand of a vector shift right operation. The value must be in the range:
6465 /// 1 <= Value <= ElementBits for a right shift; or
6466 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6467 assert(VT.isVector() && "vector shift count is not a vector type");
6468 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6469 if (!getVShiftImm(Op, ElementBits, Cnt))
6471 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6474 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6475 SelectionDAG &DAG) const {
6476 EVT VT = Op.getValueType();
6480 if (!Op.getOperand(1).getValueType().isVector())
6482 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6484 switch (Op.getOpcode()) {
6486 llvm_unreachable("unexpected shift opcode");
6489 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6490 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6491 DAG.getConstant(Cnt, DL, MVT::i32));
6492 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6493 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6495 Op.getOperand(0), Op.getOperand(1));
6498 // Right shift immediate
6499 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6501 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6502 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6503 DAG.getConstant(Cnt, DL, MVT::i32));
6506 // Right shift register. Note, there is not a shift right register
6507 // instruction, but the shift left register instruction takes a signed
6508 // value, where negative numbers specify a right shift.
6509 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6510 : Intrinsic::aarch64_neon_ushl;
6511 // negate the shift amount
6512 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6513 SDValue NegShiftLeft =
6514 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6515 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6517 return NegShiftLeft;
6523 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6524 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6525 SDLoc dl, SelectionDAG &DAG) {
6526 EVT SrcVT = LHS.getValueType();
6527 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6528 "function only supposed to emit natural comparisons");
6530 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6531 APInt CnstBits(VT.getSizeInBits(), 0);
6532 APInt UndefBits(VT.getSizeInBits(), 0);
6533 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6534 bool IsZero = IsCnst && (CnstBits == 0);
6536 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6540 case AArch64CC::NE: {
6543 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6545 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6546 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6550 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6551 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6554 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6555 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6558 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6559 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6562 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6563 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6567 // If we ignore NaNs then we can use to the MI implementation.
6571 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6572 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6579 case AArch64CC::NE: {
6582 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6584 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6585 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6589 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6590 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6593 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6594 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6597 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6598 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6601 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6602 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6604 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6606 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6609 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6610 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6612 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6614 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6618 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6619 SelectionDAG &DAG) const {
6620 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6621 SDValue LHS = Op.getOperand(0);
6622 SDValue RHS = Op.getOperand(1);
6623 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6626 if (LHS.getValueType().getVectorElementType().isInteger()) {
6627 assert(LHS.getValueType() == RHS.getValueType());
6628 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6630 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6631 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6634 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6635 LHS.getValueType().getVectorElementType() == MVT::f64);
6637 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6638 // clean. Some of them require two branches to implement.
6639 AArch64CC::CondCode CC1, CC2;
6641 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6643 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6645 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6649 if (CC2 != AArch64CC::AL) {
6651 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6652 if (!Cmp2.getNode())
6655 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6658 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6661 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6666 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6667 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6668 /// specified in the intrinsic calls.
6669 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6671 unsigned Intrinsic) const {
6672 auto &DL = I.getModule()->getDataLayout();
6673 switch (Intrinsic) {
6674 case Intrinsic::aarch64_neon_ld2:
6675 case Intrinsic::aarch64_neon_ld3:
6676 case Intrinsic::aarch64_neon_ld4:
6677 case Intrinsic::aarch64_neon_ld1x2:
6678 case Intrinsic::aarch64_neon_ld1x3:
6679 case Intrinsic::aarch64_neon_ld1x4:
6680 case Intrinsic::aarch64_neon_ld2lane:
6681 case Intrinsic::aarch64_neon_ld3lane:
6682 case Intrinsic::aarch64_neon_ld4lane:
6683 case Intrinsic::aarch64_neon_ld2r:
6684 case Intrinsic::aarch64_neon_ld3r:
6685 case Intrinsic::aarch64_neon_ld4r: {
6686 Info.opc = ISD::INTRINSIC_W_CHAIN;
6687 // Conservatively set memVT to the entire set of vectors loaded.
6688 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
6689 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6690 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6693 Info.vol = false; // volatile loads with NEON intrinsics not supported
6694 Info.readMem = true;
6695 Info.writeMem = false;
6698 case Intrinsic::aarch64_neon_st2:
6699 case Intrinsic::aarch64_neon_st3:
6700 case Intrinsic::aarch64_neon_st4:
6701 case Intrinsic::aarch64_neon_st1x2:
6702 case Intrinsic::aarch64_neon_st1x3:
6703 case Intrinsic::aarch64_neon_st1x4:
6704 case Intrinsic::aarch64_neon_st2lane:
6705 case Intrinsic::aarch64_neon_st3lane:
6706 case Intrinsic::aarch64_neon_st4lane: {
6707 Info.opc = ISD::INTRINSIC_VOID;
6708 // Conservatively set memVT to the entire set of vectors stored.
6709 unsigned NumElts = 0;
6710 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6711 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6712 if (!ArgTy->isVectorTy())
6714 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
6716 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6717 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6720 Info.vol = false; // volatile stores with NEON intrinsics not supported
6721 Info.readMem = false;
6722 Info.writeMem = true;
6725 case Intrinsic::aarch64_ldaxr:
6726 case Intrinsic::aarch64_ldxr: {
6727 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6728 Info.opc = ISD::INTRINSIC_W_CHAIN;
6729 Info.memVT = MVT::getVT(PtrTy->getElementType());
6730 Info.ptrVal = I.getArgOperand(0);
6732 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6734 Info.readMem = true;
6735 Info.writeMem = false;
6738 case Intrinsic::aarch64_stlxr:
6739 case Intrinsic::aarch64_stxr: {
6740 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6741 Info.opc = ISD::INTRINSIC_W_CHAIN;
6742 Info.memVT = MVT::getVT(PtrTy->getElementType());
6743 Info.ptrVal = I.getArgOperand(1);
6745 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6747 Info.readMem = false;
6748 Info.writeMem = true;
6751 case Intrinsic::aarch64_ldaxp:
6752 case Intrinsic::aarch64_ldxp: {
6753 Info.opc = ISD::INTRINSIC_W_CHAIN;
6754 Info.memVT = MVT::i128;
6755 Info.ptrVal = I.getArgOperand(0);
6759 Info.readMem = true;
6760 Info.writeMem = false;
6763 case Intrinsic::aarch64_stlxp:
6764 case Intrinsic::aarch64_stxp: {
6765 Info.opc = ISD::INTRINSIC_W_CHAIN;
6766 Info.memVT = MVT::i128;
6767 Info.ptrVal = I.getArgOperand(2);
6771 Info.readMem = false;
6772 Info.writeMem = true;
6782 // Truncations from 64-bit GPR to 32-bit GPR is free.
6783 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6784 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6786 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6787 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6788 return NumBits1 > NumBits2;
6790 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6791 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6793 unsigned NumBits1 = VT1.getSizeInBits();
6794 unsigned NumBits2 = VT2.getSizeInBits();
6795 return NumBits1 > NumBits2;
6798 /// Check if it is profitable to hoist instruction in then/else to if.
6799 /// Not profitable if I and it's user can form a FMA instruction
6800 /// because we prefer FMSUB/FMADD.
6801 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6802 if (I->getOpcode() != Instruction::FMul)
6805 if (I->getNumUses() != 1)
6808 Instruction *User = I->user_back();
6811 !(User->getOpcode() == Instruction::FSub ||
6812 User->getOpcode() == Instruction::FAdd))
6815 const TargetOptions &Options = getTargetMachine().Options;
6816 const DataLayout &DL = I->getModule()->getDataLayout();
6817 EVT VT = getValueType(DL, User->getOperand(0)->getType());
6819 if (isFMAFasterThanFMulAndFAdd(VT) &&
6820 isOperationLegalOrCustom(ISD::FMA, VT) &&
6821 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6827 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6829 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6830 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6832 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6833 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6834 return NumBits1 == 32 && NumBits2 == 64;
6836 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6837 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6839 unsigned NumBits1 = VT1.getSizeInBits();
6840 unsigned NumBits2 = VT2.getSizeInBits();
6841 return NumBits1 == 32 && NumBits2 == 64;
6844 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6845 EVT VT1 = Val.getValueType();
6846 if (isZExtFree(VT1, VT2)) {
6850 if (Val.getOpcode() != ISD::LOAD)
6853 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6854 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6855 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6856 VT1.getSizeInBits() <= 32);
6859 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6860 if (isa<FPExtInst>(Ext))
6863 // Vector types are next free.
6864 if (Ext->getType()->isVectorTy())
6867 for (const Use &U : Ext->uses()) {
6868 // The extension is free if we can fold it with a left shift in an
6869 // addressing mode or an arithmetic operation: add, sub, and cmp.
6871 // Is there a shift?
6872 const Instruction *Instr = cast<Instruction>(U.getUser());
6874 // Is this a constant shift?
6875 switch (Instr->getOpcode()) {
6876 case Instruction::Shl:
6877 if (!isa<ConstantInt>(Instr->getOperand(1)))
6880 case Instruction::GetElementPtr: {
6881 gep_type_iterator GTI = gep_type_begin(Instr);
6882 auto &DL = Ext->getModule()->getDataLayout();
6883 std::advance(GTI, U.getOperandNo());
6885 // This extension will end up with a shift because of the scaling factor.
6886 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6887 // Get the shift amount based on the scaling factor:
6888 // log2(sizeof(IdxTy)) - log2(8).
6890 countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy)) - 3;
6891 // Is the constant foldable in the shift of the addressing mode?
6892 // I.e., shift amount is between 1 and 4 inclusive.
6893 if (ShiftAmt == 0 || ShiftAmt > 4)
6897 case Instruction::Trunc:
6898 // Check if this is a noop.
6899 // trunc(sext ty1 to ty2) to ty1.
6900 if (Instr->getType() == Ext->getOperand(0)->getType())
6907 // At this point we can use the bfm family, so this extension is free
6913 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6914 unsigned &RequiredAligment) const {
6915 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6917 // Cyclone supports unaligned accesses.
6918 RequiredAligment = 0;
6919 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6920 return NumBits == 32 || NumBits == 64;
6923 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6924 unsigned &RequiredAligment) const {
6925 if (!LoadedType.isSimple() ||
6926 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6928 // Cyclone supports unaligned accesses.
6929 RequiredAligment = 0;
6930 unsigned NumBits = LoadedType.getSizeInBits();
6931 return NumBits == 32 || NumBits == 64;
6934 /// \brief Lower an interleaved load into a ldN intrinsic.
6936 /// E.g. Lower an interleaved load (Factor = 2):
6937 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6938 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6939 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6942 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6943 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6944 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6945 bool AArch64TargetLowering::lowerInterleavedLoad(
6946 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6947 ArrayRef<unsigned> Indices, unsigned Factor) const {
6948 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6949 "Invalid interleave factor");
6950 assert(!Shuffles.empty() && "Empty shufflevector input");
6951 assert(Shuffles.size() == Indices.size() &&
6952 "Unmatched number of shufflevectors and indices");
6954 const DataLayout &DL = LI->getModule()->getDataLayout();
6956 VectorType *VecTy = Shuffles[0]->getType();
6957 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
6959 // Skip illegal vector types.
6960 if (VecSize != 64 && VecSize != 128)
6963 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6964 // load integer vectors first and then convert to pointer vectors.
6965 Type *EltTy = VecTy->getVectorElementType();
6966 if (EltTy->isPointerTy())
6968 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
6970 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
6971 Type *Tys[2] = {VecTy, PtrTy};
6972 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
6973 Intrinsic::aarch64_neon_ld3,
6974 Intrinsic::aarch64_neon_ld4};
6976 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
6978 IRBuilder<> Builder(LI);
6979 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
6981 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
6983 // Replace uses of each shufflevector with the corresponding vector loaded
6985 for (unsigned i = 0; i < Shuffles.size(); i++) {
6986 ShuffleVectorInst *SVI = Shuffles[i];
6987 unsigned Index = Indices[i];
6989 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
6991 // Convert the integer vector to pointer vector if the element is pointer.
6992 if (EltTy->isPointerTy())
6993 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
6995 SVI->replaceAllUsesWith(SubVec);
7001 /// \brief Get a mask consisting of sequential integers starting from \p Start.
7003 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
7004 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
7006 SmallVector<Constant *, 16> Mask;
7007 for (unsigned i = 0; i < NumElts; i++)
7008 Mask.push_back(Builder.getInt32(Start + i));
7010 return ConstantVector::get(Mask);
7013 /// \brief Lower an interleaved store into a stN intrinsic.
7015 /// E.g. Lower an interleaved store (Factor = 3):
7016 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7017 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
7018 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7021 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7022 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7023 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7024 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7026 /// Note that the new shufflevectors will be removed and we'll only generate one
7027 /// st3 instruction in CodeGen.
7028 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7029 ShuffleVectorInst *SVI,
7030 unsigned Factor) const {
7031 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7032 "Invalid interleave factor");
7034 VectorType *VecTy = SVI->getType();
7035 assert(VecTy->getVectorNumElements() % Factor == 0 &&
7036 "Invalid interleaved store");
7038 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
7039 Type *EltTy = VecTy->getVectorElementType();
7040 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
7042 const DataLayout &DL = SI->getModule()->getDataLayout();
7043 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
7045 // Skip illegal vector types.
7046 if (SubVecSize != 64 && SubVecSize != 128)
7049 Value *Op0 = SVI->getOperand(0);
7050 Value *Op1 = SVI->getOperand(1);
7051 IRBuilder<> Builder(SI);
7053 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
7054 // vectors to integer vectors.
7055 if (EltTy->isPointerTy()) {
7056 Type *IntTy = DL.getIntPtrType(EltTy);
7057 unsigned NumOpElts =
7058 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
7060 // Convert to the corresponding integer vector.
7061 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
7062 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
7063 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
7065 SubVecTy = VectorType::get(IntTy, NumSubElts);
7068 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
7069 Type *Tys[2] = {SubVecTy, PtrTy};
7070 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
7071 Intrinsic::aarch64_neon_st3,
7072 Intrinsic::aarch64_neon_st4};
7074 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
7076 SmallVector<Value *, 5> Ops;
7078 // Split the shufflevector operands into sub vectors for the new stN call.
7079 for (unsigned i = 0; i < Factor; i++)
7080 Ops.push_back(Builder.CreateShuffleVector(
7081 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
7083 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
7084 Builder.CreateCall(StNFunc, Ops);
7088 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
7089 unsigned AlignCheck) {
7090 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
7091 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7094 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7095 unsigned SrcAlign, bool IsMemset,
7098 MachineFunction &MF) const {
7099 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
7100 // instruction to materialize the v2i64 zero and one store (with restrictive
7101 // addressing mode). Just do two i64 store of zero-registers.
7103 const Function *F = MF.getFunction();
7104 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
7105 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
7106 (memOpAlign(SrcAlign, DstAlign, 16) ||
7107 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
7111 (memOpAlign(SrcAlign, DstAlign, 8) ||
7112 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
7116 (memOpAlign(SrcAlign, DstAlign, 4) ||
7117 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
7123 // 12-bit optionally shifted immediates are legal for adds.
7124 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7125 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
7130 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
7131 // immediates is the same as for an add or a sub.
7132 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7135 return isLegalAddImmediate(Immed);
7138 /// isLegalAddressingMode - Return true if the addressing mode represented
7139 /// by AM is legal for this target, for a load/store of the specified type.
7140 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7141 const AddrMode &AM, Type *Ty,
7142 unsigned AS) const {
7143 // AArch64 has five basic addressing modes:
7145 // reg + 9-bit signed offset
7146 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
7148 // reg + SIZE_IN_BYTES * reg
7150 // No global is ever allowed as a base.
7154 // No reg+reg+imm addressing.
7155 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
7158 // check reg + imm case:
7159 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
7160 uint64_t NumBytes = 0;
7161 if (Ty->isSized()) {
7162 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
7163 NumBytes = NumBits / 8;
7164 if (!isPowerOf2_64(NumBits))
7169 int64_t Offset = AM.BaseOffs;
7171 // 9-bit signed offset
7172 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
7175 // 12-bit unsigned offset
7176 unsigned shift = Log2_64(NumBytes);
7177 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
7178 // Must be a multiple of NumBytes (NumBytes is a power of 2)
7179 (Offset >> shift) << shift == Offset)
7184 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
7186 if (!AM.Scale || AM.Scale == 1 ||
7187 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
7192 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7193 const AddrMode &AM, Type *Ty,
7194 unsigned AS) const {
7195 // Scaling factors are not free at all.
7196 // Operands | Rt Latency
7197 // -------------------------------------------
7199 // -------------------------------------------
7200 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
7201 // Rt, [Xn, Wm, <extend> #imm] |
7202 if (isLegalAddressingMode(DL, AM, Ty, AS))
7203 // Scale represents reg2 * scale, thus account for 1 if
7204 // it is not equal to 0 or 1.
7205 return AM.Scale != 0 && AM.Scale != 1;
7209 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7210 VT = VT.getScalarType();
7215 switch (VT.getSimpleVT().SimpleTy) {
7227 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7228 // LR is a callee-save register, but we must treat it as clobbered by any call
7229 // site. Hence we include LR in the scratch registers, which are in turn added
7230 // as implicit-defs for stackmaps and patchpoints.
7231 static const MCPhysReg ScratchRegs[] = {
7232 AArch64::X16, AArch64::X17, AArch64::LR, 0
7238 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7239 EVT VT = N->getValueType(0);
7240 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
7241 // it with shift to let it be lowered to UBFX.
7242 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7243 isa<ConstantSDNode>(N->getOperand(1))) {
7244 uint64_t TruncMask = N->getConstantOperandVal(1);
7245 if (isMask_64(TruncMask) &&
7246 N->getOperand(0).getOpcode() == ISD::SRL &&
7247 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7253 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7255 assert(Ty->isIntegerTy());
7257 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7261 int64_t Val = Imm.getSExtValue();
7262 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7265 if ((int64_t)Val < 0)
7268 Val &= (1LL << 32) - 1;
7270 unsigned LZ = countLeadingZeros((uint64_t)Val);
7271 unsigned Shift = (63 - LZ) / 16;
7272 // MOVZ is free so return true for one or fewer MOVK.
7276 // Generate SUBS and CSEL for integer abs.
7277 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7278 EVT VT = N->getValueType(0);
7280 SDValue N0 = N->getOperand(0);
7281 SDValue N1 = N->getOperand(1);
7284 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7285 // and change it to SUB and CSEL.
7286 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7287 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7288 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7289 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7290 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7291 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7293 // Generate SUBS & CSEL.
7295 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7296 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7297 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7298 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7299 SDValue(Cmp.getNode(), 1));
7304 // performXorCombine - Attempts to handle integer ABS.
7305 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7306 TargetLowering::DAGCombinerInfo &DCI,
7307 const AArch64Subtarget *Subtarget) {
7308 if (DCI.isBeforeLegalizeOps())
7311 return performIntegerAbsCombine(N, DAG);
7315 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7317 std::vector<SDNode *> *Created) const {
7318 // fold (sdiv X, pow2)
7319 EVT VT = N->getValueType(0);
7320 if ((VT != MVT::i32 && VT != MVT::i64) ||
7321 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7325 SDValue N0 = N->getOperand(0);
7326 unsigned Lg2 = Divisor.countTrailingZeros();
7327 SDValue Zero = DAG.getConstant(0, DL, VT);
7328 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7330 // Add (N0 < 0) ? Pow2 - 1 : 0;
7332 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7333 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7334 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7337 Created->push_back(Cmp.getNode());
7338 Created->push_back(Add.getNode());
7339 Created->push_back(CSel.getNode());
7344 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7346 // If we're dividing by a positive value, we're done. Otherwise, we must
7347 // negate the result.
7348 if (Divisor.isNonNegative())
7352 Created->push_back(SRA.getNode());
7353 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7356 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7357 TargetLowering::DAGCombinerInfo &DCI,
7358 const AArch64Subtarget *Subtarget) {
7359 if (DCI.isBeforeLegalizeOps())
7362 // Multiplication of a power of two plus/minus one can be done more
7363 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7364 // future CPUs have a cheaper MADD instruction, this may need to be
7365 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7366 // 64-bit is 5 cycles, so this is always a win.
7367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7368 APInt Value = C->getAPIntValue();
7369 EVT VT = N->getValueType(0);
7371 if (Value.isNonNegative()) {
7372 // (mul x, 2^N + 1) => (add (shl x, N), x)
7373 APInt VM1 = Value - 1;
7374 if (VM1.isPowerOf2()) {
7375 SDValue ShiftedVal =
7376 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7377 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7378 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7381 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7382 APInt VP1 = Value + 1;
7383 if (VP1.isPowerOf2()) {
7384 SDValue ShiftedVal =
7385 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7386 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7387 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7391 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7392 APInt VNP1 = -Value + 1;
7393 if (VNP1.isPowerOf2()) {
7394 SDValue ShiftedVal =
7395 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7396 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7397 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7400 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7401 APInt VNM1 = -Value - 1;
7402 if (VNM1.isPowerOf2()) {
7403 SDValue ShiftedVal =
7404 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7405 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7407 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7408 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7415 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7416 SelectionDAG &DAG) {
7417 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7418 // optimize away operation when it's from a constant.
7420 // The general transformation is:
7421 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7422 // AND(VECTOR_CMP(x,y), constant2)
7423 // constant2 = UNARYOP(constant)
7425 // Early exit if this isn't a vector operation, the operand of the
7426 // unary operation isn't a bitwise AND, or if the sizes of the operations
7428 EVT VT = N->getValueType(0);
7429 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7430 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7431 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7434 // Now check that the other operand of the AND is a constant. We could
7435 // make the transformation for non-constant splats as well, but it's unclear
7436 // that would be a benefit as it would not eliminate any operations, just
7437 // perform one more step in scalar code before moving to the vector unit.
7438 if (BuildVectorSDNode *BV =
7439 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7440 // Bail out if the vector isn't a constant.
7441 if (!BV->isConstant())
7444 // Everything checks out. Build up the new and improved node.
7446 EVT IntVT = BV->getValueType(0);
7447 // Create a new constant of the appropriate type for the transformed
7449 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7450 // The AND node needs bitcasts to/from an integer vector type around it.
7451 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7452 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7453 N->getOperand(0)->getOperand(0), MaskConst);
7454 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7461 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7462 const AArch64Subtarget *Subtarget) {
7463 // First try to optimize away the conversion when it's conditionally from
7464 // a constant. Vectors only.
7465 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7466 if (Res != SDValue())
7469 EVT VT = N->getValueType(0);
7470 if (VT != MVT::f32 && VT != MVT::f64)
7473 // Only optimize when the source and destination types have the same width.
7474 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7477 // If the result of an integer load is only used by an integer-to-float
7478 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7479 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7480 SDValue N0 = N->getOperand(0);
7481 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7482 // Do not change the width of a volatile load.
7483 !cast<LoadSDNode>(N0)->isVolatile()) {
7484 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7485 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7486 LN0->getPointerInfo(), LN0->isVolatile(),
7487 LN0->isNonTemporal(), LN0->isInvariant(),
7488 LN0->getAlignment());
7490 // Make sure successors of the original load stay after it by updating them
7491 // to use the new Chain.
7492 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7495 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7496 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7502 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7503 /// searches for and classifies those shifts.
7504 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7506 if (N.getOpcode() == ISD::SHL)
7508 else if (N.getOpcode() == ISD::SRL)
7513 if (!isa<ConstantSDNode>(N.getOperand(1)))
7516 ShiftAmount = N->getConstantOperandVal(1);
7517 Src = N->getOperand(0);
7521 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7522 /// registers viewed as a high/low pair. This function looks for the pattern:
7523 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7524 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7526 static SDValue tryCombineToEXTR(SDNode *N,
7527 TargetLowering::DAGCombinerInfo &DCI) {
7528 SelectionDAG &DAG = DCI.DAG;
7530 EVT VT = N->getValueType(0);
7532 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7534 if (VT != MVT::i32 && VT != MVT::i64)
7538 uint32_t ShiftLHS = 0;
7540 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7544 uint32_t ShiftRHS = 0;
7546 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7549 // If they're both trying to come from the high part of the register, they're
7550 // not really an EXTR.
7551 if (LHSFromHi == RHSFromHi)
7554 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7558 std::swap(LHS, RHS);
7559 std::swap(ShiftLHS, ShiftRHS);
7562 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7563 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7566 static SDValue tryCombineToBSL(SDNode *N,
7567 TargetLowering::DAGCombinerInfo &DCI) {
7568 EVT VT = N->getValueType(0);
7569 SelectionDAG &DAG = DCI.DAG;
7575 SDValue N0 = N->getOperand(0);
7576 if (N0.getOpcode() != ISD::AND)
7579 SDValue N1 = N->getOperand(1);
7580 if (N1.getOpcode() != ISD::AND)
7583 // We only have to look for constant vectors here since the general, variable
7584 // case can be handled in TableGen.
7585 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7586 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7587 for (int i = 1; i >= 0; --i)
7588 for (int j = 1; j >= 0; --j) {
7589 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7590 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7594 bool FoundMatch = true;
7595 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7596 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7597 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7599 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7606 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7607 N0->getOperand(1 - i), N1->getOperand(1 - j));
7613 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7614 const AArch64Subtarget *Subtarget) {
7615 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7616 if (!EnableAArch64ExtrGeneration)
7618 SelectionDAG &DAG = DCI.DAG;
7619 EVT VT = N->getValueType(0);
7621 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7624 SDValue Res = tryCombineToEXTR(N, DCI);
7628 Res = tryCombineToBSL(N, DCI);
7635 static SDValue performBitcastCombine(SDNode *N,
7636 TargetLowering::DAGCombinerInfo &DCI,
7637 SelectionDAG &DAG) {
7638 // Wait 'til after everything is legalized to try this. That way we have
7639 // legal vector types and such.
7640 if (DCI.isBeforeLegalizeOps())
7643 // Remove extraneous bitcasts around an extract_subvector.
7645 // (v4i16 (bitconvert
7646 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7648 // (extract_subvector ((v8i16 ...), (i64 4)))
7650 // Only interested in 64-bit vectors as the ultimate result.
7651 EVT VT = N->getValueType(0);
7654 if (VT.getSimpleVT().getSizeInBits() != 64)
7656 // Is the operand an extract_subvector starting at the beginning or halfway
7657 // point of the vector? A low half may also come through as an
7658 // EXTRACT_SUBREG, so look for that, too.
7659 SDValue Op0 = N->getOperand(0);
7660 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7661 !(Op0->isMachineOpcode() &&
7662 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7664 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7665 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7666 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7668 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7669 if (idx != AArch64::dsub)
7671 // The dsub reference is equivalent to a lane zero subvector reference.
7674 // Look through the bitcast of the input to the extract.
7675 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7677 SDValue Source = Op0->getOperand(0)->getOperand(0);
7678 // If the source type has twice the number of elements as our destination
7679 // type, we know this is an extract of the high or low half of the vector.
7680 EVT SVT = Source->getValueType(0);
7681 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7684 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7686 // Create the simplified form to just extract the low or high half of the
7687 // vector directly rather than bothering with the bitcasts.
7689 unsigned NumElements = VT.getVectorNumElements();
7691 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7692 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7694 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7695 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7701 static SDValue performConcatVectorsCombine(SDNode *N,
7702 TargetLowering::DAGCombinerInfo &DCI,
7703 SelectionDAG &DAG) {
7705 EVT VT = N->getValueType(0);
7706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7708 // Optimize concat_vectors of truncated vectors, where the intermediate
7709 // type is illegal, to avoid said illegality, e.g.,
7710 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7711 // (v2i16 (truncate (v2i64)))))
7713 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7714 // (v4i32 (bitcast (v2i64))),
7716 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7717 // on both input and result type, so we might generate worse code.
7718 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7719 if (N->getNumOperands() == 2 &&
7720 N0->getOpcode() == ISD::TRUNCATE &&
7721 N1->getOpcode() == ISD::TRUNCATE) {
7722 SDValue N00 = N0->getOperand(0);
7723 SDValue N10 = N1->getOperand(0);
7724 EVT N00VT = N00.getValueType();
7726 if (N00VT == N10.getValueType() &&
7727 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7728 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7729 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7730 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7731 for (size_t i = 0; i < Mask.size(); ++i)
7733 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7734 DAG.getVectorShuffle(
7736 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7737 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7741 // Wait 'til after everything is legalized to try this. That way we have
7742 // legal vector types and such.
7743 if (DCI.isBeforeLegalizeOps())
7746 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7747 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7748 // canonicalise to that.
7749 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7750 assert(VT.getVectorElementType().getSizeInBits() == 64);
7751 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7752 DAG.getConstant(0, dl, MVT::i64));
7755 // Canonicalise concat_vectors so that the right-hand vector has as few
7756 // bit-casts as possible before its real operation. The primary matching
7757 // destination for these operations will be the narrowing "2" instructions,
7758 // which depend on the operation being performed on this right-hand vector.
7760 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7762 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7764 if (N1->getOpcode() != ISD::BITCAST)
7766 SDValue RHS = N1->getOperand(0);
7767 MVT RHSTy = RHS.getValueType().getSimpleVT();
7768 // If the RHS is not a vector, this is not the pattern we're looking for.
7769 if (!RHSTy.isVector())
7772 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7774 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7775 RHSTy.getVectorNumElements() * 2);
7776 return DAG.getNode(ISD::BITCAST, dl, VT,
7777 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7778 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7782 static SDValue tryCombineFixedPointConvert(SDNode *N,
7783 TargetLowering::DAGCombinerInfo &DCI,
7784 SelectionDAG &DAG) {
7785 // Wait 'til after everything is legalized to try this. That way we have
7786 // legal vector types and such.
7787 if (DCI.isBeforeLegalizeOps())
7789 // Transform a scalar conversion of a value from a lane extract into a
7790 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7791 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7792 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7794 // The second form interacts better with instruction selection and the
7795 // register allocator to avoid cross-class register copies that aren't
7796 // coalescable due to a lane reference.
7798 // Check the operand and see if it originates from a lane extract.
7799 SDValue Op1 = N->getOperand(1);
7800 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7801 // Yep, no additional predication needed. Perform the transform.
7802 SDValue IID = N->getOperand(0);
7803 SDValue Shift = N->getOperand(2);
7804 SDValue Vec = Op1.getOperand(0);
7805 SDValue Lane = Op1.getOperand(1);
7806 EVT ResTy = N->getValueType(0);
7810 // The vector width should be 128 bits by the time we get here, even
7811 // if it started as 64 bits (the extract_vector handling will have
7813 assert(Vec.getValueType().getSizeInBits() == 128 &&
7814 "unexpected vector size on extract_vector_elt!");
7815 if (Vec.getValueType() == MVT::v4i32)
7816 VecResTy = MVT::v4f32;
7817 else if (Vec.getValueType() == MVT::v2i64)
7818 VecResTy = MVT::v2f64;
7820 llvm_unreachable("unexpected vector type!");
7823 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7829 // AArch64 high-vector "long" operations are formed by performing the non-high
7830 // version on an extract_subvector of each operand which gets the high half:
7832 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7834 // However, there are cases which don't have an extract_high explicitly, but
7835 // have another operation that can be made compatible with one for free. For
7838 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7840 // This routine does the actual conversion of such DUPs, once outer routines
7841 // have determined that everything else is in order.
7842 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7844 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7845 switch (N.getOpcode()) {
7846 case AArch64ISD::DUP:
7847 case AArch64ISD::DUPLANE8:
7848 case AArch64ISD::DUPLANE16:
7849 case AArch64ISD::DUPLANE32:
7850 case AArch64ISD::DUPLANE64:
7851 case AArch64ISD::MOVI:
7852 case AArch64ISD::MOVIshift:
7853 case AArch64ISD::MOVIedit:
7854 case AArch64ISD::MOVImsl:
7855 case AArch64ISD::MVNIshift:
7856 case AArch64ISD::MVNImsl:
7859 // FMOV could be supported, but isn't very useful, as it would only occur
7860 // if you passed a bitcast' floating point immediate to an eligible long
7861 // integer op (addl, smull, ...).
7865 MVT NarrowTy = N.getSimpleValueType();
7866 if (!NarrowTy.is64BitVector())
7869 MVT ElementTy = NarrowTy.getVectorElementType();
7870 unsigned NumElems = NarrowTy.getVectorNumElements();
7871 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7874 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7875 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7876 DAG.getConstant(NumElems, dl, MVT::i64));
7879 static bool isEssentiallyExtractSubvector(SDValue N) {
7880 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7883 return N.getOpcode() == ISD::BITCAST &&
7884 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7887 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7888 struct GenericSetCCInfo {
7889 const SDValue *Opnd0;
7890 const SDValue *Opnd1;
7894 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7895 struct AArch64SetCCInfo {
7897 AArch64CC::CondCode CC;
7900 /// \brief Helper structure to keep track of SetCC information.
7902 GenericSetCCInfo Generic;
7903 AArch64SetCCInfo AArch64;
7906 /// \brief Helper structure to be able to read SetCC information. If set to
7907 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7908 /// GenericSetCCInfo.
7909 struct SetCCInfoAndKind {
7914 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7916 /// AArch64 lowered one.
7917 /// \p SetCCInfo is filled accordingly.
7918 /// \post SetCCInfo is meanginfull only when this function returns true.
7919 /// \return True when Op is a kind of SET_CC operation.
7920 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7921 // If this is a setcc, this is straight forward.
7922 if (Op.getOpcode() == ISD::SETCC) {
7923 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7924 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7925 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7926 SetCCInfo.IsAArch64 = false;
7929 // Otherwise, check if this is a matching csel instruction.
7933 if (Op.getOpcode() != AArch64ISD::CSEL)
7935 // Set the information about the operands.
7936 // TODO: we want the operands of the Cmp not the csel
7937 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7938 SetCCInfo.IsAArch64 = true;
7939 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7940 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7942 // Check that the operands matches the constraints:
7943 // (1) Both operands must be constants.
7944 // (2) One must be 1 and the other must be 0.
7945 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7946 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7949 if (!TValue || !FValue)
7953 if (!TValue->isOne()) {
7954 // Update the comparison when we are interested in !cc.
7955 std::swap(TValue, FValue);
7956 SetCCInfo.Info.AArch64.CC =
7957 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7959 return TValue->isOne() && FValue->isNullValue();
7962 // Returns true if Op is setcc or zext of setcc.
7963 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7964 if (isSetCC(Op, Info))
7966 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7967 isSetCC(Op->getOperand(0), Info));
7970 // The folding we want to perform is:
7971 // (add x, [zext] (setcc cc ...) )
7973 // (csel x, (add x, 1), !cc ...)
7975 // The latter will get matched to a CSINC instruction.
7976 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7977 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7978 SDValue LHS = Op->getOperand(0);
7979 SDValue RHS = Op->getOperand(1);
7980 SetCCInfoAndKind InfoAndKind;
7982 // If neither operand is a SET_CC, give up.
7983 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7984 std::swap(LHS, RHS);
7985 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7989 // FIXME: This could be generatized to work for FP comparisons.
7990 EVT CmpVT = InfoAndKind.IsAArch64
7991 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7992 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7993 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7999 if (InfoAndKind.IsAArch64) {
8000 CCVal = DAG.getConstant(
8001 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8003 Cmp = *InfoAndKind.Info.AArch64.Cmp;
8005 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
8006 *InfoAndKind.Info.Generic.Opnd1,
8007 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
8010 EVT VT = Op->getValueType(0);
8011 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8012 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8015 // The basic add/sub long vector instructions have variants with "2" on the end
8016 // which act on the high-half of their inputs. They are normally matched by
8019 // (add (zeroext (extract_high LHS)),
8020 // (zeroext (extract_high RHS)))
8021 // -> uaddl2 vD, vN, vM
8023 // However, if one of the extracts is something like a duplicate, this
8024 // instruction can still be used profitably. This function puts the DAG into a
8025 // more appropriate form for those patterns to trigger.
8026 static SDValue performAddSubLongCombine(SDNode *N,
8027 TargetLowering::DAGCombinerInfo &DCI,
8028 SelectionDAG &DAG) {
8029 if (DCI.isBeforeLegalizeOps())
8032 MVT VT = N->getSimpleValueType(0);
8033 if (!VT.is128BitVector()) {
8034 if (N->getOpcode() == ISD::ADD)
8035 return performSetccAddFolding(N, DAG);
8039 // Make sure both branches are extended in the same way.
8040 SDValue LHS = N->getOperand(0);
8041 SDValue RHS = N->getOperand(1);
8042 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8043 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8044 LHS.getOpcode() != RHS.getOpcode())
8047 unsigned ExtType = LHS.getOpcode();
8049 // It's not worth doing if at least one of the inputs isn't already an
8050 // extract, but we don't know which it'll be so we have to try both.
8051 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
8052 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
8056 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8057 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
8058 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
8062 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8065 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8068 // Massage DAGs which we can use the high-half "long" operations on into
8069 // something isel will recognize better. E.g.
8071 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
8072 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8073 // (extract_high (v2i64 (dup128 scalar)))))
8075 static SDValue tryCombineLongOpWithDup(SDNode *N,
8076 TargetLowering::DAGCombinerInfo &DCI,
8077 SelectionDAG &DAG) {
8078 if (DCI.isBeforeLegalizeOps())
8081 bool IsIntrinsic = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
8082 SDValue LHS = N->getOperand(IsIntrinsic ? 1 : 0);
8083 SDValue RHS = N->getOperand(IsIntrinsic ? 2 : 1);
8084 assert(LHS.getValueType().is64BitVector() &&
8085 RHS.getValueType().is64BitVector() &&
8086 "unexpected shape for long operation");
8088 // Either node could be a DUP, but it's not worth doing both of them (you'd
8089 // just as well use the non-high version) so look for a corresponding extract
8090 // operation on the other "wing".
8091 if (isEssentiallyExtractSubvector(LHS)) {
8092 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
8095 } else if (isEssentiallyExtractSubvector(RHS)) {
8096 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
8101 // N could either be an intrinsic or a sabsdiff/uabsdiff node.
8103 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
8104 N->getOperand(0), LHS, RHS);
8106 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
8110 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
8111 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
8112 unsigned ElemBits = ElemTy.getSizeInBits();
8114 int64_t ShiftAmount;
8115 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
8116 APInt SplatValue, SplatUndef;
8117 unsigned SplatBitSize;
8119 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
8120 HasAnyUndefs, ElemBits) ||
8121 SplatBitSize != ElemBits)
8124 ShiftAmount = SplatValue.getSExtValue();
8125 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
8126 ShiftAmount = CVN->getSExtValue();
8134 llvm_unreachable("Unknown shift intrinsic");
8135 case Intrinsic::aarch64_neon_sqshl:
8136 Opcode = AArch64ISD::SQSHL_I;
8137 IsRightShift = false;
8139 case Intrinsic::aarch64_neon_uqshl:
8140 Opcode = AArch64ISD::UQSHL_I;
8141 IsRightShift = false;
8143 case Intrinsic::aarch64_neon_srshl:
8144 Opcode = AArch64ISD::SRSHR_I;
8145 IsRightShift = true;
8147 case Intrinsic::aarch64_neon_urshl:
8148 Opcode = AArch64ISD::URSHR_I;
8149 IsRightShift = true;
8151 case Intrinsic::aarch64_neon_sqshlu:
8152 Opcode = AArch64ISD::SQSHLU_I;
8153 IsRightShift = false;
8157 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8159 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8160 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8161 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
8163 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8164 DAG.getConstant(ShiftAmount, dl, MVT::i32));
8170 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
8171 // the intrinsics must be legal and take an i32, this means there's almost
8172 // certainly going to be a zext in the DAG which we can eliminate.
8173 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
8174 SDValue AndN = N->getOperand(2);
8175 if (AndN.getOpcode() != ISD::AND)
8178 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
8179 if (!CMask || CMask->getZExtValue() != Mask)
8182 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
8183 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
8186 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
8187 SelectionDAG &DAG) {
8189 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
8190 DAG.getNode(Opc, dl,
8191 N->getOperand(1).getSimpleValueType(),
8193 DAG.getConstant(0, dl, MVT::i64));
8196 static SDValue performIntrinsicCombine(SDNode *N,
8197 TargetLowering::DAGCombinerInfo &DCI,
8198 const AArch64Subtarget *Subtarget) {
8199 SelectionDAG &DAG = DCI.DAG;
8200 unsigned IID = getIntrinsicID(N);
8204 case Intrinsic::aarch64_neon_vcvtfxs2fp:
8205 case Intrinsic::aarch64_neon_vcvtfxu2fp:
8206 return tryCombineFixedPointConvert(N, DCI, DAG);
8208 case Intrinsic::aarch64_neon_saddv:
8209 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
8210 case Intrinsic::aarch64_neon_uaddv:
8211 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
8212 case Intrinsic::aarch64_neon_sminv:
8213 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
8214 case Intrinsic::aarch64_neon_uminv:
8215 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
8216 case Intrinsic::aarch64_neon_smaxv:
8217 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
8218 case Intrinsic::aarch64_neon_umaxv:
8219 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
8220 case Intrinsic::aarch64_neon_fmax:
8221 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
8222 N->getOperand(1), N->getOperand(2));
8223 case Intrinsic::aarch64_neon_fmin:
8224 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
8225 N->getOperand(1), N->getOperand(2));
8226 case Intrinsic::aarch64_neon_sabd:
8227 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
8228 N->getOperand(1), N->getOperand(2));
8229 case Intrinsic::aarch64_neon_uabd:
8230 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
8231 N->getOperand(1), N->getOperand(2));
8232 case Intrinsic::aarch64_neon_smull:
8233 case Intrinsic::aarch64_neon_umull:
8234 case Intrinsic::aarch64_neon_pmull:
8235 case Intrinsic::aarch64_neon_sqdmull:
8236 return tryCombineLongOpWithDup(N, DCI, DAG);
8237 case Intrinsic::aarch64_neon_sqshl:
8238 case Intrinsic::aarch64_neon_uqshl:
8239 case Intrinsic::aarch64_neon_sqshlu:
8240 case Intrinsic::aarch64_neon_srshl:
8241 case Intrinsic::aarch64_neon_urshl:
8242 return tryCombineShiftImm(IID, N, DAG);
8243 case Intrinsic::aarch64_crc32b:
8244 case Intrinsic::aarch64_crc32cb:
8245 return tryCombineCRC32(0xff, N, DAG);
8246 case Intrinsic::aarch64_crc32h:
8247 case Intrinsic::aarch64_crc32ch:
8248 return tryCombineCRC32(0xffff, N, DAG);
8253 static SDValue performExtendCombine(SDNode *N,
8254 TargetLowering::DAGCombinerInfo &DCI,
8255 SelectionDAG &DAG) {
8256 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8257 // we can convert that DUP into another extract_high (of a bigger DUP), which
8258 // helps the backend to decide that an sabdl2 would be useful, saving a real
8259 // extract_high operation.
8260 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8261 (N->getOperand(0).getOpcode() == ISD::SABSDIFF ||
8262 N->getOperand(0).getOpcode() == ISD::UABSDIFF)) {
8263 SDNode *ABDNode = N->getOperand(0).getNode();
8264 SDValue NewABD = tryCombineLongOpWithDup(ABDNode, DCI, DAG);
8265 if (!NewABD.getNode())
8268 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8272 // This is effectively a custom type legalization for AArch64.
8274 // Type legalization will split an extend of a small, legal, type to a larger
8275 // illegal type by first splitting the destination type, often creating
8276 // illegal source types, which then get legalized in isel-confusing ways,
8277 // leading to really terrible codegen. E.g.,
8278 // %result = v8i32 sext v8i8 %value
8280 // %losrc = extract_subreg %value, ...
8281 // %hisrc = extract_subreg %value, ...
8282 // %lo = v4i32 sext v4i8 %losrc
8283 // %hi = v4i32 sext v4i8 %hisrc
8284 // Things go rapidly downhill from there.
8286 // For AArch64, the [sz]ext vector instructions can only go up one element
8287 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8288 // take two instructions.
8290 // This implies that the most efficient way to do the extend from v8i8
8291 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8292 // the normal splitting to happen for the v8i16->v8i32.
8294 // This is pre-legalization to catch some cases where the default
8295 // type legalization will create ill-tempered code.
8296 if (!DCI.isBeforeLegalizeOps())
8299 // We're only interested in cleaning things up for non-legal vector types
8300 // here. If both the source and destination are legal, things will just
8301 // work naturally without any fiddling.
8302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8303 EVT ResVT = N->getValueType(0);
8304 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8306 // If the vector type isn't a simple VT, it's beyond the scope of what
8307 // we're worried about here. Let legalization do its thing and hope for
8309 SDValue Src = N->getOperand(0);
8310 EVT SrcVT = Src->getValueType(0);
8311 if (!ResVT.isSimple() || !SrcVT.isSimple())
8314 // If the source VT is a 64-bit vector, we can play games and get the
8315 // better results we want.
8316 if (SrcVT.getSizeInBits() != 64)
8319 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8320 unsigned ElementCount = SrcVT.getVectorNumElements();
8321 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8323 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8325 // Now split the rest of the operation into two halves, each with a 64
8329 unsigned NumElements = ResVT.getVectorNumElements();
8330 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8331 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8332 ResVT.getVectorElementType(), NumElements / 2);
8334 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8335 LoVT.getVectorNumElements());
8336 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8337 DAG.getConstant(0, DL, MVT::i64));
8338 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8339 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8340 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8341 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8343 // Now combine the parts back together so we still have a single result
8344 // like the combiner expects.
8345 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8348 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8349 /// value. The load store optimizer pass will merge them to store pair stores.
8350 /// This has better performance than a splat of the scalar followed by a split
8351 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8352 /// followed by an ext.b and two stores.
8353 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8354 SDValue StVal = St->getValue();
8355 EVT VT = StVal.getValueType();
8357 // Don't replace floating point stores, they possibly won't be transformed to
8358 // stp because of the store pair suppress pass.
8359 if (VT.isFloatingPoint())
8362 // Check for insert vector elements.
8363 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8366 // We can express a splat as store pair(s) for 2 or 4 elements.
8367 unsigned NumVecElts = VT.getVectorNumElements();
8368 if (NumVecElts != 4 && NumVecElts != 2)
8370 SDValue SplatVal = StVal.getOperand(1);
8371 unsigned RemainInsertElts = NumVecElts - 1;
8373 // Check that this is a splat.
8374 while (--RemainInsertElts) {
8375 SDValue NextInsertElt = StVal.getOperand(0);
8376 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8378 if (NextInsertElt.getOperand(1) != SplatVal)
8380 StVal = NextInsertElt;
8382 unsigned OrigAlignment = St->getAlignment();
8383 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8384 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8386 // Create scalar stores. This is at least as good as the code sequence for a
8387 // split unaligned store wich is a dup.s, ext.b, and two stores.
8388 // Most of the time the three stores should be replaced by store pair
8389 // instructions (stp).
8391 SDValue BasePtr = St->getBasePtr();
8393 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8394 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8396 unsigned Offset = EltOffset;
8397 while (--NumVecElts) {
8398 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8399 DAG.getConstant(Offset, DL, MVT::i64));
8400 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8401 St->getPointerInfo(), St->isVolatile(),
8402 St->isNonTemporal(), Alignment);
8403 Offset += EltOffset;
8408 static SDValue performSTORECombine(SDNode *N,
8409 TargetLowering::DAGCombinerInfo &DCI,
8411 const AArch64Subtarget *Subtarget) {
8412 if (!DCI.isBeforeLegalize())
8415 StoreSDNode *S = cast<StoreSDNode>(N);
8416 if (S->isVolatile())
8419 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8420 // page boundaries. We want to split such stores.
8421 if (!Subtarget->isCyclone())
8424 // Don't split at Oz.
8425 MachineFunction &MF = DAG.getMachineFunction();
8426 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8430 SDValue StVal = S->getValue();
8431 EVT VT = StVal.getValueType();
8433 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8434 // those up regresses performance on micro-benchmarks and olden/bh.
8435 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8438 // Split unaligned 16B stores. They are terrible for performance.
8439 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8440 // extensions can use this to mark that it does not want splitting to happen
8441 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8442 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8443 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8444 S->getAlignment() <= 2)
8447 // If we get a splat of a scalar convert this vector store to a store of
8448 // scalars. They will be merged into store pairs thereby removing two
8450 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8451 if (ReplacedSplat != SDValue())
8452 return ReplacedSplat;
8455 unsigned NumElts = VT.getVectorNumElements() / 2;
8456 // Split VT into two.
8458 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8459 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8460 DAG.getConstant(0, DL, MVT::i64));
8461 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8462 DAG.getConstant(NumElts, DL, MVT::i64));
8463 SDValue BasePtr = S->getBasePtr();
8465 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8466 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8467 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8468 DAG.getConstant(8, DL, MVT::i64));
8469 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8470 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8474 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8475 /// post-increment LD1R.
8476 static SDValue performPostLD1Combine(SDNode *N,
8477 TargetLowering::DAGCombinerInfo &DCI,
8479 if (DCI.isBeforeLegalizeOps())
8482 SelectionDAG &DAG = DCI.DAG;
8483 EVT VT = N->getValueType(0);
8485 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8486 SDNode *LD = N->getOperand(LoadIdx).getNode();
8487 // If it is not LOAD, can not do such combine.
8488 if (LD->getOpcode() != ISD::LOAD)
8491 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8492 EVT MemVT = LoadSDN->getMemoryVT();
8493 // Check if memory operand is the same type as the vector element.
8494 if (MemVT != VT.getVectorElementType())
8497 // Check if there are other uses. If so, do not combine as it will introduce
8499 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8501 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8507 SDValue Addr = LD->getOperand(1);
8508 SDValue Vector = N->getOperand(0);
8509 // Search for a use of the address operand that is an increment.
8510 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8511 Addr.getNode()->use_end(); UI != UE; ++UI) {
8513 if (User->getOpcode() != ISD::ADD
8514 || UI.getUse().getResNo() != Addr.getResNo())
8517 // Check that the add is independent of the load. Otherwise, folding it
8518 // would create a cycle.
8519 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8521 // Also check that add is not used in the vector operand. This would also
8523 if (User->isPredecessorOf(Vector.getNode()))
8526 // If the increment is a constant, it must match the memory ref size.
8527 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8528 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8529 uint32_t IncVal = CInc->getZExtValue();
8530 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8531 if (IncVal != NumBytes)
8533 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8536 // Finally, check that the vector doesn't depend on the load.
8537 // Again, this would create a cycle.
8538 // The load depending on the vector is fine, as that's the case for the
8539 // LD1*post we'll eventually generate anyway.
8540 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8543 SmallVector<SDValue, 8> Ops;
8544 Ops.push_back(LD->getOperand(0)); // Chain
8546 Ops.push_back(Vector); // The vector to be inserted
8547 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8549 Ops.push_back(Addr);
8552 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8553 SDVTList SDTys = DAG.getVTList(Tys);
8554 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8555 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8557 LoadSDN->getMemOperand());
8560 SmallVector<SDValue, 2> NewResults;
8561 NewResults.push_back(SDValue(LD, 0)); // The result of load
8562 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8563 DCI.CombineTo(LD, NewResults);
8564 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8565 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8572 /// Target-specific DAG combine function for NEON load/store intrinsics
8573 /// to merge base address updates.
8574 static SDValue performNEONPostLDSTCombine(SDNode *N,
8575 TargetLowering::DAGCombinerInfo &DCI,
8576 SelectionDAG &DAG) {
8577 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8580 unsigned AddrOpIdx = N->getNumOperands() - 1;
8581 SDValue Addr = N->getOperand(AddrOpIdx);
8583 // Search for a use of the address operand that is an increment.
8584 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8585 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8587 if (User->getOpcode() != ISD::ADD ||
8588 UI.getUse().getResNo() != Addr.getResNo())
8591 // Check that the add is independent of the load/store. Otherwise, folding
8592 // it would create a cycle.
8593 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8596 // Find the new opcode for the updating load/store.
8597 bool IsStore = false;
8598 bool IsLaneOp = false;
8599 bool IsDupOp = false;
8600 unsigned NewOpc = 0;
8601 unsigned NumVecs = 0;
8602 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8604 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8605 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8607 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8609 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8611 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8612 NumVecs = 2; IsStore = true; break;
8613 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8614 NumVecs = 3; IsStore = true; break;
8615 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8616 NumVecs = 4; IsStore = true; break;
8617 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8619 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8621 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8623 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8624 NumVecs = 2; IsStore = true; break;
8625 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8626 NumVecs = 3; IsStore = true; break;
8627 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8628 NumVecs = 4; IsStore = true; break;
8629 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8630 NumVecs = 2; IsDupOp = true; break;
8631 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8632 NumVecs = 3; IsDupOp = true; break;
8633 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8634 NumVecs = 4; IsDupOp = true; break;
8635 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8636 NumVecs = 2; IsLaneOp = true; break;
8637 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8638 NumVecs = 3; IsLaneOp = true; break;
8639 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8640 NumVecs = 4; IsLaneOp = true; break;
8641 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8642 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8643 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8644 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8645 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8646 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8651 VecTy = N->getOperand(2).getValueType();
8653 VecTy = N->getValueType(0);
8655 // If the increment is a constant, it must match the memory ref size.
8656 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8657 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8658 uint32_t IncVal = CInc->getZExtValue();
8659 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8660 if (IsLaneOp || IsDupOp)
8661 NumBytes /= VecTy.getVectorNumElements();
8662 if (IncVal != NumBytes)
8664 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8666 SmallVector<SDValue, 8> Ops;
8667 Ops.push_back(N->getOperand(0)); // Incoming chain
8668 // Load lane and store have vector list as input.
8669 if (IsLaneOp || IsStore)
8670 for (unsigned i = 2; i < AddrOpIdx; ++i)
8671 Ops.push_back(N->getOperand(i));
8672 Ops.push_back(Addr); // Base register
8677 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8679 for (n = 0; n < NumResultVecs; ++n)
8681 Tys[n++] = MVT::i64; // Type of write back register
8682 Tys[n] = MVT::Other; // Type of the chain
8683 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8685 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8686 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8687 MemInt->getMemoryVT(),
8688 MemInt->getMemOperand());
8691 std::vector<SDValue> NewResults;
8692 for (unsigned i = 0; i < NumResultVecs; ++i) {
8693 NewResults.push_back(SDValue(UpdN.getNode(), i));
8695 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8696 DCI.CombineTo(N, NewResults);
8697 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8704 // Checks to see if the value is the prescribed width and returns information
8705 // about its extension mode.
8707 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8708 ExtType = ISD::NON_EXTLOAD;
8709 switch(V.getNode()->getOpcode()) {
8713 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8714 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8715 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8716 ExtType = LoadNode->getExtensionType();
8721 case ISD::AssertSext: {
8722 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8723 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8724 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8725 ExtType = ISD::SEXTLOAD;
8730 case ISD::AssertZext: {
8731 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8732 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8733 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8734 ExtType = ISD::ZEXTLOAD;
8740 case ISD::TargetConstant: {
8741 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8751 // This function does a whole lot of voodoo to determine if the tests are
8752 // equivalent without and with a mask. Essentially what happens is that given a
8755 // +-------------+ +-------------+ +-------------+ +-------------+
8756 // | Input | | AddConstant | | CompConstant| | CC |
8757 // +-------------+ +-------------+ +-------------+ +-------------+
8759 // V V | +----------+
8760 // +-------------+ +----+ | |
8761 // | ADD | |0xff| | |
8762 // +-------------+ +----+ | |
8765 // +-------------+ | |
8767 // +-------------+ | |
8776 // The AND node may be safely removed for some combinations of inputs. In
8777 // particular we need to take into account the extension type of the Input,
8778 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8779 // width of the input (this can work for any width inputs, the above graph is
8780 // specific to 8 bits.
8782 // The specific equations were worked out by generating output tables for each
8783 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8784 // problem was simplified by working with 4 bit inputs, which means we only
8785 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8786 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8787 // patterns present in both extensions (0,7). For every distinct set of
8788 // AddConstant and CompConstants bit patterns we can consider the masked and
8789 // unmasked versions to be equivalent if the result of this function is true for
8790 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8793 // and w10, w8, #0x0f
8795 // cset w9, AArch64CC
8797 // cset w11, AArch64CC
8802 // Since the above function shows when the outputs are equivalent it defines
8803 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8804 // would be expensive to run during compiles. The equations below were written
8805 // in a test harness that confirmed they gave equivalent outputs to the above
8806 // for all inputs function, so they can be used determine if the removal is
8809 // isEquivalentMaskless() is the code for testing if the AND can be removed
8810 // factored out of the DAG recognition as the DAG can take several forms.
8813 bool isEquivalentMaskless(unsigned CC, unsigned width,
8814 ISD::LoadExtType ExtType, signed AddConstant,
8815 signed CompConstant) {
8816 // By being careful about our equations and only writing the in term
8817 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8818 // make them generally applicable to all bit widths.
8819 signed MaxUInt = (1 << width);
8821 // For the purposes of these comparisons sign extending the type is
8822 // equivalent to zero extending the add and displacing it by half the integer
8823 // width. Provided we are careful and make sure our equations are valid over
8824 // the whole range we can just adjust the input and avoid writing equations
8825 // for sign extended inputs.
8826 if (ExtType == ISD::SEXTLOAD)
8827 AddConstant -= (1 << (width-1));
8831 case AArch64CC::GT: {
8832 if ((AddConstant == 0) ||
8833 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8834 (AddConstant >= 0 && CompConstant < 0) ||
8835 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8839 case AArch64CC::GE: {
8840 if ((AddConstant == 0) ||
8841 (AddConstant >= 0 && CompConstant <= 0) ||
8842 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8846 case AArch64CC::LS: {
8847 if ((AddConstant >= 0 && CompConstant < 0) ||
8848 (AddConstant <= 0 && CompConstant >= -1 &&
8849 CompConstant < AddConstant + MaxUInt))
8853 case AArch64CC::MI: {
8854 if ((AddConstant == 0) ||
8855 (AddConstant > 0 && CompConstant <= 0) ||
8856 (AddConstant < 0 && CompConstant <= AddConstant))
8860 case AArch64CC::HS: {
8861 if ((AddConstant >= 0 && CompConstant <= 0) ||
8862 (AddConstant <= 0 && CompConstant >= 0 &&
8863 CompConstant <= AddConstant + MaxUInt))
8867 case AArch64CC::NE: {
8868 if ((AddConstant > 0 && CompConstant < 0) ||
8869 (AddConstant < 0 && CompConstant >= 0 &&
8870 CompConstant < AddConstant + MaxUInt) ||
8871 (AddConstant >= 0 && CompConstant >= 0 &&
8872 CompConstant >= AddConstant) ||
8873 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8882 case AArch64CC::Invalid:
8890 SDValue performCONDCombine(SDNode *N,
8891 TargetLowering::DAGCombinerInfo &DCI,
8892 SelectionDAG &DAG, unsigned CCIndex,
8893 unsigned CmpIndex) {
8894 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8895 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8896 unsigned CondOpcode = SubsNode->getOpcode();
8898 if (CondOpcode != AArch64ISD::SUBS)
8901 // There is a SUBS feeding this condition. Is it fed by a mask we can
8904 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8905 unsigned MaskBits = 0;
8907 if (AndNode->getOpcode() != ISD::AND)
8910 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8911 uint32_t CNV = CN->getZExtValue();
8914 else if (CNV == 65535)
8921 SDValue AddValue = AndNode->getOperand(0);
8923 if (AddValue.getOpcode() != ISD::ADD)
8926 // The basic dag structure is correct, grab the inputs and validate them.
8928 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8929 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8930 SDValue SubsInputValue = SubsNode->getOperand(1);
8932 // The mask is present and the provenance of all the values is a smaller type,
8933 // lets see if the mask is superfluous.
8935 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8936 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8939 ISD::LoadExtType ExtType;
8941 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8942 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8943 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8946 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8947 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8948 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8951 // The AND is not necessary, remove it.
8953 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8954 SubsNode->getValueType(1));
8955 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8957 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8958 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8960 return SDValue(N, 0);
8963 // Optimize compare with zero and branch.
8964 static SDValue performBRCONDCombine(SDNode *N,
8965 TargetLowering::DAGCombinerInfo &DCI,
8966 SelectionDAG &DAG) {
8967 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8970 SDValue Chain = N->getOperand(0);
8971 SDValue Dest = N->getOperand(1);
8972 SDValue CCVal = N->getOperand(2);
8973 SDValue Cmp = N->getOperand(3);
8975 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8976 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8977 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8980 unsigned CmpOpc = Cmp.getOpcode();
8981 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8984 // Only attempt folding if there is only one use of the flag and no use of the
8986 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8989 SDValue LHS = Cmp.getOperand(0);
8990 SDValue RHS = Cmp.getOperand(1);
8992 assert(LHS.getValueType() == RHS.getValueType() &&
8993 "Expected the value type to be the same for both operands!");
8994 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8997 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8998 std::swap(LHS, RHS);
9000 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
9003 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9004 LHS.getOpcode() == ISD::SRL)
9007 // Fold the compare into the branch instruction.
9009 if (CC == AArch64CC::EQ)
9010 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9012 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9014 // Do not add new nodes to DAG combiner worklist.
9015 DCI.CombineTo(N, BR, false);
9020 // vselect (v1i1 setcc) ->
9021 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
9022 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
9023 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
9025 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
9026 SDValue N0 = N->getOperand(0);
9027 EVT CCVT = N0.getValueType();
9029 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9030 CCVT.getVectorElementType() != MVT::i1)
9033 EVT ResVT = N->getValueType(0);
9034 EVT CmpVT = N0.getOperand(0).getValueType();
9035 // Only combine when the result type is of the same size as the compared
9037 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
9040 SDValue IfTrue = N->getOperand(1);
9041 SDValue IfFalse = N->getOperand(2);
9043 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
9044 N0.getOperand(0), N0.getOperand(1),
9045 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9046 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
9050 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
9051 /// the compare-mask instructions rather than going via NZCV, even if LHS and
9052 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
9053 /// with a vector one followed by a DUP shuffle on the result.
9054 static SDValue performSelectCombine(SDNode *N,
9055 TargetLowering::DAGCombinerInfo &DCI) {
9056 SelectionDAG &DAG = DCI.DAG;
9057 SDValue N0 = N->getOperand(0);
9058 EVT ResVT = N->getValueType(0);
9060 if (N0.getOpcode() != ISD::SETCC)
9063 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
9064 // scalar SetCCResultType. We also don't expect vectors, because we assume
9065 // that selects fed by vector SETCCs are canonicalized to VSELECT.
9066 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
9067 "Scalar-SETCC feeding SELECT has unexpected result type!");
9069 // If NumMaskElts == 0, the comparison is larger than select result. The
9070 // largest real NEON comparison is 64-bits per lane, which means the result is
9071 // at most 32-bits and an illegal vector. Just bail out for now.
9072 EVT SrcVT = N0.getOperand(0).getValueType();
9074 // Don't try to do this optimization when the setcc itself has i1 operands.
9075 // There are no legal vectors of i1, so this would be pointless.
9076 if (SrcVT == MVT::i1)
9079 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
9080 if (!ResVT.isVector() || NumMaskElts == 0)
9083 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
9084 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
9086 // Also bail out if the vector CCVT isn't the same size as ResVT.
9087 // This can happen if the SETCC operand size doesn't divide the ResVT size
9088 // (e.g., f64 vs v3f32).
9089 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
9092 // Make sure we didn't create illegal types, if we're not supposed to.
9093 assert(DCI.isBeforeLegalize() ||
9094 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
9096 // First perform a vector comparison, where lane 0 is the one we're interested
9100 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
9102 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
9103 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
9105 // Now duplicate the comparison mask we want across all other lanes.
9106 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
9107 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
9108 Mask = DAG.getNode(ISD::BITCAST, DL,
9109 ResVT.changeVectorElementTypeToInteger(), Mask);
9111 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
9114 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
9115 /// to match FMIN/FMAX patterns.
9116 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
9117 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
9118 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
9119 // vmax/vmin return NaN if either operand is a NaN;
9120 // only do the transformation when it matches that behavior.
9122 SDValue CondLHS = N->getOperand(0);
9123 SDValue CondRHS = N->getOperand(1);
9124 SDValue LHS = N->getOperand(2);
9125 SDValue RHS = N->getOperand(3);
9126 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9130 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
9131 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
9132 IsReversed = false; // x CC y ? x : y
9133 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
9134 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
9135 IsReversed = true ; // x CC y ? y : x
9140 bool IsUnordered = false, IsOrEqual;
9151 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
9152 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
9162 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
9163 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
9167 // If LHS is NaN, an ordered comparison will be false and the result will be
9168 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
9169 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9170 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9173 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
9174 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
9175 // used for unsafe math or if one of the operands is known to be nonzero.
9176 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
9177 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9180 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9183 /// Get rid of unnecessary NVCASTs (that don't change the type).
9184 static SDValue performNVCASTCombine(SDNode *N) {
9185 if (N->getValueType(0) == N->getOperand(0).getValueType())
9186 return N->getOperand(0);
9191 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
9192 DAGCombinerInfo &DCI) const {
9193 SelectionDAG &DAG = DCI.DAG;
9194 switch (N->getOpcode()) {
9199 return performAddSubLongCombine(N, DCI, DAG);
9201 return performXorCombine(N, DAG, DCI, Subtarget);
9203 return performMulCombine(N, DAG, DCI, Subtarget);
9204 case ISD::SINT_TO_FP:
9205 case ISD::UINT_TO_FP:
9206 return performIntToFpCombine(N, DAG, Subtarget);
9208 return performORCombine(N, DCI, Subtarget);
9209 case ISD::INTRINSIC_WO_CHAIN:
9210 return performIntrinsicCombine(N, DCI, Subtarget);
9211 case ISD::ANY_EXTEND:
9212 case ISD::ZERO_EXTEND:
9213 case ISD::SIGN_EXTEND:
9214 return performExtendCombine(N, DCI, DAG);
9216 return performBitcastCombine(N, DCI, DAG);
9217 case ISD::CONCAT_VECTORS:
9218 return performConcatVectorsCombine(N, DCI, DAG);
9220 return performSelectCombine(N, DCI);
9222 return performVSelectCombine(N, DCI.DAG);
9223 case ISD::SELECT_CC:
9224 return performSelectCCCombine(N, DCI.DAG);
9226 return performSTORECombine(N, DCI, DAG, Subtarget);
9227 case AArch64ISD::BRCOND:
9228 return performBRCONDCombine(N, DCI, DAG);
9229 case AArch64ISD::CSEL:
9230 return performCONDCombine(N, DCI, DAG, 2, 3);
9231 case AArch64ISD::DUP:
9232 return performPostLD1Combine(N, DCI, false);
9233 case AArch64ISD::NVCAST:
9234 return performNVCASTCombine(N);
9235 case ISD::INSERT_VECTOR_ELT:
9236 return performPostLD1Combine(N, DCI, true);
9237 case ISD::INTRINSIC_VOID:
9238 case ISD::INTRINSIC_W_CHAIN:
9239 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9240 case Intrinsic::aarch64_neon_ld2:
9241 case Intrinsic::aarch64_neon_ld3:
9242 case Intrinsic::aarch64_neon_ld4:
9243 case Intrinsic::aarch64_neon_ld1x2:
9244 case Intrinsic::aarch64_neon_ld1x3:
9245 case Intrinsic::aarch64_neon_ld1x4:
9246 case Intrinsic::aarch64_neon_ld2lane:
9247 case Intrinsic::aarch64_neon_ld3lane:
9248 case Intrinsic::aarch64_neon_ld4lane:
9249 case Intrinsic::aarch64_neon_ld2r:
9250 case Intrinsic::aarch64_neon_ld3r:
9251 case Intrinsic::aarch64_neon_ld4r:
9252 case Intrinsic::aarch64_neon_st2:
9253 case Intrinsic::aarch64_neon_st3:
9254 case Intrinsic::aarch64_neon_st4:
9255 case Intrinsic::aarch64_neon_st1x2:
9256 case Intrinsic::aarch64_neon_st1x3:
9257 case Intrinsic::aarch64_neon_st1x4:
9258 case Intrinsic::aarch64_neon_st2lane:
9259 case Intrinsic::aarch64_neon_st3lane:
9260 case Intrinsic::aarch64_neon_st4lane:
9261 return performNEONPostLDSTCombine(N, DCI, DAG);
9269 // Check if the return value is used as only a return value, as otherwise
9270 // we can't perform a tail-call. In particular, we need to check for
9271 // target ISD nodes that are returns and any other "odd" constructs
9272 // that the generic analysis code won't necessarily catch.
9273 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9274 SDValue &Chain) const {
9275 if (N->getNumValues() != 1)
9277 if (!N->hasNUsesOfValue(1, 0))
9280 SDValue TCChain = Chain;
9281 SDNode *Copy = *N->use_begin();
9282 if (Copy->getOpcode() == ISD::CopyToReg) {
9283 // If the copy has a glue operand, we conservatively assume it isn't safe to
9284 // perform a tail call.
9285 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9288 TCChain = Copy->getOperand(0);
9289 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9292 bool HasRet = false;
9293 for (SDNode *Node : Copy->uses()) {
9294 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9306 // Return whether the an instruction can potentially be optimized to a tail
9307 // call. This will cause the optimizers to attempt to move, or duplicate,
9308 // return instructions to help enable tail call optimizations for this
9310 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9311 if (!CI->isTailCall())
9317 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9319 ISD::MemIndexedMode &AM,
9321 SelectionDAG &DAG) const {
9322 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9325 Base = Op->getOperand(0);
9326 // All of the indexed addressing mode instructions take a signed
9327 // 9 bit immediate offset.
9328 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9329 int64_t RHSC = (int64_t)RHS->getZExtValue();
9330 if (RHSC >= 256 || RHSC <= -256)
9332 IsInc = (Op->getOpcode() == ISD::ADD);
9333 Offset = Op->getOperand(1);
9339 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9341 ISD::MemIndexedMode &AM,
9342 SelectionDAG &DAG) const {
9345 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9346 VT = LD->getMemoryVT();
9347 Ptr = LD->getBasePtr();
9348 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9349 VT = ST->getMemoryVT();
9350 Ptr = ST->getBasePtr();
9355 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9357 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9361 bool AArch64TargetLowering::getPostIndexedAddressParts(
9362 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9363 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9366 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9367 VT = LD->getMemoryVT();
9368 Ptr = LD->getBasePtr();
9369 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9370 VT = ST->getMemoryVT();
9371 Ptr = ST->getBasePtr();
9376 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9378 // Post-indexing updates the base, so it's not a valid transform
9379 // if that's not the same as the load's pointer.
9382 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9386 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9387 SelectionDAG &DAG) {
9389 SDValue Op = N->getOperand(0);
9391 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9395 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9396 DAG.getUNDEF(MVT::i32), Op,
9397 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9399 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9400 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9403 void AArch64TargetLowering::ReplaceNodeResults(
9404 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9405 switch (N->getOpcode()) {
9407 llvm_unreachable("Don't know how to custom expand this");
9409 ReplaceBITCASTResults(N, Results, DAG);
9411 case ISD::FP_TO_UINT:
9412 case ISD::FP_TO_SINT:
9413 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9414 // Let normal code take care of it by not adding anything to Results.
9419 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9423 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
9424 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9425 // reciprocal if there are three or more FDIVs.
9429 TargetLoweringBase::LegalizeTypeAction
9430 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9431 MVT SVT = VT.getSimpleVT();
9432 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9433 // v4i16, v2i32 instead of to promote.
9434 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9435 || SVT == MVT::v1f32)
9436 return TypeWidenVector;
9438 return TargetLoweringBase::getPreferredVectorAction(VT);
9441 // Loads and stores less than 128-bits are already atomic; ones above that
9442 // are doomed anyway, so defer to the default libcall and blame the OS when
9444 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9445 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9449 // Loads and stores less than 128-bits are already atomic; ones above that
9450 // are doomed anyway, so defer to the default libcall and blame the OS when
9452 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9453 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9457 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9458 TargetLoweringBase::AtomicRMWExpansionKind
9459 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9460 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9461 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9462 : AtomicRMWExpansionKind::None;
9465 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9469 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9470 AtomicOrdering Ord) const {
9471 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9472 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9473 bool IsAcquire = isAtLeastAcquire(Ord);
9475 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9476 // intrinsic must return {i64, i64} and we have to recombine them into a
9477 // single i128 here.
9478 if (ValTy->getPrimitiveSizeInBits() == 128) {
9480 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9481 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9483 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9484 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9486 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9487 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9488 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9489 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9490 return Builder.CreateOr(
9491 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9494 Type *Tys[] = { Addr->getType() };
9496 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9497 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9499 return Builder.CreateTruncOrBitCast(
9500 Builder.CreateCall(Ldxr, Addr),
9501 cast<PointerType>(Addr->getType())->getElementType());
9504 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9505 Value *Val, Value *Addr,
9506 AtomicOrdering Ord) const {
9507 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9508 bool IsRelease = isAtLeastRelease(Ord);
9510 // Since the intrinsics must have legal type, the i128 intrinsics take two
9511 // parameters: "i64, i64". We must marshal Val into the appropriate form
9513 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9515 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9516 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9517 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9519 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9520 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9521 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9522 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9526 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9527 Type *Tys[] = { Addr->getType() };
9528 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9530 return Builder.CreateCall(Stxr,
9531 {Builder.CreateZExtOrBitCast(
9532 Val, Stxr->getFunctionType()->getParamType(0)),
9536 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9537 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9538 return Ty->isArrayTy();
9541 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,