1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is a storage-only type, always promote it to f32.
285 setOperationAction(ISD::SETCC, MVT::f16, Promote);
286 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
287 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT, MVT::f16, Promote);
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FSUB, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FDIV, MVT::f16, Promote);
293 setOperationAction(ISD::FREM, MVT::f16, Promote);
294 setOperationAction(ISD::FMA, MVT::f16, Promote);
295 setOperationAction(ISD::FNEG, MVT::f16, Promote);
296 setOperationAction(ISD::FABS, MVT::f16, Promote);
297 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
298 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
299 setOperationAction(ISD::FCOS, MVT::f16, Promote);
300 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
301 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
302 setOperationAction(ISD::FPOW, MVT::f16, Promote);
303 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
304 setOperationAction(ISD::FRINT, MVT::f16, Promote);
305 setOperationAction(ISD::FSIN, MVT::f16, Promote);
306 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
307 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
308 setOperationAction(ISD::FEXP, MVT::f16, Promote);
309 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
310 setOperationAction(ISD::FLOG, MVT::f16, Promote);
311 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
312 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
313 setOperationAction(ISD::FROUND, MVT::f16, Promote);
314 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
315 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
316 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
318 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
320 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
321 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
322 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
323 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
324 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
325 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
326 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
327 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
333 // Expand all other v4f16 operations.
334 // FIXME: We could generate better code by promoting some operations to
336 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
337 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
338 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
339 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
340 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
341 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
342 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
343 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
344 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
345 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
346 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
347 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
348 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
349 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
350 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
351 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
352 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
353 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
354 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
355 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
356 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
357 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
358 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
359 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
360 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
361 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
364 // v8f16 is also a storage-only type, so expand it.
365 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
366 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
367 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
368 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
371 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
372 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
373 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
374 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
375 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
376 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
377 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
378 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
379 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
380 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
381 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
382 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
383 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
384 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
385 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
386 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
387 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
388 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
389 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
390 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
391 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
392 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
393 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
394 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
395 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
397 // AArch64 has implementations of a lot of rounding-like FP operations.
398 for (MVT Ty : {MVT::f32, MVT::f64}) {
399 setOperationAction(ISD::FFLOOR, Ty, Legal);
400 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
401 setOperationAction(ISD::FCEIL, Ty, Legal);
402 setOperationAction(ISD::FRINT, Ty, Legal);
403 setOperationAction(ISD::FTRUNC, Ty, Legal);
404 setOperationAction(ISD::FROUND, Ty, Legal);
407 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
409 if (Subtarget->isTargetMachO()) {
410 // For iOS, we don't want to the normal expansion of a libcall to
411 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
413 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
414 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
416 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
420 // Make floating-point constants legal for the large code model, so they don't
421 // become loads from the constant pool.
422 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
423 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
424 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
427 // AArch64 does not have floating-point extending loads, i1 sign-extending
428 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
429 for (MVT VT : MVT::fp_valuetypes()) {
430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
435 for (MVT VT : MVT::integer_valuetypes())
436 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
438 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
439 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
440 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
441 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
443 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
444 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
446 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
447 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
449 // Indexed loads and stores are supported.
450 for (unsigned im = (unsigned)ISD::PRE_INC;
451 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
452 setIndexedLoadAction(im, MVT::i8, Legal);
453 setIndexedLoadAction(im, MVT::i16, Legal);
454 setIndexedLoadAction(im, MVT::i32, Legal);
455 setIndexedLoadAction(im, MVT::i64, Legal);
456 setIndexedLoadAction(im, MVT::f64, Legal);
457 setIndexedLoadAction(im, MVT::f32, Legal);
458 setIndexedStoreAction(im, MVT::i8, Legal);
459 setIndexedStoreAction(im, MVT::i16, Legal);
460 setIndexedStoreAction(im, MVT::i32, Legal);
461 setIndexedStoreAction(im, MVT::i64, Legal);
462 setIndexedStoreAction(im, MVT::f64, Legal);
463 setIndexedStoreAction(im, MVT::f32, Legal);
467 setOperationAction(ISD::TRAP, MVT::Other, Legal);
469 // We combine OR nodes for bitfield operations.
470 setTargetDAGCombine(ISD::OR);
472 // Vector add and sub nodes may conceal a high-half opportunity.
473 // Also, try to fold ADD into CSINC/CSINV..
474 setTargetDAGCombine(ISD::ADD);
475 setTargetDAGCombine(ISD::SUB);
477 setTargetDAGCombine(ISD::XOR);
478 setTargetDAGCombine(ISD::SINT_TO_FP);
479 setTargetDAGCombine(ISD::UINT_TO_FP);
481 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
483 setTargetDAGCombine(ISD::ANY_EXTEND);
484 setTargetDAGCombine(ISD::ZERO_EXTEND);
485 setTargetDAGCombine(ISD::SIGN_EXTEND);
486 setTargetDAGCombine(ISD::BITCAST);
487 setTargetDAGCombine(ISD::CONCAT_VECTORS);
488 setTargetDAGCombine(ISD::STORE);
490 setTargetDAGCombine(ISD::MUL);
492 setTargetDAGCombine(ISD::SELECT);
493 setTargetDAGCombine(ISD::VSELECT);
495 setTargetDAGCombine(ISD::INTRINSIC_VOID);
496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
497 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
499 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
500 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
501 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
503 setStackPointerRegisterToSaveRestore(AArch64::SP);
505 setSchedulingPreference(Sched::Hybrid);
508 MaskAndBranchFoldingIsLegal = true;
509 EnableExtLdPromotion = true;
511 setMinFunctionAlignment(2);
513 RequireStrictAlign = (Align == StrictAlign);
515 setHasExtractBitsInsn(true);
517 if (Subtarget->hasNEON()) {
518 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
519 // silliness like this:
520 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
521 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
522 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
523 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
524 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
525 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
526 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
527 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
528 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
529 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
530 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
531 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
532 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
533 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
534 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
535 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
536 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
537 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
538 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
539 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
540 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
541 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
542 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
543 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
544 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
546 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
547 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
548 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
549 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
550 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
552 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
554 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
555 // elements smaller than i32, so promote the input to i32 first.
556 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
557 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
560 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
561 // -> v8f16 conversions.
562 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
563 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
564 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
565 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
566 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
567 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
568 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
569 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
570 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
571 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
572 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
573 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
574 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
576 // AArch64 doesn't have MUL.2d:
577 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
578 // Custom handling for some quad-vector types to detect MULL.
579 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
580 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
581 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
583 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
584 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
585 // Likewise, narrowing and extending vector loads/stores aren't handled
587 for (MVT VT : MVT::vector_valuetypes()) {
588 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
590 setOperationAction(ISD::MULHS, VT, Expand);
591 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
592 setOperationAction(ISD::MULHU, VT, Expand);
593 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
595 setOperationAction(ISD::BSWAP, VT, Expand);
597 for (MVT InnerVT : MVT::vector_valuetypes()) {
598 setTruncStoreAction(VT, InnerVT, Expand);
599 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
600 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
601 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
605 // AArch64 has implementations of a lot of rounding-like FP operations.
606 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
607 setOperationAction(ISD::FFLOOR, Ty, Legal);
608 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
609 setOperationAction(ISD::FCEIL, Ty, Legal);
610 setOperationAction(ISD::FRINT, Ty, Legal);
611 setOperationAction(ISD::FTRUNC, Ty, Legal);
612 setOperationAction(ISD::FROUND, Ty, Legal);
616 // Prefer likely predicted branches to selects on out-of-order cores.
617 if (Subtarget->isCortexA57())
618 PredictableSelectIsExpensive = true;
621 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
622 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
623 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
624 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
626 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
627 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
628 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
629 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
630 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
632 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
633 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
636 // Mark vector float intrinsics as expand.
637 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
638 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
639 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
640 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
645 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
649 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
650 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
651 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
652 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
653 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
654 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
655 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
656 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
662 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
663 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
664 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
665 for (MVT InnerVT : MVT::all_valuetypes())
666 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
668 // CNT supports only B element sizes.
669 if (VT != MVT::v8i8 && VT != MVT::v16i8)
670 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
672 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
673 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
674 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
675 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
676 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
678 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
679 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
681 if (Subtarget->isLittleEndian()) {
682 for (unsigned im = (unsigned)ISD::PRE_INC;
683 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
684 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
685 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
690 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
691 addRegisterClass(VT, &AArch64::FPR64RegClass);
692 addTypeForNEON(VT, MVT::v2i32);
695 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
696 addRegisterClass(VT, &AArch64::FPR128RegClass);
697 addTypeForNEON(VT, MVT::v4i32);
700 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
703 return VT.changeVectorElementTypeToInteger();
706 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
707 /// Mask are known to be either zero or one and return them in the
708 /// KnownZero/KnownOne bitsets.
709 void AArch64TargetLowering::computeKnownBitsForTargetNode(
710 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
711 const SelectionDAG &DAG, unsigned Depth) const {
712 switch (Op.getOpcode()) {
715 case AArch64ISD::CSEL: {
716 APInt KnownZero2, KnownOne2;
717 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
718 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
719 KnownZero &= KnownZero2;
720 KnownOne &= KnownOne2;
723 case ISD::INTRINSIC_W_CHAIN: {
724 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
725 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
728 case Intrinsic::aarch64_ldaxr:
729 case Intrinsic::aarch64_ldxr: {
730 unsigned BitWidth = KnownOne.getBitWidth();
731 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
732 unsigned MemBits = VT.getScalarType().getSizeInBits();
733 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
739 case ISD::INTRINSIC_WO_CHAIN:
740 case ISD::INTRINSIC_VOID: {
741 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
745 case Intrinsic::aarch64_neon_umaxv:
746 case Intrinsic::aarch64_neon_uminv: {
747 // Figure out the datatype of the vector operand. The UMINV instruction
748 // will zero extend the result, so we can mark as known zero all the
749 // bits larger than the element datatype. 32-bit or larget doesn't need
750 // this as those are legal types and will be handled by isel directly.
751 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
752 unsigned BitWidth = KnownZero.getBitWidth();
753 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
754 assert(BitWidth >= 8 && "Unexpected width!");
755 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
757 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
758 assert(BitWidth >= 16 && "Unexpected width!");
759 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
769 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
774 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
775 const TargetLibraryInfo *libInfo) const {
776 return AArch64::createFastISel(funcInfo, libInfo);
779 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
783 case AArch64ISD::CALL: return "AArch64ISD::CALL";
784 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
785 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
786 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
787 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
788 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
789 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
790 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
791 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
792 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
793 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
794 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
795 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
796 case AArch64ISD::ADC: return "AArch64ISD::ADC";
797 case AArch64ISD::SBC: return "AArch64ISD::SBC";
798 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
799 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
800 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
801 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
802 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
803 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
804 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
805 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
806 case AArch64ISD::DUP: return "AArch64ISD::DUP";
807 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
808 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
809 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
810 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
811 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
812 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
813 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
814 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
815 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
816 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
817 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
818 case AArch64ISD::BICi: return "AArch64ISD::BICi";
819 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
820 case AArch64ISD::BSL: return "AArch64ISD::BSL";
821 case AArch64ISD::NEG: return "AArch64ISD::NEG";
822 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
823 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
824 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
825 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
826 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
827 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
828 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
829 case AArch64ISD::REV16: return "AArch64ISD::REV16";
830 case AArch64ISD::REV32: return "AArch64ISD::REV32";
831 case AArch64ISD::REV64: return "AArch64ISD::REV64";
832 case AArch64ISD::EXT: return "AArch64ISD::EXT";
833 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
834 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
835 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
836 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
837 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
838 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
839 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
840 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
841 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
842 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
843 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
844 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
845 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
846 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
847 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
848 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
849 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
850 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
851 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
852 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
853 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
854 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
855 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
856 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
857 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
858 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
859 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
860 case AArch64ISD::NOT: return "AArch64ISD::NOT";
861 case AArch64ISD::BIT: return "AArch64ISD::BIT";
862 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
863 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
864 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
865 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
866 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
867 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
868 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
869 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
870 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
871 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
872 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
873 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
874 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
875 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
876 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
877 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
878 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
879 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
880 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
881 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
882 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
883 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
884 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
885 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
886 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
887 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
888 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
889 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
890 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
891 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
892 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
893 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
894 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
895 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
896 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
897 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
898 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
899 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
900 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
905 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
906 MachineBasicBlock *MBB) const {
907 // We materialise the F128CSEL pseudo-instruction as some control flow and a
911 // [... previous instrs leading to comparison ...]
917 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
919 MachineFunction *MF = MBB->getParent();
920 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
921 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
922 DebugLoc DL = MI->getDebugLoc();
923 MachineFunction::iterator It = MBB;
926 unsigned DestReg = MI->getOperand(0).getReg();
927 unsigned IfTrueReg = MI->getOperand(1).getReg();
928 unsigned IfFalseReg = MI->getOperand(2).getReg();
929 unsigned CondCode = MI->getOperand(3).getImm();
930 bool NZCVKilled = MI->getOperand(4).isKill();
932 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
933 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
934 MF->insert(It, TrueBB);
935 MF->insert(It, EndBB);
937 // Transfer rest of current basic-block to EndBB
938 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
940 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
942 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
943 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
944 MBB->addSuccessor(TrueBB);
945 MBB->addSuccessor(EndBB);
947 // TrueBB falls through to the end.
948 TrueBB->addSuccessor(EndBB);
951 TrueBB->addLiveIn(AArch64::NZCV);
952 EndBB->addLiveIn(AArch64::NZCV);
955 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
961 MI->eraseFromParent();
966 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
967 MachineBasicBlock *BB) const {
968 switch (MI->getOpcode()) {
973 llvm_unreachable("Unexpected instruction for custom inserter!");
975 case AArch64::F128CSEL:
976 return EmitF128CSEL(MI, BB);
978 case TargetOpcode::STACKMAP:
979 case TargetOpcode::PATCHPOINT:
980 return emitPatchPoint(MI, BB);
984 //===----------------------------------------------------------------------===//
985 // AArch64 Lowering private implementation.
986 //===----------------------------------------------------------------------===//
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
992 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
994 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
997 llvm_unreachable("Unknown condition code!");
999 return AArch64CC::NE;
1001 return AArch64CC::EQ;
1003 return AArch64CC::GT;
1005 return AArch64CC::GE;
1007 return AArch64CC::LT;
1009 return AArch64CC::LE;
1011 return AArch64CC::HI;
1013 return AArch64CC::HS;
1015 return AArch64CC::LO;
1017 return AArch64CC::LS;
1021 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1022 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1023 AArch64CC::CondCode &CondCode,
1024 AArch64CC::CondCode &CondCode2) {
1025 CondCode2 = AArch64CC::AL;
1028 llvm_unreachable("Unknown FP condition!");
1031 CondCode = AArch64CC::EQ;
1035 CondCode = AArch64CC::GT;
1039 CondCode = AArch64CC::GE;
1042 CondCode = AArch64CC::MI;
1045 CondCode = AArch64CC::LS;
1048 CondCode = AArch64CC::MI;
1049 CondCode2 = AArch64CC::GT;
1052 CondCode = AArch64CC::VC;
1055 CondCode = AArch64CC::VS;
1058 CondCode = AArch64CC::EQ;
1059 CondCode2 = AArch64CC::VS;
1062 CondCode = AArch64CC::HI;
1065 CondCode = AArch64CC::PL;
1069 CondCode = AArch64CC::LT;
1073 CondCode = AArch64CC::LE;
1077 CondCode = AArch64CC::NE;
1082 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1083 /// CC usable with the vector instructions. Fewer operations are available
1084 /// without a real NZCV register, so we have to use less efficient combinations
1085 /// to get the same effect.
1086 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1087 AArch64CC::CondCode &CondCode,
1088 AArch64CC::CondCode &CondCode2,
1093 // Mostly the scalar mappings work fine.
1094 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1097 Invert = true; // Fallthrough
1099 CondCode = AArch64CC::MI;
1100 CondCode2 = AArch64CC::GE;
1107 // All of the compare-mask comparisons are ordered, but we can switch
1108 // between the two by a double inversion. E.g. ULE == !OGT.
1110 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1115 static bool isLegalArithImmed(uint64_t C) {
1116 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1117 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1120 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1121 SDLoc dl, SelectionDAG &DAG) {
1122 EVT VT = LHS.getValueType();
1124 if (VT.isFloatingPoint())
1125 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1127 // The CMP instruction is just an alias for SUBS, and representing it as
1128 // SUBS means that it's possible to get CSE with subtract operations.
1129 // A later phase can perform the optimization of setting the destination
1130 // register to WZR/XZR if it ends up being unused.
1131 unsigned Opcode = AArch64ISD::SUBS;
1133 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1134 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1135 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1136 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1137 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1138 // can be set differently by this operation. It comes down to whether
1139 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1140 // everything is fine. If not then the optimization is wrong. Thus general
1141 // comparisons are only valid if op2 != 0.
1143 // So, finally, the only LLVM-native comparisons that don't mention C and V
1144 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1145 // the absence of information about op2.
1146 Opcode = AArch64ISD::ADDS;
1147 RHS = RHS.getOperand(1);
1148 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1149 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1150 !isUnsignedIntSetCC(CC)) {
1151 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1152 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1153 // of the signed comparisons.
1154 Opcode = AArch64ISD::ANDS;
1155 RHS = LHS.getOperand(1);
1156 LHS = LHS.getOperand(0);
1159 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1163 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1164 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1166 AArch64CC::CondCode AArch64CC;
1167 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1168 EVT VT = RHS.getValueType();
1169 uint64_t C = RHSC->getZExtValue();
1170 if (!isLegalArithImmed(C)) {
1171 // Constant does not fit, try adjusting it by one?
1177 if ((VT == MVT::i32 && C != 0x80000000 &&
1178 isLegalArithImmed((uint32_t)(C - 1))) ||
1179 (VT == MVT::i64 && C != 0x80000000ULL &&
1180 isLegalArithImmed(C - 1ULL))) {
1181 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1182 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1183 RHS = DAG.getConstant(C, VT);
1188 if ((VT == MVT::i32 && C != 0 &&
1189 isLegalArithImmed((uint32_t)(C - 1))) ||
1190 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1191 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1192 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1193 RHS = DAG.getConstant(C, VT);
1198 if ((VT == MVT::i32 && C != INT32_MAX &&
1199 isLegalArithImmed((uint32_t)(C + 1))) ||
1200 (VT == MVT::i64 && C != INT64_MAX &&
1201 isLegalArithImmed(C + 1ULL))) {
1202 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1203 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1204 RHS = DAG.getConstant(C, VT);
1209 if ((VT == MVT::i32 && C != UINT32_MAX &&
1210 isLegalArithImmed((uint32_t)(C + 1))) ||
1211 (VT == MVT::i64 && C != UINT64_MAX &&
1212 isLegalArithImmed(C + 1ULL))) {
1213 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1214 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1215 RHS = DAG.getConstant(C, VT);
1221 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1222 // For the i8 operand, the largest immediate is 255, so this can be easily
1223 // encoded in the compare instruction. For the i16 operand, however, the
1224 // largest immediate cannot be encoded in the compare.
1225 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1226 // constant. For example,
1228 // ldrh w0, [x0, #0]
1231 // ldrsh w0, [x0, #0]
1233 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1234 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1235 // both the LHS and RHS are truely zero extended and to make sure the
1236 // transformation is profitable.
1237 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1238 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1239 isa<LoadSDNode>(LHS)) {
1240 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1241 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1242 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1243 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1244 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1246 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1247 DAG.getValueType(MVT::i16));
1248 Cmp = emitComparison(SExt,
1249 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1251 AArch64CC = changeIntCCToAArch64CC(CC);
1252 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1258 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1259 AArch64CC = changeIntCCToAArch64CC(CC);
1260 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1264 static std::pair<SDValue, SDValue>
1265 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1266 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1267 "Unsupported value type");
1268 SDValue Value, Overflow;
1270 SDValue LHS = Op.getOperand(0);
1271 SDValue RHS = Op.getOperand(1);
1273 switch (Op.getOpcode()) {
1275 llvm_unreachable("Unknown overflow instruction!");
1277 Opc = AArch64ISD::ADDS;
1281 Opc = AArch64ISD::ADDS;
1285 Opc = AArch64ISD::SUBS;
1289 Opc = AArch64ISD::SUBS;
1292 // Multiply needs a little bit extra work.
1296 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1297 if (Op.getValueType() == MVT::i32) {
1298 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1299 // For a 32 bit multiply with overflow check we want the instruction
1300 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1301 // need to generate the following pattern:
1302 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1303 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1304 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1305 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1306 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1307 DAG.getConstant(0, MVT::i64));
1308 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1309 // operation. We need to clear out the upper 32 bits, because we used a
1310 // widening multiply that wrote all 64 bits. In the end this should be a
1312 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1314 // The signed overflow check requires more than just a simple check for
1315 // any bit set in the upper 32 bits of the result. These bits could be
1316 // just the sign bits of a negative number. To perform the overflow
1317 // check we have to arithmetic shift right the 32nd bit of the result by
1318 // 31 bits. Then we compare the result to the upper 32 bits.
1319 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1320 DAG.getConstant(32, MVT::i64));
1321 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1322 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1323 DAG.getConstant(31, MVT::i64));
1324 // It is important that LowerBits is last, otherwise the arithmetic
1325 // shift will not be folded into the compare (SUBS).
1326 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1327 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1330 // The overflow check for unsigned multiply is easy. We only need to
1331 // check if any of the upper 32 bits are set. This can be done with a
1332 // CMP (shifted register). For that we need to generate the following
1334 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1335 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1336 DAG.getConstant(32, MVT::i64));
1337 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1339 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1340 UpperBits).getValue(1);
1344 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1345 // For the 64 bit multiply
1346 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1348 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1349 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1350 DAG.getConstant(63, MVT::i64));
1351 // It is important that LowerBits is last, otherwise the arithmetic
1352 // shift will not be folded into the compare (SUBS).
1353 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1354 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1357 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1358 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1360 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1361 UpperBits).getValue(1);
1368 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1370 // Emit the AArch64 operation with overflow check.
1371 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1372 Overflow = Value.getValue(1);
1374 return std::make_pair(Value, Overflow);
1377 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1378 RTLIB::Libcall Call) const {
1379 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1380 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1384 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1385 SDValue Sel = Op.getOperand(0);
1386 SDValue Other = Op.getOperand(1);
1388 // If neither operand is a SELECT_CC, give up.
1389 if (Sel.getOpcode() != ISD::SELECT_CC)
1390 std::swap(Sel, Other);
1391 if (Sel.getOpcode() != ISD::SELECT_CC)
1394 // The folding we want to perform is:
1395 // (xor x, (select_cc a, b, cc, 0, -1) )
1397 // (csel x, (xor x, -1), cc ...)
1399 // The latter will get matched to a CSINV instruction.
1401 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1402 SDValue LHS = Sel.getOperand(0);
1403 SDValue RHS = Sel.getOperand(1);
1404 SDValue TVal = Sel.getOperand(2);
1405 SDValue FVal = Sel.getOperand(3);
1408 // FIXME: This could be generalized to non-integer comparisons.
1409 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1412 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1413 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1415 // The the values aren't constants, this isn't the pattern we're looking for.
1416 if (!CFVal || !CTVal)
1419 // We can commute the SELECT_CC by inverting the condition. This
1420 // might be needed to make this fit into a CSINV pattern.
1421 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1422 std::swap(TVal, FVal);
1423 std::swap(CTVal, CFVal);
1424 CC = ISD::getSetCCInverse(CC, true);
1427 // If the constants line up, perform the transform!
1428 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1430 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1433 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1434 DAG.getConstant(-1ULL, Other.getValueType()));
1436 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1443 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1444 EVT VT = Op.getValueType();
1446 // Let legalize expand this if it isn't a legal type yet.
1447 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1450 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1453 bool ExtraOp = false;
1454 switch (Op.getOpcode()) {
1456 llvm_unreachable("Invalid code");
1458 Opc = AArch64ISD::ADDS;
1461 Opc = AArch64ISD::SUBS;
1464 Opc = AArch64ISD::ADCS;
1468 Opc = AArch64ISD::SBCS;
1474 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1475 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1479 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1480 // Let legalize expand this if it isn't a legal type yet.
1481 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1484 AArch64CC::CondCode CC;
1485 // The actual operation that sets the overflow or carry flag.
1486 SDValue Value, Overflow;
1487 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1489 // We use 0 and 1 as false and true values.
1490 SDValue TVal = DAG.getConstant(1, MVT::i32);
1491 SDValue FVal = DAG.getConstant(0, MVT::i32);
1493 // We use an inverted condition, because the conditional select is inverted
1494 // too. This will allow it to be selected to a single instruction:
1495 // CSINC Wd, WZR, WZR, invert(cond).
1496 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1497 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1500 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1501 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1504 // Prefetch operands are:
1505 // 1: Address to prefetch
1507 // 3: int locality (0 = no locality ... 3 = extreme locality)
1508 // 4: bool isDataCache
1509 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1511 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1512 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1513 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1515 bool IsStream = !Locality;
1516 // When the locality number is set
1518 // The front-end should have filtered out the out-of-range values
1519 assert(Locality <= 3 && "Prefetch locality out-of-range");
1520 // The locality degree is the opposite of the cache speed.
1521 // Put the number the other way around.
1522 // The encoding starts at 0 for level 1
1523 Locality = 3 - Locality;
1526 // built the mask value encoding the expected behavior.
1527 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1528 (!IsData << 3) | // IsDataCache bit
1529 (Locality << 1) | // Cache level bits
1530 (unsigned)IsStream; // Stream bit
1531 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1532 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1535 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1536 SelectionDAG &DAG) const {
1537 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1540 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1542 return LowerF128Call(Op, DAG, LC);
1545 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1546 SelectionDAG &DAG) const {
1547 if (Op.getOperand(0).getValueType() != MVT::f128) {
1548 // It's legal except when f128 is involved
1553 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1555 // FP_ROUND node has a second operand indicating whether it is known to be
1556 // precise. That doesn't take part in the LibCall so we can't directly use
1558 SDValue SrcVal = Op.getOperand(0);
1559 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1560 /*isSigned*/ false, SDLoc(Op)).first;
1563 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1564 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1565 // Any additional optimization in this function should be recorded
1566 // in the cost tables.
1567 EVT InVT = Op.getOperand(0).getValueType();
1568 EVT VT = Op.getValueType();
1570 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1573 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1575 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1578 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1581 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1582 VT.getVectorNumElements());
1583 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1584 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1587 // Type changing conversions are illegal.
1591 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1592 SelectionDAG &DAG) const {
1593 if (Op.getOperand(0).getValueType().isVector())
1594 return LowerVectorFP_TO_INT(Op, DAG);
1596 // f16 conversions are promoted to f32.
1597 if (Op.getOperand(0).getValueType() == MVT::f16) {
1600 Op.getOpcode(), dl, Op.getValueType(),
1601 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1604 if (Op.getOperand(0).getValueType() != MVT::f128) {
1605 // It's legal except when f128 is involved
1610 if (Op.getOpcode() == ISD::FP_TO_SINT)
1611 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1613 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1615 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1616 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1620 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1621 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1622 // Any additional optimization in this function should be recorded
1623 // in the cost tables.
1624 EVT VT = Op.getValueType();
1626 SDValue In = Op.getOperand(0);
1627 EVT InVT = In.getValueType();
1629 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1631 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1632 InVT.getVectorNumElements());
1633 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1634 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1637 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1639 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1640 EVT CastVT = VT.changeVectorElementTypeToInteger();
1641 In = DAG.getNode(CastOpc, dl, CastVT, In);
1642 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1648 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1649 SelectionDAG &DAG) const {
1650 if (Op.getValueType().isVector())
1651 return LowerVectorINT_TO_FP(Op, DAG);
1653 // f16 conversions are promoted to f32.
1654 if (Op.getValueType() == MVT::f16) {
1657 ISD::FP_ROUND, dl, MVT::f16,
1658 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1659 DAG.getIntPtrConstant(0));
1662 // i128 conversions are libcalls.
1663 if (Op.getOperand(0).getValueType() == MVT::i128)
1666 // Other conversions are legal, unless it's to the completely software-based
1668 if (Op.getValueType() != MVT::f128)
1672 if (Op.getOpcode() == ISD::SINT_TO_FP)
1673 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1675 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1677 return LowerF128Call(Op, DAG, LC);
1680 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1681 SelectionDAG &DAG) const {
1682 // For iOS, we want to call an alternative entry point: __sincos_stret,
1683 // which returns the values in two S / D registers.
1685 SDValue Arg = Op.getOperand(0);
1686 EVT ArgVT = Arg.getValueType();
1687 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1694 Entry.isSExt = false;
1695 Entry.isZExt = false;
1696 Args.push_back(Entry);
1698 const char *LibcallName =
1699 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1700 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1702 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1703 TargetLowering::CallLoweringInfo CLI(DAG);
1704 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1705 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1707 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1708 return CallResult.first;
1711 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1712 if (Op.getValueType() != MVT::f16)
1715 assert(Op.getOperand(0).getValueType() == MVT::i16);
1718 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1719 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1721 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1722 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1726 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1727 if (OrigVT.getSizeInBits() >= 64)
1730 assert(OrigVT.isSimple() && "Expecting a simple value type");
1732 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1733 switch (OrigSimpleTy) {
1734 default: llvm_unreachable("Unexpected Vector Type");
1743 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1746 unsigned ExtOpcode) {
1747 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1748 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1749 // 64-bits we need to insert a new extension so that it will be 64-bits.
1750 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1751 if (OrigTy.getSizeInBits() >= 64)
1754 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1755 EVT NewVT = getExtensionTo64Bits(OrigTy);
1757 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1760 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1762 EVT VT = N->getValueType(0);
1764 if (N->getOpcode() != ISD::BUILD_VECTOR)
1767 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1768 SDNode *Elt = N->getOperand(i).getNode();
1769 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1770 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1771 unsigned HalfSize = EltSize / 2;
1773 if (!isIntN(HalfSize, C->getSExtValue()))
1776 if (!isUIntN(HalfSize, C->getZExtValue()))
1787 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1788 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1789 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1790 N->getOperand(0)->getValueType(0),
1794 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1795 EVT VT = N->getValueType(0);
1796 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1797 unsigned NumElts = VT.getVectorNumElements();
1798 MVT TruncVT = MVT::getIntegerVT(EltSize);
1799 SmallVector<SDValue, 8> Ops;
1800 for (unsigned i = 0; i != NumElts; ++i) {
1801 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1802 const APInt &CInt = C->getAPIntValue();
1803 // Element types smaller than 32 bits are not legal, so use i32 elements.
1804 // The values are implicitly truncated so sext vs. zext doesn't matter.
1805 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1807 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1808 MVT::getVectorVT(TruncVT, NumElts), Ops);
1811 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1812 if (N->getOpcode() == ISD::SIGN_EXTEND)
1814 if (isExtendedBUILD_VECTOR(N, DAG, true))
1819 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1820 if (N->getOpcode() == ISD::ZERO_EXTEND)
1822 if (isExtendedBUILD_VECTOR(N, DAG, false))
1827 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1828 unsigned Opcode = N->getOpcode();
1829 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1830 SDNode *N0 = N->getOperand(0).getNode();
1831 SDNode *N1 = N->getOperand(1).getNode();
1832 return N0->hasOneUse() && N1->hasOneUse() &&
1833 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1838 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1839 unsigned Opcode = N->getOpcode();
1840 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1841 SDNode *N0 = N->getOperand(0).getNode();
1842 SDNode *N1 = N->getOperand(1).getNode();
1843 return N0->hasOneUse() && N1->hasOneUse() &&
1844 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1849 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1850 // Multiplications are only custom-lowered for 128-bit vectors so that
1851 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1852 EVT VT = Op.getValueType();
1853 assert(VT.is128BitVector() && VT.isInteger() &&
1854 "unexpected type for custom-lowering ISD::MUL");
1855 SDNode *N0 = Op.getOperand(0).getNode();
1856 SDNode *N1 = Op.getOperand(1).getNode();
1857 unsigned NewOpc = 0;
1859 bool isN0SExt = isSignExtended(N0, DAG);
1860 bool isN1SExt = isSignExtended(N1, DAG);
1861 if (isN0SExt && isN1SExt)
1862 NewOpc = AArch64ISD::SMULL;
1864 bool isN0ZExt = isZeroExtended(N0, DAG);
1865 bool isN1ZExt = isZeroExtended(N1, DAG);
1866 if (isN0ZExt && isN1ZExt)
1867 NewOpc = AArch64ISD::UMULL;
1868 else if (isN1SExt || isN1ZExt) {
1869 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1870 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1871 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1872 NewOpc = AArch64ISD::SMULL;
1874 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1875 NewOpc = AArch64ISD::UMULL;
1877 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1879 NewOpc = AArch64ISD::UMULL;
1885 if (VT == MVT::v2i64)
1886 // Fall through to expand this. It is not legal.
1889 // Other vector multiplications are legal.
1894 // Legalize to a S/UMULL instruction
1897 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1899 Op0 = skipExtensionForVectorMULL(N0, DAG);
1900 assert(Op0.getValueType().is64BitVector() &&
1901 Op1.getValueType().is64BitVector() &&
1902 "unexpected types for extended operands to VMULL");
1903 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1905 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1906 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1907 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1908 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1909 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1910 EVT Op1VT = Op1.getValueType();
1911 return DAG.getNode(N0->getOpcode(), DL, VT,
1912 DAG.getNode(NewOpc, DL, VT,
1913 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1914 DAG.getNode(NewOpc, DL, VT,
1915 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1918 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1919 SelectionDAG &DAG) const {
1920 switch (Op.getOpcode()) {
1922 llvm_unreachable("unimplemented operand");
1925 return LowerBITCAST(Op, DAG);
1926 case ISD::GlobalAddress:
1927 return LowerGlobalAddress(Op, DAG);
1928 case ISD::GlobalTLSAddress:
1929 return LowerGlobalTLSAddress(Op, DAG);
1931 return LowerSETCC(Op, DAG);
1933 return LowerBR_CC(Op, DAG);
1935 return LowerSELECT(Op, DAG);
1936 case ISD::SELECT_CC:
1937 return LowerSELECT_CC(Op, DAG);
1938 case ISD::JumpTable:
1939 return LowerJumpTable(Op, DAG);
1940 case ISD::ConstantPool:
1941 return LowerConstantPool(Op, DAG);
1942 case ISD::BlockAddress:
1943 return LowerBlockAddress(Op, DAG);
1945 return LowerVASTART(Op, DAG);
1947 return LowerVACOPY(Op, DAG);
1949 return LowerVAARG(Op, DAG);
1954 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1961 return LowerXALUO(Op, DAG);
1963 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1965 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1967 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1969 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1971 return LowerFP_ROUND(Op, DAG);
1972 case ISD::FP_EXTEND:
1973 return LowerFP_EXTEND(Op, DAG);
1974 case ISD::FRAMEADDR:
1975 return LowerFRAMEADDR(Op, DAG);
1976 case ISD::RETURNADDR:
1977 return LowerRETURNADDR(Op, DAG);
1978 case ISD::INSERT_VECTOR_ELT:
1979 return LowerINSERT_VECTOR_ELT(Op, DAG);
1980 case ISD::EXTRACT_VECTOR_ELT:
1981 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1982 case ISD::BUILD_VECTOR:
1983 return LowerBUILD_VECTOR(Op, DAG);
1984 case ISD::VECTOR_SHUFFLE:
1985 return LowerVECTOR_SHUFFLE(Op, DAG);
1986 case ISD::EXTRACT_SUBVECTOR:
1987 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1991 return LowerVectorSRA_SRL_SHL(Op, DAG);
1992 case ISD::SHL_PARTS:
1993 return LowerShiftLeftParts(Op, DAG);
1994 case ISD::SRL_PARTS:
1995 case ISD::SRA_PARTS:
1996 return LowerShiftRightParts(Op, DAG);
1998 return LowerCTPOP(Op, DAG);
1999 case ISD::FCOPYSIGN:
2000 return LowerFCOPYSIGN(Op, DAG);
2002 return LowerVectorAND(Op, DAG);
2004 return LowerVectorOR(Op, DAG);
2006 return LowerXOR(Op, DAG);
2008 return LowerPREFETCH(Op, DAG);
2009 case ISD::SINT_TO_FP:
2010 case ISD::UINT_TO_FP:
2011 return LowerINT_TO_FP(Op, DAG);
2012 case ISD::FP_TO_SINT:
2013 case ISD::FP_TO_UINT:
2014 return LowerFP_TO_INT(Op, DAG);
2016 return LowerFSINCOS(Op, DAG);
2018 return LowerMUL(Op, DAG);
2022 /// getFunctionAlignment - Return the Log2 alignment of this function.
2023 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2027 //===----------------------------------------------------------------------===//
2028 // Calling Convention Implementation
2029 //===----------------------------------------------------------------------===//
2031 #include "AArch64GenCallingConv.inc"
2033 /// Selects the correct CCAssignFn for a given CallingConvention value.
2034 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2035 bool IsVarArg) const {
2038 llvm_unreachable("Unsupported calling convention.");
2039 case CallingConv::WebKit_JS:
2040 return CC_AArch64_WebKit_JS;
2041 case CallingConv::GHC:
2042 return CC_AArch64_GHC;
2043 case CallingConv::C:
2044 case CallingConv::Fast:
2045 if (!Subtarget->isTargetDarwin())
2046 return CC_AArch64_AAPCS;
2047 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2051 SDValue AArch64TargetLowering::LowerFormalArguments(
2052 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2053 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2054 SmallVectorImpl<SDValue> &InVals) const {
2055 MachineFunction &MF = DAG.getMachineFunction();
2056 MachineFrameInfo *MFI = MF.getFrameInfo();
2058 // Assign locations to all of the incoming arguments.
2059 SmallVector<CCValAssign, 16> ArgLocs;
2060 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2063 // At this point, Ins[].VT may already be promoted to i32. To correctly
2064 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2065 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2066 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2067 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2069 unsigned NumArgs = Ins.size();
2070 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2071 unsigned CurArgIdx = 0;
2072 for (unsigned i = 0; i != NumArgs; ++i) {
2073 MVT ValVT = Ins[i].VT;
2074 if (Ins[i].isOrigArg()) {
2075 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2076 CurArgIdx = Ins[i].getOrigArgIndex();
2078 // Get type of the original argument.
2079 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2080 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2081 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2082 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2084 else if (ActualMVT == MVT::i16)
2087 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2089 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2090 assert(!Res && "Call operand has unhandled type");
2093 assert(ArgLocs.size() == Ins.size());
2094 SmallVector<SDValue, 16> ArgValues;
2095 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2096 CCValAssign &VA = ArgLocs[i];
2098 if (Ins[i].Flags.isByVal()) {
2099 // Byval is used for HFAs in the PCS, but the system should work in a
2100 // non-compliant manner for larger structs.
2101 EVT PtrTy = getPointerTy();
2102 int Size = Ins[i].Flags.getByValSize();
2103 unsigned NumRegs = (Size + 7) / 8;
2105 // FIXME: This works on big-endian for composite byvals, which are the common
2106 // case. It should also work for fundamental types too.
2108 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2109 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2110 InVals.push_back(FrameIdxN);
2115 if (VA.isRegLoc()) {
2116 // Arguments stored in registers.
2117 EVT RegVT = VA.getLocVT();
2120 const TargetRegisterClass *RC;
2122 if (RegVT == MVT::i32)
2123 RC = &AArch64::GPR32RegClass;
2124 else if (RegVT == MVT::i64)
2125 RC = &AArch64::GPR64RegClass;
2126 else if (RegVT == MVT::f16)
2127 RC = &AArch64::FPR16RegClass;
2128 else if (RegVT == MVT::f32)
2129 RC = &AArch64::FPR32RegClass;
2130 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2131 RC = &AArch64::FPR64RegClass;
2132 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2133 RC = &AArch64::FPR128RegClass;
2135 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2137 // Transform the arguments in physical registers into virtual ones.
2138 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2139 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2141 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2142 // to 64 bits. Insert an assert[sz]ext to capture this, then
2143 // truncate to the right size.
2144 switch (VA.getLocInfo()) {
2146 llvm_unreachable("Unknown loc info!");
2147 case CCValAssign::Full:
2149 case CCValAssign::BCvt:
2150 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2152 case CCValAssign::AExt:
2153 case CCValAssign::SExt:
2154 case CCValAssign::ZExt:
2155 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2156 // nodes after our lowering.
2157 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2161 InVals.push_back(ArgValue);
2163 } else { // VA.isRegLoc()
2164 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2165 unsigned ArgOffset = VA.getLocMemOffset();
2166 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2168 uint32_t BEAlign = 0;
2169 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2170 !Ins[i].Flags.isInConsecutiveRegs())
2171 BEAlign = 8 - ArgSize;
2173 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2175 // Create load nodes to retrieve arguments from the stack.
2176 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2179 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2180 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2181 MVT MemVT = VA.getValVT();
2183 switch (VA.getLocInfo()) {
2186 case CCValAssign::BCvt:
2187 MemVT = VA.getLocVT();
2189 case CCValAssign::SExt:
2190 ExtType = ISD::SEXTLOAD;
2192 case CCValAssign::ZExt:
2193 ExtType = ISD::ZEXTLOAD;
2195 case CCValAssign::AExt:
2196 ExtType = ISD::EXTLOAD;
2200 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2201 MachinePointerInfo::getFixedStack(FI),
2202 MemVT, false, false, false, 0);
2204 InVals.push_back(ArgValue);
2210 if (!Subtarget->isTargetDarwin()) {
2211 // The AAPCS variadic function ABI is identical to the non-variadic
2212 // one. As a result there may be more arguments in registers and we should
2213 // save them for future reference.
2214 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2217 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2218 // This will point to the next argument passed via stack.
2219 unsigned StackOffset = CCInfo.getNextStackOffset();
2220 // We currently pass all varargs at 8-byte alignment.
2221 StackOffset = ((StackOffset + 7) & ~7);
2222 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2225 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2226 unsigned StackArgSize = CCInfo.getNextStackOffset();
2227 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2228 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2229 // This is a non-standard ABI so by fiat I say we're allowed to make full
2230 // use of the stack area to be popped, which must be aligned to 16 bytes in
2232 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2234 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2235 // a multiple of 16.
2236 FuncInfo->setArgumentStackToRestore(StackArgSize);
2238 // This realignment carries over to the available bytes below. Our own
2239 // callers will guarantee the space is free by giving an aligned value to
2242 // Even if we're not expected to free up the space, it's useful to know how
2243 // much is there while considering tail calls (because we can reuse it).
2244 FuncInfo->setBytesInStackArgArea(StackArgSize);
2249 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2250 SelectionDAG &DAG, SDLoc DL,
2251 SDValue &Chain) const {
2252 MachineFunction &MF = DAG.getMachineFunction();
2253 MachineFrameInfo *MFI = MF.getFrameInfo();
2254 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2256 SmallVector<SDValue, 8> MemOps;
2258 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2259 AArch64::X3, AArch64::X4, AArch64::X5,
2260 AArch64::X6, AArch64::X7 };
2261 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2262 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2264 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2266 if (GPRSaveSize != 0) {
2267 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2269 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2271 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2272 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2273 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2275 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2276 MachinePointerInfo::getStack(i * 8), false, false, 0);
2277 MemOps.push_back(Store);
2278 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2279 DAG.getConstant(8, getPointerTy()));
2282 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2283 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2285 if (Subtarget->hasFPARMv8()) {
2286 static const MCPhysReg FPRArgRegs[] = {
2287 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2288 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2289 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2290 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2292 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2294 if (FPRSaveSize != 0) {
2295 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2297 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2299 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2300 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2301 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2304 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2305 MachinePointerInfo::getStack(i * 16), false, false, 0);
2306 MemOps.push_back(Store);
2307 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2308 DAG.getConstant(16, getPointerTy()));
2311 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2312 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2315 if (!MemOps.empty()) {
2316 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2320 /// LowerCallResult - Lower the result values of a call into the
2321 /// appropriate copies out of appropriate physical registers.
2322 SDValue AArch64TargetLowering::LowerCallResult(
2323 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2324 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2325 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2326 SDValue ThisVal) const {
2327 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2328 ? RetCC_AArch64_WebKit_JS
2329 : RetCC_AArch64_AAPCS;
2330 // Assign locations to each value returned by this call.
2331 SmallVector<CCValAssign, 16> RVLocs;
2332 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2334 CCInfo.AnalyzeCallResult(Ins, RetCC);
2336 // Copy all of the result registers out of their specified physreg.
2337 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2338 CCValAssign VA = RVLocs[i];
2340 // Pass 'this' value directly from the argument to return value, to avoid
2341 // reg unit interference
2342 if (i == 0 && isThisReturn) {
2343 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2344 "unexpected return calling convention register assignment");
2345 InVals.push_back(ThisVal);
2350 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2351 Chain = Val.getValue(1);
2352 InFlag = Val.getValue(2);
2354 switch (VA.getLocInfo()) {
2356 llvm_unreachable("Unknown loc info!");
2357 case CCValAssign::Full:
2359 case CCValAssign::BCvt:
2360 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2364 InVals.push_back(Val);
2370 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2371 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2372 bool isCalleeStructRet, bool isCallerStructRet,
2373 const SmallVectorImpl<ISD::OutputArg> &Outs,
2374 const SmallVectorImpl<SDValue> &OutVals,
2375 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2376 // For CallingConv::C this function knows whether the ABI needs
2377 // changing. That's not true for other conventions so they will have to opt in
2379 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2382 const MachineFunction &MF = DAG.getMachineFunction();
2383 const Function *CallerF = MF.getFunction();
2384 CallingConv::ID CallerCC = CallerF->getCallingConv();
2385 bool CCMatch = CallerCC == CalleeCC;
2387 // Byval parameters hand the function a pointer directly into the stack area
2388 // we want to reuse during a tail call. Working around this *is* possible (see
2389 // X86) but less efficient and uglier in LowerCall.
2390 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2391 e = CallerF->arg_end();
2393 if (i->hasByValAttr())
2396 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2397 if (IsTailCallConvention(CalleeCC) && CCMatch)
2402 // Externally-defined functions with weak linkage should not be
2403 // tail-called on AArch64 when the OS does not support dynamic
2404 // pre-emption of symbols, as the AAELF spec requires normal calls
2405 // to undefined weak functions to be replaced with a NOP or jump to the
2406 // next instruction. The behaviour of branch instructions in this
2407 // situation (as used for tail calls) is implementation-defined, so we
2408 // cannot rely on the linker replacing the tail call with a return.
2409 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2410 const GlobalValue *GV = G->getGlobal();
2411 const Triple TT(getTargetMachine().getTargetTriple());
2412 if (GV->hasExternalWeakLinkage() &&
2413 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2417 // Now we search for cases where we can use a tail call without changing the
2418 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2421 // I want anyone implementing a new calling convention to think long and hard
2422 // about this assert.
2423 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2424 "Unexpected variadic calling convention");
2426 if (isVarArg && !Outs.empty()) {
2427 // At least two cases here: if caller is fastcc then we can't have any
2428 // memory arguments (we'd be expected to clean up the stack afterwards). If
2429 // caller is C then we could potentially use its argument area.
2431 // FIXME: for now we take the most conservative of these in both cases:
2432 // disallow all variadic memory operands.
2433 SmallVector<CCValAssign, 16> ArgLocs;
2434 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2437 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2438 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2439 if (!ArgLocs[i].isRegLoc())
2443 // If the calling conventions do not match, then we'd better make sure the
2444 // results are returned in the same way as what the caller expects.
2446 SmallVector<CCValAssign, 16> RVLocs1;
2447 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2449 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2451 SmallVector<CCValAssign, 16> RVLocs2;
2452 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2454 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2456 if (RVLocs1.size() != RVLocs2.size())
2458 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2459 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2461 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2463 if (RVLocs1[i].isRegLoc()) {
2464 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2467 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2473 // Nothing more to check if the callee is taking no arguments
2477 SmallVector<CCValAssign, 16> ArgLocs;
2478 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2481 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2483 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2485 // If the stack arguments for this call would fit into our own save area then
2486 // the call can be made tail.
2487 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2490 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2492 MachineFrameInfo *MFI,
2493 int ClobberedFI) const {
2494 SmallVector<SDValue, 8> ArgChains;
2495 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2496 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2498 // Include the original chain at the beginning of the list. When this is
2499 // used by target LowerCall hooks, this helps legalize find the
2500 // CALLSEQ_BEGIN node.
2501 ArgChains.push_back(Chain);
2503 // Add a chain value for each stack argument corresponding
2504 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2505 UE = DAG.getEntryNode().getNode()->use_end();
2507 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2508 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2509 if (FI->getIndex() < 0) {
2510 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2511 int64_t InLastByte = InFirstByte;
2512 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2514 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2515 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2516 ArgChains.push_back(SDValue(L, 1));
2519 // Build a tokenfactor for all the chains.
2520 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2523 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2524 bool TailCallOpt) const {
2525 return CallCC == CallingConv::Fast && TailCallOpt;
2528 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2529 return CallCC == CallingConv::Fast;
2532 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2533 /// and add input and output parameter nodes.
2535 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2536 SmallVectorImpl<SDValue> &InVals) const {
2537 SelectionDAG &DAG = CLI.DAG;
2539 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2540 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2541 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2542 SDValue Chain = CLI.Chain;
2543 SDValue Callee = CLI.Callee;
2544 bool &IsTailCall = CLI.IsTailCall;
2545 CallingConv::ID CallConv = CLI.CallConv;
2546 bool IsVarArg = CLI.IsVarArg;
2548 MachineFunction &MF = DAG.getMachineFunction();
2549 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2550 bool IsThisReturn = false;
2552 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2553 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2554 bool IsSibCall = false;
2557 // Check if it's really possible to do a tail call.
2558 IsTailCall = isEligibleForTailCallOptimization(
2559 Callee, CallConv, IsVarArg, IsStructRet,
2560 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2561 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2562 report_fatal_error("failed to perform tail call elimination on a call "
2563 "site marked musttail");
2565 // A sibling call is one where we're under the usual C ABI and not planning
2566 // to change that but can still do a tail call:
2567 if (!TailCallOpt && IsTailCall)
2574 // Analyze operands of the call, assigning locations to each operand.
2575 SmallVector<CCValAssign, 16> ArgLocs;
2576 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2580 // Handle fixed and variable vector arguments differently.
2581 // Variable vector arguments always go into memory.
2582 unsigned NumArgs = Outs.size();
2584 for (unsigned i = 0; i != NumArgs; ++i) {
2585 MVT ArgVT = Outs[i].VT;
2586 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2587 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2588 /*IsVarArg=*/ !Outs[i].IsFixed);
2589 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2590 assert(!Res && "Call operand has unhandled type");
2594 // At this point, Outs[].VT may already be promoted to i32. To correctly
2595 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2596 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2597 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2598 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2600 unsigned NumArgs = Outs.size();
2601 for (unsigned i = 0; i != NumArgs; ++i) {
2602 MVT ValVT = Outs[i].VT;
2603 // Get type of the original argument.
2604 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2605 /*AllowUnknown*/ true);
2606 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2607 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2608 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2609 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2611 else if (ActualMVT == MVT::i16)
2614 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2615 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2616 assert(!Res && "Call operand has unhandled type");
2621 // Get a count of how many bytes are to be pushed on the stack.
2622 unsigned NumBytes = CCInfo.getNextStackOffset();
2625 // Since we're not changing the ABI to make this a tail call, the memory
2626 // operands are already available in the caller's incoming argument space.
2630 // FPDiff is the byte offset of the call's argument area from the callee's.
2631 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2632 // by this amount for a tail call. In a sibling call it must be 0 because the
2633 // caller will deallocate the entire stack and the callee still expects its
2634 // arguments to begin at SP+0. Completely unused for non-tail calls.
2637 if (IsTailCall && !IsSibCall) {
2638 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2640 // Since callee will pop argument stack as a tail call, we must keep the
2641 // popped size 16-byte aligned.
2642 NumBytes = RoundUpToAlignment(NumBytes, 16);
2644 // FPDiff will be negative if this tail call requires more space than we
2645 // would automatically have in our incoming argument space. Positive if we
2646 // can actually shrink the stack.
2647 FPDiff = NumReusableBytes - NumBytes;
2649 // The stack pointer must be 16-byte aligned at all times it's used for a
2650 // memory operation, which in practice means at *all* times and in
2651 // particular across call boundaries. Therefore our own arguments started at
2652 // a 16-byte aligned SP and the delta applied for the tail call should
2653 // satisfy the same constraint.
2654 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2657 // Adjust the stack pointer for the new arguments...
2658 // These operations are automatically eliminated by the prolog/epilog pass
2661 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2663 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2665 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2666 SmallVector<SDValue, 8> MemOpChains;
2668 // Walk the register/memloc assignments, inserting copies/loads.
2669 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2670 ++i, ++realArgIdx) {
2671 CCValAssign &VA = ArgLocs[i];
2672 SDValue Arg = OutVals[realArgIdx];
2673 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2675 // Promote the value if needed.
2676 switch (VA.getLocInfo()) {
2678 llvm_unreachable("Unknown loc info!");
2679 case CCValAssign::Full:
2681 case CCValAssign::SExt:
2682 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2684 case CCValAssign::ZExt:
2685 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2687 case CCValAssign::AExt:
2688 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2689 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2690 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2691 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2693 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2695 case CCValAssign::BCvt:
2696 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2698 case CCValAssign::FPExt:
2699 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2703 if (VA.isRegLoc()) {
2704 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2705 assert(VA.getLocVT() == MVT::i64 &&
2706 "unexpected calling convention register assignment");
2707 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2708 "unexpected use of 'returned'");
2709 IsThisReturn = true;
2711 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2713 assert(VA.isMemLoc());
2716 MachinePointerInfo DstInfo;
2718 // FIXME: This works on big-endian for composite byvals, which are the
2719 // common case. It should also work for fundamental types too.
2720 uint32_t BEAlign = 0;
2721 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2722 : VA.getValVT().getSizeInBits();
2723 OpSize = (OpSize + 7) / 8;
2724 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2725 !Flags.isInConsecutiveRegs()) {
2727 BEAlign = 8 - OpSize;
2729 unsigned LocMemOffset = VA.getLocMemOffset();
2730 int32_t Offset = LocMemOffset + BEAlign;
2731 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2732 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2735 Offset = Offset + FPDiff;
2736 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2738 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2739 DstInfo = MachinePointerInfo::getFixedStack(FI);
2741 // Make sure any stack arguments overlapping with where we're storing
2742 // are loaded before this eventual operation. Otherwise they'll be
2744 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2746 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2748 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2749 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2752 if (Outs[i].Flags.isByVal()) {
2754 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2755 SDValue Cpy = DAG.getMemcpy(
2756 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2757 /*isVol = */ false, /*AlwaysInline = */ false,
2758 /*isTailCall = */ false,
2759 DstInfo, MachinePointerInfo());
2761 MemOpChains.push_back(Cpy);
2763 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2764 // promoted to a legal register type i32, we should truncate Arg back to
2766 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2767 VA.getValVT() == MVT::i16)
2768 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2771 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2772 MemOpChains.push_back(Store);
2777 if (!MemOpChains.empty())
2778 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2780 // Build a sequence of copy-to-reg nodes chained together with token chain
2781 // and flag operands which copy the outgoing args into the appropriate regs.
2783 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2784 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2785 RegsToPass[i].second, InFlag);
2786 InFlag = Chain.getValue(1);
2789 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2790 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2791 // node so that legalize doesn't hack it.
2792 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2793 Subtarget->isTargetMachO()) {
2794 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2795 const GlobalValue *GV = G->getGlobal();
2796 bool InternalLinkage = GV->hasInternalLinkage();
2797 if (InternalLinkage)
2798 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2800 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2802 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2804 } else if (ExternalSymbolSDNode *S =
2805 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2806 const char *Sym = S->getSymbol();
2808 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2809 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2811 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2812 const GlobalValue *GV = G->getGlobal();
2813 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2814 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2815 const char *Sym = S->getSymbol();
2816 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2819 // We don't usually want to end the call-sequence here because we would tidy
2820 // the frame up *after* the call, however in the ABI-changing tail-call case
2821 // we've carefully laid out the parameters so that when sp is reset they'll be
2822 // in the correct location.
2823 if (IsTailCall && !IsSibCall) {
2824 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2825 DAG.getIntPtrConstant(0, true), InFlag, DL);
2826 InFlag = Chain.getValue(1);
2829 std::vector<SDValue> Ops;
2830 Ops.push_back(Chain);
2831 Ops.push_back(Callee);
2834 // Each tail call may have to adjust the stack by a different amount, so
2835 // this information must travel along with the operation for eventual
2836 // consumption by emitEpilogue.
2837 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2840 // Add argument registers to the end of the list so that they are known live
2842 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2843 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2844 RegsToPass[i].second.getValueType()));
2846 // Add a register mask operand representing the call-preserved registers.
2847 const uint32_t *Mask;
2848 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2850 // For 'this' returns, use the X0-preserving mask if applicable
2851 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2853 IsThisReturn = false;
2854 Mask = TRI->getCallPreservedMask(MF, CallConv);
2857 Mask = TRI->getCallPreservedMask(MF, CallConv);
2859 assert(Mask && "Missing call preserved mask for calling convention");
2860 Ops.push_back(DAG.getRegisterMask(Mask));
2862 if (InFlag.getNode())
2863 Ops.push_back(InFlag);
2865 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2867 // If we're doing a tall call, use a TC_RETURN here rather than an
2868 // actual call instruction.
2870 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2872 // Returns a chain and a flag for retval copy to use.
2873 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2874 InFlag = Chain.getValue(1);
2876 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2877 ? RoundUpToAlignment(NumBytes, 16)
2880 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2881 DAG.getIntPtrConstant(CalleePopBytes, true),
2884 InFlag = Chain.getValue(1);
2886 // Handle result values, copying them out of physregs into vregs that we
2888 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2889 InVals, IsThisReturn,
2890 IsThisReturn ? OutVals[0] : SDValue());
2893 bool AArch64TargetLowering::CanLowerReturn(
2894 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2895 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2896 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2897 ? RetCC_AArch64_WebKit_JS
2898 : RetCC_AArch64_AAPCS;
2899 SmallVector<CCValAssign, 16> RVLocs;
2900 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2901 return CCInfo.CheckReturn(Outs, RetCC);
2905 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2907 const SmallVectorImpl<ISD::OutputArg> &Outs,
2908 const SmallVectorImpl<SDValue> &OutVals,
2909 SDLoc DL, SelectionDAG &DAG) const {
2910 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2911 ? RetCC_AArch64_WebKit_JS
2912 : RetCC_AArch64_AAPCS;
2913 SmallVector<CCValAssign, 16> RVLocs;
2914 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2916 CCInfo.AnalyzeReturn(Outs, RetCC);
2918 // Copy the result values into the output registers.
2920 SmallVector<SDValue, 4> RetOps(1, Chain);
2921 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2922 ++i, ++realRVLocIdx) {
2923 CCValAssign &VA = RVLocs[i];
2924 assert(VA.isRegLoc() && "Can only return in registers!");
2925 SDValue Arg = OutVals[realRVLocIdx];
2927 switch (VA.getLocInfo()) {
2929 llvm_unreachable("Unknown loc info!");
2930 case CCValAssign::Full:
2931 if (Outs[i].ArgVT == MVT::i1) {
2932 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2933 // value. This is strictly redundant on Darwin (which uses "zeroext
2934 // i1"), but will be optimised out before ISel.
2935 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2936 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2939 case CCValAssign::BCvt:
2940 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2944 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2945 Flag = Chain.getValue(1);
2946 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2949 RetOps[0] = Chain; // Update chain.
2951 // Add the flag if we have it.
2953 RetOps.push_back(Flag);
2955 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2958 //===----------------------------------------------------------------------===//
2959 // Other Lowering Code
2960 //===----------------------------------------------------------------------===//
2962 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2963 SelectionDAG &DAG) const {
2964 EVT PtrVT = getPointerTy();
2966 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2967 const GlobalValue *GV = GN->getGlobal();
2968 unsigned char OpFlags =
2969 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2971 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2972 "unexpected offset in global node");
2974 // This also catched the large code model case for Darwin.
2975 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2976 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2977 // FIXME: Once remat is capable of dealing with instructions with register
2978 // operands, expand this into two nodes instead of using a wrapper node.
2979 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2982 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2983 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2984 "use of MO_CONSTPOOL only supported on small model");
2985 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2986 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2987 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2988 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2989 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2990 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2991 MachinePointerInfo::getConstantPool(),
2992 /*isVolatile=*/ false,
2993 /*isNonTemporal=*/ true,
2994 /*isInvariant=*/ true, 8);
2995 if (GN->getOffset() != 0)
2996 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2997 DAG.getConstant(GN->getOffset(), PtrVT));
3001 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3002 const unsigned char MO_NC = AArch64II::MO_NC;
3004 AArch64ISD::WrapperLarge, DL, PtrVT,
3005 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3006 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3007 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3008 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3010 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3011 // the only correct model on Darwin.
3012 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3013 OpFlags | AArch64II::MO_PAGE);
3014 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3015 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3017 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3018 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3022 /// \brief Convert a TLS address reference into the correct sequence of loads
3023 /// and calls to compute the variable's address (for Darwin, currently) and
3024 /// return an SDValue containing the final node.
3026 /// Darwin only has one TLS scheme which must be capable of dealing with the
3027 /// fully general situation, in the worst case. This means:
3028 /// + "extern __thread" declaration.
3029 /// + Defined in a possibly unknown dynamic library.
3031 /// The general system is that each __thread variable has a [3 x i64] descriptor
3032 /// which contains information used by the runtime to calculate the address. The
3033 /// only part of this the compiler needs to know about is the first xword, which
3034 /// contains a function pointer that must be called with the address of the
3035 /// entire descriptor in "x0".
3037 /// Since this descriptor may be in a different unit, in general even the
3038 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3040 /// adrp x0, _var@TLVPPAGE
3041 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3042 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3043 /// ; the function pointer
3044 /// blr x1 ; Uses descriptor address in x0
3045 /// ; Address of _var is now in x0.
3047 /// If the address of _var's descriptor *is* known to the linker, then it can
3048 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3049 /// a slight efficiency gain.
3051 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3052 SelectionDAG &DAG) const {
3053 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3056 MVT PtrVT = getPointerTy();
3057 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3060 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3061 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3063 // The first entry in the descriptor is a function pointer that we must call
3064 // to obtain the address of the variable.
3065 SDValue Chain = DAG.getEntryNode();
3066 SDValue FuncTLVGet =
3067 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3068 false, true, true, 8);
3069 Chain = FuncTLVGet.getValue(1);
3071 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3072 MFI->setAdjustsStack(true);
3074 // TLS calls preserve all registers except those that absolutely must be
3075 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3077 const uint32_t *Mask =
3078 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3080 // Finally, we can make the call. This is just a degenerate version of a
3081 // normal AArch64 call node: x0 takes the address of the descriptor, and
3082 // returns the address of the variable in this thread.
3083 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3085 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3086 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3087 DAG.getRegisterMask(Mask), Chain.getValue(1));
3088 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3091 /// When accessing thread-local variables under either the general-dynamic or
3092 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3093 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3094 /// is a function pointer to carry out the resolution.
3096 /// The sequence is:
3097 /// adrp x0, :tlsdesc:var
3098 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3099 /// add x0, x0, #:tlsdesc_lo12:var
3100 /// .tlsdesccall var
3102 /// (TPIDR_EL0 offset now in x0)
3104 /// The above sequence must be produced unscheduled, to enable the linker to
3105 /// optimize/relax this sequence.
3106 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3107 /// above sequence, and expanded really late in the compilation flow, to ensure
3108 /// the sequence is produced as per above.
3109 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3110 SelectionDAG &DAG) const {
3111 EVT PtrVT = getPointerTy();
3113 SDValue Chain = DAG.getEntryNode();
3114 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3116 SmallVector<SDValue, 2> Ops;
3117 Ops.push_back(Chain);
3118 Ops.push_back(SymAddr);
3120 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3121 SDValue Glue = Chain.getValue(1);
3123 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3127 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3128 SelectionDAG &DAG) const {
3129 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3130 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3131 "ELF TLS only supported in small memory model");
3132 // Different choices can be made for the maximum size of the TLS area for a
3133 // module. For the small address model, the default TLS size is 16MiB and the
3134 // maximum TLS size is 4GiB.
3135 // FIXME: add -mtls-size command line option and make it control the 16MiB
3136 // vs. 4GiB code sequence generation.
3137 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3139 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3140 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3141 if (Model == TLSModel::LocalDynamic)
3142 Model = TLSModel::GeneralDynamic;
3146 EVT PtrVT = getPointerTy();
3148 const GlobalValue *GV = GA->getGlobal();
3150 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3152 if (Model == TLSModel::LocalExec) {
3153 SDValue HiVar = DAG.getTargetGlobalAddress(
3154 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3155 SDValue LoVar = DAG.getTargetGlobalAddress(
3157 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3159 SDValue TPWithOff_lo =
3160 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3161 HiVar, DAG.getTargetConstant(0, MVT::i32)),
3164 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3165 LoVar, DAG.getTargetConstant(0, MVT::i32)),
3168 } else if (Model == TLSModel::InitialExec) {
3169 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3170 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3171 } else if (Model == TLSModel::LocalDynamic) {
3172 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3173 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3174 // the beginning of the module's TLS region, followed by a DTPREL offset
3177 // These accesses will need deduplicating if there's more than one.
3178 AArch64FunctionInfo *MFI =
3179 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3180 MFI->incNumLocalDynamicTLSAccesses();
3182 // The call needs a relocation too for linker relaxation. It doesn't make
3183 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3185 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3188 // Now we can calculate the offset from TPIDR_EL0 to this module's
3189 // thread-local area.
3190 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3192 // Now use :dtprel_whatever: operations to calculate this variable's offset
3193 // in its thread-storage area.
3194 SDValue HiVar = DAG.getTargetGlobalAddress(
3195 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3196 SDValue LoVar = DAG.getTargetGlobalAddress(
3197 GV, DL, MVT::i64, 0,
3198 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3200 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3201 DAG.getTargetConstant(0, MVT::i32)),
3203 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3204 DAG.getTargetConstant(0, MVT::i32)),
3206 } else if (Model == TLSModel::GeneralDynamic) {
3207 // The call needs a relocation too for linker relaxation. It doesn't make
3208 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3211 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3213 // Finally we can make a call to calculate the offset from tpidr_el0.
3214 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3216 llvm_unreachable("Unsupported ELF TLS access model");
3218 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3221 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3222 SelectionDAG &DAG) const {
3223 if (Subtarget->isTargetDarwin())
3224 return LowerDarwinGlobalTLSAddress(Op, DAG);
3225 else if (Subtarget->isTargetELF())
3226 return LowerELFGlobalTLSAddress(Op, DAG);
3228 llvm_unreachable("Unexpected platform trying to use TLS");
3230 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3231 SDValue Chain = Op.getOperand(0);
3232 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3233 SDValue LHS = Op.getOperand(2);
3234 SDValue RHS = Op.getOperand(3);
3235 SDValue Dest = Op.getOperand(4);
3238 // Handle f128 first, since lowering it will result in comparing the return
3239 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3240 // is expecting to deal with.
3241 if (LHS.getValueType() == MVT::f128) {
3242 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3244 // If softenSetCCOperands returned a scalar, we need to compare the result
3245 // against zero to select between true and false values.
3246 if (!RHS.getNode()) {
3247 RHS = DAG.getConstant(0, LHS.getValueType());
3252 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3254 unsigned Opc = LHS.getOpcode();
3255 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3256 cast<ConstantSDNode>(RHS)->isOne() &&
3257 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3258 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3259 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3260 "Unexpected condition code.");
3261 // Only lower legal XALUO ops.
3262 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3265 // The actual operation with overflow check.
3266 AArch64CC::CondCode OFCC;
3267 SDValue Value, Overflow;
3268 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3270 if (CC == ISD::SETNE)
3271 OFCC = getInvertedCondCode(OFCC);
3272 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3274 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3278 if (LHS.getValueType().isInteger()) {
3279 assert((LHS.getValueType() == RHS.getValueType()) &&
3280 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3282 // If the RHS of the comparison is zero, we can potentially fold this
3283 // to a specialized branch.
3284 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3285 if (RHSC && RHSC->getZExtValue() == 0) {
3286 if (CC == ISD::SETEQ) {
3287 // See if we can use a TBZ to fold in an AND as well.
3288 // TBZ has a smaller branch displacement than CBZ. If the offset is
3289 // out of bounds, a late MI-layer pass rewrites branches.
3290 // 403.gcc is an example that hits this case.
3291 if (LHS.getOpcode() == ISD::AND &&
3292 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3293 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3294 SDValue Test = LHS.getOperand(0);
3295 uint64_t Mask = LHS.getConstantOperandVal(1);
3296 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3297 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3300 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3301 } else if (CC == ISD::SETNE) {
3302 // See if we can use a TBZ to fold in an AND as well.
3303 // TBZ has a smaller branch displacement than CBZ. If the offset is
3304 // out of bounds, a late MI-layer pass rewrites branches.
3305 // 403.gcc is an example that hits this case.
3306 if (LHS.getOpcode() == ISD::AND &&
3307 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3308 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3309 SDValue Test = LHS.getOperand(0);
3310 uint64_t Mask = LHS.getConstantOperandVal(1);
3311 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3312 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3315 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3316 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3317 // Don't combine AND since emitComparison converts the AND to an ANDS
3318 // (a.k.a. TST) and the test in the test bit and branch instruction
3319 // becomes redundant. This would also increase register pressure.
3320 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3321 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3322 DAG.getConstant(Mask, MVT::i64), Dest);
3325 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3326 LHS.getOpcode() != ISD::AND) {
3327 // Don't combine AND since emitComparison converts the AND to an ANDS
3328 // (a.k.a. TST) and the test in the test bit and branch instruction
3329 // becomes redundant. This would also increase register pressure.
3330 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3331 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3332 DAG.getConstant(Mask, MVT::i64), Dest);
3336 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3337 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3341 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3343 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3344 // clean. Some of them require two branches to implement.
3345 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3346 AArch64CC::CondCode CC1, CC2;
3347 changeFPCCToAArch64CC(CC, CC1, CC2);
3348 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3350 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3351 if (CC2 != AArch64CC::AL) {
3352 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3353 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3360 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3361 SelectionDAG &DAG) const {
3362 EVT VT = Op.getValueType();
3365 SDValue In1 = Op.getOperand(0);
3366 SDValue In2 = Op.getOperand(1);
3367 EVT SrcVT = In2.getValueType();
3369 if (SrcVT == MVT::f32 && VT == MVT::f64)
3370 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3371 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3372 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3374 // FIXME: Src type is different, bail out for now. Can VT really be a
3382 SDValue VecVal1, VecVal2;
3383 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3386 EltMask = 0x80000000ULL;
3388 if (!VT.isVector()) {
3389 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3390 DAG.getUNDEF(VecVT), In1);
3391 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3392 DAG.getUNDEF(VecVT), In2);
3394 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3395 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3397 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3401 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3402 // immediate moves cannot materialize that in a single instruction for
3403 // 64-bit elements. Instead, materialize zero and then negate it.
3406 if (!VT.isVector()) {
3407 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3408 DAG.getUNDEF(VecVT), In1);
3409 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3410 DAG.getUNDEF(VecVT), In2);
3412 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3413 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3416 llvm_unreachable("Invalid type for copysign!");
3419 SDValue BuildVec = DAG.getConstant(EltMask, VecVT);
3421 // If we couldn't materialize the mask above, then the mask vector will be
3422 // the zero vector, and we need to negate it here.
3423 if (VT == MVT::f64 || VT == MVT::v2f64) {
3424 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3425 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3426 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3430 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3433 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3434 else if (VT == MVT::f64)
3435 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3437 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3440 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3441 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3442 Attribute::NoImplicitFloat))
3445 if (!Subtarget->hasNEON())
3448 // While there is no integer popcount instruction, it can
3449 // be more efficiently lowered to the following sequence that uses
3450 // AdvSIMD registers/instructions as long as the copies to/from
3451 // the AdvSIMD registers are cheap.
3452 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3453 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3454 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3455 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3456 SDValue Val = Op.getOperand(0);
3458 EVT VT = Op.getValueType();
3461 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3462 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3464 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3465 SDValue UaddLV = DAG.getNode(
3466 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3467 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3470 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3474 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3476 if (Op.getValueType().isVector())
3477 return LowerVSETCC(Op, DAG);
3479 SDValue LHS = Op.getOperand(0);
3480 SDValue RHS = Op.getOperand(1);
3481 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3484 // We chose ZeroOrOneBooleanContents, so use zero and one.
3485 EVT VT = Op.getValueType();
3486 SDValue TVal = DAG.getConstant(1, VT);
3487 SDValue FVal = DAG.getConstant(0, VT);
3489 // Handle f128 first, since one possible outcome is a normal integer
3490 // comparison which gets picked up by the next if statement.
3491 if (LHS.getValueType() == MVT::f128) {
3492 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3494 // If softenSetCCOperands returned a scalar, use it.
3495 if (!RHS.getNode()) {
3496 assert(LHS.getValueType() == Op.getValueType() &&
3497 "Unexpected setcc expansion!");
3502 if (LHS.getValueType().isInteger()) {
3505 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3507 // Note that we inverted the condition above, so we reverse the order of
3508 // the true and false operands here. This will allow the setcc to be
3509 // matched to a single CSINC instruction.
3510 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3513 // Now we know we're dealing with FP values.
3514 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3516 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3517 // and do the comparison.
3518 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3520 AArch64CC::CondCode CC1, CC2;
3521 changeFPCCToAArch64CC(CC, CC1, CC2);
3522 if (CC2 == AArch64CC::AL) {
3523 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3524 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3526 // Note that we inverted the condition above, so we reverse the order of
3527 // the true and false operands here. This will allow the setcc to be
3528 // matched to a single CSINC instruction.
3529 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3531 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3532 // totally clean. Some of them require two CSELs to implement. As is in
3533 // this case, we emit the first CSEL and then emit a second using the output
3534 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3536 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3537 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3539 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3541 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3542 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3546 /// A SELECT_CC operation is really some kind of max or min if both values being
3547 /// compared are, in some sense, equal to the results in either case. However,
3548 /// it is permissible to compare f32 values and produce directly extended f64
3551 /// Extending the comparison operands would also be allowed, but is less likely
3552 /// to happen in practice since their use is right here. Note that truncate
3553 /// operations would *not* be semantically equivalent.
3554 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3558 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3559 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3560 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3561 Result.getValueType() == MVT::f64) {
3563 APFloat CmpVal = CCmp->getValueAPF();
3564 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3565 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3568 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3571 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3572 SDValue RHS, SDValue TVal,
3573 SDValue FVal, SDLoc dl,
3574 SelectionDAG &DAG) const {
3575 // Handle f128 first, because it will result in a comparison of some RTLIB
3576 // call result against zero.
3577 if (LHS.getValueType() == MVT::f128) {
3578 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3580 // If softenSetCCOperands returned a scalar, we need to compare the result
3581 // against zero to select between true and false values.
3582 if (!RHS.getNode()) {
3583 RHS = DAG.getConstant(0, LHS.getValueType());
3588 // Handle integers first.
3589 if (LHS.getValueType().isInteger()) {
3590 assert((LHS.getValueType() == RHS.getValueType()) &&
3591 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3593 unsigned Opcode = AArch64ISD::CSEL;
3595 // If both the TVal and the FVal are constants, see if we can swap them in
3596 // order to for a CSINV or CSINC out of them.
3597 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3598 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3600 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3601 std::swap(TVal, FVal);
3602 std::swap(CTVal, CFVal);
3603 CC = ISD::getSetCCInverse(CC, true);
3604 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3605 std::swap(TVal, FVal);
3606 std::swap(CTVal, CFVal);
3607 CC = ISD::getSetCCInverse(CC, true);
3608 } else if (TVal.getOpcode() == ISD::XOR) {
3609 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3610 // with a CSINV rather than a CSEL.
3611 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3613 if (CVal && CVal->isAllOnesValue()) {
3614 std::swap(TVal, FVal);
3615 std::swap(CTVal, CFVal);
3616 CC = ISD::getSetCCInverse(CC, true);
3618 } else if (TVal.getOpcode() == ISD::SUB) {
3619 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3620 // that we can match with a CSNEG rather than a CSEL.
3621 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3623 if (CVal && CVal->isNullValue()) {
3624 std::swap(TVal, FVal);
3625 std::swap(CTVal, CFVal);
3626 CC = ISD::getSetCCInverse(CC, true);
3628 } else if (CTVal && CFVal) {
3629 const int64_t TrueVal = CTVal->getSExtValue();
3630 const int64_t FalseVal = CFVal->getSExtValue();
3633 // If both TVal and FVal are constants, see if FVal is the
3634 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3635 // instead of a CSEL in that case.
3636 if (TrueVal == ~FalseVal) {
3637 Opcode = AArch64ISD::CSINV;
3638 } else if (TrueVal == -FalseVal) {
3639 Opcode = AArch64ISD::CSNEG;
3640 } else if (TVal.getValueType() == MVT::i32) {
3641 // If our operands are only 32-bit wide, make sure we use 32-bit
3642 // arithmetic for the check whether we can use CSINC. This ensures that
3643 // the addition in the check will wrap around properly in case there is
3644 // an overflow (which would not be the case if we do the check with
3645 // 64-bit arithmetic).
3646 const uint32_t TrueVal32 = CTVal->getZExtValue();
3647 const uint32_t FalseVal32 = CFVal->getZExtValue();
3649 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3650 Opcode = AArch64ISD::CSINC;
3652 if (TrueVal32 > FalseVal32) {
3656 // 64-bit check whether we can use CSINC.
3657 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3658 Opcode = AArch64ISD::CSINC;
3660 if (TrueVal > FalseVal) {
3665 // Swap TVal and FVal if necessary.
3667 std::swap(TVal, FVal);
3668 std::swap(CTVal, CFVal);
3669 CC = ISD::getSetCCInverse(CC, true);
3672 if (Opcode != AArch64ISD::CSEL) {
3673 // Drop FVal since we can get its value by simply inverting/negating
3680 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3682 EVT VT = TVal.getValueType();
3683 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3686 // Now we know we're dealing with FP values.
3687 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3688 assert(LHS.getValueType() == RHS.getValueType());
3689 EVT VT = TVal.getValueType();
3691 // Try to match this select into a max/min operation, which have dedicated
3692 // opcode in the instruction set.
3693 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3695 if (getTargetMachine().Options.NoNaNsFPMath) {
3696 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3697 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3698 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3699 CC = ISD::getSetCCSwappedOperands(CC);
3700 std::swap(MinMaxLHS, MinMaxRHS);
3703 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3704 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3714 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3722 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3728 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3729 // and do the comparison.
3730 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3732 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3733 // clean. Some of them require two CSELs to implement.
3734 AArch64CC::CondCode CC1, CC2;
3735 changeFPCCToAArch64CC(CC, CC1, CC2);
3736 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3737 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3739 // If we need a second CSEL, emit it, using the output of the first as the
3740 // RHS. We're effectively OR'ing the two CC's together.
3741 if (CC2 != AArch64CC::AL) {
3742 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3743 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3746 // Otherwise, return the output of the first CSEL.
3750 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3751 SelectionDAG &DAG) const {
3752 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3753 SDValue LHS = Op.getOperand(0);
3754 SDValue RHS = Op.getOperand(1);
3755 SDValue TVal = Op.getOperand(2);
3756 SDValue FVal = Op.getOperand(3);
3758 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3761 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3762 SelectionDAG &DAG) const {
3763 SDValue CCVal = Op->getOperand(0);
3764 SDValue TVal = Op->getOperand(1);
3765 SDValue FVal = Op->getOperand(2);
3768 unsigned Opc = CCVal.getOpcode();
3769 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3771 if (CCVal.getResNo() == 1 &&
3772 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3773 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3774 // Only lower legal XALUO ops.
3775 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3778 AArch64CC::CondCode OFCC;
3779 SDValue Value, Overflow;
3780 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3781 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3783 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3787 // Lower it the same way as we would lower a SELECT_CC node.
3790 if (CCVal.getOpcode() == ISD::SETCC) {
3791 LHS = CCVal.getOperand(0);
3792 RHS = CCVal.getOperand(1);
3793 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3796 RHS = DAG.getConstant(0, CCVal.getValueType());
3799 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3802 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3803 SelectionDAG &DAG) const {
3804 // Jump table entries as PC relative offsets. No additional tweaking
3805 // is necessary here. Just get the address of the jump table.
3806 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3807 EVT PtrVT = getPointerTy();
3810 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3811 !Subtarget->isTargetMachO()) {
3812 const unsigned char MO_NC = AArch64II::MO_NC;
3814 AArch64ISD::WrapperLarge, DL, PtrVT,
3815 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3816 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3817 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3818 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3819 AArch64II::MO_G0 | MO_NC));
3823 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3824 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3825 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3826 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3827 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3830 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3831 SelectionDAG &DAG) const {
3832 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3833 EVT PtrVT = getPointerTy();
3836 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3837 // Use the GOT for the large code model on iOS.
3838 if (Subtarget->isTargetMachO()) {
3839 SDValue GotAddr = DAG.getTargetConstantPool(
3840 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3842 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3845 const unsigned char MO_NC = AArch64II::MO_NC;
3847 AArch64ISD::WrapperLarge, DL, PtrVT,
3848 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3849 CP->getOffset(), AArch64II::MO_G3),
3850 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3851 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3852 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3853 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3854 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3855 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3857 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3858 // ELF, the only valid one on Darwin.
3860 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3861 CP->getOffset(), AArch64II::MO_PAGE);
3862 SDValue Lo = DAG.getTargetConstantPool(
3863 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3864 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3866 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3867 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3871 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3872 SelectionDAG &DAG) const {
3873 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3874 EVT PtrVT = getPointerTy();
3876 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3877 !Subtarget->isTargetMachO()) {
3878 const unsigned char MO_NC = AArch64II::MO_NC;
3880 AArch64ISD::WrapperLarge, DL, PtrVT,
3881 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3882 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3883 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3884 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3886 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3887 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3889 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3890 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3894 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3895 SelectionDAG &DAG) const {
3896 AArch64FunctionInfo *FuncInfo =
3897 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3901 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3902 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3903 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3904 MachinePointerInfo(SV), false, false, 0);
3907 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3908 SelectionDAG &DAG) const {
3909 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3910 // Standard, section B.3.
3911 MachineFunction &MF = DAG.getMachineFunction();
3912 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3915 SDValue Chain = Op.getOperand(0);
3916 SDValue VAList = Op.getOperand(1);
3917 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3918 SmallVector<SDValue, 4> MemOps;
3920 // void *__stack at offset 0
3922 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3923 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3924 MachinePointerInfo(SV), false, false, 8));
3926 // void *__gr_top at offset 8
3927 int GPRSize = FuncInfo->getVarArgsGPRSize();
3929 SDValue GRTop, GRTopAddr;
3931 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3932 DAG.getConstant(8, getPointerTy()));
3934 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3935 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3936 DAG.getConstant(GPRSize, getPointerTy()));
3938 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3939 MachinePointerInfo(SV, 8), false, false, 8));
3942 // void *__vr_top at offset 16
3943 int FPRSize = FuncInfo->getVarArgsFPRSize();
3945 SDValue VRTop, VRTopAddr;
3946 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3947 DAG.getConstant(16, getPointerTy()));
3949 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3950 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3951 DAG.getConstant(FPRSize, getPointerTy()));
3953 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3954 MachinePointerInfo(SV, 16), false, false, 8));
3957 // int __gr_offs at offset 24
3958 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3959 DAG.getConstant(24, getPointerTy()));
3960 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3961 GROffsAddr, MachinePointerInfo(SV, 24), false,
3964 // int __vr_offs at offset 28
3965 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3966 DAG.getConstant(28, getPointerTy()));
3967 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3968 VROffsAddr, MachinePointerInfo(SV, 28), false,
3971 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3974 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3975 SelectionDAG &DAG) const {
3976 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3977 : LowerAAPCS_VASTART(Op, DAG);
3980 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3981 SelectionDAG &DAG) const {
3982 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3984 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3985 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3986 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3988 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3989 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3990 8, false, false, false, MachinePointerInfo(DestSV),
3991 MachinePointerInfo(SrcSV));
3994 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3995 assert(Subtarget->isTargetDarwin() &&
3996 "automatic va_arg instruction only works on Darwin");
3998 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3999 EVT VT = Op.getValueType();
4001 SDValue Chain = Op.getOperand(0);
4002 SDValue Addr = Op.getOperand(1);
4003 unsigned Align = Op.getConstantOperandVal(3);
4005 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
4006 MachinePointerInfo(V), false, false, false, 0);
4007 Chain = VAList.getValue(1);
4010 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4011 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4012 DAG.getConstant(Align - 1, getPointerTy()));
4013 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
4014 DAG.getConstant(-(int64_t)Align, getPointerTy()));
4017 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4018 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4020 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4021 // up to 64 bits. At the very least, we have to increase the striding of the
4022 // vaargs list to match this, and for FP values we need to introduce
4023 // FP_ROUND nodes as well.
4024 if (VT.isInteger() && !VT.isVector())
4026 bool NeedFPTrunc = false;
4027 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4032 // Increment the pointer, VAList, to the next vaarg
4033 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4034 DAG.getConstant(ArgSize, getPointerTy()));
4035 // Store the incremented VAList to the legalized pointer
4036 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4039 // Load the actual argument out of the pointer VAList
4041 // Load the value as an f64.
4042 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4043 MachinePointerInfo(), false, false, false, 0);
4044 // Round the value down to an f32.
4045 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4046 DAG.getIntPtrConstant(1));
4047 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4048 // Merge the rounded value with the chain output of the load.
4049 return DAG.getMergeValues(Ops, DL);
4052 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4056 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4057 SelectionDAG &DAG) const {
4058 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4059 MFI->setFrameAddressIsTaken(true);
4061 EVT VT = Op.getValueType();
4063 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4065 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4067 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4068 MachinePointerInfo(), false, false, false, 0);
4072 // FIXME? Maybe this could be a TableGen attribute on some registers and
4073 // this table could be generated automatically from RegInfo.
4074 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4076 unsigned Reg = StringSwitch<unsigned>(RegName)
4077 .Case("sp", AArch64::SP)
4081 report_fatal_error("Invalid register name global variable");
4084 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4085 SelectionDAG &DAG) const {
4086 MachineFunction &MF = DAG.getMachineFunction();
4087 MachineFrameInfo *MFI = MF.getFrameInfo();
4088 MFI->setReturnAddressIsTaken(true);
4090 EVT VT = Op.getValueType();
4092 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4094 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4095 SDValue Offset = DAG.getConstant(8, getPointerTy());
4096 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4097 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4098 MachinePointerInfo(), false, false, false, 0);
4101 // Return LR, which contains the return address. Mark it an implicit live-in.
4102 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4103 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4106 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4107 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4108 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4109 SelectionDAG &DAG) const {
4110 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4111 EVT VT = Op.getValueType();
4112 unsigned VTBits = VT.getSizeInBits();
4114 SDValue ShOpLo = Op.getOperand(0);
4115 SDValue ShOpHi = Op.getOperand(1);
4116 SDValue ShAmt = Op.getOperand(2);
4118 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4120 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4122 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4123 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4124 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4125 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4126 DAG.getConstant(VTBits, MVT::i64));
4127 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4129 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4130 ISD::SETGE, dl, DAG);
4131 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4133 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4134 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4136 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4138 // AArch64 shifts larger than the register width are wrapped rather than
4139 // clamped, so we can't just emit "hi >> x".
4140 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4141 SDValue TrueValHi = Opc == ISD::SRA
4142 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4143 DAG.getConstant(VTBits - 1, MVT::i64))
4144 : DAG.getConstant(0, VT);
4146 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4148 SDValue Ops[2] = { Lo, Hi };
4149 return DAG.getMergeValues(Ops, dl);
4152 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4153 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4154 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4155 SelectionDAG &DAG) const {
4156 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4157 EVT VT = Op.getValueType();
4158 unsigned VTBits = VT.getSizeInBits();
4160 SDValue ShOpLo = Op.getOperand(0);
4161 SDValue ShOpHi = Op.getOperand(1);
4162 SDValue ShAmt = Op.getOperand(2);
4165 assert(Op.getOpcode() == ISD::SHL_PARTS);
4166 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4167 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4168 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4169 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4170 DAG.getConstant(VTBits, MVT::i64));
4171 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4172 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4174 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4176 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4177 ISD::SETGE, dl, DAG);
4178 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4180 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4182 // AArch64 shifts of larger than register sizes are wrapped rather than
4183 // clamped, so we can't just emit "lo << a" if a is too big.
4184 SDValue TrueValLo = DAG.getConstant(0, VT);
4185 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4187 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4189 SDValue Ops[2] = { Lo, Hi };
4190 return DAG.getMergeValues(Ops, dl);
4193 bool AArch64TargetLowering::isOffsetFoldingLegal(
4194 const GlobalAddressSDNode *GA) const {
4195 // The AArch64 target doesn't support folding offsets into global addresses.
4199 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4200 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4201 // FIXME: We should be able to handle f128 as well with a clever lowering.
4202 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4206 return AArch64_AM::getFP64Imm(Imm) != -1;
4207 else if (VT == MVT::f32)
4208 return AArch64_AM::getFP32Imm(Imm) != -1;
4212 //===----------------------------------------------------------------------===//
4213 // AArch64 Optimization Hooks
4214 //===----------------------------------------------------------------------===//
4216 //===----------------------------------------------------------------------===//
4217 // AArch64 Inline Assembly Support
4218 //===----------------------------------------------------------------------===//
4220 // Table of Constraints
4221 // TODO: This is the current set of constraints supported by ARM for the
4222 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4224 // r - A general register
4225 // w - An FP/SIMD register of some size in the range v0-v31
4226 // x - An FP/SIMD register of some size in the range v0-v15
4227 // I - Constant that can be used with an ADD instruction
4228 // J - Constant that can be used with a SUB instruction
4229 // K - Constant that can be used with a 32-bit logical instruction
4230 // L - Constant that can be used with a 64-bit logical instruction
4231 // M - Constant that can be used as a 32-bit MOV immediate
4232 // N - Constant that can be used as a 64-bit MOV immediate
4233 // Q - A memory reference with base register and no offset
4234 // S - A symbolic address
4235 // Y - Floating point constant zero
4236 // Z - Integer constant zero
4238 // Note that general register operands will be output using their 64-bit x
4239 // register name, whatever the size of the variable, unless the asm operand
4240 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4241 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4244 /// getConstraintType - Given a constraint letter, return the type of
4245 /// constraint it is for this target.
4246 AArch64TargetLowering::ConstraintType
4247 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4248 if (Constraint.size() == 1) {
4249 switch (Constraint[0]) {
4256 return C_RegisterClass;
4257 // An address with a single base register. Due to the way we
4258 // currently handle addresses it is the same as 'r'.
4263 return TargetLowering::getConstraintType(Constraint);
4266 /// Examine constraint type and operand type and determine a weight value.
4267 /// This object must already have been set up with the operand type
4268 /// and the current alternative constraint selected.
4269 TargetLowering::ConstraintWeight
4270 AArch64TargetLowering::getSingleConstraintMatchWeight(
4271 AsmOperandInfo &info, const char *constraint) const {
4272 ConstraintWeight weight = CW_Invalid;
4273 Value *CallOperandVal = info.CallOperandVal;
4274 // If we don't have a value, we can't do a match,
4275 // but allow it at the lowest weight.
4276 if (!CallOperandVal)
4278 Type *type = CallOperandVal->getType();
4279 // Look at the constraint type.
4280 switch (*constraint) {
4282 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4286 if (type->isFloatingPointTy() || type->isVectorTy())
4287 weight = CW_Register;
4290 weight = CW_Constant;
4296 std::pair<unsigned, const TargetRegisterClass *>
4297 AArch64TargetLowering::getRegForInlineAsmConstraint(
4298 const TargetRegisterInfo *TRI, const std::string &Constraint,
4300 if (Constraint.size() == 1) {
4301 switch (Constraint[0]) {
4303 if (VT.getSizeInBits() == 64)
4304 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4305 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4308 return std::make_pair(0U, &AArch64::FPR32RegClass);
4309 if (VT.getSizeInBits() == 64)
4310 return std::make_pair(0U, &AArch64::FPR64RegClass);
4311 if (VT.getSizeInBits() == 128)
4312 return std::make_pair(0U, &AArch64::FPR128RegClass);
4314 // The instructions that this constraint is designed for can
4315 // only take 128-bit registers so just use that regclass.
4317 if (VT.getSizeInBits() == 128)
4318 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4322 if (StringRef("{cc}").equals_lower(Constraint))
4323 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4325 // Use the default implementation in TargetLowering to convert the register
4326 // constraint into a member of a register class.
4327 std::pair<unsigned, const TargetRegisterClass *> Res;
4328 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4330 // Not found as a standard register?
4332 unsigned Size = Constraint.size();
4333 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4334 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4335 const std::string Reg =
4336 std::string(&Constraint[2], &Constraint[Size - 1]);
4337 int RegNo = atoi(Reg.c_str());
4338 if (RegNo >= 0 && RegNo <= 31) {
4339 // v0 - v31 are aliases of q0 - q31.
4340 // By default we'll emit v0-v31 for this unless there's a modifier where
4341 // we'll emit the correct register as well.
4342 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4343 Res.second = &AArch64::FPR128RegClass;
4351 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4352 /// vector. If it is invalid, don't add anything to Ops.
4353 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4354 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4355 SelectionDAG &DAG) const {
4358 // Currently only support length 1 constraints.
4359 if (Constraint.length() != 1)
4362 char ConstraintLetter = Constraint[0];
4363 switch (ConstraintLetter) {
4367 // This set of constraints deal with valid constants for various instructions.
4368 // Validate and return a target constant for them if we can.
4370 // 'z' maps to xzr or wzr so it needs an input of 0.
4371 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4372 if (!C || C->getZExtValue() != 0)
4375 if (Op.getValueType() == MVT::i64)
4376 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4378 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4388 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4392 // Grab the value and do some validation.
4393 uint64_t CVal = C->getZExtValue();
4394 switch (ConstraintLetter) {
4395 // The I constraint applies only to simple ADD or SUB immediate operands:
4396 // i.e. 0 to 4095 with optional shift by 12
4397 // The J constraint applies only to ADD or SUB immediates that would be
4398 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4399 // instruction [or vice versa], in other words -1 to -4095 with optional
4400 // left shift by 12.
4402 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4406 uint64_t NVal = -C->getSExtValue();
4407 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4408 CVal = C->getSExtValue();
4413 // The K and L constraints apply *only* to logical immediates, including
4414 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4415 // been removed and MOV should be used). So these constraints have to
4416 // distinguish between bit patterns that are valid 32-bit or 64-bit
4417 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4418 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4421 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4425 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4428 // The M and N constraints are a superset of K and L respectively, for use
4429 // with the MOV (immediate) alias. As well as the logical immediates they
4430 // also match 32 or 64-bit immediates that can be loaded either using a
4431 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4432 // (M) or 64-bit 0x1234000000000000 (N) etc.
4433 // As a note some of this code is liberally stolen from the asm parser.
4435 if (!isUInt<32>(CVal))
4437 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4439 if ((CVal & 0xFFFF) == CVal)
4441 if ((CVal & 0xFFFF0000ULL) == CVal)
4443 uint64_t NCVal = ~(uint32_t)CVal;
4444 if ((NCVal & 0xFFFFULL) == NCVal)
4446 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4451 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4453 if ((CVal & 0xFFFFULL) == CVal)
4455 if ((CVal & 0xFFFF0000ULL) == CVal)
4457 if ((CVal & 0xFFFF00000000ULL) == CVal)
4459 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4461 uint64_t NCVal = ~CVal;
4462 if ((NCVal & 0xFFFFULL) == NCVal)
4464 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4466 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4468 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4476 // All assembler immediates are 64-bit integers.
4477 Result = DAG.getTargetConstant(CVal, MVT::i64);
4481 if (Result.getNode()) {
4482 Ops.push_back(Result);
4486 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4489 //===----------------------------------------------------------------------===//
4490 // AArch64 Advanced SIMD Support
4491 //===----------------------------------------------------------------------===//
4493 /// WidenVector - Given a value in the V64 register class, produce the
4494 /// equivalent value in the V128 register class.
4495 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4496 EVT VT = V64Reg.getValueType();
4497 unsigned NarrowSize = VT.getVectorNumElements();
4498 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4499 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4502 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4503 V64Reg, DAG.getConstant(0, MVT::i32));
4506 /// getExtFactor - Determine the adjustment factor for the position when
4507 /// generating an "extract from vector registers" instruction.
4508 static unsigned getExtFactor(SDValue &V) {
4509 EVT EltType = V.getValueType().getVectorElementType();
4510 return EltType.getSizeInBits() / 8;
4513 /// NarrowVector - Given a value in the V128 register class, produce the
4514 /// equivalent value in the V64 register class.
4515 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4516 EVT VT = V128Reg.getValueType();
4517 unsigned WideSize = VT.getVectorNumElements();
4518 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4519 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4522 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4525 // Gather data to see if the operation can be modelled as a
4526 // shuffle in combination with VEXTs.
4527 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4528 SelectionDAG &DAG) const {
4529 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4531 EVT VT = Op.getValueType();
4532 unsigned NumElts = VT.getVectorNumElements();
4534 struct ShuffleSourceInfo {
4539 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4540 // be compatible with the shuffle we intend to construct. As a result
4541 // ShuffleVec will be some sliding window into the original Vec.
4544 // Code should guarantee that element i in Vec starts at element "WindowBase
4545 // + i * WindowScale in ShuffleVec".
4549 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4550 ShuffleSourceInfo(SDValue Vec)
4551 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4555 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4557 SmallVector<ShuffleSourceInfo, 2> Sources;
4558 for (unsigned i = 0; i < NumElts; ++i) {
4559 SDValue V = Op.getOperand(i);
4560 if (V.getOpcode() == ISD::UNDEF)
4562 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4563 // A shuffle can only come from building a vector from various
4564 // elements of other vectors.
4568 // Add this element source to the list if it's not already there.
4569 SDValue SourceVec = V.getOperand(0);
4570 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4571 if (Source == Sources.end())
4572 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4574 // Update the minimum and maximum lane number seen.
4575 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4576 Source->MinElt = std::min(Source->MinElt, EltNo);
4577 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4580 // Currently only do something sane when at most two source vectors
4582 if (Sources.size() > 2)
4585 // Find out the smallest element size among result and two sources, and use
4586 // it as element size to build the shuffle_vector.
4587 EVT SmallestEltTy = VT.getVectorElementType();
4588 for (auto &Source : Sources) {
4589 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4590 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4591 SmallestEltTy = SrcEltTy;
4594 unsigned ResMultiplier =
4595 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4596 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4597 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4599 // If the source vector is too wide or too narrow, we may nevertheless be able
4600 // to construct a compatible shuffle either by concatenating it with UNDEF or
4601 // extracting a suitable range of elements.
4602 for (auto &Src : Sources) {
4603 EVT SrcVT = Src.ShuffleVec.getValueType();
4605 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4608 // This stage of the search produces a source with the same element type as
4609 // the original, but with a total width matching the BUILD_VECTOR output.
4610 EVT EltVT = SrcVT.getVectorElementType();
4611 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4612 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4614 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4615 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4616 // We can pad out the smaller vector for free, so if it's part of a
4619 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4620 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4624 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4626 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4627 // Span too large for a VEXT to cope
4631 if (Src.MinElt >= NumSrcElts) {
4632 // The extraction can just take the second half
4634 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4635 DAG.getConstant(NumSrcElts, MVT::i64));
4636 Src.WindowBase = -NumSrcElts;
4637 } else if (Src.MaxElt < NumSrcElts) {
4638 // The extraction can just take the first half
4640 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4641 DAG.getConstant(0, MVT::i64));
4643 // An actual VEXT is needed
4645 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4646 DAG.getConstant(0, MVT::i64));
4648 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4649 DAG.getConstant(NumSrcElts, MVT::i64));
4650 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4652 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4653 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4654 Src.WindowBase = -Src.MinElt;
4658 // Another possible incompatibility occurs from the vector element types. We
4659 // can fix this by bitcasting the source vectors to the same type we intend
4661 for (auto &Src : Sources) {
4662 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4663 if (SrcEltTy == SmallestEltTy)
4665 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4666 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4667 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4668 Src.WindowBase *= Src.WindowScale;
4671 // Final sanity check before we try to actually produce a shuffle.
4673 for (auto Src : Sources)
4674 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4677 // The stars all align, our next step is to produce the mask for the shuffle.
4678 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4679 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4680 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4681 SDValue Entry = Op.getOperand(i);
4682 if (Entry.getOpcode() == ISD::UNDEF)
4685 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4686 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4688 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4689 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4691 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4692 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4693 VT.getVectorElementType().getSizeInBits());
4694 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4696 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4697 // starting at the appropriate offset.
4698 int *LaneMask = &Mask[i * ResMultiplier];
4700 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4701 ExtractBase += NumElts * (Src - Sources.begin());
4702 for (int j = 0; j < LanesDefined; ++j)
4703 LaneMask[j] = ExtractBase + j;
4706 // Final check before we try to produce nonsense...
4707 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4710 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4711 for (unsigned i = 0; i < Sources.size(); ++i)
4712 ShuffleOps[i] = Sources[i].ShuffleVec;
4714 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4715 ShuffleOps[1], &Mask[0]);
4716 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4719 // check if an EXT instruction can handle the shuffle mask when the
4720 // vector sources of the shuffle are the same.
4721 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4722 unsigned NumElts = VT.getVectorNumElements();
4724 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4730 // If this is a VEXT shuffle, the immediate value is the index of the first
4731 // element. The other shuffle indices must be the successive elements after
4733 unsigned ExpectedElt = Imm;
4734 for (unsigned i = 1; i < NumElts; ++i) {
4735 // Increment the expected index. If it wraps around, just follow it
4736 // back to index zero and keep going.
4738 if (ExpectedElt == NumElts)
4742 continue; // ignore UNDEF indices
4743 if (ExpectedElt != static_cast<unsigned>(M[i]))
4750 // check if an EXT instruction can handle the shuffle mask when the
4751 // vector sources of the shuffle are different.
4752 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4754 // Look for the first non-undef element.
4755 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4756 [](int Elt) {return Elt >= 0;});
4758 // Benefit form APInt to handle overflow when calculating expected element.
4759 unsigned NumElts = VT.getVectorNumElements();
4760 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4761 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4762 // The following shuffle indices must be the successive elements after the
4763 // first real element.
4764 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4765 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4766 if (FirstWrongElt != M.end())
4769 // The index of an EXT is the first element if it is not UNDEF.
4770 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4771 // value of the first element. E.g.
4772 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4773 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4774 // ExpectedElt is the last mask index plus 1.
4775 Imm = ExpectedElt.getZExtValue();
4777 // There are two difference cases requiring to reverse input vectors.
4778 // For example, for vector <4 x i32> we have the following cases,
4779 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4780 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4781 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4782 // to reverse two input vectors.
4791 /// isREVMask - Check if a vector shuffle corresponds to a REV
4792 /// instruction with the specified blocksize. (The order of the elements
4793 /// within each block of the vector is reversed.)
4794 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4795 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4796 "Only possible block sizes for REV are: 16, 32, 64");
4798 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4802 unsigned NumElts = VT.getVectorNumElements();
4803 unsigned BlockElts = M[0] + 1;
4804 // If the first shuffle index is UNDEF, be optimistic.
4806 BlockElts = BlockSize / EltSz;
4808 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4811 for (unsigned i = 0; i < NumElts; ++i) {
4813 continue; // ignore UNDEF indices
4814 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4821 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4822 unsigned NumElts = VT.getVectorNumElements();
4823 WhichResult = (M[0] == 0 ? 0 : 1);
4824 unsigned Idx = WhichResult * NumElts / 2;
4825 for (unsigned i = 0; i != NumElts; i += 2) {
4826 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4827 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4835 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4836 unsigned NumElts = VT.getVectorNumElements();
4837 WhichResult = (M[0] == 0 ? 0 : 1);
4838 for (unsigned i = 0; i != NumElts; ++i) {
4840 continue; // ignore UNDEF indices
4841 if ((unsigned)M[i] != 2 * i + WhichResult)
4848 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4849 unsigned NumElts = VT.getVectorNumElements();
4850 WhichResult = (M[0] == 0 ? 0 : 1);
4851 for (unsigned i = 0; i < NumElts; i += 2) {
4852 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4853 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4859 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4860 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4861 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4862 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4863 unsigned NumElts = VT.getVectorNumElements();
4864 WhichResult = (M[0] == 0 ? 0 : 1);
4865 unsigned Idx = WhichResult * NumElts / 2;
4866 for (unsigned i = 0; i != NumElts; i += 2) {
4867 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4868 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4876 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4877 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4878 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4879 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4880 unsigned Half = VT.getVectorNumElements() / 2;
4881 WhichResult = (M[0] == 0 ? 0 : 1);
4882 for (unsigned j = 0; j != 2; ++j) {
4883 unsigned Idx = WhichResult;
4884 for (unsigned i = 0; i != Half; ++i) {
4885 int MIdx = M[i + j * Half];
4886 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4895 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4896 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4897 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4898 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4899 unsigned NumElts = VT.getVectorNumElements();
4900 WhichResult = (M[0] == 0 ? 0 : 1);
4901 for (unsigned i = 0; i < NumElts; i += 2) {
4902 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4903 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4909 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4910 bool &DstIsLeft, int &Anomaly) {
4911 if (M.size() != static_cast<size_t>(NumInputElements))
4914 int NumLHSMatch = 0, NumRHSMatch = 0;
4915 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4917 for (int i = 0; i < NumInputElements; ++i) {
4927 LastLHSMismatch = i;
4929 if (M[i] == i + NumInputElements)
4932 LastRHSMismatch = i;
4935 if (NumLHSMatch == NumInputElements - 1) {
4937 Anomaly = LastLHSMismatch;
4939 } else if (NumRHSMatch == NumInputElements - 1) {
4941 Anomaly = LastRHSMismatch;
4948 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4949 if (VT.getSizeInBits() != 128)
4952 unsigned NumElts = VT.getVectorNumElements();
4954 for (int I = 0, E = NumElts / 2; I != E; I++) {
4959 int Offset = NumElts / 2;
4960 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4961 if (Mask[I] != I + SplitLHS * Offset)
4968 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4970 EVT VT = Op.getValueType();
4971 SDValue V0 = Op.getOperand(0);
4972 SDValue V1 = Op.getOperand(1);
4973 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4975 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4976 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4979 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4981 if (!isConcatMask(Mask, VT, SplitV0))
4984 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4985 VT.getVectorNumElements() / 2);
4987 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4988 DAG.getConstant(0, MVT::i64));
4990 if (V1.getValueType().getSizeInBits() == 128) {
4991 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4992 DAG.getConstant(0, MVT::i64));
4994 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4997 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4998 /// the specified operations to build the shuffle.
4999 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5000 SDValue RHS, SelectionDAG &DAG,
5002 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5003 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5004 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5007 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5016 OP_VUZPL, // VUZP, left result
5017 OP_VUZPR, // VUZP, right result
5018 OP_VZIPL, // VZIP, left result
5019 OP_VZIPR, // VZIP, right result
5020 OP_VTRNL, // VTRN, left result
5021 OP_VTRNR // VTRN, right result
5024 if (OpNum == OP_COPY) {
5025 if (LHSID == (1 * 9 + 2) * 9 + 3)
5027 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5031 SDValue OpLHS, OpRHS;
5032 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5033 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5034 EVT VT = OpLHS.getValueType();
5038 llvm_unreachable("Unknown shuffle opcode!");
5040 // VREV divides the vector in half and swaps within the half.
5041 if (VT.getVectorElementType() == MVT::i32 ||
5042 VT.getVectorElementType() == MVT::f32)
5043 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5044 // vrev <4 x i16> -> REV32
5045 if (VT.getVectorElementType() == MVT::i16 ||
5046 VT.getVectorElementType() == MVT::f16)
5047 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5048 // vrev <4 x i8> -> REV16
5049 assert(VT.getVectorElementType() == MVT::i8);
5050 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5055 EVT EltTy = VT.getVectorElementType();
5057 if (EltTy == MVT::i8)
5058 Opcode = AArch64ISD::DUPLANE8;
5059 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5060 Opcode = AArch64ISD::DUPLANE16;
5061 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5062 Opcode = AArch64ISD::DUPLANE32;
5063 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5064 Opcode = AArch64ISD::DUPLANE64;
5066 llvm_unreachable("Invalid vector element type?");
5068 if (VT.getSizeInBits() == 64)
5069 OpLHS = WidenVector(OpLHS, DAG);
5070 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5071 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5076 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5077 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5078 DAG.getConstant(Imm, MVT::i32));
5081 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5084 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5087 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5090 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5093 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5096 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5101 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5102 SelectionDAG &DAG) {
5103 // Check to see if we can use the TBL instruction.
5104 SDValue V1 = Op.getOperand(0);
5105 SDValue V2 = Op.getOperand(1);
5108 EVT EltVT = Op.getValueType().getVectorElementType();
5109 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5111 SmallVector<SDValue, 8> TBLMask;
5112 for (int Val : ShuffleMask) {
5113 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5114 unsigned Offset = Byte + Val * BytesPerElt;
5115 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5119 MVT IndexVT = MVT::v8i8;
5120 unsigned IndexLen = 8;
5121 if (Op.getValueType().getSizeInBits() == 128) {
5122 IndexVT = MVT::v16i8;
5126 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5127 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5130 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5132 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5133 Shuffle = DAG.getNode(
5134 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5135 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5136 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5137 makeArrayRef(TBLMask.data(), IndexLen)));
5139 if (IndexLen == 8) {
5140 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5141 Shuffle = DAG.getNode(
5142 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5143 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5144 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5145 makeArrayRef(TBLMask.data(), IndexLen)));
5147 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5148 // cannot currently represent the register constraints on the input
5150 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5151 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5152 // &TBLMask[0], IndexLen));
5153 Shuffle = DAG.getNode(
5154 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5155 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5156 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5157 makeArrayRef(TBLMask.data(), IndexLen)));
5160 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5163 static unsigned getDUPLANEOp(EVT EltType) {
5164 if (EltType == MVT::i8)
5165 return AArch64ISD::DUPLANE8;
5166 if (EltType == MVT::i16 || EltType == MVT::f16)
5167 return AArch64ISD::DUPLANE16;
5168 if (EltType == MVT::i32 || EltType == MVT::f32)
5169 return AArch64ISD::DUPLANE32;
5170 if (EltType == MVT::i64 || EltType == MVT::f64)
5171 return AArch64ISD::DUPLANE64;
5173 llvm_unreachable("Invalid vector element type?");
5176 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5177 SelectionDAG &DAG) const {
5179 EVT VT = Op.getValueType();
5181 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5183 // Convert shuffles that are directly supported on NEON to target-specific
5184 // DAG nodes, instead of keeping them as shuffles and matching them again
5185 // during code selection. This is more efficient and avoids the possibility
5186 // of inconsistencies between legalization and selection.
5187 ArrayRef<int> ShuffleMask = SVN->getMask();
5189 SDValue V1 = Op.getOperand(0);
5190 SDValue V2 = Op.getOperand(1);
5192 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5193 V1.getValueType().getSimpleVT())) {
5194 int Lane = SVN->getSplatIndex();
5195 // If this is undef splat, generate it via "just" vdup, if possible.
5199 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5200 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5202 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5203 // constant. If so, we can just reference the lane's definition directly.
5204 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5205 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5206 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5208 // Otherwise, duplicate from the lane of the input vector.
5209 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5211 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5212 // to make a vector of the same size as this SHUFFLE. We can ignore the
5213 // extract entirely, and canonicalise the concat using WidenVector.
5214 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5215 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5216 V1 = V1.getOperand(0);
5217 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5218 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5219 Lane -= Idx * VT.getVectorNumElements() / 2;
5220 V1 = WidenVector(V1.getOperand(Idx), DAG);
5221 } else if (VT.getSizeInBits() == 64)
5222 V1 = WidenVector(V1, DAG);
5224 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5227 if (isREVMask(ShuffleMask, VT, 64))
5228 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5229 if (isREVMask(ShuffleMask, VT, 32))
5230 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5231 if (isREVMask(ShuffleMask, VT, 16))
5232 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5234 bool ReverseEXT = false;
5236 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5239 Imm *= getExtFactor(V1);
5240 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5241 DAG.getConstant(Imm, MVT::i32));
5242 } else if (V2->getOpcode() == ISD::UNDEF &&
5243 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5244 Imm *= getExtFactor(V1);
5245 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5246 DAG.getConstant(Imm, MVT::i32));
5249 unsigned WhichResult;
5250 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5251 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5252 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5254 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5255 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5256 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5258 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5259 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5260 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5263 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5264 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5265 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5267 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5268 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5269 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5271 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5272 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5273 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5276 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5277 if (Concat.getNode())
5282 int NumInputElements = V1.getValueType().getVectorNumElements();
5283 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5284 SDValue DstVec = DstIsLeft ? V1 : V2;
5285 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5287 SDValue SrcVec = V1;
5288 int SrcLane = ShuffleMask[Anomaly];
5289 if (SrcLane >= NumInputElements) {
5291 SrcLane -= VT.getVectorNumElements();
5293 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5295 EVT ScalarVT = VT.getVectorElementType();
5297 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5298 ScalarVT = MVT::i32;
5301 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5302 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5306 // If the shuffle is not directly supported and it has 4 elements, use
5307 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5308 unsigned NumElts = VT.getVectorNumElements();
5310 unsigned PFIndexes[4];
5311 for (unsigned i = 0; i != 4; ++i) {
5312 if (ShuffleMask[i] < 0)
5315 PFIndexes[i] = ShuffleMask[i];
5318 // Compute the index in the perfect shuffle table.
5319 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5320 PFIndexes[2] * 9 + PFIndexes[3];
5321 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5322 unsigned Cost = (PFEntry >> 30);
5325 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5328 return GenerateTBL(Op, ShuffleMask, DAG);
5331 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5333 EVT VT = BVN->getValueType(0);
5334 APInt SplatBits, SplatUndef;
5335 unsigned SplatBitSize;
5337 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5338 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5340 for (unsigned i = 0; i < NumSplats; ++i) {
5341 CnstBits <<= SplatBitSize;
5342 UndefBits <<= SplatBitSize;
5343 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5344 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5353 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5354 SelectionDAG &DAG) const {
5355 BuildVectorSDNode *BVN =
5356 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5357 SDValue LHS = Op.getOperand(0);
5359 EVT VT = Op.getValueType();
5364 APInt CnstBits(VT.getSizeInBits(), 0);
5365 APInt UndefBits(VT.getSizeInBits(), 0);
5366 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5367 // We only have BIC vector immediate instruction, which is and-not.
5368 CnstBits = ~CnstBits;
5370 // We make use of a little bit of goto ickiness in order to avoid having to
5371 // duplicate the immediate matching logic for the undef toggled case.
5372 bool SecondTry = false;
5375 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5376 CnstBits = CnstBits.zextOrTrunc(64);
5377 uint64_t CnstVal = CnstBits.getZExtValue();
5379 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5380 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5381 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5382 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5383 DAG.getConstant(CnstVal, MVT::i32),
5384 DAG.getConstant(0, MVT::i32));
5385 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5388 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5389 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5391 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5392 DAG.getConstant(CnstVal, MVT::i32),
5393 DAG.getConstant(8, MVT::i32));
5394 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5397 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5400 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5401 DAG.getConstant(CnstVal, MVT::i32),
5402 DAG.getConstant(16, MVT::i32));
5403 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5406 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5409 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5410 DAG.getConstant(CnstVal, MVT::i32),
5411 DAG.getConstant(24, MVT::i32));
5412 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5415 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5416 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5417 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5418 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5419 DAG.getConstant(CnstVal, MVT::i32),
5420 DAG.getConstant(0, MVT::i32));
5421 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5424 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5425 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5426 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5427 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5428 DAG.getConstant(CnstVal, MVT::i32),
5429 DAG.getConstant(8, MVT::i32));
5430 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5437 CnstBits = ~UndefBits;
5441 // We can always fall back to a non-immediate AND.
5446 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5447 // consists of only the same constant int value, returned in reference arg
5449 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5450 uint64_t &ConstVal) {
5451 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5454 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5457 EVT VT = Bvec->getValueType(0);
5458 unsigned NumElts = VT.getVectorNumElements();
5459 for (unsigned i = 1; i < NumElts; ++i)
5460 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5462 ConstVal = FirstElt->getZExtValue();
5466 static unsigned getIntrinsicID(const SDNode *N) {
5467 unsigned Opcode = N->getOpcode();
5470 return Intrinsic::not_intrinsic;
5471 case ISD::INTRINSIC_WO_CHAIN: {
5472 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5473 if (IID < Intrinsic::num_intrinsics)
5475 return Intrinsic::not_intrinsic;
5480 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5481 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5482 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5483 // Also, logical shift right -> sri, with the same structure.
5484 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5485 EVT VT = N->getValueType(0);
5492 // Is the first op an AND?
5493 const SDValue And = N->getOperand(0);
5494 if (And.getOpcode() != ISD::AND)
5497 // Is the second op an shl or lshr?
5498 SDValue Shift = N->getOperand(1);
5499 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5500 // or AArch64ISD::VLSHR vector, #shift
5501 unsigned ShiftOpc = Shift.getOpcode();
5502 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5504 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5506 // Is the shift amount constant?
5507 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5511 // Is the and mask vector all constant?
5513 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5516 // Is C1 == ~C2, taking into account how much one can shift elements of a
5518 uint64_t C2 = C2node->getZExtValue();
5519 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5520 if (C2 > ElemSizeInBits)
5522 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5523 if ((C1 & ElemMask) != (~C2 & ElemMask))
5526 SDValue X = And.getOperand(0);
5527 SDValue Y = Shift.getOperand(0);
5530 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5532 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5533 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5535 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5536 DEBUG(N->dump(&DAG));
5537 DEBUG(dbgs() << "into: \n");
5538 DEBUG(ResultSLI->dump(&DAG));
5544 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5545 SelectionDAG &DAG) const {
5546 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5547 if (EnableAArch64SlrGeneration) {
5548 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5553 BuildVectorSDNode *BVN =
5554 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5555 SDValue LHS = Op.getOperand(1);
5557 EVT VT = Op.getValueType();
5559 // OR commutes, so try swapping the operands.
5561 LHS = Op.getOperand(0);
5562 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5567 APInt CnstBits(VT.getSizeInBits(), 0);
5568 APInt UndefBits(VT.getSizeInBits(), 0);
5569 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5570 // We make use of a little bit of goto ickiness in order to avoid having to
5571 // duplicate the immediate matching logic for the undef toggled case.
5572 bool SecondTry = false;
5575 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5576 CnstBits = CnstBits.zextOrTrunc(64);
5577 uint64_t CnstVal = CnstBits.getZExtValue();
5579 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5580 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5581 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5582 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5583 DAG.getConstant(CnstVal, MVT::i32),
5584 DAG.getConstant(0, MVT::i32));
5585 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5588 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5589 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5590 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5591 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5592 DAG.getConstant(CnstVal, MVT::i32),
5593 DAG.getConstant(8, MVT::i32));
5594 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5597 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5598 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5599 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5600 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5601 DAG.getConstant(CnstVal, MVT::i32),
5602 DAG.getConstant(16, MVT::i32));
5603 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5606 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5607 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5608 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5609 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5610 DAG.getConstant(CnstVal, MVT::i32),
5611 DAG.getConstant(24, MVT::i32));
5612 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5615 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5616 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5617 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5618 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5619 DAG.getConstant(CnstVal, MVT::i32),
5620 DAG.getConstant(0, MVT::i32));
5621 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5624 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5625 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5626 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5627 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5628 DAG.getConstant(CnstVal, MVT::i32),
5629 DAG.getConstant(8, MVT::i32));
5630 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5637 CnstBits = UndefBits;
5641 // We can always fall back to a non-immediate OR.
5646 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5647 // be truncated to fit element width.
5648 static SDValue NormalizeBuildVector(SDValue Op,
5649 SelectionDAG &DAG) {
5650 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5652 EVT VT = Op.getValueType();
5653 EVT EltTy= VT.getVectorElementType();
5655 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5658 SmallVector<SDValue, 16> Ops;
5659 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5660 SDValue Lane = Op.getOperand(I);
5661 if (Lane.getOpcode() == ISD::Constant) {
5662 APInt LowBits(EltTy.getSizeInBits(),
5663 cast<ConstantSDNode>(Lane)->getZExtValue());
5664 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5666 Ops.push_back(Lane);
5668 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5671 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5672 SelectionDAG &DAG) const {
5674 EVT VT = Op.getValueType();
5675 Op = NormalizeBuildVector(Op, DAG);
5676 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5678 APInt CnstBits(VT.getSizeInBits(), 0);
5679 APInt UndefBits(VT.getSizeInBits(), 0);
5680 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5681 // We make use of a little bit of goto ickiness in order to avoid having to
5682 // duplicate the immediate matching logic for the undef toggled case.
5683 bool SecondTry = false;
5686 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5687 CnstBits = CnstBits.zextOrTrunc(64);
5688 uint64_t CnstVal = CnstBits.getZExtValue();
5690 // Certain magic vector constants (used to express things like NOT
5691 // and NEG) are passed through unmodified. This allows codegen patterns
5692 // for these operations to match. Special-purpose patterns will lower
5693 // these immediates to MOVIs if it proves necessary.
5694 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5697 // The many faces of MOVI...
5698 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5699 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5700 if (VT.getSizeInBits() == 128) {
5701 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5702 DAG.getConstant(CnstVal, MVT::i32));
5703 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5706 // Support the V64 version via subregister insertion.
5707 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5708 DAG.getConstant(CnstVal, MVT::i32));
5709 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5712 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5713 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5714 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5715 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5716 DAG.getConstant(CnstVal, MVT::i32),
5717 DAG.getConstant(0, MVT::i32));
5718 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5721 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5722 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5723 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5724 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5725 DAG.getConstant(CnstVal, MVT::i32),
5726 DAG.getConstant(8, MVT::i32));
5727 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5730 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5731 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5732 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5733 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5734 DAG.getConstant(CnstVal, MVT::i32),
5735 DAG.getConstant(16, MVT::i32));
5736 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5739 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5740 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5741 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5742 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5743 DAG.getConstant(CnstVal, MVT::i32),
5744 DAG.getConstant(24, MVT::i32));
5745 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5748 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5749 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5750 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5751 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5752 DAG.getConstant(CnstVal, MVT::i32),
5753 DAG.getConstant(0, MVT::i32));
5754 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5757 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5758 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5759 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5760 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5761 DAG.getConstant(CnstVal, MVT::i32),
5762 DAG.getConstant(8, MVT::i32));
5763 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5766 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5767 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5768 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5769 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5770 DAG.getConstant(CnstVal, MVT::i32),
5771 DAG.getConstant(264, MVT::i32));
5772 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5775 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5776 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5777 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5778 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5779 DAG.getConstant(CnstVal, MVT::i32),
5780 DAG.getConstant(272, MVT::i32));
5781 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5784 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5785 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5786 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5787 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5788 DAG.getConstant(CnstVal, MVT::i32));
5789 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5792 // The few faces of FMOV...
5793 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5794 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5795 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5796 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5797 DAG.getConstant(CnstVal, MVT::i32));
5798 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5801 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5802 VT.getSizeInBits() == 128) {
5803 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5804 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5805 DAG.getConstant(CnstVal, MVT::i32));
5806 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5809 // The many faces of MVNI...
5811 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5812 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5813 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5814 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5815 DAG.getConstant(CnstVal, MVT::i32),
5816 DAG.getConstant(0, MVT::i32));
5817 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5820 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5821 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5822 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5823 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5824 DAG.getConstant(CnstVal, MVT::i32),
5825 DAG.getConstant(8, MVT::i32));
5826 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5829 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5830 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5831 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5832 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5833 DAG.getConstant(CnstVal, MVT::i32),
5834 DAG.getConstant(16, MVT::i32));
5835 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5838 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5839 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5840 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5841 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5842 DAG.getConstant(CnstVal, MVT::i32),
5843 DAG.getConstant(24, MVT::i32));
5844 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5847 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5848 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5849 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5850 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5851 DAG.getConstant(CnstVal, MVT::i32),
5852 DAG.getConstant(0, MVT::i32));
5853 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5856 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5857 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5858 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5859 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5860 DAG.getConstant(CnstVal, MVT::i32),
5861 DAG.getConstant(8, MVT::i32));
5862 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5865 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5866 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5867 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5868 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5869 DAG.getConstant(CnstVal, MVT::i32),
5870 DAG.getConstant(264, MVT::i32));
5871 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5874 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5875 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5876 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5877 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5878 DAG.getConstant(CnstVal, MVT::i32),
5879 DAG.getConstant(272, MVT::i32));
5880 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5887 CnstBits = UndefBits;
5892 // Scan through the operands to find some interesting properties we can
5894 // 1) If only one value is used, we can use a DUP, or
5895 // 2) if only the low element is not undef, we can just insert that, or
5896 // 3) if only one constant value is used (w/ some non-constant lanes),
5897 // we can splat the constant value into the whole vector then fill
5898 // in the non-constant lanes.
5899 // 4) FIXME: If different constant values are used, but we can intelligently
5900 // select the values we'll be overwriting for the non-constant
5901 // lanes such that we can directly materialize the vector
5902 // some other way (MOVI, e.g.), we can be sneaky.
5903 unsigned NumElts = VT.getVectorNumElements();
5904 bool isOnlyLowElement = true;
5905 bool usesOnlyOneValue = true;
5906 bool usesOnlyOneConstantValue = true;
5907 bool isConstant = true;
5908 unsigned NumConstantLanes = 0;
5910 SDValue ConstantValue;
5911 for (unsigned i = 0; i < NumElts; ++i) {
5912 SDValue V = Op.getOperand(i);
5913 if (V.getOpcode() == ISD::UNDEF)
5916 isOnlyLowElement = false;
5917 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5920 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5922 if (!ConstantValue.getNode())
5924 else if (ConstantValue != V)
5925 usesOnlyOneConstantValue = false;
5928 if (!Value.getNode())
5930 else if (V != Value)
5931 usesOnlyOneValue = false;
5934 if (!Value.getNode())
5935 return DAG.getUNDEF(VT);
5937 if (isOnlyLowElement)
5938 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5940 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5941 // i32 and try again.
5942 if (usesOnlyOneValue) {
5944 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5945 Value.getValueType() != VT)
5946 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5948 // This is actually a DUPLANExx operation, which keeps everything vectory.
5950 // DUPLANE works on 128-bit vectors, widen it if necessary.
5951 SDValue Lane = Value.getOperand(1);
5952 Value = Value.getOperand(0);
5953 if (Value.getValueType().getSizeInBits() == 64)
5954 Value = WidenVector(Value, DAG);
5956 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5957 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5960 if (VT.getVectorElementType().isFloatingPoint()) {
5961 SmallVector<SDValue, 8> Ops;
5962 EVT EltTy = VT.getVectorElementType();
5963 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5964 "Unsupported floating-point vector type");
5965 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5966 for (unsigned i = 0; i < NumElts; ++i)
5967 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5968 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5969 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5970 Val = LowerBUILD_VECTOR(Val, DAG);
5972 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5976 // If there was only one constant value used and for more than one lane,
5977 // start by splatting that value, then replace the non-constant lanes. This
5978 // is better than the default, which will perform a separate initialization
5980 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5981 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5982 // Now insert the non-constant lanes.
5983 for (unsigned i = 0; i < NumElts; ++i) {
5984 SDValue V = Op.getOperand(i);
5985 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5986 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5987 // Note that type legalization likely mucked about with the VT of the
5988 // source operand, so we may have to convert it here before inserting.
5989 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5995 // If all elements are constants and the case above didn't get hit, fall back
5996 // to the default expansion, which will generate a load from the constant
6001 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6003 SDValue shuffle = ReconstructShuffle(Op, DAG);
6004 if (shuffle != SDValue())
6008 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6009 // know the default expansion would otherwise fall back on something even
6010 // worse. For a vector with one or two non-undef values, that's
6011 // scalar_to_vector for the elements followed by a shuffle (provided the
6012 // shuffle is valid for the target) and materialization element by element
6013 // on the stack followed by a load for everything else.
6014 if (!isConstant && !usesOnlyOneValue) {
6015 SDValue Vec = DAG.getUNDEF(VT);
6016 SDValue Op0 = Op.getOperand(0);
6017 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6019 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6020 // a) Avoid a RMW dependency on the full vector register, and
6021 // b) Allow the register coalescer to fold away the copy if the
6022 // value is already in an S or D register.
6023 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6024 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6026 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6027 DAG.getTargetConstant(SubIdx, MVT::i32));
6028 Vec = SDValue(N, 0);
6031 for (; i < NumElts; ++i) {
6032 SDValue V = Op.getOperand(i);
6033 if (V.getOpcode() == ISD::UNDEF)
6035 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
6036 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6041 // Just use the default expansion. We failed to find a better alternative.
6045 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6046 SelectionDAG &DAG) const {
6047 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6049 // Check for non-constant or out of range lane.
6050 EVT VT = Op.getOperand(0).getValueType();
6051 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6052 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6056 // Insertion/extraction are legal for V128 types.
6057 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6058 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6062 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6063 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6066 // For V64 types, we perform insertion by expanding the value
6067 // to a V128 type and perform the insertion on that.
6069 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6070 EVT WideTy = WideVec.getValueType();
6072 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6073 Op.getOperand(1), Op.getOperand(2));
6074 // Re-narrow the resultant vector.
6075 return NarrowVector(Node, DAG);
6079 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6080 SelectionDAG &DAG) const {
6081 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6083 // Check for non-constant or out of range lane.
6084 EVT VT = Op.getOperand(0).getValueType();
6085 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6086 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6090 // Insertion/extraction are legal for V128 types.
6091 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6092 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6096 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6097 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6100 // For V64 types, we perform extraction by expanding the value
6101 // to a V128 type and perform the extraction on that.
6103 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6104 EVT WideTy = WideVec.getValueType();
6106 EVT ExtrTy = WideTy.getVectorElementType();
6107 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6110 // For extractions, we just return the result directly.
6111 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6115 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6116 SelectionDAG &DAG) const {
6117 EVT VT = Op.getOperand(0).getValueType();
6123 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6126 unsigned Val = Cst->getZExtValue();
6128 unsigned Size = Op.getValueType().getSizeInBits();
6132 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6135 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6138 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6141 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6144 llvm_unreachable("Unexpected vector type in extract_subvector!");
6147 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6149 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6155 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6157 if (VT.getVectorNumElements() == 4 &&
6158 (VT.is128BitVector() || VT.is64BitVector())) {
6159 unsigned PFIndexes[4];
6160 for (unsigned i = 0; i != 4; ++i) {
6164 PFIndexes[i] = M[i];
6167 // Compute the index in the perfect shuffle table.
6168 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6169 PFIndexes[2] * 9 + PFIndexes[3];
6170 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6171 unsigned Cost = (PFEntry >> 30);
6179 unsigned DummyUnsigned;
6181 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6182 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6183 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6184 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6185 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6186 isZIPMask(M, VT, DummyUnsigned) ||
6187 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6188 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6189 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6190 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6191 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6194 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6195 /// operand of a vector shift operation, where all the elements of the
6196 /// build_vector must have the same constant integer value.
6197 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6198 // Ignore bit_converts.
6199 while (Op.getOpcode() == ISD::BITCAST)
6200 Op = Op.getOperand(0);
6201 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6202 APInt SplatBits, SplatUndef;
6203 unsigned SplatBitSize;
6205 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6206 HasAnyUndefs, ElementBits) ||
6207 SplatBitSize > ElementBits)
6209 Cnt = SplatBits.getSExtValue();
6213 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6214 /// operand of a vector shift left operation. That value must be in the range:
6215 /// 0 <= Value < ElementBits for a left shift; or
6216 /// 0 <= Value <= ElementBits for a long left shift.
6217 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6218 assert(VT.isVector() && "vector shift count is not a vector type");
6219 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6220 if (!getVShiftImm(Op, ElementBits, Cnt))
6222 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6225 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6226 /// operand of a vector shift right operation. For a shift opcode, the value
6227 /// is positive, but for an intrinsic the value count must be negative. The
6228 /// absolute value must be in the range:
6229 /// 1 <= |Value| <= ElementBits for a right shift; or
6230 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6231 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6233 assert(VT.isVector() && "vector shift count is not a vector type");
6234 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6235 if (!getVShiftImm(Op, ElementBits, Cnt))
6239 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6242 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6243 SelectionDAG &DAG) const {
6244 EVT VT = Op.getValueType();
6248 if (!Op.getOperand(1).getValueType().isVector())
6250 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6252 switch (Op.getOpcode()) {
6254 llvm_unreachable("unexpected shift opcode");
6257 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6258 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6259 DAG.getConstant(Cnt, MVT::i32));
6260 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6261 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6262 Op.getOperand(0), Op.getOperand(1));
6265 // Right shift immediate
6266 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6269 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6270 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6271 DAG.getConstant(Cnt, MVT::i32));
6274 // Right shift register. Note, there is not a shift right register
6275 // instruction, but the shift left register instruction takes a signed
6276 // value, where negative numbers specify a right shift.
6277 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6278 : Intrinsic::aarch64_neon_ushl;
6279 // negate the shift amount
6280 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6281 SDValue NegShiftLeft =
6282 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6283 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6284 return NegShiftLeft;
6290 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6291 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6292 SDLoc dl, SelectionDAG &DAG) {
6293 EVT SrcVT = LHS.getValueType();
6294 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6295 "function only supposed to emit natural comparisons");
6297 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6298 APInt CnstBits(VT.getSizeInBits(), 0);
6299 APInt UndefBits(VT.getSizeInBits(), 0);
6300 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6301 bool IsZero = IsCnst && (CnstBits == 0);
6303 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6307 case AArch64CC::NE: {
6310 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6312 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6313 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6317 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6318 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6321 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6322 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6325 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6326 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6329 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6330 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6334 // If we ignore NaNs then we can use to the MI implementation.
6338 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6339 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6346 case AArch64CC::NE: {
6349 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6351 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6352 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6356 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6357 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6360 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6361 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6364 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6365 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6368 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6369 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6371 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6373 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6376 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6377 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6379 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6381 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6385 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6386 SelectionDAG &DAG) const {
6387 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6388 SDValue LHS = Op.getOperand(0);
6389 SDValue RHS = Op.getOperand(1);
6390 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6393 if (LHS.getValueType().getVectorElementType().isInteger()) {
6394 assert(LHS.getValueType() == RHS.getValueType());
6395 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6397 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6398 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6401 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6402 LHS.getValueType().getVectorElementType() == MVT::f64);
6404 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6405 // clean. Some of them require two branches to implement.
6406 AArch64CC::CondCode CC1, CC2;
6408 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6410 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6412 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6416 if (CC2 != AArch64CC::AL) {
6418 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6419 if (!Cmp2.getNode())
6422 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6425 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6428 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6433 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6434 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6435 /// specified in the intrinsic calls.
6436 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6438 unsigned Intrinsic) const {
6439 switch (Intrinsic) {
6440 case Intrinsic::aarch64_neon_ld2:
6441 case Intrinsic::aarch64_neon_ld3:
6442 case Intrinsic::aarch64_neon_ld4:
6443 case Intrinsic::aarch64_neon_ld1x2:
6444 case Intrinsic::aarch64_neon_ld1x3:
6445 case Intrinsic::aarch64_neon_ld1x4:
6446 case Intrinsic::aarch64_neon_ld2lane:
6447 case Intrinsic::aarch64_neon_ld3lane:
6448 case Intrinsic::aarch64_neon_ld4lane:
6449 case Intrinsic::aarch64_neon_ld2r:
6450 case Intrinsic::aarch64_neon_ld3r:
6451 case Intrinsic::aarch64_neon_ld4r: {
6452 Info.opc = ISD::INTRINSIC_W_CHAIN;
6453 // Conservatively set memVT to the entire set of vectors loaded.
6454 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6455 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6456 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6459 Info.vol = false; // volatile loads with NEON intrinsics not supported
6460 Info.readMem = true;
6461 Info.writeMem = false;
6464 case Intrinsic::aarch64_neon_st2:
6465 case Intrinsic::aarch64_neon_st3:
6466 case Intrinsic::aarch64_neon_st4:
6467 case Intrinsic::aarch64_neon_st1x2:
6468 case Intrinsic::aarch64_neon_st1x3:
6469 case Intrinsic::aarch64_neon_st1x4:
6470 case Intrinsic::aarch64_neon_st2lane:
6471 case Intrinsic::aarch64_neon_st3lane:
6472 case Intrinsic::aarch64_neon_st4lane: {
6473 Info.opc = ISD::INTRINSIC_VOID;
6474 // Conservatively set memVT to the entire set of vectors stored.
6475 unsigned NumElts = 0;
6476 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6477 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6478 if (!ArgTy->isVectorTy())
6480 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6482 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6483 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6486 Info.vol = false; // volatile stores with NEON intrinsics not supported
6487 Info.readMem = false;
6488 Info.writeMem = true;
6491 case Intrinsic::aarch64_ldaxr:
6492 case Intrinsic::aarch64_ldxr: {
6493 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6494 Info.opc = ISD::INTRINSIC_W_CHAIN;
6495 Info.memVT = MVT::getVT(PtrTy->getElementType());
6496 Info.ptrVal = I.getArgOperand(0);
6498 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6500 Info.readMem = true;
6501 Info.writeMem = false;
6504 case Intrinsic::aarch64_stlxr:
6505 case Intrinsic::aarch64_stxr: {
6506 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6507 Info.opc = ISD::INTRINSIC_W_CHAIN;
6508 Info.memVT = MVT::getVT(PtrTy->getElementType());
6509 Info.ptrVal = I.getArgOperand(1);
6511 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6513 Info.readMem = false;
6514 Info.writeMem = true;
6517 case Intrinsic::aarch64_ldaxp:
6518 case Intrinsic::aarch64_ldxp: {
6519 Info.opc = ISD::INTRINSIC_W_CHAIN;
6520 Info.memVT = MVT::i128;
6521 Info.ptrVal = I.getArgOperand(0);
6525 Info.readMem = true;
6526 Info.writeMem = false;
6529 case Intrinsic::aarch64_stlxp:
6530 case Intrinsic::aarch64_stxp: {
6531 Info.opc = ISD::INTRINSIC_W_CHAIN;
6532 Info.memVT = MVT::i128;
6533 Info.ptrVal = I.getArgOperand(2);
6537 Info.readMem = false;
6538 Info.writeMem = true;
6548 // Truncations from 64-bit GPR to 32-bit GPR is free.
6549 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6550 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6552 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6553 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6554 return NumBits1 > NumBits2;
6556 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6557 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6559 unsigned NumBits1 = VT1.getSizeInBits();
6560 unsigned NumBits2 = VT2.getSizeInBits();
6561 return NumBits1 > NumBits2;
6564 /// Check if it is profitable to hoist instruction in then/else to if.
6565 /// Not profitable if I and it's user can form a FMA instruction
6566 /// because we prefer FMSUB/FMADD.
6567 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6568 if (I->getOpcode() != Instruction::FMul)
6571 if (I->getNumUses() != 1)
6574 Instruction *User = I->user_back();
6577 !(User->getOpcode() == Instruction::FSub ||
6578 User->getOpcode() == Instruction::FAdd))
6581 const TargetOptions &Options = getTargetMachine().Options;
6582 EVT VT = getValueType(User->getOperand(0)->getType());
6584 if (isFMAFasterThanFMulAndFAdd(VT) &&
6585 isOperationLegalOrCustom(ISD::FMA, VT) &&
6586 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6592 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6594 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6595 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6597 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6598 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6599 return NumBits1 == 32 && NumBits2 == 64;
6601 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6602 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6604 unsigned NumBits1 = VT1.getSizeInBits();
6605 unsigned NumBits2 = VT2.getSizeInBits();
6606 return NumBits1 == 32 && NumBits2 == 64;
6609 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6610 EVT VT1 = Val.getValueType();
6611 if (isZExtFree(VT1, VT2)) {
6615 if (Val.getOpcode() != ISD::LOAD)
6618 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6619 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6620 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6621 VT1.getSizeInBits() <= 32);
6624 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6625 if (isa<FPExtInst>(Ext))
6628 // Vector types are next free.
6629 if (Ext->getType()->isVectorTy())
6632 for (const Use &U : Ext->uses()) {
6633 // The extension is free if we can fold it with a left shift in an
6634 // addressing mode or an arithmetic operation: add, sub, and cmp.
6636 // Is there a shift?
6637 const Instruction *Instr = cast<Instruction>(U.getUser());
6639 // Is this a constant shift?
6640 switch (Instr->getOpcode()) {
6641 case Instruction::Shl:
6642 if (!isa<ConstantInt>(Instr->getOperand(1)))
6645 case Instruction::GetElementPtr: {
6646 gep_type_iterator GTI = gep_type_begin(Instr);
6647 std::advance(GTI, U.getOperandNo());
6649 // This extension will end up with a shift because of the scaling factor.
6650 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6651 // Get the shift amount based on the scaling factor:
6652 // log2(sizeof(IdxTy)) - log2(8).
6654 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6655 // Is the constant foldable in the shift of the addressing mode?
6656 // I.e., shift amount is between 1 and 4 inclusive.
6657 if (ShiftAmt == 0 || ShiftAmt > 4)
6661 case Instruction::Trunc:
6662 // Check if this is a noop.
6663 // trunc(sext ty1 to ty2) to ty1.
6664 if (Instr->getType() == Ext->getOperand(0)->getType())
6671 // At this point we can use the bfm family, so this extension is free
6677 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6678 unsigned &RequiredAligment) const {
6679 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6681 // Cyclone supports unaligned accesses.
6682 RequiredAligment = 0;
6683 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6684 return NumBits == 32 || NumBits == 64;
6687 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6688 unsigned &RequiredAligment) const {
6689 if (!LoadedType.isSimple() ||
6690 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6692 // Cyclone supports unaligned accesses.
6693 RequiredAligment = 0;
6694 unsigned NumBits = LoadedType.getSizeInBits();
6695 return NumBits == 32 || NumBits == 64;
6698 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6699 unsigned AlignCheck) {
6700 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6701 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6704 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6705 unsigned SrcAlign, bool IsMemset,
6708 MachineFunction &MF) const {
6709 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6710 // instruction to materialize the v2i64 zero and one store (with restrictive
6711 // addressing mode). Just do two i64 store of zero-registers.
6713 const Function *F = MF.getFunction();
6714 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6715 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6716 (memOpAlign(SrcAlign, DstAlign, 16) ||
6717 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6721 (memOpAlign(SrcAlign, DstAlign, 8) ||
6722 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
6726 (memOpAlign(SrcAlign, DstAlign, 4) ||
6727 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
6733 // 12-bit optionally shifted immediates are legal for adds.
6734 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6735 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6740 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6741 // immediates is the same as for an add or a sub.
6742 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6745 return isLegalAddImmediate(Immed);
6748 /// isLegalAddressingMode - Return true if the addressing mode represented
6749 /// by AM is legal for this target, for a load/store of the specified type.
6750 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6752 // AArch64 has five basic addressing modes:
6754 // reg + 9-bit signed offset
6755 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6757 // reg + SIZE_IN_BYTES * reg
6759 // No global is ever allowed as a base.
6763 // No reg+reg+imm addressing.
6764 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6767 // check reg + imm case:
6768 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6769 uint64_t NumBytes = 0;
6770 if (Ty->isSized()) {
6771 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6772 NumBytes = NumBits / 8;
6773 if (!isPowerOf2_64(NumBits))
6778 int64_t Offset = AM.BaseOffs;
6780 // 9-bit signed offset
6781 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6784 // 12-bit unsigned offset
6785 unsigned shift = Log2_64(NumBytes);
6786 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6787 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6788 (Offset >> shift) << shift == Offset)
6793 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6795 if (!AM.Scale || AM.Scale == 1 ||
6796 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6801 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6803 // Scaling factors are not free at all.
6804 // Operands | Rt Latency
6805 // -------------------------------------------
6807 // -------------------------------------------
6808 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6809 // Rt, [Xn, Wm, <extend> #imm] |
6810 if (isLegalAddressingMode(AM, Ty))
6811 // Scale represents reg2 * scale, thus account for 1 if
6812 // it is not equal to 0 or 1.
6813 return AM.Scale != 0 && AM.Scale != 1;
6817 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6818 VT = VT.getScalarType();
6823 switch (VT.getSimpleVT().SimpleTy) {
6835 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6836 // LR is a callee-save register, but we must treat it as clobbered by any call
6837 // site. Hence we include LR in the scratch registers, which are in turn added
6838 // as implicit-defs for stackmaps and patchpoints.
6839 static const MCPhysReg ScratchRegs[] = {
6840 AArch64::X16, AArch64::X17, AArch64::LR, 0
6846 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6847 EVT VT = N->getValueType(0);
6848 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6849 // it with shift to let it be lowered to UBFX.
6850 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6851 isa<ConstantSDNode>(N->getOperand(1))) {
6852 uint64_t TruncMask = N->getConstantOperandVal(1);
6853 if (isMask_64(TruncMask) &&
6854 N->getOperand(0).getOpcode() == ISD::SRL &&
6855 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6861 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6863 assert(Ty->isIntegerTy());
6865 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6869 int64_t Val = Imm.getSExtValue();
6870 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6873 if ((int64_t)Val < 0)
6876 Val &= (1LL << 32) - 1;
6878 unsigned LZ = countLeadingZeros((uint64_t)Val);
6879 unsigned Shift = (63 - LZ) / 16;
6880 // MOVZ is free so return true for one or fewer MOVK.
6884 // Generate SUBS and CSEL for integer abs.
6885 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6886 EVT VT = N->getValueType(0);
6888 SDValue N0 = N->getOperand(0);
6889 SDValue N1 = N->getOperand(1);
6892 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6893 // and change it to SUB and CSEL.
6894 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6895 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6896 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6897 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6898 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6899 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6901 // Generate SUBS & CSEL.
6903 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6904 N0.getOperand(0), DAG.getConstant(0, VT));
6905 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6906 DAG.getConstant(AArch64CC::PL, MVT::i32),
6907 SDValue(Cmp.getNode(), 1));
6912 // performXorCombine - Attempts to handle integer ABS.
6913 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6914 TargetLowering::DAGCombinerInfo &DCI,
6915 const AArch64Subtarget *Subtarget) {
6916 if (DCI.isBeforeLegalizeOps())
6919 return performIntegerAbsCombine(N, DAG);
6923 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6925 std::vector<SDNode *> *Created) const {
6926 // fold (sdiv X, pow2)
6927 EVT VT = N->getValueType(0);
6928 if ((VT != MVT::i32 && VT != MVT::i64) ||
6929 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6933 SDValue N0 = N->getOperand(0);
6934 unsigned Lg2 = Divisor.countTrailingZeros();
6935 SDValue Zero = DAG.getConstant(0, VT);
6936 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6938 // Add (N0 < 0) ? Pow2 - 1 : 0;
6940 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6941 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6942 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6945 Created->push_back(Cmp.getNode());
6946 Created->push_back(Add.getNode());
6947 Created->push_back(CSel.getNode());
6952 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6954 // If we're dividing by a positive value, we're done. Otherwise, we must
6955 // negate the result.
6956 if (Divisor.isNonNegative())
6960 Created->push_back(SRA.getNode());
6961 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6964 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6965 TargetLowering::DAGCombinerInfo &DCI,
6966 const AArch64Subtarget *Subtarget) {
6967 if (DCI.isBeforeLegalizeOps())
6970 // Multiplication of a power of two plus/minus one can be done more
6971 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6972 // future CPUs have a cheaper MADD instruction, this may need to be
6973 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6974 // 64-bit is 5 cycles, so this is always a win.
6975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6976 APInt Value = C->getAPIntValue();
6977 EVT VT = N->getValueType(0);
6978 if (Value.isNonNegative()) {
6979 // (mul x, 2^N + 1) => (add (shl x, N), x)
6980 APInt VM1 = Value - 1;
6981 if (VM1.isPowerOf2()) {
6982 SDValue ShiftedVal =
6983 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6984 DAG.getConstant(VM1.logBase2(), MVT::i64));
6985 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6988 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6989 APInt VP1 = Value + 1;
6990 if (VP1.isPowerOf2()) {
6991 SDValue ShiftedVal =
6992 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6993 DAG.getConstant(VP1.logBase2(), MVT::i64));
6994 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6998 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6999 APInt VNP1 = -Value + 1;
7000 if (VNP1.isPowerOf2()) {
7001 SDValue ShiftedVal =
7002 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
7003 DAG.getConstant(VNP1.logBase2(), MVT::i64));
7004 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
7007 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7008 APInt VNM1 = -Value - 1;
7009 if (VNM1.isPowerOf2()) {
7010 SDValue ShiftedVal =
7011 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
7012 DAG.getConstant(VNM1.logBase2(), MVT::i64));
7014 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
7015 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
7022 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7023 SelectionDAG &DAG) {
7024 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7025 // optimize away operation when it's from a constant.
7027 // The general transformation is:
7028 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7029 // AND(VECTOR_CMP(x,y), constant2)
7030 // constant2 = UNARYOP(constant)
7032 // Early exit if this isn't a vector operation, the operand of the
7033 // unary operation isn't a bitwise AND, or if the sizes of the operations
7035 EVT VT = N->getValueType(0);
7036 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7037 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7038 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7041 // Now check that the other operand of the AND is a constant. We could
7042 // make the transformation for non-constant splats as well, but it's unclear
7043 // that would be a benefit as it would not eliminate any operations, just
7044 // perform one more step in scalar code before moving to the vector unit.
7045 if (BuildVectorSDNode *BV =
7046 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7047 // Bail out if the vector isn't a constant.
7048 if (!BV->isConstant())
7051 // Everything checks out. Build up the new and improved node.
7053 EVT IntVT = BV->getValueType(0);
7054 // Create a new constant of the appropriate type for the transformed
7056 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7057 // The AND node needs bitcasts to/from an integer vector type around it.
7058 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7059 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7060 N->getOperand(0)->getOperand(0), MaskConst);
7061 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7068 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7069 const AArch64Subtarget *Subtarget) {
7070 // First try to optimize away the conversion when it's conditionally from
7071 // a constant. Vectors only.
7072 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7073 if (Res != SDValue())
7076 EVT VT = N->getValueType(0);
7077 if (VT != MVT::f32 && VT != MVT::f64)
7080 // Only optimize when the source and destination types have the same width.
7081 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7084 // If the result of an integer load is only used by an integer-to-float
7085 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7086 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7087 SDValue N0 = N->getOperand(0);
7088 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7089 // Do not change the width of a volatile load.
7090 !cast<LoadSDNode>(N0)->isVolatile()) {
7091 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7092 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7093 LN0->getPointerInfo(), LN0->isVolatile(),
7094 LN0->isNonTemporal(), LN0->isInvariant(),
7095 LN0->getAlignment());
7097 // Make sure successors of the original load stay after it by updating them
7098 // to use the new Chain.
7099 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7102 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7103 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7109 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7110 /// searches for and classifies those shifts.
7111 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7113 if (N.getOpcode() == ISD::SHL)
7115 else if (N.getOpcode() == ISD::SRL)
7120 if (!isa<ConstantSDNode>(N.getOperand(1)))
7123 ShiftAmount = N->getConstantOperandVal(1);
7124 Src = N->getOperand(0);
7128 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7129 /// registers viewed as a high/low pair. This function looks for the pattern:
7130 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7131 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7133 static SDValue tryCombineToEXTR(SDNode *N,
7134 TargetLowering::DAGCombinerInfo &DCI) {
7135 SelectionDAG &DAG = DCI.DAG;
7137 EVT VT = N->getValueType(0);
7139 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7141 if (VT != MVT::i32 && VT != MVT::i64)
7145 uint32_t ShiftLHS = 0;
7147 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7151 uint32_t ShiftRHS = 0;
7153 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7156 // If they're both trying to come from the high part of the register, they're
7157 // not really an EXTR.
7158 if (LHSFromHi == RHSFromHi)
7161 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7165 std::swap(LHS, RHS);
7166 std::swap(ShiftLHS, ShiftRHS);
7169 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7170 DAG.getConstant(ShiftRHS, MVT::i64));
7173 static SDValue tryCombineToBSL(SDNode *N,
7174 TargetLowering::DAGCombinerInfo &DCI) {
7175 EVT VT = N->getValueType(0);
7176 SelectionDAG &DAG = DCI.DAG;
7182 SDValue N0 = N->getOperand(0);
7183 if (N0.getOpcode() != ISD::AND)
7186 SDValue N1 = N->getOperand(1);
7187 if (N1.getOpcode() != ISD::AND)
7190 // We only have to look for constant vectors here since the general, variable
7191 // case can be handled in TableGen.
7192 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7193 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7194 for (int i = 1; i >= 0; --i)
7195 for (int j = 1; j >= 0; --j) {
7196 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7197 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7201 bool FoundMatch = true;
7202 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7203 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7204 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7206 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7213 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7214 N0->getOperand(1 - i), N1->getOperand(1 - j));
7220 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7221 const AArch64Subtarget *Subtarget) {
7222 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7223 if (!EnableAArch64ExtrGeneration)
7225 SelectionDAG &DAG = DCI.DAG;
7226 EVT VT = N->getValueType(0);
7228 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7231 SDValue Res = tryCombineToEXTR(N, DCI);
7235 Res = tryCombineToBSL(N, DCI);
7242 static SDValue performBitcastCombine(SDNode *N,
7243 TargetLowering::DAGCombinerInfo &DCI,
7244 SelectionDAG &DAG) {
7245 // Wait 'til after everything is legalized to try this. That way we have
7246 // legal vector types and such.
7247 if (DCI.isBeforeLegalizeOps())
7250 // Remove extraneous bitcasts around an extract_subvector.
7252 // (v4i16 (bitconvert
7253 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7255 // (extract_subvector ((v8i16 ...), (i64 4)))
7257 // Only interested in 64-bit vectors as the ultimate result.
7258 EVT VT = N->getValueType(0);
7261 if (VT.getSimpleVT().getSizeInBits() != 64)
7263 // Is the operand an extract_subvector starting at the beginning or halfway
7264 // point of the vector? A low half may also come through as an
7265 // EXTRACT_SUBREG, so look for that, too.
7266 SDValue Op0 = N->getOperand(0);
7267 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7268 !(Op0->isMachineOpcode() &&
7269 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7271 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7272 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7273 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7275 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7276 if (idx != AArch64::dsub)
7278 // The dsub reference is equivalent to a lane zero subvector reference.
7281 // Look through the bitcast of the input to the extract.
7282 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7284 SDValue Source = Op0->getOperand(0)->getOperand(0);
7285 // If the source type has twice the number of elements as our destination
7286 // type, we know this is an extract of the high or low half of the vector.
7287 EVT SVT = Source->getValueType(0);
7288 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7291 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7293 // Create the simplified form to just extract the low or high half of the
7294 // vector directly rather than bothering with the bitcasts.
7296 unsigned NumElements = VT.getVectorNumElements();
7298 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7299 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7301 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7302 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7308 static SDValue performConcatVectorsCombine(SDNode *N,
7309 TargetLowering::DAGCombinerInfo &DCI,
7310 SelectionDAG &DAG) {
7312 EVT VT = N->getValueType(0);
7313 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7315 // Optimize concat_vectors of truncated vectors, where the intermediate
7316 // type is illegal, to avoid said illegality, e.g.,
7317 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7318 // (v2i16 (truncate (v2i64)))))
7320 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7321 // (v4i32 (bitcast (v2i64))),
7323 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7324 // on both input and result type, so we might generate worse code.
7325 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7326 if (N->getNumOperands() == 2 &&
7327 N0->getOpcode() == ISD::TRUNCATE &&
7328 N1->getOpcode() == ISD::TRUNCATE) {
7329 SDValue N00 = N0->getOperand(0);
7330 SDValue N10 = N1->getOperand(0);
7331 EVT N00VT = N00.getValueType();
7333 if (N00VT == N10.getValueType() &&
7334 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7335 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7336 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7337 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7338 for (size_t i = 0; i < Mask.size(); ++i)
7340 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7341 DAG.getVectorShuffle(
7343 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7344 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7348 // Wait 'til after everything is legalized to try this. That way we have
7349 // legal vector types and such.
7350 if (DCI.isBeforeLegalizeOps())
7353 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7354 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7355 // canonicalise to that.
7356 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7357 assert(VT.getVectorElementType().getSizeInBits() == 64);
7358 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7359 DAG.getConstant(0, MVT::i64));
7362 // Canonicalise concat_vectors so that the right-hand vector has as few
7363 // bit-casts as possible before its real operation. The primary matching
7364 // destination for these operations will be the narrowing "2" instructions,
7365 // which depend on the operation being performed on this right-hand vector.
7367 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7369 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7371 if (N1->getOpcode() != ISD::BITCAST)
7373 SDValue RHS = N1->getOperand(0);
7374 MVT RHSTy = RHS.getValueType().getSimpleVT();
7375 // If the RHS is not a vector, this is not the pattern we're looking for.
7376 if (!RHSTy.isVector())
7379 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7381 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7382 RHSTy.getVectorNumElements() * 2);
7383 return DAG.getNode(ISD::BITCAST, dl, VT,
7384 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7385 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7389 static SDValue tryCombineFixedPointConvert(SDNode *N,
7390 TargetLowering::DAGCombinerInfo &DCI,
7391 SelectionDAG &DAG) {
7392 // Wait 'til after everything is legalized to try this. That way we have
7393 // legal vector types and such.
7394 if (DCI.isBeforeLegalizeOps())
7396 // Transform a scalar conversion of a value from a lane extract into a
7397 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7398 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7399 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7401 // The second form interacts better with instruction selection and the
7402 // register allocator to avoid cross-class register copies that aren't
7403 // coalescable due to a lane reference.
7405 // Check the operand and see if it originates from a lane extract.
7406 SDValue Op1 = N->getOperand(1);
7407 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7408 // Yep, no additional predication needed. Perform the transform.
7409 SDValue IID = N->getOperand(0);
7410 SDValue Shift = N->getOperand(2);
7411 SDValue Vec = Op1.getOperand(0);
7412 SDValue Lane = Op1.getOperand(1);
7413 EVT ResTy = N->getValueType(0);
7417 // The vector width should be 128 bits by the time we get here, even
7418 // if it started as 64 bits (the extract_vector handling will have
7420 assert(Vec.getValueType().getSizeInBits() == 128 &&
7421 "unexpected vector size on extract_vector_elt!");
7422 if (Vec.getValueType() == MVT::v4i32)
7423 VecResTy = MVT::v4f32;
7424 else if (Vec.getValueType() == MVT::v2i64)
7425 VecResTy = MVT::v2f64;
7427 llvm_unreachable("unexpected vector type!");
7430 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7431 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7436 // AArch64 high-vector "long" operations are formed by performing the non-high
7437 // version on an extract_subvector of each operand which gets the high half:
7439 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7441 // However, there are cases which don't have an extract_high explicitly, but
7442 // have another operation that can be made compatible with one for free. For
7445 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7447 // This routine does the actual conversion of such DUPs, once outer routines
7448 // have determined that everything else is in order.
7449 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7450 // We can handle most types of duplicate, but the lane ones have an extra
7451 // operand saying *which* lane, so we need to know.
7453 switch (N.getOpcode()) {
7454 case AArch64ISD::DUP:
7457 case AArch64ISD::DUPLANE8:
7458 case AArch64ISD::DUPLANE16:
7459 case AArch64ISD::DUPLANE32:
7460 case AArch64ISD::DUPLANE64:
7467 MVT NarrowTy = N.getSimpleValueType();
7468 if (!NarrowTy.is64BitVector())
7471 MVT ElementTy = NarrowTy.getVectorElementType();
7472 unsigned NumElems = NarrowTy.getVectorNumElements();
7473 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7477 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7480 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7482 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7483 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7486 static bool isEssentiallyExtractSubvector(SDValue N) {
7487 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7490 return N.getOpcode() == ISD::BITCAST &&
7491 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7494 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7495 struct GenericSetCCInfo {
7496 const SDValue *Opnd0;
7497 const SDValue *Opnd1;
7501 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7502 struct AArch64SetCCInfo {
7504 AArch64CC::CondCode CC;
7507 /// \brief Helper structure to keep track of SetCC information.
7509 GenericSetCCInfo Generic;
7510 AArch64SetCCInfo AArch64;
7513 /// \brief Helper structure to be able to read SetCC information. If set to
7514 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7515 /// GenericSetCCInfo.
7516 struct SetCCInfoAndKind {
7521 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7523 /// AArch64 lowered one.
7524 /// \p SetCCInfo is filled accordingly.
7525 /// \post SetCCInfo is meanginfull only when this function returns true.
7526 /// \return True when Op is a kind of SET_CC operation.
7527 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7528 // If this is a setcc, this is straight forward.
7529 if (Op.getOpcode() == ISD::SETCC) {
7530 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7531 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7532 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7533 SetCCInfo.IsAArch64 = false;
7536 // Otherwise, check if this is a matching csel instruction.
7540 if (Op.getOpcode() != AArch64ISD::CSEL)
7542 // Set the information about the operands.
7543 // TODO: we want the operands of the Cmp not the csel
7544 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7545 SetCCInfo.IsAArch64 = true;
7546 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7547 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7549 // Check that the operands matches the constraints:
7550 // (1) Both operands must be constants.
7551 // (2) One must be 1 and the other must be 0.
7552 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7553 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7556 if (!TValue || !FValue)
7560 if (!TValue->isOne()) {
7561 // Update the comparison when we are interested in !cc.
7562 std::swap(TValue, FValue);
7563 SetCCInfo.Info.AArch64.CC =
7564 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7566 return TValue->isOne() && FValue->isNullValue();
7569 // Returns true if Op is setcc or zext of setcc.
7570 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7571 if (isSetCC(Op, Info))
7573 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7574 isSetCC(Op->getOperand(0), Info));
7577 // The folding we want to perform is:
7578 // (add x, [zext] (setcc cc ...) )
7580 // (csel x, (add x, 1), !cc ...)
7582 // The latter will get matched to a CSINC instruction.
7583 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7584 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7585 SDValue LHS = Op->getOperand(0);
7586 SDValue RHS = Op->getOperand(1);
7587 SetCCInfoAndKind InfoAndKind;
7589 // If neither operand is a SET_CC, give up.
7590 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7591 std::swap(LHS, RHS);
7592 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7596 // FIXME: This could be generatized to work for FP comparisons.
7597 EVT CmpVT = InfoAndKind.IsAArch64
7598 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7599 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7600 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7606 if (InfoAndKind.IsAArch64) {
7607 CCVal = DAG.getConstant(
7608 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7609 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7611 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7612 *InfoAndKind.Info.Generic.Opnd1,
7613 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7616 EVT VT = Op->getValueType(0);
7617 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7618 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7621 // The basic add/sub long vector instructions have variants with "2" on the end
7622 // which act on the high-half of their inputs. They are normally matched by
7625 // (add (zeroext (extract_high LHS)),
7626 // (zeroext (extract_high RHS)))
7627 // -> uaddl2 vD, vN, vM
7629 // However, if one of the extracts is something like a duplicate, this
7630 // instruction can still be used profitably. This function puts the DAG into a
7631 // more appropriate form for those patterns to trigger.
7632 static SDValue performAddSubLongCombine(SDNode *N,
7633 TargetLowering::DAGCombinerInfo &DCI,
7634 SelectionDAG &DAG) {
7635 if (DCI.isBeforeLegalizeOps())
7638 MVT VT = N->getSimpleValueType(0);
7639 if (!VT.is128BitVector()) {
7640 if (N->getOpcode() == ISD::ADD)
7641 return performSetccAddFolding(N, DAG);
7645 // Make sure both branches are extended in the same way.
7646 SDValue LHS = N->getOperand(0);
7647 SDValue RHS = N->getOperand(1);
7648 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7649 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7650 LHS.getOpcode() != RHS.getOpcode())
7653 unsigned ExtType = LHS.getOpcode();
7655 // It's not worth doing if at least one of the inputs isn't already an
7656 // extract, but we don't know which it'll be so we have to try both.
7657 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7658 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7662 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7663 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7664 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7668 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7671 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7674 // Massage DAGs which we can use the high-half "long" operations on into
7675 // something isel will recognize better. E.g.
7677 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7678 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7679 // (extract_high (v2i64 (dup128 scalar)))))
7681 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7682 TargetLowering::DAGCombinerInfo &DCI,
7683 SelectionDAG &DAG) {
7684 if (DCI.isBeforeLegalizeOps())
7687 SDValue LHS = N->getOperand(1);
7688 SDValue RHS = N->getOperand(2);
7689 assert(LHS.getValueType().is64BitVector() &&
7690 RHS.getValueType().is64BitVector() &&
7691 "unexpected shape for long operation");
7693 // Either node could be a DUP, but it's not worth doing both of them (you'd
7694 // just as well use the non-high version) so look for a corresponding extract
7695 // operation on the other "wing".
7696 if (isEssentiallyExtractSubvector(LHS)) {
7697 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7700 } else if (isEssentiallyExtractSubvector(RHS)) {
7701 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7706 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7707 N->getOperand(0), LHS, RHS);
7710 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7711 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7712 unsigned ElemBits = ElemTy.getSizeInBits();
7714 int64_t ShiftAmount;
7715 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7716 APInt SplatValue, SplatUndef;
7717 unsigned SplatBitSize;
7719 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7720 HasAnyUndefs, ElemBits) ||
7721 SplatBitSize != ElemBits)
7724 ShiftAmount = SplatValue.getSExtValue();
7725 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7726 ShiftAmount = CVN->getSExtValue();
7734 llvm_unreachable("Unknown shift intrinsic");
7735 case Intrinsic::aarch64_neon_sqshl:
7736 Opcode = AArch64ISD::SQSHL_I;
7737 IsRightShift = false;
7739 case Intrinsic::aarch64_neon_uqshl:
7740 Opcode = AArch64ISD::UQSHL_I;
7741 IsRightShift = false;
7743 case Intrinsic::aarch64_neon_srshl:
7744 Opcode = AArch64ISD::SRSHR_I;
7745 IsRightShift = true;
7747 case Intrinsic::aarch64_neon_urshl:
7748 Opcode = AArch64ISD::URSHR_I;
7749 IsRightShift = true;
7751 case Intrinsic::aarch64_neon_sqshlu:
7752 Opcode = AArch64ISD::SQSHLU_I;
7753 IsRightShift = false;
7757 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7758 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7759 DAG.getConstant(-ShiftAmount, MVT::i32));
7760 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7761 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7762 DAG.getConstant(ShiftAmount, MVT::i32));
7767 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7768 // the intrinsics must be legal and take an i32, this means there's almost
7769 // certainly going to be a zext in the DAG which we can eliminate.
7770 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7771 SDValue AndN = N->getOperand(2);
7772 if (AndN.getOpcode() != ISD::AND)
7775 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7776 if (!CMask || CMask->getZExtValue() != Mask)
7779 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7780 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7783 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7784 SelectionDAG &DAG) {
7785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
7786 DAG.getNode(Opc, SDLoc(N),
7787 N->getOperand(1).getSimpleValueType(),
7789 DAG.getConstant(0, MVT::i64));
7792 static SDValue performIntrinsicCombine(SDNode *N,
7793 TargetLowering::DAGCombinerInfo &DCI,
7794 const AArch64Subtarget *Subtarget) {
7795 SelectionDAG &DAG = DCI.DAG;
7796 unsigned IID = getIntrinsicID(N);
7800 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7801 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7802 return tryCombineFixedPointConvert(N, DCI, DAG);
7804 case Intrinsic::aarch64_neon_saddv:
7805 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7806 case Intrinsic::aarch64_neon_uaddv:
7807 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7808 case Intrinsic::aarch64_neon_sminv:
7809 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7810 case Intrinsic::aarch64_neon_uminv:
7811 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7812 case Intrinsic::aarch64_neon_smaxv:
7813 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7814 case Intrinsic::aarch64_neon_umaxv:
7815 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7816 case Intrinsic::aarch64_neon_fmax:
7817 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7818 N->getOperand(1), N->getOperand(2));
7819 case Intrinsic::aarch64_neon_fmin:
7820 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7821 N->getOperand(1), N->getOperand(2));
7822 case Intrinsic::aarch64_neon_smull:
7823 case Intrinsic::aarch64_neon_umull:
7824 case Intrinsic::aarch64_neon_pmull:
7825 case Intrinsic::aarch64_neon_sqdmull:
7826 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7827 case Intrinsic::aarch64_neon_sqshl:
7828 case Intrinsic::aarch64_neon_uqshl:
7829 case Intrinsic::aarch64_neon_sqshlu:
7830 case Intrinsic::aarch64_neon_srshl:
7831 case Intrinsic::aarch64_neon_urshl:
7832 return tryCombineShiftImm(IID, N, DAG);
7833 case Intrinsic::aarch64_crc32b:
7834 case Intrinsic::aarch64_crc32cb:
7835 return tryCombineCRC32(0xff, N, DAG);
7836 case Intrinsic::aarch64_crc32h:
7837 case Intrinsic::aarch64_crc32ch:
7838 return tryCombineCRC32(0xffff, N, DAG);
7843 static SDValue performExtendCombine(SDNode *N,
7844 TargetLowering::DAGCombinerInfo &DCI,
7845 SelectionDAG &DAG) {
7846 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7847 // we can convert that DUP into another extract_high (of a bigger DUP), which
7848 // helps the backend to decide that an sabdl2 would be useful, saving a real
7849 // extract_high operation.
7850 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7851 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7852 SDNode *ABDNode = N->getOperand(0).getNode();
7853 unsigned IID = getIntrinsicID(ABDNode);
7854 if (IID == Intrinsic::aarch64_neon_sabd ||
7855 IID == Intrinsic::aarch64_neon_uabd) {
7856 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7857 if (!NewABD.getNode())
7860 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7865 // This is effectively a custom type legalization for AArch64.
7867 // Type legalization will split an extend of a small, legal, type to a larger
7868 // illegal type by first splitting the destination type, often creating
7869 // illegal source types, which then get legalized in isel-confusing ways,
7870 // leading to really terrible codegen. E.g.,
7871 // %result = v8i32 sext v8i8 %value
7873 // %losrc = extract_subreg %value, ...
7874 // %hisrc = extract_subreg %value, ...
7875 // %lo = v4i32 sext v4i8 %losrc
7876 // %hi = v4i32 sext v4i8 %hisrc
7877 // Things go rapidly downhill from there.
7879 // For AArch64, the [sz]ext vector instructions can only go up one element
7880 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7881 // take two instructions.
7883 // This implies that the most efficient way to do the extend from v8i8
7884 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7885 // the normal splitting to happen for the v8i16->v8i32.
7887 // This is pre-legalization to catch some cases where the default
7888 // type legalization will create ill-tempered code.
7889 if (!DCI.isBeforeLegalizeOps())
7892 // We're only interested in cleaning things up for non-legal vector types
7893 // here. If both the source and destination are legal, things will just
7894 // work naturally without any fiddling.
7895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7896 EVT ResVT = N->getValueType(0);
7897 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7899 // If the vector type isn't a simple VT, it's beyond the scope of what
7900 // we're worried about here. Let legalization do its thing and hope for
7902 SDValue Src = N->getOperand(0);
7903 EVT SrcVT = Src->getValueType(0);
7904 if (!ResVT.isSimple() || !SrcVT.isSimple())
7907 // If the source VT is a 64-bit vector, we can play games and get the
7908 // better results we want.
7909 if (SrcVT.getSizeInBits() != 64)
7912 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7913 unsigned ElementCount = SrcVT.getVectorNumElements();
7914 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7916 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7918 // Now split the rest of the operation into two halves, each with a 64
7922 unsigned NumElements = ResVT.getVectorNumElements();
7923 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7924 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7925 ResVT.getVectorElementType(), NumElements / 2);
7927 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7928 LoVT.getVectorNumElements());
7929 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7930 DAG.getConstant(0, MVT::i64));
7931 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7932 DAG.getConstant(InNVT.getVectorNumElements(), MVT::i64));
7933 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7934 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7936 // Now combine the parts back together so we still have a single result
7937 // like the combiner expects.
7938 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7941 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7942 /// value. The load store optimizer pass will merge them to store pair stores.
7943 /// This has better performance than a splat of the scalar followed by a split
7944 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7945 /// followed by an ext.b and two stores.
7946 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7947 SDValue StVal = St->getValue();
7948 EVT VT = StVal.getValueType();
7950 // Don't replace floating point stores, they possibly won't be transformed to
7951 // stp because of the store pair suppress pass.
7952 if (VT.isFloatingPoint())
7955 // Check for insert vector elements.
7956 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7959 // We can express a splat as store pair(s) for 2 or 4 elements.
7960 unsigned NumVecElts = VT.getVectorNumElements();
7961 if (NumVecElts != 4 && NumVecElts != 2)
7963 SDValue SplatVal = StVal.getOperand(1);
7964 unsigned RemainInsertElts = NumVecElts - 1;
7966 // Check that this is a splat.
7967 while (--RemainInsertElts) {
7968 SDValue NextInsertElt = StVal.getOperand(0);
7969 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7971 if (NextInsertElt.getOperand(1) != SplatVal)
7973 StVal = NextInsertElt;
7975 unsigned OrigAlignment = St->getAlignment();
7976 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7977 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7979 // Create scalar stores. This is at least as good as the code sequence for a
7980 // split unaligned store wich is a dup.s, ext.b, and two stores.
7981 // Most of the time the three stores should be replaced by store pair
7982 // instructions (stp).
7984 SDValue BasePtr = St->getBasePtr();
7986 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7987 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7989 unsigned Offset = EltOffset;
7990 while (--NumVecElts) {
7991 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7992 DAG.getConstant(Offset, MVT::i64));
7993 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7994 St->getPointerInfo(), St->isVolatile(),
7995 St->isNonTemporal(), Alignment);
7996 Offset += EltOffset;
8001 static SDValue performSTORECombine(SDNode *N,
8002 TargetLowering::DAGCombinerInfo &DCI,
8004 const AArch64Subtarget *Subtarget) {
8005 if (!DCI.isBeforeLegalize())
8008 StoreSDNode *S = cast<StoreSDNode>(N);
8009 if (S->isVolatile())
8012 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8013 // page boundaries. We want to split such stores.
8014 if (!Subtarget->isCyclone())
8017 // Don't split at Oz.
8018 MachineFunction &MF = DAG.getMachineFunction();
8019 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8023 SDValue StVal = S->getValue();
8024 EVT VT = StVal.getValueType();
8026 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8027 // those up regresses performance on micro-benchmarks and olden/bh.
8028 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8031 // Split unaligned 16B stores. They are terrible for performance.
8032 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8033 // extensions can use this to mark that it does not want splitting to happen
8034 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8035 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8036 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8037 S->getAlignment() <= 2)
8040 // If we get a splat of a scalar convert this vector store to a store of
8041 // scalars. They will be merged into store pairs thereby removing two
8043 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8044 if (ReplacedSplat != SDValue())
8045 return ReplacedSplat;
8048 unsigned NumElts = VT.getVectorNumElements() / 2;
8049 // Split VT into two.
8051 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8052 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8053 DAG.getConstant(0, MVT::i64));
8054 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8055 DAG.getConstant(NumElts, MVT::i64));
8056 SDValue BasePtr = S->getBasePtr();
8058 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8059 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8060 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8061 DAG.getConstant(8, MVT::i64));
8062 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8063 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8067 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8068 /// post-increment LD1R.
8069 static SDValue performPostLD1Combine(SDNode *N,
8070 TargetLowering::DAGCombinerInfo &DCI,
8072 if (DCI.isBeforeLegalizeOps())
8075 SelectionDAG &DAG = DCI.DAG;
8076 EVT VT = N->getValueType(0);
8078 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8079 SDNode *LD = N->getOperand(LoadIdx).getNode();
8080 // If it is not LOAD, can not do such combine.
8081 if (LD->getOpcode() != ISD::LOAD)
8084 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8085 EVT MemVT = LoadSDN->getMemoryVT();
8086 // Check if memory operand is the same type as the vector element.
8087 if (MemVT != VT.getVectorElementType())
8090 // Check if there are other uses. If so, do not combine as it will introduce
8092 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8094 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8100 SDValue Addr = LD->getOperand(1);
8101 SDValue Vector = N->getOperand(0);
8102 // Search for a use of the address operand that is an increment.
8103 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8104 Addr.getNode()->use_end(); UI != UE; ++UI) {
8106 if (User->getOpcode() != ISD::ADD
8107 || UI.getUse().getResNo() != Addr.getResNo())
8110 // Check that the add is independent of the load. Otherwise, folding it
8111 // would create a cycle.
8112 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8114 // Also check that add is not used in the vector operand. This would also
8116 if (User->isPredecessorOf(Vector.getNode()))
8119 // If the increment is a constant, it must match the memory ref size.
8120 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8121 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8122 uint32_t IncVal = CInc->getZExtValue();
8123 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8124 if (IncVal != NumBytes)
8126 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8129 // Finally, check that the vector doesn't depend on the load.
8130 // Again, this would create a cycle.
8131 // The load depending on the vector is fine, as that's the case for the
8132 // LD1*post we'll eventually generate anyway.
8133 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8136 SmallVector<SDValue, 8> Ops;
8137 Ops.push_back(LD->getOperand(0)); // Chain
8139 Ops.push_back(Vector); // The vector to be inserted
8140 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8142 Ops.push_back(Addr);
8145 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8146 SDVTList SDTys = DAG.getVTList(Tys);
8147 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8148 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8150 LoadSDN->getMemOperand());
8153 SmallVector<SDValue, 2> NewResults;
8154 NewResults.push_back(SDValue(LD, 0)); // The result of load
8155 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8156 DCI.CombineTo(LD, NewResults);
8157 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8158 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8165 /// Target-specific DAG combine function for NEON load/store intrinsics
8166 /// to merge base address updates.
8167 static SDValue performNEONPostLDSTCombine(SDNode *N,
8168 TargetLowering::DAGCombinerInfo &DCI,
8169 SelectionDAG &DAG) {
8170 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8173 unsigned AddrOpIdx = N->getNumOperands() - 1;
8174 SDValue Addr = N->getOperand(AddrOpIdx);
8176 // Search for a use of the address operand that is an increment.
8177 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8178 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8180 if (User->getOpcode() != ISD::ADD ||
8181 UI.getUse().getResNo() != Addr.getResNo())
8184 // Check that the add is independent of the load/store. Otherwise, folding
8185 // it would create a cycle.
8186 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8189 // Find the new opcode for the updating load/store.
8190 bool IsStore = false;
8191 bool IsLaneOp = false;
8192 bool IsDupOp = false;
8193 unsigned NewOpc = 0;
8194 unsigned NumVecs = 0;
8195 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8197 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8198 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8200 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8202 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8204 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8205 NumVecs = 2; IsStore = true; break;
8206 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8207 NumVecs = 3; IsStore = true; break;
8208 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8209 NumVecs = 4; IsStore = true; break;
8210 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8212 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8214 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8216 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8217 NumVecs = 2; IsStore = true; break;
8218 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8219 NumVecs = 3; IsStore = true; break;
8220 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8221 NumVecs = 4; IsStore = true; break;
8222 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8223 NumVecs = 2; IsDupOp = true; break;
8224 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8225 NumVecs = 3; IsDupOp = true; break;
8226 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8227 NumVecs = 4; IsDupOp = true; break;
8228 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8229 NumVecs = 2; IsLaneOp = true; break;
8230 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8231 NumVecs = 3; IsLaneOp = true; break;
8232 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8233 NumVecs = 4; IsLaneOp = true; break;
8234 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8235 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8236 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8237 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8238 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8239 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8244 VecTy = N->getOperand(2).getValueType();
8246 VecTy = N->getValueType(0);
8248 // If the increment is a constant, it must match the memory ref size.
8249 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8250 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8251 uint32_t IncVal = CInc->getZExtValue();
8252 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8253 if (IsLaneOp || IsDupOp)
8254 NumBytes /= VecTy.getVectorNumElements();
8255 if (IncVal != NumBytes)
8257 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8259 SmallVector<SDValue, 8> Ops;
8260 Ops.push_back(N->getOperand(0)); // Incoming chain
8261 // Load lane and store have vector list as input.
8262 if (IsLaneOp || IsStore)
8263 for (unsigned i = 2; i < AddrOpIdx; ++i)
8264 Ops.push_back(N->getOperand(i));
8265 Ops.push_back(Addr); // Base register
8270 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8272 for (n = 0; n < NumResultVecs; ++n)
8274 Tys[n++] = MVT::i64; // Type of write back register
8275 Tys[n] = MVT::Other; // Type of the chain
8276 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8278 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8279 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8280 MemInt->getMemoryVT(),
8281 MemInt->getMemOperand());
8284 std::vector<SDValue> NewResults;
8285 for (unsigned i = 0; i < NumResultVecs; ++i) {
8286 NewResults.push_back(SDValue(UpdN.getNode(), i));
8288 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8289 DCI.CombineTo(N, NewResults);
8290 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8297 // Checks to see if the value is the prescribed width and returns information
8298 // about its extension mode.
8300 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8301 ExtType = ISD::NON_EXTLOAD;
8302 switch(V.getNode()->getOpcode()) {
8306 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8307 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8308 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8309 ExtType = LoadNode->getExtensionType();
8314 case ISD::AssertSext: {
8315 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8316 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8317 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8318 ExtType = ISD::SEXTLOAD;
8323 case ISD::AssertZext: {
8324 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8325 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8326 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8327 ExtType = ISD::ZEXTLOAD;
8333 case ISD::TargetConstant: {
8334 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8344 // This function does a whole lot of voodoo to determine if the tests are
8345 // equivalent without and with a mask. Essentially what happens is that given a
8348 // +-------------+ +-------------+ +-------------+ +-------------+
8349 // | Input | | AddConstant | | CompConstant| | CC |
8350 // +-------------+ +-------------+ +-------------+ +-------------+
8352 // V V | +----------+
8353 // +-------------+ +----+ | |
8354 // | ADD | |0xff| | |
8355 // +-------------+ +----+ | |
8358 // +-------------+ | |
8360 // +-------------+ | |
8369 // The AND node may be safely removed for some combinations of inputs. In
8370 // particular we need to take into account the extension type of the Input,
8371 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8372 // width of the input (this can work for any width inputs, the above graph is
8373 // specific to 8 bits.
8375 // The specific equations were worked out by generating output tables for each
8376 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8377 // problem was simplified by working with 4 bit inputs, which means we only
8378 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8379 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8380 // patterns present in both extensions (0,7). For every distinct set of
8381 // AddConstant and CompConstants bit patterns we can consider the masked and
8382 // unmasked versions to be equivalent if the result of this function is true for
8383 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8386 // and w10, w8, #0x0f
8388 // cset w9, AArch64CC
8390 // cset w11, AArch64CC
8395 // Since the above function shows when the outputs are equivalent it defines
8396 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8397 // would be expensive to run during compiles. The equations below were written
8398 // in a test harness that confirmed they gave equivalent outputs to the above
8399 // for all inputs function, so they can be used determine if the removal is
8402 // isEquivalentMaskless() is the code for testing if the AND can be removed
8403 // factored out of the DAG recognition as the DAG can take several forms.
8406 bool isEquivalentMaskless(unsigned CC, unsigned width,
8407 ISD::LoadExtType ExtType, signed AddConstant,
8408 signed CompConstant) {
8409 // By being careful about our equations and only writing the in term
8410 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8411 // make them generally applicable to all bit widths.
8412 signed MaxUInt = (1 << width);
8414 // For the purposes of these comparisons sign extending the type is
8415 // equivalent to zero extending the add and displacing it by half the integer
8416 // width. Provided we are careful and make sure our equations are valid over
8417 // the whole range we can just adjust the input and avoid writing equations
8418 // for sign extended inputs.
8419 if (ExtType == ISD::SEXTLOAD)
8420 AddConstant -= (1 << (width-1));
8424 case AArch64CC::GT: {
8425 if ((AddConstant == 0) ||
8426 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8427 (AddConstant >= 0 && CompConstant < 0) ||
8428 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8432 case AArch64CC::GE: {
8433 if ((AddConstant == 0) ||
8434 (AddConstant >= 0 && CompConstant <= 0) ||
8435 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8439 case AArch64CC::LS: {
8440 if ((AddConstant >= 0 && CompConstant < 0) ||
8441 (AddConstant <= 0 && CompConstant >= -1 &&
8442 CompConstant < AddConstant + MaxUInt))
8446 case AArch64CC::MI: {
8447 if ((AddConstant == 0) ||
8448 (AddConstant > 0 && CompConstant <= 0) ||
8449 (AddConstant < 0 && CompConstant <= AddConstant))
8453 case AArch64CC::HS: {
8454 if ((AddConstant >= 0 && CompConstant <= 0) ||
8455 (AddConstant <= 0 && CompConstant >= 0 &&
8456 CompConstant <= AddConstant + MaxUInt))
8460 case AArch64CC::NE: {
8461 if ((AddConstant > 0 && CompConstant < 0) ||
8462 (AddConstant < 0 && CompConstant >= 0 &&
8463 CompConstant < AddConstant + MaxUInt) ||
8464 (AddConstant >= 0 && CompConstant >= 0 &&
8465 CompConstant >= AddConstant) ||
8466 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8475 case AArch64CC::Invalid:
8483 SDValue performCONDCombine(SDNode *N,
8484 TargetLowering::DAGCombinerInfo &DCI,
8485 SelectionDAG &DAG, unsigned CCIndex,
8486 unsigned CmpIndex) {
8487 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8488 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8489 unsigned CondOpcode = SubsNode->getOpcode();
8491 if (CondOpcode != AArch64ISD::SUBS)
8494 // There is a SUBS feeding this condition. Is it fed by a mask we can
8497 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8498 unsigned MaskBits = 0;
8500 if (AndNode->getOpcode() != ISD::AND)
8503 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8504 uint32_t CNV = CN->getZExtValue();
8507 else if (CNV == 65535)
8514 SDValue AddValue = AndNode->getOperand(0);
8516 if (AddValue.getOpcode() != ISD::ADD)
8519 // The basic dag structure is correct, grab the inputs and validate them.
8521 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8522 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8523 SDValue SubsInputValue = SubsNode->getOperand(1);
8525 // The mask is present and the provenance of all the values is a smaller type,
8526 // lets see if the mask is superfluous.
8528 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8529 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8532 ISD::LoadExtType ExtType;
8534 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8535 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8536 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8539 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8540 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8541 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8544 // The AND is not necessary, remove it.
8546 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8547 SubsNode->getValueType(1));
8548 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8550 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8551 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8553 return SDValue(N, 0);
8556 // Optimize compare with zero and branch.
8557 static SDValue performBRCONDCombine(SDNode *N,
8558 TargetLowering::DAGCombinerInfo &DCI,
8559 SelectionDAG &DAG) {
8560 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8563 SDValue Chain = N->getOperand(0);
8564 SDValue Dest = N->getOperand(1);
8565 SDValue CCVal = N->getOperand(2);
8566 SDValue Cmp = N->getOperand(3);
8568 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8569 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8570 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8573 unsigned CmpOpc = Cmp.getOpcode();
8574 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8577 // Only attempt folding if there is only one use of the flag and no use of the
8579 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8582 SDValue LHS = Cmp.getOperand(0);
8583 SDValue RHS = Cmp.getOperand(1);
8585 assert(LHS.getValueType() == RHS.getValueType() &&
8586 "Expected the value type to be the same for both operands!");
8587 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8590 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8591 std::swap(LHS, RHS);
8593 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8596 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8597 LHS.getOpcode() == ISD::SRL)
8600 // Fold the compare into the branch instruction.
8602 if (CC == AArch64CC::EQ)
8603 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8605 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8607 // Do not add new nodes to DAG combiner worklist.
8608 DCI.CombineTo(N, BR, false);
8613 // vselect (v1i1 setcc) ->
8614 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8615 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8616 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8618 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8619 SDValue N0 = N->getOperand(0);
8620 EVT CCVT = N0.getValueType();
8622 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8623 CCVT.getVectorElementType() != MVT::i1)
8626 EVT ResVT = N->getValueType(0);
8627 EVT CmpVT = N0.getOperand(0).getValueType();
8628 // Only combine when the result type is of the same size as the compared
8630 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8633 SDValue IfTrue = N->getOperand(1);
8634 SDValue IfFalse = N->getOperand(2);
8636 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8637 N0.getOperand(0), N0.getOperand(1),
8638 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8639 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8643 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8644 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8645 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8646 /// with a vector one followed by a DUP shuffle on the result.
8647 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8648 SDValue N0 = N->getOperand(0);
8649 EVT ResVT = N->getValueType(0);
8651 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8654 // If NumMaskElts == 0, the comparison is larger than select result. The
8655 // largest real NEON comparison is 64-bits per lane, which means the result is
8656 // at most 32-bits and an illegal vector. Just bail out for now.
8657 EVT SrcVT = N0.getOperand(0).getValueType();
8659 // Don't try to do this optimization when the setcc itself has i1 operands.
8660 // There are no legal vectors of i1, so this would be pointless.
8661 if (SrcVT == MVT::i1)
8664 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8665 if (!ResVT.isVector() || NumMaskElts == 0)
8668 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8669 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8671 // Also bail out if the vector CCVT isn't the same size as ResVT.
8672 // This can happen if the SETCC operand size doesn't divide the ResVT size
8673 // (e.g., f64 vs v3f32).
8674 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
8677 // First perform a vector comparison, where lane 0 is the one we're interested
8681 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8683 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8684 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8686 // Now duplicate the comparison mask we want across all other lanes.
8687 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8688 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8689 Mask = DAG.getNode(ISD::BITCAST, DL,
8690 ResVT.changeVectorElementTypeToInteger(), Mask);
8692 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8695 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8696 DAGCombinerInfo &DCI) const {
8697 SelectionDAG &DAG = DCI.DAG;
8698 switch (N->getOpcode()) {
8703 return performAddSubLongCombine(N, DCI, DAG);
8705 return performXorCombine(N, DAG, DCI, Subtarget);
8707 return performMulCombine(N, DAG, DCI, Subtarget);
8708 case ISD::SINT_TO_FP:
8709 case ISD::UINT_TO_FP:
8710 return performIntToFpCombine(N, DAG, Subtarget);
8712 return performORCombine(N, DCI, Subtarget);
8713 case ISD::INTRINSIC_WO_CHAIN:
8714 return performIntrinsicCombine(N, DCI, Subtarget);
8715 case ISD::ANY_EXTEND:
8716 case ISD::ZERO_EXTEND:
8717 case ISD::SIGN_EXTEND:
8718 return performExtendCombine(N, DCI, DAG);
8720 return performBitcastCombine(N, DCI, DAG);
8721 case ISD::CONCAT_VECTORS:
8722 return performConcatVectorsCombine(N, DCI, DAG);
8724 return performSelectCombine(N, DAG);
8726 return performVSelectCombine(N, DCI.DAG);
8728 return performSTORECombine(N, DCI, DAG, Subtarget);
8729 case AArch64ISD::BRCOND:
8730 return performBRCONDCombine(N, DCI, DAG);
8731 case AArch64ISD::CSEL:
8732 return performCONDCombine(N, DCI, DAG, 2, 3);
8733 case AArch64ISD::DUP:
8734 return performPostLD1Combine(N, DCI, false);
8735 case ISD::INSERT_VECTOR_ELT:
8736 return performPostLD1Combine(N, DCI, true);
8737 case ISD::INTRINSIC_VOID:
8738 case ISD::INTRINSIC_W_CHAIN:
8739 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8740 case Intrinsic::aarch64_neon_ld2:
8741 case Intrinsic::aarch64_neon_ld3:
8742 case Intrinsic::aarch64_neon_ld4:
8743 case Intrinsic::aarch64_neon_ld1x2:
8744 case Intrinsic::aarch64_neon_ld1x3:
8745 case Intrinsic::aarch64_neon_ld1x4:
8746 case Intrinsic::aarch64_neon_ld2lane:
8747 case Intrinsic::aarch64_neon_ld3lane:
8748 case Intrinsic::aarch64_neon_ld4lane:
8749 case Intrinsic::aarch64_neon_ld2r:
8750 case Intrinsic::aarch64_neon_ld3r:
8751 case Intrinsic::aarch64_neon_ld4r:
8752 case Intrinsic::aarch64_neon_st2:
8753 case Intrinsic::aarch64_neon_st3:
8754 case Intrinsic::aarch64_neon_st4:
8755 case Intrinsic::aarch64_neon_st1x2:
8756 case Intrinsic::aarch64_neon_st1x3:
8757 case Intrinsic::aarch64_neon_st1x4:
8758 case Intrinsic::aarch64_neon_st2lane:
8759 case Intrinsic::aarch64_neon_st3lane:
8760 case Intrinsic::aarch64_neon_st4lane:
8761 return performNEONPostLDSTCombine(N, DCI, DAG);
8769 // Check if the return value is used as only a return value, as otherwise
8770 // we can't perform a tail-call. In particular, we need to check for
8771 // target ISD nodes that are returns and any other "odd" constructs
8772 // that the generic analysis code won't necessarily catch.
8773 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8774 SDValue &Chain) const {
8775 if (N->getNumValues() != 1)
8777 if (!N->hasNUsesOfValue(1, 0))
8780 SDValue TCChain = Chain;
8781 SDNode *Copy = *N->use_begin();
8782 if (Copy->getOpcode() == ISD::CopyToReg) {
8783 // If the copy has a glue operand, we conservatively assume it isn't safe to
8784 // perform a tail call.
8785 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8788 TCChain = Copy->getOperand(0);
8789 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8792 bool HasRet = false;
8793 for (SDNode *Node : Copy->uses()) {
8794 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8806 // Return whether the an instruction can potentially be optimized to a tail
8807 // call. This will cause the optimizers to attempt to move, or duplicate,
8808 // return instructions to help enable tail call optimizations for this
8810 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8811 if (!CI->isTailCall())
8817 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8819 ISD::MemIndexedMode &AM,
8821 SelectionDAG &DAG) const {
8822 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8825 Base = Op->getOperand(0);
8826 // All of the indexed addressing mode instructions take a signed
8827 // 9 bit immediate offset.
8828 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8829 int64_t RHSC = (int64_t)RHS->getZExtValue();
8830 if (RHSC >= 256 || RHSC <= -256)
8832 IsInc = (Op->getOpcode() == ISD::ADD);
8833 Offset = Op->getOperand(1);
8839 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8841 ISD::MemIndexedMode &AM,
8842 SelectionDAG &DAG) const {
8845 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8846 VT = LD->getMemoryVT();
8847 Ptr = LD->getBasePtr();
8848 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8849 VT = ST->getMemoryVT();
8850 Ptr = ST->getBasePtr();
8855 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8857 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8861 bool AArch64TargetLowering::getPostIndexedAddressParts(
8862 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8863 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8866 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8867 VT = LD->getMemoryVT();
8868 Ptr = LD->getBasePtr();
8869 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8870 VT = ST->getMemoryVT();
8871 Ptr = ST->getBasePtr();
8876 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8878 // Post-indexing updates the base, so it's not a valid transform
8879 // if that's not the same as the load's pointer.
8882 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8886 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8887 SelectionDAG &DAG) {
8889 SDValue Op = N->getOperand(0);
8891 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8895 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8896 DAG.getUNDEF(MVT::i32), Op,
8897 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8899 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8900 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8903 void AArch64TargetLowering::ReplaceNodeResults(
8904 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8905 switch (N->getOpcode()) {
8907 llvm_unreachable("Don't know how to custom expand this");
8909 ReplaceBITCASTResults(N, Results, DAG);
8911 case ISD::FP_TO_UINT:
8912 case ISD::FP_TO_SINT:
8913 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8914 // Let normal code take care of it by not adding anything to Results.
8919 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8923 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8924 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8925 // reciprocal if there are three or more FDIVs.
8926 return NumUsers > 2;
8929 TargetLoweringBase::LegalizeTypeAction
8930 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8931 MVT SVT = VT.getSimpleVT();
8932 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8933 // v4i16, v2i32 instead of to promote.
8934 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8935 || SVT == MVT::v1f32)
8936 return TypeWidenVector;
8938 return TargetLoweringBase::getPreferredVectorAction(VT);
8941 // Loads and stores less than 128-bits are already atomic; ones above that
8942 // are doomed anyway, so defer to the default libcall and blame the OS when
8944 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8945 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8949 // Loads and stores less than 128-bits are already atomic; ones above that
8950 // are doomed anyway, so defer to the default libcall and blame the OS when
8952 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8953 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8957 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8958 TargetLoweringBase::AtomicRMWExpansionKind
8959 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8960 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8961 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
8962 : AtomicRMWExpansionKind::None;
8965 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8969 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8970 AtomicOrdering Ord) const {
8971 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8972 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8973 bool IsAcquire = isAtLeastAcquire(Ord);
8975 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8976 // intrinsic must return {i64, i64} and we have to recombine them into a
8977 // single i128 here.
8978 if (ValTy->getPrimitiveSizeInBits() == 128) {
8980 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8981 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8983 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8984 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8986 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8987 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8988 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8989 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8990 return Builder.CreateOr(
8991 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8994 Type *Tys[] = { Addr->getType() };
8996 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8997 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8999 return Builder.CreateTruncOrBitCast(
9000 Builder.CreateCall(Ldxr, Addr),
9001 cast<PointerType>(Addr->getType())->getElementType());
9004 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9005 Value *Val, Value *Addr,
9006 AtomicOrdering Ord) const {
9007 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9008 bool IsRelease = isAtLeastRelease(Ord);
9010 // Since the intrinsics must have legal type, the i128 intrinsics take two
9011 // parameters: "i64, i64". We must marshal Val into the appropriate form
9013 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9015 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9016 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9017 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9019 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9020 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9021 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9022 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
9026 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9027 Type *Tys[] = { Addr->getType() };
9028 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9030 return Builder.CreateCall2(
9031 Stxr, Builder.CreateZExtOrBitCast(
9032 Val, Stxr->getFunctionType()->getParamType(0)),
9036 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9037 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9038 return Ty->isArrayTy();