1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/Support/MathExtras.h"
33 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
34 assert (TM.getSubtarget<AArch64Subtarget>().isTargetELF() &&
35 "unknown subtarget type");
36 return new AArch64ElfTargetObjectFile();
39 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
40 : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
42 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
44 // SIMD compares set the entire lane's bits to 1
45 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
47 // Scalar register <-> type mapping
48 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
49 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
51 if (Subtarget->hasFPARMv8()) {
52 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
53 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
54 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
55 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
58 if (Subtarget->hasNEON()) {
60 addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass);
61 addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass);
62 addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass);
63 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
64 addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
65 addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
66 addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
67 addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass);
68 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
69 addRegisterClass(MVT::v2f32, &AArch64::FPR64RegClass);
70 addRegisterClass(MVT::v16i8, &AArch64::FPR128RegClass);
71 addRegisterClass(MVT::v8i16, &AArch64::FPR128RegClass);
72 addRegisterClass(MVT::v4i32, &AArch64::FPR128RegClass);
73 addRegisterClass(MVT::v2i64, &AArch64::FPR128RegClass);
74 addRegisterClass(MVT::v4f32, &AArch64::FPR128RegClass);
75 addRegisterClass(MVT::v2f64, &AArch64::FPR128RegClass);
78 computeRegisterProperties();
80 // We combine OR nodes for bitfield and NEON BSL operations.
81 setTargetDAGCombine(ISD::OR);
83 setTargetDAGCombine(ISD::AND);
84 setTargetDAGCombine(ISD::SRA);
85 setTargetDAGCombine(ISD::SRL);
86 setTargetDAGCombine(ISD::SHL);
88 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
89 setTargetDAGCombine(ISD::INTRINSIC_VOID);
90 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
92 // AArch64 does not have i1 loads, or much of anything for i1 really.
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
95 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
97 setStackPointerRegisterToSaveRestore(AArch64::XSP);
98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
99 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
100 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
102 // We'll lower globals to wrappers for selection.
103 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
104 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
106 // A64 instructions have the comparison predicate attached to the user of the
107 // result, but having a separate comparison is valuable for matching.
108 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
109 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
110 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
111 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
113 setOperationAction(ISD::SELECT, MVT::i32, Custom);
114 setOperationAction(ISD::SELECT, MVT::i64, Custom);
115 setOperationAction(ISD::SELECT, MVT::f32, Custom);
116 setOperationAction(ISD::SELECT, MVT::f64, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
121 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
123 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
125 setOperationAction(ISD::SETCC, MVT::i32, Custom);
126 setOperationAction(ISD::SETCC, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::f32, Custom);
128 setOperationAction(ISD::SETCC, MVT::f64, Custom);
130 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
131 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::VASTART, MVT::Other, Custom);
135 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
136 setOperationAction(ISD::VAEND, MVT::Other, Expand);
137 setOperationAction(ISD::VAARG, MVT::Other, Expand);
139 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
140 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
142 setOperationAction(ISD::ROTL, MVT::i32, Expand);
143 setOperationAction(ISD::ROTL, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i32, Expand);
146 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
148 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
150 setOperationAction(ISD::SREM, MVT::i32, Expand);
151 setOperationAction(ISD::SREM, MVT::i64, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
160 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
161 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
163 // Legal floating-point operations.
164 setOperationAction(ISD::FABS, MVT::f32, Legal);
165 setOperationAction(ISD::FABS, MVT::f64, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
170 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
171 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
173 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
174 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
176 setOperationAction(ISD::FNEG, MVT::f32, Legal);
177 setOperationAction(ISD::FNEG, MVT::f64, Legal);
179 setOperationAction(ISD::FRINT, MVT::f32, Legal);
180 setOperationAction(ISD::FRINT, MVT::f64, Legal);
182 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
183 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
185 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
186 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
188 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
189 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
190 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
192 // Illegal floating-point operations.
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
196 setOperationAction(ISD::FCOS, MVT::f32, Expand);
197 setOperationAction(ISD::FCOS, MVT::f64, Expand);
199 setOperationAction(ISD::FEXP, MVT::f32, Expand);
200 setOperationAction(ISD::FEXP, MVT::f64, Expand);
202 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
203 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
205 setOperationAction(ISD::FLOG, MVT::f32, Expand);
206 setOperationAction(ISD::FLOG, MVT::f64, Expand);
208 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
209 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
211 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
212 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
214 setOperationAction(ISD::FPOW, MVT::f32, Expand);
215 setOperationAction(ISD::FPOW, MVT::f64, Expand);
217 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
218 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
220 setOperationAction(ISD::FREM, MVT::f32, Expand);
221 setOperationAction(ISD::FREM, MVT::f64, Expand);
223 setOperationAction(ISD::FSIN, MVT::f32, Expand);
224 setOperationAction(ISD::FSIN, MVT::f64, Expand);
226 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
227 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
229 // Virtually no operation on f128 is legal, but LLVM can't expand them when
230 // there's a valid register class, so we need custom operations in most cases.
231 setOperationAction(ISD::FABS, MVT::f128, Expand);
232 setOperationAction(ISD::FADD, MVT::f128, Custom);
233 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
234 setOperationAction(ISD::FCOS, MVT::f128, Expand);
235 setOperationAction(ISD::FDIV, MVT::f128, Custom);
236 setOperationAction(ISD::FMA, MVT::f128, Expand);
237 setOperationAction(ISD::FMUL, MVT::f128, Custom);
238 setOperationAction(ISD::FNEG, MVT::f128, Expand);
239 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
240 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
241 setOperationAction(ISD::FPOW, MVT::f128, Expand);
242 setOperationAction(ISD::FREM, MVT::f128, Expand);
243 setOperationAction(ISD::FRINT, MVT::f128, Expand);
244 setOperationAction(ISD::FSIN, MVT::f128, Expand);
245 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
246 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
247 setOperationAction(ISD::FSUB, MVT::f128, Custom);
248 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
249 setOperationAction(ISD::SETCC, MVT::f128, Custom);
250 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
251 setOperationAction(ISD::SELECT, MVT::f128, Expand);
252 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
253 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
255 // Lowering for many of the conversions is actually specified by the non-f128
256 // type. The LowerXXX function will be trivial when f128 isn't involved.
257 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
259 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
260 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
261 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
262 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
263 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
265 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
266 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
267 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
268 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
269 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
270 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
272 // This prevents LLVM trying to compress double constants into a floating
273 // constant-pool entry and trying to load from there. It's of doubtful benefit
274 // for A64: we'd need LDR followed by FCVT, I believe.
275 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
276 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
277 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
279 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
280 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
281 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
282 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
283 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
284 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
286 setExceptionPointerRegister(AArch64::X0);
287 setExceptionSelectorRegister(AArch64::X1);
289 if (Subtarget->hasNEON()) {
290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Expand);
291 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
292 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
293 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v1i64, Expand);
294 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v16i8, Expand);
295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Expand);
296 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
297 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Expand);
299 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i8, Custom);
300 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
301 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
302 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i16, Custom);
303 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
304 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
305 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i32, Custom);
306 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
307 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
308 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
309 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
310 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
311 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v1f64, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
315 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
316 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
317 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
318 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
319 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
320 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
321 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
322 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
323 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom);
324 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
325 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom);
326 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32, Legal);
329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal);
330 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
332 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
333 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal);
334 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal);
336 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i8, Custom);
337 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i16, Custom);
338 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
339 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
340 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
342 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
343 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
344 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
345 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
346 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
347 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
348 setOperationAction(ISD::SETCC, MVT::v1i64, Custom);
349 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
350 setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
351 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
352 setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
353 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
355 setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
356 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
357 setOperationAction(ISD::FFLOOR, MVT::v1f64, Legal);
358 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
360 setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
361 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
362 setOperationAction(ISD::FCEIL, MVT::v1f64, Legal);
363 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
365 setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
366 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
367 setOperationAction(ISD::FTRUNC, MVT::v1f64, Legal);
368 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
370 setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
371 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
372 setOperationAction(ISD::FRINT, MVT::v1f64, Legal);
373 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
375 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal);
376 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
377 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Legal);
378 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
380 setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
381 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
382 setOperationAction(ISD::FROUND, MVT::v1f64, Legal);
383 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
385 setOperationAction(ISD::SINT_TO_FP, MVT::v1i8, Custom);
386 setOperationAction(ISD::SINT_TO_FP, MVT::v1i16, Custom);
387 setOperationAction(ISD::SINT_TO_FP, MVT::v1i32, Custom);
388 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
389 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
390 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
392 setOperationAction(ISD::UINT_TO_FP, MVT::v1i8, Custom);
393 setOperationAction(ISD::UINT_TO_FP, MVT::v1i16, Custom);
394 setOperationAction(ISD::UINT_TO_FP, MVT::v1i32, Custom);
395 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
396 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
397 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
399 setOperationAction(ISD::FP_TO_SINT, MVT::v1i8, Custom);
400 setOperationAction(ISD::FP_TO_SINT, MVT::v1i16, Custom);
401 setOperationAction(ISD::FP_TO_SINT, MVT::v1i32, Custom);
402 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
403 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
404 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Custom);
406 setOperationAction(ISD::FP_TO_UINT, MVT::v1i8, Custom);
407 setOperationAction(ISD::FP_TO_UINT, MVT::v1i16, Custom);
408 setOperationAction(ISD::FP_TO_UINT, MVT::v1i32, Custom);
409 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
410 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
411 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Custom);
413 // Neon does not support vector divide/remainder operations except
414 // floating-point divide.
415 setOperationAction(ISD::SDIV, MVT::v1i8, Expand);
416 setOperationAction(ISD::SDIV, MVT::v8i8, Expand);
417 setOperationAction(ISD::SDIV, MVT::v16i8, Expand);
418 setOperationAction(ISD::SDIV, MVT::v1i16, Expand);
419 setOperationAction(ISD::SDIV, MVT::v4i16, Expand);
420 setOperationAction(ISD::SDIV, MVT::v8i16, Expand);
421 setOperationAction(ISD::SDIV, MVT::v1i32, Expand);
422 setOperationAction(ISD::SDIV, MVT::v2i32, Expand);
423 setOperationAction(ISD::SDIV, MVT::v4i32, Expand);
424 setOperationAction(ISD::SDIV, MVT::v1i64, Expand);
425 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
427 setOperationAction(ISD::UDIV, MVT::v1i8, Expand);
428 setOperationAction(ISD::UDIV, MVT::v8i8, Expand);
429 setOperationAction(ISD::UDIV, MVT::v16i8, Expand);
430 setOperationAction(ISD::UDIV, MVT::v1i16, Expand);
431 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
432 setOperationAction(ISD::UDIV, MVT::v8i16, Expand);
433 setOperationAction(ISD::UDIV, MVT::v1i32, Expand);
434 setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
435 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
436 setOperationAction(ISD::UDIV, MVT::v1i64, Expand);
437 setOperationAction(ISD::UDIV, MVT::v2i64, Expand);
439 setOperationAction(ISD::SREM, MVT::v1i8, Expand);
440 setOperationAction(ISD::SREM, MVT::v8i8, Expand);
441 setOperationAction(ISD::SREM, MVT::v16i8, Expand);
442 setOperationAction(ISD::SREM, MVT::v1i16, Expand);
443 setOperationAction(ISD::SREM, MVT::v4i16, Expand);
444 setOperationAction(ISD::SREM, MVT::v8i16, Expand);
445 setOperationAction(ISD::SREM, MVT::v1i32, Expand);
446 setOperationAction(ISD::SREM, MVT::v2i32, Expand);
447 setOperationAction(ISD::SREM, MVT::v4i32, Expand);
448 setOperationAction(ISD::SREM, MVT::v1i64, Expand);
449 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
451 setOperationAction(ISD::UREM, MVT::v1i8, Expand);
452 setOperationAction(ISD::UREM, MVT::v8i8, Expand);
453 setOperationAction(ISD::UREM, MVT::v16i8, Expand);
454 setOperationAction(ISD::UREM, MVT::v1i16, Expand);
455 setOperationAction(ISD::UREM, MVT::v4i16, Expand);
456 setOperationAction(ISD::UREM, MVT::v8i16, Expand);
457 setOperationAction(ISD::UREM, MVT::v1i32, Expand);
458 setOperationAction(ISD::UREM, MVT::v2i32, Expand);
459 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
460 setOperationAction(ISD::UREM, MVT::v1i64, Expand);
461 setOperationAction(ISD::UREM, MVT::v2i64, Expand);
463 setOperationAction(ISD::FREM, MVT::v2f32, Expand);
464 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
465 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
466 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
468 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
469 setOperationAction(ISD::SELECT, MVT::v16i8, Expand);
470 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
471 setOperationAction(ISD::SELECT, MVT::v8i16, Expand);
472 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
473 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
474 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
475 setOperationAction(ISD::SELECT, MVT::v2i64, Expand);
476 setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
477 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
478 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
479 setOperationAction(ISD::SELECT, MVT::v2f64, Expand);
481 setOperationAction(ISD::SELECT_CC, MVT::v8i8, Custom);
482 setOperationAction(ISD::SELECT_CC, MVT::v16i8, Custom);
483 setOperationAction(ISD::SELECT_CC, MVT::v4i16, Custom);
484 setOperationAction(ISD::SELECT_CC, MVT::v8i16, Custom);
485 setOperationAction(ISD::SELECT_CC, MVT::v2i32, Custom);
486 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Custom);
487 setOperationAction(ISD::SELECT_CC, MVT::v1i64, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::v2i64, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::v2f32, Custom);
490 setOperationAction(ISD::SELECT_CC, MVT::v4f32, Custom);
491 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Custom);
492 setOperationAction(ISD::SELECT_CC, MVT::v2f64, Custom);
494 // Vector ExtLoad and TruncStore are expanded.
495 for (unsigned I = MVT::FIRST_VECTOR_VALUETYPE;
496 I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
497 MVT VT = (MVT::SimpleValueType) I;
498 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
499 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
500 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
501 for (unsigned II = MVT::FIRST_VECTOR_VALUETYPE;
502 II <= MVT::LAST_VECTOR_VALUETYPE; ++II) {
503 MVT VT1 = (MVT::SimpleValueType) II;
504 // A TruncStore has two vector types of the same number of elements
505 // and different element sizes.
506 if (VT.getVectorNumElements() == VT1.getVectorNumElements() &&
507 VT.getVectorElementType().getSizeInBits()
508 > VT1.getVectorElementType().getSizeInBits())
509 setTruncStoreAction(VT, VT1, Expand);
513 // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
514 // FIXME: For a v2i64 multiply, we copy VPR to GPR and do 2 i64 multiplies,
515 // and then copy back to VPR. This solution may be optimized by Following 3
516 // NEON instructions:
517 // pmull v2.1q, v0.1d, v1.1d
518 // pmull2 v3.1q, v0.2d, v1.2d
519 // ins v2.d[1], v3.d[0]
520 // As currently we can't verify the correctness of such assumption, we can
521 // do such optimization in the future.
522 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
523 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
525 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
526 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
527 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
528 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
529 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
530 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
531 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
532 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
533 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
536 setTargetDAGCombine(ISD::SETCC);
537 setTargetDAGCombine(ISD::SIGN_EXTEND);
538 setTargetDAGCombine(ISD::VSELECT);
541 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
542 // It's reasonably important that this value matches the "natural" legal
543 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
544 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
545 if (!VT.isVector()) return MVT::i32;
546 return VT.changeVectorElementTypeToInteger();
549 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
552 static const unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
553 AArch64::LDXR_word, AArch64::LDXR_dword};
554 static const unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
555 AArch64::LDAXR_word, AArch64::LDAXR_dword};
556 static const unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
557 AArch64::STXR_word, AArch64::STXR_dword};
558 static const unsigned StoreRels[] = {AArch64::STLXR_byte,AArch64::STLXR_hword,
559 AArch64::STLXR_word, AArch64::STLXR_dword};
561 const unsigned *LoadOps, *StoreOps;
562 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
567 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
568 StoreOps = StoreRels;
570 StoreOps = StoreBares;
572 assert(isPowerOf2_32(Size) && Size <= 8 &&
573 "unsupported size for atomic binary op!");
575 LdrOpc = LoadOps[Log2_32(Size)];
576 StrOpc = StoreOps[Log2_32(Size)];
579 // FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really
580 // have value type mapped, and they are both being defined as MVT::untyped.
581 // Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost
582 // would fail to figure out the register pressure correctly.
583 std::pair<const TargetRegisterClass*, uint8_t>
584 AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
585 const TargetRegisterClass *RRC = 0;
587 switch (VT.SimpleTy) {
589 return TargetLowering::findRepresentativeClass(VT);
591 RRC = &AArch64::QPairRegClass;
595 RRC = &AArch64::QQuadRegClass;
599 return std::make_pair(RRC, Cost);
603 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
605 unsigned BinOpcode) const {
606 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
607 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
609 const BasicBlock *LLVM_BB = BB->getBasicBlock();
610 MachineFunction *MF = BB->getParent();
611 MachineFunction::iterator It = BB;
614 unsigned dest = MI->getOperand(0).getReg();
615 unsigned ptr = MI->getOperand(1).getReg();
616 unsigned incr = MI->getOperand(2).getReg();
617 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
618 DebugLoc dl = MI->getDebugLoc();
620 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
622 unsigned ldrOpc, strOpc;
623 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
625 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
626 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
627 MF->insert(It, loopMBB);
628 MF->insert(It, exitMBB);
630 // Transfer the remainder of BB and its successor edges to exitMBB.
631 exitMBB->splice(exitMBB->begin(), BB,
632 std::next(MachineBasicBlock::iterator(MI)), BB->end());
633 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
635 const TargetRegisterClass *TRC
636 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
637 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
641 // fallthrough --> loopMBB
642 BB->addSuccessor(loopMBB);
646 // <binop> scratch, dest, incr
647 // stxr stxr_status, scratch, ptr
648 // cbnz stxr_status, loopMBB
649 // fallthrough --> exitMBB
651 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
653 // All arithmetic operations we'll be creating are designed to take an extra
654 // shift or extend operand, which we can conveniently set to zero.
656 // Operand order needs to go the other way for NAND.
657 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
658 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
659 .addReg(incr).addReg(dest).addImm(0);
661 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
662 .addReg(dest).addReg(incr).addImm(0);
665 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
666 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
667 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
669 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
670 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
671 .addReg(stxr_status).addMBB(loopMBB);
673 BB->addSuccessor(loopMBB);
674 BB->addSuccessor(exitMBB);
680 MI->eraseFromParent(); // The instruction is gone now.
686 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
687 MachineBasicBlock *BB,
690 A64CC::CondCodes Cond) const {
691 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
693 const BasicBlock *LLVM_BB = BB->getBasicBlock();
694 MachineFunction *MF = BB->getParent();
695 MachineFunction::iterator It = BB;
698 unsigned dest = MI->getOperand(0).getReg();
699 unsigned ptr = MI->getOperand(1).getReg();
700 unsigned incr = MI->getOperand(2).getReg();
701 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
703 unsigned oldval = dest;
704 DebugLoc dl = MI->getDebugLoc();
706 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
707 const TargetRegisterClass *TRC, *TRCsp;
709 TRC = &AArch64::GPR64RegClass;
710 TRCsp = &AArch64::GPR64xspRegClass;
712 TRC = &AArch64::GPR32RegClass;
713 TRCsp = &AArch64::GPR32wspRegClass;
716 unsigned ldrOpc, strOpc;
717 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
719 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
720 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
721 MF->insert(It, loopMBB);
722 MF->insert(It, exitMBB);
724 // Transfer the remainder of BB and its successor edges to exitMBB.
725 exitMBB->splice(exitMBB->begin(), BB,
726 std::next(MachineBasicBlock::iterator(MI)), BB->end());
727 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
729 unsigned scratch = MRI.createVirtualRegister(TRC);
730 MRI.constrainRegClass(scratch, TRCsp);
734 // fallthrough --> loopMBB
735 BB->addSuccessor(loopMBB);
739 // cmp incr, dest (, sign extend if necessary)
740 // csel scratch, dest, incr, cond
741 // stxr stxr_status, scratch, ptr
742 // cbnz stxr_status, loopMBB
743 // fallthrough --> exitMBB
745 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
747 // Build compare and cmov instructions.
748 MRI.constrainRegClass(incr, TRCsp);
749 BuildMI(BB, dl, TII->get(CmpOp))
750 .addReg(incr).addReg(oldval).addImm(0);
752 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
754 .addReg(oldval).addReg(incr).addImm(Cond);
756 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
757 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
759 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
760 .addReg(scratch).addReg(ptr);
761 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
762 .addReg(stxr_status).addMBB(loopMBB);
764 BB->addSuccessor(loopMBB);
765 BB->addSuccessor(exitMBB);
771 MI->eraseFromParent(); // The instruction is gone now.
777 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
778 MachineBasicBlock *BB,
779 unsigned Size) const {
780 unsigned dest = MI->getOperand(0).getReg();
781 unsigned ptr = MI->getOperand(1).getReg();
782 unsigned oldval = MI->getOperand(2).getReg();
783 unsigned newval = MI->getOperand(3).getReg();
784 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
785 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
786 DebugLoc dl = MI->getDebugLoc();
788 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
789 const TargetRegisterClass *TRCsp;
790 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
792 unsigned ldrOpc, strOpc;
793 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
795 MachineFunction *MF = BB->getParent();
796 const BasicBlock *LLVM_BB = BB->getBasicBlock();
797 MachineFunction::iterator It = BB;
798 ++It; // insert the new blocks after the current block
800 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
801 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
802 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
803 MF->insert(It, loop1MBB);
804 MF->insert(It, loop2MBB);
805 MF->insert(It, exitMBB);
807 // Transfer the remainder of BB and its successor edges to exitMBB.
808 exitMBB->splice(exitMBB->begin(), BB,
809 std::next(MachineBasicBlock::iterator(MI)), BB->end());
810 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
814 // fallthrough --> loop1MBB
815 BB->addSuccessor(loop1MBB);
822 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
824 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
825 MRI.constrainRegClass(dest, TRCsp);
826 BuildMI(BB, dl, TII->get(CmpOp))
827 .addReg(dest).addReg(oldval).addImm(0);
828 BuildMI(BB, dl, TII->get(AArch64::Bcc))
829 .addImm(A64CC::NE).addMBB(exitMBB);
830 BB->addSuccessor(loop2MBB);
831 BB->addSuccessor(exitMBB);
834 // strex stxr_status, newval, [ptr]
835 // cbnz stxr_status, loop1MBB
837 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
838 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
840 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
841 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
842 .addReg(stxr_status).addMBB(loop1MBB);
843 BB->addSuccessor(loop1MBB);
844 BB->addSuccessor(exitMBB);
850 MI->eraseFromParent(); // The instruction is gone now.
856 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
857 MachineBasicBlock *MBB) const {
858 // We materialise the F128CSEL pseudo-instruction using conditional branches
859 // and loads, giving an instruciton sequence like:
868 // Using virtual registers would probably not be beneficial since COPY
869 // instructions are expensive for f128 (there's no actual instruction to
872 // An alternative would be to do an integer-CSEL on some address. E.g.:
877 // csel x0, x0, x1, ne
880 // It's unclear which approach is actually optimal.
881 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
882 MachineFunction *MF = MBB->getParent();
883 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
884 DebugLoc DL = MI->getDebugLoc();
885 MachineFunction::iterator It = MBB;
888 unsigned DestReg = MI->getOperand(0).getReg();
889 unsigned IfTrueReg = MI->getOperand(1).getReg();
890 unsigned IfFalseReg = MI->getOperand(2).getReg();
891 unsigned CondCode = MI->getOperand(3).getImm();
892 bool NZCVKilled = MI->getOperand(4).isKill();
894 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
895 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
896 MF->insert(It, TrueBB);
897 MF->insert(It, EndBB);
899 // Transfer rest of current basic-block to EndBB
900 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
902 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
904 // We need somewhere to store the f128 value needed.
905 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
907 // [... start of incoming MBB ...]
908 // str qIFFALSE, [sp]
911 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
913 .addFrameIndex(ScratchFI)
915 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
918 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
920 MBB->addSuccessor(TrueBB);
921 MBB->addSuccessor(EndBB);
924 // NZCV is live-through TrueBB.
925 TrueBB->addLiveIn(AArch64::NZCV);
926 EndBB->addLiveIn(AArch64::NZCV);
931 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
933 .addFrameIndex(ScratchFI)
936 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
938 TrueBB->addSuccessor(EndBB);
942 // [... rest of incoming MBB ...]
943 MachineInstr *StartOfEnd = EndBB->begin();
944 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
945 .addFrameIndex(ScratchFI)
948 MI->eraseFromParent();
953 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
954 MachineBasicBlock *MBB) const {
955 switch (MI->getOpcode()) {
956 default: llvm_unreachable("Unhandled instruction with custom inserter");
957 case AArch64::F128CSEL:
958 return EmitF128CSEL(MI, MBB);
959 case AArch64::ATOMIC_LOAD_ADD_I8:
960 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
961 case AArch64::ATOMIC_LOAD_ADD_I16:
962 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
963 case AArch64::ATOMIC_LOAD_ADD_I32:
964 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
965 case AArch64::ATOMIC_LOAD_ADD_I64:
966 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
968 case AArch64::ATOMIC_LOAD_SUB_I8:
969 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
970 case AArch64::ATOMIC_LOAD_SUB_I16:
971 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
972 case AArch64::ATOMIC_LOAD_SUB_I32:
973 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
974 case AArch64::ATOMIC_LOAD_SUB_I64:
975 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
977 case AArch64::ATOMIC_LOAD_AND_I8:
978 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
979 case AArch64::ATOMIC_LOAD_AND_I16:
980 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
981 case AArch64::ATOMIC_LOAD_AND_I32:
982 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
983 case AArch64::ATOMIC_LOAD_AND_I64:
984 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
986 case AArch64::ATOMIC_LOAD_OR_I8:
987 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
988 case AArch64::ATOMIC_LOAD_OR_I16:
989 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
990 case AArch64::ATOMIC_LOAD_OR_I32:
991 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
992 case AArch64::ATOMIC_LOAD_OR_I64:
993 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
995 case AArch64::ATOMIC_LOAD_XOR_I8:
996 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
997 case AArch64::ATOMIC_LOAD_XOR_I16:
998 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
999 case AArch64::ATOMIC_LOAD_XOR_I32:
1000 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
1001 case AArch64::ATOMIC_LOAD_XOR_I64:
1002 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
1004 case AArch64::ATOMIC_LOAD_NAND_I8:
1005 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
1006 case AArch64::ATOMIC_LOAD_NAND_I16:
1007 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
1008 case AArch64::ATOMIC_LOAD_NAND_I32:
1009 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
1010 case AArch64::ATOMIC_LOAD_NAND_I64:
1011 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
1013 case AArch64::ATOMIC_LOAD_MIN_I8:
1014 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
1015 case AArch64::ATOMIC_LOAD_MIN_I16:
1016 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
1017 case AArch64::ATOMIC_LOAD_MIN_I32:
1018 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
1019 case AArch64::ATOMIC_LOAD_MIN_I64:
1020 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
1022 case AArch64::ATOMIC_LOAD_MAX_I8:
1023 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
1024 case AArch64::ATOMIC_LOAD_MAX_I16:
1025 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
1026 case AArch64::ATOMIC_LOAD_MAX_I32:
1027 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
1028 case AArch64::ATOMIC_LOAD_MAX_I64:
1029 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
1031 case AArch64::ATOMIC_LOAD_UMIN_I8:
1032 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
1033 case AArch64::ATOMIC_LOAD_UMIN_I16:
1034 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
1035 case AArch64::ATOMIC_LOAD_UMIN_I32:
1036 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
1037 case AArch64::ATOMIC_LOAD_UMIN_I64:
1038 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
1040 case AArch64::ATOMIC_LOAD_UMAX_I8:
1041 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
1042 case AArch64::ATOMIC_LOAD_UMAX_I16:
1043 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
1044 case AArch64::ATOMIC_LOAD_UMAX_I32:
1045 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
1046 case AArch64::ATOMIC_LOAD_UMAX_I64:
1047 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
1049 case AArch64::ATOMIC_SWAP_I8:
1050 return emitAtomicBinary(MI, MBB, 1, 0);
1051 case AArch64::ATOMIC_SWAP_I16:
1052 return emitAtomicBinary(MI, MBB, 2, 0);
1053 case AArch64::ATOMIC_SWAP_I32:
1054 return emitAtomicBinary(MI, MBB, 4, 0);
1055 case AArch64::ATOMIC_SWAP_I64:
1056 return emitAtomicBinary(MI, MBB, 8, 0);
1058 case AArch64::ATOMIC_CMP_SWAP_I8:
1059 return emitAtomicCmpSwap(MI, MBB, 1);
1060 case AArch64::ATOMIC_CMP_SWAP_I16:
1061 return emitAtomicCmpSwap(MI, MBB, 2);
1062 case AArch64::ATOMIC_CMP_SWAP_I32:
1063 return emitAtomicCmpSwap(MI, MBB, 4);
1064 case AArch64::ATOMIC_CMP_SWAP_I64:
1065 return emitAtomicCmpSwap(MI, MBB, 8);
1070 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
1072 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
1073 case AArch64ISD::Call: return "AArch64ISD::Call";
1074 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
1075 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
1076 case AArch64ISD::BFI: return "AArch64ISD::BFI";
1077 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
1078 case AArch64ISD::Ret: return "AArch64ISD::Ret";
1079 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
1080 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
1081 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
1082 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
1083 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
1084 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
1085 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
1086 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
1088 case AArch64ISD::NEON_MOVIMM:
1089 return "AArch64ISD::NEON_MOVIMM";
1090 case AArch64ISD::NEON_MVNIMM:
1091 return "AArch64ISD::NEON_MVNIMM";
1092 case AArch64ISD::NEON_FMOVIMM:
1093 return "AArch64ISD::NEON_FMOVIMM";
1094 case AArch64ISD::NEON_CMP:
1095 return "AArch64ISD::NEON_CMP";
1096 case AArch64ISD::NEON_CMPZ:
1097 return "AArch64ISD::NEON_CMPZ";
1098 case AArch64ISD::NEON_TST:
1099 return "AArch64ISD::NEON_TST";
1100 case AArch64ISD::NEON_QSHLs:
1101 return "AArch64ISD::NEON_QSHLs";
1102 case AArch64ISD::NEON_QSHLu:
1103 return "AArch64ISD::NEON_QSHLu";
1104 case AArch64ISD::NEON_VDUP:
1105 return "AArch64ISD::NEON_VDUP";
1106 case AArch64ISD::NEON_VDUPLANE:
1107 return "AArch64ISD::NEON_VDUPLANE";
1108 case AArch64ISD::NEON_REV16:
1109 return "AArch64ISD::NEON_REV16";
1110 case AArch64ISD::NEON_REV32:
1111 return "AArch64ISD::NEON_REV32";
1112 case AArch64ISD::NEON_REV64:
1113 return "AArch64ISD::NEON_REV64";
1114 case AArch64ISD::NEON_UZP1:
1115 return "AArch64ISD::NEON_UZP1";
1116 case AArch64ISD::NEON_UZP2:
1117 return "AArch64ISD::NEON_UZP2";
1118 case AArch64ISD::NEON_ZIP1:
1119 return "AArch64ISD::NEON_ZIP1";
1120 case AArch64ISD::NEON_ZIP2:
1121 return "AArch64ISD::NEON_ZIP2";
1122 case AArch64ISD::NEON_TRN1:
1123 return "AArch64ISD::NEON_TRN1";
1124 case AArch64ISD::NEON_TRN2:
1125 return "AArch64ISD::NEON_TRN2";
1126 case AArch64ISD::NEON_LD1_UPD:
1127 return "AArch64ISD::NEON_LD1_UPD";
1128 case AArch64ISD::NEON_LD2_UPD:
1129 return "AArch64ISD::NEON_LD2_UPD";
1130 case AArch64ISD::NEON_LD3_UPD:
1131 return "AArch64ISD::NEON_LD3_UPD";
1132 case AArch64ISD::NEON_LD4_UPD:
1133 return "AArch64ISD::NEON_LD4_UPD";
1134 case AArch64ISD::NEON_ST1_UPD:
1135 return "AArch64ISD::NEON_ST1_UPD";
1136 case AArch64ISD::NEON_ST2_UPD:
1137 return "AArch64ISD::NEON_ST2_UPD";
1138 case AArch64ISD::NEON_ST3_UPD:
1139 return "AArch64ISD::NEON_ST3_UPD";
1140 case AArch64ISD::NEON_ST4_UPD:
1141 return "AArch64ISD::NEON_ST4_UPD";
1142 case AArch64ISD::NEON_LD1x2_UPD:
1143 return "AArch64ISD::NEON_LD1x2_UPD";
1144 case AArch64ISD::NEON_LD1x3_UPD:
1145 return "AArch64ISD::NEON_LD1x3_UPD";
1146 case AArch64ISD::NEON_LD1x4_UPD:
1147 return "AArch64ISD::NEON_LD1x4_UPD";
1148 case AArch64ISD::NEON_ST1x2_UPD:
1149 return "AArch64ISD::NEON_ST1x2_UPD";
1150 case AArch64ISD::NEON_ST1x3_UPD:
1151 return "AArch64ISD::NEON_ST1x3_UPD";
1152 case AArch64ISD::NEON_ST1x4_UPD:
1153 return "AArch64ISD::NEON_ST1x4_UPD";
1154 case AArch64ISD::NEON_LD2DUP:
1155 return "AArch64ISD::NEON_LD2DUP";
1156 case AArch64ISD::NEON_LD3DUP:
1157 return "AArch64ISD::NEON_LD3DUP";
1158 case AArch64ISD::NEON_LD4DUP:
1159 return "AArch64ISD::NEON_LD4DUP";
1160 case AArch64ISD::NEON_LD2DUP_UPD:
1161 return "AArch64ISD::NEON_LD2DUP_UPD";
1162 case AArch64ISD::NEON_LD3DUP_UPD:
1163 return "AArch64ISD::NEON_LD3DUP_UPD";
1164 case AArch64ISD::NEON_LD4DUP_UPD:
1165 return "AArch64ISD::NEON_LD4DUP_UPD";
1166 case AArch64ISD::NEON_LD2LN_UPD:
1167 return "AArch64ISD::NEON_LD2LN_UPD";
1168 case AArch64ISD::NEON_LD3LN_UPD:
1169 return "AArch64ISD::NEON_LD3LN_UPD";
1170 case AArch64ISD::NEON_LD4LN_UPD:
1171 return "AArch64ISD::NEON_LD4LN_UPD";
1172 case AArch64ISD::NEON_ST2LN_UPD:
1173 return "AArch64ISD::NEON_ST2LN_UPD";
1174 case AArch64ISD::NEON_ST3LN_UPD:
1175 return "AArch64ISD::NEON_ST3LN_UPD";
1176 case AArch64ISD::NEON_ST4LN_UPD:
1177 return "AArch64ISD::NEON_ST4LN_UPD";
1178 case AArch64ISD::NEON_VEXTRACT:
1179 return "AArch64ISD::NEON_VEXTRACT";
1185 static const uint16_t AArch64FPRArgRegs[] = {
1186 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1187 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1189 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
1191 static const uint16_t AArch64ArgRegs[] = {
1192 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
1193 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1195 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
1197 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
1198 CCValAssign::LocInfo LocInfo,
1199 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1200 // Mark all remaining general purpose registers as allocated. We don't
1201 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
1202 // i64 will go in registers (C.11).
1203 for (unsigned i = 0; i < NumArgRegs; ++i)
1204 State.AllocateReg(AArch64ArgRegs[i]);
1209 #include "AArch64GenCallingConv.inc"
1211 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1214 default: llvm_unreachable("Unsupported calling convention");
1215 case CallingConv::Fast:
1216 case CallingConv::C:
1222 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
1223 SDLoc DL, SDValue &Chain) const {
1224 MachineFunction &MF = DAG.getMachineFunction();
1225 MachineFrameInfo *MFI = MF.getFrameInfo();
1226 AArch64MachineFunctionInfo *FuncInfo
1227 = MF.getInfo<AArch64MachineFunctionInfo>();
1229 SmallVector<SDValue, 8> MemOps;
1231 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
1233 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
1236 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
1238 if (GPRSaveSize != 0) {
1239 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1241 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1243 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
1244 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
1245 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1246 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1247 MachinePointerInfo::getStack(i * 8),
1249 MemOps.push_back(Store);
1250 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1251 DAG.getConstant(8, getPointerTy()));
1255 if (getSubtarget()->hasFPARMv8()) {
1256 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1258 // According to the AArch64 Procedure Call Standard, section B.1/B.3, we
1259 // can omit a register save area if we know we'll never use registers of
1261 if (FPRSaveSize != 0) {
1262 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1264 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1266 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1267 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
1268 &AArch64::FPR128RegClass);
1269 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1270 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1271 MachinePointerInfo::getStack(i * 16),
1273 MemOps.push_back(Store);
1274 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1275 DAG.getConstant(16, getPointerTy()));
1278 FuncInfo->setVariadicFPRIdx(FPRIdx);
1279 FuncInfo->setVariadicFPRSize(FPRSaveSize);
1282 unsigned StackOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), 8);
1283 int StackIdx = MFI->CreateFixedObject(8, StackOffset, true);
1285 FuncInfo->setVariadicStackIdx(StackIdx);
1286 FuncInfo->setVariadicGPRIdx(GPRIdx);
1287 FuncInfo->setVariadicGPRSize(GPRSaveSize);
1289 if (!MemOps.empty()) {
1290 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
1297 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
1298 CallingConv::ID CallConv, bool isVarArg,
1299 const SmallVectorImpl<ISD::InputArg> &Ins,
1300 SDLoc dl, SelectionDAG &DAG,
1301 SmallVectorImpl<SDValue> &InVals) const {
1302 MachineFunction &MF = DAG.getMachineFunction();
1303 AArch64MachineFunctionInfo *FuncInfo
1304 = MF.getInfo<AArch64MachineFunctionInfo>();
1305 MachineFrameInfo *MFI = MF.getFrameInfo();
1306 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1308 SmallVector<CCValAssign, 16> ArgLocs;
1309 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1310 getTargetMachine(), ArgLocs, *DAG.getContext());
1311 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1313 SmallVector<SDValue, 16> ArgValues;
1316 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1317 CCValAssign &VA = ArgLocs[i];
1318 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1320 if (Flags.isByVal()) {
1321 // Byval is used for small structs and HFAs in the PCS, but the system
1322 // should work in a non-compliant manner for larger structs.
1323 EVT PtrTy = getPointerTy();
1324 int Size = Flags.getByValSize();
1325 unsigned NumRegs = (Size + 7) / 8;
1327 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
1328 VA.getLocMemOffset(),
1330 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1331 InVals.push_back(FrameIdxN);
1334 } else if (VA.isRegLoc()) {
1335 MVT RegVT = VA.getLocVT();
1336 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1337 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1339 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1340 } else { // VA.isRegLoc()
1341 assert(VA.isMemLoc());
1343 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
1344 VA.getLocMemOffset(), true);
1346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1347 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1348 MachinePointerInfo::getFixedStack(FI),
1349 false, false, false, 0);
1354 switch (VA.getLocInfo()) {
1355 default: llvm_unreachable("Unknown loc info!");
1356 case CCValAssign::Full: break;
1357 case CCValAssign::BCvt:
1358 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
1360 case CCValAssign::SExt:
1361 case CCValAssign::ZExt:
1362 case CCValAssign::AExt:
1363 case CCValAssign::FPExt: {
1364 unsigned DestSize = VA.getValVT().getSizeInBits();
1365 unsigned DestSubReg;
1368 case 8: DestSubReg = AArch64::sub_8; break;
1369 case 16: DestSubReg = AArch64::sub_16; break;
1370 case 32: DestSubReg = AArch64::sub_32; break;
1371 case 64: DestSubReg = AArch64::sub_64; break;
1372 default: llvm_unreachable("Unexpected argument promotion");
1375 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
1376 VA.getValVT(), ArgValue,
1377 DAG.getTargetConstant(DestSubReg, MVT::i32)),
1383 InVals.push_back(ArgValue);
1387 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
1389 unsigned StackArgSize = CCInfo.getNextStackOffset();
1390 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1391 // This is a non-standard ABI so by fiat I say we're allowed to make full
1392 // use of the stack area to be popped, which must be aligned to 16 bytes in
1394 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1396 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1397 // a multiple of 16.
1398 FuncInfo->setArgumentStackToRestore(StackArgSize);
1400 // This realignment carries over to the available bytes below. Our own
1401 // callers will guarantee the space is free by giving an aligned value to
1404 // Even if we're not expected to free up the space, it's useful to know how
1405 // much is there while considering tail calls (because we can reuse it).
1406 FuncInfo->setBytesInStackArgArea(StackArgSize);
1412 AArch64TargetLowering::LowerReturn(SDValue Chain,
1413 CallingConv::ID CallConv, bool isVarArg,
1414 const SmallVectorImpl<ISD::OutputArg> &Outs,
1415 const SmallVectorImpl<SDValue> &OutVals,
1416 SDLoc dl, SelectionDAG &DAG) const {
1417 // CCValAssign - represent the assignment of the return value to a location.
1418 SmallVector<CCValAssign, 16> RVLocs;
1420 // CCState - Info about the registers and stack slots.
1421 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1422 getTargetMachine(), RVLocs, *DAG.getContext());
1424 // Analyze outgoing return values.
1425 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1428 SmallVector<SDValue, 4> RetOps(1, Chain);
1430 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1431 // PCS: "If the type, T, of the result of a function is such that
1432 // void func(T arg) would require that arg be passed as a value in a
1433 // register (or set of registers) according to the rules in 5.4, then the
1434 // result is returned in the same registers as would be used for such an
1437 // Otherwise, the caller shall reserve a block of memory of sufficient
1438 // size and alignment to hold the result. The address of the memory block
1439 // shall be passed as an additional argument to the function in x8."
1441 // This is implemented in two places. The register-return values are dealt
1442 // with here, more complex returns are passed as an sret parameter, which
1443 // means we don't have to worry about it during actual return.
1444 CCValAssign &VA = RVLocs[i];
1445 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1448 SDValue Arg = OutVals[i];
1450 // There's no convenient note in the ABI about this as there is for normal
1451 // arguments, but it says return values are passed in the same registers as
1452 // an argument would be. I believe that includes the comments about
1453 // unspecified higher bits, putting the burden of widening on the *caller*
1454 // for return values.
1455 switch (VA.getLocInfo()) {
1456 default: llvm_unreachable("Unknown loc info");
1457 case CCValAssign::Full: break;
1458 case CCValAssign::SExt:
1459 case CCValAssign::ZExt:
1460 case CCValAssign::AExt:
1461 // Floating-point values should only be extended when they're going into
1462 // memory, which can't happen here so an integer extend is acceptable.
1463 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1465 case CCValAssign::BCvt:
1466 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1470 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1471 Flag = Chain.getValue(1);
1472 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1475 RetOps[0] = Chain; // Update chain.
1477 // Add the flag if we have it.
1479 RetOps.push_back(Flag);
1481 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1482 &RetOps[0], RetOps.size());
1485 unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
1486 // This is a new backend. For anything more precise than this a FE should
1487 // set an explicit alignment.
1492 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1493 SmallVectorImpl<SDValue> &InVals) const {
1494 SelectionDAG &DAG = CLI.DAG;
1496 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1497 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1498 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1499 SDValue Chain = CLI.Chain;
1500 SDValue Callee = CLI.Callee;
1501 bool &IsTailCall = CLI.IsTailCall;
1502 CallingConv::ID CallConv = CLI.CallConv;
1503 bool IsVarArg = CLI.IsVarArg;
1505 MachineFunction &MF = DAG.getMachineFunction();
1506 AArch64MachineFunctionInfo *FuncInfo
1507 = MF.getInfo<AArch64MachineFunctionInfo>();
1508 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1509 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1510 bool IsSibCall = false;
1513 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1514 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1515 Outs, OutVals, Ins, DAG);
1517 // A sibling call is one where we're under the usual C ABI and not planning
1518 // to change that but can still do a tail call:
1519 if (!TailCallOpt && IsTailCall)
1523 SmallVector<CCValAssign, 16> ArgLocs;
1524 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1525 getTargetMachine(), ArgLocs, *DAG.getContext());
1526 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1528 // On AArch64 (and all other architectures I'm aware of) the most this has to
1529 // do is adjust the stack pointer.
1530 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1532 // Since we're not changing the ABI to make this a tail call, the memory
1533 // operands are already available in the caller's incoming argument space.
1537 // FPDiff is the byte offset of the call's argument area from the callee's.
1538 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1539 // by this amount for a tail call. In a sibling call it must be 0 because the
1540 // caller will deallocate the entire stack and the callee still expects its
1541 // arguments to begin at SP+0. Completely unused for non-tail calls.
1544 if (IsTailCall && !IsSibCall) {
1545 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1547 // FPDiff will be negative if this tail call requires more space than we
1548 // would automatically have in our incoming argument space. Positive if we
1549 // can actually shrink the stack.
1550 FPDiff = NumReusableBytes - NumBytes;
1552 // The stack pointer must be 16-byte aligned at all times it's used for a
1553 // memory operation, which in practice means at *all* times and in
1554 // particular across call boundaries. Therefore our own arguments started at
1555 // a 16-byte aligned SP and the delta applied for the tail call should
1556 // satisfy the same constraint.
1557 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1561 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1564 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1567 SmallVector<SDValue, 8> MemOpChains;
1568 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1570 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1571 CCValAssign &VA = ArgLocs[i];
1572 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1573 SDValue Arg = OutVals[i];
1575 // Callee does the actual widening, so all extensions just use an implicit
1576 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1577 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1578 // alternative works on integer types too.
1579 switch (VA.getLocInfo()) {
1580 default: llvm_unreachable("Unknown loc info!");
1581 case CCValAssign::Full: break;
1582 case CCValAssign::SExt:
1583 case CCValAssign::ZExt:
1584 case CCValAssign::AExt:
1585 case CCValAssign::FPExt: {
1586 unsigned SrcSize = VA.getValVT().getSizeInBits();
1590 case 8: SrcSubReg = AArch64::sub_8; break;
1591 case 16: SrcSubReg = AArch64::sub_16; break;
1592 case 32: SrcSubReg = AArch64::sub_32; break;
1593 case 64: SrcSubReg = AArch64::sub_64; break;
1594 default: llvm_unreachable("Unexpected argument promotion");
1597 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1599 DAG.getUNDEF(VA.getLocVT()),
1601 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1606 case CCValAssign::BCvt:
1607 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1611 if (VA.isRegLoc()) {
1612 // A normal register (sub-) argument. For now we just note it down because
1613 // we want to copy things into registers as late as possible to avoid
1614 // register-pressure (and possibly worse).
1615 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1619 assert(VA.isMemLoc() && "unexpected argument location");
1622 MachinePointerInfo DstInfo;
1624 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1625 VA.getLocVT().getSizeInBits();
1626 OpSize = (OpSize + 7) / 8;
1627 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1628 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1630 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1631 DstInfo = MachinePointerInfo::getFixedStack(FI);
1633 // Make sure any stack arguments overlapping with where we're storing are
1634 // loaded before this eventual operation. Otherwise they'll be clobbered.
1635 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1637 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1639 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1640 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1643 if (Flags.isByVal()) {
1644 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1645 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1646 Flags.getByValAlign(),
1647 /*isVolatile = */ false,
1648 /*alwaysInline = */ false,
1649 DstInfo, MachinePointerInfo(0));
1650 MemOpChains.push_back(Cpy);
1652 // Normal stack argument, put it where it's needed.
1653 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1655 MemOpChains.push_back(Store);
1659 // The loads and stores generated above shouldn't clash with each
1660 // other. Combining them with this TokenFactor notes that fact for the rest of
1662 if (!MemOpChains.empty())
1663 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1664 &MemOpChains[0], MemOpChains.size());
1666 // Most of the rest of the instructions need to be glued together; we don't
1667 // want assignments to actual registers used by a call to be rearranged by a
1668 // well-meaning scheduler.
1671 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1672 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1673 RegsToPass[i].second, InFlag);
1674 InFlag = Chain.getValue(1);
1677 // The linker is responsible for inserting veneers when necessary to put a
1678 // function call destination in range, so we don't need to bother with a
1680 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1681 const GlobalValue *GV = G->getGlobal();
1682 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1683 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1684 const char *Sym = S->getSymbol();
1685 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1688 // We don't usually want to end the call-sequence here because we would tidy
1689 // the frame up *after* the call, however in the ABI-changing tail-call case
1690 // we've carefully laid out the parameters so that when sp is reset they'll be
1691 // in the correct location.
1692 if (IsTailCall && !IsSibCall) {
1693 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1694 DAG.getIntPtrConstant(0, true), InFlag, dl);
1695 InFlag = Chain.getValue(1);
1698 // We produce the following DAG scheme for the actual call instruction:
1699 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1701 // Most arguments aren't going to be used and just keep the values live as
1702 // far as LLVM is concerned. It's expected to be selected as simply "bl
1703 // callee" (for a direct, non-tail call).
1704 std::vector<SDValue> Ops;
1705 Ops.push_back(Chain);
1706 Ops.push_back(Callee);
1709 // Each tail call may have to adjust the stack by a different amount, so
1710 // this information must travel along with the operation for eventual
1711 // consumption by emitEpilogue.
1712 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1715 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1716 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1717 RegsToPass[i].second.getValueType()));
1720 // Add a register mask operand representing the call-preserved registers. This
1721 // is used later in codegen to constrain register-allocation.
1722 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1723 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1724 assert(Mask && "Missing call preserved mask for calling convention");
1725 Ops.push_back(DAG.getRegisterMask(Mask));
1727 // If we needed glue, put it in as the last argument.
1728 if (InFlag.getNode())
1729 Ops.push_back(InFlag);
1731 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1734 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1737 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1738 InFlag = Chain.getValue(1);
1740 // Now we can reclaim the stack, just as well do it before working out where
1741 // our return value is.
1743 uint64_t CalleePopBytes
1744 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1746 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1747 DAG.getIntPtrConstant(CalleePopBytes, true),
1749 InFlag = Chain.getValue(1);
1752 return LowerCallResult(Chain, InFlag, CallConv,
1753 IsVarArg, Ins, dl, DAG, InVals);
1757 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1758 CallingConv::ID CallConv, bool IsVarArg,
1759 const SmallVectorImpl<ISD::InputArg> &Ins,
1760 SDLoc dl, SelectionDAG &DAG,
1761 SmallVectorImpl<SDValue> &InVals) const {
1762 // Assign locations to each value returned by this call.
1763 SmallVector<CCValAssign, 16> RVLocs;
1764 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1765 getTargetMachine(), RVLocs, *DAG.getContext());
1766 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1768 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1769 CCValAssign VA = RVLocs[i];
1771 // Return values that are too big to fit into registers should use an sret
1772 // pointer, so this can be a lot simpler than the main argument code.
1773 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1775 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1777 Chain = Val.getValue(1);
1778 InFlag = Val.getValue(2);
1780 switch (VA.getLocInfo()) {
1781 default: llvm_unreachable("Unknown loc info!");
1782 case CCValAssign::Full: break;
1783 case CCValAssign::BCvt:
1784 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1786 case CCValAssign::ZExt:
1787 case CCValAssign::SExt:
1788 case CCValAssign::AExt:
1789 // Floating-point arguments only get extended/truncated if they're going
1790 // in memory, so using the integer operation is acceptable here.
1791 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1795 InVals.push_back(Val);
1802 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1803 CallingConv::ID CalleeCC,
1805 bool IsCalleeStructRet,
1806 bool IsCallerStructRet,
1807 const SmallVectorImpl<ISD::OutputArg> &Outs,
1808 const SmallVectorImpl<SDValue> &OutVals,
1809 const SmallVectorImpl<ISD::InputArg> &Ins,
1810 SelectionDAG& DAG) const {
1812 // For CallingConv::C this function knows whether the ABI needs
1813 // changing. That's not true for other conventions so they will have to opt in
1815 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1818 const MachineFunction &MF = DAG.getMachineFunction();
1819 const Function *CallerF = MF.getFunction();
1820 CallingConv::ID CallerCC = CallerF->getCallingConv();
1821 bool CCMatch = CallerCC == CalleeCC;
1823 // Byval parameters hand the function a pointer directly into the stack area
1824 // we want to reuse during a tail call. Working around this *is* possible (see
1825 // X86) but less efficient and uglier in LowerCall.
1826 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1827 e = CallerF->arg_end(); i != e; ++i)
1828 if (i->hasByValAttr())
1831 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1832 if (IsTailCallConvention(CalleeCC) && CCMatch)
1837 // Now we search for cases where we can use a tail call without changing the
1838 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1841 // I want anyone implementing a new calling convention to think long and hard
1842 // about this assert.
1843 assert((!IsVarArg || CalleeCC == CallingConv::C)
1844 && "Unexpected variadic calling convention");
1846 if (IsVarArg && !Outs.empty()) {
1847 // At least two cases here: if caller is fastcc then we can't have any
1848 // memory arguments (we'd be expected to clean up the stack afterwards). If
1849 // caller is C then we could potentially use its argument area.
1851 // FIXME: for now we take the most conservative of these in both cases:
1852 // disallow all variadic memory operands.
1853 SmallVector<CCValAssign, 16> ArgLocs;
1854 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1855 getTargetMachine(), ArgLocs, *DAG.getContext());
1857 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1859 if (!ArgLocs[i].isRegLoc())
1863 // If the calling conventions do not match, then we'd better make sure the
1864 // results are returned in the same way as what the caller expects.
1866 SmallVector<CCValAssign, 16> RVLocs1;
1867 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1868 getTargetMachine(), RVLocs1, *DAG.getContext());
1869 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1871 SmallVector<CCValAssign, 16> RVLocs2;
1872 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1873 getTargetMachine(), RVLocs2, *DAG.getContext());
1874 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1876 if (RVLocs1.size() != RVLocs2.size())
1878 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1879 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1881 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1883 if (RVLocs1[i].isRegLoc()) {
1884 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1887 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1893 // Nothing more to check if the callee is taking no arguments
1897 SmallVector<CCValAssign, 16> ArgLocs;
1898 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1899 getTargetMachine(), ArgLocs, *DAG.getContext());
1901 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1903 const AArch64MachineFunctionInfo *FuncInfo
1904 = MF.getInfo<AArch64MachineFunctionInfo>();
1906 // If the stack arguments for this call would fit into our own save area then
1907 // the call can be made tail.
1908 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1911 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1912 bool TailCallOpt) const {
1913 return CallCC == CallingConv::Fast && TailCallOpt;
1916 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1917 return CallCC == CallingConv::Fast;
1920 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1922 MachineFrameInfo *MFI,
1923 int ClobberedFI) const {
1924 SmallVector<SDValue, 8> ArgChains;
1925 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1926 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1928 // Include the original chain at the beginning of the list. When this is
1929 // used by target LowerCall hooks, this helps legalize find the
1930 // CALLSEQ_BEGIN node.
1931 ArgChains.push_back(Chain);
1933 // Add a chain value for each stack argument corresponding
1934 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1935 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1936 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1937 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1938 if (FI->getIndex() < 0) {
1939 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1940 int64_t InLastByte = InFirstByte;
1941 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1943 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1944 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1945 ArgChains.push_back(SDValue(L, 1));
1948 // Build a tokenfactor for all the chains.
1949 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1950 &ArgChains[0], ArgChains.size());
1953 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1955 case ISD::SETEQ: return A64CC::EQ;
1956 case ISD::SETGT: return A64CC::GT;
1957 case ISD::SETGE: return A64CC::GE;
1958 case ISD::SETLT: return A64CC::LT;
1959 case ISD::SETLE: return A64CC::LE;
1960 case ISD::SETNE: return A64CC::NE;
1961 case ISD::SETUGT: return A64CC::HI;
1962 case ISD::SETUGE: return A64CC::HS;
1963 case ISD::SETULT: return A64CC::LO;
1964 case ISD::SETULE: return A64CC::LS;
1965 default: llvm_unreachable("Unexpected condition code");
1969 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1970 // icmp is implemented using adds/subs immediate, which take an unsigned
1971 // 12-bit immediate, optionally shifted left by 12 bits.
1973 // Symmetric by using adds/subs
1977 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1980 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1981 ISD::CondCode CC, SDValue &A64cc,
1982 SelectionDAG &DAG, SDLoc &dl) const {
1983 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1985 EVT VT = RHSC->getValueType(0);
1986 bool knownInvalid = false;
1988 // I'm not convinced the rest of LLVM handles these edge cases properly, but
1989 // we can at least get it right.
1990 if (isSignedIntSetCC(CC)) {
1991 C = RHSC->getSExtValue();
1992 } else if (RHSC->getZExtValue() > INT64_MAX) {
1993 // A 64-bit constant not representable by a signed 64-bit integer is far
1994 // too big to fit into a SUBS immediate anyway.
1995 knownInvalid = true;
1997 C = RHSC->getZExtValue();
2000 if (!knownInvalid && !isLegalICmpImmediate(C)) {
2001 // Constant does not fit, try adjusting it by one?
2006 if (isLegalICmpImmediate(C-1)) {
2007 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2008 RHS = DAG.getConstant(C-1, VT);
2013 if (isLegalICmpImmediate(C-1)) {
2014 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2015 RHS = DAG.getConstant(C-1, VT);
2020 if (isLegalICmpImmediate(C+1)) {
2021 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2022 RHS = DAG.getConstant(C+1, VT);
2027 if (isLegalICmpImmediate(C+1)) {
2028 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2029 RHS = DAG.getConstant(C+1, VT);
2036 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
2037 A64cc = DAG.getConstant(CondCode, MVT::i32);
2038 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2039 DAG.getCondCode(CC));
2042 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
2043 A64CC::CondCodes &Alternative) {
2044 A64CC::CondCodes CondCode = A64CC::Invalid;
2045 Alternative = A64CC::Invalid;
2048 default: llvm_unreachable("Unknown FP condition!");
2050 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
2052 case ISD::SETOGT: CondCode = A64CC::GT; break;
2054 case ISD::SETOGE: CondCode = A64CC::GE; break;
2055 case ISD::SETOLT: CondCode = A64CC::MI; break;
2056 case ISD::SETOLE: CondCode = A64CC::LS; break;
2057 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
2058 case ISD::SETO: CondCode = A64CC::VC; break;
2059 case ISD::SETUO: CondCode = A64CC::VS; break;
2060 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
2061 case ISD::SETUGT: CondCode = A64CC::HI; break;
2062 case ISD::SETUGE: CondCode = A64CC::PL; break;
2064 case ISD::SETULT: CondCode = A64CC::LT; break;
2066 case ISD::SETULE: CondCode = A64CC::LE; break;
2068 case ISD::SETUNE: CondCode = A64CC::NE; break;
2074 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
2076 EVT PtrVT = getPointerTy();
2077 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2079 switch(getTargetMachine().getCodeModel()) {
2080 case CodeModel::Small:
2081 // The most efficient code is PC-relative anyway for the small memory model,
2082 // so we don't need to worry about relocation model.
2083 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2084 DAG.getTargetBlockAddress(BA, PtrVT, 0,
2085 AArch64II::MO_NO_FLAG),
2086 DAG.getTargetBlockAddress(BA, PtrVT, 0,
2087 AArch64II::MO_LO12),
2088 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
2089 case CodeModel::Large:
2091 AArch64ISD::WrapperLarge, DL, PtrVT,
2092 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3),
2093 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2094 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2095 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2097 llvm_unreachable("Only small and large code models supported now");
2102 // (BRCOND chain, val, dest)
2104 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2106 SDValue Chain = Op.getOperand(0);
2107 SDValue TheBit = Op.getOperand(1);
2108 SDValue DestBB = Op.getOperand(2);
2110 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2111 // that as the consumer we are responsible for ignoring rubbish in higher
2113 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2114 DAG.getConstant(1, MVT::i32));
2116 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2117 DAG.getConstant(0, TheBit.getValueType()),
2118 DAG.getCondCode(ISD::SETNE));
2120 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
2121 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
2125 // (BR_CC chain, condcode, lhs, rhs, dest)
2127 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2129 SDValue Chain = Op.getOperand(0);
2130 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2131 SDValue LHS = Op.getOperand(2);
2132 SDValue RHS = Op.getOperand(3);
2133 SDValue DestBB = Op.getOperand(4);
2135 if (LHS.getValueType() == MVT::f128) {
2136 // f128 comparisons are lowered to runtime calls by a routine which sets
2137 // LHS, RHS and CC appropriately for the rest of this function to continue.
2138 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2140 // If softenSetCCOperands returned a scalar, we need to compare the result
2141 // against zero to select between true and false values.
2142 if (RHS.getNode() == 0) {
2143 RHS = DAG.getConstant(0, LHS.getValueType());
2148 if (LHS.getValueType().isInteger()) {
2151 // Integers are handled in a separate function because the combinations of
2152 // immediates and tests can get hairy and we may want to fiddle things.
2153 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2155 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2156 Chain, CmpOp, A64cc, DestBB);
2159 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2160 // conditional branch, hence FPCCToA64CC can set a second test, where either
2161 // passing is sufficient.
2162 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2163 CondCode = FPCCToA64CC(CC, Alternative);
2164 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2165 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2166 DAG.getCondCode(CC));
2167 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2168 Chain, SetCC, A64cc, DestBB);
2170 if (Alternative != A64CC::Invalid) {
2171 A64cc = DAG.getConstant(Alternative, MVT::i32);
2172 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2173 A64BR_CC, SetCC, A64cc, DestBB);
2181 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
2182 RTLIB::Libcall Call) const {
2185 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
2186 EVT ArgVT = Op.getOperand(i).getValueType();
2187 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2188 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
2189 Entry.isSExt = false;
2190 Entry.isZExt = false;
2191 Args.push_back(Entry);
2193 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
2195 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2197 // By default, the input chain to this libcall is the entry node of the
2198 // function. If the libcall is going to be emitted as a tail call then
2199 // isUsedByReturnOnly will change it to the right chain if the return
2200 // node which is being folded has a non-entry input chain.
2201 SDValue InChain = DAG.getEntryNode();
2203 // isTailCall may be true since the callee does not reference caller stack
2204 // frame. Check if it's in the right position.
2205 SDValue TCChain = InChain;
2206 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
2211 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
2212 0, getLibcallCallingConv(Call), isTailCall,
2213 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2214 Callee, Args, DAG, SDLoc(Op));
2215 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2217 if (!CallInfo.second.getNode())
2218 // It's a tailcall, return the chain (which is the DAG root).
2219 return DAG.getRoot();
2221 return CallInfo.first;
2225 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
2226 if (Op.getOperand(0).getValueType() != MVT::f128) {
2227 // It's legal except when f128 is involved
2232 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
2234 SDValue SrcVal = Op.getOperand(0);
2235 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
2236 /*isSigned*/ false, SDLoc(Op)).first;
2240 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
2241 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
2244 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
2246 return LowerF128ToCall(Op, DAG, LC);
2249 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2252 EVT VT = Op.getValueType();
2253 SDValue Vec = Op.getOperand(0);
2254 EVT OpVT = Vec.getValueType();
2255 unsigned Opc = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
2257 if (VT.getVectorNumElements() == 1) {
2258 assert(OpVT == MVT::v1f64 && "Unexpected vector type!");
2259 if (VT.getSizeInBits() == OpVT.getSizeInBits())
2261 return DAG.UnrollVectorOp(Op.getNode());
2264 if (VT.getSizeInBits() > OpVT.getSizeInBits()) {
2265 assert(Vec.getValueType() == MVT::v2f32 && VT == MVT::v2i64 &&
2266 "Unexpected vector type!");
2267 Vec = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Vec);
2268 return DAG.getNode(Opc, dl, VT, Vec);
2269 } else if (VT.getSizeInBits() < OpVT.getSizeInBits()) {
2270 EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
2271 OpVT.getVectorElementType().getSizeInBits());
2273 EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
2274 Vec = DAG.getNode(Opc, dl, CastVT, Vec);
2275 return DAG.getNode(ISD::TRUNCATE, dl, VT, Vec);
2277 return DAG.getNode(Opc, dl, VT, Vec);
2280 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2281 // We custom lower concat_vectors with 4, 8, or 16 operands that are all the
2282 // same operand and of type v1* using the DUP instruction.
2283 unsigned NumOps = Op->getNumOperands();
2284 if (NumOps != 4 && NumOps != 8 && NumOps != 16)
2287 // Must be a single value for VDUP.
2288 bool isConstant = true;
2289 SDValue Op0 = Op.getOperand(0);
2290 for (unsigned i = 1; i < NumOps; ++i) {
2291 SDValue OpN = Op.getOperand(i);
2295 if (!isa<ConstantSDNode>(OpN->getOperand(0)))
2299 // Verify the value type.
2300 EVT EltVT = Op0.getValueType();
2302 default: llvm_unreachable("Unexpected number of operands");
2304 if (EltVT != MVT::v1i16 && EltVT != MVT::v1i32)
2308 if (EltVT != MVT::v1i8 && EltVT != MVT::v1i16)
2312 if (EltVT != MVT::v1i8)
2318 EVT VT = Op.getValueType();
2319 // VDUP produces better code for constants.
2321 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Op0->getOperand(0));
2322 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, Op0,
2323 DAG.getConstant(0, MVT::i64));
2327 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2328 bool IsSigned) const {
2329 if (Op.getValueType().isVector())
2330 return LowerVectorFP_TO_INT(Op, DAG, IsSigned);
2331 if (Op.getOperand(0).getValueType() != MVT::f128) {
2332 // It's legal except when f128 is involved
2338 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2340 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2342 return LowerF128ToCall(Op, DAG, LC);
2345 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2346 MachineFunction &MF = DAG.getMachineFunction();
2347 MachineFrameInfo *MFI = MF.getFrameInfo();
2348 MFI->setReturnAddressIsTaken(true);
2350 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2353 EVT VT = Op.getValueType();
2355 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2357 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2358 SDValue Offset = DAG.getConstant(8, MVT::i64);
2359 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2360 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2361 MachinePointerInfo(), false, false, false, 0);
2364 // Return X30, which contains the return address. Mark it an implicit live-in.
2365 unsigned Reg = MF.addLiveIn(AArch64::X30, getRegClassFor(MVT::i64));
2366 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, MVT::i64);
2370 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
2372 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2373 MFI->setFrameAddressIsTaken(true);
2375 EVT VT = Op.getValueType();
2377 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2378 unsigned FrameReg = AArch64::X29;
2379 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2381 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2382 MachinePointerInfo(),
2383 false, false, false, 0);
2388 AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op,
2389 SelectionDAG &DAG) const {
2390 assert(getTargetMachine().getCodeModel() == CodeModel::Large);
2391 assert(getTargetMachine().getRelocationModel() == Reloc::Static);
2393 EVT PtrVT = getPointerTy();
2395 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2396 const GlobalValue *GV = GN->getGlobal();
2398 SDValue GlobalAddr = DAG.getNode(
2399 AArch64ISD::WrapperLarge, dl, PtrVT,
2400 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3),
2401 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2402 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2403 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2405 if (GN->getOffset() != 0)
2406 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2407 DAG.getConstant(GN->getOffset(), PtrVT));
2413 AArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op,
2414 SelectionDAG &DAG) const {
2415 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
2417 EVT PtrVT = getPointerTy();
2419 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2420 const GlobalValue *GV = GN->getGlobal();
2421 unsigned Alignment = GV->getAlignment();
2422 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2423 if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) {
2424 // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate
2425 // to zero when they remain undefined. In PIC mode the GOT can take care of
2426 // this, but in absolute mode we use a constant pool load.
2428 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2429 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2430 AArch64II::MO_NO_FLAG),
2431 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2432 AArch64II::MO_LO12),
2433 DAG.getConstant(8, MVT::i32));
2434 SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
2435 MachinePointerInfo::getConstantPool(),
2436 /*isVolatile=*/ false,
2437 /*isNonTemporal=*/ true,
2438 /*isInvariant=*/ true, 8);
2439 if (GN->getOffset() != 0)
2440 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2441 DAG.getConstant(GN->getOffset(), PtrVT));
2446 if (Alignment == 0) {
2447 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
2448 if (GVPtrTy->getElementType()->isSized()) {
2450 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
2452 // Be conservative if we can't guess, not that it really matters:
2453 // functions and labels aren't valid for loads, and the methods used to
2454 // actually calculate an address work with any alignment.
2459 unsigned char HiFixup, LoFixup;
2460 bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM);
2463 HiFixup = AArch64II::MO_GOT;
2464 LoFixup = AArch64II::MO_GOT_LO12;
2467 HiFixup = AArch64II::MO_NO_FLAG;
2468 LoFixup = AArch64II::MO_LO12;
2471 // AArch64's small model demands the following sequence:
2472 // ADRP x0, somewhere
2473 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
2474 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2475 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2477 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2479 DAG.getConstant(Alignment, MVT::i32));
2482 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
2486 if (GN->getOffset() != 0)
2487 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
2488 DAG.getConstant(GN->getOffset(), PtrVT));
2494 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
2495 SelectionDAG &DAG) const {
2496 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
2497 // we make those distinctions here.
2499 switch (getTargetMachine().getCodeModel()) {
2500 case CodeModel::Small:
2501 return LowerGlobalAddressELFSmall(Op, DAG);
2502 case CodeModel::Large:
2503 return LowerGlobalAddressELFLarge(Op, DAG);
2505 llvm_unreachable("Only small and large code models supported now");
2510 AArch64TargetLowering::LowerConstantPool(SDValue Op,
2511 SelectionDAG &DAG) const {
2513 EVT PtrVT = getPointerTy();
2514 ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Op);
2515 const Constant *C = CN->getConstVal();
2517 switch(getTargetMachine().getCodeModel()) {
2518 case CodeModel::Small:
2519 // The most efficient code is PC-relative anyway for the small memory model,
2520 // so we don't need to worry about relocation model.
2521 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2522 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2523 AArch64II::MO_NO_FLAG),
2524 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2525 AArch64II::MO_LO12),
2526 DAG.getConstant(CN->getAlignment(), MVT::i32));
2527 case CodeModel::Large:
2529 AArch64ISD::WrapperLarge, DL, PtrVT,
2530 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
2531 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
2532 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
2533 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC));
2535 llvm_unreachable("Only small and large code models supported now");
2539 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
2542 SelectionDAG &DAG) const {
2543 EVT PtrVT = getPointerTy();
2545 // The function we need to call is simply the first entry in the GOT for this
2546 // descriptor, load it in preparation.
2547 SDValue Func, Chain;
2548 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2551 // The function takes only one argument: the address of the descriptor itself
2554 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2555 Glue = Chain.getValue(1);
2557 // Finally, there's a special calling-convention which means that the lookup
2558 // must preserve all registers (except X0, obviously).
2559 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2560 const AArch64RegisterInfo *A64RI
2561 = static_cast<const AArch64RegisterInfo *>(TRI);
2562 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
2564 // We're now ready to populate the argument list, as with a normal call:
2565 std::vector<SDValue> Ops;
2566 Ops.push_back(Chain);
2567 Ops.push_back(Func);
2568 Ops.push_back(SymAddr);
2569 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2570 Ops.push_back(DAG.getRegisterMask(Mask));
2571 Ops.push_back(Glue);
2573 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2574 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
2576 Glue = Chain.getValue(1);
2578 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
2579 // back to the generic handling code.
2580 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2584 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2585 SelectionDAG &DAG) const {
2586 assert(getSubtarget()->isTargetELF() &&
2587 "TLS not implemented for non-ELF targets");
2588 assert(getTargetMachine().getCodeModel() == CodeModel::Small
2589 && "TLS only supported in small memory model");
2590 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2592 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2595 EVT PtrVT = getPointerTy();
2597 const GlobalValue *GV = GA->getGlobal();
2599 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2601 if (Model == TLSModel::InitialExec) {
2602 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2603 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2604 AArch64II::MO_GOTTPREL),
2605 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2606 AArch64II::MO_GOTTPREL_LO12),
2607 DAG.getConstant(8, MVT::i32));
2608 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2610 } else if (Model == TLSModel::LocalExec) {
2611 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2612 AArch64II::MO_TPREL_G1);
2613 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2614 AArch64II::MO_TPREL_G0_NC);
2616 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2617 DAG.getTargetConstant(1, MVT::i32)), 0);
2618 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2620 DAG.getTargetConstant(0, MVT::i32)), 0);
2621 } else if (Model == TLSModel::GeneralDynamic) {
2622 // Accesses used in this sequence go via the TLS descriptor which lives in
2623 // the GOT. Prepare an address we can use to handle this.
2624 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2625 AArch64II::MO_TLSDESC);
2626 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2627 AArch64II::MO_TLSDESC_LO12);
2628 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2630 DAG.getConstant(8, MVT::i32));
2631 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2633 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2634 } else if (Model == TLSModel::LocalDynamic) {
2635 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2636 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2637 // the beginning of the module's TLS region, followed by a DTPREL offset
2640 // These accesses will need deduplicating if there's more than one.
2641 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2642 .getInfo<AArch64MachineFunctionInfo>();
2643 MFI->incNumLocalDynamicTLSAccesses();
2646 // Get the location of _TLS_MODULE_BASE_:
2647 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2648 AArch64II::MO_TLSDESC);
2649 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2650 AArch64II::MO_TLSDESC_LO12);
2651 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2653 DAG.getConstant(8, MVT::i32));
2654 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2656 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2658 // Get the variable's offset from _TLS_MODULE_BASE_
2659 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2660 AArch64II::MO_DTPREL_G1);
2661 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2662 AArch64II::MO_DTPREL_G0_NC);
2664 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2665 DAG.getTargetConstant(0, MVT::i32)), 0);
2666 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2668 DAG.getTargetConstant(0, MVT::i32)), 0);
2670 llvm_unreachable("Unsupported TLS access model");
2673 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2676 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2679 EVT VT = Op.getValueType();
2680 SDValue Vec = Op.getOperand(0);
2681 unsigned Opc = IsSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
2683 if (VT.getVectorNumElements() == 1) {
2684 assert(VT == MVT::v1f64 && "Unexpected vector type!");
2685 if (VT.getSizeInBits() == Vec.getValueSizeInBits())
2687 return DAG.UnrollVectorOp(Op.getNode());
2690 if (VT.getSizeInBits() < Vec.getValueSizeInBits()) {
2691 assert(Vec.getValueType() == MVT::v2i64 && VT == MVT::v2f32 &&
2692 "Unexpected vector type!");
2693 Vec = DAG.getNode(Opc, dl, MVT::v2f64, Vec);
2694 return DAG.getNode(ISD::FP_ROUND, dl, VT, Vec, DAG.getIntPtrConstant(0));
2695 } else if (VT.getSizeInBits() > Vec.getValueSizeInBits()) {
2696 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2697 EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
2698 VT.getVectorElementType().getSizeInBits());
2700 EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
2701 Vec = DAG.getNode(CastOpc, dl, CastVT, Vec);
2704 return DAG.getNode(Opc, dl, VT, Vec);
2708 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2709 bool IsSigned) const {
2710 if (Op.getValueType().isVector())
2711 return LowerVectorINT_TO_FP(Op, DAG, IsSigned);
2712 if (Op.getValueType() != MVT::f128) {
2713 // Legal for everything except f128.
2719 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2721 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2723 return LowerF128ToCall(Op, DAG, LC);
2728 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2729 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2731 EVT PtrVT = getPointerTy();
2733 // When compiling PIC, jump tables get put in the code section so a static
2734 // relocation-style is acceptable for both cases.
2735 switch (getTargetMachine().getCodeModel()) {
2736 case CodeModel::Small:
2737 return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2738 DAG.getTargetJumpTable(JT->getIndex(), PtrVT),
2739 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2740 AArch64II::MO_LO12),
2741 DAG.getConstant(1, MVT::i32));
2742 case CodeModel::Large:
2744 AArch64ISD::WrapperLarge, dl, PtrVT,
2745 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3),
2746 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC),
2747 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC),
2748 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC));
2750 llvm_unreachable("Only small and large code models supported now");
2754 // (SELECT testbit, iftrue, iffalse)
2756 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2758 SDValue TheBit = Op.getOperand(0);
2759 SDValue IfTrue = Op.getOperand(1);
2760 SDValue IfFalse = Op.getOperand(2);
2762 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2763 // that as the consumer we are responsible for ignoring rubbish in higher
2765 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2766 DAG.getConstant(1, MVT::i32));
2767 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2768 DAG.getConstant(0, TheBit.getValueType()),
2769 DAG.getCondCode(ISD::SETNE));
2771 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2772 A64CMP, IfTrue, IfFalse,
2773 DAG.getConstant(A64CC::NE, MVT::i32));
2776 static SDValue LowerVectorSETCC(SDValue Op, SelectionDAG &DAG) {
2778 SDValue LHS = Op.getOperand(0);
2779 SDValue RHS = Op.getOperand(1);
2780 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2781 EVT VT = Op.getValueType();
2782 bool Invert = false;
2786 if (LHS.getValueType().isInteger()) {
2788 // Attempt to use Vector Integer Compare Mask Test instruction.
2789 // TST = icmp ne (and (op0, op1), zero).
2790 if (CC == ISD::SETNE) {
2791 if (((LHS.getOpcode() == ISD::AND) &&
2792 ISD::isBuildVectorAllZeros(RHS.getNode())) ||
2793 ((RHS.getOpcode() == ISD::AND) &&
2794 ISD::isBuildVectorAllZeros(LHS.getNode()))) {
2796 SDValue AndOp = (LHS.getOpcode() == ISD::AND) ? LHS : RHS;
2797 SDValue NewLHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(0));
2798 SDValue NewRHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(1));
2799 return DAG.getNode(AArch64ISD::NEON_TST, DL, VT, NewLHS, NewRHS);
2803 // Attempt to use Vector Integer Compare Mask against Zero instr (Signed).
2804 // Note: Compare against Zero does not support unsigned predicates.
2805 if ((ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2806 ISD::isBuildVectorAllZeros(LHS.getNode())) &&
2807 !isUnsignedIntSetCC(CC)) {
2809 // If LHS is the zero value, swap operands and CondCode.
2810 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2811 CC = getSetCCSwappedOperands(CC);
2816 // Ensure valid CondCode for Compare Mask against Zero instruction:
2817 // EQ, GE, GT, LE, LT.
2818 if (ISD::SETNE == CC) {
2823 // Using constant type to differentiate integer and FP compares with zero.
2824 Op1 = DAG.getConstant(0, MVT::i32);
2825 Opcode = AArch64ISD::NEON_CMPZ;
2828 // Attempt to use Vector Integer Compare Mask instr (Signed/Unsigned).
2829 // Ensure valid CondCode for Compare Mask instr: EQ, GE, GT, UGE, UGT.
2833 llvm_unreachable("Illegal integer comparison.");
2849 CC = getSetCCSwappedOperands(CC);
2853 std::swap(LHS, RHS);
2855 Opcode = AArch64ISD::NEON_CMP;
2860 // Generate Compare Mask instr or Compare Mask against Zero instr.
2862 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2865 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2870 // Now handle Floating Point cases.
2871 // Attempt to use Vector Floating Point Compare Mask against Zero instruction.
2872 if (ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2873 ISD::isBuildVectorAllZeros(LHS.getNode())) {
2875 // If LHS is the zero value, swap operands and CondCode.
2876 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2877 CC = getSetCCSwappedOperands(CC);
2882 // Using constant type to differentiate integer and FP compares with zero.
2883 Op1 = DAG.getConstantFP(0, MVT::f32);
2884 Opcode = AArch64ISD::NEON_CMPZ;
2886 // Attempt to use Vector Floating Point Compare Mask instruction.
2889 Opcode = AArch64ISD::NEON_CMP;
2893 // Some register compares have to be implemented with swapped CC and operands,
2894 // e.g.: OLT implemented as OGT with swapped operands.
2895 bool SwapIfRegArgs = false;
2897 // Ensure valid CondCode for FP Compare Mask against Zero instruction:
2898 // EQ, GE, GT, LE, LT.
2899 // And ensure valid CondCode for FP Compare Mask instruction: EQ, GE, GT.
2902 llvm_unreachable("Illegal FP comparison");
2905 Invert = true; // Fallthrough
2913 SwapIfRegArgs = true;
2922 SwapIfRegArgs = true;
2931 SwapIfRegArgs = true;
2940 SwapIfRegArgs = true;
2947 Invert = true; // Fallthrough
2949 // Expand this to (OGT |OLT).
2951 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT));
2953 SwapIfRegArgs = true;
2956 Invert = true; // Fallthrough
2958 // Expand this to (OGE | OLT).
2960 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE));
2962 SwapIfRegArgs = true;
2966 if (Opcode == AArch64ISD::NEON_CMP && SwapIfRegArgs) {
2967 CC = getSetCCSwappedOperands(CC);
2968 std::swap(Op0, Op1);
2971 // Generate FP Compare Mask instr or FP Compare Mask against Zero instr
2972 SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2974 if (NeonCmpAlt.getNode())
2975 NeonCmp = DAG.getNode(ISD::OR, DL, VT, NeonCmp, NeonCmpAlt);
2978 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2983 // (SETCC lhs, rhs, condcode)
2985 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2987 SDValue LHS = Op.getOperand(0);
2988 SDValue RHS = Op.getOperand(1);
2989 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2990 EVT VT = Op.getValueType();
2993 return LowerVectorSETCC(Op, DAG);
2995 if (LHS.getValueType() == MVT::f128) {
2996 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
2997 // for the rest of the function (some i32 or i64 values).
2998 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3000 // If softenSetCCOperands returned a scalar, use it.
3001 if (RHS.getNode() == 0) {
3002 assert(LHS.getValueType() == Op.getValueType() &&
3003 "Unexpected setcc expansion!");
3008 if (LHS.getValueType().isInteger()) {
3011 // Integers are handled in a separate function because the combinations of
3012 // immediates and tests can get hairy and we may want to fiddle things.
3013 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
3015 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
3016 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3020 // Note that some LLVM floating-point CondCodes can't be lowered to a single
3021 // conditional branch, hence FPCCToA64CC can set a second test, where either
3022 // passing is sufficient.
3023 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3024 CondCode = FPCCToA64CC(CC, Alternative);
3025 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3026 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3027 DAG.getCondCode(CC));
3028 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
3029 CmpOp, DAG.getConstant(1, VT),
3030 DAG.getConstant(0, VT), A64cc);
3032 if (Alternative != A64CC::Invalid) {
3033 A64cc = DAG.getConstant(Alternative, MVT::i32);
3034 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
3035 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
3038 return A64SELECT_CC;
3041 static SDValue LowerVectorSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3043 SDValue LHS = Op.getOperand(0);
3044 SDValue RHS = Op.getOperand(1);
3045 SDValue IfTrue = Op.getOperand(2);
3046 SDValue IfFalse = Op.getOperand(3);
3047 EVT IfTrueVT = IfTrue.getValueType();
3048 EVT CondVT = IfTrueVT.changeVectorElementTypeToInteger();
3049 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3051 // If LHS & RHS are floating point and IfTrue & IfFalse are vectors, we will
3052 // use NEON compare.
3053 if ((LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64)) {
3054 EVT EltVT = LHS.getValueType();
3055 unsigned EltNum = 128 / EltVT.getSizeInBits();
3056 EVT VT = EVT::getVectorVT(*DAG.getContext(), EltVT, EltNum);
3057 unsigned SubConstant =
3058 (LHS.getValueType() == MVT::f32) ? AArch64::sub_32 :AArch64::sub_64;
3059 EVT CEltT = (LHS.getValueType() == MVT::f32) ? MVT::i32 : MVT::i64;
3060 EVT CVT = EVT::getVectorVT(*DAG.getContext(), CEltT, EltNum);
3063 = SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
3064 VT, DAG.getTargetConstant(0, MVT::i32), LHS,
3065 DAG.getTargetConstant(SubConstant, MVT::i32)), 0);
3067 = SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
3068 VT, DAG.getTargetConstant(0, MVT::i32), RHS,
3069 DAG.getTargetConstant(SubConstant, MVT::i32)), 0);
3071 SDValue VSetCC = DAG.getSetCC(dl, CVT, LHS, RHS, CC);
3072 SDValue ResCC = LowerVectorSETCC(VSetCC, DAG);
3073 if (CEltT.getSizeInBits() < IfTrueVT.getSizeInBits()) {
3075 EVT::getVectorVT(*DAG.getContext(), CEltT,
3076 IfTrueVT.getSizeInBits() / CEltT.getSizeInBits());
3077 ResCC = DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, DUPVT, ResCC,
3078 DAG.getConstant(0, MVT::i64, false));
3080 ResCC = DAG.getNode(ISD::BITCAST, dl, CondVT, ResCC);
3082 // FIXME: If IfTrue & IfFalse hold v1i8, v1i16 or v1i32, this function
3083 // can't handle them and will hit this assert.
3084 assert(CEltT.getSizeInBits() == IfTrueVT.getSizeInBits() &&
3085 "Vector of IfTrue & IfFalse is too small.");
3088 EltNum * IfTrueVT.getSizeInBits() / ResCC.getValueSizeInBits();
3089 EVT ExVT = EVT::getVectorVT(*DAG.getContext(), CEltT, ExEltNum);
3090 ResCC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ExVT, ResCC,
3091 DAG.getConstant(0, MVT::i64, false));
3092 ResCC = DAG.getNode(ISD::BITCAST, dl, CondVT, ResCC);
3094 SDValue VSelect = DAG.getNode(ISD::VSELECT, dl, IfTrue.getValueType(),
3095 ResCC, IfTrue, IfFalse);
3099 // Here we handle the case that LHS & RHS are integer and IfTrue & IfFalse are
3101 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3102 CondCode = FPCCToA64CC(CC, Alternative);
3103 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3104 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3105 DAG.getCondCode(CC));
3106 EVT SEVT = MVT::i32;
3107 if (IfTrue.getValueType().getVectorElementType().getSizeInBits() > 32)
3109 SDValue AllOne = DAG.getConstant(-1, SEVT);
3110 SDValue AllZero = DAG.getConstant(0, SEVT);
3111 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, SEVT, SetCC,
3112 AllOne, AllZero, A64cc);
3114 if (Alternative != A64CC::Invalid) {
3115 A64cc = DAG.getConstant(Alternative, MVT::i32);
3116 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
3117 SetCC, AllOne, A64SELECT_CC, A64cc);
3120 if (IfTrue.getValueType().getVectorNumElements() == 1)
3121 VDup = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, CondVT, A64SELECT_CC);
3123 VDup = DAG.getNode(AArch64ISD::NEON_VDUP, dl, CondVT, A64SELECT_CC);
3124 SDValue VSelect = DAG.getNode(ISD::VSELECT, dl, IfTrue.getValueType(),
3125 VDup, IfTrue, IfFalse);
3129 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
3131 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3133 SDValue LHS = Op.getOperand(0);
3134 SDValue RHS = Op.getOperand(1);
3135 SDValue IfTrue = Op.getOperand(2);
3136 SDValue IfFalse = Op.getOperand(3);
3137 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3139 if (IfTrue.getValueType().isVector())
3140 return LowerVectorSELECT_CC(Op, DAG);
3142 if (LHS.getValueType() == MVT::f128) {
3143 // f128 comparisons are lowered to libcalls, but slot in nicely here
3145 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3147 // If softenSetCCOperands returned a scalar, we need to compare the result
3148 // against zero to select between true and false values.
3149 if (RHS.getNode() == 0) {
3150 RHS = DAG.getConstant(0, LHS.getValueType());
3155 if (LHS.getValueType().isInteger()) {
3158 // Integers are handled in a separate function because the combinations of
3159 // immediates and tests can get hairy and we may want to fiddle things.
3160 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
3162 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), CmpOp,
3163 IfTrue, IfFalse, A64cc);
3166 // Note that some LLVM floating-point CondCodes can't be lowered to a single
3167 // conditional branch, hence FPCCToA64CC can set a second test, where either
3168 // passing is sufficient.
3169 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3170 CondCode = FPCCToA64CC(CC, Alternative);
3171 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3172 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3173 DAG.getCondCode(CC));
3174 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
3176 SetCC, IfTrue, IfFalse, A64cc);
3178 if (Alternative != A64CC::Invalid) {
3179 A64cc = DAG.getConstant(Alternative, MVT::i32);
3180 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
3181 SetCC, IfTrue, A64SELECT_CC, A64cc);
3185 return A64SELECT_CC;
3189 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3190 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3191 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3193 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
3194 // rather than just 8.
3195 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op),
3196 Op.getOperand(1), Op.getOperand(2),
3197 DAG.getConstant(32, MVT::i32), 8, false, false,
3198 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
3202 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3203 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3204 // Standard, section B.3.
3205 MachineFunction &MF = DAG.getMachineFunction();
3206 AArch64MachineFunctionInfo *FuncInfo
3207 = MF.getInfo<AArch64MachineFunctionInfo>();
3210 SDValue Chain = Op.getOperand(0);
3211 SDValue VAList = Op.getOperand(1);
3212 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3213 SmallVector<SDValue, 4> MemOps;
3215 // void *__stack at offset 0
3216 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
3218 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3219 MachinePointerInfo(SV), false, false, 0));
3221 // void *__gr_top at offset 8
3222 int GPRSize = FuncInfo->getVariadicGPRSize();
3224 SDValue GRTop, GRTopAddr;
3226 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3227 DAG.getConstant(8, getPointerTy()));
3229 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
3230 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3231 DAG.getConstant(GPRSize, getPointerTy()));
3233 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3234 MachinePointerInfo(SV, 8),
3238 // void *__vr_top at offset 16
3239 int FPRSize = FuncInfo->getVariadicFPRSize();
3241 SDValue VRTop, VRTopAddr;
3242 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3243 DAG.getConstant(16, getPointerTy()));
3245 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
3246 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3247 DAG.getConstant(FPRSize, getPointerTy()));
3249 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3250 MachinePointerInfo(SV, 16),
3254 // int __gr_offs at offset 24
3255 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3256 DAG.getConstant(24, getPointerTy()));
3257 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3258 GROffsAddr, MachinePointerInfo(SV, 24),
3261 // int __vr_offs at offset 28
3262 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3263 DAG.getConstant(28, getPointerTy()));
3264 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3265 VROffsAddr, MachinePointerInfo(SV, 28),
3268 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
3273 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3274 switch (Op.getOpcode()) {
3275 default: llvm_unreachable("Don't know how to custom lower this!");
3276 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
3277 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
3278 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
3279 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
3280 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
3281 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
3282 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
3283 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
3284 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
3285 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
3286 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3287 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3289 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3290 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3291 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3292 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
3293 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3294 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3295 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3296 case ISD::SELECT: return LowerSELECT(Op, DAG);
3297 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3298 case ISD::SETCC: return LowerSETCC(Op, DAG);
3299 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3300 case ISD::VASTART: return LowerVASTART(Op, DAG);
3301 case ISD::BUILD_VECTOR:
3302 return LowerBUILD_VECTOR(Op, DAG, getSubtarget());
3303 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3304 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3310 /// Check if the specified splat value corresponds to a valid vector constant
3311 /// for a Neon instruction with a "modified immediate" operand (e.g., MOVI). If
3312 /// so, return the encoded 8-bit immediate and the OpCmode instruction fields
3314 static bool isNeonModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3315 unsigned SplatBitSize, SelectionDAG &DAG,
3316 bool is128Bits, NeonModImmType type, EVT &VT,
3317 unsigned &Imm, unsigned &OpCmode) {
3318 switch (SplatBitSize) {
3320 llvm_unreachable("unexpected size for isNeonModifiedImm");
3322 if (type != Neon_Mov_Imm)
3324 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3325 // Neon movi per byte: Op=0, Cmode=1110.
3328 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3332 // Neon move inst per halfword
3333 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3334 if ((SplatBits & ~0xff) == 0) {
3335 // Value = 0x00nn is 0x00nn LSL 0
3336 // movi: Op=0, Cmode=1000; mvni: Op=1, Cmode=1000
3337 // bic: Op=1, Cmode=1001; orr: Op=0, Cmode=1001
3343 if ((SplatBits & ~0xff00) == 0) {
3344 // Value = 0xnn00 is 0x00nn LSL 8
3345 // movi: Op=0, Cmode=1010; mvni: Op=1, Cmode=1010
3346 // bic: Op=1, Cmode=1011; orr: Op=0, Cmode=1011
3348 Imm = SplatBits >> 8;
3352 // can't handle any other
3357 // First the LSL variants (MSL is unusable by some interested instructions).
3359 // Neon move instr per word, shift zeros
3360 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3361 if ((SplatBits & ~0xff) == 0) {
3362 // Value = 0x000000nn is 0x000000nn LSL 0
3363 // movi: Op=0, Cmode= 0000; mvni: Op=1, Cmode= 0000
3364 // bic: Op=1, Cmode= 0001; orr: Op=0, Cmode= 0001
3370 if ((SplatBits & ~0xff00) == 0) {
3371 // Value = 0x0000nn00 is 0x000000nn LSL 8
3372 // movi: Op=0, Cmode= 0010; mvni: Op=1, Cmode= 0010
3373 // bic: Op=1, Cmode= 0011; orr : Op=0, Cmode= 0011
3375 Imm = SplatBits >> 8;
3379 if ((SplatBits & ~0xff0000) == 0) {
3380 // Value = 0x00nn0000 is 0x000000nn LSL 16
3381 // movi: Op=0, Cmode= 0100; mvni: Op=1, Cmode= 0100
3382 // bic: Op=1, Cmode= 0101; orr: Op=0, Cmode= 0101
3384 Imm = SplatBits >> 16;
3388 if ((SplatBits & ~0xff000000) == 0) {
3389 // Value = 0xnn000000 is 0x000000nn LSL 24
3390 // movi: Op=0, Cmode= 0110; mvni: Op=1, Cmode= 0110
3391 // bic: Op=1, Cmode= 0111; orr: Op=0, Cmode= 0111
3393 Imm = SplatBits >> 24;
3398 // Now the MSL immediates.
3400 // Neon move instr per word, shift ones
3401 if ((SplatBits & ~0xffff) == 0 &&
3402 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3403 // Value = 0x0000nnff is 0x000000nn MSL 8
3404 // movi: Op=0, Cmode= 1100; mvni: Op=1, Cmode= 1100
3406 Imm = SplatBits >> 8;
3410 if ((SplatBits & ~0xffffff) == 0 &&
3411 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3412 // Value = 0x00nnffff is 0x000000nn MSL 16
3413 // movi: Op=1, Cmode= 1101; mvni: Op=1, Cmode= 1101
3415 Imm = SplatBits >> 16;
3419 // can't handle any other
3424 if (type != Neon_Mov_Imm)
3426 // Neon move instr bytemask, where each byte is either 0x00 or 0xff.
3427 // movi Op=1, Cmode=1110.
3429 uint64_t BitMask = 0xff;
3431 unsigned ImmMask = 1;
3433 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3434 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3437 } else if ((SplatBits & BitMask) != 0) {
3444 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3452 static SDValue PerformANDCombine(SDNode *N,
3453 TargetLowering::DAGCombinerInfo &DCI) {
3455 SelectionDAG &DAG = DCI.DAG;
3457 EVT VT = N->getValueType(0);
3459 // We're looking for an SRA/SHL pair which form an SBFX.
3461 if (VT != MVT::i32 && VT != MVT::i64)
3464 if (!isa<ConstantSDNode>(N->getOperand(1)))
3467 uint64_t TruncMask = N->getConstantOperandVal(1);
3468 if (!isMask_64(TruncMask))
3471 uint64_t Width = CountPopulation_64(TruncMask);
3472 SDValue Shift = N->getOperand(0);
3474 if (Shift.getOpcode() != ISD::SRL)
3477 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3479 uint64_t LSB = Shift->getConstantOperandVal(1);
3481 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3484 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
3485 DAG.getConstant(LSB, MVT::i64),
3486 DAG.getConstant(LSB + Width - 1, MVT::i64));
3489 /// For a true bitfield insert, the bits getting into that contiguous mask
3490 /// should come from the low part of an existing value: they must be formed from
3491 /// a compatible SHL operation (unless they're already low). This function
3492 /// checks that condition and returns the least-significant bit that's
3493 /// intended. If the operation not a field preparation, -1 is returned.
3494 static int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT,
3495 SDValue &MaskedVal, uint64_t Mask) {
3496 if (!isShiftedMask_64(Mask))
3499 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
3500 // instruction. BFI will do a left-shift by LSB before applying the mask we've
3501 // spotted, so in general we should pre-emptively "undo" that by making sure
3502 // the incoming bits have had a right-shift applied to them.
3504 // This right shift, however, will combine with existing left/right shifts. In
3505 // the simplest case of a completely straight bitfield operation, it will be
3506 // expected to completely cancel out with an existing SHL. More complicated
3507 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
3510 uint64_t LSB = countTrailingZeros(Mask);
3511 int64_t ShiftRightRequired = LSB;
3512 if (MaskedVal.getOpcode() == ISD::SHL &&
3513 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3514 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
3515 MaskedVal = MaskedVal.getOperand(0);
3516 } else if (MaskedVal.getOpcode() == ISD::SRL &&
3517 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3518 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
3519 MaskedVal = MaskedVal.getOperand(0);
3522 if (ShiftRightRequired > 0)
3523 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
3524 DAG.getConstant(ShiftRightRequired, MVT::i64));
3525 else if (ShiftRightRequired < 0) {
3526 // We could actually end up with a residual left shift, for example with
3527 // "struc.bitfield = val << 1".
3528 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
3529 DAG.getConstant(-ShiftRightRequired, MVT::i64));
3535 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
3536 /// a mask and an extension. Returns true if a BFI was found and provides
3537 /// information on its surroundings.
3538 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
3541 if (N.getOpcode() == ISD::ZERO_EXTEND) {
3543 N = N.getOperand(0);
3546 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
3547 Mask = N->getConstantOperandVal(1);
3548 N = N.getOperand(0);
3550 // Mask is the whole width.
3551 Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
3554 if (N.getOpcode() == AArch64ISD::BFI) {
3562 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
3563 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
3564 /// can often be further combined with a larger mask. Ultimately, we want mask
3565 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
3566 static SDValue tryCombineToBFI(SDNode *N,
3567 TargetLowering::DAGCombinerInfo &DCI,
3568 const AArch64Subtarget *Subtarget) {
3569 SelectionDAG &DAG = DCI.DAG;
3571 EVT VT = N->getValueType(0);
3573 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3575 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
3576 // abandon the effort.
3577 SDValue LHS = N->getOperand(0);
3578 if (LHS.getOpcode() != ISD::AND)
3582 if (isa<ConstantSDNode>(LHS.getOperand(1)))
3583 LHSMask = LHS->getConstantOperandVal(1);
3587 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
3588 // is or abandon the effort.
3589 SDValue RHS = N->getOperand(1);
3590 if (RHS.getOpcode() != ISD::AND)
3594 if (isa<ConstantSDNode>(RHS.getOperand(1)))
3595 RHSMask = RHS->getConstantOperandVal(1);
3599 // Can't do anything if the masks are incompatible.
3600 if (LHSMask & RHSMask)
3603 // Now we need one of the masks to be a contiguous field. Without loss of
3604 // generality that should be the RHS one.
3605 SDValue Bitfield = LHS.getOperand(0);
3606 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
3607 // We know that LHS is a candidate new value, and RHS isn't already a better
3609 std::swap(LHS, RHS);
3610 std::swap(LHSMask, RHSMask);
3613 // We've done our best to put the right operands in the right places, all we
3614 // can do now is check whether a BFI exists.
3615 Bitfield = RHS.getOperand(0);
3616 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
3620 uint32_t Width = CountPopulation_64(RHSMask);
3621 assert(Width && "Expected non-zero bitfield width");
3623 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3624 LHS.getOperand(0), Bitfield,
3625 DAG.getConstant(LSB, MVT::i64),
3626 DAG.getConstant(Width, MVT::i64));
3629 if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3632 return DAG.getNode(ISD::AND, DL, VT, BFI,
3633 DAG.getConstant(LHSMask | RHSMask, VT));
3636 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
3637 /// original input. This is surprisingly common because SROA splits things up
3638 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
3639 /// on the low (say) byte of a word. This is then orred into the rest of the
3640 /// word afterwards.
3642 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
3644 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
3645 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
3647 static SDValue tryCombineToLargerBFI(SDNode *N,
3648 TargetLowering::DAGCombinerInfo &DCI,
3649 const AArch64Subtarget *Subtarget) {
3650 SelectionDAG &DAG = DCI.DAG;
3652 EVT VT = N->getValueType(0);
3654 // First job is to hunt for a MaskedBFI on either the left or right. Swap
3655 // operands if it's actually on the right.
3657 SDValue PossExtraMask;
3658 uint64_t ExistingMask = 0;
3659 bool Extended = false;
3660 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
3661 PossExtraMask = N->getOperand(1);
3662 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
3663 PossExtraMask = N->getOperand(0);
3667 // We can only combine a BFI with another compatible mask.
3668 if (PossExtraMask.getOpcode() != ISD::AND ||
3669 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
3672 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
3674 // Masks must be compatible.
3675 if (ExtraMask & ExistingMask)
3678 SDValue OldBFIVal = BFI.getOperand(0);
3679 SDValue NewBFIVal = BFI.getOperand(1);
3681 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
3682 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
3683 // need to be made compatible.
3684 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
3685 && "Invalid types for BFI");
3686 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
3687 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
3690 // We need the MaskedBFI to be combined with a mask of the *same* value.
3691 if (PossExtraMask.getOperand(0) != OldBFIVal)
3694 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3695 OldBFIVal, NewBFIVal,
3696 BFI.getOperand(2), BFI.getOperand(3));
3698 // If the masking is trivial, we don't need to create it.
3699 if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3702 return DAG.getNode(ISD::AND, DL, VT, BFI,
3703 DAG.getConstant(ExtraMask | ExistingMask, VT));
3706 /// An EXTR instruction is made up of two shifts, ORed together. This helper
3707 /// searches for and classifies those shifts.
3708 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
3710 if (N.getOpcode() == ISD::SHL)
3712 else if (N.getOpcode() == ISD::SRL)
3717 if (!isa<ConstantSDNode>(N.getOperand(1)))
3720 ShiftAmount = N->getConstantOperandVal(1);
3721 Src = N->getOperand(0);
3725 /// EXTR instruction extracts a contiguous chunk of bits from two existing
3726 /// registers viewed as a high/low pair. This function looks for the pattern:
3727 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
3728 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
3730 static SDValue tryCombineToEXTR(SDNode *N,
3731 TargetLowering::DAGCombinerInfo &DCI) {
3732 SelectionDAG &DAG = DCI.DAG;
3734 EVT VT = N->getValueType(0);
3736 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3738 if (VT != MVT::i32 && VT != MVT::i64)
3742 uint32_t ShiftLHS = 0;
3744 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
3748 uint32_t ShiftRHS = 0;
3750 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
3753 // If they're both trying to come from the high part of the register, they're
3754 // not really an EXTR.
3755 if (LHSFromHi == RHSFromHi)
3758 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
3762 std::swap(LHS, RHS);
3763 std::swap(ShiftLHS, ShiftRHS);
3766 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
3768 DAG.getConstant(ShiftRHS, MVT::i64));
3771 /// Target-specific dag combine xforms for ISD::OR
3772 static SDValue PerformORCombine(SDNode *N,
3773 TargetLowering::DAGCombinerInfo &DCI,
3774 const AArch64Subtarget *Subtarget) {
3776 SelectionDAG &DAG = DCI.DAG;
3778 EVT VT = N->getValueType(0);
3780 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3783 // Attempt to recognise bitfield-insert operations.
3784 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
3788 // Attempt to combine an existing MaskedBFI operation into one with a larger
3790 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
3794 Res = tryCombineToEXTR(N, DCI);
3798 if (!Subtarget->hasNEON())
3801 // Attempt to use vector immediate-form BSL
3802 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
3804 SDValue N0 = N->getOperand(0);
3805 if (N0.getOpcode() != ISD::AND)
3808 SDValue N1 = N->getOperand(1);
3809 if (N1.getOpcode() != ISD::AND)
3812 if (VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
3814 unsigned SplatBitSize;
3816 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
3818 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
3821 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
3823 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
3824 HasAnyUndefs) && !HasAnyUndefs &&
3825 SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
3826 SplatBits0 == ~SplatBits1) {
3828 return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1),
3829 N0->getOperand(0), N1->getOperand(0));
3837 /// Target-specific dag combine xforms for ISD::SRA
3838 static SDValue PerformSRACombine(SDNode *N,
3839 TargetLowering::DAGCombinerInfo &DCI) {
3841 SelectionDAG &DAG = DCI.DAG;
3843 EVT VT = N->getValueType(0);
3845 // We're looking for an SRA/SHL pair which form an SBFX.
3847 if (VT != MVT::i32 && VT != MVT::i64)
3850 if (!isa<ConstantSDNode>(N->getOperand(1)))
3853 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
3854 SDValue Shift = N->getOperand(0);
3856 if (Shift.getOpcode() != ISD::SHL)
3859 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3862 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
3863 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
3864 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
3866 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3869 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
3870 DAG.getConstant(LSB, MVT::i64),
3871 DAG.getConstant(LSB + Width - 1, MVT::i64));
3874 /// Check if this is a valid build_vector for the immediate operand of
3875 /// a vector shift operation, where all the elements of the build_vector
3876 /// must have the same constant integer value.
3877 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3878 // Ignore bit_converts.
3879 while (Op.getOpcode() == ISD::BITCAST)
3880 Op = Op.getOperand(0);
3881 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3882 APInt SplatBits, SplatUndef;
3883 unsigned SplatBitSize;
3885 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3886 HasAnyUndefs, ElementBits) ||
3887 SplatBitSize > ElementBits)
3889 Cnt = SplatBits.getSExtValue();
3893 /// Check if this is a valid build_vector for the immediate operand of
3894 /// a vector shift left operation. That value must be in the range:
3895 /// 0 <= Value < ElementBits
3896 static bool isVShiftLImm(SDValue Op, EVT VT, int64_t &Cnt) {
3897 assert(VT.isVector() && "vector shift count is not a vector type");
3898 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3899 if (!getVShiftImm(Op, ElementBits, Cnt))
3901 return (Cnt >= 0 && Cnt < ElementBits);
3904 /// Check if this is a valid build_vector for the immediate operand of a
3905 /// vector shift right operation. The value must be in the range:
3906 /// 1 <= Value <= ElementBits
3907 static bool isVShiftRImm(SDValue Op, EVT VT, int64_t &Cnt) {
3908 assert(VT.isVector() && "vector shift count is not a vector type");
3909 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3910 if (!getVShiftImm(Op, ElementBits, Cnt))
3912 return (Cnt >= 1 && Cnt <= ElementBits);
3915 static SDValue GenForSextInreg(SDNode *N,
3916 TargetLowering::DAGCombinerInfo &DCI,
3917 EVT SrcVT, EVT DestVT, EVT SubRegVT,
3918 const int *Mask, SDValue Src) {
3919 SelectionDAG &DAG = DCI.DAG;
3921 = DAG.getNode(ISD::BITCAST, SDLoc(N), SrcVT, Src);
3923 = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), DestVT, Bitcast);
3925 = DAG.getVectorShuffle(DestVT, SDLoc(N), Sext, DAG.getUNDEF(DestVT), Mask);
3926 SDValue ExtractSubreg
3927 = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N),
3928 SubRegVT, ShuffleVec,
3929 DAG.getTargetConstant(AArch64::sub_64, MVT::i32)), 0);
3930 return ExtractSubreg;
3933 /// Checks for vector shifts and lowers them.
3934 static SDValue PerformShiftCombine(SDNode *N,
3935 TargetLowering::DAGCombinerInfo &DCI,
3936 const AArch64Subtarget *ST) {
3937 SelectionDAG &DAG = DCI.DAG;
3938 EVT VT = N->getValueType(0);
3939 if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64))
3940 return PerformSRACombine(N, DCI);
3942 // We're looking for an SRA/SHL pair to help generating instruction
3943 // sshll v0.8h, v0.8b, #0
3944 // The instruction STXL is also the alias of this instruction.
3946 // For example, for DAG like below,
3947 // v2i32 = sra (v2i32 (shl v2i32, 16)), 16
3948 // we can transform it into
3949 // v2i32 = EXTRACT_SUBREG
3950 // (v4i32 (suffle_vector
3951 // (v4i32 (sext (v4i16 (bitcast v2i32))),
3952 // undef, (0, 2, u, u)),
3955 // With this transformation we expect to generate "SSHLL + UZIP1"
3956 // Sometimes UZIP1 can be optimized away by combining with other context.
3957 int64_t ShrCnt, ShlCnt;
3958 if (N->getOpcode() == ISD::SRA
3959 && (VT == MVT::v2i32 || VT == MVT::v4i16)
3960 && isVShiftRImm(N->getOperand(1), VT, ShrCnt)
3961 && N->getOperand(0).getOpcode() == ISD::SHL
3962 && isVShiftRImm(N->getOperand(0).getOperand(1), VT, ShlCnt)) {
3963 SDValue Src = N->getOperand(0).getOperand(0);
3964 if (VT == MVT::v2i32 && ShrCnt == 16 && ShlCnt == 16) {
3965 // sext_inreg(v2i32, v2i16)
3966 // We essentially only care the Mask {0, 2, u, u}
3967 int Mask[4] = {0, 2, 4, 6};
3968 return GenForSextInreg(N, DCI, MVT::v4i16, MVT::v4i32, MVT::v2i32,
3971 else if (VT == MVT::v2i32 && ShrCnt == 24 && ShlCnt == 24) {
3972 // sext_inreg(v2i16, v2i8)
3973 // We essentially only care the Mask {0, u, 4, u, u, u, u, u, u, u, u, u}
3974 int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
3975 return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v2i32,
3978 else if (VT == MVT::v4i16 && ShrCnt == 8 && ShlCnt == 8) {
3979 // sext_inreg(v4i16, v4i8)
3980 // We essentially only care the Mask {0, 2, 4, 6, u, u, u, u, u, u, u, u}
3981 int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
3982 return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v4i16,
3987 // Nothing to be done for scalar shifts.
3988 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3989 if (!VT.isVector() || !TLI.isTypeLegal(VT))
3992 assert(ST->hasNEON() && "unexpected vector shift");
3995 switch (N->getOpcode()) {
3997 llvm_unreachable("unexpected shift opcode");
4000 if (isVShiftLImm(N->getOperand(1), VT, Cnt)) {
4002 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
4003 DAG.getConstant(Cnt, MVT::i32));
4004 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), RHS);
4010 if (isVShiftRImm(N->getOperand(1), VT, Cnt)) {
4012 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
4013 DAG.getConstant(Cnt, MVT::i32));
4014 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N->getOperand(0), RHS);
4022 /// ARM-specific DAG combining for intrinsics.
4023 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4024 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4028 // Don't do anything for most intrinsics.
4031 case Intrinsic::arm_neon_vqshifts:
4032 case Intrinsic::arm_neon_vqshiftu:
4033 EVT VT = N->getOperand(1).getValueType();
4035 if (!isVShiftLImm(N->getOperand(2), VT, Cnt))
4037 unsigned VShiftOpc = (IntNo == Intrinsic::arm_neon_vqshifts)
4038 ? AArch64ISD::NEON_QSHLs
4039 : AArch64ISD::NEON_QSHLu;
4040 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
4041 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4047 /// Target-specific DAG combine function for NEON load/store intrinsics
4048 /// to merge base address updates.
4049 static SDValue CombineBaseUpdate(SDNode *N,
4050 TargetLowering::DAGCombinerInfo &DCI) {
4051 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4054 SelectionDAG &DAG = DCI.DAG;
4055 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
4056 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
4057 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
4058 SDValue Addr = N->getOperand(AddrOpIdx);
4060 // Search for a use of the address operand that is an increment.
4061 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
4062 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
4064 if (User->getOpcode() != ISD::ADD ||
4065 UI.getUse().getResNo() != Addr.getResNo())
4068 // Check that the add is independent of the load/store. Otherwise, folding
4069 // it would create a cycle.
4070 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
4073 // Find the new opcode for the updating load/store.
4075 bool isLaneOp = false;
4076 unsigned NewOpc = 0;
4077 unsigned NumVecs = 0;
4079 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
4081 default: llvm_unreachable("unexpected intrinsic for Neon base update");
4082 case Intrinsic::arm_neon_vld1: NewOpc = AArch64ISD::NEON_LD1_UPD;
4084 case Intrinsic::arm_neon_vld2: NewOpc = AArch64ISD::NEON_LD2_UPD;
4086 case Intrinsic::arm_neon_vld3: NewOpc = AArch64ISD::NEON_LD3_UPD;
4088 case Intrinsic::arm_neon_vld4: NewOpc = AArch64ISD::NEON_LD4_UPD;
4090 case Intrinsic::arm_neon_vst1: NewOpc = AArch64ISD::NEON_ST1_UPD;
4091 NumVecs = 1; isLoad = false; break;
4092 case Intrinsic::arm_neon_vst2: NewOpc = AArch64ISD::NEON_ST2_UPD;
4093 NumVecs = 2; isLoad = false; break;
4094 case Intrinsic::arm_neon_vst3: NewOpc = AArch64ISD::NEON_ST3_UPD;
4095 NumVecs = 3; isLoad = false; break;
4096 case Intrinsic::arm_neon_vst4: NewOpc = AArch64ISD::NEON_ST4_UPD;
4097 NumVecs = 4; isLoad = false; break;
4098 case Intrinsic::aarch64_neon_vld1x2: NewOpc = AArch64ISD::NEON_LD1x2_UPD;
4100 case Intrinsic::aarch64_neon_vld1x3: NewOpc = AArch64ISD::NEON_LD1x3_UPD;
4102 case Intrinsic::aarch64_neon_vld1x4: NewOpc = AArch64ISD::NEON_LD1x4_UPD;
4104 case Intrinsic::aarch64_neon_vst1x2: NewOpc = AArch64ISD::NEON_ST1x2_UPD;
4105 NumVecs = 2; isLoad = false; break;
4106 case Intrinsic::aarch64_neon_vst1x3: NewOpc = AArch64ISD::NEON_ST1x3_UPD;
4107 NumVecs = 3; isLoad = false; break;
4108 case Intrinsic::aarch64_neon_vst1x4: NewOpc = AArch64ISD::NEON_ST1x4_UPD;
4109 NumVecs = 4; isLoad = false; break;
4110 case Intrinsic::arm_neon_vld2lane: NewOpc = AArch64ISD::NEON_LD2LN_UPD;
4111 NumVecs = 2; isLaneOp = true; break;
4112 case Intrinsic::arm_neon_vld3lane: NewOpc = AArch64ISD::NEON_LD3LN_UPD;
4113 NumVecs = 3; isLaneOp = true; break;
4114 case Intrinsic::arm_neon_vld4lane: NewOpc = AArch64ISD::NEON_LD4LN_UPD;
4115 NumVecs = 4; isLaneOp = true; break;
4116 case Intrinsic::arm_neon_vst2lane: NewOpc = AArch64ISD::NEON_ST2LN_UPD;
4117 NumVecs = 2; isLoad = false; isLaneOp = true; break;
4118 case Intrinsic::arm_neon_vst3lane: NewOpc = AArch64ISD::NEON_ST3LN_UPD;
4119 NumVecs = 3; isLoad = false; isLaneOp = true; break;
4120 case Intrinsic::arm_neon_vst4lane: NewOpc = AArch64ISD::NEON_ST4LN_UPD;
4121 NumVecs = 4; isLoad = false; isLaneOp = true; break;
4125 switch (N->getOpcode()) {
4126 default: llvm_unreachable("unexpected opcode for Neon base update");
4127 case AArch64ISD::NEON_LD2DUP: NewOpc = AArch64ISD::NEON_LD2DUP_UPD;
4129 case AArch64ISD::NEON_LD3DUP: NewOpc = AArch64ISD::NEON_LD3DUP_UPD;
4131 case AArch64ISD::NEON_LD4DUP: NewOpc = AArch64ISD::NEON_LD4DUP_UPD;
4136 // Find the size of memory referenced by the load/store.
4139 VecTy = N->getValueType(0);
4141 VecTy = N->getOperand(AddrOpIdx + 1).getValueType();
4142 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
4144 NumBytes /= VecTy.getVectorNumElements();
4146 // If the increment is a constant, it must match the memory ref size.
4147 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
4148 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
4149 uint32_t IncVal = CInc->getZExtValue();
4150 if (IncVal != NumBytes)
4152 Inc = DAG.getTargetConstant(IncVal, MVT::i32);
4155 // Create the new updating load/store node.
4157 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
4159 for (n = 0; n < NumResultVecs; ++n)
4161 Tys[n++] = MVT::i64;
4162 Tys[n] = MVT::Other;
4163 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs + 2);
4164 SmallVector<SDValue, 8> Ops;
4165 Ops.push_back(N->getOperand(0)); // incoming chain
4166 Ops.push_back(N->getOperand(AddrOpIdx));
4168 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
4169 Ops.push_back(N->getOperand(i));
4171 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
4172 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
4173 Ops.data(), Ops.size(),
4174 MemInt->getMemoryVT(),
4175 MemInt->getMemOperand());
4178 std::vector<SDValue> NewResults;
4179 for (unsigned i = 0; i < NumResultVecs; ++i) {
4180 NewResults.push_back(SDValue(UpdN.getNode(), i));
4182 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); // chain
4183 DCI.CombineTo(N, NewResults);
4184 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
4191 /// For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1)
4192 /// intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
4193 /// If so, combine them to a vldN-dup operation and return true.
4194 static SDValue CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
4195 SelectionDAG &DAG = DCI.DAG;
4196 EVT VT = N->getValueType(0);
4198 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
4199 SDNode *VLD = N->getOperand(0).getNode();
4200 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
4202 unsigned NumVecs = 0;
4203 unsigned NewOpc = 0;
4204 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
4205 if (IntNo == Intrinsic::arm_neon_vld2lane) {
4207 NewOpc = AArch64ISD::NEON_LD2DUP;
4208 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
4210 NewOpc = AArch64ISD::NEON_LD3DUP;
4211 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
4213 NewOpc = AArch64ISD::NEON_LD4DUP;
4218 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
4219 // numbers match the load.
4220 unsigned VLDLaneNo =
4221 cast<ConstantSDNode>(VLD->getOperand(NumVecs + 3))->getZExtValue();
4222 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4224 // Ignore uses of the chain result.
4225 if (UI.getUse().getResNo() == NumVecs)
4228 if (User->getOpcode() != AArch64ISD::NEON_VDUPLANE ||
4229 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
4233 // Create the vldN-dup node.
4236 for (n = 0; n < NumVecs; ++n)
4238 Tys[n] = MVT::Other;
4239 SDVTList SDTys = DAG.getVTList(Tys, NumVecs + 1);
4240 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
4241 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
4242 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, Ops, 2,
4243 VLDMemInt->getMemoryVT(),
4244 VLDMemInt->getMemOperand());
4247 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4249 unsigned ResNo = UI.getUse().getResNo();
4250 // Ignore uses of the chain result.
4251 if (ResNo == NumVecs)
4254 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
4257 // Now the vldN-lane intrinsic is dead except for its chain result.
4258 // Update uses of the chain.
4259 std::vector<SDValue> VLDDupResults;
4260 for (unsigned n = 0; n < NumVecs; ++n)
4261 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
4262 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
4263 DCI.CombineTo(VLD, VLDDupResults);
4265 return SDValue(N, 0);
4269 // v1i1 (bitcast (i1 setcc (extract_vector_elt, extract_vector_elt))
4270 // FIXME: Currently the type legalizer can't handle SETCC having v1i1 as result.
4271 // If it can legalize "v1i1 SETCC" correctly, no need to combine such SETCC.
4272 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
4273 EVT ResVT = N->getValueType(0);
4275 if (!ResVT.isVector() || ResVT.getVectorNumElements() != 1 ||
4276 ResVT.getVectorElementType() != MVT::i1)
4279 SDValue LHS = N->getOperand(0);
4280 SDValue RHS = N->getOperand(1);
4281 EVT CmpVT = LHS.getValueType();
4282 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
4283 CmpVT.getVectorElementType(), LHS,
4284 DAG.getConstant(0, MVT::i64));
4285 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
4286 CmpVT.getVectorElementType(), RHS,
4287 DAG.getConstant(0, MVT::i64));
4289 DAG.getSetCC(SDLoc(N), MVT::i1, LHS, RHS,
4290 cast<CondCodeSDNode>(N->getOperand(2))->get());
4291 return DAG.getNode(ISD::BITCAST, SDLoc(N), ResVT, SetCC);
4294 // vselect (v1i1 setcc) ->
4295 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
4296 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
4297 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
4299 static SDValue PerformVSelectCombine(SDNode *N, SelectionDAG &DAG) {
4300 SDValue N0 = N->getOperand(0);
4301 EVT CCVT = N0.getValueType();
4303 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
4304 CCVT.getVectorElementType() != MVT::i1)
4307 EVT ResVT = N->getValueType(0);
4308 EVT CmpVT = N0.getOperand(0).getValueType();
4309 // Only combine when the result type is of the same size as the compared
4311 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
4314 SDValue IfTrue = N->getOperand(1);
4315 SDValue IfFalse = N->getOperand(2);
4317 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
4318 N0.getOperand(0), N0.getOperand(1),
4319 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4320 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
4324 // sign_extend (extract_vector_elt (v1i1 setcc)) ->
4325 // extract_vector_elt (v1iXX setcc)
4326 // (XX is the size of the compared operand type)
4327 static SDValue PerformSignExtendCombine(SDNode *N, SelectionDAG &DAG) {
4328 SDValue N0 = N->getOperand(0);
4329 SDValue Vec = N0.getOperand(0);
4331 if (N0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4332 Vec.getOpcode() != ISD::SETCC)
4335 EVT ResVT = N->getValueType(0);
4336 EVT CmpVT = Vec.getOperand(0).getValueType();
4337 // Only optimize when the result type is of the same size as the element
4338 // type of the compared operand.
4339 if (ResVT.getSizeInBits() != CmpVT.getVectorElementType().getSizeInBits())
4342 SDValue Lane = N0.getOperand(1);
4344 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
4345 Vec.getOperand(0), Vec.getOperand(1),
4346 cast<CondCodeSDNode>(Vec.getOperand(2))->get());
4347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ResVT,
4352 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
4353 DAGCombinerInfo &DCI) const {
4354 switch (N->getOpcode()) {
4356 case ISD::AND: return PerformANDCombine(N, DCI);
4357 case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
4361 return PerformShiftCombine(N, DCI, getSubtarget());
4362 case ISD::SETCC: return PerformSETCCCombine(N, DCI.DAG);
4363 case ISD::VSELECT: return PerformVSelectCombine(N, DCI.DAG);
4364 case ISD::SIGN_EXTEND: return PerformSignExtendCombine(N, DCI.DAG);
4365 case ISD::INTRINSIC_WO_CHAIN:
4366 return PerformIntrinsicCombine(N, DCI.DAG);
4367 case AArch64ISD::NEON_VDUPLANE:
4368 return CombineVLDDUP(N, DCI);
4369 case AArch64ISD::NEON_LD2DUP:
4370 case AArch64ISD::NEON_LD3DUP:
4371 case AArch64ISD::NEON_LD4DUP:
4372 return CombineBaseUpdate(N, DCI);
4373 case ISD::INTRINSIC_VOID:
4374 case ISD::INTRINSIC_W_CHAIN:
4375 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
4376 case Intrinsic::arm_neon_vld1:
4377 case Intrinsic::arm_neon_vld2:
4378 case Intrinsic::arm_neon_vld3:
4379 case Intrinsic::arm_neon_vld4:
4380 case Intrinsic::arm_neon_vst1:
4381 case Intrinsic::arm_neon_vst2:
4382 case Intrinsic::arm_neon_vst3:
4383 case Intrinsic::arm_neon_vst4:
4384 case Intrinsic::arm_neon_vld2lane:
4385 case Intrinsic::arm_neon_vld3lane:
4386 case Intrinsic::arm_neon_vld4lane:
4387 case Intrinsic::aarch64_neon_vld1x2:
4388 case Intrinsic::aarch64_neon_vld1x3:
4389 case Intrinsic::aarch64_neon_vld1x4:
4390 case Intrinsic::aarch64_neon_vst1x2:
4391 case Intrinsic::aarch64_neon_vst1x3:
4392 case Intrinsic::aarch64_neon_vst1x4:
4393 case Intrinsic::arm_neon_vst2lane:
4394 case Intrinsic::arm_neon_vst3lane:
4395 case Intrinsic::arm_neon_vst4lane:
4396 return CombineBaseUpdate(N, DCI);
4405 AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
4406 VT = VT.getScalarType();
4411 switch (VT.getSimpleVT().SimpleTy) {
4424 // Check whether a shuffle_vector could be presented as concat_vector.
4425 bool AArch64TargetLowering::isConcatVector(SDValue Op, SelectionDAG &DAG,
4426 SDValue V0, SDValue V1,
4428 SDValue &Res) const {
4430 EVT VT = Op.getValueType();
4431 if (VT.getSizeInBits() != 128)
4433 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4434 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4437 unsigned NumElts = VT.getVectorNumElements();
4438 bool isContactVector = true;
4439 bool splitV0 = false;
4440 if (V0.getValueType().getSizeInBits() == 128)
4443 for (int I = 0, E = NumElts / 2; I != E; I++) {
4445 isContactVector = false;
4450 if (isContactVector) {
4451 int offset = NumElts / 2;
4452 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4453 if (Mask[I] != I + splitV0 * offset) {
4454 isContactVector = false;
4460 if (isContactVector) {
4461 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4464 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4465 DAG.getConstant(0, MVT::i64));
4467 if (V1.getValueType().getSizeInBits() == 128) {
4468 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4469 DAG.getConstant(0, MVT::i64));
4471 Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4477 // Check whether a Build Vector could be presented as Shuffle Vector.
4478 // This Shuffle Vector maybe not legalized, so the length of its operand and
4479 // the length of result may not equal.
4480 bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
4481 SDValue &V0, SDValue &V1,
4484 EVT VT = Op.getValueType();
4485 unsigned NumElts = VT.getVectorNumElements();
4486 unsigned V0NumElts = 0;
4488 // Check if all elements are extracted from less than 3 vectors.
4489 for (unsigned i = 0; i < NumElts; ++i) {
4490 SDValue Elt = Op.getOperand(i);
4491 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4492 Elt.getOperand(0).getValueType().getVectorElementType() !=
4493 VT.getVectorElementType())
4496 if (V0.getNode() == 0) {
4497 V0 = Elt.getOperand(0);
4498 V0NumElts = V0.getValueType().getVectorNumElements();
4500 if (Elt.getOperand(0) == V0) {
4501 Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue());
4503 } else if (V1.getNode() == 0) {
4504 V1 = Elt.getOperand(0);
4506 if (Elt.getOperand(0) == V1) {
4507 unsigned Lane = cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue();
4508 Mask[i] = (Lane + V0NumElts);
4517 // If this is a case we can't handle, return null and let the default
4518 // expansion code take care of it.
4520 AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4521 const AArch64Subtarget *ST) const {
4523 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4525 EVT VT = Op.getValueType();
4527 APInt SplatBits, SplatUndef;
4528 unsigned SplatBitSize;
4531 unsigned UseNeonMov = VT.getSizeInBits() >= 64;
4533 // Note we favor lowering MOVI over MVNI.
4534 // This has implications on the definition of patterns in TableGen to select
4535 // BIC immediate instructions but not ORR immediate instructions.
4536 // If this lowering order is changed, TableGen patterns for BIC immediate and
4537 // ORR immediate instructions have to be updated.
4539 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4540 if (SplatBitSize <= 64) {
4541 // First attempt to use vector immediate-form MOVI
4544 unsigned OpCmode = 0;
4546 if (isNeonModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
4547 SplatBitSize, DAG, VT.is128BitVector(),
4548 Neon_Mov_Imm, NeonMovVT, Imm, OpCmode)) {
4549 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4550 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4552 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4553 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MOVIMM, DL, NeonMovVT,
4554 ImmVal, OpCmodeVal);
4555 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4559 // Then attempt to use vector immediate-form MVNI
4560 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4561 if (isNeonModifiedImm(NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
4562 DAG, VT.is128BitVector(), Neon_Mvn_Imm, NeonMovVT,
4564 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4565 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4566 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4567 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MVNIMM, DL, NeonMovVT,
4568 ImmVal, OpCmodeVal);
4569 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4573 // Attempt to use vector immediate-form FMOV
4574 if (((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) ||
4575 (VT == MVT::v2f64 && SplatBitSize == 64)) {
4577 SplatBitSize == 32 ? APFloat::IEEEsingle : APFloat::IEEEdouble,
4580 if (A64Imms::isFPImm(RealVal, ImmVal)) {
4581 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4582 return DAG.getNode(AArch64ISD::NEON_FMOVIMM, DL, VT, Val);
4588 unsigned NumElts = VT.getVectorNumElements();
4589 bool isOnlyLowElement = true;
4590 bool usesOnlyOneValue = true;
4591 bool hasDominantValue = false;
4592 bool isConstant = true;
4594 // Map of the number of times a particular SDValue appears in the
4596 DenseMap<SDValue, unsigned> ValueCounts;
4598 for (unsigned i = 0; i < NumElts; ++i) {
4599 SDValue V = Op.getOperand(i);
4600 if (V.getOpcode() == ISD::UNDEF)
4603 isOnlyLowElement = false;
4604 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4607 ValueCounts.insert(std::make_pair(V, 0));
4608 unsigned &Count = ValueCounts[V];
4610 // Is this value dominant? (takes up more than half of the lanes)
4611 if (++Count > (NumElts / 2)) {
4612 hasDominantValue = true;
4616 if (ValueCounts.size() != 1)
4617 usesOnlyOneValue = false;
4618 if (!Value.getNode() && ValueCounts.size() > 0)
4619 Value = ValueCounts.begin()->first;
4621 if (ValueCounts.size() == 0)
4622 return DAG.getUNDEF(VT);
4624 if (isOnlyLowElement)
4625 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4627 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4628 if (hasDominantValue && EltSize <= 64) {
4629 // Use VDUP for non-constant splats.
4633 // If we are DUPing a value that comes directly from a vector, we could
4634 // just use DUPLANE. We can only do this if the lane being extracted
4635 // is at a constant index, as the DUP from lane instructions only have
4636 // constant-index forms.
4638 // If there is a TRUNCATE between EXTRACT_VECTOR_ELT and DUP, we can
4639 // remove TRUNCATE for DUPLANE by apdating the source vector to
4640 // appropriate vector type and lane index.
4642 // FIXME: for now we have v1i8, v1i16, v1i32 legal vector types, if they
4643 // are not legal any more, no need to check the type size in bits should
4644 // be large than 64.
4646 if (Value->getOpcode() == ISD::TRUNCATE)
4647 V = Value->getOperand(0);
4648 if (V->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4649 isa<ConstantSDNode>(V->getOperand(1)) &&
4650 V->getOperand(0).getValueType().getSizeInBits() >= 64) {
4652 // If the element size of source vector is larger than DUPLANE
4653 // element size, we can do transformation by,
4654 // 1) bitcasting source register to smaller element vector
4655 // 2) mutiplying the lane index by SrcEltSize/ResEltSize
4656 // For example, we can lower
4657 // "v8i16 vdup_lane(v4i32, 1)"
4659 // "v8i16 vdup_lane(v8i16 bitcast(v4i32), 2)".
4660 SDValue SrcVec = V->getOperand(0);
4661 unsigned SrcEltSize =
4662 SrcVec.getValueType().getVectorElementType().getSizeInBits();
4663 unsigned ResEltSize = VT.getVectorElementType().getSizeInBits();
4664 if (SrcEltSize > ResEltSize) {
4665 assert((SrcEltSize % ResEltSize == 0) && "Invalid element size");
4667 unsigned SrcSize = SrcVec.getValueType().getSizeInBits();
4668 unsigned ResSize = VT.getSizeInBits();
4670 if (SrcSize > ResSize) {
4671 assert((SrcSize % ResSize == 0) && "Invalid vector size");
4673 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4674 SrcSize / ResEltSize);
4675 BitCast = DAG.getNode(ISD::BITCAST, DL, CastVT, SrcVec);
4677 assert((SrcSize == ResSize) && "Invalid vector size of source vec");
4678 BitCast = DAG.getNode(ISD::BITCAST, DL, VT, SrcVec);
4681 unsigned LaneIdx = V->getConstantOperandVal(1);
4683 DAG.getConstant((SrcEltSize / ResEltSize) * LaneIdx, MVT::i64);
4684 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, BitCast, Lane);
4686 assert((SrcEltSize == ResEltSize) &&
4687 "Invalid element size of source vec");
4688 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, V->getOperand(0),
4692 N = DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4694 if (!usesOnlyOneValue) {
4695 // The dominant value was splatted as 'N', but we now have to insert
4696 // all differing elements.
4697 for (unsigned I = 0; I < NumElts; ++I) {
4698 if (Op.getOperand(I) == Value)
4700 SmallVector<SDValue, 3> Ops;
4702 Ops.push_back(Op.getOperand(I));
4703 Ops.push_back(DAG.getConstant(I, MVT::i64));
4704 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
4709 if (usesOnlyOneValue && isConstant) {
4710 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4713 // If all elements are constants and the case above didn't get hit, fall back
4714 // to the default expansion, which will generate a load from the constant
4719 // Try to lower this in lowering ShuffleVector way.
4722 if (isKnownShuffleVector(Op, DAG, V0, V1, Mask)) {
4723 unsigned V0NumElts = V0.getValueType().getVectorNumElements();
4724 if (!V1.getNode() && V0NumElts == NumElts * 2) {
4725 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
4726 DAG.getConstant(NumElts, MVT::i64));
4727 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
4728 DAG.getConstant(0, MVT::i64));
4729 V0NumElts = V0.getValueType().getVectorNumElements();
4732 if (V1.getNode() && NumElts == V0NumElts &&
4733 V0NumElts == V1.getValueType().getVectorNumElements()) {
4734 SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
4735 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
4738 return LowerVECTOR_SHUFFLE(Shuffle, DAG);
4741 if (isConcatVector(Op, DAG, V0, V1, Mask, Res))
4746 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4747 // know the default expansion would otherwise fall back on something even
4748 // worse. For a vector with one or two non-undef values, that's
4749 // scalar_to_vector for the elements followed by a shuffle (provided the
4750 // shuffle is valid for the target) and materialization element by element
4751 // on the stack followed by a load for everything else.
4752 if (!isConstant && !usesOnlyOneValue) {
4753 SDValue Vec = DAG.getUNDEF(VT);
4754 for (unsigned i = 0 ; i < NumElts; ++i) {
4755 SDValue V = Op.getOperand(i);
4756 if (V.getOpcode() == ISD::UNDEF)
4758 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
4759 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, LaneIdx);
4766 /// isREVMask - Check if a vector shuffle corresponds to a REV
4767 /// instruction with the specified blocksize. (The order of the elements
4768 /// within each block of the vector is reversed.)
4769 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4770 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4771 "Only possible block sizes for REV are: 16, 32, 64");
4773 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4777 unsigned NumElts = VT.getVectorNumElements();
4778 unsigned BlockElts = M[0] + 1;
4779 // If the first shuffle index is UNDEF, be optimistic.
4781 BlockElts = BlockSize / EltSz;
4783 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4786 for (unsigned i = 0; i < NumElts; ++i) {
4788 continue; // ignore UNDEF indices
4789 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4796 // isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
4798 static unsigned isPermuteMask(ArrayRef<int> M, EVT VT, bool isV2undef) {
4799 unsigned NumElts = VT.getVectorNumElements();
4803 bool ismatch = true;
4806 for (unsigned i = 0; i < NumElts; ++i) {
4807 unsigned answer = i * 2;
4808 if (isV2undef && answer >= NumElts)
4810 if (M[i] != -1 && (unsigned)M[i] != answer) {
4816 return AArch64ISD::NEON_UZP1;
4820 for (unsigned i = 0; i < NumElts; ++i) {
4821 unsigned answer = i * 2 + 1;
4822 if (isV2undef && answer >= NumElts)
4824 if (M[i] != -1 && (unsigned)M[i] != answer) {
4830 return AArch64ISD::NEON_UZP2;
4834 for (unsigned i = 0; i < NumElts; ++i) {
4835 unsigned answer = i / 2 + NumElts * (i % 2);
4836 if (isV2undef && answer >= NumElts)
4838 if (M[i] != -1 && (unsigned)M[i] != answer) {
4844 return AArch64ISD::NEON_ZIP1;
4848 for (unsigned i = 0; i < NumElts; ++i) {
4849 unsigned answer = (NumElts + i) / 2 + NumElts * (i % 2);
4850 if (isV2undef && answer >= NumElts)
4852 if (M[i] != -1 && (unsigned)M[i] != answer) {
4858 return AArch64ISD::NEON_ZIP2;
4862 for (unsigned i = 0; i < NumElts; ++i) {
4863 unsigned answer = i + (NumElts - 1) * (i % 2);
4864 if (isV2undef && answer >= NumElts)
4866 if (M[i] != -1 && (unsigned)M[i] != answer) {
4872 return AArch64ISD::NEON_TRN1;
4876 for (unsigned i = 0; i < NumElts; ++i) {
4877 unsigned answer = 1 + i + (NumElts - 1) * (i % 2);
4878 if (isV2undef && answer >= NumElts)
4880 if (M[i] != -1 && (unsigned)M[i] != answer) {
4886 return AArch64ISD::NEON_TRN2;
4892 AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4893 SelectionDAG &DAG) const {
4894 SDValue V1 = Op.getOperand(0);
4895 SDValue V2 = Op.getOperand(1);
4897 EVT VT = Op.getValueType();
4898 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4900 // Convert shuffles that are directly supported on NEON to target-specific
4901 // DAG nodes, instead of keeping them as shuffles and matching them again
4902 // during code selection. This is more efficient and avoids the possibility
4903 // of inconsistencies between legalization and selection.
4904 ArrayRef<int> ShuffleMask = SVN->getMask();
4906 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4910 if (isREVMask(ShuffleMask, VT, 64))
4911 return DAG.getNode(AArch64ISD::NEON_REV64, dl, VT, V1);
4912 if (isREVMask(ShuffleMask, VT, 32))
4913 return DAG.getNode(AArch64ISD::NEON_REV32, dl, VT, V1);
4914 if (isREVMask(ShuffleMask, VT, 16))
4915 return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1);
4918 if (V2.getOpcode() == ISD::UNDEF)
4919 ISDNo = isPermuteMask(ShuffleMask, VT, true);
4921 ISDNo = isPermuteMask(ShuffleMask, VT, false);
4924 if (V2.getOpcode() == ISD::UNDEF)
4925 return DAG.getNode(ISDNo, dl, VT, V1, V1);
4927 return DAG.getNode(ISDNo, dl, VT, V1, V2);
4931 if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
4934 // If the element of shuffle mask are all the same constant, we can
4935 // transform it into either NEON_VDUP or NEON_VDUPLANE
4936 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4937 int Lane = SVN->getSplatIndex();
4938 // If this is undef splat, generate it via "just" vdup, if possible.
4939 if (Lane == -1) Lane = 0;
4941 // Test if V1 is a SCALAR_TO_VECTOR.
4942 if (V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4943 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(0));
4945 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR.
4946 if (V1.getOpcode() == ISD::BUILD_VECTOR) {
4947 bool IsScalarToVector = true;
4948 for (unsigned i = 0, e = V1.getNumOperands(); i != e; ++i)
4949 if (V1.getOperand(i).getOpcode() != ISD::UNDEF &&
4950 i != (unsigned)Lane) {
4951 IsScalarToVector = false;
4954 if (IsScalarToVector)
4955 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT,
4956 V1.getOperand(Lane));
4959 // Test if V1 is a EXTRACT_SUBVECTOR.
4960 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4961 int ExtLane = cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4962 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
4963 DAG.getConstant(Lane + ExtLane, MVT::i64));
4965 // Test if V1 is a CONCAT_VECTORS.
4966 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
4967 V1.getOperand(1).getOpcode() == ISD::UNDEF) {
4968 SDValue Op0 = V1.getOperand(0);
4969 assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
4970 "Invalid vector lane access");
4971 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
4972 DAG.getConstant(Lane, MVT::i64));
4975 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,
4976 DAG.getConstant(Lane, MVT::i64));
4979 int Length = ShuffleMask.size();
4980 int V1EltNum = V1.getValueType().getVectorNumElements();
4982 // If the number of v1 elements is the same as the number of shuffle mask
4983 // element and the shuffle masks are sequential values, we can transform
4984 // it into NEON_VEXTRACT.
4985 if (V1EltNum == Length) {
4986 // Check if the shuffle mask is sequential.
4988 while (ShuffleMask[SkipUndef] == -1) {
4991 int CurMask = ShuffleMask[SkipUndef];
4992 if (CurMask >= SkipUndef) {
4993 bool IsSequential = true;
4994 for (int I = SkipUndef; I < Length; ++I) {
4995 if (ShuffleMask[I] != -1 && ShuffleMask[I] != CurMask) {
4996 IsSequential = false;
5002 assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect");
5003 unsigned VecSize = EltSize * V1EltNum;
5004 unsigned Index = (EltSize / 8) * (ShuffleMask[SkipUndef] - SkipUndef);
5005 if (VecSize == 64 || VecSize == 128)
5006 return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2,
5007 DAG.getConstant(Index, MVT::i64));
5012 // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert
5013 // by element from V2 to V1 .
5014 // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a
5015 // better choice to be inserted than V1 as less insert needed, so we count
5016 // element to be inserted for both V1 and V2, and select less one as insert
5019 // Collect elements need to be inserted and their index.
5020 SmallVector<int, 8> NV1Elt;
5021 SmallVector<int, 8> N1Index;
5022 SmallVector<int, 8> NV2Elt;
5023 SmallVector<int, 8> N2Index;
5024 for (int I = 0; I != Length; ++I) {
5025 if (ShuffleMask[I] != I) {
5026 NV1Elt.push_back(ShuffleMask[I]);
5027 N1Index.push_back(I);
5030 for (int I = 0; I != Length; ++I) {
5031 if (ShuffleMask[I] != (I + V1EltNum)) {
5032 NV2Elt.push_back(ShuffleMask[I]);
5033 N2Index.push_back(I);
5037 // Decide which to be inserted. If all lanes mismatch, neither V1 nor V2
5038 // will be inserted.
5040 SmallVector<int, 8> InsMasks = NV1Elt;
5041 SmallVector<int, 8> InsIndex = N1Index;
5042 if ((int)NV1Elt.size() != Length || (int)NV2Elt.size() != Length) {
5043 if (NV1Elt.size() > NV2Elt.size()) {
5049 InsV = DAG.getNode(ISD::UNDEF, dl, VT);
5052 for (int I = 0, E = InsMasks.size(); I != E; ++I) {
5054 int Mask = InsMasks[I];
5055 if (Mask >= V1EltNum) {
5059 // Any value type smaller than i32 is illegal in AArch64, and this lower
5060 // function is called after legalize pass, so we need to legalize
5063 if (VT.getVectorElementType().isFloatingPoint())
5064 EltVT = (EltSize == 64) ? MVT::f64 : MVT::f32;
5066 EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32;
5069 ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
5070 DAG.getConstant(Mask, MVT::i64));
5071 InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV,
5072 DAG.getConstant(InsIndex[I], MVT::i64));
5078 AArch64TargetLowering::ConstraintType
5079 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
5080 if (Constraint.size() == 1) {
5081 switch (Constraint[0]) {
5083 case 'w': // An FP/SIMD vector register
5084 return C_RegisterClass;
5085 case 'I': // Constant that can be used with an ADD instruction
5086 case 'J': // Constant that can be used with a SUB instruction
5087 case 'K': // Constant that can be used with a 32-bit logical instruction
5088 case 'L': // Constant that can be used with a 64-bit logical instruction
5089 case 'M': // Constant that can be used as a 32-bit MOV immediate
5090 case 'N': // Constant that can be used as a 64-bit MOV immediate
5091 case 'Y': // Floating point constant zero
5092 case 'Z': // Integer constant zero
5094 case 'Q': // A memory reference with base register and no offset
5096 case 'S': // A symbolic address
5101 // FIXME: Ump, Utf, Usa, Ush
5102 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
5103 // whatever they may be
5104 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
5105 // Usa: An absolute symbolic address
5106 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
5107 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
5108 && Constraint != "Ush" && "Unimplemented constraints");
5110 return TargetLowering::getConstraintType(Constraint);
5113 TargetLowering::ConstraintWeight
5114 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
5115 const char *Constraint) const {
5117 llvm_unreachable("Constraint weight unimplemented");
5121 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5122 std::string &Constraint,
5123 std::vector<SDValue> &Ops,
5124 SelectionDAG &DAG) const {
5125 SDValue Result(0, 0);
5127 // Only length 1 constraints are C_Other.
5128 if (Constraint.size() != 1) return;
5130 // Only C_Other constraints get lowered like this. That means constants for us
5131 // so return early if there's no hope the constraint can be lowered.
5133 switch(Constraint[0]) {
5135 case 'I': case 'J': case 'K': case 'L':
5136 case 'M': case 'N': case 'Z': {
5137 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5141 uint64_t CVal = C->getZExtValue();
5144 switch (Constraint[0]) {
5146 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
5147 // is a peculiarly useless SUB constraint.
5148 llvm_unreachable("Unimplemented C_Other constraint");
5154 if (A64Imms::isLogicalImm(32, CVal, Bits))
5158 if (A64Imms::isLogicalImm(64, CVal, Bits))
5167 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5171 // An absolute symbolic address or label reference.
5172 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
5173 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
5174 GA->getValueType(0));
5175 } else if (const BlockAddressSDNode *BA
5176 = dyn_cast<BlockAddressSDNode>(Op)) {
5177 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
5178 BA->getValueType(0));
5179 } else if (const ExternalSymbolSDNode *ES
5180 = dyn_cast<ExternalSymbolSDNode>(Op)) {
5181 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
5182 ES->getValueType(0));
5188 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
5189 if (CFP->isExactlyValue(0.0)) {
5190 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
5197 if (Result.getNode()) {
5198 Ops.push_back(Result);
5202 // It's an unknown constraint for us. Let generic code have a go.
5203 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5206 std::pair<unsigned, const TargetRegisterClass*>
5207 AArch64TargetLowering::getRegForInlineAsmConstraint(
5208 const std::string &Constraint,
5210 if (Constraint.size() == 1) {
5211 switch (Constraint[0]) {
5213 if (VT.getSizeInBits() <= 32)
5214 return std::make_pair(0U, &AArch64::GPR32RegClass);
5215 else if (VT == MVT::i64)
5216 return std::make_pair(0U, &AArch64::GPR64RegClass);
5220 return std::make_pair(0U, &AArch64::FPR16RegClass);
5221 else if (VT == MVT::f32)
5222 return std::make_pair(0U, &AArch64::FPR32RegClass);
5223 else if (VT.getSizeInBits() == 64)
5224 return std::make_pair(0U, &AArch64::FPR64RegClass);
5225 else if (VT.getSizeInBits() == 128)
5226 return std::make_pair(0U, &AArch64::FPR128RegClass);
5231 // Use the default implementation in TargetLowering to convert the register
5232 // constraint into a member of a register class.
5233 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5236 /// Represent NEON load and store intrinsics as MemIntrinsicNodes.
5237 /// The associated MachineMemOperands record the alignment specified
5238 /// in the intrinsic calls.
5239 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5241 unsigned Intrinsic) const {
5242 switch (Intrinsic) {
5243 case Intrinsic::arm_neon_vld1:
5244 case Intrinsic::arm_neon_vld2:
5245 case Intrinsic::arm_neon_vld3:
5246 case Intrinsic::arm_neon_vld4:
5247 case Intrinsic::aarch64_neon_vld1x2:
5248 case Intrinsic::aarch64_neon_vld1x3:
5249 case Intrinsic::aarch64_neon_vld1x4:
5250 case Intrinsic::arm_neon_vld2lane:
5251 case Intrinsic::arm_neon_vld3lane:
5252 case Intrinsic::arm_neon_vld4lane: {
5253 Info.opc = ISD::INTRINSIC_W_CHAIN;
5254 // Conservatively set memVT to the entire set of vectors loaded.
5255 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5256 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5257 Info.ptrVal = I.getArgOperand(0);
5259 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5260 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5261 Info.vol = false; // volatile loads with NEON intrinsics not supported
5262 Info.readMem = true;
5263 Info.writeMem = false;
5266 case Intrinsic::arm_neon_vst1:
5267 case Intrinsic::arm_neon_vst2:
5268 case Intrinsic::arm_neon_vst3:
5269 case Intrinsic::arm_neon_vst4:
5270 case Intrinsic::aarch64_neon_vst1x2:
5271 case Intrinsic::aarch64_neon_vst1x3:
5272 case Intrinsic::aarch64_neon_vst1x4:
5273 case Intrinsic::arm_neon_vst2lane:
5274 case Intrinsic::arm_neon_vst3lane:
5275 case Intrinsic::arm_neon_vst4lane: {
5276 Info.opc = ISD::INTRINSIC_VOID;
5277 // Conservatively set memVT to the entire set of vectors stored.
5278 unsigned NumElts = 0;
5279 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5280 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5281 if (!ArgTy->isVectorTy())
5283 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5285 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5286 Info.ptrVal = I.getArgOperand(0);
5288 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5289 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5290 Info.vol = false; // volatile stores with NEON intrinsics not supported
5291 Info.readMem = false;
5292 Info.writeMem = true;