1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GetElementPtrTypeIterator.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "aarch64-lower"
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
50 static cl::opt<AlignMode>
51 Align(cl::desc("Load/store alignment support"),
52 cl::Hidden, cl::init(NoStrictAlign),
54 clEnumValN(StrictAlign, "aarch64-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
57 "Allow unaligned memory accesses"),
60 // Place holder until extr generation is tested fully.
62 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
63 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
67 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
68 cl::desc("Allow AArch64 SLI/SRI formation"),
71 // FIXME: The necessary dtprel relocations don't seem to be supported
72 // well in the GNU bfd and gold linkers at the moment. Therefore, by
73 // default, for now, fall back to GeneralDynamic code generation.
74 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
75 "aarch64-elf-ldtls-generation", cl::Hidden,
76 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
79 /// Value type used for condition codes.
80 static const MVT MVT_CC = MVT::i32;
82 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
83 const AArch64Subtarget &STI)
84 : TargetLowering(TM), Subtarget(&STI) {
86 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
87 // we have to make something up. Arbitrarily, choose ZeroOrOne.
88 setBooleanContents(ZeroOrOneBooleanContent);
89 // When comparing vectors the result sets the different elements in the
90 // vector to all-one or all-zero.
91 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
93 // Set up the register classes.
94 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
95 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
97 if (Subtarget->hasFPARMv8()) {
98 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
99 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
100 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
101 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
104 if (Subtarget->hasNEON()) {
105 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
106 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
107 // Someone set us up the NEON.
108 addDRTypeForNEON(MVT::v2f32);
109 addDRTypeForNEON(MVT::v8i8);
110 addDRTypeForNEON(MVT::v4i16);
111 addDRTypeForNEON(MVT::v2i32);
112 addDRTypeForNEON(MVT::v1i64);
113 addDRTypeForNEON(MVT::v1f64);
114 addDRTypeForNEON(MVT::v4f16);
116 addQRTypeForNEON(MVT::v4f32);
117 addQRTypeForNEON(MVT::v2f64);
118 addQRTypeForNEON(MVT::v16i8);
119 addQRTypeForNEON(MVT::v8i16);
120 addQRTypeForNEON(MVT::v4i32);
121 addQRTypeForNEON(MVT::v2i64);
122 addQRTypeForNEON(MVT::v8f16);
125 // Compute derived properties from the register classes
126 computeRegisterProperties(Subtarget->getRegisterInfo());
128 // Provide all sorts of operation actions
129 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
130 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
131 setOperationAction(ISD::SETCC, MVT::i32, Custom);
132 setOperationAction(ISD::SETCC, MVT::i64, Custom);
133 setOperationAction(ISD::SETCC, MVT::f32, Custom);
134 setOperationAction(ISD::SETCC, MVT::f64, Custom);
135 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
136 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
137 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
138 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
139 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT, MVT::f64, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
145 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
146 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
147 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
148 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
149 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
151 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
152 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
153 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
155 setOperationAction(ISD::FREM, MVT::f32, Expand);
156 setOperationAction(ISD::FREM, MVT::f64, Expand);
157 setOperationAction(ISD::FREM, MVT::f80, Expand);
159 // Custom lowering hooks are needed for XOR
160 // to fold it into CSINC/CSINV.
161 setOperationAction(ISD::XOR, MVT::i32, Custom);
162 setOperationAction(ISD::XOR, MVT::i64, Custom);
164 // Virtually no operation on f128 is legal, but LLVM can't expand them when
165 // there's a valid register class, so we need custom operations in most cases.
166 setOperationAction(ISD::FABS, MVT::f128, Expand);
167 setOperationAction(ISD::FADD, MVT::f128, Custom);
168 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
169 setOperationAction(ISD::FCOS, MVT::f128, Expand);
170 setOperationAction(ISD::FDIV, MVT::f128, Custom);
171 setOperationAction(ISD::FMA, MVT::f128, Expand);
172 setOperationAction(ISD::FMUL, MVT::f128, Custom);
173 setOperationAction(ISD::FNEG, MVT::f128, Expand);
174 setOperationAction(ISD::FPOW, MVT::f128, Expand);
175 setOperationAction(ISD::FREM, MVT::f128, Expand);
176 setOperationAction(ISD::FRINT, MVT::f128, Expand);
177 setOperationAction(ISD::FSIN, MVT::f128, Expand);
178 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
179 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
180 setOperationAction(ISD::FSUB, MVT::f128, Custom);
181 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
182 setOperationAction(ISD::SETCC, MVT::f128, Custom);
183 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
184 setOperationAction(ISD::SELECT, MVT::f128, Custom);
185 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
186 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
188 // Lowering for many of the conversions is actually specified by the non-f128
189 // type. The LowerXXX function will be trivial when f128 isn't involved.
190 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
191 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
192 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
193 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
194 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
195 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
196 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
197 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
198 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
199 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
200 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
201 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
202 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
203 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
205 // Variable arguments.
206 setOperationAction(ISD::VASTART, MVT::Other, Custom);
207 setOperationAction(ISD::VAARG, MVT::Other, Custom);
208 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
209 setOperationAction(ISD::VAEND, MVT::Other, Expand);
211 // Variable-sized objects.
212 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
213 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
214 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
216 // Exception handling.
217 // FIXME: These are guesses. Has this been defined yet?
218 setExceptionPointerRegister(AArch64::X0);
219 setExceptionSelectorRegister(AArch64::X1);
221 // Constant pool entries
222 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
225 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
227 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
228 setOperationAction(ISD::ADDC, MVT::i32, Custom);
229 setOperationAction(ISD::ADDE, MVT::i32, Custom);
230 setOperationAction(ISD::SUBC, MVT::i32, Custom);
231 setOperationAction(ISD::SUBE, MVT::i32, Custom);
232 setOperationAction(ISD::ADDC, MVT::i64, Custom);
233 setOperationAction(ISD::ADDE, MVT::i64, Custom);
234 setOperationAction(ISD::SUBC, MVT::i64, Custom);
235 setOperationAction(ISD::SUBE, MVT::i64, Custom);
237 // AArch64 lacks both left-rotate and popcount instructions.
238 setOperationAction(ISD::ROTL, MVT::i32, Expand);
239 setOperationAction(ISD::ROTL, MVT::i64, Expand);
241 // AArch64 doesn't have {U|S}MUL_LOHI.
242 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
243 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
246 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
247 // counterparts, which AArch64 supports directly.
248 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
249 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
250 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
251 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
253 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
254 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
256 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::SREM, MVT::i32, Expand);
259 setOperationAction(ISD::SREM, MVT::i64, Expand);
260 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
261 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
262 setOperationAction(ISD::UREM, MVT::i32, Expand);
263 setOperationAction(ISD::UREM, MVT::i64, Expand);
265 // Custom lower Add/Sub/Mul with overflow.
266 setOperationAction(ISD::SADDO, MVT::i32, Custom);
267 setOperationAction(ISD::SADDO, MVT::i64, Custom);
268 setOperationAction(ISD::UADDO, MVT::i32, Custom);
269 setOperationAction(ISD::UADDO, MVT::i64, Custom);
270 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
271 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
272 setOperationAction(ISD::USUBO, MVT::i32, Custom);
273 setOperationAction(ISD::USUBO, MVT::i64, Custom);
274 setOperationAction(ISD::SMULO, MVT::i32, Custom);
275 setOperationAction(ISD::SMULO, MVT::i64, Custom);
276 setOperationAction(ISD::UMULO, MVT::i32, Custom);
277 setOperationAction(ISD::UMULO, MVT::i64, Custom);
279 setOperationAction(ISD::FSIN, MVT::f32, Expand);
280 setOperationAction(ISD::FSIN, MVT::f64, Expand);
281 setOperationAction(ISD::FCOS, MVT::f32, Expand);
282 setOperationAction(ISD::FCOS, MVT::f64, Expand);
283 setOperationAction(ISD::FPOW, MVT::f32, Expand);
284 setOperationAction(ISD::FPOW, MVT::f64, Expand);
285 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
286 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
288 // f16 is a storage-only type, always promote it to f32.
289 setOperationAction(ISD::SETCC, MVT::f16, Promote);
290 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
291 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
292 setOperationAction(ISD::SELECT, MVT::f16, Promote);
293 setOperationAction(ISD::FADD, MVT::f16, Promote);
294 setOperationAction(ISD::FSUB, MVT::f16, Promote);
295 setOperationAction(ISD::FMUL, MVT::f16, Promote);
296 setOperationAction(ISD::FDIV, MVT::f16, Promote);
297 setOperationAction(ISD::FREM, MVT::f16, Promote);
298 setOperationAction(ISD::FMA, MVT::f16, Promote);
299 setOperationAction(ISD::FNEG, MVT::f16, Promote);
300 setOperationAction(ISD::FABS, MVT::f16, Promote);
301 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
302 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
303 setOperationAction(ISD::FCOS, MVT::f16, Promote);
304 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
305 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
306 setOperationAction(ISD::FPOW, MVT::f16, Promote);
307 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
308 setOperationAction(ISD::FRINT, MVT::f16, Promote);
309 setOperationAction(ISD::FSIN, MVT::f16, Promote);
310 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
311 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
312 setOperationAction(ISD::FEXP, MVT::f16, Promote);
313 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
314 setOperationAction(ISD::FLOG, MVT::f16, Promote);
315 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
316 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
317 setOperationAction(ISD::FROUND, MVT::f16, Promote);
318 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
319 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
320 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
322 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
324 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
325 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
326 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
327 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
328 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
329 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
330 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
332 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
333 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
334 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
335 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
337 // Expand all other v4f16 operations.
338 // FIXME: We could generate better code by promoting some operations to
340 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
341 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
342 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
343 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
344 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
345 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
346 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
347 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
348 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
349 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
350 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
351 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
352 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
353 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
354 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
355 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
356 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
357 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
358 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
359 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
360 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
361 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
362 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
363 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
364 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
365 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
368 // v8f16 is also a storage-only type, so expand it.
369 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
371 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
372 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
373 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
374 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
375 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
376 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
377 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
378 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
379 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
380 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
381 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
382 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
383 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
384 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
385 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
386 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
387 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
388 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
389 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
390 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
391 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
392 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
393 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
394 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
395 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
396 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
397 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
398 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
399 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
401 // AArch64 has implementations of a lot of rounding-like FP operations.
402 for (MVT Ty : {MVT::f32, MVT::f64}) {
403 setOperationAction(ISD::FFLOOR, Ty, Legal);
404 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
405 setOperationAction(ISD::FCEIL, Ty, Legal);
406 setOperationAction(ISD::FRINT, Ty, Legal);
407 setOperationAction(ISD::FTRUNC, Ty, Legal);
408 setOperationAction(ISD::FROUND, Ty, Legal);
411 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
413 if (Subtarget->isTargetMachO()) {
414 // For iOS, we don't want to the normal expansion of a libcall to
415 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
417 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
418 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
420 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
421 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
424 // Make floating-point constants legal for the large code model, so they don't
425 // become loads from the constant pool.
426 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
427 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
428 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
431 // AArch64 does not have floating-point extending loads, i1 sign-extending
432 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
433 for (MVT VT : MVT::fp_valuetypes()) {
434 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
435 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
436 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
437 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
439 for (MVT VT : MVT::integer_valuetypes())
440 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
442 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
443 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
444 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
445 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
446 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
447 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
448 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
450 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
451 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
453 // Indexed loads and stores are supported.
454 for (unsigned im = (unsigned)ISD::PRE_INC;
455 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
456 setIndexedLoadAction(im, MVT::i8, Legal);
457 setIndexedLoadAction(im, MVT::i16, Legal);
458 setIndexedLoadAction(im, MVT::i32, Legal);
459 setIndexedLoadAction(im, MVT::i64, Legal);
460 setIndexedLoadAction(im, MVT::f64, Legal);
461 setIndexedLoadAction(im, MVT::f32, Legal);
462 setIndexedStoreAction(im, MVT::i8, Legal);
463 setIndexedStoreAction(im, MVT::i16, Legal);
464 setIndexedStoreAction(im, MVT::i32, Legal);
465 setIndexedStoreAction(im, MVT::i64, Legal);
466 setIndexedStoreAction(im, MVT::f64, Legal);
467 setIndexedStoreAction(im, MVT::f32, Legal);
471 setOperationAction(ISD::TRAP, MVT::Other, Legal);
473 // We combine OR nodes for bitfield operations.
474 setTargetDAGCombine(ISD::OR);
476 // Vector add and sub nodes may conceal a high-half opportunity.
477 // Also, try to fold ADD into CSINC/CSINV..
478 setTargetDAGCombine(ISD::ADD);
479 setTargetDAGCombine(ISD::SUB);
481 setTargetDAGCombine(ISD::XOR);
482 setTargetDAGCombine(ISD::SINT_TO_FP);
483 setTargetDAGCombine(ISD::UINT_TO_FP);
485 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
487 setTargetDAGCombine(ISD::ANY_EXTEND);
488 setTargetDAGCombine(ISD::ZERO_EXTEND);
489 setTargetDAGCombine(ISD::SIGN_EXTEND);
490 setTargetDAGCombine(ISD::BITCAST);
491 setTargetDAGCombine(ISD::CONCAT_VECTORS);
492 setTargetDAGCombine(ISD::STORE);
494 setTargetDAGCombine(ISD::MUL);
496 setTargetDAGCombine(ISD::SELECT);
497 setTargetDAGCombine(ISD::VSELECT);
498 setTargetDAGCombine(ISD::SELECT_CC);
500 setTargetDAGCombine(ISD::INTRINSIC_VOID);
501 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
502 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
504 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
505 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
506 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
508 setStackPointerRegisterToSaveRestore(AArch64::SP);
510 setSchedulingPreference(Sched::Hybrid);
513 MaskAndBranchFoldingIsLegal = true;
514 EnableExtLdPromotion = true;
516 setMinFunctionAlignment(2);
518 RequireStrictAlign = (Align == StrictAlign);
520 setHasExtractBitsInsn(true);
522 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
524 if (Subtarget->hasNEON()) {
525 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
526 // silliness like this:
527 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
528 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
529 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
530 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
531 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
532 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
533 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
534 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
535 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
536 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
537 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
538 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
539 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
540 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
541 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
542 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
543 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
544 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
545 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
546 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
547 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
548 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
549 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
550 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
551 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
553 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
554 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
555 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
556 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
557 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
559 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
561 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
562 // elements smaller than i32, so promote the input to i32 first.
563 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
564 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
565 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
566 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
567 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
568 // -> v8f16 conversions.
569 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
570 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
571 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
572 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
573 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
574 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
575 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
576 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
577 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
578 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
579 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
580 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
581 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
583 // AArch64 doesn't have MUL.2d:
584 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
585 // Custom handling for some quad-vector types to detect MULL.
586 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
587 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
588 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
590 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
591 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
592 // Likewise, narrowing and extending vector loads/stores aren't handled
594 for (MVT VT : MVT::vector_valuetypes()) {
595 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
597 setOperationAction(ISD::MULHS, VT, Expand);
598 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
599 setOperationAction(ISD::MULHU, VT, Expand);
600 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
602 setOperationAction(ISD::BSWAP, VT, Expand);
604 for (MVT InnerVT : MVT::vector_valuetypes()) {
605 setTruncStoreAction(VT, InnerVT, Expand);
606 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
607 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
608 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
612 // AArch64 has implementations of a lot of rounding-like FP operations.
613 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
614 setOperationAction(ISD::FFLOOR, Ty, Legal);
615 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
616 setOperationAction(ISD::FCEIL, Ty, Legal);
617 setOperationAction(ISD::FRINT, Ty, Legal);
618 setOperationAction(ISD::FTRUNC, Ty, Legal);
619 setOperationAction(ISD::FROUND, Ty, Legal);
623 // Prefer likely predicted branches to selects on out-of-order cores.
624 if (Subtarget->isCortexA57())
625 PredictableSelectIsExpensive = true;
628 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
629 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
630 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
631 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
633 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
634 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
635 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
636 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
637 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
639 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
640 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
643 // Mark vector float intrinsics as expand.
644 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
645 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
647 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
648 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
649 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
650 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
651 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
652 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
653 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
656 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
661 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
662 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
663 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
664 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
665 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
666 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
667 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
669 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
670 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
671 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
672 for (MVT InnerVT : MVT::all_valuetypes())
673 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
675 // CNT supports only B element sizes.
676 if (VT != MVT::v8i8 && VT != MVT::v16i8)
677 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
679 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
680 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
681 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
682 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
683 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
685 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
686 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
688 // [SU][MIN|MAX] and [SU]ABSDIFF are available for all NEON types apart from
690 if (!VT.isFloatingPoint() &&
691 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
692 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
693 ISD::SABSDIFF, ISD::UABSDIFF})
694 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
696 if (Subtarget->isLittleEndian()) {
697 for (unsigned im = (unsigned)ISD::PRE_INC;
698 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
699 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
700 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
705 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
706 addRegisterClass(VT, &AArch64::FPR64RegClass);
707 addTypeForNEON(VT, MVT::v2i32);
710 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
711 addRegisterClass(VT, &AArch64::FPR128RegClass);
712 addTypeForNEON(VT, MVT::v4i32);
715 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
719 return VT.changeVectorElementTypeToInteger();
722 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
723 /// Mask are known to be either zero or one and return them in the
724 /// KnownZero/KnownOne bitsets.
725 void AArch64TargetLowering::computeKnownBitsForTargetNode(
726 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
727 const SelectionDAG &DAG, unsigned Depth) const {
728 switch (Op.getOpcode()) {
731 case AArch64ISD::CSEL: {
732 APInt KnownZero2, KnownOne2;
733 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
734 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
735 KnownZero &= KnownZero2;
736 KnownOne &= KnownOne2;
739 case ISD::INTRINSIC_W_CHAIN: {
740 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
741 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
744 case Intrinsic::aarch64_ldaxr:
745 case Intrinsic::aarch64_ldxr: {
746 unsigned BitWidth = KnownOne.getBitWidth();
747 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
748 unsigned MemBits = VT.getScalarType().getSizeInBits();
749 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
755 case ISD::INTRINSIC_WO_CHAIN:
756 case ISD::INTRINSIC_VOID: {
757 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
761 case Intrinsic::aarch64_neon_umaxv:
762 case Intrinsic::aarch64_neon_uminv: {
763 // Figure out the datatype of the vector operand. The UMINV instruction
764 // will zero extend the result, so we can mark as known zero all the
765 // bits larger than the element datatype. 32-bit or larget doesn't need
766 // this as those are legal types and will be handled by isel directly.
767 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
768 unsigned BitWidth = KnownZero.getBitWidth();
769 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
770 assert(BitWidth >= 8 && "Unexpected width!");
771 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
773 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
774 assert(BitWidth >= 16 && "Unexpected width!");
775 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
785 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
791 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
792 const TargetLibraryInfo *libInfo) const {
793 return AArch64::createFastISel(funcInfo, libInfo);
796 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
797 switch ((AArch64ISD::NodeType)Opcode) {
798 case AArch64ISD::FIRST_NUMBER: break;
799 case AArch64ISD::CALL: return "AArch64ISD::CALL";
800 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
801 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
802 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
803 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
804 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
805 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
806 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
807 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
808 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
809 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
810 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
811 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
812 case AArch64ISD::ADC: return "AArch64ISD::ADC";
813 case AArch64ISD::SBC: return "AArch64ISD::SBC";
814 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
815 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
816 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
817 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
818 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
819 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
820 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
821 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
822 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
823 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
824 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
825 case AArch64ISD::DUP: return "AArch64ISD::DUP";
826 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
827 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
828 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
829 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
830 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
831 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
832 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
833 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
834 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
835 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
836 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
837 case AArch64ISD::BICi: return "AArch64ISD::BICi";
838 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
839 case AArch64ISD::BSL: return "AArch64ISD::BSL";
840 case AArch64ISD::NEG: return "AArch64ISD::NEG";
841 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
842 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
843 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
844 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
845 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
846 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
847 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
848 case AArch64ISD::REV16: return "AArch64ISD::REV16";
849 case AArch64ISD::REV32: return "AArch64ISD::REV32";
850 case AArch64ISD::REV64: return "AArch64ISD::REV64";
851 case AArch64ISD::EXT: return "AArch64ISD::EXT";
852 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
853 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
854 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
855 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
856 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
857 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
858 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
859 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
860 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
861 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
862 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
863 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
864 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
865 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
866 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
867 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
868 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
869 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
870 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
871 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
872 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
873 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
874 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
875 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
876 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
877 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
878 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
879 case AArch64ISD::NOT: return "AArch64ISD::NOT";
880 case AArch64ISD::BIT: return "AArch64ISD::BIT";
881 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
882 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
883 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
884 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
885 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
886 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
887 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
888 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
889 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
890 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
891 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
892 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
893 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
894 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
895 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
896 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
897 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
898 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
899 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
900 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
901 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
902 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
903 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
904 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
905 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
906 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
907 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
908 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
909 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
910 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
911 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
912 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
913 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
914 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
915 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
916 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
917 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
918 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
919 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
920 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
926 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
927 MachineBasicBlock *MBB) const {
928 // We materialise the F128CSEL pseudo-instruction as some control flow and a
932 // [... previous instrs leading to comparison ...]
938 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
940 MachineFunction *MF = MBB->getParent();
941 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
942 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
943 DebugLoc DL = MI->getDebugLoc();
944 MachineFunction::iterator It = MBB;
947 unsigned DestReg = MI->getOperand(0).getReg();
948 unsigned IfTrueReg = MI->getOperand(1).getReg();
949 unsigned IfFalseReg = MI->getOperand(2).getReg();
950 unsigned CondCode = MI->getOperand(3).getImm();
951 bool NZCVKilled = MI->getOperand(4).isKill();
953 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
954 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
955 MF->insert(It, TrueBB);
956 MF->insert(It, EndBB);
958 // Transfer rest of current basic-block to EndBB
959 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
961 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
963 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
964 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
965 MBB->addSuccessor(TrueBB);
966 MBB->addSuccessor(EndBB);
968 // TrueBB falls through to the end.
969 TrueBB->addSuccessor(EndBB);
972 TrueBB->addLiveIn(AArch64::NZCV);
973 EndBB->addLiveIn(AArch64::NZCV);
976 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
982 MI->eraseFromParent();
987 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
988 MachineBasicBlock *BB) const {
989 switch (MI->getOpcode()) {
994 llvm_unreachable("Unexpected instruction for custom inserter!");
996 case AArch64::F128CSEL:
997 return EmitF128CSEL(MI, BB);
999 case TargetOpcode::STACKMAP:
1000 case TargetOpcode::PATCHPOINT:
1001 return emitPatchPoint(MI, BB);
1005 //===----------------------------------------------------------------------===//
1006 // AArch64 Lowering private implementation.
1007 //===----------------------------------------------------------------------===//
1009 //===----------------------------------------------------------------------===//
1011 //===----------------------------------------------------------------------===//
1013 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1015 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1018 llvm_unreachable("Unknown condition code!");
1020 return AArch64CC::NE;
1022 return AArch64CC::EQ;
1024 return AArch64CC::GT;
1026 return AArch64CC::GE;
1028 return AArch64CC::LT;
1030 return AArch64CC::LE;
1032 return AArch64CC::HI;
1034 return AArch64CC::HS;
1036 return AArch64CC::LO;
1038 return AArch64CC::LS;
1042 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1043 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1044 AArch64CC::CondCode &CondCode,
1045 AArch64CC::CondCode &CondCode2) {
1046 CondCode2 = AArch64CC::AL;
1049 llvm_unreachable("Unknown FP condition!");
1052 CondCode = AArch64CC::EQ;
1056 CondCode = AArch64CC::GT;
1060 CondCode = AArch64CC::GE;
1063 CondCode = AArch64CC::MI;
1066 CondCode = AArch64CC::LS;
1069 CondCode = AArch64CC::MI;
1070 CondCode2 = AArch64CC::GT;
1073 CondCode = AArch64CC::VC;
1076 CondCode = AArch64CC::VS;
1079 CondCode = AArch64CC::EQ;
1080 CondCode2 = AArch64CC::VS;
1083 CondCode = AArch64CC::HI;
1086 CondCode = AArch64CC::PL;
1090 CondCode = AArch64CC::LT;
1094 CondCode = AArch64CC::LE;
1098 CondCode = AArch64CC::NE;
1103 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1104 /// CC usable with the vector instructions. Fewer operations are available
1105 /// without a real NZCV register, so we have to use less efficient combinations
1106 /// to get the same effect.
1107 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1108 AArch64CC::CondCode &CondCode,
1109 AArch64CC::CondCode &CondCode2,
1114 // Mostly the scalar mappings work fine.
1115 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1118 Invert = true; // Fallthrough
1120 CondCode = AArch64CC::MI;
1121 CondCode2 = AArch64CC::GE;
1128 // All of the compare-mask comparisons are ordered, but we can switch
1129 // between the two by a double inversion. E.g. ULE == !OGT.
1131 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1136 static bool isLegalArithImmed(uint64_t C) {
1137 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1138 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1141 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1142 SDLoc dl, SelectionDAG &DAG) {
1143 EVT VT = LHS.getValueType();
1145 if (VT.isFloatingPoint())
1146 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1148 // The CMP instruction is just an alias for SUBS, and representing it as
1149 // SUBS means that it's possible to get CSE with subtract operations.
1150 // A later phase can perform the optimization of setting the destination
1151 // register to WZR/XZR if it ends up being unused.
1152 unsigned Opcode = AArch64ISD::SUBS;
1154 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1155 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1156 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1157 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1158 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1159 // can be set differently by this operation. It comes down to whether
1160 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1161 // everything is fine. If not then the optimization is wrong. Thus general
1162 // comparisons are only valid if op2 != 0.
1164 // So, finally, the only LLVM-native comparisons that don't mention C and V
1165 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1166 // the absence of information about op2.
1167 Opcode = AArch64ISD::ADDS;
1168 RHS = RHS.getOperand(1);
1169 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1170 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1171 !isUnsignedIntSetCC(CC)) {
1172 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1173 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1174 // of the signed comparisons.
1175 Opcode = AArch64ISD::ANDS;
1176 RHS = LHS.getOperand(1);
1177 LHS = LHS.getOperand(0);
1180 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1184 /// \defgroup AArch64CCMP CMP;CCMP matching
1186 /// These functions deal with the formation of CMP;CCMP;... sequences.
1187 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1188 /// a comparison. They set the NZCV flags to a predefined value if their
1189 /// predicate is false. This allows to express arbitrary conjunctions, for
1190 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1193 /// ccmp B, inv(CB), CA
1194 /// check for CB flags
1196 /// In general we can create code for arbitrary "... (and (and A B) C)"
1197 /// sequences. We can also implement some "or" expressions, because "(or A B)"
1198 /// is equivalent to "not (and (not A) (not B))" and we can implement some
1199 /// negation operations:
1200 /// We can negate the results of a single comparison by inverting the flags
1201 /// used when the predicate fails and inverting the flags tested in the next
1202 /// instruction; We can also negate the results of the whole previous
1203 /// conditional compare sequence by inverting the flags tested in the next
1204 /// instruction. However there is no way to negate the result of a partial
1207 /// Therefore on encountering an "or" expression we can negate the subtree on
1208 /// one side and have to be able to push the negate to the leafs of the subtree
1209 /// on the other side (see also the comments in code). As complete example:
1210 /// "or (or (setCA (cmp A)) (setCB (cmp B)))
1211 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1212 /// is transformed to
1213 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1214 /// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1215 /// and implemented as:
1217 /// ccmp D, inv(CD), CC
1218 /// ccmp A, CA, inv(CD)
1219 /// ccmp B, CB, inv(CA)
1220 /// check for CB flags
1221 /// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1222 /// by conditional compare sequences.
1225 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1226 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1227 ISD::CondCode CC, SDValue CCOp,
1228 SDValue Condition, unsigned NZCV,
1229 SDLoc DL, SelectionDAG &DAG) {
1230 unsigned Opcode = 0;
1231 if (LHS.getValueType().isFloatingPoint())
1232 Opcode = AArch64ISD::FCCMP;
1233 else if (RHS.getOpcode() == ISD::SUB) {
1234 SDValue SubOp0 = RHS.getOperand(0);
1235 if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
1236 if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1237 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1238 Opcode = AArch64ISD::CCMN;
1239 RHS = RHS.getOperand(1);
1243 Opcode = AArch64ISD::CCMP;
1245 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1246 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1249 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1250 /// CanPushNegate is set to true if we can push a negate operation through
1251 /// the tree in a was that we are left with AND operations and negate operations
1252 /// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1253 /// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1254 /// brought into such a form.
1255 static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
1256 unsigned Depth = 0) {
1257 if (!Val.hasOneUse())
1259 unsigned Opcode = Val->getOpcode();
1260 if (Opcode == ISD::SETCC) {
1261 CanPushNegate = true;
1264 // Protect against stack overflow.
1267 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1268 SDValue O0 = Val->getOperand(0);
1269 SDValue O1 = Val->getOperand(1);
1270 bool CanPushNegateL;
1271 if (!isConjunctionDisjunctionTree(O0, CanPushNegateL, Depth+1))
1273 bool CanPushNegateR;
1274 if (!isConjunctionDisjunctionTree(O1, CanPushNegateR, Depth+1))
1276 // We cannot push a negate through an AND operation (it would become an OR),
1277 // we can however change a (not (or x y)) to (and (not x) (not y)) if we can
1278 // push the negate through the x/y subtrees.
1279 CanPushNegate = (Opcode == ISD::OR) && CanPushNegateL && CanPushNegateR;
1285 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1286 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1287 /// Tries to transform the given i1 producing node @p Val to a series compare
1288 /// and conditional compare operations. @returns an NZCV flags producing node
1289 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1290 /// transformation was not possible.
1291 /// On recursive invocations @p PushNegate may be set to true to have negation
1292 /// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1293 /// for the comparisons in the current subtree; @p Depth limits the search
1294 /// depth to avoid stack overflow.
1295 static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1296 AArch64CC::CondCode &OutCC, bool PushNegate = false,
1297 SDValue CCOp = SDValue(), AArch64CC::CondCode Predicate = AArch64CC::AL,
1298 unsigned Depth = 0) {
1299 // We're at a tree leaf, produce a conditional comparison operation.
1300 unsigned Opcode = Val->getOpcode();
1301 if (Opcode == ISD::SETCC) {
1302 SDValue LHS = Val->getOperand(0);
1303 SDValue RHS = Val->getOperand(1);
1304 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1305 bool isInteger = LHS.getValueType().isInteger();
1307 CC = getSetCCInverse(CC, isInteger);
1309 // Determine OutCC and handle FP special case.
1311 OutCC = changeIntCCToAArch64CC(CC);
1313 assert(LHS.getValueType().isFloatingPoint());
1314 AArch64CC::CondCode ExtraCC;
1315 changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
1316 // Surpisingly some floating point conditions can't be tested with a
1317 // single condition code. Construct an additional comparison in this case.
1318 // See comment below on how we deal with OR conditions.
1319 if (ExtraCC != AArch64CC::AL) {
1321 if (!CCOp.getNode())
1322 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1324 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1325 // Note that we want the inverse of ExtraCC, so NZCV is not inversed.
1326 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
1327 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
1331 Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
1332 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1336 // Produce a normal comparison if we are first in the chain
1337 if (!CCOp.getNode())
1338 return emitComparison(LHS, RHS, CC, DL, DAG);
1339 // Otherwise produce a ccmp.
1340 SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
1341 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1342 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1343 return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
1345 } else if (Opcode != ISD::AND && Opcode != ISD::OR)
1348 assert((Opcode == ISD::OR || !PushNegate)
1349 && "Can only push negate through OR operation");
1351 // Check if both sides can be transformed.
1352 SDValue LHS = Val->getOperand(0);
1353 SDValue RHS = Val->getOperand(1);
1354 bool CanPushNegateL;
1355 if (!isConjunctionDisjunctionTree(LHS, CanPushNegateL, Depth+1))
1357 bool CanPushNegateR;
1358 if (!isConjunctionDisjunctionTree(RHS, CanPushNegateR, Depth+1))
1361 // Do we need to negate our operands?
1362 bool NegateOperands = Opcode == ISD::OR;
1363 // We can negate the results of all previous operations by inverting the
1364 // predicate flags giving us a free negation for one side. For the other side
1365 // we need to be able to push the negation to the leafs of the tree.
1366 if (NegateOperands) {
1367 if (!CanPushNegateL && !CanPushNegateR)
1369 // Order the side where we can push the negate through to LHS.
1370 if (!CanPushNegateL && CanPushNegateR) {
1371 std::swap(LHS, RHS);
1372 CanPushNegateL = true;
1376 // Emit RHS. If we want to negate the tree we only need to push a negate
1377 // through if we are already in a PushNegate case, otherwise we can negate
1378 // the "flags to test" afterwards.
1379 AArch64CC::CondCode RHSCC;
1380 SDValue CmpR = emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, PushNegate,
1381 CCOp, Predicate, Depth+1);
1382 if (NegateOperands && !PushNegate)
1383 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1384 // Emit LHS. We must push the negate through if we need to negate it.
1385 SDValue CmpL = emitConjunctionDisjunctionTree(DAG, LHS, OutCC, NegateOperands,
1386 CmpR, RHSCC, Depth+1);
1387 // If we transformed an OR to and AND then we have to negate the result
1388 // (or absorb a PushNegate resulting in a double negation).
1389 if (Opcode == ISD::OR && !PushNegate)
1390 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1396 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1397 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1398 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1399 EVT VT = RHS.getValueType();
1400 uint64_t C = RHSC->getZExtValue();
1401 if (!isLegalArithImmed(C)) {
1402 // Constant does not fit, try adjusting it by one?
1408 if ((VT == MVT::i32 && C != 0x80000000 &&
1409 isLegalArithImmed((uint32_t)(C - 1))) ||
1410 (VT == MVT::i64 && C != 0x80000000ULL &&
1411 isLegalArithImmed(C - 1ULL))) {
1412 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1413 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1414 RHS = DAG.getConstant(C, dl, VT);
1419 if ((VT == MVT::i32 && C != 0 &&
1420 isLegalArithImmed((uint32_t)(C - 1))) ||
1421 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1422 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1423 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1424 RHS = DAG.getConstant(C, dl, VT);
1429 if ((VT == MVT::i32 && C != INT32_MAX &&
1430 isLegalArithImmed((uint32_t)(C + 1))) ||
1431 (VT == MVT::i64 && C != INT64_MAX &&
1432 isLegalArithImmed(C + 1ULL))) {
1433 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1434 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1435 RHS = DAG.getConstant(C, dl, VT);
1440 if ((VT == MVT::i32 && C != UINT32_MAX &&
1441 isLegalArithImmed((uint32_t)(C + 1))) ||
1442 (VT == MVT::i64 && C != UINT64_MAX &&
1443 isLegalArithImmed(C + 1ULL))) {
1444 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1445 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1446 RHS = DAG.getConstant(C, dl, VT);
1453 AArch64CC::CondCode AArch64CC;
1454 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1455 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1457 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1458 // For the i8 operand, the largest immediate is 255, so this can be easily
1459 // encoded in the compare instruction. For the i16 operand, however, the
1460 // largest immediate cannot be encoded in the compare.
1461 // Therefore, use a sign extending load and cmn to avoid materializing the
1462 // -1 constant. For example,
1464 // ldrh w0, [x0, #0]
1467 // ldrsh w0, [x0, #0]
1469 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1470 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1471 // ensure both the LHS and RHS are truely zero extended and to make sure the
1472 // transformation is profitable.
1473 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1474 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1475 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1476 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1477 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1478 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1480 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1481 DAG.getValueType(MVT::i16));
1482 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1483 RHS.getValueType()),
1485 AArch64CC = changeIntCCToAArch64CC(CC);
1489 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1490 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1491 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1492 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1498 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1499 AArch64CC = changeIntCCToAArch64CC(CC);
1501 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1505 static std::pair<SDValue, SDValue>
1506 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1507 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1508 "Unsupported value type");
1509 SDValue Value, Overflow;
1511 SDValue LHS = Op.getOperand(0);
1512 SDValue RHS = Op.getOperand(1);
1514 switch (Op.getOpcode()) {
1516 llvm_unreachable("Unknown overflow instruction!");
1518 Opc = AArch64ISD::ADDS;
1522 Opc = AArch64ISD::ADDS;
1526 Opc = AArch64ISD::SUBS;
1530 Opc = AArch64ISD::SUBS;
1533 // Multiply needs a little bit extra work.
1537 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1538 if (Op.getValueType() == MVT::i32) {
1539 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1540 // For a 32 bit multiply with overflow check we want the instruction
1541 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1542 // need to generate the following pattern:
1543 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1544 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1545 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1546 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1547 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1548 DAG.getConstant(0, DL, MVT::i64));
1549 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1550 // operation. We need to clear out the upper 32 bits, because we used a
1551 // widening multiply that wrote all 64 bits. In the end this should be a
1553 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1555 // The signed overflow check requires more than just a simple check for
1556 // any bit set in the upper 32 bits of the result. These bits could be
1557 // just the sign bits of a negative number. To perform the overflow
1558 // check we have to arithmetic shift right the 32nd bit of the result by
1559 // 31 bits. Then we compare the result to the upper 32 bits.
1560 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1561 DAG.getConstant(32, DL, MVT::i64));
1562 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1563 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1564 DAG.getConstant(31, DL, MVT::i64));
1565 // It is important that LowerBits is last, otherwise the arithmetic
1566 // shift will not be folded into the compare (SUBS).
1567 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1568 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1571 // The overflow check for unsigned multiply is easy. We only need to
1572 // check if any of the upper 32 bits are set. This can be done with a
1573 // CMP (shifted register). For that we need to generate the following
1575 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1576 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1577 DAG.getConstant(32, DL, MVT::i64));
1578 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1580 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1581 DAG.getConstant(0, DL, MVT::i64),
1582 UpperBits).getValue(1);
1586 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1587 // For the 64 bit multiply
1588 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1590 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1591 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1592 DAG.getConstant(63, DL, MVT::i64));
1593 // It is important that LowerBits is last, otherwise the arithmetic
1594 // shift will not be folded into the compare (SUBS).
1595 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1596 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1599 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1600 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1602 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1603 DAG.getConstant(0, DL, MVT::i64),
1604 UpperBits).getValue(1);
1611 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1613 // Emit the AArch64 operation with overflow check.
1614 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1615 Overflow = Value.getValue(1);
1617 return std::make_pair(Value, Overflow);
1620 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1621 RTLIB::Libcall Call) const {
1622 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1623 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1627 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1628 SDValue Sel = Op.getOperand(0);
1629 SDValue Other = Op.getOperand(1);
1631 // If neither operand is a SELECT_CC, give up.
1632 if (Sel.getOpcode() != ISD::SELECT_CC)
1633 std::swap(Sel, Other);
1634 if (Sel.getOpcode() != ISD::SELECT_CC)
1637 // The folding we want to perform is:
1638 // (xor x, (select_cc a, b, cc, 0, -1) )
1640 // (csel x, (xor x, -1), cc ...)
1642 // The latter will get matched to a CSINV instruction.
1644 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1645 SDValue LHS = Sel.getOperand(0);
1646 SDValue RHS = Sel.getOperand(1);
1647 SDValue TVal = Sel.getOperand(2);
1648 SDValue FVal = Sel.getOperand(3);
1651 // FIXME: This could be generalized to non-integer comparisons.
1652 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1655 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1656 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1658 // The values aren't constants, this isn't the pattern we're looking for.
1659 if (!CFVal || !CTVal)
1662 // We can commute the SELECT_CC by inverting the condition. This
1663 // might be needed to make this fit into a CSINV pattern.
1664 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1665 std::swap(TVal, FVal);
1666 std::swap(CTVal, CFVal);
1667 CC = ISD::getSetCCInverse(CC, true);
1670 // If the constants line up, perform the transform!
1671 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1673 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1676 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1677 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1679 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1686 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1687 EVT VT = Op.getValueType();
1689 // Let legalize expand this if it isn't a legal type yet.
1690 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1693 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1696 bool ExtraOp = false;
1697 switch (Op.getOpcode()) {
1699 llvm_unreachable("Invalid code");
1701 Opc = AArch64ISD::ADDS;
1704 Opc = AArch64ISD::SUBS;
1707 Opc = AArch64ISD::ADCS;
1711 Opc = AArch64ISD::SBCS;
1717 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1718 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1722 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1723 // Let legalize expand this if it isn't a legal type yet.
1724 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1728 AArch64CC::CondCode CC;
1729 // The actual operation that sets the overflow or carry flag.
1730 SDValue Value, Overflow;
1731 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1733 // We use 0 and 1 as false and true values.
1734 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1735 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1737 // We use an inverted condition, because the conditional select is inverted
1738 // too. This will allow it to be selected to a single instruction:
1739 // CSINC Wd, WZR, WZR, invert(cond).
1740 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1741 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1744 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1745 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1748 // Prefetch operands are:
1749 // 1: Address to prefetch
1751 // 3: int locality (0 = no locality ... 3 = extreme locality)
1752 // 4: bool isDataCache
1753 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1755 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1756 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1757 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1759 bool IsStream = !Locality;
1760 // When the locality number is set
1762 // The front-end should have filtered out the out-of-range values
1763 assert(Locality <= 3 && "Prefetch locality out-of-range");
1764 // The locality degree is the opposite of the cache speed.
1765 // Put the number the other way around.
1766 // The encoding starts at 0 for level 1
1767 Locality = 3 - Locality;
1770 // built the mask value encoding the expected behavior.
1771 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1772 (!IsData << 3) | // IsDataCache bit
1773 (Locality << 1) | // Cache level bits
1774 (unsigned)IsStream; // Stream bit
1775 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1776 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1779 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1780 SelectionDAG &DAG) const {
1781 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1784 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1786 return LowerF128Call(Op, DAG, LC);
1789 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1790 SelectionDAG &DAG) const {
1791 if (Op.getOperand(0).getValueType() != MVT::f128) {
1792 // It's legal except when f128 is involved
1797 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1799 // FP_ROUND node has a second operand indicating whether it is known to be
1800 // precise. That doesn't take part in the LibCall so we can't directly use
1802 SDValue SrcVal = Op.getOperand(0);
1803 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1804 /*isSigned*/ false, SDLoc(Op)).first;
1807 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1808 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1809 // Any additional optimization in this function should be recorded
1810 // in the cost tables.
1811 EVT InVT = Op.getOperand(0).getValueType();
1812 EVT VT = Op.getValueType();
1814 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1817 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1819 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1822 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1825 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1826 VT.getVectorNumElements());
1827 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1828 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1831 // Type changing conversions are illegal.
1835 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1836 SelectionDAG &DAG) const {
1837 if (Op.getOperand(0).getValueType().isVector())
1838 return LowerVectorFP_TO_INT(Op, DAG);
1840 // f16 conversions are promoted to f32.
1841 if (Op.getOperand(0).getValueType() == MVT::f16) {
1844 Op.getOpcode(), dl, Op.getValueType(),
1845 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1848 if (Op.getOperand(0).getValueType() != MVT::f128) {
1849 // It's legal except when f128 is involved
1854 if (Op.getOpcode() == ISD::FP_TO_SINT)
1855 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1857 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1859 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1860 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1864 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1865 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1866 // Any additional optimization in this function should be recorded
1867 // in the cost tables.
1868 EVT VT = Op.getValueType();
1870 SDValue In = Op.getOperand(0);
1871 EVT InVT = In.getValueType();
1873 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1875 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1876 InVT.getVectorNumElements());
1877 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1878 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1881 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1883 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1884 EVT CastVT = VT.changeVectorElementTypeToInteger();
1885 In = DAG.getNode(CastOpc, dl, CastVT, In);
1886 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1892 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1893 SelectionDAG &DAG) const {
1894 if (Op.getValueType().isVector())
1895 return LowerVectorINT_TO_FP(Op, DAG);
1897 // f16 conversions are promoted to f32.
1898 if (Op.getValueType() == MVT::f16) {
1901 ISD::FP_ROUND, dl, MVT::f16,
1902 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1903 DAG.getIntPtrConstant(0, dl));
1906 // i128 conversions are libcalls.
1907 if (Op.getOperand(0).getValueType() == MVT::i128)
1910 // Other conversions are legal, unless it's to the completely software-based
1912 if (Op.getValueType() != MVT::f128)
1916 if (Op.getOpcode() == ISD::SINT_TO_FP)
1917 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1919 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1921 return LowerF128Call(Op, DAG, LC);
1924 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1925 SelectionDAG &DAG) const {
1926 // For iOS, we want to call an alternative entry point: __sincos_stret,
1927 // which returns the values in two S / D registers.
1929 SDValue Arg = Op.getOperand(0);
1930 EVT ArgVT = Arg.getValueType();
1931 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1938 Entry.isSExt = false;
1939 Entry.isZExt = false;
1940 Args.push_back(Entry);
1942 const char *LibcallName =
1943 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1945 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
1947 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1948 TargetLowering::CallLoweringInfo CLI(DAG);
1949 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1950 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1952 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1953 return CallResult.first;
1956 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1957 if (Op.getValueType() != MVT::f16)
1960 assert(Op.getOperand(0).getValueType() == MVT::i16);
1963 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1964 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1966 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1967 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1971 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1972 if (OrigVT.getSizeInBits() >= 64)
1975 assert(OrigVT.isSimple() && "Expecting a simple value type");
1977 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1978 switch (OrigSimpleTy) {
1979 default: llvm_unreachable("Unexpected Vector Type");
1988 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1991 unsigned ExtOpcode) {
1992 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1993 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1994 // 64-bits we need to insert a new extension so that it will be 64-bits.
1995 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1996 if (OrigTy.getSizeInBits() >= 64)
1999 // Must extend size to at least 64 bits to be used as an operand for VMULL.
2000 EVT NewVT = getExtensionTo64Bits(OrigTy);
2002 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
2005 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2007 EVT VT = N->getValueType(0);
2009 if (N->getOpcode() != ISD::BUILD_VECTOR)
2012 for (const SDValue &Elt : N->op_values()) {
2013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2014 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2015 unsigned HalfSize = EltSize / 2;
2017 if (!isIntN(HalfSize, C->getSExtValue()))
2020 if (!isUIntN(HalfSize, C->getZExtValue()))
2031 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2032 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2033 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2034 N->getOperand(0)->getValueType(0),
2038 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2039 EVT VT = N->getValueType(0);
2041 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
2042 unsigned NumElts = VT.getVectorNumElements();
2043 MVT TruncVT = MVT::getIntegerVT(EltSize);
2044 SmallVector<SDValue, 8> Ops;
2045 for (unsigned i = 0; i != NumElts; ++i) {
2046 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2047 const APInt &CInt = C->getAPIntValue();
2048 // Element types smaller than 32 bits are not legal, so use i32 elements.
2049 // The values are implicitly truncated so sext vs. zext doesn't matter.
2050 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2052 return DAG.getNode(ISD::BUILD_VECTOR, dl,
2053 MVT::getVectorVT(TruncVT, NumElts), Ops);
2056 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2057 if (N->getOpcode() == ISD::SIGN_EXTEND)
2059 if (isExtendedBUILD_VECTOR(N, DAG, true))
2064 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2065 if (N->getOpcode() == ISD::ZERO_EXTEND)
2067 if (isExtendedBUILD_VECTOR(N, DAG, false))
2072 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2073 unsigned Opcode = N->getOpcode();
2074 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2075 SDNode *N0 = N->getOperand(0).getNode();
2076 SDNode *N1 = N->getOperand(1).getNode();
2077 return N0->hasOneUse() && N1->hasOneUse() &&
2078 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2083 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2084 unsigned Opcode = N->getOpcode();
2085 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2086 SDNode *N0 = N->getOperand(0).getNode();
2087 SDNode *N1 = N->getOperand(1).getNode();
2088 return N0->hasOneUse() && N1->hasOneUse() &&
2089 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2094 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2095 // Multiplications are only custom-lowered for 128-bit vectors so that
2096 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2097 EVT VT = Op.getValueType();
2098 assert(VT.is128BitVector() && VT.isInteger() &&
2099 "unexpected type for custom-lowering ISD::MUL");
2100 SDNode *N0 = Op.getOperand(0).getNode();
2101 SDNode *N1 = Op.getOperand(1).getNode();
2102 unsigned NewOpc = 0;
2104 bool isN0SExt = isSignExtended(N0, DAG);
2105 bool isN1SExt = isSignExtended(N1, DAG);
2106 if (isN0SExt && isN1SExt)
2107 NewOpc = AArch64ISD::SMULL;
2109 bool isN0ZExt = isZeroExtended(N0, DAG);
2110 bool isN1ZExt = isZeroExtended(N1, DAG);
2111 if (isN0ZExt && isN1ZExt)
2112 NewOpc = AArch64ISD::UMULL;
2113 else if (isN1SExt || isN1ZExt) {
2114 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2115 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2116 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2117 NewOpc = AArch64ISD::SMULL;
2119 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2120 NewOpc = AArch64ISD::UMULL;
2122 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2124 NewOpc = AArch64ISD::UMULL;
2130 if (VT == MVT::v2i64)
2131 // Fall through to expand this. It is not legal.
2134 // Other vector multiplications are legal.
2139 // Legalize to a S/UMULL instruction
2142 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2144 Op0 = skipExtensionForVectorMULL(N0, DAG);
2145 assert(Op0.getValueType().is64BitVector() &&
2146 Op1.getValueType().is64BitVector() &&
2147 "unexpected types for extended operands to VMULL");
2148 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2150 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2151 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2152 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2153 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2154 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2155 EVT Op1VT = Op1.getValueType();
2156 return DAG.getNode(N0->getOpcode(), DL, VT,
2157 DAG.getNode(NewOpc, DL, VT,
2158 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2159 DAG.getNode(NewOpc, DL, VT,
2160 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2163 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2164 SelectionDAG &DAG) const {
2165 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2168 default: return SDValue(); // Don't custom lower most intrinsics.
2169 case Intrinsic::aarch64_thread_pointer: {
2170 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2171 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2176 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2177 SelectionDAG &DAG) const {
2178 switch (Op.getOpcode()) {
2180 llvm_unreachable("unimplemented operand");
2183 return LowerBITCAST(Op, DAG);
2184 case ISD::GlobalAddress:
2185 return LowerGlobalAddress(Op, DAG);
2186 case ISD::GlobalTLSAddress:
2187 return LowerGlobalTLSAddress(Op, DAG);
2189 return LowerSETCC(Op, DAG);
2191 return LowerBR_CC(Op, DAG);
2193 return LowerSELECT(Op, DAG);
2194 case ISD::SELECT_CC:
2195 return LowerSELECT_CC(Op, DAG);
2196 case ISD::JumpTable:
2197 return LowerJumpTable(Op, DAG);
2198 case ISD::ConstantPool:
2199 return LowerConstantPool(Op, DAG);
2200 case ISD::BlockAddress:
2201 return LowerBlockAddress(Op, DAG);
2203 return LowerVASTART(Op, DAG);
2205 return LowerVACOPY(Op, DAG);
2207 return LowerVAARG(Op, DAG);
2212 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2219 return LowerXALUO(Op, DAG);
2221 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2223 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2225 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2227 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2229 return LowerFP_ROUND(Op, DAG);
2230 case ISD::FP_EXTEND:
2231 return LowerFP_EXTEND(Op, DAG);
2232 case ISD::FRAMEADDR:
2233 return LowerFRAMEADDR(Op, DAG);
2234 case ISD::RETURNADDR:
2235 return LowerRETURNADDR(Op, DAG);
2236 case ISD::INSERT_VECTOR_ELT:
2237 return LowerINSERT_VECTOR_ELT(Op, DAG);
2238 case ISD::EXTRACT_VECTOR_ELT:
2239 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2240 case ISD::BUILD_VECTOR:
2241 return LowerBUILD_VECTOR(Op, DAG);
2242 case ISD::VECTOR_SHUFFLE:
2243 return LowerVECTOR_SHUFFLE(Op, DAG);
2244 case ISD::EXTRACT_SUBVECTOR:
2245 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2249 return LowerVectorSRA_SRL_SHL(Op, DAG);
2250 case ISD::SHL_PARTS:
2251 return LowerShiftLeftParts(Op, DAG);
2252 case ISD::SRL_PARTS:
2253 case ISD::SRA_PARTS:
2254 return LowerShiftRightParts(Op, DAG);
2256 return LowerCTPOP(Op, DAG);
2257 case ISD::FCOPYSIGN:
2258 return LowerFCOPYSIGN(Op, DAG);
2260 return LowerVectorAND(Op, DAG);
2262 return LowerVectorOR(Op, DAG);
2264 return LowerXOR(Op, DAG);
2266 return LowerPREFETCH(Op, DAG);
2267 case ISD::SINT_TO_FP:
2268 case ISD::UINT_TO_FP:
2269 return LowerINT_TO_FP(Op, DAG);
2270 case ISD::FP_TO_SINT:
2271 case ISD::FP_TO_UINT:
2272 return LowerFP_TO_INT(Op, DAG);
2274 return LowerFSINCOS(Op, DAG);
2276 return LowerMUL(Op, DAG);
2277 case ISD::INTRINSIC_WO_CHAIN:
2278 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2282 /// getFunctionAlignment - Return the Log2 alignment of this function.
2283 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2287 //===----------------------------------------------------------------------===//
2288 // Calling Convention Implementation
2289 //===----------------------------------------------------------------------===//
2291 #include "AArch64GenCallingConv.inc"
2293 /// Selects the correct CCAssignFn for a given CallingConvention value.
2294 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2295 bool IsVarArg) const {
2298 llvm_unreachable("Unsupported calling convention.");
2299 case CallingConv::WebKit_JS:
2300 return CC_AArch64_WebKit_JS;
2301 case CallingConv::GHC:
2302 return CC_AArch64_GHC;
2303 case CallingConv::C:
2304 case CallingConv::Fast:
2305 if (!Subtarget->isTargetDarwin())
2306 return CC_AArch64_AAPCS;
2307 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2311 SDValue AArch64TargetLowering::LowerFormalArguments(
2312 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2313 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2314 SmallVectorImpl<SDValue> &InVals) const {
2315 MachineFunction &MF = DAG.getMachineFunction();
2316 MachineFrameInfo *MFI = MF.getFrameInfo();
2318 // Assign locations to all of the incoming arguments.
2319 SmallVector<CCValAssign, 16> ArgLocs;
2320 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2323 // At this point, Ins[].VT may already be promoted to i32. To correctly
2324 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2325 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2326 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2327 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2329 unsigned NumArgs = Ins.size();
2330 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2331 unsigned CurArgIdx = 0;
2332 for (unsigned i = 0; i != NumArgs; ++i) {
2333 MVT ValVT = Ins[i].VT;
2334 if (Ins[i].isOrigArg()) {
2335 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2336 CurArgIdx = Ins[i].getOrigArgIndex();
2338 // Get type of the original argument.
2339 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2340 /*AllowUnknown*/ true);
2341 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2342 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2343 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2345 else if (ActualMVT == MVT::i16)
2348 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2350 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2351 assert(!Res && "Call operand has unhandled type");
2354 assert(ArgLocs.size() == Ins.size());
2355 SmallVector<SDValue, 16> ArgValues;
2356 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2357 CCValAssign &VA = ArgLocs[i];
2359 if (Ins[i].Flags.isByVal()) {
2360 // Byval is used for HFAs in the PCS, but the system should work in a
2361 // non-compliant manner for larger structs.
2362 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2363 int Size = Ins[i].Flags.getByValSize();
2364 unsigned NumRegs = (Size + 7) / 8;
2366 // FIXME: This works on big-endian for composite byvals, which are the common
2367 // case. It should also work for fundamental types too.
2369 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2370 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2371 InVals.push_back(FrameIdxN);
2376 if (VA.isRegLoc()) {
2377 // Arguments stored in registers.
2378 EVT RegVT = VA.getLocVT();
2381 const TargetRegisterClass *RC;
2383 if (RegVT == MVT::i32)
2384 RC = &AArch64::GPR32RegClass;
2385 else if (RegVT == MVT::i64)
2386 RC = &AArch64::GPR64RegClass;
2387 else if (RegVT == MVT::f16)
2388 RC = &AArch64::FPR16RegClass;
2389 else if (RegVT == MVT::f32)
2390 RC = &AArch64::FPR32RegClass;
2391 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2392 RC = &AArch64::FPR64RegClass;
2393 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2394 RC = &AArch64::FPR128RegClass;
2396 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2398 // Transform the arguments in physical registers into virtual ones.
2399 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2400 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2402 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2403 // to 64 bits. Insert an assert[sz]ext to capture this, then
2404 // truncate to the right size.
2405 switch (VA.getLocInfo()) {
2407 llvm_unreachable("Unknown loc info!");
2408 case CCValAssign::Full:
2410 case CCValAssign::BCvt:
2411 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2413 case CCValAssign::AExt:
2414 case CCValAssign::SExt:
2415 case CCValAssign::ZExt:
2416 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2417 // nodes after our lowering.
2418 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2422 InVals.push_back(ArgValue);
2424 } else { // VA.isRegLoc()
2425 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2426 unsigned ArgOffset = VA.getLocMemOffset();
2427 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2429 uint32_t BEAlign = 0;
2430 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2431 !Ins[i].Flags.isInConsecutiveRegs())
2432 BEAlign = 8 - ArgSize;
2434 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2436 // Create load nodes to retrieve arguments from the stack.
2437 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2440 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2441 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2442 MVT MemVT = VA.getValVT();
2444 switch (VA.getLocInfo()) {
2447 case CCValAssign::BCvt:
2448 MemVT = VA.getLocVT();
2450 case CCValAssign::SExt:
2451 ExtType = ISD::SEXTLOAD;
2453 case CCValAssign::ZExt:
2454 ExtType = ISD::ZEXTLOAD;
2456 case CCValAssign::AExt:
2457 ExtType = ISD::EXTLOAD;
2461 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2462 MachinePointerInfo::getFixedStack(FI),
2463 MemVT, false, false, false, 0);
2465 InVals.push_back(ArgValue);
2471 if (!Subtarget->isTargetDarwin()) {
2472 // The AAPCS variadic function ABI is identical to the non-variadic
2473 // one. As a result there may be more arguments in registers and we should
2474 // save them for future reference.
2475 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2478 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2479 // This will point to the next argument passed via stack.
2480 unsigned StackOffset = CCInfo.getNextStackOffset();
2481 // We currently pass all varargs at 8-byte alignment.
2482 StackOffset = ((StackOffset + 7) & ~7);
2483 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2486 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2487 unsigned StackArgSize = CCInfo.getNextStackOffset();
2488 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2489 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2490 // This is a non-standard ABI so by fiat I say we're allowed to make full
2491 // use of the stack area to be popped, which must be aligned to 16 bytes in
2493 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2495 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2496 // a multiple of 16.
2497 FuncInfo->setArgumentStackToRestore(StackArgSize);
2499 // This realignment carries over to the available bytes below. Our own
2500 // callers will guarantee the space is free by giving an aligned value to
2503 // Even if we're not expected to free up the space, it's useful to know how
2504 // much is there while considering tail calls (because we can reuse it).
2505 FuncInfo->setBytesInStackArgArea(StackArgSize);
2510 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2511 SelectionDAG &DAG, SDLoc DL,
2512 SDValue &Chain) const {
2513 MachineFunction &MF = DAG.getMachineFunction();
2514 MachineFrameInfo *MFI = MF.getFrameInfo();
2515 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2516 auto PtrVT = getPointerTy(DAG.getDataLayout());
2518 SmallVector<SDValue, 8> MemOps;
2520 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2521 AArch64::X3, AArch64::X4, AArch64::X5,
2522 AArch64::X6, AArch64::X7 };
2523 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2524 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2526 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2528 if (GPRSaveSize != 0) {
2529 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2531 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2533 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2534 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2535 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2537 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2538 MachinePointerInfo::getStack(i * 8), false, false, 0);
2539 MemOps.push_back(Store);
2541 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2544 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2545 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2547 if (Subtarget->hasFPARMv8()) {
2548 static const MCPhysReg FPRArgRegs[] = {
2549 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2550 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2551 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2552 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2554 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2556 if (FPRSaveSize != 0) {
2557 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2559 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2561 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2562 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2563 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2566 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2567 MachinePointerInfo::getStack(i * 16), false, false, 0);
2568 MemOps.push_back(Store);
2569 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2570 DAG.getConstant(16, DL, PtrVT));
2573 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2574 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2577 if (!MemOps.empty()) {
2578 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2582 /// LowerCallResult - Lower the result values of a call into the
2583 /// appropriate copies out of appropriate physical registers.
2584 SDValue AArch64TargetLowering::LowerCallResult(
2585 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2586 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2587 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2588 SDValue ThisVal) const {
2589 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2590 ? RetCC_AArch64_WebKit_JS
2591 : RetCC_AArch64_AAPCS;
2592 // Assign locations to each value returned by this call.
2593 SmallVector<CCValAssign, 16> RVLocs;
2594 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2596 CCInfo.AnalyzeCallResult(Ins, RetCC);
2598 // Copy all of the result registers out of their specified physreg.
2599 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2600 CCValAssign VA = RVLocs[i];
2602 // Pass 'this' value directly from the argument to return value, to avoid
2603 // reg unit interference
2604 if (i == 0 && isThisReturn) {
2605 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2606 "unexpected return calling convention register assignment");
2607 InVals.push_back(ThisVal);
2612 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2613 Chain = Val.getValue(1);
2614 InFlag = Val.getValue(2);
2616 switch (VA.getLocInfo()) {
2618 llvm_unreachable("Unknown loc info!");
2619 case CCValAssign::Full:
2621 case CCValAssign::BCvt:
2622 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2626 InVals.push_back(Val);
2632 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2633 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2634 bool isCalleeStructRet, bool isCallerStructRet,
2635 const SmallVectorImpl<ISD::OutputArg> &Outs,
2636 const SmallVectorImpl<SDValue> &OutVals,
2637 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2638 // For CallingConv::C this function knows whether the ABI needs
2639 // changing. That's not true for other conventions so they will have to opt in
2641 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2644 const MachineFunction &MF = DAG.getMachineFunction();
2645 const Function *CallerF = MF.getFunction();
2646 CallingConv::ID CallerCC = CallerF->getCallingConv();
2647 bool CCMatch = CallerCC == CalleeCC;
2649 // Byval parameters hand the function a pointer directly into the stack area
2650 // we want to reuse during a tail call. Working around this *is* possible (see
2651 // X86) but less efficient and uglier in LowerCall.
2652 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2653 e = CallerF->arg_end();
2655 if (i->hasByValAttr())
2658 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2659 if (IsTailCallConvention(CalleeCC) && CCMatch)
2664 // Externally-defined functions with weak linkage should not be
2665 // tail-called on AArch64 when the OS does not support dynamic
2666 // pre-emption of symbols, as the AAELF spec requires normal calls
2667 // to undefined weak functions to be replaced with a NOP or jump to the
2668 // next instruction. The behaviour of branch instructions in this
2669 // situation (as used for tail calls) is implementation-defined, so we
2670 // cannot rely on the linker replacing the tail call with a return.
2671 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2672 const GlobalValue *GV = G->getGlobal();
2673 const Triple &TT = getTargetMachine().getTargetTriple();
2674 if (GV->hasExternalWeakLinkage() &&
2675 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2679 // Now we search for cases where we can use a tail call without changing the
2680 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2683 // I want anyone implementing a new calling convention to think long and hard
2684 // about this assert.
2685 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2686 "Unexpected variadic calling convention");
2688 if (isVarArg && !Outs.empty()) {
2689 // At least two cases here: if caller is fastcc then we can't have any
2690 // memory arguments (we'd be expected to clean up the stack afterwards). If
2691 // caller is C then we could potentially use its argument area.
2693 // FIXME: for now we take the most conservative of these in both cases:
2694 // disallow all variadic memory operands.
2695 SmallVector<CCValAssign, 16> ArgLocs;
2696 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2699 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2700 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2701 if (!ArgLocs[i].isRegLoc())
2705 // If the calling conventions do not match, then we'd better make sure the
2706 // results are returned in the same way as what the caller expects.
2708 SmallVector<CCValAssign, 16> RVLocs1;
2709 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2711 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2713 SmallVector<CCValAssign, 16> RVLocs2;
2714 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2716 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2718 if (RVLocs1.size() != RVLocs2.size())
2720 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2721 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2723 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2725 if (RVLocs1[i].isRegLoc()) {
2726 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2729 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2735 // Nothing more to check if the callee is taking no arguments
2739 SmallVector<CCValAssign, 16> ArgLocs;
2740 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2743 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2745 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2747 // If the stack arguments for this call would fit into our own save area then
2748 // the call can be made tail.
2749 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2752 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2754 MachineFrameInfo *MFI,
2755 int ClobberedFI) const {
2756 SmallVector<SDValue, 8> ArgChains;
2757 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2758 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2760 // Include the original chain at the beginning of the list. When this is
2761 // used by target LowerCall hooks, this helps legalize find the
2762 // CALLSEQ_BEGIN node.
2763 ArgChains.push_back(Chain);
2765 // Add a chain value for each stack argument corresponding
2766 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2767 UE = DAG.getEntryNode().getNode()->use_end();
2769 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2770 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2771 if (FI->getIndex() < 0) {
2772 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2773 int64_t InLastByte = InFirstByte;
2774 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2776 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2777 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2778 ArgChains.push_back(SDValue(L, 1));
2781 // Build a tokenfactor for all the chains.
2782 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2785 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2786 bool TailCallOpt) const {
2787 return CallCC == CallingConv::Fast && TailCallOpt;
2790 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2791 return CallCC == CallingConv::Fast;
2794 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2795 /// and add input and output parameter nodes.
2797 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2798 SmallVectorImpl<SDValue> &InVals) const {
2799 SelectionDAG &DAG = CLI.DAG;
2801 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2802 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2803 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2804 SDValue Chain = CLI.Chain;
2805 SDValue Callee = CLI.Callee;
2806 bool &IsTailCall = CLI.IsTailCall;
2807 CallingConv::ID CallConv = CLI.CallConv;
2808 bool IsVarArg = CLI.IsVarArg;
2810 MachineFunction &MF = DAG.getMachineFunction();
2811 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2812 bool IsThisReturn = false;
2814 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2815 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2816 bool IsSibCall = false;
2819 // Check if it's really possible to do a tail call.
2820 IsTailCall = isEligibleForTailCallOptimization(
2821 Callee, CallConv, IsVarArg, IsStructRet,
2822 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2823 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2824 report_fatal_error("failed to perform tail call elimination on a call "
2825 "site marked musttail");
2827 // A sibling call is one where we're under the usual C ABI and not planning
2828 // to change that but can still do a tail call:
2829 if (!TailCallOpt && IsTailCall)
2836 // Analyze operands of the call, assigning locations to each operand.
2837 SmallVector<CCValAssign, 16> ArgLocs;
2838 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2842 // Handle fixed and variable vector arguments differently.
2843 // Variable vector arguments always go into memory.
2844 unsigned NumArgs = Outs.size();
2846 for (unsigned i = 0; i != NumArgs; ++i) {
2847 MVT ArgVT = Outs[i].VT;
2848 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2849 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2850 /*IsVarArg=*/ !Outs[i].IsFixed);
2851 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2852 assert(!Res && "Call operand has unhandled type");
2856 // At this point, Outs[].VT may already be promoted to i32. To correctly
2857 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2858 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2859 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2860 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2862 unsigned NumArgs = Outs.size();
2863 for (unsigned i = 0; i != NumArgs; ++i) {
2864 MVT ValVT = Outs[i].VT;
2865 // Get type of the original argument.
2866 EVT ActualVT = getValueType(DAG.getDataLayout(),
2867 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2868 /*AllowUnknown*/ true);
2869 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2870 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2871 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2872 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2874 else if (ActualMVT == MVT::i16)
2877 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2878 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2879 assert(!Res && "Call operand has unhandled type");
2884 // Get a count of how many bytes are to be pushed on the stack.
2885 unsigned NumBytes = CCInfo.getNextStackOffset();
2888 // Since we're not changing the ABI to make this a tail call, the memory
2889 // operands are already available in the caller's incoming argument space.
2893 // FPDiff is the byte offset of the call's argument area from the callee's.
2894 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2895 // by this amount for a tail call. In a sibling call it must be 0 because the
2896 // caller will deallocate the entire stack and the callee still expects its
2897 // arguments to begin at SP+0. Completely unused for non-tail calls.
2900 if (IsTailCall && !IsSibCall) {
2901 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2903 // Since callee will pop argument stack as a tail call, we must keep the
2904 // popped size 16-byte aligned.
2905 NumBytes = RoundUpToAlignment(NumBytes, 16);
2907 // FPDiff will be negative if this tail call requires more space than we
2908 // would automatically have in our incoming argument space. Positive if we
2909 // can actually shrink the stack.
2910 FPDiff = NumReusableBytes - NumBytes;
2912 // The stack pointer must be 16-byte aligned at all times it's used for a
2913 // memory operation, which in practice means at *all* times and in
2914 // particular across call boundaries. Therefore our own arguments started at
2915 // a 16-byte aligned SP and the delta applied for the tail call should
2916 // satisfy the same constraint.
2917 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2920 // Adjust the stack pointer for the new arguments...
2921 // These operations are automatically eliminated by the prolog/epilog pass
2923 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2927 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
2928 getPointerTy(DAG.getDataLayout()));
2930 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2931 SmallVector<SDValue, 8> MemOpChains;
2932 auto PtrVT = getPointerTy(DAG.getDataLayout());
2934 // Walk the register/memloc assignments, inserting copies/loads.
2935 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2936 ++i, ++realArgIdx) {
2937 CCValAssign &VA = ArgLocs[i];
2938 SDValue Arg = OutVals[realArgIdx];
2939 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2941 // Promote the value if needed.
2942 switch (VA.getLocInfo()) {
2944 llvm_unreachable("Unknown loc info!");
2945 case CCValAssign::Full:
2947 case CCValAssign::SExt:
2948 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2950 case CCValAssign::ZExt:
2951 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2953 case CCValAssign::AExt:
2954 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2955 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2956 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2957 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2959 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2961 case CCValAssign::BCvt:
2962 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2964 case CCValAssign::FPExt:
2965 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2969 if (VA.isRegLoc()) {
2970 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2971 assert(VA.getLocVT() == MVT::i64 &&
2972 "unexpected calling convention register assignment");
2973 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2974 "unexpected use of 'returned'");
2975 IsThisReturn = true;
2977 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2979 assert(VA.isMemLoc());
2982 MachinePointerInfo DstInfo;
2984 // FIXME: This works on big-endian for composite byvals, which are the
2985 // common case. It should also work for fundamental types too.
2986 uint32_t BEAlign = 0;
2987 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2988 : VA.getValVT().getSizeInBits();
2989 OpSize = (OpSize + 7) / 8;
2990 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2991 !Flags.isInConsecutiveRegs()) {
2993 BEAlign = 8 - OpSize;
2995 unsigned LocMemOffset = VA.getLocMemOffset();
2996 int32_t Offset = LocMemOffset + BEAlign;
2997 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2998 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3001 Offset = Offset + FPDiff;
3002 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3005 DstInfo = MachinePointerInfo::getFixedStack(FI);
3007 // Make sure any stack arguments overlapping with where we're storing
3008 // are loaded before this eventual operation. Otherwise they'll be
3010 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3012 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3014 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3015 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
3018 if (Outs[i].Flags.isByVal()) {
3020 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3021 SDValue Cpy = DAG.getMemcpy(
3022 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3023 /*isVol = */ false, /*AlwaysInline = */ false,
3024 /*isTailCall = */ false,
3025 DstInfo, MachinePointerInfo());
3027 MemOpChains.push_back(Cpy);
3029 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3030 // promoted to a legal register type i32, we should truncate Arg back to
3032 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3033 VA.getValVT() == MVT::i16)
3034 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3037 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
3038 MemOpChains.push_back(Store);
3043 if (!MemOpChains.empty())
3044 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3046 // Build a sequence of copy-to-reg nodes chained together with token chain
3047 // and flag operands which copy the outgoing args into the appropriate regs.
3049 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3050 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
3051 RegsToPass[i].second, InFlag);
3052 InFlag = Chain.getValue(1);
3055 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3056 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3057 // node so that legalize doesn't hack it.
3058 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3059 Subtarget->isTargetMachO()) {
3060 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3061 const GlobalValue *GV = G->getGlobal();
3062 bool InternalLinkage = GV->hasInternalLinkage();
3063 if (InternalLinkage)
3064 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3067 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3068 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3070 } else if (ExternalSymbolSDNode *S =
3071 dyn_cast<ExternalSymbolSDNode>(Callee)) {
3072 const char *Sym = S->getSymbol();
3073 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3074 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3076 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3077 const GlobalValue *GV = G->getGlobal();
3078 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3079 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3080 const char *Sym = S->getSymbol();
3081 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3084 // We don't usually want to end the call-sequence here because we would tidy
3085 // the frame up *after* the call, however in the ABI-changing tail-call case
3086 // we've carefully laid out the parameters so that when sp is reset they'll be
3087 // in the correct location.
3088 if (IsTailCall && !IsSibCall) {
3089 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3090 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3091 InFlag = Chain.getValue(1);
3094 std::vector<SDValue> Ops;
3095 Ops.push_back(Chain);
3096 Ops.push_back(Callee);
3099 // Each tail call may have to adjust the stack by a different amount, so
3100 // this information must travel along with the operation for eventual
3101 // consumption by emitEpilogue.
3102 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3105 // Add argument registers to the end of the list so that they are known live
3107 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3108 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3109 RegsToPass[i].second.getValueType()));
3111 // Add a register mask operand representing the call-preserved registers.
3112 const uint32_t *Mask;
3113 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3115 // For 'this' returns, use the X0-preserving mask if applicable
3116 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3118 IsThisReturn = false;
3119 Mask = TRI->getCallPreservedMask(MF, CallConv);
3122 Mask = TRI->getCallPreservedMask(MF, CallConv);
3124 assert(Mask && "Missing call preserved mask for calling convention");
3125 Ops.push_back(DAG.getRegisterMask(Mask));
3127 if (InFlag.getNode())
3128 Ops.push_back(InFlag);
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3132 // If we're doing a tall call, use a TC_RETURN here rather than an
3133 // actual call instruction.
3135 MF.getFrameInfo()->setHasTailCall();
3136 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3139 // Returns a chain and a flag for retval copy to use.
3140 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3141 InFlag = Chain.getValue(1);
3143 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
3144 ? RoundUpToAlignment(NumBytes, 16)
3147 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3148 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3151 InFlag = Chain.getValue(1);
3153 // Handle result values, copying them out of physregs into vregs that we
3155 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3156 InVals, IsThisReturn,
3157 IsThisReturn ? OutVals[0] : SDValue());
3160 bool AArch64TargetLowering::CanLowerReturn(
3161 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3162 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3163 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3164 ? RetCC_AArch64_WebKit_JS
3165 : RetCC_AArch64_AAPCS;
3166 SmallVector<CCValAssign, 16> RVLocs;
3167 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3168 return CCInfo.CheckReturn(Outs, RetCC);
3172 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3174 const SmallVectorImpl<ISD::OutputArg> &Outs,
3175 const SmallVectorImpl<SDValue> &OutVals,
3176 SDLoc DL, SelectionDAG &DAG) const {
3177 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3178 ? RetCC_AArch64_WebKit_JS
3179 : RetCC_AArch64_AAPCS;
3180 SmallVector<CCValAssign, 16> RVLocs;
3181 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3183 CCInfo.AnalyzeReturn(Outs, RetCC);
3185 // Copy the result values into the output registers.
3187 SmallVector<SDValue, 4> RetOps(1, Chain);
3188 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3189 ++i, ++realRVLocIdx) {
3190 CCValAssign &VA = RVLocs[i];
3191 assert(VA.isRegLoc() && "Can only return in registers!");
3192 SDValue Arg = OutVals[realRVLocIdx];
3194 switch (VA.getLocInfo()) {
3196 llvm_unreachable("Unknown loc info!");
3197 case CCValAssign::Full:
3198 if (Outs[i].ArgVT == MVT::i1) {
3199 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3200 // value. This is strictly redundant on Darwin (which uses "zeroext
3201 // i1"), but will be optimised out before ISel.
3202 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3203 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3206 case CCValAssign::BCvt:
3207 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3211 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3212 Flag = Chain.getValue(1);
3213 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3216 RetOps[0] = Chain; // Update chain.
3218 // Add the flag if we have it.
3220 RetOps.push_back(Flag);
3222 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3225 //===----------------------------------------------------------------------===//
3226 // Other Lowering Code
3227 //===----------------------------------------------------------------------===//
3229 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3230 SelectionDAG &DAG) const {
3231 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3233 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3234 const GlobalValue *GV = GN->getGlobal();
3235 unsigned char OpFlags =
3236 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3238 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
3239 "unexpected offset in global node");
3241 // This also catched the large code model case for Darwin.
3242 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3243 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
3244 // FIXME: Once remat is capable of dealing with instructions with register
3245 // operands, expand this into two nodes instead of using a wrapper node.
3246 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3249 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
3250 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3251 "use of MO_CONSTPOOL only supported on small model");
3252 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
3253 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3254 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3255 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
3256 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3257 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3258 MachinePointerInfo::getConstantPool(),
3259 /*isVolatile=*/ false,
3260 /*isNonTemporal=*/ true,
3261 /*isInvariant=*/ true, 8);
3262 if (GN->getOffset() != 0)
3263 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3264 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3268 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3269 const unsigned char MO_NC = AArch64II::MO_NC;
3271 AArch64ISD::WrapperLarge, DL, PtrVT,
3272 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3273 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3274 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3275 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3277 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3278 // the only correct model on Darwin.
3279 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3280 OpFlags | AArch64II::MO_PAGE);
3281 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3282 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3284 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3285 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3289 /// \brief Convert a TLS address reference into the correct sequence of loads
3290 /// and calls to compute the variable's address (for Darwin, currently) and
3291 /// return an SDValue containing the final node.
3293 /// Darwin only has one TLS scheme which must be capable of dealing with the
3294 /// fully general situation, in the worst case. This means:
3295 /// + "extern __thread" declaration.
3296 /// + Defined in a possibly unknown dynamic library.
3298 /// The general system is that each __thread variable has a [3 x i64] descriptor
3299 /// which contains information used by the runtime to calculate the address. The
3300 /// only part of this the compiler needs to know about is the first xword, which
3301 /// contains a function pointer that must be called with the address of the
3302 /// entire descriptor in "x0".
3304 /// Since this descriptor may be in a different unit, in general even the
3305 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3307 /// adrp x0, _var@TLVPPAGE
3308 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3309 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3310 /// ; the function pointer
3311 /// blr x1 ; Uses descriptor address in x0
3312 /// ; Address of _var is now in x0.
3314 /// If the address of _var's descriptor *is* known to the linker, then it can
3315 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3316 /// a slight efficiency gain.
3318 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3319 SelectionDAG &DAG) const {
3320 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3323 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3324 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3327 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3328 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3330 // The first entry in the descriptor is a function pointer that we must call
3331 // to obtain the address of the variable.
3332 SDValue Chain = DAG.getEntryNode();
3333 SDValue FuncTLVGet =
3334 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3335 false, true, true, 8);
3336 Chain = FuncTLVGet.getValue(1);
3338 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3339 MFI->setAdjustsStack(true);
3341 // TLS calls preserve all registers except those that absolutely must be
3342 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3344 const uint32_t *Mask =
3345 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3347 // Finally, we can make the call. This is just a degenerate version of a
3348 // normal AArch64 call node: x0 takes the address of the descriptor, and
3349 // returns the address of the variable in this thread.
3350 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3352 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3353 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3354 DAG.getRegisterMask(Mask), Chain.getValue(1));
3355 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3358 /// When accessing thread-local variables under either the general-dynamic or
3359 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3360 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3361 /// is a function pointer to carry out the resolution.
3363 /// The sequence is:
3364 /// adrp x0, :tlsdesc:var
3365 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3366 /// add x0, x0, #:tlsdesc_lo12:var
3367 /// .tlsdesccall var
3369 /// (TPIDR_EL0 offset now in x0)
3371 /// The above sequence must be produced unscheduled, to enable the linker to
3372 /// optimize/relax this sequence.
3373 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3374 /// above sequence, and expanded really late in the compilation flow, to ensure
3375 /// the sequence is produced as per above.
3376 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3377 SelectionDAG &DAG) const {
3378 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3380 SDValue Chain = DAG.getEntryNode();
3381 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3383 SmallVector<SDValue, 2> Ops;
3384 Ops.push_back(Chain);
3385 Ops.push_back(SymAddr);
3387 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3388 SDValue Glue = Chain.getValue(1);
3390 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3394 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3395 SelectionDAG &DAG) const {
3396 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3397 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3398 "ELF TLS only supported in small memory model");
3399 // Different choices can be made for the maximum size of the TLS area for a
3400 // module. For the small address model, the default TLS size is 16MiB and the
3401 // maximum TLS size is 4GiB.
3402 // FIXME: add -mtls-size command line option and make it control the 16MiB
3403 // vs. 4GiB code sequence generation.
3404 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3406 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3408 if (DAG.getTarget().Options.EmulatedTLS)
3409 return LowerToTLSEmulatedModel(GA, DAG);
3411 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3412 if (Model == TLSModel::LocalDynamic)
3413 Model = TLSModel::GeneralDynamic;
3417 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3419 const GlobalValue *GV = GA->getGlobal();
3421 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3423 if (Model == TLSModel::LocalExec) {
3424 SDValue HiVar = DAG.getTargetGlobalAddress(
3425 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3426 SDValue LoVar = DAG.getTargetGlobalAddress(
3428 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3430 SDValue TPWithOff_lo =
3431 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3433 DAG.getTargetConstant(0, DL, MVT::i32)),
3436 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3438 DAG.getTargetConstant(0, DL, MVT::i32)),
3441 } else if (Model == TLSModel::InitialExec) {
3442 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3443 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3444 } else if (Model == TLSModel::LocalDynamic) {
3445 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3446 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3447 // the beginning of the module's TLS region, followed by a DTPREL offset
3450 // These accesses will need deduplicating if there's more than one.
3451 AArch64FunctionInfo *MFI =
3452 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3453 MFI->incNumLocalDynamicTLSAccesses();
3455 // The call needs a relocation too for linker relaxation. It doesn't make
3456 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3458 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3461 // Now we can calculate the offset from TPIDR_EL0 to this module's
3462 // thread-local area.
3463 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3465 // Now use :dtprel_whatever: operations to calculate this variable's offset
3466 // in its thread-storage area.
3467 SDValue HiVar = DAG.getTargetGlobalAddress(
3468 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3469 SDValue LoVar = DAG.getTargetGlobalAddress(
3470 GV, DL, MVT::i64, 0,
3471 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3473 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3474 DAG.getTargetConstant(0, DL, MVT::i32)),
3476 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3477 DAG.getTargetConstant(0, DL, MVT::i32)),
3479 } else if (Model == TLSModel::GeneralDynamic) {
3480 // The call needs a relocation too for linker relaxation. It doesn't make
3481 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3484 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3486 // Finally we can make a call to calculate the offset from tpidr_el0.
3487 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3489 llvm_unreachable("Unsupported ELF TLS access model");
3491 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3494 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3495 SelectionDAG &DAG) const {
3496 if (Subtarget->isTargetDarwin())
3497 return LowerDarwinGlobalTLSAddress(Op, DAG);
3498 else if (Subtarget->isTargetELF())
3499 return LowerELFGlobalTLSAddress(Op, DAG);
3501 llvm_unreachable("Unexpected platform trying to use TLS");
3503 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3504 SDValue Chain = Op.getOperand(0);
3505 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3506 SDValue LHS = Op.getOperand(2);
3507 SDValue RHS = Op.getOperand(3);
3508 SDValue Dest = Op.getOperand(4);
3511 // Handle f128 first, since lowering it will result in comparing the return
3512 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3513 // is expecting to deal with.
3514 if (LHS.getValueType() == MVT::f128) {
3515 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3517 // If softenSetCCOperands returned a scalar, we need to compare the result
3518 // against zero to select between true and false values.
3519 if (!RHS.getNode()) {
3520 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3525 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3527 unsigned Opc = LHS.getOpcode();
3528 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3529 cast<ConstantSDNode>(RHS)->isOne() &&
3530 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3531 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3532 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3533 "Unexpected condition code.");
3534 // Only lower legal XALUO ops.
3535 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3538 // The actual operation with overflow check.
3539 AArch64CC::CondCode OFCC;
3540 SDValue Value, Overflow;
3541 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3543 if (CC == ISD::SETNE)
3544 OFCC = getInvertedCondCode(OFCC);
3545 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3547 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3551 if (LHS.getValueType().isInteger()) {
3552 assert((LHS.getValueType() == RHS.getValueType()) &&
3553 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3555 // If the RHS of the comparison is zero, we can potentially fold this
3556 // to a specialized branch.
3557 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3558 if (RHSC && RHSC->getZExtValue() == 0) {
3559 if (CC == ISD::SETEQ) {
3560 // See if we can use a TBZ to fold in an AND as well.
3561 // TBZ has a smaller branch displacement than CBZ. If the offset is
3562 // out of bounds, a late MI-layer pass rewrites branches.
3563 // 403.gcc is an example that hits this case.
3564 if (LHS.getOpcode() == ISD::AND &&
3565 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3566 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3567 SDValue Test = LHS.getOperand(0);
3568 uint64_t Mask = LHS.getConstantOperandVal(1);
3569 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3570 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3574 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3575 } else if (CC == ISD::SETNE) {
3576 // See if we can use a TBZ to fold in an AND as well.
3577 // TBZ has a smaller branch displacement than CBZ. If the offset is
3578 // out of bounds, a late MI-layer pass rewrites branches.
3579 // 403.gcc is an example that hits this case.
3580 if (LHS.getOpcode() == ISD::AND &&
3581 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3582 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3583 SDValue Test = LHS.getOperand(0);
3584 uint64_t Mask = LHS.getConstantOperandVal(1);
3585 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3586 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3590 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3591 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3592 // Don't combine AND since emitComparison converts the AND to an ANDS
3593 // (a.k.a. TST) and the test in the test bit and branch instruction
3594 // becomes redundant. This would also increase register pressure.
3595 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3596 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3597 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3600 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3601 LHS.getOpcode() != ISD::AND) {
3602 // Don't combine AND since emitComparison converts the AND to an ANDS
3603 // (a.k.a. TST) and the test in the test bit and branch instruction
3604 // becomes redundant. This would also increase register pressure.
3605 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3606 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3607 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3611 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3612 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3616 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3618 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3619 // clean. Some of them require two branches to implement.
3620 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3621 AArch64CC::CondCode CC1, CC2;
3622 changeFPCCToAArch64CC(CC, CC1, CC2);
3623 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3625 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3626 if (CC2 != AArch64CC::AL) {
3627 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3628 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3635 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3636 SelectionDAG &DAG) const {
3637 EVT VT = Op.getValueType();
3640 SDValue In1 = Op.getOperand(0);
3641 SDValue In2 = Op.getOperand(1);
3642 EVT SrcVT = In2.getValueType();
3644 if (SrcVT == MVT::f32 && VT == MVT::f64)
3645 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3646 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3647 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3648 DAG.getIntPtrConstant(0, DL));
3650 // FIXME: Src type is different, bail out for now. Can VT really be a
3658 SDValue VecVal1, VecVal2;
3659 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3662 EltMask = 0x80000000ULL;
3664 if (!VT.isVector()) {
3665 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3666 DAG.getUNDEF(VecVT), In1);
3667 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3668 DAG.getUNDEF(VecVT), In2);
3670 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3671 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3673 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3677 // We want to materialize a mask with the high bit set, but the AdvSIMD
3678 // immediate moves cannot materialize that in a single instruction for
3679 // 64-bit elements. Instead, materialize zero and then negate it.
3682 if (!VT.isVector()) {
3683 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3684 DAG.getUNDEF(VecVT), In1);
3685 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3686 DAG.getUNDEF(VecVT), In2);
3688 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3689 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3692 llvm_unreachable("Invalid type for copysign!");
3695 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3697 // If we couldn't materialize the mask above, then the mask vector will be
3698 // the zero vector, and we need to negate it here.
3699 if (VT == MVT::f64 || VT == MVT::v2f64) {
3700 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3701 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3702 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3706 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3709 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3710 else if (VT == MVT::f64)
3711 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3713 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3716 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3717 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3718 Attribute::NoImplicitFloat))
3721 if (!Subtarget->hasNEON())
3724 // While there is no integer popcount instruction, it can
3725 // be more efficiently lowered to the following sequence that uses
3726 // AdvSIMD registers/instructions as long as the copies to/from
3727 // the AdvSIMD registers are cheap.
3728 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3729 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3730 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3731 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3732 SDValue Val = Op.getOperand(0);
3734 EVT VT = Op.getValueType();
3737 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3738 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3740 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3741 SDValue UaddLV = DAG.getNode(
3742 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3743 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3746 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3750 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3752 if (Op.getValueType().isVector())
3753 return LowerVSETCC(Op, DAG);
3755 SDValue LHS = Op.getOperand(0);
3756 SDValue RHS = Op.getOperand(1);
3757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3760 // We chose ZeroOrOneBooleanContents, so use zero and one.
3761 EVT VT = Op.getValueType();
3762 SDValue TVal = DAG.getConstant(1, dl, VT);
3763 SDValue FVal = DAG.getConstant(0, dl, VT);
3765 // Handle f128 first, since one possible outcome is a normal integer
3766 // comparison which gets picked up by the next if statement.
3767 if (LHS.getValueType() == MVT::f128) {
3768 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3770 // If softenSetCCOperands returned a scalar, use it.
3771 if (!RHS.getNode()) {
3772 assert(LHS.getValueType() == Op.getValueType() &&
3773 "Unexpected setcc expansion!");
3778 if (LHS.getValueType().isInteger()) {
3781 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3783 // Note that we inverted the condition above, so we reverse the order of
3784 // the true and false operands here. This will allow the setcc to be
3785 // matched to a single CSINC instruction.
3786 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3789 // Now we know we're dealing with FP values.
3790 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3792 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3793 // and do the comparison.
3794 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3796 AArch64CC::CondCode CC1, CC2;
3797 changeFPCCToAArch64CC(CC, CC1, CC2);
3798 if (CC2 == AArch64CC::AL) {
3799 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3800 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3802 // Note that we inverted the condition above, so we reverse the order of
3803 // the true and false operands here. This will allow the setcc to be
3804 // matched to a single CSINC instruction.
3805 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3807 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3808 // totally clean. Some of them require two CSELs to implement. As is in
3809 // this case, we emit the first CSEL and then emit a second using the output
3810 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3812 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3813 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3815 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3817 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3818 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3822 /// A SELECT_CC operation is really some kind of max or min if both values being
3823 /// compared are, in some sense, equal to the results in either case. However,
3824 /// it is permissible to compare f32 values and produce directly extended f64
3827 /// Extending the comparison operands would also be allowed, but is less likely
3828 /// to happen in practice since their use is right here. Note that truncate
3829 /// operations would *not* be semantically equivalent.
3830 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3832 return (Cmp.getValueType() == MVT::f32 ||
3833 Cmp.getValueType() == MVT::f64);
3835 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3836 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3837 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3838 Result.getValueType() == MVT::f64) {
3840 APFloat CmpVal = CCmp->getValueAPF();
3841 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3842 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3845 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3848 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3849 SDValue RHS, SDValue TVal,
3850 SDValue FVal, SDLoc dl,
3851 SelectionDAG &DAG) const {
3852 // Handle f128 first, because it will result in a comparison of some RTLIB
3853 // call result against zero.
3854 if (LHS.getValueType() == MVT::f128) {
3855 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3857 // If softenSetCCOperands returned a scalar, we need to compare the result
3858 // against zero to select between true and false values.
3859 if (!RHS.getNode()) {
3860 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3865 // Handle integers first.
3866 if (LHS.getValueType().isInteger()) {
3867 assert((LHS.getValueType() == RHS.getValueType()) &&
3868 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3870 unsigned Opcode = AArch64ISD::CSEL;
3872 // If both the TVal and the FVal are constants, see if we can swap them in
3873 // order to for a CSINV or CSINC out of them.
3874 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3875 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3877 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3878 std::swap(TVal, FVal);
3879 std::swap(CTVal, CFVal);
3880 CC = ISD::getSetCCInverse(CC, true);
3881 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3882 std::swap(TVal, FVal);
3883 std::swap(CTVal, CFVal);
3884 CC = ISD::getSetCCInverse(CC, true);
3885 } else if (TVal.getOpcode() == ISD::XOR) {
3886 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3887 // with a CSINV rather than a CSEL.
3888 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3890 if (CVal && CVal->isAllOnesValue()) {
3891 std::swap(TVal, FVal);
3892 std::swap(CTVal, CFVal);
3893 CC = ISD::getSetCCInverse(CC, true);
3895 } else if (TVal.getOpcode() == ISD::SUB) {
3896 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3897 // that we can match with a CSNEG rather than a CSEL.
3898 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3900 if (CVal && CVal->isNullValue()) {
3901 std::swap(TVal, FVal);
3902 std::swap(CTVal, CFVal);
3903 CC = ISD::getSetCCInverse(CC, true);
3905 } else if (CTVal && CFVal) {
3906 const int64_t TrueVal = CTVal->getSExtValue();
3907 const int64_t FalseVal = CFVal->getSExtValue();
3910 // If both TVal and FVal are constants, see if FVal is the
3911 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3912 // instead of a CSEL in that case.
3913 if (TrueVal == ~FalseVal) {
3914 Opcode = AArch64ISD::CSINV;
3915 } else if (TrueVal == -FalseVal) {
3916 Opcode = AArch64ISD::CSNEG;
3917 } else if (TVal.getValueType() == MVT::i32) {
3918 // If our operands are only 32-bit wide, make sure we use 32-bit
3919 // arithmetic for the check whether we can use CSINC. This ensures that
3920 // the addition in the check will wrap around properly in case there is
3921 // an overflow (which would not be the case if we do the check with
3922 // 64-bit arithmetic).
3923 const uint32_t TrueVal32 = CTVal->getZExtValue();
3924 const uint32_t FalseVal32 = CFVal->getZExtValue();
3926 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3927 Opcode = AArch64ISD::CSINC;
3929 if (TrueVal32 > FalseVal32) {
3933 // 64-bit check whether we can use CSINC.
3934 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3935 Opcode = AArch64ISD::CSINC;
3937 if (TrueVal > FalseVal) {
3942 // Swap TVal and FVal if necessary.
3944 std::swap(TVal, FVal);
3945 std::swap(CTVal, CFVal);
3946 CC = ISD::getSetCCInverse(CC, true);
3949 if (Opcode != AArch64ISD::CSEL) {
3950 // Drop FVal since we can get its value by simply inverting/negating
3957 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3959 EVT VT = TVal.getValueType();
3960 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3963 // Now we know we're dealing with FP values.
3964 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3965 assert(LHS.getValueType() == RHS.getValueType());
3966 EVT VT = TVal.getValueType();
3967 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3969 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3970 // clean. Some of them require two CSELs to implement.
3971 AArch64CC::CondCode CC1, CC2;
3972 changeFPCCToAArch64CC(CC, CC1, CC2);
3973 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3974 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3976 // If we need a second CSEL, emit it, using the output of the first as the
3977 // RHS. We're effectively OR'ing the two CC's together.
3978 if (CC2 != AArch64CC::AL) {
3979 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3980 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3983 // Otherwise, return the output of the first CSEL.
3987 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3988 SelectionDAG &DAG) const {
3989 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3990 SDValue LHS = Op.getOperand(0);
3991 SDValue RHS = Op.getOperand(1);
3992 SDValue TVal = Op.getOperand(2);
3993 SDValue FVal = Op.getOperand(3);
3995 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3998 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3999 SelectionDAG &DAG) const {
4000 SDValue CCVal = Op->getOperand(0);
4001 SDValue TVal = Op->getOperand(1);
4002 SDValue FVal = Op->getOperand(2);
4005 unsigned Opc = CCVal.getOpcode();
4006 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4008 if (CCVal.getResNo() == 1 &&
4009 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4010 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4011 // Only lower legal XALUO ops.
4012 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4015 AArch64CC::CondCode OFCC;
4016 SDValue Value, Overflow;
4017 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4018 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4020 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4024 // Lower it the same way as we would lower a SELECT_CC node.
4027 if (CCVal.getOpcode() == ISD::SETCC) {
4028 LHS = CCVal.getOperand(0);
4029 RHS = CCVal.getOperand(1);
4030 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4033 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4036 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4039 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4040 SelectionDAG &DAG) const {
4041 // Jump table entries as PC relative offsets. No additional tweaking
4042 // is necessary here. Just get the address of the jump table.
4043 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4044 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4047 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4048 !Subtarget->isTargetMachO()) {
4049 const unsigned char MO_NC = AArch64II::MO_NC;
4051 AArch64ISD::WrapperLarge, DL, PtrVT,
4052 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
4053 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
4054 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
4055 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4056 AArch64II::MO_G0 | MO_NC));
4060 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
4061 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4062 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4063 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4064 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4067 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4068 SelectionDAG &DAG) const {
4069 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4070 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4073 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4074 // Use the GOT for the large code model on iOS.
4075 if (Subtarget->isTargetMachO()) {
4076 SDValue GotAddr = DAG.getTargetConstantPool(
4077 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4079 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
4082 const unsigned char MO_NC = AArch64II::MO_NC;
4084 AArch64ISD::WrapperLarge, DL, PtrVT,
4085 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4086 CP->getOffset(), AArch64II::MO_G3),
4087 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4088 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
4089 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4090 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
4091 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4092 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
4094 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4095 // ELF, the only valid one on Darwin.
4097 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4098 CP->getOffset(), AArch64II::MO_PAGE);
4099 SDValue Lo = DAG.getTargetConstantPool(
4100 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4101 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4103 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4104 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4108 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4109 SelectionDAG &DAG) const {
4110 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4111 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4113 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4114 !Subtarget->isTargetMachO()) {
4115 const unsigned char MO_NC = AArch64II::MO_NC;
4117 AArch64ISD::WrapperLarge, DL, PtrVT,
4118 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
4119 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
4120 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
4121 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
4123 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
4124 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
4126 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4127 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4131 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4132 SelectionDAG &DAG) const {
4133 AArch64FunctionInfo *FuncInfo =
4134 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4137 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4138 getPointerTy(DAG.getDataLayout()));
4139 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4140 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4141 MachinePointerInfo(SV), false, false, 0);
4144 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4145 SelectionDAG &DAG) const {
4146 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4147 // Standard, section B.3.
4148 MachineFunction &MF = DAG.getMachineFunction();
4149 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4150 auto PtrVT = getPointerTy(DAG.getDataLayout());
4153 SDValue Chain = Op.getOperand(0);
4154 SDValue VAList = Op.getOperand(1);
4155 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4156 SmallVector<SDValue, 4> MemOps;
4158 // void *__stack at offset 0
4159 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4160 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4161 MachinePointerInfo(SV), false, false, 8));
4163 // void *__gr_top at offset 8
4164 int GPRSize = FuncInfo->getVarArgsGPRSize();
4166 SDValue GRTop, GRTopAddr;
4169 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4171 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4172 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4173 DAG.getConstant(GPRSize, DL, PtrVT));
4175 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4176 MachinePointerInfo(SV, 8), false, false, 8));
4179 // void *__vr_top at offset 16
4180 int FPRSize = FuncInfo->getVarArgsFPRSize();
4182 SDValue VRTop, VRTopAddr;
4183 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4184 DAG.getConstant(16, DL, PtrVT));
4186 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4187 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4188 DAG.getConstant(FPRSize, DL, PtrVT));
4190 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4191 MachinePointerInfo(SV, 16), false, false, 8));
4194 // int __gr_offs at offset 24
4195 SDValue GROffsAddr =
4196 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4197 MemOps.push_back(DAG.getStore(Chain, DL,
4198 DAG.getConstant(-GPRSize, DL, MVT::i32),
4199 GROffsAddr, MachinePointerInfo(SV, 24), false,
4202 // int __vr_offs at offset 28
4203 SDValue VROffsAddr =
4204 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4205 MemOps.push_back(DAG.getStore(Chain, DL,
4206 DAG.getConstant(-FPRSize, DL, MVT::i32),
4207 VROffsAddr, MachinePointerInfo(SV, 28), false,
4210 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4213 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4214 SelectionDAG &DAG) const {
4215 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
4216 : LowerAAPCS_VASTART(Op, DAG);
4219 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4220 SelectionDAG &DAG) const {
4221 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4224 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
4225 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4226 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4228 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4230 DAG.getConstant(VaListSize, DL, MVT::i32),
4231 8, false, false, false, MachinePointerInfo(DestSV),
4232 MachinePointerInfo(SrcSV));
4235 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4236 assert(Subtarget->isTargetDarwin() &&
4237 "automatic va_arg instruction only works on Darwin");
4239 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4240 EVT VT = Op.getValueType();
4242 SDValue Chain = Op.getOperand(0);
4243 SDValue Addr = Op.getOperand(1);
4244 unsigned Align = Op.getConstantOperandVal(3);
4245 auto PtrVT = getPointerTy(DAG.getDataLayout());
4247 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V),
4248 false, false, false, 0);
4249 Chain = VAList.getValue(1);
4252 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4253 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4254 DAG.getConstant(Align - 1, DL, PtrVT));
4255 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4256 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4259 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4260 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4262 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4263 // up to 64 bits. At the very least, we have to increase the striding of the
4264 // vaargs list to match this, and for FP values we need to introduce
4265 // FP_ROUND nodes as well.
4266 if (VT.isInteger() && !VT.isVector())
4268 bool NeedFPTrunc = false;
4269 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4274 // Increment the pointer, VAList, to the next vaarg
4275 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4276 DAG.getConstant(ArgSize, DL, PtrVT));
4277 // Store the incremented VAList to the legalized pointer
4278 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4281 // Load the actual argument out of the pointer VAList
4283 // Load the value as an f64.
4284 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4285 MachinePointerInfo(), false, false, false, 0);
4286 // Round the value down to an f32.
4287 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4288 DAG.getIntPtrConstant(1, DL));
4289 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4290 // Merge the rounded value with the chain output of the load.
4291 return DAG.getMergeValues(Ops, DL);
4294 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4298 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4299 SelectionDAG &DAG) const {
4300 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4301 MFI->setFrameAddressIsTaken(true);
4303 EVT VT = Op.getValueType();
4305 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4307 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4309 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4310 MachinePointerInfo(), false, false, false, 0);
4314 // FIXME? Maybe this could be a TableGen attribute on some registers and
4315 // this table could be generated automatically from RegInfo.
4316 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4317 SelectionDAG &DAG) const {
4318 unsigned Reg = StringSwitch<unsigned>(RegName)
4319 .Case("sp", AArch64::SP)
4323 report_fatal_error(Twine("Invalid register name \""
4324 + StringRef(RegName) + "\"."));
4327 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4328 SelectionDAG &DAG) const {
4329 MachineFunction &MF = DAG.getMachineFunction();
4330 MachineFrameInfo *MFI = MF.getFrameInfo();
4331 MFI->setReturnAddressIsTaken(true);
4333 EVT VT = Op.getValueType();
4335 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4337 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4338 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4339 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4340 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4341 MachinePointerInfo(), false, false, false, 0);
4344 // Return LR, which contains the return address. Mark it an implicit live-in.
4345 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4346 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4349 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4350 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4351 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4352 SelectionDAG &DAG) const {
4353 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4354 EVT VT = Op.getValueType();
4355 unsigned VTBits = VT.getSizeInBits();
4357 SDValue ShOpLo = Op.getOperand(0);
4358 SDValue ShOpHi = Op.getOperand(1);
4359 SDValue ShAmt = Op.getOperand(2);
4361 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4363 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4365 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4366 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4367 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4368 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4369 DAG.getConstant(VTBits, dl, MVT::i64));
4370 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4372 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4373 ISD::SETGE, dl, DAG);
4374 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4376 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4377 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4379 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4381 // AArch64 shifts larger than the register width are wrapped rather than
4382 // clamped, so we can't just emit "hi >> x".
4383 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4384 SDValue TrueValHi = Opc == ISD::SRA
4385 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4386 DAG.getConstant(VTBits - 1, dl,
4388 : DAG.getConstant(0, dl, VT);
4390 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4392 SDValue Ops[2] = { Lo, Hi };
4393 return DAG.getMergeValues(Ops, dl);
4396 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4397 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4398 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4399 SelectionDAG &DAG) const {
4400 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4401 EVT VT = Op.getValueType();
4402 unsigned VTBits = VT.getSizeInBits();
4404 SDValue ShOpLo = Op.getOperand(0);
4405 SDValue ShOpHi = Op.getOperand(1);
4406 SDValue ShAmt = Op.getOperand(2);
4409 assert(Op.getOpcode() == ISD::SHL_PARTS);
4410 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4411 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4412 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4413 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4414 DAG.getConstant(VTBits, dl, MVT::i64));
4415 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4416 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4418 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4420 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4421 ISD::SETGE, dl, DAG);
4422 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4424 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4426 // AArch64 shifts of larger than register sizes are wrapped rather than
4427 // clamped, so we can't just emit "lo << a" if a is too big.
4428 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4429 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4431 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4433 SDValue Ops[2] = { Lo, Hi };
4434 return DAG.getMergeValues(Ops, dl);
4437 bool AArch64TargetLowering::isOffsetFoldingLegal(
4438 const GlobalAddressSDNode *GA) const {
4439 // The AArch64 target doesn't support folding offsets into global addresses.
4443 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4444 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4445 // FIXME: We should be able to handle f128 as well with a clever lowering.
4446 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4450 return AArch64_AM::getFP64Imm(Imm) != -1;
4451 else if (VT == MVT::f32)
4452 return AArch64_AM::getFP32Imm(Imm) != -1;
4456 //===----------------------------------------------------------------------===//
4457 // AArch64 Optimization Hooks
4458 //===----------------------------------------------------------------------===//
4460 //===----------------------------------------------------------------------===//
4461 // AArch64 Inline Assembly Support
4462 //===----------------------------------------------------------------------===//
4464 // Table of Constraints
4465 // TODO: This is the current set of constraints supported by ARM for the
4466 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4468 // r - A general register
4469 // w - An FP/SIMD register of some size in the range v0-v31
4470 // x - An FP/SIMD register of some size in the range v0-v15
4471 // I - Constant that can be used with an ADD instruction
4472 // J - Constant that can be used with a SUB instruction
4473 // K - Constant that can be used with a 32-bit logical instruction
4474 // L - Constant that can be used with a 64-bit logical instruction
4475 // M - Constant that can be used as a 32-bit MOV immediate
4476 // N - Constant that can be used as a 64-bit MOV immediate
4477 // Q - A memory reference with base register and no offset
4478 // S - A symbolic address
4479 // Y - Floating point constant zero
4480 // Z - Integer constant zero
4482 // Note that general register operands will be output using their 64-bit x
4483 // register name, whatever the size of the variable, unless the asm operand
4484 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4485 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4488 /// getConstraintType - Given a constraint letter, return the type of
4489 /// constraint it is for this target.
4490 AArch64TargetLowering::ConstraintType
4491 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4492 if (Constraint.size() == 1) {
4493 switch (Constraint[0]) {
4500 return C_RegisterClass;
4501 // An address with a single base register. Due to the way we
4502 // currently handle addresses it is the same as 'r'.
4507 return TargetLowering::getConstraintType(Constraint);
4510 /// Examine constraint type and operand type and determine a weight value.
4511 /// This object must already have been set up with the operand type
4512 /// and the current alternative constraint selected.
4513 TargetLowering::ConstraintWeight
4514 AArch64TargetLowering::getSingleConstraintMatchWeight(
4515 AsmOperandInfo &info, const char *constraint) const {
4516 ConstraintWeight weight = CW_Invalid;
4517 Value *CallOperandVal = info.CallOperandVal;
4518 // If we don't have a value, we can't do a match,
4519 // but allow it at the lowest weight.
4520 if (!CallOperandVal)
4522 Type *type = CallOperandVal->getType();
4523 // Look at the constraint type.
4524 switch (*constraint) {
4526 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4530 if (type->isFloatingPointTy() || type->isVectorTy())
4531 weight = CW_Register;
4534 weight = CW_Constant;
4540 std::pair<unsigned, const TargetRegisterClass *>
4541 AArch64TargetLowering::getRegForInlineAsmConstraint(
4542 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4543 if (Constraint.size() == 1) {
4544 switch (Constraint[0]) {
4546 if (VT.getSizeInBits() == 64)
4547 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4548 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4551 return std::make_pair(0U, &AArch64::FPR32RegClass);
4552 if (VT.getSizeInBits() == 64)
4553 return std::make_pair(0U, &AArch64::FPR64RegClass);
4554 if (VT.getSizeInBits() == 128)
4555 return std::make_pair(0U, &AArch64::FPR128RegClass);
4557 // The instructions that this constraint is designed for can
4558 // only take 128-bit registers so just use that regclass.
4560 if (VT.getSizeInBits() == 128)
4561 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4565 if (StringRef("{cc}").equals_lower(Constraint))
4566 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4568 // Use the default implementation in TargetLowering to convert the register
4569 // constraint into a member of a register class.
4570 std::pair<unsigned, const TargetRegisterClass *> Res;
4571 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4573 // Not found as a standard register?
4575 unsigned Size = Constraint.size();
4576 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4577 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4579 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4580 if (!Failed && RegNo >= 0 && RegNo <= 31) {
4581 // v0 - v31 are aliases of q0 - q31.
4582 // By default we'll emit v0-v31 for this unless there's a modifier where
4583 // we'll emit the correct register as well.
4584 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4585 Res.second = &AArch64::FPR128RegClass;
4593 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4594 /// vector. If it is invalid, don't add anything to Ops.
4595 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4596 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4597 SelectionDAG &DAG) const {
4600 // Currently only support length 1 constraints.
4601 if (Constraint.length() != 1)
4604 char ConstraintLetter = Constraint[0];
4605 switch (ConstraintLetter) {
4609 // This set of constraints deal with valid constants for various instructions.
4610 // Validate and return a target constant for them if we can.
4612 // 'z' maps to xzr or wzr so it needs an input of 0.
4613 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4614 if (!C || C->getZExtValue() != 0)
4617 if (Op.getValueType() == MVT::i64)
4618 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4620 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4630 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4634 // Grab the value and do some validation.
4635 uint64_t CVal = C->getZExtValue();
4636 switch (ConstraintLetter) {
4637 // The I constraint applies only to simple ADD or SUB immediate operands:
4638 // i.e. 0 to 4095 with optional shift by 12
4639 // The J constraint applies only to ADD or SUB immediates that would be
4640 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4641 // instruction [or vice versa], in other words -1 to -4095 with optional
4642 // left shift by 12.
4644 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4648 uint64_t NVal = -C->getSExtValue();
4649 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4650 CVal = C->getSExtValue();
4655 // The K and L constraints apply *only* to logical immediates, including
4656 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4657 // been removed and MOV should be used). So these constraints have to
4658 // distinguish between bit patterns that are valid 32-bit or 64-bit
4659 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4660 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4663 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4667 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4670 // The M and N constraints are a superset of K and L respectively, for use
4671 // with the MOV (immediate) alias. As well as the logical immediates they
4672 // also match 32 or 64-bit immediates that can be loaded either using a
4673 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4674 // (M) or 64-bit 0x1234000000000000 (N) etc.
4675 // As a note some of this code is liberally stolen from the asm parser.
4677 if (!isUInt<32>(CVal))
4679 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4681 if ((CVal & 0xFFFF) == CVal)
4683 if ((CVal & 0xFFFF0000ULL) == CVal)
4685 uint64_t NCVal = ~(uint32_t)CVal;
4686 if ((NCVal & 0xFFFFULL) == NCVal)
4688 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4693 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4695 if ((CVal & 0xFFFFULL) == CVal)
4697 if ((CVal & 0xFFFF0000ULL) == CVal)
4699 if ((CVal & 0xFFFF00000000ULL) == CVal)
4701 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4703 uint64_t NCVal = ~CVal;
4704 if ((NCVal & 0xFFFFULL) == NCVal)
4706 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4708 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4710 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4718 // All assembler immediates are 64-bit integers.
4719 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4723 if (Result.getNode()) {
4724 Ops.push_back(Result);
4728 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4731 //===----------------------------------------------------------------------===//
4732 // AArch64 Advanced SIMD Support
4733 //===----------------------------------------------------------------------===//
4735 /// WidenVector - Given a value in the V64 register class, produce the
4736 /// equivalent value in the V128 register class.
4737 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4738 EVT VT = V64Reg.getValueType();
4739 unsigned NarrowSize = VT.getVectorNumElements();
4740 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4741 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4744 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4745 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4748 /// getExtFactor - Determine the adjustment factor for the position when
4749 /// generating an "extract from vector registers" instruction.
4750 static unsigned getExtFactor(SDValue &V) {
4751 EVT EltType = V.getValueType().getVectorElementType();
4752 return EltType.getSizeInBits() / 8;
4755 /// NarrowVector - Given a value in the V128 register class, produce the
4756 /// equivalent value in the V64 register class.
4757 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4758 EVT VT = V128Reg.getValueType();
4759 unsigned WideSize = VT.getVectorNumElements();
4760 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4761 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4764 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4767 // Gather data to see if the operation can be modelled as a
4768 // shuffle in combination with VEXTs.
4769 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4770 SelectionDAG &DAG) const {
4771 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4773 EVT VT = Op.getValueType();
4774 unsigned NumElts = VT.getVectorNumElements();
4776 struct ShuffleSourceInfo {
4781 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4782 // be compatible with the shuffle we intend to construct. As a result
4783 // ShuffleVec will be some sliding window into the original Vec.
4786 // Code should guarantee that element i in Vec starts at element "WindowBase
4787 // + i * WindowScale in ShuffleVec".
4791 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4792 ShuffleSourceInfo(SDValue Vec)
4793 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4797 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4799 SmallVector<ShuffleSourceInfo, 2> Sources;
4800 for (unsigned i = 0; i < NumElts; ++i) {
4801 SDValue V = Op.getOperand(i);
4802 if (V.getOpcode() == ISD::UNDEF)
4804 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4805 // A shuffle can only come from building a vector from various
4806 // elements of other vectors.
4810 // Add this element source to the list if it's not already there.
4811 SDValue SourceVec = V.getOperand(0);
4812 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4813 if (Source == Sources.end())
4814 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4816 // Update the minimum and maximum lane number seen.
4817 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4818 Source->MinElt = std::min(Source->MinElt, EltNo);
4819 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4822 // Currently only do something sane when at most two source vectors
4824 if (Sources.size() > 2)
4827 // Find out the smallest element size among result and two sources, and use
4828 // it as element size to build the shuffle_vector.
4829 EVT SmallestEltTy = VT.getVectorElementType();
4830 for (auto &Source : Sources) {
4831 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4832 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4833 SmallestEltTy = SrcEltTy;
4836 unsigned ResMultiplier =
4837 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4838 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4839 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4841 // If the source vector is too wide or too narrow, we may nevertheless be able
4842 // to construct a compatible shuffle either by concatenating it with UNDEF or
4843 // extracting a suitable range of elements.
4844 for (auto &Src : Sources) {
4845 EVT SrcVT = Src.ShuffleVec.getValueType();
4847 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4850 // This stage of the search produces a source with the same element type as
4851 // the original, but with a total width matching the BUILD_VECTOR output.
4852 EVT EltVT = SrcVT.getVectorElementType();
4853 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4854 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4856 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4857 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4858 // We can pad out the smaller vector for free, so if it's part of a
4861 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4862 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4866 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4868 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4869 // Span too large for a VEXT to cope
4873 if (Src.MinElt >= NumSrcElts) {
4874 // The extraction can just take the second half
4876 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4877 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4878 Src.WindowBase = -NumSrcElts;
4879 } else if (Src.MaxElt < NumSrcElts) {
4880 // The extraction can just take the first half
4882 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4883 DAG.getConstant(0, dl, MVT::i64));
4885 // An actual VEXT is needed
4887 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4888 DAG.getConstant(0, dl, MVT::i64));
4890 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4891 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4892 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4894 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4896 DAG.getConstant(Imm, dl, MVT::i32));
4897 Src.WindowBase = -Src.MinElt;
4901 // Another possible incompatibility occurs from the vector element types. We
4902 // can fix this by bitcasting the source vectors to the same type we intend
4904 for (auto &Src : Sources) {
4905 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4906 if (SrcEltTy == SmallestEltTy)
4908 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4909 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4910 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4911 Src.WindowBase *= Src.WindowScale;
4914 // Final sanity check before we try to actually produce a shuffle.
4916 for (auto Src : Sources)
4917 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4920 // The stars all align, our next step is to produce the mask for the shuffle.
4921 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4922 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4923 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4924 SDValue Entry = Op.getOperand(i);
4925 if (Entry.getOpcode() == ISD::UNDEF)
4928 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4929 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4931 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4932 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4934 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4935 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4936 VT.getVectorElementType().getSizeInBits());
4937 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4939 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4940 // starting at the appropriate offset.
4941 int *LaneMask = &Mask[i * ResMultiplier];
4943 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4944 ExtractBase += NumElts * (Src - Sources.begin());
4945 for (int j = 0; j < LanesDefined; ++j)
4946 LaneMask[j] = ExtractBase + j;
4949 // Final check before we try to produce nonsense...
4950 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4953 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4954 for (unsigned i = 0; i < Sources.size(); ++i)
4955 ShuffleOps[i] = Sources[i].ShuffleVec;
4957 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4958 ShuffleOps[1], &Mask[0]);
4959 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4962 // check if an EXT instruction can handle the shuffle mask when the
4963 // vector sources of the shuffle are the same.
4964 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4965 unsigned NumElts = VT.getVectorNumElements();
4967 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4973 // If this is a VEXT shuffle, the immediate value is the index of the first
4974 // element. The other shuffle indices must be the successive elements after
4976 unsigned ExpectedElt = Imm;
4977 for (unsigned i = 1; i < NumElts; ++i) {
4978 // Increment the expected index. If it wraps around, just follow it
4979 // back to index zero and keep going.
4981 if (ExpectedElt == NumElts)
4985 continue; // ignore UNDEF indices
4986 if (ExpectedElt != static_cast<unsigned>(M[i]))
4993 // check if an EXT instruction can handle the shuffle mask when the
4994 // vector sources of the shuffle are different.
4995 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4997 // Look for the first non-undef element.
4998 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4999 [](int Elt) {return Elt >= 0;});
5001 // Benefit form APInt to handle overflow when calculating expected element.
5002 unsigned NumElts = VT.getVectorNumElements();
5003 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
5004 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
5005 // The following shuffle indices must be the successive elements after the
5006 // first real element.
5007 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5008 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5009 if (FirstWrongElt != M.end())
5012 // The index of an EXT is the first element if it is not UNDEF.
5013 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5014 // value of the first element. E.g.
5015 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5016 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5017 // ExpectedElt is the last mask index plus 1.
5018 Imm = ExpectedElt.getZExtValue();
5020 // There are two difference cases requiring to reverse input vectors.
5021 // For example, for vector <4 x i32> we have the following cases,
5022 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5023 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5024 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5025 // to reverse two input vectors.
5034 /// isREVMask - Check if a vector shuffle corresponds to a REV
5035 /// instruction with the specified blocksize. (The order of the elements
5036 /// within each block of the vector is reversed.)
5037 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5038 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
5039 "Only possible block sizes for REV are: 16, 32, 64");
5041 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5045 unsigned NumElts = VT.getVectorNumElements();
5046 unsigned BlockElts = M[0] + 1;
5047 // If the first shuffle index is UNDEF, be optimistic.
5049 BlockElts = BlockSize / EltSz;
5051 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5054 for (unsigned i = 0; i < NumElts; ++i) {
5056 continue; // ignore UNDEF indices
5057 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5064 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5065 unsigned NumElts = VT.getVectorNumElements();
5066 WhichResult = (M[0] == 0 ? 0 : 1);
5067 unsigned Idx = WhichResult * NumElts / 2;
5068 for (unsigned i = 0; i != NumElts; i += 2) {
5069 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5070 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5078 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5079 unsigned NumElts = VT.getVectorNumElements();
5080 WhichResult = (M[0] == 0 ? 0 : 1);
5081 for (unsigned i = 0; i != NumElts; ++i) {
5083 continue; // ignore UNDEF indices
5084 if ((unsigned)M[i] != 2 * i + WhichResult)
5091 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5092 unsigned NumElts = VT.getVectorNumElements();
5093 WhichResult = (M[0] == 0 ? 0 : 1);
5094 for (unsigned i = 0; i < NumElts; i += 2) {
5095 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5096 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5102 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5103 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5104 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5105 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5106 unsigned NumElts = VT.getVectorNumElements();
5107 WhichResult = (M[0] == 0 ? 0 : 1);
5108 unsigned Idx = WhichResult * NumElts / 2;
5109 for (unsigned i = 0; i != NumElts; i += 2) {
5110 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5111 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5119 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5120 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5121 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5122 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5123 unsigned Half = VT.getVectorNumElements() / 2;
5124 WhichResult = (M[0] == 0 ? 0 : 1);
5125 for (unsigned j = 0; j != 2; ++j) {
5126 unsigned Idx = WhichResult;
5127 for (unsigned i = 0; i != Half; ++i) {
5128 int MIdx = M[i + j * Half];
5129 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5138 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5139 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5140 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5141 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5142 unsigned NumElts = VT.getVectorNumElements();
5143 WhichResult = (M[0] == 0 ? 0 : 1);
5144 for (unsigned i = 0; i < NumElts; i += 2) {
5145 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5146 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5152 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5153 bool &DstIsLeft, int &Anomaly) {
5154 if (M.size() != static_cast<size_t>(NumInputElements))
5157 int NumLHSMatch = 0, NumRHSMatch = 0;
5158 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5160 for (int i = 0; i < NumInputElements; ++i) {
5170 LastLHSMismatch = i;
5172 if (M[i] == i + NumInputElements)
5175 LastRHSMismatch = i;
5178 if (NumLHSMatch == NumInputElements - 1) {
5180 Anomaly = LastLHSMismatch;
5182 } else if (NumRHSMatch == NumInputElements - 1) {
5184 Anomaly = LastRHSMismatch;
5191 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5192 if (VT.getSizeInBits() != 128)
5195 unsigned NumElts = VT.getVectorNumElements();
5197 for (int I = 0, E = NumElts / 2; I != E; I++) {
5202 int Offset = NumElts / 2;
5203 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5204 if (Mask[I] != I + SplitLHS * Offset)
5211 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5213 EVT VT = Op.getValueType();
5214 SDValue V0 = Op.getOperand(0);
5215 SDValue V1 = Op.getOperand(1);
5216 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5218 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5219 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5222 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
5224 if (!isConcatMask(Mask, VT, SplitV0))
5227 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5228 VT.getVectorNumElements() / 2);
5230 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5231 DAG.getConstant(0, DL, MVT::i64));
5233 if (V1.getValueType().getSizeInBits() == 128) {
5234 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5235 DAG.getConstant(0, DL, MVT::i64));
5237 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5240 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5241 /// the specified operations to build the shuffle.
5242 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5243 SDValue RHS, SelectionDAG &DAG,
5245 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5246 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5247 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5250 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5259 OP_VUZPL, // VUZP, left result
5260 OP_VUZPR, // VUZP, right result
5261 OP_VZIPL, // VZIP, left result
5262 OP_VZIPR, // VZIP, right result
5263 OP_VTRNL, // VTRN, left result
5264 OP_VTRNR // VTRN, right result
5267 if (OpNum == OP_COPY) {
5268 if (LHSID == (1 * 9 + 2) * 9 + 3)
5270 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5274 SDValue OpLHS, OpRHS;
5275 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5276 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5277 EVT VT = OpLHS.getValueType();
5281 llvm_unreachable("Unknown shuffle opcode!");
5283 // VREV divides the vector in half and swaps within the half.
5284 if (VT.getVectorElementType() == MVT::i32 ||
5285 VT.getVectorElementType() == MVT::f32)
5286 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5287 // vrev <4 x i16> -> REV32
5288 if (VT.getVectorElementType() == MVT::i16 ||
5289 VT.getVectorElementType() == MVT::f16)
5290 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5291 // vrev <4 x i8> -> REV16
5292 assert(VT.getVectorElementType() == MVT::i8);
5293 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5298 EVT EltTy = VT.getVectorElementType();
5300 if (EltTy == MVT::i8)
5301 Opcode = AArch64ISD::DUPLANE8;
5302 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5303 Opcode = AArch64ISD::DUPLANE16;
5304 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5305 Opcode = AArch64ISD::DUPLANE32;
5306 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5307 Opcode = AArch64ISD::DUPLANE64;
5309 llvm_unreachable("Invalid vector element type?");
5311 if (VT.getSizeInBits() == 64)
5312 OpLHS = WidenVector(OpLHS, DAG);
5313 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5314 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5319 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5320 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5321 DAG.getConstant(Imm, dl, MVT::i32));
5324 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5327 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5330 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5333 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5336 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5339 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5344 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5345 SelectionDAG &DAG) {
5346 // Check to see if we can use the TBL instruction.
5347 SDValue V1 = Op.getOperand(0);
5348 SDValue V2 = Op.getOperand(1);
5351 EVT EltVT = Op.getValueType().getVectorElementType();
5352 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5354 SmallVector<SDValue, 8> TBLMask;
5355 for (int Val : ShuffleMask) {
5356 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5357 unsigned Offset = Byte + Val * BytesPerElt;
5358 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5362 MVT IndexVT = MVT::v8i8;
5363 unsigned IndexLen = 8;
5364 if (Op.getValueType().getSizeInBits() == 128) {
5365 IndexVT = MVT::v16i8;
5369 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5370 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5373 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5375 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5376 Shuffle = DAG.getNode(
5377 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5378 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5379 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5380 makeArrayRef(TBLMask.data(), IndexLen)));
5382 if (IndexLen == 8) {
5383 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5384 Shuffle = DAG.getNode(
5385 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5386 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5387 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5388 makeArrayRef(TBLMask.data(), IndexLen)));
5390 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5391 // cannot currently represent the register constraints on the input
5393 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5394 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5395 // &TBLMask[0], IndexLen));
5396 Shuffle = DAG.getNode(
5397 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5398 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5400 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5401 makeArrayRef(TBLMask.data(), IndexLen)));
5404 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5407 static unsigned getDUPLANEOp(EVT EltType) {
5408 if (EltType == MVT::i8)
5409 return AArch64ISD::DUPLANE8;
5410 if (EltType == MVT::i16 || EltType == MVT::f16)
5411 return AArch64ISD::DUPLANE16;
5412 if (EltType == MVT::i32 || EltType == MVT::f32)
5413 return AArch64ISD::DUPLANE32;
5414 if (EltType == MVT::i64 || EltType == MVT::f64)
5415 return AArch64ISD::DUPLANE64;
5417 llvm_unreachable("Invalid vector element type?");
5420 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5421 SelectionDAG &DAG) const {
5423 EVT VT = Op.getValueType();
5425 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5427 // Convert shuffles that are directly supported on NEON to target-specific
5428 // DAG nodes, instead of keeping them as shuffles and matching them again
5429 // during code selection. This is more efficient and avoids the possibility
5430 // of inconsistencies between legalization and selection.
5431 ArrayRef<int> ShuffleMask = SVN->getMask();
5433 SDValue V1 = Op.getOperand(0);
5434 SDValue V2 = Op.getOperand(1);
5436 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5437 V1.getValueType().getSimpleVT())) {
5438 int Lane = SVN->getSplatIndex();
5439 // If this is undef splat, generate it via "just" vdup, if possible.
5443 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5444 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5446 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5447 // constant. If so, we can just reference the lane's definition directly.
5448 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5449 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5450 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5452 // Otherwise, duplicate from the lane of the input vector.
5453 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5455 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5456 // to make a vector of the same size as this SHUFFLE. We can ignore the
5457 // extract entirely, and canonicalise the concat using WidenVector.
5458 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5459 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5460 V1 = V1.getOperand(0);
5461 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5462 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5463 Lane -= Idx * VT.getVectorNumElements() / 2;
5464 V1 = WidenVector(V1.getOperand(Idx), DAG);
5465 } else if (VT.getSizeInBits() == 64)
5466 V1 = WidenVector(V1, DAG);
5468 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5471 if (isREVMask(ShuffleMask, VT, 64))
5472 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5473 if (isREVMask(ShuffleMask, VT, 32))
5474 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5475 if (isREVMask(ShuffleMask, VT, 16))
5476 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5478 bool ReverseEXT = false;
5480 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5483 Imm *= getExtFactor(V1);
5484 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5485 DAG.getConstant(Imm, dl, MVT::i32));
5486 } else if (V2->getOpcode() == ISD::UNDEF &&
5487 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5488 Imm *= getExtFactor(V1);
5489 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5490 DAG.getConstant(Imm, dl, MVT::i32));
5493 unsigned WhichResult;
5494 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5495 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5496 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5498 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5499 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5500 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5502 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5503 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5504 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5507 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5508 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5509 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5511 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5512 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5513 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5515 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5516 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5517 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5520 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5521 if (Concat.getNode())
5526 int NumInputElements = V1.getValueType().getVectorNumElements();
5527 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5528 SDValue DstVec = DstIsLeft ? V1 : V2;
5529 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5531 SDValue SrcVec = V1;
5532 int SrcLane = ShuffleMask[Anomaly];
5533 if (SrcLane >= NumInputElements) {
5535 SrcLane -= VT.getVectorNumElements();
5537 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5539 EVT ScalarVT = VT.getVectorElementType();
5541 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5542 ScalarVT = MVT::i32;
5545 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5546 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5550 // If the shuffle is not directly supported and it has 4 elements, use
5551 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5552 unsigned NumElts = VT.getVectorNumElements();
5554 unsigned PFIndexes[4];
5555 for (unsigned i = 0; i != 4; ++i) {
5556 if (ShuffleMask[i] < 0)
5559 PFIndexes[i] = ShuffleMask[i];
5562 // Compute the index in the perfect shuffle table.
5563 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5564 PFIndexes[2] * 9 + PFIndexes[3];
5565 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5566 unsigned Cost = (PFEntry >> 30);
5569 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5572 return GenerateTBL(Op, ShuffleMask, DAG);
5575 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5577 EVT VT = BVN->getValueType(0);
5578 APInt SplatBits, SplatUndef;
5579 unsigned SplatBitSize;
5581 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5582 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5584 for (unsigned i = 0; i < NumSplats; ++i) {
5585 CnstBits <<= SplatBitSize;
5586 UndefBits <<= SplatBitSize;
5587 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5588 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5597 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5598 SelectionDAG &DAG) const {
5599 BuildVectorSDNode *BVN =
5600 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5601 SDValue LHS = Op.getOperand(0);
5603 EVT VT = Op.getValueType();
5608 APInt CnstBits(VT.getSizeInBits(), 0);
5609 APInt UndefBits(VT.getSizeInBits(), 0);
5610 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5611 // We only have BIC vector immediate instruction, which is and-not.
5612 CnstBits = ~CnstBits;
5614 // We make use of a little bit of goto ickiness in order to avoid having to
5615 // duplicate the immediate matching logic for the undef toggled case.
5616 bool SecondTry = false;
5619 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5620 CnstBits = CnstBits.zextOrTrunc(64);
5621 uint64_t CnstVal = CnstBits.getZExtValue();
5623 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5624 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5625 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5626 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5627 DAG.getConstant(CnstVal, dl, MVT::i32),
5628 DAG.getConstant(0, dl, MVT::i32));
5629 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5632 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5633 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5634 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5635 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5636 DAG.getConstant(CnstVal, dl, MVT::i32),
5637 DAG.getConstant(8, dl, MVT::i32));
5638 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5641 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5642 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5643 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5644 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5645 DAG.getConstant(CnstVal, dl, MVT::i32),
5646 DAG.getConstant(16, dl, MVT::i32));
5647 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5650 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5651 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5652 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5653 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5654 DAG.getConstant(CnstVal, dl, MVT::i32),
5655 DAG.getConstant(24, dl, MVT::i32));
5656 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5659 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5660 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5661 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5662 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5663 DAG.getConstant(CnstVal, dl, MVT::i32),
5664 DAG.getConstant(0, dl, MVT::i32));
5665 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5668 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5669 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5670 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5671 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5672 DAG.getConstant(CnstVal, dl, MVT::i32),
5673 DAG.getConstant(8, dl, MVT::i32));
5674 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5681 CnstBits = ~UndefBits;
5685 // We can always fall back to a non-immediate AND.
5690 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5691 // consists of only the same constant int value, returned in reference arg
5693 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5694 uint64_t &ConstVal) {
5695 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5698 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5701 EVT VT = Bvec->getValueType(0);
5702 unsigned NumElts = VT.getVectorNumElements();
5703 for (unsigned i = 1; i < NumElts; ++i)
5704 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5706 ConstVal = FirstElt->getZExtValue();
5710 static unsigned getIntrinsicID(const SDNode *N) {
5711 unsigned Opcode = N->getOpcode();
5714 return Intrinsic::not_intrinsic;
5715 case ISD::INTRINSIC_WO_CHAIN: {
5716 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5717 if (IID < Intrinsic::num_intrinsics)
5719 return Intrinsic::not_intrinsic;
5724 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5725 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5726 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5727 // Also, logical shift right -> sri, with the same structure.
5728 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5729 EVT VT = N->getValueType(0);
5736 // Is the first op an AND?
5737 const SDValue And = N->getOperand(0);
5738 if (And.getOpcode() != ISD::AND)
5741 // Is the second op an shl or lshr?
5742 SDValue Shift = N->getOperand(1);
5743 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5744 // or AArch64ISD::VLSHR vector, #shift
5745 unsigned ShiftOpc = Shift.getOpcode();
5746 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5748 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5750 // Is the shift amount constant?
5751 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5755 // Is the and mask vector all constant?
5757 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5760 // Is C1 == ~C2, taking into account how much one can shift elements of a
5762 uint64_t C2 = C2node->getZExtValue();
5763 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5764 if (C2 > ElemSizeInBits)
5766 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5767 if ((C1 & ElemMask) != (~C2 & ElemMask))
5770 SDValue X = And.getOperand(0);
5771 SDValue Y = Shift.getOperand(0);
5774 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5776 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5777 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5778 Shift.getOperand(1));
5780 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5781 DEBUG(N->dump(&DAG));
5782 DEBUG(dbgs() << "into: \n");
5783 DEBUG(ResultSLI->dump(&DAG));
5789 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5790 SelectionDAG &DAG) const {
5791 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5792 if (EnableAArch64SlrGeneration) {
5793 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5798 BuildVectorSDNode *BVN =
5799 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5800 SDValue LHS = Op.getOperand(1);
5802 EVT VT = Op.getValueType();
5804 // OR commutes, so try swapping the operands.
5806 LHS = Op.getOperand(0);
5807 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5812 APInt CnstBits(VT.getSizeInBits(), 0);
5813 APInt UndefBits(VT.getSizeInBits(), 0);
5814 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5815 // We make use of a little bit of goto ickiness in order to avoid having to
5816 // duplicate the immediate matching logic for the undef toggled case.
5817 bool SecondTry = false;
5820 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5821 CnstBits = CnstBits.zextOrTrunc(64);
5822 uint64_t CnstVal = CnstBits.getZExtValue();
5824 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5825 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5826 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5827 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5828 DAG.getConstant(CnstVal, dl, MVT::i32),
5829 DAG.getConstant(0, dl, MVT::i32));
5830 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5833 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5834 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5835 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5836 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5837 DAG.getConstant(CnstVal, dl, MVT::i32),
5838 DAG.getConstant(8, dl, MVT::i32));
5839 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5842 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5843 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5844 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5845 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5846 DAG.getConstant(CnstVal, dl, MVT::i32),
5847 DAG.getConstant(16, dl, MVT::i32));
5848 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5851 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5852 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5853 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5854 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5855 DAG.getConstant(CnstVal, dl, MVT::i32),
5856 DAG.getConstant(24, dl, MVT::i32));
5857 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5860 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5861 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5862 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5863 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5864 DAG.getConstant(CnstVal, dl, MVT::i32),
5865 DAG.getConstant(0, dl, MVT::i32));
5866 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5869 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5870 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5871 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5872 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5873 DAG.getConstant(CnstVal, dl, MVT::i32),
5874 DAG.getConstant(8, dl, MVT::i32));
5875 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5882 CnstBits = UndefBits;
5886 // We can always fall back to a non-immediate OR.
5891 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5892 // be truncated to fit element width.
5893 static SDValue NormalizeBuildVector(SDValue Op,
5894 SelectionDAG &DAG) {
5895 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5897 EVT VT = Op.getValueType();
5898 EVT EltTy= VT.getVectorElementType();
5900 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5903 SmallVector<SDValue, 16> Ops;
5904 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5905 SDValue Lane = Op.getOperand(I);
5906 if (Lane.getOpcode() == ISD::Constant) {
5907 APInt LowBits(EltTy.getSizeInBits(),
5908 cast<ConstantSDNode>(Lane)->getZExtValue());
5909 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5911 Ops.push_back(Lane);
5913 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5916 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5917 SelectionDAG &DAG) const {
5919 EVT VT = Op.getValueType();
5920 Op = NormalizeBuildVector(Op, DAG);
5921 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5923 APInt CnstBits(VT.getSizeInBits(), 0);
5924 APInt UndefBits(VT.getSizeInBits(), 0);
5925 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5926 // We make use of a little bit of goto ickiness in order to avoid having to
5927 // duplicate the immediate matching logic for the undef toggled case.
5928 bool SecondTry = false;
5931 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5932 CnstBits = CnstBits.zextOrTrunc(64);
5933 uint64_t CnstVal = CnstBits.getZExtValue();
5935 // Certain magic vector constants (used to express things like NOT
5936 // and NEG) are passed through unmodified. This allows codegen patterns
5937 // for these operations to match. Special-purpose patterns will lower
5938 // these immediates to MOVIs if it proves necessary.
5939 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5942 // The many faces of MOVI...
5943 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5944 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5945 if (VT.getSizeInBits() == 128) {
5946 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5947 DAG.getConstant(CnstVal, dl, MVT::i32));
5948 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5951 // Support the V64 version via subregister insertion.
5952 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5953 DAG.getConstant(CnstVal, dl, MVT::i32));
5954 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5957 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5958 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5959 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5960 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5961 DAG.getConstant(CnstVal, dl, MVT::i32),
5962 DAG.getConstant(0, dl, MVT::i32));
5963 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5966 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5967 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5968 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5969 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5970 DAG.getConstant(CnstVal, dl, MVT::i32),
5971 DAG.getConstant(8, dl, MVT::i32));
5972 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5975 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5976 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5977 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5978 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5979 DAG.getConstant(CnstVal, dl, MVT::i32),
5980 DAG.getConstant(16, dl, MVT::i32));
5981 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5984 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5985 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5986 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5987 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5988 DAG.getConstant(CnstVal, dl, MVT::i32),
5989 DAG.getConstant(24, dl, MVT::i32));
5990 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5993 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5994 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5995 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5996 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5997 DAG.getConstant(CnstVal, dl, MVT::i32),
5998 DAG.getConstant(0, dl, MVT::i32));
5999 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6002 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6003 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6004 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6005 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6006 DAG.getConstant(CnstVal, dl, MVT::i32),
6007 DAG.getConstant(8, dl, MVT::i32));
6008 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6011 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6012 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6013 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6014 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6015 DAG.getConstant(CnstVal, dl, MVT::i32),
6016 DAG.getConstant(264, dl, MVT::i32));
6017 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6020 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6021 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6022 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6023 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6024 DAG.getConstant(CnstVal, dl, MVT::i32),
6025 DAG.getConstant(272, dl, MVT::i32));
6026 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6029 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
6030 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
6031 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6032 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
6033 DAG.getConstant(CnstVal, dl, MVT::i32));
6034 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6037 // The few faces of FMOV...
6038 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
6039 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
6040 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6041 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
6042 DAG.getConstant(CnstVal, dl, MVT::i32));
6043 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6046 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
6047 VT.getSizeInBits() == 128) {
6048 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
6049 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
6050 DAG.getConstant(CnstVal, dl, MVT::i32));
6051 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6054 // The many faces of MVNI...
6056 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6057 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6058 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6059 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6060 DAG.getConstant(CnstVal, dl, MVT::i32),
6061 DAG.getConstant(0, dl, MVT::i32));
6062 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6065 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6066 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6067 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6068 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6069 DAG.getConstant(CnstVal, dl, MVT::i32),
6070 DAG.getConstant(8, dl, MVT::i32));
6071 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6074 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6075 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6076 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6077 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6078 DAG.getConstant(CnstVal, dl, MVT::i32),
6079 DAG.getConstant(16, dl, MVT::i32));
6080 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6083 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6084 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6085 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6086 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6087 DAG.getConstant(CnstVal, dl, MVT::i32),
6088 DAG.getConstant(24, dl, MVT::i32));
6089 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6092 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6093 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6094 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6095 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6096 DAG.getConstant(CnstVal, dl, MVT::i32),
6097 DAG.getConstant(0, dl, MVT::i32));
6098 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6101 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6102 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6103 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6104 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6105 DAG.getConstant(CnstVal, dl, MVT::i32),
6106 DAG.getConstant(8, dl, MVT::i32));
6107 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6110 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6111 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6112 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6113 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6114 DAG.getConstant(CnstVal, dl, MVT::i32),
6115 DAG.getConstant(264, dl, MVT::i32));
6116 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6119 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6120 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6121 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6122 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6123 DAG.getConstant(CnstVal, dl, MVT::i32),
6124 DAG.getConstant(272, dl, MVT::i32));
6125 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6132 CnstBits = UndefBits;
6137 // Scan through the operands to find some interesting properties we can
6139 // 1) If only one value is used, we can use a DUP, or
6140 // 2) if only the low element is not undef, we can just insert that, or
6141 // 3) if only one constant value is used (w/ some non-constant lanes),
6142 // we can splat the constant value into the whole vector then fill
6143 // in the non-constant lanes.
6144 // 4) FIXME: If different constant values are used, but we can intelligently
6145 // select the values we'll be overwriting for the non-constant
6146 // lanes such that we can directly materialize the vector
6147 // some other way (MOVI, e.g.), we can be sneaky.
6148 unsigned NumElts = VT.getVectorNumElements();
6149 bool isOnlyLowElement = true;
6150 bool usesOnlyOneValue = true;
6151 bool usesOnlyOneConstantValue = true;
6152 bool isConstant = true;
6153 unsigned NumConstantLanes = 0;
6155 SDValue ConstantValue;
6156 for (unsigned i = 0; i < NumElts; ++i) {
6157 SDValue V = Op.getOperand(i);
6158 if (V.getOpcode() == ISD::UNDEF)
6161 isOnlyLowElement = false;
6162 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6165 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
6167 if (!ConstantValue.getNode())
6169 else if (ConstantValue != V)
6170 usesOnlyOneConstantValue = false;
6173 if (!Value.getNode())
6175 else if (V != Value)
6176 usesOnlyOneValue = false;
6179 if (!Value.getNode())
6180 return DAG.getUNDEF(VT);
6182 if (isOnlyLowElement)
6183 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6185 // Use DUP for non-constant splats. For f32 constant splats, reduce to
6186 // i32 and try again.
6187 if (usesOnlyOneValue) {
6189 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6190 Value.getValueType() != VT)
6191 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6193 // This is actually a DUPLANExx operation, which keeps everything vectory.
6195 // DUPLANE works on 128-bit vectors, widen it if necessary.
6196 SDValue Lane = Value.getOperand(1);
6197 Value = Value.getOperand(0);
6198 if (Value.getValueType().getSizeInBits() == 64)
6199 Value = WidenVector(Value, DAG);
6201 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6202 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6205 if (VT.getVectorElementType().isFloatingPoint()) {
6206 SmallVector<SDValue, 8> Ops;
6207 EVT EltTy = VT.getVectorElementType();
6208 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
6209 "Unsupported floating-point vector type");
6210 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
6211 for (unsigned i = 0; i < NumElts; ++i)
6212 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
6213 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
6214 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
6215 Val = LowerBUILD_VECTOR(Val, DAG);
6217 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6221 // If there was only one constant value used and for more than one lane,
6222 // start by splatting that value, then replace the non-constant lanes. This
6223 // is better than the default, which will perform a separate initialization
6225 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6226 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6227 // Now insert the non-constant lanes.
6228 for (unsigned i = 0; i < NumElts; ++i) {
6229 SDValue V = Op.getOperand(i);
6230 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6231 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6232 // Note that type legalization likely mucked about with the VT of the
6233 // source operand, so we may have to convert it here before inserting.
6234 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6240 // If all elements are constants and the case above didn't get hit, fall back
6241 // to the default expansion, which will generate a load from the constant
6246 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6248 SDValue shuffle = ReconstructShuffle(Op, DAG);
6249 if (shuffle != SDValue())
6253 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6254 // know the default expansion would otherwise fall back on something even
6255 // worse. For a vector with one or two non-undef values, that's
6256 // scalar_to_vector for the elements followed by a shuffle (provided the
6257 // shuffle is valid for the target) and materialization element by element
6258 // on the stack followed by a load for everything else.
6259 if (!isConstant && !usesOnlyOneValue) {
6260 SDValue Vec = DAG.getUNDEF(VT);
6261 SDValue Op0 = Op.getOperand(0);
6262 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6264 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6265 // a) Avoid a RMW dependency on the full vector register, and
6266 // b) Allow the register coalescer to fold away the copy if the
6267 // value is already in an S or D register.
6268 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6269 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6271 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6272 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6273 Vec = SDValue(N, 0);
6276 for (; i < NumElts; ++i) {
6277 SDValue V = Op.getOperand(i);
6278 if (V.getOpcode() == ISD::UNDEF)
6280 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6281 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6286 // Just use the default expansion. We failed to find a better alternative.
6290 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6291 SelectionDAG &DAG) const {
6292 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6294 // Check for non-constant or out of range lane.
6295 EVT VT = Op.getOperand(0).getValueType();
6296 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6297 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6301 // Insertion/extraction are legal for V128 types.
6302 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6303 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6307 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6308 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6311 // For V64 types, we perform insertion by expanding the value
6312 // to a V128 type and perform the insertion on that.
6314 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6315 EVT WideTy = WideVec.getValueType();
6317 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6318 Op.getOperand(1), Op.getOperand(2));
6319 // Re-narrow the resultant vector.
6320 return NarrowVector(Node, DAG);
6324 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6325 SelectionDAG &DAG) const {
6326 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6328 // Check for non-constant or out of range lane.
6329 EVT VT = Op.getOperand(0).getValueType();
6330 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6331 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6335 // Insertion/extraction are legal for V128 types.
6336 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6337 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6341 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6342 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6345 // For V64 types, we perform extraction by expanding the value
6346 // to a V128 type and perform the extraction on that.
6348 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6349 EVT WideTy = WideVec.getValueType();
6351 EVT ExtrTy = WideTy.getVectorElementType();
6352 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6355 // For extractions, we just return the result directly.
6356 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6360 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6361 SelectionDAG &DAG) const {
6362 EVT VT = Op.getOperand(0).getValueType();
6368 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6371 unsigned Val = Cst->getZExtValue();
6373 unsigned Size = Op.getValueType().getSizeInBits();
6377 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6380 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6383 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6386 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6389 llvm_unreachable("Unexpected vector type in extract_subvector!");
6392 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6394 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6400 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6402 if (VT.getVectorNumElements() == 4 &&
6403 (VT.is128BitVector() || VT.is64BitVector())) {
6404 unsigned PFIndexes[4];
6405 for (unsigned i = 0; i != 4; ++i) {
6409 PFIndexes[i] = M[i];
6412 // Compute the index in the perfect shuffle table.
6413 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6414 PFIndexes[2] * 9 + PFIndexes[3];
6415 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6416 unsigned Cost = (PFEntry >> 30);
6424 unsigned DummyUnsigned;
6426 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6427 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6428 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6429 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6430 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6431 isZIPMask(M, VT, DummyUnsigned) ||
6432 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6433 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6434 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6435 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6436 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6439 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6440 /// operand of a vector shift operation, where all the elements of the
6441 /// build_vector must have the same constant integer value.
6442 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6443 // Ignore bit_converts.
6444 while (Op.getOpcode() == ISD::BITCAST)
6445 Op = Op.getOperand(0);
6446 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6447 APInt SplatBits, SplatUndef;
6448 unsigned SplatBitSize;
6450 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6451 HasAnyUndefs, ElementBits) ||
6452 SplatBitSize > ElementBits)
6454 Cnt = SplatBits.getSExtValue();
6458 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6459 /// operand of a vector shift left operation. That value must be in the range:
6460 /// 0 <= Value < ElementBits for a left shift; or
6461 /// 0 <= Value <= ElementBits for a long left shift.
6462 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6463 assert(VT.isVector() && "vector shift count is not a vector type");
6464 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6465 if (!getVShiftImm(Op, ElementBits, Cnt))
6467 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6470 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6471 /// operand of a vector shift right operation. The value must be in the range:
6472 /// 1 <= Value <= ElementBits for a right shift; or
6473 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6474 assert(VT.isVector() && "vector shift count is not a vector type");
6475 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6476 if (!getVShiftImm(Op, ElementBits, Cnt))
6478 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6481 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6482 SelectionDAG &DAG) const {
6483 EVT VT = Op.getValueType();
6487 if (!Op.getOperand(1).getValueType().isVector())
6489 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6491 switch (Op.getOpcode()) {
6493 llvm_unreachable("unexpected shift opcode");
6496 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6497 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6498 DAG.getConstant(Cnt, DL, MVT::i32));
6499 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6500 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6502 Op.getOperand(0), Op.getOperand(1));
6505 // Right shift immediate
6506 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6508 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6509 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6510 DAG.getConstant(Cnt, DL, MVT::i32));
6513 // Right shift register. Note, there is not a shift right register
6514 // instruction, but the shift left register instruction takes a signed
6515 // value, where negative numbers specify a right shift.
6516 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6517 : Intrinsic::aarch64_neon_ushl;
6518 // negate the shift amount
6519 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6520 SDValue NegShiftLeft =
6521 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6522 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6524 return NegShiftLeft;
6530 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6531 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6532 SDLoc dl, SelectionDAG &DAG) {
6533 EVT SrcVT = LHS.getValueType();
6534 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6535 "function only supposed to emit natural comparisons");
6537 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6538 APInt CnstBits(VT.getSizeInBits(), 0);
6539 APInt UndefBits(VT.getSizeInBits(), 0);
6540 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6541 bool IsZero = IsCnst && (CnstBits == 0);
6543 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6547 case AArch64CC::NE: {
6550 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6552 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6553 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6557 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6558 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6561 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6562 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6565 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6566 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6569 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6570 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6574 // If we ignore NaNs then we can use to the MI implementation.
6578 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6579 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6586 case AArch64CC::NE: {
6589 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6591 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6592 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6596 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6597 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6600 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6601 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6604 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6605 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6608 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6609 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6611 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6613 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6616 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6617 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6619 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6621 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6625 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6626 SelectionDAG &DAG) const {
6627 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6628 SDValue LHS = Op.getOperand(0);
6629 SDValue RHS = Op.getOperand(1);
6630 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6633 if (LHS.getValueType().getVectorElementType().isInteger()) {
6634 assert(LHS.getValueType() == RHS.getValueType());
6635 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6637 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6638 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6641 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6642 LHS.getValueType().getVectorElementType() == MVT::f64);
6644 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6645 // clean. Some of them require two branches to implement.
6646 AArch64CC::CondCode CC1, CC2;
6648 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6650 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6652 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6656 if (CC2 != AArch64CC::AL) {
6658 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6659 if (!Cmp2.getNode())
6662 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6665 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6668 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6673 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6674 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6675 /// specified in the intrinsic calls.
6676 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6678 unsigned Intrinsic) const {
6679 auto &DL = I.getModule()->getDataLayout();
6680 switch (Intrinsic) {
6681 case Intrinsic::aarch64_neon_ld2:
6682 case Intrinsic::aarch64_neon_ld3:
6683 case Intrinsic::aarch64_neon_ld4:
6684 case Intrinsic::aarch64_neon_ld1x2:
6685 case Intrinsic::aarch64_neon_ld1x3:
6686 case Intrinsic::aarch64_neon_ld1x4:
6687 case Intrinsic::aarch64_neon_ld2lane:
6688 case Intrinsic::aarch64_neon_ld3lane:
6689 case Intrinsic::aarch64_neon_ld4lane:
6690 case Intrinsic::aarch64_neon_ld2r:
6691 case Intrinsic::aarch64_neon_ld3r:
6692 case Intrinsic::aarch64_neon_ld4r: {
6693 Info.opc = ISD::INTRINSIC_W_CHAIN;
6694 // Conservatively set memVT to the entire set of vectors loaded.
6695 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
6696 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6697 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6700 Info.vol = false; // volatile loads with NEON intrinsics not supported
6701 Info.readMem = true;
6702 Info.writeMem = false;
6705 case Intrinsic::aarch64_neon_st2:
6706 case Intrinsic::aarch64_neon_st3:
6707 case Intrinsic::aarch64_neon_st4:
6708 case Intrinsic::aarch64_neon_st1x2:
6709 case Intrinsic::aarch64_neon_st1x3:
6710 case Intrinsic::aarch64_neon_st1x4:
6711 case Intrinsic::aarch64_neon_st2lane:
6712 case Intrinsic::aarch64_neon_st3lane:
6713 case Intrinsic::aarch64_neon_st4lane: {
6714 Info.opc = ISD::INTRINSIC_VOID;
6715 // Conservatively set memVT to the entire set of vectors stored.
6716 unsigned NumElts = 0;
6717 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6718 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6719 if (!ArgTy->isVectorTy())
6721 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
6723 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6724 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6727 Info.vol = false; // volatile stores with NEON intrinsics not supported
6728 Info.readMem = false;
6729 Info.writeMem = true;
6732 case Intrinsic::aarch64_ldaxr:
6733 case Intrinsic::aarch64_ldxr: {
6734 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6735 Info.opc = ISD::INTRINSIC_W_CHAIN;
6736 Info.memVT = MVT::getVT(PtrTy->getElementType());
6737 Info.ptrVal = I.getArgOperand(0);
6739 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6741 Info.readMem = true;
6742 Info.writeMem = false;
6745 case Intrinsic::aarch64_stlxr:
6746 case Intrinsic::aarch64_stxr: {
6747 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6748 Info.opc = ISD::INTRINSIC_W_CHAIN;
6749 Info.memVT = MVT::getVT(PtrTy->getElementType());
6750 Info.ptrVal = I.getArgOperand(1);
6752 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
6754 Info.readMem = false;
6755 Info.writeMem = true;
6758 case Intrinsic::aarch64_ldaxp:
6759 case Intrinsic::aarch64_ldxp: {
6760 Info.opc = ISD::INTRINSIC_W_CHAIN;
6761 Info.memVT = MVT::i128;
6762 Info.ptrVal = I.getArgOperand(0);
6766 Info.readMem = true;
6767 Info.writeMem = false;
6770 case Intrinsic::aarch64_stlxp:
6771 case Intrinsic::aarch64_stxp: {
6772 Info.opc = ISD::INTRINSIC_W_CHAIN;
6773 Info.memVT = MVT::i128;
6774 Info.ptrVal = I.getArgOperand(2);
6778 Info.readMem = false;
6779 Info.writeMem = true;
6789 // Truncations from 64-bit GPR to 32-bit GPR is free.
6790 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6791 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6793 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6794 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6795 return NumBits1 > NumBits2;
6797 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6798 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6800 unsigned NumBits1 = VT1.getSizeInBits();
6801 unsigned NumBits2 = VT2.getSizeInBits();
6802 return NumBits1 > NumBits2;
6805 /// Check if it is profitable to hoist instruction in then/else to if.
6806 /// Not profitable if I and it's user can form a FMA instruction
6807 /// because we prefer FMSUB/FMADD.
6808 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6809 if (I->getOpcode() != Instruction::FMul)
6812 if (I->getNumUses() != 1)
6815 Instruction *User = I->user_back();
6818 !(User->getOpcode() == Instruction::FSub ||
6819 User->getOpcode() == Instruction::FAdd))
6822 const TargetOptions &Options = getTargetMachine().Options;
6823 const DataLayout &DL = I->getModule()->getDataLayout();
6824 EVT VT = getValueType(DL, User->getOperand(0)->getType());
6826 if (isFMAFasterThanFMulAndFAdd(VT) &&
6827 isOperationLegalOrCustom(ISD::FMA, VT) &&
6828 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6834 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6836 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6837 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6839 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6840 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6841 return NumBits1 == 32 && NumBits2 == 64;
6843 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6844 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6846 unsigned NumBits1 = VT1.getSizeInBits();
6847 unsigned NumBits2 = VT2.getSizeInBits();
6848 return NumBits1 == 32 && NumBits2 == 64;
6851 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6852 EVT VT1 = Val.getValueType();
6853 if (isZExtFree(VT1, VT2)) {
6857 if (Val.getOpcode() != ISD::LOAD)
6860 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6861 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6862 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6863 VT1.getSizeInBits() <= 32);
6866 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6867 if (isa<FPExtInst>(Ext))
6870 // Vector types are next free.
6871 if (Ext->getType()->isVectorTy())
6874 for (const Use &U : Ext->uses()) {
6875 // The extension is free if we can fold it with a left shift in an
6876 // addressing mode or an arithmetic operation: add, sub, and cmp.
6878 // Is there a shift?
6879 const Instruction *Instr = cast<Instruction>(U.getUser());
6881 // Is this a constant shift?
6882 switch (Instr->getOpcode()) {
6883 case Instruction::Shl:
6884 if (!isa<ConstantInt>(Instr->getOperand(1)))
6887 case Instruction::GetElementPtr: {
6888 gep_type_iterator GTI = gep_type_begin(Instr);
6889 auto &DL = Ext->getModule()->getDataLayout();
6890 std::advance(GTI, U.getOperandNo());
6892 // This extension will end up with a shift because of the scaling factor.
6893 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6894 // Get the shift amount based on the scaling factor:
6895 // log2(sizeof(IdxTy)) - log2(8).
6897 countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy)) - 3;
6898 // Is the constant foldable in the shift of the addressing mode?
6899 // I.e., shift amount is between 1 and 4 inclusive.
6900 if (ShiftAmt == 0 || ShiftAmt > 4)
6904 case Instruction::Trunc:
6905 // Check if this is a noop.
6906 // trunc(sext ty1 to ty2) to ty1.
6907 if (Instr->getType() == Ext->getOperand(0)->getType())
6914 // At this point we can use the bfm family, so this extension is free
6920 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6921 unsigned &RequiredAligment) const {
6922 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6924 // Cyclone supports unaligned accesses.
6925 RequiredAligment = 0;
6926 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6927 return NumBits == 32 || NumBits == 64;
6930 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6931 unsigned &RequiredAligment) const {
6932 if (!LoadedType.isSimple() ||
6933 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6935 // Cyclone supports unaligned accesses.
6936 RequiredAligment = 0;
6937 unsigned NumBits = LoadedType.getSizeInBits();
6938 return NumBits == 32 || NumBits == 64;
6941 /// \brief Lower an interleaved load into a ldN intrinsic.
6943 /// E.g. Lower an interleaved load (Factor = 2):
6944 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
6945 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
6946 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
6949 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
6950 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
6951 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
6952 bool AArch64TargetLowering::lowerInterleavedLoad(
6953 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
6954 ArrayRef<unsigned> Indices, unsigned Factor) const {
6955 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
6956 "Invalid interleave factor");
6957 assert(!Shuffles.empty() && "Empty shufflevector input");
6958 assert(Shuffles.size() == Indices.size() &&
6959 "Unmatched number of shufflevectors and indices");
6961 const DataLayout &DL = LI->getModule()->getDataLayout();
6963 VectorType *VecTy = Shuffles[0]->getType();
6964 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
6966 // Skip illegal vector types.
6967 if (VecSize != 64 && VecSize != 128)
6970 // A pointer vector can not be the return type of the ldN intrinsics. Need to
6971 // load integer vectors first and then convert to pointer vectors.
6972 Type *EltTy = VecTy->getVectorElementType();
6973 if (EltTy->isPointerTy())
6975 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
6977 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
6978 Type *Tys[2] = {VecTy, PtrTy};
6979 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
6980 Intrinsic::aarch64_neon_ld3,
6981 Intrinsic::aarch64_neon_ld4};
6983 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
6985 IRBuilder<> Builder(LI);
6986 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
6988 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
6990 // Replace uses of each shufflevector with the corresponding vector loaded
6992 for (unsigned i = 0; i < Shuffles.size(); i++) {
6993 ShuffleVectorInst *SVI = Shuffles[i];
6994 unsigned Index = Indices[i];
6996 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
6998 // Convert the integer vector to pointer vector if the element is pointer.
6999 if (EltTy->isPointerTy())
7000 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
7002 SVI->replaceAllUsesWith(SubVec);
7008 /// \brief Get a mask consisting of sequential integers starting from \p Start.
7010 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
7011 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
7013 SmallVector<Constant *, 16> Mask;
7014 for (unsigned i = 0; i < NumElts; i++)
7015 Mask.push_back(Builder.getInt32(Start + i));
7017 return ConstantVector::get(Mask);
7020 /// \brief Lower an interleaved store into a stN intrinsic.
7022 /// E.g. Lower an interleaved store (Factor = 3):
7023 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7024 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
7025 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7028 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7029 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7030 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7031 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7033 /// Note that the new shufflevectors will be removed and we'll only generate one
7034 /// st3 instruction in CodeGen.
7035 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7036 ShuffleVectorInst *SVI,
7037 unsigned Factor) const {
7038 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7039 "Invalid interleave factor");
7041 VectorType *VecTy = SVI->getType();
7042 assert(VecTy->getVectorNumElements() % Factor == 0 &&
7043 "Invalid interleaved store");
7045 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
7046 Type *EltTy = VecTy->getVectorElementType();
7047 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
7049 const DataLayout &DL = SI->getModule()->getDataLayout();
7050 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
7052 // Skip illegal vector types.
7053 if (SubVecSize != 64 && SubVecSize != 128)
7056 Value *Op0 = SVI->getOperand(0);
7057 Value *Op1 = SVI->getOperand(1);
7058 IRBuilder<> Builder(SI);
7060 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
7061 // vectors to integer vectors.
7062 if (EltTy->isPointerTy()) {
7063 Type *IntTy = DL.getIntPtrType(EltTy);
7064 unsigned NumOpElts =
7065 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
7067 // Convert to the corresponding integer vector.
7068 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
7069 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
7070 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
7072 SubVecTy = VectorType::get(IntTy, NumSubElts);
7075 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
7076 Type *Tys[2] = {SubVecTy, PtrTy};
7077 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
7078 Intrinsic::aarch64_neon_st3,
7079 Intrinsic::aarch64_neon_st4};
7081 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
7083 SmallVector<Value *, 5> Ops;
7085 // Split the shufflevector operands into sub vectors for the new stN call.
7086 for (unsigned i = 0; i < Factor; i++)
7087 Ops.push_back(Builder.CreateShuffleVector(
7088 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
7090 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
7091 Builder.CreateCall(StNFunc, Ops);
7095 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
7096 unsigned AlignCheck) {
7097 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
7098 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7101 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7102 unsigned SrcAlign, bool IsMemset,
7105 MachineFunction &MF) const {
7106 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
7107 // instruction to materialize the v2i64 zero and one store (with restrictive
7108 // addressing mode). Just do two i64 store of zero-registers.
7110 const Function *F = MF.getFunction();
7111 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
7112 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
7113 (memOpAlign(SrcAlign, DstAlign, 16) ||
7114 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
7118 (memOpAlign(SrcAlign, DstAlign, 8) ||
7119 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
7123 (memOpAlign(SrcAlign, DstAlign, 4) ||
7124 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
7130 // 12-bit optionally shifted immediates are legal for adds.
7131 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7132 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
7137 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
7138 // immediates is the same as for an add or a sub.
7139 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7142 return isLegalAddImmediate(Immed);
7145 /// isLegalAddressingMode - Return true if the addressing mode represented
7146 /// by AM is legal for this target, for a load/store of the specified type.
7147 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7148 const AddrMode &AM, Type *Ty,
7149 unsigned AS) const {
7150 // AArch64 has five basic addressing modes:
7152 // reg + 9-bit signed offset
7153 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
7155 // reg + SIZE_IN_BYTES * reg
7157 // No global is ever allowed as a base.
7161 // No reg+reg+imm addressing.
7162 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
7165 // check reg + imm case:
7166 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
7167 uint64_t NumBytes = 0;
7168 if (Ty->isSized()) {
7169 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
7170 NumBytes = NumBits / 8;
7171 if (!isPowerOf2_64(NumBits))
7176 int64_t Offset = AM.BaseOffs;
7178 // 9-bit signed offset
7179 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
7182 // 12-bit unsigned offset
7183 unsigned shift = Log2_64(NumBytes);
7184 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
7185 // Must be a multiple of NumBytes (NumBytes is a power of 2)
7186 (Offset >> shift) << shift == Offset)
7191 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
7193 if (!AM.Scale || AM.Scale == 1 ||
7194 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
7199 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7200 const AddrMode &AM, Type *Ty,
7201 unsigned AS) const {
7202 // Scaling factors are not free at all.
7203 // Operands | Rt Latency
7204 // -------------------------------------------
7206 // -------------------------------------------
7207 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
7208 // Rt, [Xn, Wm, <extend> #imm] |
7209 if (isLegalAddressingMode(DL, AM, Ty, AS))
7210 // Scale represents reg2 * scale, thus account for 1 if
7211 // it is not equal to 0 or 1.
7212 return AM.Scale != 0 && AM.Scale != 1;
7216 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7217 VT = VT.getScalarType();
7222 switch (VT.getSimpleVT().SimpleTy) {
7234 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7235 // LR is a callee-save register, but we must treat it as clobbered by any call
7236 // site. Hence we include LR in the scratch registers, which are in turn added
7237 // as implicit-defs for stackmaps and patchpoints.
7238 static const MCPhysReg ScratchRegs[] = {
7239 AArch64::X16, AArch64::X17, AArch64::LR, 0
7245 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7246 EVT VT = N->getValueType(0);
7247 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
7248 // it with shift to let it be lowered to UBFX.
7249 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7250 isa<ConstantSDNode>(N->getOperand(1))) {
7251 uint64_t TruncMask = N->getConstantOperandVal(1);
7252 if (isMask_64(TruncMask) &&
7253 N->getOperand(0).getOpcode() == ISD::SRL &&
7254 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7260 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7262 assert(Ty->isIntegerTy());
7264 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7268 int64_t Val = Imm.getSExtValue();
7269 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7272 if ((int64_t)Val < 0)
7275 Val &= (1LL << 32) - 1;
7277 unsigned LZ = countLeadingZeros((uint64_t)Val);
7278 unsigned Shift = (63 - LZ) / 16;
7279 // MOVZ is free so return true for one or fewer MOVK.
7283 // Generate SUBS and CSEL for integer abs.
7284 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7285 EVT VT = N->getValueType(0);
7287 SDValue N0 = N->getOperand(0);
7288 SDValue N1 = N->getOperand(1);
7291 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7292 // and change it to SUB and CSEL.
7293 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7294 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7295 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7296 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7297 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7298 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7300 // Generate SUBS & CSEL.
7302 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7303 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7304 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7305 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7306 SDValue(Cmp.getNode(), 1));
7311 // performXorCombine - Attempts to handle integer ABS.
7312 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7313 TargetLowering::DAGCombinerInfo &DCI,
7314 const AArch64Subtarget *Subtarget) {
7315 if (DCI.isBeforeLegalizeOps())
7318 return performIntegerAbsCombine(N, DAG);
7322 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7324 std::vector<SDNode *> *Created) const {
7325 // fold (sdiv X, pow2)
7326 EVT VT = N->getValueType(0);
7327 if ((VT != MVT::i32 && VT != MVT::i64) ||
7328 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7332 SDValue N0 = N->getOperand(0);
7333 unsigned Lg2 = Divisor.countTrailingZeros();
7334 SDValue Zero = DAG.getConstant(0, DL, VT);
7335 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7337 // Add (N0 < 0) ? Pow2 - 1 : 0;
7339 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7340 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7341 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7344 Created->push_back(Cmp.getNode());
7345 Created->push_back(Add.getNode());
7346 Created->push_back(CSel.getNode());
7351 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7353 // If we're dividing by a positive value, we're done. Otherwise, we must
7354 // negate the result.
7355 if (Divisor.isNonNegative())
7359 Created->push_back(SRA.getNode());
7360 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7363 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7364 TargetLowering::DAGCombinerInfo &DCI,
7365 const AArch64Subtarget *Subtarget) {
7366 if (DCI.isBeforeLegalizeOps())
7369 // Multiplication of a power of two plus/minus one can be done more
7370 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7371 // future CPUs have a cheaper MADD instruction, this may need to be
7372 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7373 // 64-bit is 5 cycles, so this is always a win.
7374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
7375 APInt Value = C->getAPIntValue();
7376 EVT VT = N->getValueType(0);
7378 if (Value.isNonNegative()) {
7379 // (mul x, 2^N + 1) => (add (shl x, N), x)
7380 APInt VM1 = Value - 1;
7381 if (VM1.isPowerOf2()) {
7382 SDValue ShiftedVal =
7383 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7384 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
7385 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7388 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7389 APInt VP1 = Value + 1;
7390 if (VP1.isPowerOf2()) {
7391 SDValue ShiftedVal =
7392 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7393 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
7394 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7398 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7399 APInt VNP1 = -Value + 1;
7400 if (VNP1.isPowerOf2()) {
7401 SDValue ShiftedVal =
7402 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7403 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
7404 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7407 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7408 APInt VNM1 = -Value - 1;
7409 if (VNM1.isPowerOf2()) {
7410 SDValue ShiftedVal =
7411 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7412 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7414 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7415 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7422 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7423 SelectionDAG &DAG) {
7424 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7425 // optimize away operation when it's from a constant.
7427 // The general transformation is:
7428 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7429 // AND(VECTOR_CMP(x,y), constant2)
7430 // constant2 = UNARYOP(constant)
7432 // Early exit if this isn't a vector operation, the operand of the
7433 // unary operation isn't a bitwise AND, or if the sizes of the operations
7435 EVT VT = N->getValueType(0);
7436 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7437 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7438 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7441 // Now check that the other operand of the AND is a constant. We could
7442 // make the transformation for non-constant splats as well, but it's unclear
7443 // that would be a benefit as it would not eliminate any operations, just
7444 // perform one more step in scalar code before moving to the vector unit.
7445 if (BuildVectorSDNode *BV =
7446 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7447 // Bail out if the vector isn't a constant.
7448 if (!BV->isConstant())
7451 // Everything checks out. Build up the new and improved node.
7453 EVT IntVT = BV->getValueType(0);
7454 // Create a new constant of the appropriate type for the transformed
7456 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7457 // The AND node needs bitcasts to/from an integer vector type around it.
7458 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7459 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7460 N->getOperand(0)->getOperand(0), MaskConst);
7461 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7468 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7469 const AArch64Subtarget *Subtarget) {
7470 // First try to optimize away the conversion when it's conditionally from
7471 // a constant. Vectors only.
7472 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7473 if (Res != SDValue())
7476 EVT VT = N->getValueType(0);
7477 if (VT != MVT::f32 && VT != MVT::f64)
7480 // Only optimize when the source and destination types have the same width.
7481 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7484 // If the result of an integer load is only used by an integer-to-float
7485 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7486 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7487 SDValue N0 = N->getOperand(0);
7488 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7489 // Do not change the width of a volatile load.
7490 !cast<LoadSDNode>(N0)->isVolatile()) {
7491 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7492 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7493 LN0->getPointerInfo(), LN0->isVolatile(),
7494 LN0->isNonTemporal(), LN0->isInvariant(),
7495 LN0->getAlignment());
7497 // Make sure successors of the original load stay after it by updating them
7498 // to use the new Chain.
7499 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7502 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7503 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7509 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7510 /// searches for and classifies those shifts.
7511 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7513 if (N.getOpcode() == ISD::SHL)
7515 else if (N.getOpcode() == ISD::SRL)
7520 if (!isa<ConstantSDNode>(N.getOperand(1)))
7523 ShiftAmount = N->getConstantOperandVal(1);
7524 Src = N->getOperand(0);
7528 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7529 /// registers viewed as a high/low pair. This function looks for the pattern:
7530 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7531 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7533 static SDValue tryCombineToEXTR(SDNode *N,
7534 TargetLowering::DAGCombinerInfo &DCI) {
7535 SelectionDAG &DAG = DCI.DAG;
7537 EVT VT = N->getValueType(0);
7539 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7541 if (VT != MVT::i32 && VT != MVT::i64)
7545 uint32_t ShiftLHS = 0;
7547 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7551 uint32_t ShiftRHS = 0;
7553 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7556 // If they're both trying to come from the high part of the register, they're
7557 // not really an EXTR.
7558 if (LHSFromHi == RHSFromHi)
7561 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7565 std::swap(LHS, RHS);
7566 std::swap(ShiftLHS, ShiftRHS);
7569 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7570 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7573 static SDValue tryCombineToBSL(SDNode *N,
7574 TargetLowering::DAGCombinerInfo &DCI) {
7575 EVT VT = N->getValueType(0);
7576 SelectionDAG &DAG = DCI.DAG;
7582 SDValue N0 = N->getOperand(0);
7583 if (N0.getOpcode() != ISD::AND)
7586 SDValue N1 = N->getOperand(1);
7587 if (N1.getOpcode() != ISD::AND)
7590 // We only have to look for constant vectors here since the general, variable
7591 // case can be handled in TableGen.
7592 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7593 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7594 for (int i = 1; i >= 0; --i)
7595 for (int j = 1; j >= 0; --j) {
7596 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7597 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7601 bool FoundMatch = true;
7602 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7603 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7604 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7606 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7613 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7614 N0->getOperand(1 - i), N1->getOperand(1 - j));
7620 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7621 const AArch64Subtarget *Subtarget) {
7622 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7623 if (!EnableAArch64ExtrGeneration)
7625 SelectionDAG &DAG = DCI.DAG;
7626 EVT VT = N->getValueType(0);
7628 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7631 SDValue Res = tryCombineToEXTR(N, DCI);
7635 Res = tryCombineToBSL(N, DCI);
7642 static SDValue performBitcastCombine(SDNode *N,
7643 TargetLowering::DAGCombinerInfo &DCI,
7644 SelectionDAG &DAG) {
7645 // Wait 'til after everything is legalized to try this. That way we have
7646 // legal vector types and such.
7647 if (DCI.isBeforeLegalizeOps())
7650 // Remove extraneous bitcasts around an extract_subvector.
7652 // (v4i16 (bitconvert
7653 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7655 // (extract_subvector ((v8i16 ...), (i64 4)))
7657 // Only interested in 64-bit vectors as the ultimate result.
7658 EVT VT = N->getValueType(0);
7661 if (VT.getSimpleVT().getSizeInBits() != 64)
7663 // Is the operand an extract_subvector starting at the beginning or halfway
7664 // point of the vector? A low half may also come through as an
7665 // EXTRACT_SUBREG, so look for that, too.
7666 SDValue Op0 = N->getOperand(0);
7667 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7668 !(Op0->isMachineOpcode() &&
7669 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7671 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7672 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7673 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7675 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7676 if (idx != AArch64::dsub)
7678 // The dsub reference is equivalent to a lane zero subvector reference.
7681 // Look through the bitcast of the input to the extract.
7682 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7684 SDValue Source = Op0->getOperand(0)->getOperand(0);
7685 // If the source type has twice the number of elements as our destination
7686 // type, we know this is an extract of the high or low half of the vector.
7687 EVT SVT = Source->getValueType(0);
7688 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7691 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7693 // Create the simplified form to just extract the low or high half of the
7694 // vector directly rather than bothering with the bitcasts.
7696 unsigned NumElements = VT.getVectorNumElements();
7698 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7699 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7701 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7702 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7708 static SDValue performConcatVectorsCombine(SDNode *N,
7709 TargetLowering::DAGCombinerInfo &DCI,
7710 SelectionDAG &DAG) {
7712 EVT VT = N->getValueType(0);
7713 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7715 // Optimize concat_vectors of truncated vectors, where the intermediate
7716 // type is illegal, to avoid said illegality, e.g.,
7717 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7718 // (v2i16 (truncate (v2i64)))))
7720 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7721 // (v4i32 (bitcast (v2i64))),
7723 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7724 // on both input and result type, so we might generate worse code.
7725 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7726 if (N->getNumOperands() == 2 &&
7727 N0->getOpcode() == ISD::TRUNCATE &&
7728 N1->getOpcode() == ISD::TRUNCATE) {
7729 SDValue N00 = N0->getOperand(0);
7730 SDValue N10 = N1->getOperand(0);
7731 EVT N00VT = N00.getValueType();
7733 if (N00VT == N10.getValueType() &&
7734 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7735 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7736 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7737 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7738 for (size_t i = 0; i < Mask.size(); ++i)
7740 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7741 DAG.getVectorShuffle(
7743 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7744 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7748 // Wait 'til after everything is legalized to try this. That way we have
7749 // legal vector types and such.
7750 if (DCI.isBeforeLegalizeOps())
7753 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7754 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7755 // canonicalise to that.
7756 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7757 assert(VT.getVectorElementType().getSizeInBits() == 64);
7758 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7759 DAG.getConstant(0, dl, MVT::i64));
7762 // Canonicalise concat_vectors so that the right-hand vector has as few
7763 // bit-casts as possible before its real operation. The primary matching
7764 // destination for these operations will be the narrowing "2" instructions,
7765 // which depend on the operation being performed on this right-hand vector.
7767 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7769 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7771 if (N1->getOpcode() != ISD::BITCAST)
7773 SDValue RHS = N1->getOperand(0);
7774 MVT RHSTy = RHS.getValueType().getSimpleVT();
7775 // If the RHS is not a vector, this is not the pattern we're looking for.
7776 if (!RHSTy.isVector())
7779 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7781 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7782 RHSTy.getVectorNumElements() * 2);
7783 return DAG.getNode(ISD::BITCAST, dl, VT,
7784 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7785 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7789 static SDValue tryCombineFixedPointConvert(SDNode *N,
7790 TargetLowering::DAGCombinerInfo &DCI,
7791 SelectionDAG &DAG) {
7792 // Wait 'til after everything is legalized to try this. That way we have
7793 // legal vector types and such.
7794 if (DCI.isBeforeLegalizeOps())
7796 // Transform a scalar conversion of a value from a lane extract into a
7797 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7798 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7799 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7801 // The second form interacts better with instruction selection and the
7802 // register allocator to avoid cross-class register copies that aren't
7803 // coalescable due to a lane reference.
7805 // Check the operand and see if it originates from a lane extract.
7806 SDValue Op1 = N->getOperand(1);
7807 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7808 // Yep, no additional predication needed. Perform the transform.
7809 SDValue IID = N->getOperand(0);
7810 SDValue Shift = N->getOperand(2);
7811 SDValue Vec = Op1.getOperand(0);
7812 SDValue Lane = Op1.getOperand(1);
7813 EVT ResTy = N->getValueType(0);
7817 // The vector width should be 128 bits by the time we get here, even
7818 // if it started as 64 bits (the extract_vector handling will have
7820 assert(Vec.getValueType().getSizeInBits() == 128 &&
7821 "unexpected vector size on extract_vector_elt!");
7822 if (Vec.getValueType() == MVT::v4i32)
7823 VecResTy = MVT::v4f32;
7824 else if (Vec.getValueType() == MVT::v2i64)
7825 VecResTy = MVT::v2f64;
7827 llvm_unreachable("unexpected vector type!");
7830 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7831 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7836 // AArch64 high-vector "long" operations are formed by performing the non-high
7837 // version on an extract_subvector of each operand which gets the high half:
7839 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7841 // However, there are cases which don't have an extract_high explicitly, but
7842 // have another operation that can be made compatible with one for free. For
7845 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7847 // This routine does the actual conversion of such DUPs, once outer routines
7848 // have determined that everything else is in order.
7849 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
7851 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7852 switch (N.getOpcode()) {
7853 case AArch64ISD::DUP:
7854 case AArch64ISD::DUPLANE8:
7855 case AArch64ISD::DUPLANE16:
7856 case AArch64ISD::DUPLANE32:
7857 case AArch64ISD::DUPLANE64:
7858 case AArch64ISD::MOVI:
7859 case AArch64ISD::MOVIshift:
7860 case AArch64ISD::MOVIedit:
7861 case AArch64ISD::MOVImsl:
7862 case AArch64ISD::MVNIshift:
7863 case AArch64ISD::MVNImsl:
7866 // FMOV could be supported, but isn't very useful, as it would only occur
7867 // if you passed a bitcast' floating point immediate to an eligible long
7868 // integer op (addl, smull, ...).
7872 MVT NarrowTy = N.getSimpleValueType();
7873 if (!NarrowTy.is64BitVector())
7876 MVT ElementTy = NarrowTy.getVectorElementType();
7877 unsigned NumElems = NarrowTy.getVectorNumElements();
7878 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7881 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
7882 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
7883 DAG.getConstant(NumElems, dl, MVT::i64));
7886 static bool isEssentiallyExtractSubvector(SDValue N) {
7887 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7890 return N.getOpcode() == ISD::BITCAST &&
7891 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7894 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7895 struct GenericSetCCInfo {
7896 const SDValue *Opnd0;
7897 const SDValue *Opnd1;
7901 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7902 struct AArch64SetCCInfo {
7904 AArch64CC::CondCode CC;
7907 /// \brief Helper structure to keep track of SetCC information.
7909 GenericSetCCInfo Generic;
7910 AArch64SetCCInfo AArch64;
7913 /// \brief Helper structure to be able to read SetCC information. If set to
7914 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7915 /// GenericSetCCInfo.
7916 struct SetCCInfoAndKind {
7921 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7923 /// AArch64 lowered one.
7924 /// \p SetCCInfo is filled accordingly.
7925 /// \post SetCCInfo is meanginfull only when this function returns true.
7926 /// \return True when Op is a kind of SET_CC operation.
7927 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7928 // If this is a setcc, this is straight forward.
7929 if (Op.getOpcode() == ISD::SETCC) {
7930 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7931 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7932 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7933 SetCCInfo.IsAArch64 = false;
7936 // Otherwise, check if this is a matching csel instruction.
7940 if (Op.getOpcode() != AArch64ISD::CSEL)
7942 // Set the information about the operands.
7943 // TODO: we want the operands of the Cmp not the csel
7944 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7945 SetCCInfo.IsAArch64 = true;
7946 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7947 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7949 // Check that the operands matches the constraints:
7950 // (1) Both operands must be constants.
7951 // (2) One must be 1 and the other must be 0.
7952 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7953 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7956 if (!TValue || !FValue)
7960 if (!TValue->isOne()) {
7961 // Update the comparison when we are interested in !cc.
7962 std::swap(TValue, FValue);
7963 SetCCInfo.Info.AArch64.CC =
7964 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7966 return TValue->isOne() && FValue->isNullValue();
7969 // Returns true if Op is setcc or zext of setcc.
7970 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7971 if (isSetCC(Op, Info))
7973 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7974 isSetCC(Op->getOperand(0), Info));
7977 // The folding we want to perform is:
7978 // (add x, [zext] (setcc cc ...) )
7980 // (csel x, (add x, 1), !cc ...)
7982 // The latter will get matched to a CSINC instruction.
7983 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7984 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7985 SDValue LHS = Op->getOperand(0);
7986 SDValue RHS = Op->getOperand(1);
7987 SetCCInfoAndKind InfoAndKind;
7989 // If neither operand is a SET_CC, give up.
7990 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7991 std::swap(LHS, RHS);
7992 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7996 // FIXME: This could be generatized to work for FP comparisons.
7997 EVT CmpVT = InfoAndKind.IsAArch64
7998 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7999 : InfoAndKind.Info.Generic.Opnd0->getValueType();
8000 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
8006 if (InfoAndKind.IsAArch64) {
8007 CCVal = DAG.getConstant(
8008 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8010 Cmp = *InfoAndKind.Info.AArch64.Cmp;
8012 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
8013 *InfoAndKind.Info.Generic.Opnd1,
8014 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
8017 EVT VT = Op->getValueType(0);
8018 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8019 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8022 // The basic add/sub long vector instructions have variants with "2" on the end
8023 // which act on the high-half of their inputs. They are normally matched by
8026 // (add (zeroext (extract_high LHS)),
8027 // (zeroext (extract_high RHS)))
8028 // -> uaddl2 vD, vN, vM
8030 // However, if one of the extracts is something like a duplicate, this
8031 // instruction can still be used profitably. This function puts the DAG into a
8032 // more appropriate form for those patterns to trigger.
8033 static SDValue performAddSubLongCombine(SDNode *N,
8034 TargetLowering::DAGCombinerInfo &DCI,
8035 SelectionDAG &DAG) {
8036 if (DCI.isBeforeLegalizeOps())
8039 MVT VT = N->getSimpleValueType(0);
8040 if (!VT.is128BitVector()) {
8041 if (N->getOpcode() == ISD::ADD)
8042 return performSetccAddFolding(N, DAG);
8046 // Make sure both branches are extended in the same way.
8047 SDValue LHS = N->getOperand(0);
8048 SDValue RHS = N->getOperand(1);
8049 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8050 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8051 LHS.getOpcode() != RHS.getOpcode())
8054 unsigned ExtType = LHS.getOpcode();
8056 // It's not worth doing if at least one of the inputs isn't already an
8057 // extract, but we don't know which it'll be so we have to try both.
8058 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
8059 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
8063 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8064 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
8065 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
8069 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8072 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8075 // Massage DAGs which we can use the high-half "long" operations on into
8076 // something isel will recognize better. E.g.
8078 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
8079 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8080 // (extract_high (v2i64 (dup128 scalar)))))
8082 static SDValue tryCombineLongOpWithDup(SDNode *N,
8083 TargetLowering::DAGCombinerInfo &DCI,
8084 SelectionDAG &DAG) {
8085 if (DCI.isBeforeLegalizeOps())
8088 bool IsIntrinsic = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
8089 SDValue LHS = N->getOperand(IsIntrinsic ? 1 : 0);
8090 SDValue RHS = N->getOperand(IsIntrinsic ? 2 : 1);
8091 assert(LHS.getValueType().is64BitVector() &&
8092 RHS.getValueType().is64BitVector() &&
8093 "unexpected shape for long operation");
8095 // Either node could be a DUP, but it's not worth doing both of them (you'd
8096 // just as well use the non-high version) so look for a corresponding extract
8097 // operation on the other "wing".
8098 if (isEssentiallyExtractSubvector(LHS)) {
8099 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
8102 } else if (isEssentiallyExtractSubvector(RHS)) {
8103 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
8108 // N could either be an intrinsic or a sabsdiff/uabsdiff node.
8110 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
8111 N->getOperand(0), LHS, RHS);
8113 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
8117 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
8118 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
8119 unsigned ElemBits = ElemTy.getSizeInBits();
8121 int64_t ShiftAmount;
8122 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
8123 APInt SplatValue, SplatUndef;
8124 unsigned SplatBitSize;
8126 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
8127 HasAnyUndefs, ElemBits) ||
8128 SplatBitSize != ElemBits)
8131 ShiftAmount = SplatValue.getSExtValue();
8132 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
8133 ShiftAmount = CVN->getSExtValue();
8141 llvm_unreachable("Unknown shift intrinsic");
8142 case Intrinsic::aarch64_neon_sqshl:
8143 Opcode = AArch64ISD::SQSHL_I;
8144 IsRightShift = false;
8146 case Intrinsic::aarch64_neon_uqshl:
8147 Opcode = AArch64ISD::UQSHL_I;
8148 IsRightShift = false;
8150 case Intrinsic::aarch64_neon_srshl:
8151 Opcode = AArch64ISD::SRSHR_I;
8152 IsRightShift = true;
8154 case Intrinsic::aarch64_neon_urshl:
8155 Opcode = AArch64ISD::URSHR_I;
8156 IsRightShift = true;
8158 case Intrinsic::aarch64_neon_sqshlu:
8159 Opcode = AArch64ISD::SQSHLU_I;
8160 IsRightShift = false;
8164 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8166 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8167 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8168 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
8170 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8171 DAG.getConstant(ShiftAmount, dl, MVT::i32));
8177 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
8178 // the intrinsics must be legal and take an i32, this means there's almost
8179 // certainly going to be a zext in the DAG which we can eliminate.
8180 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
8181 SDValue AndN = N->getOperand(2);
8182 if (AndN.getOpcode() != ISD::AND)
8185 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
8186 if (!CMask || CMask->getZExtValue() != Mask)
8189 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
8190 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
8193 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
8194 SelectionDAG &DAG) {
8196 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
8197 DAG.getNode(Opc, dl,
8198 N->getOperand(1).getSimpleValueType(),
8200 DAG.getConstant(0, dl, MVT::i64));
8203 static SDValue performIntrinsicCombine(SDNode *N,
8204 TargetLowering::DAGCombinerInfo &DCI,
8205 const AArch64Subtarget *Subtarget) {
8206 SelectionDAG &DAG = DCI.DAG;
8207 unsigned IID = getIntrinsicID(N);
8211 case Intrinsic::aarch64_neon_vcvtfxs2fp:
8212 case Intrinsic::aarch64_neon_vcvtfxu2fp:
8213 return tryCombineFixedPointConvert(N, DCI, DAG);
8215 case Intrinsic::aarch64_neon_saddv:
8216 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
8217 case Intrinsic::aarch64_neon_uaddv:
8218 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
8219 case Intrinsic::aarch64_neon_sminv:
8220 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
8221 case Intrinsic::aarch64_neon_uminv:
8222 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
8223 case Intrinsic::aarch64_neon_smaxv:
8224 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
8225 case Intrinsic::aarch64_neon_umaxv:
8226 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
8227 case Intrinsic::aarch64_neon_fmax:
8228 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
8229 N->getOperand(1), N->getOperand(2));
8230 case Intrinsic::aarch64_neon_fmin:
8231 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
8232 N->getOperand(1), N->getOperand(2));
8233 case Intrinsic::aarch64_neon_sabd:
8234 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
8235 N->getOperand(1), N->getOperand(2));
8236 case Intrinsic::aarch64_neon_uabd:
8237 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
8238 N->getOperand(1), N->getOperand(2));
8239 case Intrinsic::aarch64_neon_smull:
8240 case Intrinsic::aarch64_neon_umull:
8241 case Intrinsic::aarch64_neon_pmull:
8242 case Intrinsic::aarch64_neon_sqdmull:
8243 return tryCombineLongOpWithDup(N, DCI, DAG);
8244 case Intrinsic::aarch64_neon_sqshl:
8245 case Intrinsic::aarch64_neon_uqshl:
8246 case Intrinsic::aarch64_neon_sqshlu:
8247 case Intrinsic::aarch64_neon_srshl:
8248 case Intrinsic::aarch64_neon_urshl:
8249 return tryCombineShiftImm(IID, N, DAG);
8250 case Intrinsic::aarch64_crc32b:
8251 case Intrinsic::aarch64_crc32cb:
8252 return tryCombineCRC32(0xff, N, DAG);
8253 case Intrinsic::aarch64_crc32h:
8254 case Intrinsic::aarch64_crc32ch:
8255 return tryCombineCRC32(0xffff, N, DAG);
8260 static SDValue performExtendCombine(SDNode *N,
8261 TargetLowering::DAGCombinerInfo &DCI,
8262 SelectionDAG &DAG) {
8263 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8264 // we can convert that DUP into another extract_high (of a bigger DUP), which
8265 // helps the backend to decide that an sabdl2 would be useful, saving a real
8266 // extract_high operation.
8267 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8268 (N->getOperand(0).getOpcode() == ISD::SABSDIFF ||
8269 N->getOperand(0).getOpcode() == ISD::UABSDIFF)) {
8270 SDNode *ABDNode = N->getOperand(0).getNode();
8271 SDValue NewABD = tryCombineLongOpWithDup(ABDNode, DCI, DAG);
8272 if (!NewABD.getNode())
8275 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8279 // This is effectively a custom type legalization for AArch64.
8281 // Type legalization will split an extend of a small, legal, type to a larger
8282 // illegal type by first splitting the destination type, often creating
8283 // illegal source types, which then get legalized in isel-confusing ways,
8284 // leading to really terrible codegen. E.g.,
8285 // %result = v8i32 sext v8i8 %value
8287 // %losrc = extract_subreg %value, ...
8288 // %hisrc = extract_subreg %value, ...
8289 // %lo = v4i32 sext v4i8 %losrc
8290 // %hi = v4i32 sext v4i8 %hisrc
8291 // Things go rapidly downhill from there.
8293 // For AArch64, the [sz]ext vector instructions can only go up one element
8294 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8295 // take two instructions.
8297 // This implies that the most efficient way to do the extend from v8i8
8298 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8299 // the normal splitting to happen for the v8i16->v8i32.
8301 // This is pre-legalization to catch some cases where the default
8302 // type legalization will create ill-tempered code.
8303 if (!DCI.isBeforeLegalizeOps())
8306 // We're only interested in cleaning things up for non-legal vector types
8307 // here. If both the source and destination are legal, things will just
8308 // work naturally without any fiddling.
8309 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8310 EVT ResVT = N->getValueType(0);
8311 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8313 // If the vector type isn't a simple VT, it's beyond the scope of what
8314 // we're worried about here. Let legalization do its thing and hope for
8316 SDValue Src = N->getOperand(0);
8317 EVT SrcVT = Src->getValueType(0);
8318 if (!ResVT.isSimple() || !SrcVT.isSimple())
8321 // If the source VT is a 64-bit vector, we can play games and get the
8322 // better results we want.
8323 if (SrcVT.getSizeInBits() != 64)
8326 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
8327 unsigned ElementCount = SrcVT.getVectorNumElements();
8328 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8330 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8332 // Now split the rest of the operation into two halves, each with a 64
8336 unsigned NumElements = ResVT.getVectorNumElements();
8337 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8338 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8339 ResVT.getVectorElementType(), NumElements / 2);
8341 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8342 LoVT.getVectorNumElements());
8343 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8344 DAG.getConstant(0, DL, MVT::i64));
8345 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8346 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8347 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8348 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8350 // Now combine the parts back together so we still have a single result
8351 // like the combiner expects.
8352 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8355 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
8356 /// value. The load store optimizer pass will merge them to store pair stores.
8357 /// This has better performance than a splat of the scalar followed by a split
8358 /// vector store. Even if the stores are not merged it is four stores vs a dup,
8359 /// followed by an ext.b and two stores.
8360 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
8361 SDValue StVal = St->getValue();
8362 EVT VT = StVal.getValueType();
8364 // Don't replace floating point stores, they possibly won't be transformed to
8365 // stp because of the store pair suppress pass.
8366 if (VT.isFloatingPoint())
8369 // Check for insert vector elements.
8370 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8373 // We can express a splat as store pair(s) for 2 or 4 elements.
8374 unsigned NumVecElts = VT.getVectorNumElements();
8375 if (NumVecElts != 4 && NumVecElts != 2)
8377 SDValue SplatVal = StVal.getOperand(1);
8378 unsigned RemainInsertElts = NumVecElts - 1;
8380 // Check that this is a splat.
8381 while (--RemainInsertElts) {
8382 SDValue NextInsertElt = StVal.getOperand(0);
8383 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8385 if (NextInsertElt.getOperand(1) != SplatVal)
8387 StVal = NextInsertElt;
8389 unsigned OrigAlignment = St->getAlignment();
8390 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
8391 unsigned Alignment = std::min(OrigAlignment, EltOffset);
8393 // Create scalar stores. This is at least as good as the code sequence for a
8394 // split unaligned store wich is a dup.s, ext.b, and two stores.
8395 // Most of the time the three stores should be replaced by store pair
8396 // instructions (stp).
8398 SDValue BasePtr = St->getBasePtr();
8400 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
8401 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
8403 unsigned Offset = EltOffset;
8404 while (--NumVecElts) {
8405 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8406 DAG.getConstant(Offset, DL, MVT::i64));
8407 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8408 St->getPointerInfo(), St->isVolatile(),
8409 St->isNonTemporal(), Alignment);
8410 Offset += EltOffset;
8415 static SDValue performSTORECombine(SDNode *N,
8416 TargetLowering::DAGCombinerInfo &DCI,
8418 const AArch64Subtarget *Subtarget) {
8419 if (!DCI.isBeforeLegalize())
8422 StoreSDNode *S = cast<StoreSDNode>(N);
8423 if (S->isVolatile())
8426 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8427 // page boundaries. We want to split such stores.
8428 if (!Subtarget->isCyclone())
8431 // Don't split at Oz.
8432 MachineFunction &MF = DAG.getMachineFunction();
8433 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8437 SDValue StVal = S->getValue();
8438 EVT VT = StVal.getValueType();
8440 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8441 // those up regresses performance on micro-benchmarks and olden/bh.
8442 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8445 // Split unaligned 16B stores. They are terrible for performance.
8446 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8447 // extensions can use this to mark that it does not want splitting to happen
8448 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8449 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8450 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8451 S->getAlignment() <= 2)
8454 // If we get a splat of a scalar convert this vector store to a store of
8455 // scalars. They will be merged into store pairs thereby removing two
8457 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8458 if (ReplacedSplat != SDValue())
8459 return ReplacedSplat;
8462 unsigned NumElts = VT.getVectorNumElements() / 2;
8463 // Split VT into two.
8465 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8466 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8467 DAG.getConstant(0, DL, MVT::i64));
8468 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8469 DAG.getConstant(NumElts, DL, MVT::i64));
8470 SDValue BasePtr = S->getBasePtr();
8472 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8473 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8474 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8475 DAG.getConstant(8, DL, MVT::i64));
8476 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8477 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8481 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8482 /// post-increment LD1R.
8483 static SDValue performPostLD1Combine(SDNode *N,
8484 TargetLowering::DAGCombinerInfo &DCI,
8486 if (DCI.isBeforeLegalizeOps())
8489 SelectionDAG &DAG = DCI.DAG;
8490 EVT VT = N->getValueType(0);
8492 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8493 SDNode *LD = N->getOperand(LoadIdx).getNode();
8494 // If it is not LOAD, can not do such combine.
8495 if (LD->getOpcode() != ISD::LOAD)
8498 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8499 EVT MemVT = LoadSDN->getMemoryVT();
8500 // Check if memory operand is the same type as the vector element.
8501 if (MemVT != VT.getVectorElementType())
8504 // Check if there are other uses. If so, do not combine as it will introduce
8506 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8508 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8514 SDValue Addr = LD->getOperand(1);
8515 SDValue Vector = N->getOperand(0);
8516 // Search for a use of the address operand that is an increment.
8517 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8518 Addr.getNode()->use_end(); UI != UE; ++UI) {
8520 if (User->getOpcode() != ISD::ADD
8521 || UI.getUse().getResNo() != Addr.getResNo())
8524 // Check that the add is independent of the load. Otherwise, folding it
8525 // would create a cycle.
8526 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8528 // Also check that add is not used in the vector operand. This would also
8530 if (User->isPredecessorOf(Vector.getNode()))
8533 // If the increment is a constant, it must match the memory ref size.
8534 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8535 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8536 uint32_t IncVal = CInc->getZExtValue();
8537 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8538 if (IncVal != NumBytes)
8540 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8543 // Finally, check that the vector doesn't depend on the load.
8544 // Again, this would create a cycle.
8545 // The load depending on the vector is fine, as that's the case for the
8546 // LD1*post we'll eventually generate anyway.
8547 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8550 SmallVector<SDValue, 8> Ops;
8551 Ops.push_back(LD->getOperand(0)); // Chain
8553 Ops.push_back(Vector); // The vector to be inserted
8554 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8556 Ops.push_back(Addr);
8559 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8560 SDVTList SDTys = DAG.getVTList(Tys);
8561 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8562 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8564 LoadSDN->getMemOperand());
8567 SmallVector<SDValue, 2> NewResults;
8568 NewResults.push_back(SDValue(LD, 0)); // The result of load
8569 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8570 DCI.CombineTo(LD, NewResults);
8571 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8572 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8579 /// Target-specific DAG combine function for NEON load/store intrinsics
8580 /// to merge base address updates.
8581 static SDValue performNEONPostLDSTCombine(SDNode *N,
8582 TargetLowering::DAGCombinerInfo &DCI,
8583 SelectionDAG &DAG) {
8584 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8587 unsigned AddrOpIdx = N->getNumOperands() - 1;
8588 SDValue Addr = N->getOperand(AddrOpIdx);
8590 // Search for a use of the address operand that is an increment.
8591 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8592 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8594 if (User->getOpcode() != ISD::ADD ||
8595 UI.getUse().getResNo() != Addr.getResNo())
8598 // Check that the add is independent of the load/store. Otherwise, folding
8599 // it would create a cycle.
8600 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8603 // Find the new opcode for the updating load/store.
8604 bool IsStore = false;
8605 bool IsLaneOp = false;
8606 bool IsDupOp = false;
8607 unsigned NewOpc = 0;
8608 unsigned NumVecs = 0;
8609 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8611 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8612 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8614 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8616 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8618 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8619 NumVecs = 2; IsStore = true; break;
8620 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8621 NumVecs = 3; IsStore = true; break;
8622 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8623 NumVecs = 4; IsStore = true; break;
8624 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8626 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8628 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8630 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8631 NumVecs = 2; IsStore = true; break;
8632 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8633 NumVecs = 3; IsStore = true; break;
8634 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8635 NumVecs = 4; IsStore = true; break;
8636 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8637 NumVecs = 2; IsDupOp = true; break;
8638 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8639 NumVecs = 3; IsDupOp = true; break;
8640 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8641 NumVecs = 4; IsDupOp = true; break;
8642 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8643 NumVecs = 2; IsLaneOp = true; break;
8644 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8645 NumVecs = 3; IsLaneOp = true; break;
8646 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8647 NumVecs = 4; IsLaneOp = true; break;
8648 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8649 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8650 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8651 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8652 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8653 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8658 VecTy = N->getOperand(2).getValueType();
8660 VecTy = N->getValueType(0);
8662 // If the increment is a constant, it must match the memory ref size.
8663 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8664 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8665 uint32_t IncVal = CInc->getZExtValue();
8666 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8667 if (IsLaneOp || IsDupOp)
8668 NumBytes /= VecTy.getVectorNumElements();
8669 if (IncVal != NumBytes)
8671 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8673 SmallVector<SDValue, 8> Ops;
8674 Ops.push_back(N->getOperand(0)); // Incoming chain
8675 // Load lane and store have vector list as input.
8676 if (IsLaneOp || IsStore)
8677 for (unsigned i = 2; i < AddrOpIdx; ++i)
8678 Ops.push_back(N->getOperand(i));
8679 Ops.push_back(Addr); // Base register
8684 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8686 for (n = 0; n < NumResultVecs; ++n)
8688 Tys[n++] = MVT::i64; // Type of write back register
8689 Tys[n] = MVT::Other; // Type of the chain
8690 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8692 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8693 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8694 MemInt->getMemoryVT(),
8695 MemInt->getMemOperand());
8698 std::vector<SDValue> NewResults;
8699 for (unsigned i = 0; i < NumResultVecs; ++i) {
8700 NewResults.push_back(SDValue(UpdN.getNode(), i));
8702 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8703 DCI.CombineTo(N, NewResults);
8704 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8711 // Checks to see if the value is the prescribed width and returns information
8712 // about its extension mode.
8714 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8715 ExtType = ISD::NON_EXTLOAD;
8716 switch(V.getNode()->getOpcode()) {
8720 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8721 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8722 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8723 ExtType = LoadNode->getExtensionType();
8728 case ISD::AssertSext: {
8729 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8730 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8731 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8732 ExtType = ISD::SEXTLOAD;
8737 case ISD::AssertZext: {
8738 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8739 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8740 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8741 ExtType = ISD::ZEXTLOAD;
8747 case ISD::TargetConstant: {
8748 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8758 // This function does a whole lot of voodoo to determine if the tests are
8759 // equivalent without and with a mask. Essentially what happens is that given a
8762 // +-------------+ +-------------+ +-------------+ +-------------+
8763 // | Input | | AddConstant | | CompConstant| | CC |
8764 // +-------------+ +-------------+ +-------------+ +-------------+
8766 // V V | +----------+
8767 // +-------------+ +----+ | |
8768 // | ADD | |0xff| | |
8769 // +-------------+ +----+ | |
8772 // +-------------+ | |
8774 // +-------------+ | |
8783 // The AND node may be safely removed for some combinations of inputs. In
8784 // particular we need to take into account the extension type of the Input,
8785 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8786 // width of the input (this can work for any width inputs, the above graph is
8787 // specific to 8 bits.
8789 // The specific equations were worked out by generating output tables for each
8790 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8791 // problem was simplified by working with 4 bit inputs, which means we only
8792 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8793 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8794 // patterns present in both extensions (0,7). For every distinct set of
8795 // AddConstant and CompConstants bit patterns we can consider the masked and
8796 // unmasked versions to be equivalent if the result of this function is true for
8797 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8800 // and w10, w8, #0x0f
8802 // cset w9, AArch64CC
8804 // cset w11, AArch64CC
8809 // Since the above function shows when the outputs are equivalent it defines
8810 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8811 // would be expensive to run during compiles. The equations below were written
8812 // in a test harness that confirmed they gave equivalent outputs to the above
8813 // for all inputs function, so they can be used determine if the removal is
8816 // isEquivalentMaskless() is the code for testing if the AND can be removed
8817 // factored out of the DAG recognition as the DAG can take several forms.
8820 bool isEquivalentMaskless(unsigned CC, unsigned width,
8821 ISD::LoadExtType ExtType, signed AddConstant,
8822 signed CompConstant) {
8823 // By being careful about our equations and only writing the in term
8824 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8825 // make them generally applicable to all bit widths.
8826 signed MaxUInt = (1 << width);
8828 // For the purposes of these comparisons sign extending the type is
8829 // equivalent to zero extending the add and displacing it by half the integer
8830 // width. Provided we are careful and make sure our equations are valid over
8831 // the whole range we can just adjust the input and avoid writing equations
8832 // for sign extended inputs.
8833 if (ExtType == ISD::SEXTLOAD)
8834 AddConstant -= (1 << (width-1));
8838 case AArch64CC::GT: {
8839 if ((AddConstant == 0) ||
8840 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8841 (AddConstant >= 0 && CompConstant < 0) ||
8842 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8846 case AArch64CC::GE: {
8847 if ((AddConstant == 0) ||
8848 (AddConstant >= 0 && CompConstant <= 0) ||
8849 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8853 case AArch64CC::LS: {
8854 if ((AddConstant >= 0 && CompConstant < 0) ||
8855 (AddConstant <= 0 && CompConstant >= -1 &&
8856 CompConstant < AddConstant + MaxUInt))
8860 case AArch64CC::MI: {
8861 if ((AddConstant == 0) ||
8862 (AddConstant > 0 && CompConstant <= 0) ||
8863 (AddConstant < 0 && CompConstant <= AddConstant))
8867 case AArch64CC::HS: {
8868 if ((AddConstant >= 0 && CompConstant <= 0) ||
8869 (AddConstant <= 0 && CompConstant >= 0 &&
8870 CompConstant <= AddConstant + MaxUInt))
8874 case AArch64CC::NE: {
8875 if ((AddConstant > 0 && CompConstant < 0) ||
8876 (AddConstant < 0 && CompConstant >= 0 &&
8877 CompConstant < AddConstant + MaxUInt) ||
8878 (AddConstant >= 0 && CompConstant >= 0 &&
8879 CompConstant >= AddConstant) ||
8880 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8889 case AArch64CC::Invalid:
8897 SDValue performCONDCombine(SDNode *N,
8898 TargetLowering::DAGCombinerInfo &DCI,
8899 SelectionDAG &DAG, unsigned CCIndex,
8900 unsigned CmpIndex) {
8901 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8902 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8903 unsigned CondOpcode = SubsNode->getOpcode();
8905 if (CondOpcode != AArch64ISD::SUBS)
8908 // There is a SUBS feeding this condition. Is it fed by a mask we can
8911 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8912 unsigned MaskBits = 0;
8914 if (AndNode->getOpcode() != ISD::AND)
8917 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8918 uint32_t CNV = CN->getZExtValue();
8921 else if (CNV == 65535)
8928 SDValue AddValue = AndNode->getOperand(0);
8930 if (AddValue.getOpcode() != ISD::ADD)
8933 // The basic dag structure is correct, grab the inputs and validate them.
8935 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8936 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8937 SDValue SubsInputValue = SubsNode->getOperand(1);
8939 // The mask is present and the provenance of all the values is a smaller type,
8940 // lets see if the mask is superfluous.
8942 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8943 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8946 ISD::LoadExtType ExtType;
8948 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8949 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8950 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8953 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8954 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8955 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8958 // The AND is not necessary, remove it.
8960 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8961 SubsNode->getValueType(1));
8962 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8964 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8965 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8967 return SDValue(N, 0);
8970 // Optimize compare with zero and branch.
8971 static SDValue performBRCONDCombine(SDNode *N,
8972 TargetLowering::DAGCombinerInfo &DCI,
8973 SelectionDAG &DAG) {
8974 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8977 SDValue Chain = N->getOperand(0);
8978 SDValue Dest = N->getOperand(1);
8979 SDValue CCVal = N->getOperand(2);
8980 SDValue Cmp = N->getOperand(3);
8982 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8983 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8984 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8987 unsigned CmpOpc = Cmp.getOpcode();
8988 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8991 // Only attempt folding if there is only one use of the flag and no use of the
8993 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8996 SDValue LHS = Cmp.getOperand(0);
8997 SDValue RHS = Cmp.getOperand(1);
8999 assert(LHS.getValueType() == RHS.getValueType() &&
9000 "Expected the value type to be the same for both operands!");
9001 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
9004 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
9005 std::swap(LHS, RHS);
9007 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
9010 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9011 LHS.getOpcode() == ISD::SRL)
9014 // Fold the compare into the branch instruction.
9016 if (CC == AArch64CC::EQ)
9017 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9019 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9021 // Do not add new nodes to DAG combiner worklist.
9022 DCI.CombineTo(N, BR, false);
9027 // vselect (v1i1 setcc) ->
9028 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
9029 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
9030 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
9032 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
9033 SDValue N0 = N->getOperand(0);
9034 EVT CCVT = N0.getValueType();
9036 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9037 CCVT.getVectorElementType() != MVT::i1)
9040 EVT ResVT = N->getValueType(0);
9041 EVT CmpVT = N0.getOperand(0).getValueType();
9042 // Only combine when the result type is of the same size as the compared
9044 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
9047 SDValue IfTrue = N->getOperand(1);
9048 SDValue IfFalse = N->getOperand(2);
9050 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
9051 N0.getOperand(0), N0.getOperand(1),
9052 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9053 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
9057 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
9058 /// the compare-mask instructions rather than going via NZCV, even if LHS and
9059 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
9060 /// with a vector one followed by a DUP shuffle on the result.
9061 static SDValue performSelectCombine(SDNode *N,
9062 TargetLowering::DAGCombinerInfo &DCI) {
9063 SelectionDAG &DAG = DCI.DAG;
9064 SDValue N0 = N->getOperand(0);
9065 EVT ResVT = N->getValueType(0);
9067 if (N0.getOpcode() != ISD::SETCC)
9070 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
9071 // scalar SetCCResultType. We also don't expect vectors, because we assume
9072 // that selects fed by vector SETCCs are canonicalized to VSELECT.
9073 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
9074 "Scalar-SETCC feeding SELECT has unexpected result type!");
9076 // If NumMaskElts == 0, the comparison is larger than select result. The
9077 // largest real NEON comparison is 64-bits per lane, which means the result is
9078 // at most 32-bits and an illegal vector. Just bail out for now.
9079 EVT SrcVT = N0.getOperand(0).getValueType();
9081 // Don't try to do this optimization when the setcc itself has i1 operands.
9082 // There are no legal vectors of i1, so this would be pointless.
9083 if (SrcVT == MVT::i1)
9086 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
9087 if (!ResVT.isVector() || NumMaskElts == 0)
9090 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
9091 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
9093 // Also bail out if the vector CCVT isn't the same size as ResVT.
9094 // This can happen if the SETCC operand size doesn't divide the ResVT size
9095 // (e.g., f64 vs v3f32).
9096 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
9099 // Make sure we didn't create illegal types, if we're not supposed to.
9100 assert(DCI.isBeforeLegalize() ||
9101 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
9103 // First perform a vector comparison, where lane 0 is the one we're interested
9107 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
9109 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
9110 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
9112 // Now duplicate the comparison mask we want across all other lanes.
9113 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
9114 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
9115 Mask = DAG.getNode(ISD::BITCAST, DL,
9116 ResVT.changeVectorElementTypeToInteger(), Mask);
9118 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
9121 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
9122 /// to match FMIN/FMAX patterns.
9123 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
9124 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
9125 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
9126 // vmax/vmin return NaN if either operand is a NaN;
9127 // only do the transformation when it matches that behavior.
9129 SDValue CondLHS = N->getOperand(0);
9130 SDValue CondRHS = N->getOperand(1);
9131 SDValue LHS = N->getOperand(2);
9132 SDValue RHS = N->getOperand(3);
9133 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9137 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
9138 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
9139 IsReversed = false; // x CC y ? x : y
9140 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
9141 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
9142 IsReversed = true ; // x CC y ? y : x
9147 bool IsUnordered = false, IsOrEqual;
9158 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
9159 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
9169 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
9170 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
9174 // If LHS is NaN, an ordered comparison will be false and the result will be
9175 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
9176 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9177 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9180 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
9181 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
9182 // used for unsafe math or if one of the operands is known to be nonzero.
9183 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
9184 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9187 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9190 /// Get rid of unnecessary NVCASTs (that don't change the type).
9191 static SDValue performNVCASTCombine(SDNode *N) {
9192 if (N->getValueType(0) == N->getOperand(0).getValueType())
9193 return N->getOperand(0);
9198 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
9199 DAGCombinerInfo &DCI) const {
9200 SelectionDAG &DAG = DCI.DAG;
9201 switch (N->getOpcode()) {
9206 return performAddSubLongCombine(N, DCI, DAG);
9208 return performXorCombine(N, DAG, DCI, Subtarget);
9210 return performMulCombine(N, DAG, DCI, Subtarget);
9211 case ISD::SINT_TO_FP:
9212 case ISD::UINT_TO_FP:
9213 return performIntToFpCombine(N, DAG, Subtarget);
9215 return performORCombine(N, DCI, Subtarget);
9216 case ISD::INTRINSIC_WO_CHAIN:
9217 return performIntrinsicCombine(N, DCI, Subtarget);
9218 case ISD::ANY_EXTEND:
9219 case ISD::ZERO_EXTEND:
9220 case ISD::SIGN_EXTEND:
9221 return performExtendCombine(N, DCI, DAG);
9223 return performBitcastCombine(N, DCI, DAG);
9224 case ISD::CONCAT_VECTORS:
9225 return performConcatVectorsCombine(N, DCI, DAG);
9227 return performSelectCombine(N, DCI);
9229 return performVSelectCombine(N, DCI.DAG);
9230 case ISD::SELECT_CC:
9231 return performSelectCCCombine(N, DCI.DAG);
9233 return performSTORECombine(N, DCI, DAG, Subtarget);
9234 case AArch64ISD::BRCOND:
9235 return performBRCONDCombine(N, DCI, DAG);
9236 case AArch64ISD::CSEL:
9237 return performCONDCombine(N, DCI, DAG, 2, 3);
9238 case AArch64ISD::DUP:
9239 return performPostLD1Combine(N, DCI, false);
9240 case AArch64ISD::NVCAST:
9241 return performNVCASTCombine(N);
9242 case ISD::INSERT_VECTOR_ELT:
9243 return performPostLD1Combine(N, DCI, true);
9244 case ISD::INTRINSIC_VOID:
9245 case ISD::INTRINSIC_W_CHAIN:
9246 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9247 case Intrinsic::aarch64_neon_ld2:
9248 case Intrinsic::aarch64_neon_ld3:
9249 case Intrinsic::aarch64_neon_ld4:
9250 case Intrinsic::aarch64_neon_ld1x2:
9251 case Intrinsic::aarch64_neon_ld1x3:
9252 case Intrinsic::aarch64_neon_ld1x4:
9253 case Intrinsic::aarch64_neon_ld2lane:
9254 case Intrinsic::aarch64_neon_ld3lane:
9255 case Intrinsic::aarch64_neon_ld4lane:
9256 case Intrinsic::aarch64_neon_ld2r:
9257 case Intrinsic::aarch64_neon_ld3r:
9258 case Intrinsic::aarch64_neon_ld4r:
9259 case Intrinsic::aarch64_neon_st2:
9260 case Intrinsic::aarch64_neon_st3:
9261 case Intrinsic::aarch64_neon_st4:
9262 case Intrinsic::aarch64_neon_st1x2:
9263 case Intrinsic::aarch64_neon_st1x3:
9264 case Intrinsic::aarch64_neon_st1x4:
9265 case Intrinsic::aarch64_neon_st2lane:
9266 case Intrinsic::aarch64_neon_st3lane:
9267 case Intrinsic::aarch64_neon_st4lane:
9268 return performNEONPostLDSTCombine(N, DCI, DAG);
9276 // Check if the return value is used as only a return value, as otherwise
9277 // we can't perform a tail-call. In particular, we need to check for
9278 // target ISD nodes that are returns and any other "odd" constructs
9279 // that the generic analysis code won't necessarily catch.
9280 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9281 SDValue &Chain) const {
9282 if (N->getNumValues() != 1)
9284 if (!N->hasNUsesOfValue(1, 0))
9287 SDValue TCChain = Chain;
9288 SDNode *Copy = *N->use_begin();
9289 if (Copy->getOpcode() == ISD::CopyToReg) {
9290 // If the copy has a glue operand, we conservatively assume it isn't safe to
9291 // perform a tail call.
9292 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
9295 TCChain = Copy->getOperand(0);
9296 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9299 bool HasRet = false;
9300 for (SDNode *Node : Copy->uses()) {
9301 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9313 // Return whether the an instruction can potentially be optimized to a tail
9314 // call. This will cause the optimizers to attempt to move, or duplicate,
9315 // return instructions to help enable tail call optimizations for this
9317 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9318 if (!CI->isTailCall())
9324 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
9326 ISD::MemIndexedMode &AM,
9328 SelectionDAG &DAG) const {
9329 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9332 Base = Op->getOperand(0);
9333 // All of the indexed addressing mode instructions take a signed
9334 // 9 bit immediate offset.
9335 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
9336 int64_t RHSC = (int64_t)RHS->getZExtValue();
9337 if (RHSC >= 256 || RHSC <= -256)
9339 IsInc = (Op->getOpcode() == ISD::ADD);
9340 Offset = Op->getOperand(1);
9346 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9348 ISD::MemIndexedMode &AM,
9349 SelectionDAG &DAG) const {
9352 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9353 VT = LD->getMemoryVT();
9354 Ptr = LD->getBasePtr();
9355 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9356 VT = ST->getMemoryVT();
9357 Ptr = ST->getBasePtr();
9362 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
9364 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
9368 bool AArch64TargetLowering::getPostIndexedAddressParts(
9369 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
9370 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
9373 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9374 VT = LD->getMemoryVT();
9375 Ptr = LD->getBasePtr();
9376 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9377 VT = ST->getMemoryVT();
9378 Ptr = ST->getBasePtr();
9383 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
9385 // Post-indexing updates the base, so it's not a valid transform
9386 // if that's not the same as the load's pointer.
9389 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
9393 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
9394 SelectionDAG &DAG) {
9396 SDValue Op = N->getOperand(0);
9398 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
9402 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
9403 DAG.getUNDEF(MVT::i32), Op,
9404 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
9406 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
9407 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
9410 void AArch64TargetLowering::ReplaceNodeResults(
9411 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
9412 switch (N->getOpcode()) {
9414 llvm_unreachable("Don't know how to custom expand this");
9416 ReplaceBITCASTResults(N, Results, DAG);
9418 case ISD::FP_TO_UINT:
9419 case ISD::FP_TO_SINT:
9420 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
9421 // Let normal code take care of it by not adding anything to Results.
9426 bool AArch64TargetLowering::useLoadStackGuardNode() const {
9430 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9431 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9432 // reciprocal if there are three or more FDIVs.
9433 return NumUsers > 2;
9436 TargetLoweringBase::LegalizeTypeAction
9437 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9438 MVT SVT = VT.getSimpleVT();
9439 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9440 // v4i16, v2i32 instead of to promote.
9441 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9442 || SVT == MVT::v1f32)
9443 return TypeWidenVector;
9445 return TargetLoweringBase::getPreferredVectorAction(VT);
9448 // Loads and stores less than 128-bits are already atomic; ones above that
9449 // are doomed anyway, so defer to the default libcall and blame the OS when
9451 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9452 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9456 // Loads and stores less than 128-bits are already atomic; ones above that
9457 // are doomed anyway, so defer to the default libcall and blame the OS when
9459 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9460 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9464 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9465 TargetLoweringBase::AtomicRMWExpansionKind
9466 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9467 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9468 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9469 : AtomicRMWExpansionKind::None;
9472 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9476 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9477 AtomicOrdering Ord) const {
9478 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9479 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9480 bool IsAcquire = isAtLeastAcquire(Ord);
9482 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9483 // intrinsic must return {i64, i64} and we have to recombine them into a
9484 // single i128 here.
9485 if (ValTy->getPrimitiveSizeInBits() == 128) {
9487 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9488 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9490 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9491 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9493 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9494 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9495 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9496 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9497 return Builder.CreateOr(
9498 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9501 Type *Tys[] = { Addr->getType() };
9503 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9504 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9506 return Builder.CreateTruncOrBitCast(
9507 Builder.CreateCall(Ldxr, Addr),
9508 cast<PointerType>(Addr->getType())->getElementType());
9511 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9512 Value *Val, Value *Addr,
9513 AtomicOrdering Ord) const {
9514 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9515 bool IsRelease = isAtLeastRelease(Ord);
9517 // Since the intrinsics must have legal type, the i128 intrinsics take two
9518 // parameters: "i64, i64". We must marshal Val into the appropriate form
9520 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9522 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9523 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9524 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9526 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9527 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9528 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9529 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
9533 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9534 Type *Tys[] = { Addr->getType() };
9535 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9537 return Builder.CreateCall(Stxr,
9538 {Builder.CreateZExtOrBitCast(
9539 Val, Stxr->getFunctionType()->getParamType(0)),
9543 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9544 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9545 return Ty->isArrayTy();
9548 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,