1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
46 static cl::opt<AlignMode>
47 Align(cl::desc("Load/store alignment support"),
48 cl::Hidden, cl::init(NoStrictAlign),
50 clEnumValN(StrictAlign, "aarch64-strict-align",
51 "Disallow all unaligned memory accesses"),
52 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
53 "Allow unaligned memory accesses"),
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
64 cl::desc("Allow AArch64 SLI/SRI formation"),
67 //===----------------------------------------------------------------------===//
68 // AArch64 Lowering public interface.
69 //===----------------------------------------------------------------------===//
70 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
71 if (TT.isOSBinFormatMachO())
72 return new AArch64_MachoTargetObjectFile();
74 return new AArch64_ELFTargetObjectFile();
77 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
79 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82 // we have to make something up. Arbitrarily, choose ZeroOrOne.
83 setBooleanContents(ZeroOrOneBooleanContent);
84 // When comparing vectors the result sets the different elements in the
85 // vector to all-one or all-zero.
86 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
92 if (Subtarget->hasFPARMv8()) {
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
99 if (Subtarget->hasNEON()) {
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102 // Someone set us up the NEON.
103 addDRTypeForNEON(MVT::v2f32);
104 addDRTypeForNEON(MVT::v8i8);
105 addDRTypeForNEON(MVT::v4i16);
106 addDRTypeForNEON(MVT::v2i32);
107 addDRTypeForNEON(MVT::v1i64);
108 addDRTypeForNEON(MVT::v1f64);
110 addQRTypeForNEON(MVT::v4f32);
111 addQRTypeForNEON(MVT::v2f64);
112 addQRTypeForNEON(MVT::v16i8);
113 addQRTypeForNEON(MVT::v8i16);
114 addQRTypeForNEON(MVT::v4i32);
115 addQRTypeForNEON(MVT::v2i64);
118 // Compute derived properties from the register classes
119 computeRegisterProperties();
121 // Provide all sorts of operation actions
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
141 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
142 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::FREM, MVT::f32, Expand);
149 setOperationAction(ISD::FREM, MVT::f64, Expand);
150 setOperationAction(ISD::FREM, MVT::f80, Expand);
152 // Custom lowering hooks are needed for XOR
153 // to fold it into CSINC/CSINV.
154 setOperationAction(ISD::XOR, MVT::i32, Custom);
155 setOperationAction(ISD::XOR, MVT::i64, Custom);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
158 // there's a valid register class, so we need custom operations in most cases.
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
198 // Variable arguments.
199 setOperationAction(ISD::VASTART, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Custom);
201 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
202 setOperationAction(ISD::VAEND, MVT::Other, Expand);
204 // Variable-sized objects.
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
209 // Exception handling.
210 // FIXME: These are guesses. Has this been defined yet?
211 setExceptionPointerRegister(AArch64::X0);
212 setExceptionSelectorRegister(AArch64::X1);
214 // Constant pool entries
215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
221 setOperationAction(ISD::ADDC, MVT::i32, Custom);
222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
223 setOperationAction(ISD::SUBC, MVT::i32, Custom);
224 setOperationAction(ISD::SUBE, MVT::i32, Custom);
225 setOperationAction(ISD::ADDC, MVT::i64, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
227 setOperationAction(ISD::SUBC, MVT::i64, Custom);
228 setOperationAction(ISD::SUBE, MVT::i64, Custom);
230 // AArch64 lacks both left-rotate and popcount instructions.
231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
234 // AArch64 doesn't have {U|S}MUL_LOHI.
235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240 // counterparts, which AArch64 supports directly.
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
247 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::SREM, MVT::i64, Expand);
253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::UREM, MVT::i32, Expand);
256 setOperationAction(ISD::UREM, MVT::i64, Expand);
258 // Custom lower Add/Sub/Mul with overflow.
259 setOperationAction(ISD::SADDO, MVT::i32, Custom);
260 setOperationAction(ISD::SADDO, MVT::i64, Custom);
261 setOperationAction(ISD::UADDO, MVT::i32, Custom);
262 setOperationAction(ISD::UADDO, MVT::i64, Custom);
263 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
265 setOperationAction(ISD::USUBO, MVT::i32, Custom);
266 setOperationAction(ISD::USUBO, MVT::i64, Custom);
267 setOperationAction(ISD::SMULO, MVT::i32, Custom);
268 setOperationAction(ISD::SMULO, MVT::i64, Custom);
269 setOperationAction(ISD::UMULO, MVT::i32, Custom);
270 setOperationAction(ISD::UMULO, MVT::i64, Custom);
272 setOperationAction(ISD::FSIN, MVT::f32, Expand);
273 setOperationAction(ISD::FSIN, MVT::f64, Expand);
274 setOperationAction(ISD::FCOS, MVT::f32, Expand);
275 setOperationAction(ISD::FCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FPOW, MVT::f32, Expand);
277 setOperationAction(ISD::FPOW, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
281 // AArch64 has implementations of a lot of rounding-like FP operations.
282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284 MVT Ty = RoundingTypes[I];
285 setOperationAction(ISD::FFLOOR, Ty, Legal);
286 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
287 setOperationAction(ISD::FCEIL, Ty, Legal);
288 setOperationAction(ISD::FRINT, Ty, Legal);
289 setOperationAction(ISD::FTRUNC, Ty, Legal);
290 setOperationAction(ISD::FROUND, Ty, Legal);
293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
295 if (Subtarget->isTargetMachO()) {
296 // For iOS, we don't want to the normal expansion of a libcall to
297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
306 // AArch64 does not have floating-point extending loads, i1 sign-extending
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
308 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
309 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
312 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
315 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
319 // Indexed loads and stores are supported.
320 for (unsigned im = (unsigned)ISD::PRE_INC;
321 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
322 setIndexedLoadAction(im, MVT::i8, Legal);
323 setIndexedLoadAction(im, MVT::i16, Legal);
324 setIndexedLoadAction(im, MVT::i32, Legal);
325 setIndexedLoadAction(im, MVT::i64, Legal);
326 setIndexedLoadAction(im, MVT::f64, Legal);
327 setIndexedLoadAction(im, MVT::f32, Legal);
328 setIndexedStoreAction(im, MVT::i8, Legal);
329 setIndexedStoreAction(im, MVT::i16, Legal);
330 setIndexedStoreAction(im, MVT::i32, Legal);
331 setIndexedStoreAction(im, MVT::i64, Legal);
332 setIndexedStoreAction(im, MVT::f64, Legal);
333 setIndexedStoreAction(im, MVT::f32, Legal);
337 setOperationAction(ISD::TRAP, MVT::Other, Legal);
339 // We combine OR nodes for bitfield operations.
340 setTargetDAGCombine(ISD::OR);
342 // Vector add and sub nodes may conceal a high-half opportunity.
343 // Also, try to fold ADD into CSINC/CSINV..
344 setTargetDAGCombine(ISD::ADD);
345 setTargetDAGCombine(ISD::SUB);
347 setTargetDAGCombine(ISD::XOR);
348 setTargetDAGCombine(ISD::SINT_TO_FP);
349 setTargetDAGCombine(ISD::UINT_TO_FP);
351 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
353 setTargetDAGCombine(ISD::ANY_EXTEND);
354 setTargetDAGCombine(ISD::ZERO_EXTEND);
355 setTargetDAGCombine(ISD::SIGN_EXTEND);
356 setTargetDAGCombine(ISD::BITCAST);
357 setTargetDAGCombine(ISD::CONCAT_VECTORS);
358 setTargetDAGCombine(ISD::STORE);
360 setTargetDAGCombine(ISD::MUL);
362 setTargetDAGCombine(ISD::SELECT);
363 setTargetDAGCombine(ISD::VSELECT);
365 setTargetDAGCombine(ISD::INTRINSIC_VOID);
366 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
367 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
369 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
370 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
371 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
373 setStackPointerRegisterToSaveRestore(AArch64::SP);
375 setSchedulingPreference(Sched::Hybrid);
378 MaskAndBranchFoldingIsLegal = true;
380 setMinFunctionAlignment(2);
382 RequireStrictAlign = (Align == StrictAlign);
384 setHasExtractBitsInsn(true);
386 if (Subtarget->hasNEON()) {
387 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
388 // silliness like this:
389 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
390 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
391 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
394 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
395 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
396 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
398 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
400 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
401 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
402 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
403 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
404 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
408 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
410 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
411 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
413 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
415 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
416 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
418 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
421 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
423 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
424 // elements smaller than i32, so promote the input to i32 first.
425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
426 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
429 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
430 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
431 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
435 // AArch64 doesn't have MUL.2d:
436 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
437 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
438 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
439 // Likewise, narrowing and extending vector loads/stores aren't handled
441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
442 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
444 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
447 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
448 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
452 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
454 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
455 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
456 setTruncStoreAction((MVT::SimpleValueType)VT,
457 (MVT::SimpleValueType)InnerVT, Expand);
458 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
463 // AArch64 has implementations of a lot of rounding-like FP operations.
464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
465 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
466 MVT Ty = RoundingVecTypes[I];
467 setOperationAction(ISD::FFLOOR, Ty, Legal);
468 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
469 setOperationAction(ISD::FCEIL, Ty, Legal);
470 setOperationAction(ISD::FRINT, Ty, Legal);
471 setOperationAction(ISD::FTRUNC, Ty, Legal);
472 setOperationAction(ISD::FROUND, Ty, Legal);
477 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
478 if (VT == MVT::v2f32) {
479 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
480 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
482 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
483 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
484 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
485 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
486 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
488 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
489 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
492 // Mark vector float intrinsics as expand.
493 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
494 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
495 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
506 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
518 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
519 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
521 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
523 // CNT supports only B element sizes.
524 if (VT != MVT::v8i8 && VT != MVT::v16i8)
525 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
527 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
533 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
534 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
536 if (Subtarget->isLittleEndian()) {
537 for (unsigned im = (unsigned)ISD::PRE_INC;
538 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
539 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
540 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
545 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
546 addRegisterClass(VT, &AArch64::FPR64RegClass);
547 addTypeForNEON(VT, MVT::v2i32);
550 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
551 addRegisterClass(VT, &AArch64::FPR128RegClass);
552 addTypeForNEON(VT, MVT::v4i32);
555 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
558 return VT.changeVectorElementTypeToInteger();
561 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
562 /// Mask are known to be either zero or one and return them in the
563 /// KnownZero/KnownOne bitsets.
564 void AArch64TargetLowering::computeKnownBitsForTargetNode(
565 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
566 const SelectionDAG &DAG, unsigned Depth) const {
567 switch (Op.getOpcode()) {
570 case AArch64ISD::CSEL: {
571 APInt KnownZero2, KnownOne2;
572 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
573 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
574 KnownZero &= KnownZero2;
575 KnownOne &= KnownOne2;
578 case ISD::INTRINSIC_W_CHAIN: {
579 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
580 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
583 case Intrinsic::aarch64_ldaxr:
584 case Intrinsic::aarch64_ldxr: {
585 unsigned BitWidth = KnownOne.getBitWidth();
586 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
587 unsigned MemBits = VT.getScalarType().getSizeInBits();
588 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
594 case ISD::INTRINSIC_WO_CHAIN:
595 case ISD::INTRINSIC_VOID: {
596 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
600 case Intrinsic::aarch64_neon_umaxv:
601 case Intrinsic::aarch64_neon_uminv: {
602 // Figure out the datatype of the vector operand. The UMINV instruction
603 // will zero extend the result, so we can mark as known zero all the
604 // bits larger than the element datatype. 32-bit or larget doesn't need
605 // this as those are legal types and will be handled by isel directly.
606 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
607 unsigned BitWidth = KnownZero.getBitWidth();
608 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
609 assert(BitWidth >= 8 && "Unexpected width!");
610 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
612 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
613 assert(BitWidth >= 16 && "Unexpected width!");
614 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
624 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
628 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
629 // FIXME: On AArch64, this depends on the type.
630 // Basically, the addressable offsets are o to 4095 * Ty.getSizeInBytes().
631 // and the offset has to be a multiple of the related size in bytes.
636 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
637 const TargetLibraryInfo *libInfo) const {
638 return AArch64::createFastISel(funcInfo, libInfo);
641 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
645 case AArch64ISD::CALL: return "AArch64ISD::CALL";
646 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
647 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
648 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
649 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
650 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
651 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
652 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
653 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
654 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
655 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
656 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
657 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
658 case AArch64ISD::ADC: return "AArch64ISD::ADC";
659 case AArch64ISD::SBC: return "AArch64ISD::SBC";
660 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
661 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
662 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
663 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
664 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
665 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
666 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
667 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
668 case AArch64ISD::DUP: return "AArch64ISD::DUP";
669 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
670 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
671 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
672 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
673 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
674 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
675 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
676 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
677 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
678 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
679 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
680 case AArch64ISD::BICi: return "AArch64ISD::BICi";
681 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
682 case AArch64ISD::BSL: return "AArch64ISD::BSL";
683 case AArch64ISD::NEG: return "AArch64ISD::NEG";
684 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
685 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
686 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
687 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
688 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
689 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
690 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
691 case AArch64ISD::REV16: return "AArch64ISD::REV16";
692 case AArch64ISD::REV32: return "AArch64ISD::REV32";
693 case AArch64ISD::REV64: return "AArch64ISD::REV64";
694 case AArch64ISD::EXT: return "AArch64ISD::EXT";
695 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
696 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
697 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
698 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
699 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
700 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
701 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
702 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
703 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
704 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
705 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
706 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
707 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
708 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
709 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
710 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
711 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
712 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
713 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
714 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
715 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
716 case AArch64ISD::NOT: return "AArch64ISD::NOT";
717 case AArch64ISD::BIT: return "AArch64ISD::BIT";
718 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
719 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
720 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
721 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
722 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
723 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
724 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
725 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
726 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
727 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
728 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
729 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
730 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
731 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
732 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
733 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
734 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
735 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
736 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
737 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
738 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
739 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
740 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
741 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
742 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
743 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
744 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
745 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
746 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
747 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
748 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
749 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
750 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
751 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
752 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
753 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
758 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
759 MachineBasicBlock *MBB) const {
760 // We materialise the F128CSEL pseudo-instruction as some control flow and a
764 // [... previous instrs leading to comparison ...]
770 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
772 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
773 MachineFunction *MF = MBB->getParent();
774 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
775 DebugLoc DL = MI->getDebugLoc();
776 MachineFunction::iterator It = MBB;
779 unsigned DestReg = MI->getOperand(0).getReg();
780 unsigned IfTrueReg = MI->getOperand(1).getReg();
781 unsigned IfFalseReg = MI->getOperand(2).getReg();
782 unsigned CondCode = MI->getOperand(3).getImm();
783 bool NZCVKilled = MI->getOperand(4).isKill();
785 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
786 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MF->insert(It, TrueBB);
788 MF->insert(It, EndBB);
790 // Transfer rest of current basic-block to EndBB
791 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
793 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
795 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
796 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
797 MBB->addSuccessor(TrueBB);
798 MBB->addSuccessor(EndBB);
800 // TrueBB falls through to the end.
801 TrueBB->addSuccessor(EndBB);
804 TrueBB->addLiveIn(AArch64::NZCV);
805 EndBB->addLiveIn(AArch64::NZCV);
808 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
814 MI->eraseFromParent();
819 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
820 MachineBasicBlock *BB) const {
821 switch (MI->getOpcode()) {
826 llvm_unreachable("Unexpected instruction for custom inserter!");
828 case AArch64::F128CSEL:
829 return EmitF128CSEL(MI, BB);
831 case TargetOpcode::STACKMAP:
832 case TargetOpcode::PATCHPOINT:
833 return emitPatchPoint(MI, BB);
837 //===----------------------------------------------------------------------===//
838 // AArch64 Lowering private implementation.
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
847 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
850 llvm_unreachable("Unknown condition code!");
852 return AArch64CC::NE;
854 return AArch64CC::EQ;
856 return AArch64CC::GT;
858 return AArch64CC::GE;
860 return AArch64CC::LT;
862 return AArch64CC::LE;
864 return AArch64CC::HI;
866 return AArch64CC::HS;
868 return AArch64CC::LO;
870 return AArch64CC::LS;
874 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
875 static void changeFPCCToAArch64CC(ISD::CondCode CC,
876 AArch64CC::CondCode &CondCode,
877 AArch64CC::CondCode &CondCode2) {
878 CondCode2 = AArch64CC::AL;
881 llvm_unreachable("Unknown FP condition!");
884 CondCode = AArch64CC::EQ;
888 CondCode = AArch64CC::GT;
892 CondCode = AArch64CC::GE;
895 CondCode = AArch64CC::MI;
898 CondCode = AArch64CC::LS;
901 CondCode = AArch64CC::MI;
902 CondCode2 = AArch64CC::GT;
905 CondCode = AArch64CC::VC;
908 CondCode = AArch64CC::VS;
911 CondCode = AArch64CC::EQ;
912 CondCode2 = AArch64CC::VS;
915 CondCode = AArch64CC::HI;
918 CondCode = AArch64CC::PL;
922 CondCode = AArch64CC::LT;
926 CondCode = AArch64CC::LE;
930 CondCode = AArch64CC::NE;
935 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
936 /// CC usable with the vector instructions. Fewer operations are available
937 /// without a real NZCV register, so we have to use less efficient combinations
938 /// to get the same effect.
939 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
940 AArch64CC::CondCode &CondCode,
941 AArch64CC::CondCode &CondCode2,
946 // Mostly the scalar mappings work fine.
947 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
950 Invert = true; // Fallthrough
952 CondCode = AArch64CC::MI;
953 CondCode2 = AArch64CC::GE;
960 // All of the compare-mask comparisons are ordered, but we can switch
961 // between the two by a double inversion. E.g. ULE == !OGT.
963 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
968 static bool isLegalArithImmed(uint64_t C) {
969 // Matches AArch64DAGToDAGISel::SelectArithImmed().
970 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
973 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
974 SDLoc dl, SelectionDAG &DAG) {
975 EVT VT = LHS.getValueType();
977 if (VT.isFloatingPoint())
978 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
980 // The CMP instruction is just an alias for SUBS, and representing it as
981 // SUBS means that it's possible to get CSE with subtract operations.
982 // A later phase can perform the optimization of setting the destination
983 // register to WZR/XZR if it ends up being unused.
984 unsigned Opcode = AArch64ISD::SUBS;
986 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
987 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
988 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
989 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
990 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
991 // can be set differently by this operation. It comes down to whether
992 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
993 // everything is fine. If not then the optimization is wrong. Thus general
994 // comparisons are only valid if op2 != 0.
996 // So, finally, the only LLVM-native comparisons that don't mention C and V
997 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
998 // the absence of information about op2.
999 Opcode = AArch64ISD::ADDS;
1000 RHS = RHS.getOperand(1);
1001 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1002 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1003 !isUnsignedIntSetCC(CC)) {
1004 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1005 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1006 // of the signed comparisons.
1007 Opcode = AArch64ISD::ANDS;
1008 RHS = LHS.getOperand(1);
1009 LHS = LHS.getOperand(0);
1012 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1016 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1017 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1018 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1019 EVT VT = RHS.getValueType();
1020 uint64_t C = RHSC->getZExtValue();
1021 if (!isLegalArithImmed(C)) {
1022 // Constant does not fit, try adjusting it by one?
1028 if ((VT == MVT::i32 && C != 0x80000000 &&
1029 isLegalArithImmed((uint32_t)(C - 1))) ||
1030 (VT == MVT::i64 && C != 0x80000000ULL &&
1031 isLegalArithImmed(C - 1ULL))) {
1032 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1033 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1034 RHS = DAG.getConstant(C, VT);
1039 if ((VT == MVT::i32 && C != 0 &&
1040 isLegalArithImmed((uint32_t)(C - 1))) ||
1041 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1042 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1043 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1044 RHS = DAG.getConstant(C, VT);
1049 if ((VT == MVT::i32 && C != 0x7fffffff &&
1050 isLegalArithImmed((uint32_t)(C + 1))) ||
1051 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1052 isLegalArithImmed(C + 1ULL))) {
1053 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1054 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1055 RHS = DAG.getConstant(C, VT);
1060 if ((VT == MVT::i32 && C != 0xffffffff &&
1061 isLegalArithImmed((uint32_t)(C + 1))) ||
1062 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1063 isLegalArithImmed(C + 1ULL))) {
1064 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1065 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1066 RHS = DAG.getConstant(C, VT);
1073 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1074 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1075 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1079 static std::pair<SDValue, SDValue>
1080 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1081 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1082 "Unsupported value type");
1083 SDValue Value, Overflow;
1085 SDValue LHS = Op.getOperand(0);
1086 SDValue RHS = Op.getOperand(1);
1088 switch (Op.getOpcode()) {
1090 llvm_unreachable("Unknown overflow instruction!");
1092 Opc = AArch64ISD::ADDS;
1096 Opc = AArch64ISD::ADDS;
1100 Opc = AArch64ISD::SUBS;
1104 Opc = AArch64ISD::SUBS;
1107 // Multiply needs a little bit extra work.
1111 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1112 if (Op.getValueType() == MVT::i32) {
1113 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1114 // For a 32 bit multiply with overflow check we want the instruction
1115 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1116 // need to generate the following pattern:
1117 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1118 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1119 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1120 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1121 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1122 DAG.getConstant(0, MVT::i64));
1123 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1124 // operation. We need to clear out the upper 32 bits, because we used a
1125 // widening multiply that wrote all 64 bits. In the end this should be a
1127 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1129 // The signed overflow check requires more than just a simple check for
1130 // any bit set in the upper 32 bits of the result. These bits could be
1131 // just the sign bits of a negative number. To perform the overflow
1132 // check we have to arithmetic shift right the 32nd bit of the result by
1133 // 31 bits. Then we compare the result to the upper 32 bits.
1134 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1135 DAG.getConstant(32, MVT::i64));
1136 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1137 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1138 DAG.getConstant(31, MVT::i64));
1139 // It is important that LowerBits is last, otherwise the arithmetic
1140 // shift will not be folded into the compare (SUBS).
1141 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1142 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1145 // The overflow check for unsigned multiply is easy. We only need to
1146 // check if any of the upper 32 bits are set. This can be done with a
1147 // CMP (shifted register). For that we need to generate the following
1149 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1150 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1151 DAG.getConstant(32, MVT::i64));
1152 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1154 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1155 UpperBits).getValue(1);
1159 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1160 // For the 64 bit multiply
1161 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1163 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1164 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1165 DAG.getConstant(63, MVT::i64));
1166 // It is important that LowerBits is last, otherwise the arithmetic
1167 // shift will not be folded into the compare (SUBS).
1168 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1169 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1172 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1173 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1175 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1176 UpperBits).getValue(1);
1183 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1185 // Emit the AArch64 operation with overflow check.
1186 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1187 Overflow = Value.getValue(1);
1189 return std::make_pair(Value, Overflow);
1192 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1193 RTLIB::Libcall Call) const {
1194 SmallVector<SDValue, 2> Ops;
1195 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1196 Ops.push_back(Op.getOperand(i));
1198 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1202 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1203 SDValue Sel = Op.getOperand(0);
1204 SDValue Other = Op.getOperand(1);
1206 // If neither operand is a SELECT_CC, give up.
1207 if (Sel.getOpcode() != ISD::SELECT_CC)
1208 std::swap(Sel, Other);
1209 if (Sel.getOpcode() != ISD::SELECT_CC)
1212 // The folding we want to perform is:
1213 // (xor x, (select_cc a, b, cc, 0, -1) )
1215 // (csel x, (xor x, -1), cc ...)
1217 // The latter will get matched to a CSINV instruction.
1219 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1220 SDValue LHS = Sel.getOperand(0);
1221 SDValue RHS = Sel.getOperand(1);
1222 SDValue TVal = Sel.getOperand(2);
1223 SDValue FVal = Sel.getOperand(3);
1226 // FIXME: This could be generalized to non-integer comparisons.
1227 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1230 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1231 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1233 // The the values aren't constants, this isn't the pattern we're looking for.
1234 if (!CFVal || !CTVal)
1237 // We can commute the SELECT_CC by inverting the condition. This
1238 // might be needed to make this fit into a CSINV pattern.
1239 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1240 std::swap(TVal, FVal);
1241 std::swap(CTVal, CFVal);
1242 CC = ISD::getSetCCInverse(CC, true);
1245 // If the constants line up, perform the transform!
1246 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1248 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1251 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1252 DAG.getConstant(-1ULL, Other.getValueType()));
1254 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1261 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1262 EVT VT = Op.getValueType();
1264 // Let legalize expand this if it isn't a legal type yet.
1265 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1268 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1271 bool ExtraOp = false;
1272 switch (Op.getOpcode()) {
1274 llvm_unreachable("Invalid code");
1276 Opc = AArch64ISD::ADDS;
1279 Opc = AArch64ISD::SUBS;
1282 Opc = AArch64ISD::ADCS;
1286 Opc = AArch64ISD::SBCS;
1292 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1293 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1297 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1298 // Let legalize expand this if it isn't a legal type yet.
1299 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1302 AArch64CC::CondCode CC;
1303 // The actual operation that sets the overflow or carry flag.
1304 SDValue Value, Overflow;
1305 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1307 // We use 0 and 1 as false and true values.
1308 SDValue TVal = DAG.getConstant(1, MVT::i32);
1309 SDValue FVal = DAG.getConstant(0, MVT::i32);
1311 // We use an inverted condition, because the conditional select is inverted
1312 // too. This will allow it to be selected to a single instruction:
1313 // CSINC Wd, WZR, WZR, invert(cond).
1314 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1315 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1318 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1319 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1322 // Prefetch operands are:
1323 // 1: Address to prefetch
1325 // 3: int locality (0 = no locality ... 3 = extreme locality)
1326 // 4: bool isDataCache
1327 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1329 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1330 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1331 // The data thing is not used.
1332 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1334 bool IsStream = !Locality;
1335 // When the locality number is set
1337 // The front-end should have filtered out the out-of-range values
1338 assert(Locality <= 3 && "Prefetch locality out-of-range");
1339 // The locality degree is the opposite of the cache speed.
1340 // Put the number the other way around.
1341 // The encoding starts at 0 for level 1
1342 Locality = 3 - Locality;
1345 // built the mask value encoding the expected behavior.
1346 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1347 (Locality << 1) | // Cache level bits
1348 (unsigned)IsStream; // Stream bit
1349 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1350 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1353 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1354 SelectionDAG &DAG) const {
1355 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1358 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1360 return LowerF128Call(Op, DAG, LC);
1363 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1364 SelectionDAG &DAG) const {
1365 if (Op.getOperand(0).getValueType() != MVT::f128) {
1366 // It's legal except when f128 is involved
1371 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1373 // FP_ROUND node has a second operand indicating whether it is known to be
1374 // precise. That doesn't take part in the LibCall so we can't directly use
1376 SDValue SrcVal = Op.getOperand(0);
1377 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1378 /*isSigned*/ false, SDLoc(Op)).first;
1381 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1382 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1383 // Any additional optimization in this function should be recorded
1384 // in the cost tables.
1385 EVT InVT = Op.getOperand(0).getValueType();
1386 EVT VT = Op.getValueType();
1388 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1391 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1393 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1396 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1398 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1399 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1402 // Type changing conversions are illegal.
1406 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1407 SelectionDAG &DAG) const {
1408 if (Op.getOperand(0).getValueType().isVector())
1409 return LowerVectorFP_TO_INT(Op, DAG);
1411 if (Op.getOperand(0).getValueType() != MVT::f128) {
1412 // It's legal except when f128 is involved
1417 if (Op.getOpcode() == ISD::FP_TO_SINT)
1418 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1420 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1422 SmallVector<SDValue, 2> Ops;
1423 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1424 Ops.push_back(Op.getOperand(i));
1426 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1430 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1431 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1432 // Any additional optimization in this function should be recorded
1433 // in the cost tables.
1434 EVT VT = Op.getValueType();
1436 SDValue In = Op.getOperand(0);
1437 EVT InVT = In.getValueType();
1439 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1441 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1442 InVT.getVectorNumElements());
1443 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1444 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1447 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1449 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1450 EVT CastVT = VT.changeVectorElementTypeToInteger();
1451 In = DAG.getNode(CastOpc, dl, CastVT, In);
1452 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1458 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1459 SelectionDAG &DAG) const {
1460 if (Op.getValueType().isVector())
1461 return LowerVectorINT_TO_FP(Op, DAG);
1463 // i128 conversions are libcalls.
1464 if (Op.getOperand(0).getValueType() == MVT::i128)
1467 // Other conversions are legal, unless it's to the completely software-based
1469 if (Op.getValueType() != MVT::f128)
1473 if (Op.getOpcode() == ISD::SINT_TO_FP)
1474 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1476 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1478 return LowerF128Call(Op, DAG, LC);
1481 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1482 SelectionDAG &DAG) const {
1483 // For iOS, we want to call an alternative entry point: __sincos_stret,
1484 // which returns the values in two S / D registers.
1486 SDValue Arg = Op.getOperand(0);
1487 EVT ArgVT = Arg.getValueType();
1488 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1495 Entry.isSExt = false;
1496 Entry.isZExt = false;
1497 Args.push_back(Entry);
1499 const char *LibcallName =
1500 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1501 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1503 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1504 TargetLowering::CallLoweringInfo CLI(DAG);
1505 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1506 .setCallee(CallingConv::Fast, RetTy, Callee, &Args, 0);
1508 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1509 return CallResult.first;
1512 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1513 SelectionDAG &DAG) const {
1514 switch (Op.getOpcode()) {
1516 llvm_unreachable("unimplemented operand");
1518 case ISD::GlobalAddress:
1519 return LowerGlobalAddress(Op, DAG);
1520 case ISD::GlobalTLSAddress:
1521 return LowerGlobalTLSAddress(Op, DAG);
1523 return LowerSETCC(Op, DAG);
1525 return LowerBR_CC(Op, DAG);
1527 return LowerSELECT(Op, DAG);
1528 case ISD::SELECT_CC:
1529 return LowerSELECT_CC(Op, DAG);
1530 case ISD::JumpTable:
1531 return LowerJumpTable(Op, DAG);
1532 case ISD::ConstantPool:
1533 return LowerConstantPool(Op, DAG);
1534 case ISD::BlockAddress:
1535 return LowerBlockAddress(Op, DAG);
1537 return LowerVASTART(Op, DAG);
1539 return LowerVACOPY(Op, DAG);
1541 return LowerVAARG(Op, DAG);
1546 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1553 return LowerXALUO(Op, DAG);
1555 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1557 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1559 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1561 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1563 return LowerFP_ROUND(Op, DAG);
1564 case ISD::FP_EXTEND:
1565 return LowerFP_EXTEND(Op, DAG);
1566 case ISD::FRAMEADDR:
1567 return LowerFRAMEADDR(Op, DAG);
1568 case ISD::RETURNADDR:
1569 return LowerRETURNADDR(Op, DAG);
1570 case ISD::INSERT_VECTOR_ELT:
1571 return LowerINSERT_VECTOR_ELT(Op, DAG);
1572 case ISD::EXTRACT_VECTOR_ELT:
1573 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1574 case ISD::BUILD_VECTOR:
1575 return LowerBUILD_VECTOR(Op, DAG);
1576 case ISD::VECTOR_SHUFFLE:
1577 return LowerVECTOR_SHUFFLE(Op, DAG);
1578 case ISD::EXTRACT_SUBVECTOR:
1579 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1583 return LowerVectorSRA_SRL_SHL(Op, DAG);
1584 case ISD::SHL_PARTS:
1585 return LowerShiftLeftParts(Op, DAG);
1586 case ISD::SRL_PARTS:
1587 case ISD::SRA_PARTS:
1588 return LowerShiftRightParts(Op, DAG);
1590 return LowerCTPOP(Op, DAG);
1591 case ISD::FCOPYSIGN:
1592 return LowerFCOPYSIGN(Op, DAG);
1594 return LowerVectorAND(Op, DAG);
1596 return LowerVectorOR(Op, DAG);
1598 return LowerXOR(Op, DAG);
1600 return LowerPREFETCH(Op, DAG);
1601 case ISD::SINT_TO_FP:
1602 case ISD::UINT_TO_FP:
1603 return LowerINT_TO_FP(Op, DAG);
1604 case ISD::FP_TO_SINT:
1605 case ISD::FP_TO_UINT:
1606 return LowerFP_TO_INT(Op, DAG);
1608 return LowerFSINCOS(Op, DAG);
1612 /// getFunctionAlignment - Return the Log2 alignment of this function.
1613 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1617 //===----------------------------------------------------------------------===//
1618 // Calling Convention Implementation
1619 //===----------------------------------------------------------------------===//
1621 #include "AArch64GenCallingConv.inc"
1623 /// Selects the correct CCAssignFn for a the given CallingConvention
1625 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1626 bool IsVarArg) const {
1629 llvm_unreachable("Unsupported calling convention.");
1630 case CallingConv::WebKit_JS:
1631 return CC_AArch64_WebKit_JS;
1632 case CallingConv::C:
1633 case CallingConv::Fast:
1634 if (!Subtarget->isTargetDarwin())
1635 return CC_AArch64_AAPCS;
1636 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1640 SDValue AArch64TargetLowering::LowerFormalArguments(
1641 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1642 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1643 SmallVectorImpl<SDValue> &InVals) const {
1644 MachineFunction &MF = DAG.getMachineFunction();
1645 MachineFrameInfo *MFI = MF.getFrameInfo();
1647 // Assign locations to all of the incoming arguments.
1648 SmallVector<CCValAssign, 16> ArgLocs;
1649 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1650 getTargetMachine(), ArgLocs, *DAG.getContext());
1652 // At this point, Ins[].VT may already be promoted to i32. To correctly
1653 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1654 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1655 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1656 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1658 unsigned NumArgs = Ins.size();
1659 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1660 unsigned CurArgIdx = 0;
1661 for (unsigned i = 0; i != NumArgs; ++i) {
1662 MVT ValVT = Ins[i].VT;
1663 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1664 CurArgIdx = Ins[i].OrigArgIndex;
1666 // Get type of the original argument.
1667 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1668 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1669 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1670 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1672 else if (ActualMVT == MVT::i16)
1675 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1677 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1678 assert(!Res && "Call operand has unhandled type");
1681 assert(ArgLocs.size() == Ins.size());
1682 SmallVector<SDValue, 16> ArgValues;
1683 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1684 CCValAssign &VA = ArgLocs[i];
1686 if (Ins[i].Flags.isByVal()) {
1687 // Byval is used for HFAs in the PCS, but the system should work in a
1688 // non-compliant manner for larger structs.
1689 EVT PtrTy = getPointerTy();
1690 int Size = Ins[i].Flags.getByValSize();
1691 unsigned NumRegs = (Size + 7) / 8;
1693 // FIXME: This works on big-endian for composite byvals, which are the common
1694 // case. It should also work for fundamental types too.
1696 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1697 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1698 InVals.push_back(FrameIdxN);
1703 if (VA.isRegLoc()) {
1704 // Arguments stored in registers.
1705 EVT RegVT = VA.getLocVT();
1708 const TargetRegisterClass *RC;
1710 if (RegVT == MVT::i32)
1711 RC = &AArch64::GPR32RegClass;
1712 else if (RegVT == MVT::i64)
1713 RC = &AArch64::GPR64RegClass;
1714 else if (RegVT == MVT::f32)
1715 RC = &AArch64::FPR32RegClass;
1716 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1717 RC = &AArch64::FPR64RegClass;
1718 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1719 RC = &AArch64::FPR128RegClass;
1721 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1723 // Transform the arguments in physical registers into virtual ones.
1724 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1725 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1727 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1728 // to 64 bits. Insert an assert[sz]ext to capture this, then
1729 // truncate to the right size.
1730 switch (VA.getLocInfo()) {
1732 llvm_unreachable("Unknown loc info!");
1733 case CCValAssign::Full:
1735 case CCValAssign::BCvt:
1736 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1738 case CCValAssign::AExt:
1739 case CCValAssign::SExt:
1740 case CCValAssign::ZExt:
1741 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1742 // nodes after our lowering.
1743 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1747 InVals.push_back(ArgValue);
1749 } else { // VA.isRegLoc()
1750 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1751 unsigned ArgOffset = VA.getLocMemOffset();
1752 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1754 uint32_t BEAlign = 0;
1755 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1756 BEAlign = 8 - ArgSize;
1758 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1760 // Create load nodes to retrieve arguments from the stack.
1761 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1764 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1765 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1766 MVT MemVT = VA.getValVT();
1768 switch (VA.getLocInfo()) {
1771 case CCValAssign::BCvt:
1772 MemVT = VA.getLocVT();
1774 case CCValAssign::SExt:
1775 ExtType = ISD::SEXTLOAD;
1777 case CCValAssign::ZExt:
1778 ExtType = ISD::ZEXTLOAD;
1780 case CCValAssign::AExt:
1781 ExtType = ISD::EXTLOAD;
1785 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1786 MachinePointerInfo::getFixedStack(FI),
1787 MemVT, false, false, false, nullptr);
1789 InVals.push_back(ArgValue);
1795 if (!Subtarget->isTargetDarwin()) {
1796 // The AAPCS variadic function ABI is identical to the non-variadic
1797 // one. As a result there may be more arguments in registers and we should
1798 // save them for future reference.
1799 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1802 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1803 // This will point to the next argument passed via stack.
1804 unsigned StackOffset = CCInfo.getNextStackOffset();
1805 // We currently pass all varargs at 8-byte alignment.
1806 StackOffset = ((StackOffset + 7) & ~7);
1807 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1810 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1811 unsigned StackArgSize = CCInfo.getNextStackOffset();
1812 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1813 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1814 // This is a non-standard ABI so by fiat I say we're allowed to make full
1815 // use of the stack area to be popped, which must be aligned to 16 bytes in
1817 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1819 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1820 // a multiple of 16.
1821 FuncInfo->setArgumentStackToRestore(StackArgSize);
1823 // This realignment carries over to the available bytes below. Our own
1824 // callers will guarantee the space is free by giving an aligned value to
1827 // Even if we're not expected to free up the space, it's useful to know how
1828 // much is there while considering tail calls (because we can reuse it).
1829 FuncInfo->setBytesInStackArgArea(StackArgSize);
1834 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1835 SelectionDAG &DAG, SDLoc DL,
1836 SDValue &Chain) const {
1837 MachineFunction &MF = DAG.getMachineFunction();
1838 MachineFrameInfo *MFI = MF.getFrameInfo();
1839 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1841 SmallVector<SDValue, 8> MemOps;
1843 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1844 AArch64::X3, AArch64::X4, AArch64::X5,
1845 AArch64::X6, AArch64::X7 };
1846 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1847 unsigned FirstVariadicGPR =
1848 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1850 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1852 if (GPRSaveSize != 0) {
1853 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1855 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1857 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1858 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1859 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1861 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1862 MachinePointerInfo::getStack(i * 8), false, false, 0);
1863 MemOps.push_back(Store);
1864 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1865 DAG.getConstant(8, getPointerTy()));
1868 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1869 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1871 if (Subtarget->hasFPARMv8()) {
1872 static const MCPhysReg FPRArgRegs[] = {
1873 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1874 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1875 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1876 unsigned FirstVariadicFPR =
1877 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1879 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1881 if (FPRSaveSize != 0) {
1882 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1884 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1886 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1887 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1888 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1891 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1892 MachinePointerInfo::getStack(i * 16), false, false, 0);
1893 MemOps.push_back(Store);
1894 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1895 DAG.getConstant(16, getPointerTy()));
1898 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1899 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1902 if (!MemOps.empty()) {
1903 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1907 /// LowerCallResult - Lower the result values of a call into the
1908 /// appropriate copies out of appropriate physical registers.
1909 SDValue AArch64TargetLowering::LowerCallResult(
1910 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1911 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1912 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1913 SDValue ThisVal) const {
1914 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1915 ? RetCC_AArch64_WebKit_JS
1916 : RetCC_AArch64_AAPCS;
1917 // Assign locations to each value returned by this call.
1918 SmallVector<CCValAssign, 16> RVLocs;
1919 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1920 getTargetMachine(), RVLocs, *DAG.getContext());
1921 CCInfo.AnalyzeCallResult(Ins, RetCC);
1923 // Copy all of the result registers out of their specified physreg.
1924 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1925 CCValAssign VA = RVLocs[i];
1927 // Pass 'this' value directly from the argument to return value, to avoid
1928 // reg unit interference
1929 if (i == 0 && isThisReturn) {
1930 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1931 "unexpected return calling convention register assignment");
1932 InVals.push_back(ThisVal);
1937 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1938 Chain = Val.getValue(1);
1939 InFlag = Val.getValue(2);
1941 switch (VA.getLocInfo()) {
1943 llvm_unreachable("Unknown loc info!");
1944 case CCValAssign::Full:
1946 case CCValAssign::BCvt:
1947 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1951 InVals.push_back(Val);
1957 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1958 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1959 bool isCalleeStructRet, bool isCallerStructRet,
1960 const SmallVectorImpl<ISD::OutputArg> &Outs,
1961 const SmallVectorImpl<SDValue> &OutVals,
1962 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1963 // For CallingConv::C this function knows whether the ABI needs
1964 // changing. That's not true for other conventions so they will have to opt in
1966 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1969 const MachineFunction &MF = DAG.getMachineFunction();
1970 const Function *CallerF = MF.getFunction();
1971 CallingConv::ID CallerCC = CallerF->getCallingConv();
1972 bool CCMatch = CallerCC == CalleeCC;
1974 // Byval parameters hand the function a pointer directly into the stack area
1975 // we want to reuse during a tail call. Working around this *is* possible (see
1976 // X86) but less efficient and uglier in LowerCall.
1977 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1978 e = CallerF->arg_end();
1980 if (i->hasByValAttr())
1983 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1984 if (IsTailCallConvention(CalleeCC) && CCMatch)
1989 // Now we search for cases where we can use a tail call without changing the
1990 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1993 // I want anyone implementing a new calling convention to think long and hard
1994 // about this assert.
1995 assert((!isVarArg || CalleeCC == CallingConv::C) &&
1996 "Unexpected variadic calling convention");
1998 if (isVarArg && !Outs.empty()) {
1999 // At least two cases here: if caller is fastcc then we can't have any
2000 // memory arguments (we'd be expected to clean up the stack afterwards). If
2001 // caller is C then we could potentially use its argument area.
2003 // FIXME: for now we take the most conservative of these in both cases:
2004 // disallow all variadic memory operands.
2005 SmallVector<CCValAssign, 16> ArgLocs;
2006 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2007 getTargetMachine(), ArgLocs, *DAG.getContext());
2009 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2010 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2011 if (!ArgLocs[i].isRegLoc())
2015 // If the calling conventions do not match, then we'd better make sure the
2016 // results are returned in the same way as what the caller expects.
2018 SmallVector<CCValAssign, 16> RVLocs1;
2019 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2020 getTargetMachine(), RVLocs1, *DAG.getContext());
2021 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2023 SmallVector<CCValAssign, 16> RVLocs2;
2024 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2025 getTargetMachine(), RVLocs2, *DAG.getContext());
2026 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2028 if (RVLocs1.size() != RVLocs2.size())
2030 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2031 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2033 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2035 if (RVLocs1[i].isRegLoc()) {
2036 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2039 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2045 // Nothing more to check if the callee is taking no arguments
2049 SmallVector<CCValAssign, 16> ArgLocs;
2050 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2051 getTargetMachine(), ArgLocs, *DAG.getContext());
2053 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2055 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2057 // If the stack arguments for this call would fit into our own save area then
2058 // the call can be made tail.
2059 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2062 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2064 MachineFrameInfo *MFI,
2065 int ClobberedFI) const {
2066 SmallVector<SDValue, 8> ArgChains;
2067 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2068 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2070 // Include the original chain at the beginning of the list. When this is
2071 // used by target LowerCall hooks, this helps legalize find the
2072 // CALLSEQ_BEGIN node.
2073 ArgChains.push_back(Chain);
2075 // Add a chain value for each stack argument corresponding
2076 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2077 UE = DAG.getEntryNode().getNode()->use_end();
2079 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2080 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2081 if (FI->getIndex() < 0) {
2082 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2083 int64_t InLastByte = InFirstByte;
2084 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2086 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2087 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2088 ArgChains.push_back(SDValue(L, 1));
2091 // Build a tokenfactor for all the chains.
2092 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2095 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2096 bool TailCallOpt) const {
2097 return CallCC == CallingConv::Fast && TailCallOpt;
2100 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2101 return CallCC == CallingConv::Fast;
2104 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2105 /// and add input and output parameter nodes.
2107 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2108 SmallVectorImpl<SDValue> &InVals) const {
2109 SelectionDAG &DAG = CLI.DAG;
2111 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2112 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2113 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2114 SDValue Chain = CLI.Chain;
2115 SDValue Callee = CLI.Callee;
2116 bool &IsTailCall = CLI.IsTailCall;
2117 CallingConv::ID CallConv = CLI.CallConv;
2118 bool IsVarArg = CLI.IsVarArg;
2120 MachineFunction &MF = DAG.getMachineFunction();
2121 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2122 bool IsThisReturn = false;
2124 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2125 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2126 bool IsSibCall = false;
2129 // Check if it's really possible to do a tail call.
2130 IsTailCall = isEligibleForTailCallOptimization(
2131 Callee, CallConv, IsVarArg, IsStructRet,
2132 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2133 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2134 report_fatal_error("failed to perform tail call elimination on a call "
2135 "site marked musttail");
2137 // A sibling call is one where we're under the usual C ABI and not planning
2138 // to change that but can still do a tail call:
2139 if (!TailCallOpt && IsTailCall)
2146 // Analyze operands of the call, assigning locations to each operand.
2147 SmallVector<CCValAssign, 16> ArgLocs;
2148 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2149 getTargetMachine(), ArgLocs, *DAG.getContext());
2152 // Handle fixed and variable vector arguments differently.
2153 // Variable vector arguments always go into memory.
2154 unsigned NumArgs = Outs.size();
2156 for (unsigned i = 0; i != NumArgs; ++i) {
2157 MVT ArgVT = Outs[i].VT;
2158 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2159 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2160 /*IsVarArg=*/ !Outs[i].IsFixed);
2161 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2162 assert(!Res && "Call operand has unhandled type");
2166 // At this point, Outs[].VT may already be promoted to i32. To correctly
2167 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2168 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2169 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2170 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2172 unsigned NumArgs = Outs.size();
2173 for (unsigned i = 0; i != NumArgs; ++i) {
2174 MVT ValVT = Outs[i].VT;
2175 // Get type of the original argument.
2176 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2177 /*AllowUnknown*/ true);
2178 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2179 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2180 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2181 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2183 else if (ActualMVT == MVT::i16)
2186 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2187 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2188 assert(!Res && "Call operand has unhandled type");
2193 // Get a count of how many bytes are to be pushed on the stack.
2194 unsigned NumBytes = CCInfo.getNextStackOffset();
2197 // Since we're not changing the ABI to make this a tail call, the memory
2198 // operands are already available in the caller's incoming argument space.
2202 // FPDiff is the byte offset of the call's argument area from the callee's.
2203 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2204 // by this amount for a tail call. In a sibling call it must be 0 because the
2205 // caller will deallocate the entire stack and the callee still expects its
2206 // arguments to begin at SP+0. Completely unused for non-tail calls.
2209 if (IsTailCall && !IsSibCall) {
2210 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2212 // Since callee will pop argument stack as a tail call, we must keep the
2213 // popped size 16-byte aligned.
2214 NumBytes = RoundUpToAlignment(NumBytes, 16);
2216 // FPDiff will be negative if this tail call requires more space than we
2217 // would automatically have in our incoming argument space. Positive if we
2218 // can actually shrink the stack.
2219 FPDiff = NumReusableBytes - NumBytes;
2221 // The stack pointer must be 16-byte aligned at all times it's used for a
2222 // memory operation, which in practice means at *all* times and in
2223 // particular across call boundaries. Therefore our own arguments started at
2224 // a 16-byte aligned SP and the delta applied for the tail call should
2225 // satisfy the same constraint.
2226 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2229 // Adjust the stack pointer for the new arguments...
2230 // These operations are automatically eliminated by the prolog/epilog pass
2233 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2235 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2237 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2238 SmallVector<SDValue, 8> MemOpChains;
2240 // Walk the register/memloc assignments, inserting copies/loads.
2241 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2242 ++i, ++realArgIdx) {
2243 CCValAssign &VA = ArgLocs[i];
2244 SDValue Arg = OutVals[realArgIdx];
2245 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2247 // Promote the value if needed.
2248 switch (VA.getLocInfo()) {
2250 llvm_unreachable("Unknown loc info!");
2251 case CCValAssign::Full:
2253 case CCValAssign::SExt:
2254 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2256 case CCValAssign::ZExt:
2257 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2259 case CCValAssign::AExt:
2260 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2261 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2262 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2263 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2265 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2267 case CCValAssign::BCvt:
2268 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2270 case CCValAssign::FPExt:
2271 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2275 if (VA.isRegLoc()) {
2276 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2277 assert(VA.getLocVT() == MVT::i64 &&
2278 "unexpected calling convention register assignment");
2279 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2280 "unexpected use of 'returned'");
2281 IsThisReturn = true;
2283 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2285 assert(VA.isMemLoc());
2288 MachinePointerInfo DstInfo;
2290 // FIXME: This works on big-endian for composite byvals, which are the
2291 // common case. It should also work for fundamental types too.
2292 uint32_t BEAlign = 0;
2293 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2294 : VA.getLocVT().getSizeInBits();
2295 OpSize = (OpSize + 7) / 8;
2296 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2298 BEAlign = 8 - OpSize;
2300 unsigned LocMemOffset = VA.getLocMemOffset();
2301 int32_t Offset = LocMemOffset + BEAlign;
2302 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2303 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2306 Offset = Offset + FPDiff;
2307 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2309 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2310 DstInfo = MachinePointerInfo::getFixedStack(FI);
2312 // Make sure any stack arguments overlapping with where we're storing
2313 // are loaded before this eventual operation. Otherwise they'll be
2315 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2317 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2319 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2320 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2323 if (Outs[i].Flags.isByVal()) {
2325 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2326 SDValue Cpy = DAG.getMemcpy(
2327 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2328 /*isVolatile = */ false,
2329 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2331 MemOpChains.push_back(Cpy);
2333 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2334 // promoted to a legal register type i32, we should truncate Arg back to
2336 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2337 VA.getValVT() == MVT::i16)
2338 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2341 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2342 MemOpChains.push_back(Store);
2347 if (!MemOpChains.empty())
2348 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2350 // Build a sequence of copy-to-reg nodes chained together with token chain
2351 // and flag operands which copy the outgoing args into the appropriate regs.
2353 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2354 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2355 RegsToPass[i].second, InFlag);
2356 InFlag = Chain.getValue(1);
2359 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2360 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2361 // node so that legalize doesn't hack it.
2362 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2363 Subtarget->isTargetMachO()) {
2364 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2365 const GlobalValue *GV = G->getGlobal();
2366 bool InternalLinkage = GV->hasInternalLinkage();
2367 if (InternalLinkage)
2368 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2370 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2372 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2374 } else if (ExternalSymbolSDNode *S =
2375 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2376 const char *Sym = S->getSymbol();
2378 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2379 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2381 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2382 const GlobalValue *GV = G->getGlobal();
2383 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2384 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2385 const char *Sym = S->getSymbol();
2386 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2389 // We don't usually want to end the call-sequence here because we would tidy
2390 // the frame up *after* the call, however in the ABI-changing tail-call case
2391 // we've carefully laid out the parameters so that when sp is reset they'll be
2392 // in the correct location.
2393 if (IsTailCall && !IsSibCall) {
2394 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2395 DAG.getIntPtrConstant(0, true), InFlag, DL);
2396 InFlag = Chain.getValue(1);
2399 std::vector<SDValue> Ops;
2400 Ops.push_back(Chain);
2401 Ops.push_back(Callee);
2404 // Each tail call may have to adjust the stack by a different amount, so
2405 // this information must travel along with the operation for eventual
2406 // consumption by emitEpilogue.
2407 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2410 // Add argument registers to the end of the list so that they are known live
2412 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2413 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2414 RegsToPass[i].second.getValueType()));
2416 // Add a register mask operand representing the call-preserved registers.
2417 const uint32_t *Mask;
2418 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2419 const AArch64RegisterInfo *ARI =
2420 static_cast<const AArch64RegisterInfo *>(TRI);
2422 // For 'this' returns, use the X0-preserving mask if applicable
2423 Mask = ARI->getThisReturnPreservedMask(CallConv);
2425 IsThisReturn = false;
2426 Mask = ARI->getCallPreservedMask(CallConv);
2429 Mask = ARI->getCallPreservedMask(CallConv);
2431 assert(Mask && "Missing call preserved mask for calling convention");
2432 Ops.push_back(DAG.getRegisterMask(Mask));
2434 if (InFlag.getNode())
2435 Ops.push_back(InFlag);
2437 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2439 // If we're doing a tall call, use a TC_RETURN here rather than an
2440 // actual call instruction.
2442 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2444 // Returns a chain and a flag for retval copy to use.
2445 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2446 InFlag = Chain.getValue(1);
2448 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2449 ? RoundUpToAlignment(NumBytes, 16)
2452 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2453 DAG.getIntPtrConstant(CalleePopBytes, true),
2456 InFlag = Chain.getValue(1);
2458 // Handle result values, copying them out of physregs into vregs that we
2460 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2461 InVals, IsThisReturn,
2462 IsThisReturn ? OutVals[0] : SDValue());
2465 bool AArch64TargetLowering::CanLowerReturn(
2466 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2467 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2468 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2469 ? RetCC_AArch64_WebKit_JS
2470 : RetCC_AArch64_AAPCS;
2471 SmallVector<CCValAssign, 16> RVLocs;
2472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2473 return CCInfo.CheckReturn(Outs, RetCC);
2477 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2479 const SmallVectorImpl<ISD::OutputArg> &Outs,
2480 const SmallVectorImpl<SDValue> &OutVals,
2481 SDLoc DL, SelectionDAG &DAG) const {
2482 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2483 ? RetCC_AArch64_WebKit_JS
2484 : RetCC_AArch64_AAPCS;
2485 SmallVector<CCValAssign, 16> RVLocs;
2486 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2487 getTargetMachine(), RVLocs, *DAG.getContext());
2488 CCInfo.AnalyzeReturn(Outs, RetCC);
2490 // Copy the result values into the output registers.
2492 SmallVector<SDValue, 4> RetOps(1, Chain);
2493 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2494 ++i, ++realRVLocIdx) {
2495 CCValAssign &VA = RVLocs[i];
2496 assert(VA.isRegLoc() && "Can only return in registers!");
2497 SDValue Arg = OutVals[realRVLocIdx];
2499 switch (VA.getLocInfo()) {
2501 llvm_unreachable("Unknown loc info!");
2502 case CCValAssign::Full:
2503 if (Outs[i].ArgVT == MVT::i1) {
2504 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2505 // value. This is strictly redundant on Darwin (which uses "zeroext
2506 // i1"), but will be optimised out before ISel.
2507 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2508 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2511 case CCValAssign::BCvt:
2512 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2516 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2517 Flag = Chain.getValue(1);
2518 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2521 RetOps[0] = Chain; // Update chain.
2523 // Add the flag if we have it.
2525 RetOps.push_back(Flag);
2527 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2530 //===----------------------------------------------------------------------===//
2531 // Other Lowering Code
2532 //===----------------------------------------------------------------------===//
2534 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2535 SelectionDAG &DAG) const {
2536 EVT PtrVT = getPointerTy();
2538 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2539 unsigned char OpFlags =
2540 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2542 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2543 "unexpected offset in global node");
2545 // This also catched the large code model case for Darwin.
2546 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2547 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2548 // FIXME: Once remat is capable of dealing with instructions with register
2549 // operands, expand this into two nodes instead of using a wrapper node.
2550 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2553 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2554 const unsigned char MO_NC = AArch64II::MO_NC;
2556 AArch64ISD::WrapperLarge, DL, PtrVT,
2557 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2558 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2559 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2560 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2562 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2563 // the only correct model on Darwin.
2564 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2565 OpFlags | AArch64II::MO_PAGE);
2566 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2567 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2569 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2570 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2574 /// \brief Convert a TLS address reference into the correct sequence of loads
2575 /// and calls to compute the variable's address (for Darwin, currently) and
2576 /// return an SDValue containing the final node.
2578 /// Darwin only has one TLS scheme which must be capable of dealing with the
2579 /// fully general situation, in the worst case. This means:
2580 /// + "extern __thread" declaration.
2581 /// + Defined in a possibly unknown dynamic library.
2583 /// The general system is that each __thread variable has a [3 x i64] descriptor
2584 /// which contains information used by the runtime to calculate the address. The
2585 /// only part of this the compiler needs to know about is the first xword, which
2586 /// contains a function pointer that must be called with the address of the
2587 /// entire descriptor in "x0".
2589 /// Since this descriptor may be in a different unit, in general even the
2590 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2592 /// adrp x0, _var@TLVPPAGE
2593 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2594 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2595 /// ; the function pointer
2596 /// blr x1 ; Uses descriptor address in x0
2597 /// ; Address of _var is now in x0.
2599 /// If the address of _var's descriptor *is* known to the linker, then it can
2600 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2601 /// a slight efficiency gain.
2603 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2604 SelectionDAG &DAG) const {
2605 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2608 MVT PtrVT = getPointerTy();
2609 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2612 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2613 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2615 // The first entry in the descriptor is a function pointer that we must call
2616 // to obtain the address of the variable.
2617 SDValue Chain = DAG.getEntryNode();
2618 SDValue FuncTLVGet =
2619 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2620 false, true, true, 8);
2621 Chain = FuncTLVGet.getValue(1);
2623 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2624 MFI->setAdjustsStack(true);
2626 // TLS calls preserve all registers except those that absolutely must be
2627 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2629 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2630 const AArch64RegisterInfo *ARI =
2631 static_cast<const AArch64RegisterInfo *>(TRI);
2632 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2634 // Finally, we can make the call. This is just a degenerate version of a
2635 // normal AArch64 call node: x0 takes the address of the descriptor, and
2636 // returns the address of the variable in this thread.
2637 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2639 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2640 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2641 DAG.getRegisterMask(Mask), Chain.getValue(1));
2642 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2645 /// When accessing thread-local variables under either the general-dynamic or
2646 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2647 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2648 /// is a function pointer to carry out the resolution. This function takes the
2649 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2650 /// other registers (except LR, NZCV) are preserved.
2652 /// Thus, the ideal call sequence on AArch64 is:
2654 /// adrp x0, :tlsdesc:thread_var
2655 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2656 /// add x0, x0, :tlsdesc_lo12:thread_var
2657 /// .tlsdesccall thread_var
2659 /// (TPIDR_EL0 offset now in x0).
2661 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2662 /// relocation to help the linker relax this sequence if it turns out to be too
2665 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2667 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2668 SDValue DescAddr, SDLoc DL,
2669 SelectionDAG &DAG) const {
2670 EVT PtrVT = getPointerTy();
2672 // The function we need to call is simply the first entry in the GOT for this
2673 // descriptor, load it in preparation.
2674 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2676 // TLS calls preserve all registers except those that absolutely must be
2677 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2679 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2680 const AArch64RegisterInfo *ARI =
2681 static_cast<const AArch64RegisterInfo *>(TRI);
2682 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2684 // The function takes only one argument: the address of the descriptor itself
2686 SDValue Glue, Chain;
2687 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2688 Glue = Chain.getValue(1);
2690 // We're now ready to populate the argument list, as with a normal call:
2691 SmallVector<SDValue, 6> Ops;
2692 Ops.push_back(Chain);
2693 Ops.push_back(Func);
2694 Ops.push_back(SymAddr);
2695 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2696 Ops.push_back(DAG.getRegisterMask(Mask));
2697 Ops.push_back(Glue);
2699 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2700 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2701 Glue = Chain.getValue(1);
2703 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2707 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2708 SelectionDAG &DAG) const {
2709 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2710 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2711 "ELF TLS only supported in small memory model");
2712 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2714 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2717 EVT PtrVT = getPointerTy();
2719 const GlobalValue *GV = GA->getGlobal();
2721 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2723 if (Model == TLSModel::LocalExec) {
2724 SDValue HiVar = DAG.getTargetGlobalAddress(
2725 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2726 SDValue LoVar = DAG.getTargetGlobalAddress(
2728 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2730 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2731 DAG.getTargetConstant(16, MVT::i32)),
2733 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2734 DAG.getTargetConstant(0, MVT::i32)),
2736 } else if (Model == TLSModel::InitialExec) {
2737 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2738 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2739 } else if (Model == TLSModel::LocalDynamic) {
2740 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2741 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2742 // the beginning of the module's TLS region, followed by a DTPREL offset
2745 // These accesses will need deduplicating if there's more than one.
2746 AArch64FunctionInfo *MFI =
2747 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2748 MFI->incNumLocalDynamicTLSAccesses();
2750 // Accesses used in this sequence go via the TLS descriptor which lives in
2751 // the GOT. Prepare an address we can use to handle this.
2752 SDValue HiDesc = DAG.getTargetExternalSymbol(
2753 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2754 SDValue LoDesc = DAG.getTargetExternalSymbol(
2755 "_TLS_MODULE_BASE_", PtrVT,
2756 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2758 // First argument to the descriptor call is the address of the descriptor
2760 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2761 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2763 // The call needs a relocation too for linker relaxation. It doesn't make
2764 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2766 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2769 // Now we can calculate the offset from TPIDR_EL0 to this module's
2770 // thread-local area.
2771 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2773 // Now use :dtprel_whatever: operations to calculate this variable's offset
2774 // in its thread-storage area.
2775 SDValue HiVar = DAG.getTargetGlobalAddress(
2776 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2777 SDValue LoVar = DAG.getTargetGlobalAddress(
2778 GV, DL, MVT::i64, 0,
2779 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2782 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2783 DAG.getTargetConstant(16, MVT::i32)),
2786 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2787 DAG.getTargetConstant(0, MVT::i32)),
2790 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2791 } else if (Model == TLSModel::GeneralDynamic) {
2792 // Accesses used in this sequence go via the TLS descriptor which lives in
2793 // the GOT. Prepare an address we can use to handle this.
2794 SDValue HiDesc = DAG.getTargetGlobalAddress(
2795 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2796 SDValue LoDesc = DAG.getTargetGlobalAddress(
2798 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2800 // First argument to the descriptor call is the address of the descriptor
2802 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2803 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2805 // The call needs a relocation too for linker relaxation. It doesn't make
2806 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2809 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2811 // Finally we can make a call to calculate the offset from tpidr_el0.
2812 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2814 llvm_unreachable("Unsupported ELF TLS access model");
2816 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2819 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2820 SelectionDAG &DAG) const {
2821 if (Subtarget->isTargetDarwin())
2822 return LowerDarwinGlobalTLSAddress(Op, DAG);
2823 else if (Subtarget->isTargetELF())
2824 return LowerELFGlobalTLSAddress(Op, DAG);
2826 llvm_unreachable("Unexpected platform trying to use TLS");
2828 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2829 SDValue Chain = Op.getOperand(0);
2830 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2831 SDValue LHS = Op.getOperand(2);
2832 SDValue RHS = Op.getOperand(3);
2833 SDValue Dest = Op.getOperand(4);
2836 // Handle f128 first, since lowering it will result in comparing the return
2837 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2838 // is expecting to deal with.
2839 if (LHS.getValueType() == MVT::f128) {
2840 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2842 // If softenSetCCOperands returned a scalar, we need to compare the result
2843 // against zero to select between true and false values.
2844 if (!RHS.getNode()) {
2845 RHS = DAG.getConstant(0, LHS.getValueType());
2850 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2852 unsigned Opc = LHS.getOpcode();
2853 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2854 cast<ConstantSDNode>(RHS)->isOne() &&
2855 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2856 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2857 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2858 "Unexpected condition code.");
2859 // Only lower legal XALUO ops.
2860 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2863 // The actual operation with overflow check.
2864 AArch64CC::CondCode OFCC;
2865 SDValue Value, Overflow;
2866 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2868 if (CC == ISD::SETNE)
2869 OFCC = getInvertedCondCode(OFCC);
2870 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2872 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2876 if (LHS.getValueType().isInteger()) {
2877 assert((LHS.getValueType() == RHS.getValueType()) &&
2878 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2880 // If the RHS of the comparison is zero, we can potentially fold this
2881 // to a specialized branch.
2882 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2883 if (RHSC && RHSC->getZExtValue() == 0) {
2884 if (CC == ISD::SETEQ) {
2885 // See if we can use a TBZ to fold in an AND as well.
2886 // TBZ has a smaller branch displacement than CBZ. If the offset is
2887 // out of bounds, a late MI-layer pass rewrites branches.
2888 // 403.gcc is an example that hits this case.
2889 if (LHS.getOpcode() == ISD::AND &&
2890 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2891 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2892 SDValue Test = LHS.getOperand(0);
2893 uint64_t Mask = LHS.getConstantOperandVal(1);
2895 // TBZ only operates on i64's, but the ext should be free.
2896 if (Test.getValueType() == MVT::i32)
2897 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2899 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2900 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2903 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2904 } else if (CC == ISD::SETNE) {
2905 // See if we can use a TBZ to fold in an AND as well.
2906 // TBZ has a smaller branch displacement than CBZ. If the offset is
2907 // out of bounds, a late MI-layer pass rewrites branches.
2908 // 403.gcc is an example that hits this case.
2909 if (LHS.getOpcode() == ISD::AND &&
2910 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2911 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2912 SDValue Test = LHS.getOperand(0);
2913 uint64_t Mask = LHS.getConstantOperandVal(1);
2915 // TBNZ only operates on i64's, but the ext should be free.
2916 if (Test.getValueType() == MVT::i32)
2917 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2919 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2920 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2923 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2928 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2929 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2933 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2935 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2936 // clean. Some of them require two branches to implement.
2937 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2938 AArch64CC::CondCode CC1, CC2;
2939 changeFPCCToAArch64CC(CC, CC1, CC2);
2940 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2942 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2943 if (CC2 != AArch64CC::AL) {
2944 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2945 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2952 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2953 SelectionDAG &DAG) const {
2954 EVT VT = Op.getValueType();
2957 SDValue In1 = Op.getOperand(0);
2958 SDValue In2 = Op.getOperand(1);
2959 EVT SrcVT = In2.getValueType();
2961 if (SrcVT == MVT::f32 && VT == MVT::f64)
2962 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2963 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2964 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2966 // FIXME: Src type is different, bail out for now. Can VT really be a
2973 SDValue EltMask, VecVal1, VecVal2;
2974 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2977 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2979 if (!VT.isVector()) {
2980 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2981 DAG.getUNDEF(VecVT), In1);
2982 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2983 DAG.getUNDEF(VecVT), In2);
2985 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2986 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2988 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
2992 // We want to materialize a mask with the the high bit set, but the AdvSIMD
2993 // immediate moves cannot materialize that in a single instruction for
2994 // 64-bit elements. Instead, materialize zero and then negate it.
2995 EltMask = DAG.getConstant(0, EltVT);
2997 if (!VT.isVector()) {
2998 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
2999 DAG.getUNDEF(VecVT), In1);
3000 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3001 DAG.getUNDEF(VecVT), In2);
3003 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3004 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3007 llvm_unreachable("Invalid type for copysign!");
3010 std::vector<SDValue> BuildVectorOps;
3011 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3012 BuildVectorOps.push_back(EltMask);
3014 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3016 // If we couldn't materialize the mask above, then the mask vector will be
3017 // the zero vector, and we need to negate it here.
3018 if (VT == MVT::f64 || VT == MVT::v2f64) {
3019 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3020 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3021 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3025 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3028 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3029 else if (VT == MVT::f64)
3030 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3032 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3035 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3036 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3037 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3040 // While there is no integer popcount instruction, it can
3041 // be more efficiently lowered to the following sequence that uses
3042 // AdvSIMD registers/instructions as long as the copies to/from
3043 // the AdvSIMD registers are cheap.
3044 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3045 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3046 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3047 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3048 SDValue Val = Op.getOperand(0);
3050 EVT VT = Op.getValueType();
3051 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3054 if (VT == MVT::i32) {
3055 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3056 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3059 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3062 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3063 SDValue UaddLV = DAG.getNode(
3064 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3065 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3068 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3072 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3074 if (Op.getValueType().isVector())
3075 return LowerVSETCC(Op, DAG);
3077 SDValue LHS = Op.getOperand(0);
3078 SDValue RHS = Op.getOperand(1);
3079 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3082 // We chose ZeroOrOneBooleanContents, so use zero and one.
3083 EVT VT = Op.getValueType();
3084 SDValue TVal = DAG.getConstant(1, VT);
3085 SDValue FVal = DAG.getConstant(0, VT);
3087 // Handle f128 first, since one possible outcome is a normal integer
3088 // comparison which gets picked up by the next if statement.
3089 if (LHS.getValueType() == MVT::f128) {
3090 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3092 // If softenSetCCOperands returned a scalar, use it.
3093 if (!RHS.getNode()) {
3094 assert(LHS.getValueType() == Op.getValueType() &&
3095 "Unexpected setcc expansion!");
3100 if (LHS.getValueType().isInteger()) {
3103 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3105 // Note that we inverted the condition above, so we reverse the order of
3106 // the true and false operands here. This will allow the setcc to be
3107 // matched to a single CSINC instruction.
3108 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3111 // Now we know we're dealing with FP values.
3112 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3114 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3115 // and do the comparison.
3116 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3118 AArch64CC::CondCode CC1, CC2;
3119 changeFPCCToAArch64CC(CC, CC1, CC2);
3120 if (CC2 == AArch64CC::AL) {
3121 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3122 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3124 // Note that we inverted the condition above, so we reverse the order of
3125 // the true and false operands here. This will allow the setcc to be
3126 // matched to a single CSINC instruction.
3127 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3129 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3130 // totally clean. Some of them require two CSELs to implement. As is in
3131 // this case, we emit the first CSEL and then emit a second using the output
3132 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3134 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3135 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3137 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3139 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3140 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3144 /// A SELECT_CC operation is really some kind of max or min if both values being
3145 /// compared are, in some sense, equal to the results in either case. However,
3146 /// it is permissible to compare f32 values and produce directly extended f64
3149 /// Extending the comparison operands would also be allowed, but is less likely
3150 /// to happen in practice since their use is right here. Note that truncate
3151 /// operations would *not* be semantically equivalent.
3152 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3156 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3157 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3158 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3159 Result.getValueType() == MVT::f64) {
3161 APFloat CmpVal = CCmp->getValueAPF();
3162 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3163 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3166 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3169 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3170 SelectionDAG &DAG) const {
3171 SDValue CC = Op->getOperand(0);
3172 SDValue TVal = Op->getOperand(1);
3173 SDValue FVal = Op->getOperand(2);
3176 unsigned Opc = CC.getOpcode();
3177 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3179 if (CC.getResNo() == 1 &&
3180 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3181 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3182 // Only lower legal XALUO ops.
3183 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3186 AArch64CC::CondCode OFCC;
3187 SDValue Value, Overflow;
3188 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3189 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3191 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3195 if (CC.getOpcode() == ISD::SETCC)
3196 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3197 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3199 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3203 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3204 SelectionDAG &DAG) const {
3205 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3206 SDValue LHS = Op.getOperand(0);
3207 SDValue RHS = Op.getOperand(1);
3208 SDValue TVal = Op.getOperand(2);
3209 SDValue FVal = Op.getOperand(3);
3212 // Handle f128 first, because it will result in a comparison of some RTLIB
3213 // call result against zero.
3214 if (LHS.getValueType() == MVT::f128) {
3215 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3217 // If softenSetCCOperands returned a scalar, we need to compare the result
3218 // against zero to select between true and false values.
3219 if (!RHS.getNode()) {
3220 RHS = DAG.getConstant(0, LHS.getValueType());
3225 // Handle integers first.
3226 if (LHS.getValueType().isInteger()) {
3227 assert((LHS.getValueType() == RHS.getValueType()) &&
3228 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3230 unsigned Opcode = AArch64ISD::CSEL;
3232 // If both the TVal and the FVal are constants, see if we can swap them in
3233 // order to for a CSINV or CSINC out of them.
3234 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3235 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3237 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3238 std::swap(TVal, FVal);
3239 std::swap(CTVal, CFVal);
3240 CC = ISD::getSetCCInverse(CC, true);
3241 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3242 std::swap(TVal, FVal);
3243 std::swap(CTVal, CFVal);
3244 CC = ISD::getSetCCInverse(CC, true);
3245 } else if (TVal.getOpcode() == ISD::XOR) {
3246 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3247 // with a CSINV rather than a CSEL.
3248 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3250 if (CVal && CVal->isAllOnesValue()) {
3251 std::swap(TVal, FVal);
3252 std::swap(CTVal, CFVal);
3253 CC = ISD::getSetCCInverse(CC, true);
3255 } else if (TVal.getOpcode() == ISD::SUB) {
3256 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3257 // that we can match with a CSNEG rather than a CSEL.
3258 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3260 if (CVal && CVal->isNullValue()) {
3261 std::swap(TVal, FVal);
3262 std::swap(CTVal, CFVal);
3263 CC = ISD::getSetCCInverse(CC, true);
3265 } else if (CTVal && CFVal) {
3266 const int64_t TrueVal = CTVal->getSExtValue();
3267 const int64_t FalseVal = CFVal->getSExtValue();
3270 // If both TVal and FVal are constants, see if FVal is the
3271 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3272 // instead of a CSEL in that case.
3273 if (TrueVal == ~FalseVal) {
3274 Opcode = AArch64ISD::CSINV;
3275 } else if (TrueVal == -FalseVal) {
3276 Opcode = AArch64ISD::CSNEG;
3277 } else if (TVal.getValueType() == MVT::i32) {
3278 // If our operands are only 32-bit wide, make sure we use 32-bit
3279 // arithmetic for the check whether we can use CSINC. This ensures that
3280 // the addition in the check will wrap around properly in case there is
3281 // an overflow (which would not be the case if we do the check with
3282 // 64-bit arithmetic).
3283 const uint32_t TrueVal32 = CTVal->getZExtValue();
3284 const uint32_t FalseVal32 = CFVal->getZExtValue();
3286 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3287 Opcode = AArch64ISD::CSINC;
3289 if (TrueVal32 > FalseVal32) {
3293 // 64-bit check whether we can use CSINC.
3294 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3295 Opcode = AArch64ISD::CSINC;
3297 if (TrueVal > FalseVal) {
3302 // Swap TVal and FVal if necessary.
3304 std::swap(TVal, FVal);
3305 std::swap(CTVal, CFVal);
3306 CC = ISD::getSetCCInverse(CC, true);
3309 if (Opcode != AArch64ISD::CSEL) {
3310 // Drop FVal since we can get its value by simply inverting/negating
3317 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3319 EVT VT = Op.getValueType();
3320 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3323 // Now we know we're dealing with FP values.
3324 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3325 assert(LHS.getValueType() == RHS.getValueType());
3326 EVT VT = Op.getValueType();
3328 // Try to match this select into a max/min operation, which have dedicated
3329 // opcode in the instruction set.
3330 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3332 if (getTargetMachine().Options.NoNaNsFPMath) {
3333 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3334 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3335 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3336 CC = ISD::getSetCCSwappedOperands(CC);
3337 std::swap(MinMaxLHS, MinMaxRHS);
3340 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3341 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3351 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3359 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3365 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3366 // and do the comparison.
3367 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3369 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3370 // clean. Some of them require two CSELs to implement.
3371 AArch64CC::CondCode CC1, CC2;
3372 changeFPCCToAArch64CC(CC, CC1, CC2);
3373 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3374 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3376 // If we need a second CSEL, emit it, using the output of the first as the
3377 // RHS. We're effectively OR'ing the two CC's together.
3378 if (CC2 != AArch64CC::AL) {
3379 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3380 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3383 // Otherwise, return the output of the first CSEL.
3387 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3388 SelectionDAG &DAG) const {
3389 // Jump table entries as PC relative offsets. No additional tweaking
3390 // is necessary here. Just get the address of the jump table.
3391 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3392 EVT PtrVT = getPointerTy();
3395 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3396 !Subtarget->isTargetMachO()) {
3397 const unsigned char MO_NC = AArch64II::MO_NC;
3399 AArch64ISD::WrapperLarge, DL, PtrVT,
3400 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3401 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3402 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3403 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3404 AArch64II::MO_G0 | MO_NC));
3408 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3409 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3410 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3411 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3412 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3415 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3416 SelectionDAG &DAG) const {
3417 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3418 EVT PtrVT = getPointerTy();
3421 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3422 // Use the GOT for the large code model on iOS.
3423 if (Subtarget->isTargetMachO()) {
3424 SDValue GotAddr = DAG.getTargetConstantPool(
3425 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3427 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3430 const unsigned char MO_NC = AArch64II::MO_NC;
3432 AArch64ISD::WrapperLarge, DL, PtrVT,
3433 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3434 CP->getOffset(), AArch64II::MO_G3),
3435 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3436 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3437 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3438 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3439 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3440 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3442 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3443 // ELF, the only valid one on Darwin.
3445 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3446 CP->getOffset(), AArch64II::MO_PAGE);
3447 SDValue Lo = DAG.getTargetConstantPool(
3448 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3449 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3451 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3452 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3456 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3457 SelectionDAG &DAG) const {
3458 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3459 EVT PtrVT = getPointerTy();
3461 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3462 !Subtarget->isTargetMachO()) {
3463 const unsigned char MO_NC = AArch64II::MO_NC;
3465 AArch64ISD::WrapperLarge, DL, PtrVT,
3466 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3467 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3468 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3469 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3471 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3472 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3474 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3475 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3479 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3480 SelectionDAG &DAG) const {
3481 AArch64FunctionInfo *FuncInfo =
3482 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3486 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3487 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3488 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3489 MachinePointerInfo(SV), false, false, 0);
3492 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3493 SelectionDAG &DAG) const {
3494 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3495 // Standard, section B.3.
3496 MachineFunction &MF = DAG.getMachineFunction();
3497 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3500 SDValue Chain = Op.getOperand(0);
3501 SDValue VAList = Op.getOperand(1);
3502 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3503 SmallVector<SDValue, 4> MemOps;
3505 // void *__stack at offset 0
3507 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3508 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3509 MachinePointerInfo(SV), false, false, 8));
3511 // void *__gr_top at offset 8
3512 int GPRSize = FuncInfo->getVarArgsGPRSize();
3514 SDValue GRTop, GRTopAddr;
3516 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3517 DAG.getConstant(8, getPointerTy()));
3519 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3520 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3521 DAG.getConstant(GPRSize, getPointerTy()));
3523 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3524 MachinePointerInfo(SV, 8), false, false, 8));
3527 // void *__vr_top at offset 16
3528 int FPRSize = FuncInfo->getVarArgsFPRSize();
3530 SDValue VRTop, VRTopAddr;
3531 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3532 DAG.getConstant(16, getPointerTy()));
3534 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3535 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3536 DAG.getConstant(FPRSize, getPointerTy()));
3538 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3539 MachinePointerInfo(SV, 16), false, false, 8));
3542 // int __gr_offs at offset 24
3543 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3544 DAG.getConstant(24, getPointerTy()));
3545 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3546 GROffsAddr, MachinePointerInfo(SV, 24), false,
3549 // int __vr_offs at offset 28
3550 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3551 DAG.getConstant(28, getPointerTy()));
3552 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3553 VROffsAddr, MachinePointerInfo(SV, 28), false,
3556 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3559 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3560 SelectionDAG &DAG) const {
3561 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3562 : LowerAAPCS_VASTART(Op, DAG);
3565 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3566 SelectionDAG &DAG) const {
3567 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3569 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3570 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3571 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3573 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3574 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3575 8, false, false, MachinePointerInfo(DestSV),
3576 MachinePointerInfo(SrcSV));
3579 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3580 assert(Subtarget->isTargetDarwin() &&
3581 "automatic va_arg instruction only works on Darwin");
3583 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3584 EVT VT = Op.getValueType();
3586 SDValue Chain = Op.getOperand(0);
3587 SDValue Addr = Op.getOperand(1);
3588 unsigned Align = Op.getConstantOperandVal(3);
3590 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3591 MachinePointerInfo(V), false, false, false, 0);
3592 Chain = VAList.getValue(1);
3595 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3596 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3597 DAG.getConstant(Align - 1, getPointerTy()));
3598 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3599 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3602 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3603 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3605 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3606 // up to 64 bits. At the very least, we have to increase the striding of the
3607 // vaargs list to match this, and for FP values we need to introduce
3608 // FP_ROUND nodes as well.
3609 if (VT.isInteger() && !VT.isVector())
3611 bool NeedFPTrunc = false;
3612 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3617 // Increment the pointer, VAList, to the next vaarg
3618 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3619 DAG.getConstant(ArgSize, getPointerTy()));
3620 // Store the incremented VAList to the legalized pointer
3621 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3624 // Load the actual argument out of the pointer VAList
3626 // Load the value as an f64.
3627 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3628 MachinePointerInfo(), false, false, false, 0);
3629 // Round the value down to an f32.
3630 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3631 DAG.getIntPtrConstant(1));
3632 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3633 // Merge the rounded value with the chain output of the load.
3634 return DAG.getMergeValues(Ops, DL);
3637 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3641 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3642 SelectionDAG &DAG) const {
3643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3644 MFI->setFrameAddressIsTaken(true);
3646 EVT VT = Op.getValueType();
3648 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3650 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3652 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3653 MachinePointerInfo(), false, false, false, 0);
3657 // FIXME? Maybe this could be a TableGen attribute on some registers and
3658 // this table could be generated automatically from RegInfo.
3659 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3661 unsigned Reg = StringSwitch<unsigned>(RegName)
3662 .Case("sp", AArch64::SP)
3666 report_fatal_error("Invalid register name global variable");
3669 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3670 SelectionDAG &DAG) const {
3671 MachineFunction &MF = DAG.getMachineFunction();
3672 MachineFrameInfo *MFI = MF.getFrameInfo();
3673 MFI->setReturnAddressIsTaken(true);
3675 EVT VT = Op.getValueType();
3677 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3679 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3680 SDValue Offset = DAG.getConstant(8, getPointerTy());
3681 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3682 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3683 MachinePointerInfo(), false, false, false, 0);
3686 // Return LR, which contains the return address. Mark it an implicit live-in.
3687 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3688 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3691 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3692 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3693 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3694 SelectionDAG &DAG) const {
3695 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3696 EVT VT = Op.getValueType();
3697 unsigned VTBits = VT.getSizeInBits();
3699 SDValue ShOpLo = Op.getOperand(0);
3700 SDValue ShOpHi = Op.getOperand(1);
3701 SDValue ShAmt = Op.getOperand(2);
3703 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3705 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3707 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3708 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3709 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3710 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3711 DAG.getConstant(VTBits, MVT::i64));
3712 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3714 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3715 ISD::SETGE, dl, DAG);
3716 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3718 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3719 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3721 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3723 // AArch64 shifts larger than the register width are wrapped rather than
3724 // clamped, so we can't just emit "hi >> x".
3725 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3726 SDValue TrueValHi = Opc == ISD::SRA
3727 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3728 DAG.getConstant(VTBits - 1, MVT::i64))
3729 : DAG.getConstant(0, VT);
3731 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3733 SDValue Ops[2] = { Lo, Hi };
3734 return DAG.getMergeValues(Ops, dl);
3737 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3738 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3739 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3740 SelectionDAG &DAG) const {
3741 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3742 EVT VT = Op.getValueType();
3743 unsigned VTBits = VT.getSizeInBits();
3745 SDValue ShOpLo = Op.getOperand(0);
3746 SDValue ShOpHi = Op.getOperand(1);
3747 SDValue ShAmt = Op.getOperand(2);
3750 assert(Op.getOpcode() == ISD::SHL_PARTS);
3751 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3752 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3753 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3754 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3755 DAG.getConstant(VTBits, MVT::i64));
3756 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3757 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3759 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3761 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3762 ISD::SETGE, dl, DAG);
3763 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3765 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3767 // AArch64 shifts of larger than register sizes are wrapped rather than
3768 // clamped, so we can't just emit "lo << a" if a is too big.
3769 SDValue TrueValLo = DAG.getConstant(0, VT);
3770 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3772 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3774 SDValue Ops[2] = { Lo, Hi };
3775 return DAG.getMergeValues(Ops, dl);
3778 bool AArch64TargetLowering::isOffsetFoldingLegal(
3779 const GlobalAddressSDNode *GA) const {
3780 // The AArch64 target doesn't support folding offsets into global addresses.
3784 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3785 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3786 // FIXME: We should be able to handle f128 as well with a clever lowering.
3787 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3791 return AArch64_AM::getFP64Imm(Imm) != -1;
3792 else if (VT == MVT::f32)
3793 return AArch64_AM::getFP32Imm(Imm) != -1;
3797 //===----------------------------------------------------------------------===//
3798 // AArch64 Optimization Hooks
3799 //===----------------------------------------------------------------------===//
3801 //===----------------------------------------------------------------------===//
3802 // AArch64 Inline Assembly Support
3803 //===----------------------------------------------------------------------===//
3805 // Table of Constraints
3806 // TODO: This is the current set of constraints supported by ARM for the
3807 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3809 // r - A general register
3810 // w - An FP/SIMD register of some size in the range v0-v31
3811 // x - An FP/SIMD register of some size in the range v0-v15
3812 // I - Constant that can be used with an ADD instruction
3813 // J - Constant that can be used with a SUB instruction
3814 // K - Constant that can be used with a 32-bit logical instruction
3815 // L - Constant that can be used with a 64-bit logical instruction
3816 // M - Constant that can be used as a 32-bit MOV immediate
3817 // N - Constant that can be used as a 64-bit MOV immediate
3818 // Q - A memory reference with base register and no offset
3819 // S - A symbolic address
3820 // Y - Floating point constant zero
3821 // Z - Integer constant zero
3823 // Note that general register operands will be output using their 64-bit x
3824 // register name, whatever the size of the variable, unless the asm operand
3825 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3826 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3829 /// getConstraintType - Given a constraint letter, return the type of
3830 /// constraint it is for this target.
3831 AArch64TargetLowering::ConstraintType
3832 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3833 if (Constraint.size() == 1) {
3834 switch (Constraint[0]) {
3841 return C_RegisterClass;
3842 // An address with a single base register. Due to the way we
3843 // currently handle addresses it is the same as 'r'.
3848 return TargetLowering::getConstraintType(Constraint);
3851 /// Examine constraint type and operand type and determine a weight value.
3852 /// This object must already have been set up with the operand type
3853 /// and the current alternative constraint selected.
3854 TargetLowering::ConstraintWeight
3855 AArch64TargetLowering::getSingleConstraintMatchWeight(
3856 AsmOperandInfo &info, const char *constraint) const {
3857 ConstraintWeight weight = CW_Invalid;
3858 Value *CallOperandVal = info.CallOperandVal;
3859 // If we don't have a value, we can't do a match,
3860 // but allow it at the lowest weight.
3861 if (!CallOperandVal)
3863 Type *type = CallOperandVal->getType();
3864 // Look at the constraint type.
3865 switch (*constraint) {
3867 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3871 if (type->isFloatingPointTy() || type->isVectorTy())
3872 weight = CW_Register;
3875 weight = CW_Constant;
3881 std::pair<unsigned, const TargetRegisterClass *>
3882 AArch64TargetLowering::getRegForInlineAsmConstraint(
3883 const std::string &Constraint, MVT VT) const {
3884 if (Constraint.size() == 1) {
3885 switch (Constraint[0]) {
3887 if (VT.getSizeInBits() == 64)
3888 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3889 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3892 return std::make_pair(0U, &AArch64::FPR32RegClass);
3893 if (VT.getSizeInBits() == 64)
3894 return std::make_pair(0U, &AArch64::FPR64RegClass);
3895 if (VT.getSizeInBits() == 128)
3896 return std::make_pair(0U, &AArch64::FPR128RegClass);
3898 // The instructions that this constraint is designed for can
3899 // only take 128-bit registers so just use that regclass.
3901 if (VT.getSizeInBits() == 128)
3902 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3906 if (StringRef("{cc}").equals_lower(Constraint))
3907 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3909 // Use the default implementation in TargetLowering to convert the register
3910 // constraint into a member of a register class.
3911 std::pair<unsigned, const TargetRegisterClass *> Res;
3912 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3914 // Not found as a standard register?
3916 unsigned Size = Constraint.size();
3917 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3918 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3919 const std::string Reg =
3920 std::string(&Constraint[2], &Constraint[Size - 1]);
3921 int RegNo = atoi(Reg.c_str());
3922 if (RegNo >= 0 && RegNo <= 31) {
3923 // v0 - v31 are aliases of q0 - q31.
3924 // By default we'll emit v0-v31 for this unless there's a modifier where
3925 // we'll emit the correct register as well.
3926 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3927 Res.second = &AArch64::FPR128RegClass;
3935 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3936 /// vector. If it is invalid, don't add anything to Ops.
3937 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3938 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3939 SelectionDAG &DAG) const {
3942 // Currently only support length 1 constraints.
3943 if (Constraint.length() != 1)
3946 char ConstraintLetter = Constraint[0];
3947 switch (ConstraintLetter) {
3951 // This set of constraints deal with valid constants for various instructions.
3952 // Validate and return a target constant for them if we can.
3954 // 'z' maps to xzr or wzr so it needs an input of 0.
3955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3956 if (!C || C->getZExtValue() != 0)
3959 if (Op.getValueType() == MVT::i64)
3960 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3962 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3976 // Grab the value and do some validation.
3977 uint64_t CVal = C->getZExtValue();
3978 switch (ConstraintLetter) {
3979 // The I constraint applies only to simple ADD or SUB immediate operands:
3980 // i.e. 0 to 4095 with optional shift by 12
3981 // The J constraint applies only to ADD or SUB immediates that would be
3982 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3983 // instruction [or vice versa], in other words -1 to -4095 with optional
3984 // left shift by 12.
3986 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
3990 uint64_t NVal = -C->getSExtValue();
3991 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
3995 // The K and L constraints apply *only* to logical immediates, including
3996 // what used to be the MOVI alias for ORR (though the MOVI alias has now
3997 // been removed and MOV should be used). So these constraints have to
3998 // distinguish between bit patterns that are valid 32-bit or 64-bit
3999 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4000 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4003 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4007 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4010 // The M and N constraints are a superset of K and L respectively, for use
4011 // with the MOV (immediate) alias. As well as the logical immediates they
4012 // also match 32 or 64-bit immediates that can be loaded either using a
4013 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4014 // (M) or 64-bit 0x1234000000000000 (N) etc.
4015 // As a note some of this code is liberally stolen from the asm parser.
4017 if (!isUInt<32>(CVal))
4019 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4021 if ((CVal & 0xFFFF) == CVal)
4023 if ((CVal & 0xFFFF0000ULL) == CVal)
4025 uint64_t NCVal = ~(uint32_t)CVal;
4026 if ((NCVal & 0xFFFFULL) == NCVal)
4028 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4033 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4035 if ((CVal & 0xFFFFULL) == CVal)
4037 if ((CVal & 0xFFFF0000ULL) == CVal)
4039 if ((CVal & 0xFFFF00000000ULL) == CVal)
4041 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4043 uint64_t NCVal = ~CVal;
4044 if ((NCVal & 0xFFFFULL) == NCVal)
4046 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4048 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4050 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4058 // All assembler immediates are 64-bit integers.
4059 Result = DAG.getTargetConstant(CVal, MVT::i64);
4063 if (Result.getNode()) {
4064 Ops.push_back(Result);
4068 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4071 //===----------------------------------------------------------------------===//
4072 // AArch64 Advanced SIMD Support
4073 //===----------------------------------------------------------------------===//
4075 /// WidenVector - Given a value in the V64 register class, produce the
4076 /// equivalent value in the V128 register class.
4077 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4078 EVT VT = V64Reg.getValueType();
4079 unsigned NarrowSize = VT.getVectorNumElements();
4080 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4081 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4084 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4085 V64Reg, DAG.getConstant(0, MVT::i32));
4088 /// getExtFactor - Determine the adjustment factor for the position when
4089 /// generating an "extract from vector registers" instruction.
4090 static unsigned getExtFactor(SDValue &V) {
4091 EVT EltType = V.getValueType().getVectorElementType();
4092 return EltType.getSizeInBits() / 8;
4095 /// NarrowVector - Given a value in the V128 register class, produce the
4096 /// equivalent value in the V64 register class.
4097 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4098 EVT VT = V128Reg.getValueType();
4099 unsigned WideSize = VT.getVectorNumElements();
4100 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4101 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4104 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4107 // Gather data to see if the operation can be modelled as a
4108 // shuffle in combination with VEXTs.
4109 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4110 SelectionDAG &DAG) const {
4111 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4113 EVT VT = Op.getValueType();
4114 unsigned NumElts = VT.getVectorNumElements();
4116 SmallVector<SDValue, 2> SourceVecs;
4117 SmallVector<unsigned, 2> MinElts;
4118 SmallVector<unsigned, 2> MaxElts;
4120 for (unsigned i = 0; i < NumElts; ++i) {
4121 SDValue V = Op.getOperand(i);
4122 if (V.getOpcode() == ISD::UNDEF)
4124 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4125 // A shuffle can only come from building a vector from various
4126 // elements of other vectors.
4130 // Record this extraction against the appropriate vector if possible...
4131 SDValue SourceVec = V.getOperand(0);
4132 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4133 bool FoundSource = false;
4134 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4135 if (SourceVecs[j] == SourceVec) {
4136 if (MinElts[j] > EltNo)
4138 if (MaxElts[j] < EltNo)
4145 // Or record a new source if not...
4147 SourceVecs.push_back(SourceVec);
4148 MinElts.push_back(EltNo);
4149 MaxElts.push_back(EltNo);
4153 // Currently only do something sane when at most two source vectors
4155 if (SourceVecs.size() > 2)
4158 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4159 int VEXTOffsets[2] = { 0, 0 };
4160 int OffsetMultipliers[2] = { 1, 1 };
4162 // This loop extracts the usage patterns of the source vectors
4163 // and prepares appropriate SDValues for a shuffle if possible.
4164 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4165 unsigned NumSrcElts = SourceVecs[i].getValueType().getVectorNumElements();
4166 SDValue CurSource = SourceVecs[i];
4167 if (SourceVecs[i].getValueType().getVectorElementType() !=
4168 VT.getVectorElementType()) {
4169 // It may hit this case if SourceVecs[i] is AssertSext/AssertZext.
4170 // Then bitcast it to the vector which holds asserted element type,
4171 // and record the multiplier of element width between SourceVecs and
4172 // Build_vector which is needed to extract the correct lanes later.
4174 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4175 SourceVecs[i].getValueSizeInBits() /
4176 VT.getVectorElementType().getSizeInBits());
4178 CurSource = DAG.getNode(ISD::BITCAST, dl, CastVT, SourceVecs[i]);
4179 OffsetMultipliers[i] = CastVT.getVectorNumElements() / NumSrcElts;
4180 NumSrcElts *= OffsetMultipliers[i];
4181 MaxElts[i] *= OffsetMultipliers[i];
4182 MinElts[i] *= OffsetMultipliers[i];
4185 if (CurSource.getValueType() == VT) {
4186 // No VEXT necessary
4187 ShuffleSrcs[i] = CurSource;
4190 } else if (NumSrcElts < NumElts) {
4191 // We can pad out the smaller vector for free, so if it's part of a
4193 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, CurSource,
4194 DAG.getUNDEF(CurSource.getValueType()));
4198 // Since only 64-bit and 128-bit vectors are legal on ARM and
4199 // we've eliminated the other cases...
4200 assert(NumSrcElts == 2 * NumElts &&
4201 "unexpected vector sizes in ReconstructShuffle");
4203 if (MaxElts[i] - MinElts[i] >= NumElts) {
4204 // Span too large for a VEXT to cope
4208 if (MinElts[i] >= NumElts) {
4209 // The extraction can just take the second half
4210 VEXTOffsets[i] = NumElts;
4211 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4212 DAG.getIntPtrConstant(NumElts));
4213 } else if (MaxElts[i] < NumElts) {
4214 // The extraction can just take the first half
4216 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4217 DAG.getIntPtrConstant(0));
4219 // An actual VEXT is needed
4220 VEXTOffsets[i] = MinElts[i];
4221 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4222 DAG.getIntPtrConstant(0));
4223 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4224 DAG.getIntPtrConstant(NumElts));
4225 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4226 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4227 DAG.getConstant(Imm, MVT::i32));
4231 SmallVector<int, 8> Mask;
4233 for (unsigned i = 0; i < NumElts; ++i) {
4234 SDValue Entry = Op.getOperand(i);
4235 if (Entry.getOpcode() == ISD::UNDEF) {
4240 SDValue ExtractVec = Entry.getOperand(0);
4242 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4243 if (ExtractVec == SourceVecs[0]) {
4244 Mask.push_back(ExtractElt * OffsetMultipliers[0] - VEXTOffsets[0]);
4246 Mask.push_back(ExtractElt * OffsetMultipliers[1] + NumElts -
4251 // Final check before we try to produce nonsense...
4252 if (isShuffleMaskLegal(Mask, VT))
4253 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4259 // check if an EXT instruction can handle the shuffle mask when the
4260 // vector sources of the shuffle are the same.
4261 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4262 unsigned NumElts = VT.getVectorNumElements();
4264 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4270 // If this is a VEXT shuffle, the immediate value is the index of the first
4271 // element. The other shuffle indices must be the successive elements after
4273 unsigned ExpectedElt = Imm;
4274 for (unsigned i = 1; i < NumElts; ++i) {
4275 // Increment the expected index. If it wraps around, just follow it
4276 // back to index zero and keep going.
4278 if (ExpectedElt == NumElts)
4282 continue; // ignore UNDEF indices
4283 if (ExpectedElt != static_cast<unsigned>(M[i]))
4290 // check if an EXT instruction can handle the shuffle mask when the
4291 // vector sources of the shuffle are different.
4292 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4294 // Look for the first non-undef element.
4295 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4296 [](int Elt) {return Elt >= 0;});
4298 // Benefit form APInt to handle overflow when calculating expected element.
4299 unsigned NumElts = VT.getVectorNumElements();
4300 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4301 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4302 // The following shuffle indices must be the successive elements after the
4303 // first real element.
4304 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4305 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4306 if (FirstWrongElt != M.end())
4309 // The index of an EXT is the first element if it is not UNDEF.
4310 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4311 // value of the first element. E.g.
4312 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4313 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4314 // ExpectedElt is the last mask index plus 1.
4315 Imm = ExpectedElt.getZExtValue();
4317 // There are two difference cases requiring to reverse input vectors.
4318 // For example, for vector <4 x i32> we have the following cases,
4319 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4320 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4321 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4322 // to reverse two input vectors.
4331 /// isREVMask - Check if a vector shuffle corresponds to a REV
4332 /// instruction with the specified blocksize. (The order of the elements
4333 /// within each block of the vector is reversed.)
4334 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4335 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4336 "Only possible block sizes for REV are: 16, 32, 64");
4338 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4342 unsigned NumElts = VT.getVectorNumElements();
4343 unsigned BlockElts = M[0] + 1;
4344 // If the first shuffle index is UNDEF, be optimistic.
4346 BlockElts = BlockSize / EltSz;
4348 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4351 for (unsigned i = 0; i < NumElts; ++i) {
4353 continue; // ignore UNDEF indices
4354 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4361 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4362 unsigned NumElts = VT.getVectorNumElements();
4363 WhichResult = (M[0] == 0 ? 0 : 1);
4364 unsigned Idx = WhichResult * NumElts / 2;
4365 for (unsigned i = 0; i != NumElts; i += 2) {
4366 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4367 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4375 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4376 unsigned NumElts = VT.getVectorNumElements();
4377 WhichResult = (M[0] == 0 ? 0 : 1);
4378 for (unsigned i = 0; i != NumElts; ++i) {
4380 continue; // ignore UNDEF indices
4381 if ((unsigned)M[i] != 2 * i + WhichResult)
4388 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4389 unsigned NumElts = VT.getVectorNumElements();
4390 WhichResult = (M[0] == 0 ? 0 : 1);
4391 for (unsigned i = 0; i < NumElts; i += 2) {
4392 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4393 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4399 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4400 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4401 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4402 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4403 unsigned NumElts = VT.getVectorNumElements();
4404 WhichResult = (M[0] == 0 ? 0 : 1);
4405 unsigned Idx = WhichResult * NumElts / 2;
4406 for (unsigned i = 0; i != NumElts; i += 2) {
4407 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4408 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4416 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4417 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4418 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4419 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4420 unsigned Half = VT.getVectorNumElements() / 2;
4421 WhichResult = (M[0] == 0 ? 0 : 1);
4422 for (unsigned j = 0; j != 2; ++j) {
4423 unsigned Idx = WhichResult;
4424 for (unsigned i = 0; i != Half; ++i) {
4425 int MIdx = M[i + j * Half];
4426 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4435 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4436 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4437 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4438 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4439 unsigned NumElts = VT.getVectorNumElements();
4440 WhichResult = (M[0] == 0 ? 0 : 1);
4441 for (unsigned i = 0; i < NumElts; i += 2) {
4442 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4443 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4449 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4450 bool &DstIsLeft, int &Anomaly) {
4451 if (M.size() != static_cast<size_t>(NumInputElements))
4454 int NumLHSMatch = 0, NumRHSMatch = 0;
4455 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4457 for (int i = 0; i < NumInputElements; ++i) {
4467 LastLHSMismatch = i;
4469 if (M[i] == i + NumInputElements)
4472 LastRHSMismatch = i;
4475 if (NumLHSMatch == NumInputElements - 1) {
4477 Anomaly = LastLHSMismatch;
4479 } else if (NumRHSMatch == NumInputElements - 1) {
4481 Anomaly = LastRHSMismatch;
4488 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4489 if (VT.getSizeInBits() != 128)
4492 unsigned NumElts = VT.getVectorNumElements();
4494 for (int I = 0, E = NumElts / 2; I != E; I++) {
4499 int Offset = NumElts / 2;
4500 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4501 if (Mask[I] != I + SplitLHS * Offset)
4508 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4510 EVT VT = Op.getValueType();
4511 SDValue V0 = Op.getOperand(0);
4512 SDValue V1 = Op.getOperand(1);
4513 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4515 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4516 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4519 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4521 if (!isConcatMask(Mask, VT, SplitV0))
4524 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4525 VT.getVectorNumElements() / 2);
4527 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4528 DAG.getConstant(0, MVT::i64));
4530 if (V1.getValueType().getSizeInBits() == 128) {
4531 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4532 DAG.getConstant(0, MVT::i64));
4534 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4537 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4538 /// the specified operations to build the shuffle.
4539 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4540 SDValue RHS, SelectionDAG &DAG,
4542 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4543 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4544 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4547 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4556 OP_VUZPL, // VUZP, left result
4557 OP_VUZPR, // VUZP, right result
4558 OP_VZIPL, // VZIP, left result
4559 OP_VZIPR, // VZIP, right result
4560 OP_VTRNL, // VTRN, left result
4561 OP_VTRNR // VTRN, right result
4564 if (OpNum == OP_COPY) {
4565 if (LHSID == (1 * 9 + 2) * 9 + 3)
4567 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4571 SDValue OpLHS, OpRHS;
4572 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4573 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4574 EVT VT = OpLHS.getValueType();
4578 llvm_unreachable("Unknown shuffle opcode!");
4580 // VREV divides the vector in half and swaps within the half.
4581 if (VT.getVectorElementType() == MVT::i32 ||
4582 VT.getVectorElementType() == MVT::f32)
4583 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4584 // vrev <4 x i16> -> REV32
4585 if (VT.getVectorElementType() == MVT::i16)
4586 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4587 // vrev <4 x i8> -> REV16
4588 assert(VT.getVectorElementType() == MVT::i8);
4589 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4594 EVT EltTy = VT.getVectorElementType();
4596 if (EltTy == MVT::i8)
4597 Opcode = AArch64ISD::DUPLANE8;
4598 else if (EltTy == MVT::i16)
4599 Opcode = AArch64ISD::DUPLANE16;
4600 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4601 Opcode = AArch64ISD::DUPLANE32;
4602 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4603 Opcode = AArch64ISD::DUPLANE64;
4605 llvm_unreachable("Invalid vector element type?");
4607 if (VT.getSizeInBits() == 64)
4608 OpLHS = WidenVector(OpLHS, DAG);
4609 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4610 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4615 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4616 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4617 DAG.getConstant(Imm, MVT::i32));
4620 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4623 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4626 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4629 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4632 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4635 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4640 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4641 SelectionDAG &DAG) {
4642 // Check to see if we can use the TBL instruction.
4643 SDValue V1 = Op.getOperand(0);
4644 SDValue V2 = Op.getOperand(1);
4647 EVT EltVT = Op.getValueType().getVectorElementType();
4648 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4650 SmallVector<SDValue, 8> TBLMask;
4651 for (int Val : ShuffleMask) {
4652 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4653 unsigned Offset = Byte + Val * BytesPerElt;
4654 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4658 MVT IndexVT = MVT::v8i8;
4659 unsigned IndexLen = 8;
4660 if (Op.getValueType().getSizeInBits() == 128) {
4661 IndexVT = MVT::v16i8;
4665 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4666 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4669 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4671 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4672 Shuffle = DAG.getNode(
4673 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4674 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4675 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4676 makeArrayRef(TBLMask.data(), IndexLen)));
4678 if (IndexLen == 8) {
4679 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4680 Shuffle = DAG.getNode(
4681 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4682 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4683 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4684 makeArrayRef(TBLMask.data(), IndexLen)));
4686 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4687 // cannot currently represent the register constraints on the input
4689 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4690 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4691 // &TBLMask[0], IndexLen));
4692 Shuffle = DAG.getNode(
4693 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4694 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4695 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4696 makeArrayRef(TBLMask.data(), IndexLen)));
4699 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4702 static unsigned getDUPLANEOp(EVT EltType) {
4703 if (EltType == MVT::i8)
4704 return AArch64ISD::DUPLANE8;
4705 if (EltType == MVT::i16)
4706 return AArch64ISD::DUPLANE16;
4707 if (EltType == MVT::i32 || EltType == MVT::f32)
4708 return AArch64ISD::DUPLANE32;
4709 if (EltType == MVT::i64 || EltType == MVT::f64)
4710 return AArch64ISD::DUPLANE64;
4712 llvm_unreachable("Invalid vector element type?");
4715 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4716 SelectionDAG &DAG) const {
4718 EVT VT = Op.getValueType();
4720 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4722 // Convert shuffles that are directly supported on NEON to target-specific
4723 // DAG nodes, instead of keeping them as shuffles and matching them again
4724 // during code selection. This is more efficient and avoids the possibility
4725 // of inconsistencies between legalization and selection.
4726 ArrayRef<int> ShuffleMask = SVN->getMask();
4728 SDValue V1 = Op.getOperand(0);
4729 SDValue V2 = Op.getOperand(1);
4731 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4732 V1.getValueType().getSimpleVT())) {
4733 int Lane = SVN->getSplatIndex();
4734 // If this is undef splat, generate it via "just" vdup, if possible.
4738 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4739 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4741 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4742 // constant. If so, we can just reference the lane's definition directly.
4743 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4744 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4745 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4747 // Otherwise, duplicate from the lane of the input vector.
4748 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4750 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4751 // to make a vector of the same size as this SHUFFLE. We can ignore the
4752 // extract entirely, and canonicalise the concat using WidenVector.
4753 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4754 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4755 V1 = V1.getOperand(0);
4756 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4757 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4758 Lane -= Idx * VT.getVectorNumElements() / 2;
4759 V1 = WidenVector(V1.getOperand(Idx), DAG);
4760 } else if (VT.getSizeInBits() == 64)
4761 V1 = WidenVector(V1, DAG);
4763 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4766 if (isREVMask(ShuffleMask, VT, 64))
4767 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4768 if (isREVMask(ShuffleMask, VT, 32))
4769 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4770 if (isREVMask(ShuffleMask, VT, 16))
4771 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4773 bool ReverseEXT = false;
4775 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4778 Imm *= getExtFactor(V1);
4779 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4780 DAG.getConstant(Imm, MVT::i32));
4781 } else if (V2->getOpcode() == ISD::UNDEF &&
4782 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4783 Imm *= getExtFactor(V1);
4784 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4785 DAG.getConstant(Imm, MVT::i32));
4788 unsigned WhichResult;
4789 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4790 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4791 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4793 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4794 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4795 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4797 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4798 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4799 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4802 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4803 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4804 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4806 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4807 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4808 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4810 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4811 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4812 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4815 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4816 if (Concat.getNode())
4821 int NumInputElements = V1.getValueType().getVectorNumElements();
4822 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4823 SDValue DstVec = DstIsLeft ? V1 : V2;
4824 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4826 SDValue SrcVec = V1;
4827 int SrcLane = ShuffleMask[Anomaly];
4828 if (SrcLane >= NumInputElements) {
4830 SrcLane -= VT.getVectorNumElements();
4832 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4834 EVT ScalarVT = VT.getVectorElementType();
4835 if (ScalarVT.getSizeInBits() < 32)
4836 ScalarVT = MVT::i32;
4839 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4840 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4844 // If the shuffle is not directly supported and it has 4 elements, use
4845 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4846 unsigned NumElts = VT.getVectorNumElements();
4848 unsigned PFIndexes[4];
4849 for (unsigned i = 0; i != 4; ++i) {
4850 if (ShuffleMask[i] < 0)
4853 PFIndexes[i] = ShuffleMask[i];
4856 // Compute the index in the perfect shuffle table.
4857 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4858 PFIndexes[2] * 9 + PFIndexes[3];
4859 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4860 unsigned Cost = (PFEntry >> 30);
4863 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4866 return GenerateTBL(Op, ShuffleMask, DAG);
4869 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4871 EVT VT = BVN->getValueType(0);
4872 APInt SplatBits, SplatUndef;
4873 unsigned SplatBitSize;
4875 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4876 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4878 for (unsigned i = 0; i < NumSplats; ++i) {
4879 CnstBits <<= SplatBitSize;
4880 UndefBits <<= SplatBitSize;
4881 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4882 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4891 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4892 SelectionDAG &DAG) const {
4893 BuildVectorSDNode *BVN =
4894 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4895 SDValue LHS = Op.getOperand(0);
4897 EVT VT = Op.getValueType();
4902 APInt CnstBits(VT.getSizeInBits(), 0);
4903 APInt UndefBits(VT.getSizeInBits(), 0);
4904 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4905 // We only have BIC vector immediate instruction, which is and-not.
4906 CnstBits = ~CnstBits;
4908 // We make use of a little bit of goto ickiness in order to avoid having to
4909 // duplicate the immediate matching logic for the undef toggled case.
4910 bool SecondTry = false;
4913 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4914 CnstBits = CnstBits.zextOrTrunc(64);
4915 uint64_t CnstVal = CnstBits.getZExtValue();
4917 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4918 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4919 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4920 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4921 DAG.getConstant(CnstVal, MVT::i32),
4922 DAG.getConstant(0, MVT::i32));
4923 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4926 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4927 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4928 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4929 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4930 DAG.getConstant(CnstVal, MVT::i32),
4931 DAG.getConstant(8, MVT::i32));
4932 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4935 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4936 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4937 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4938 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4939 DAG.getConstant(CnstVal, MVT::i32),
4940 DAG.getConstant(16, MVT::i32));
4941 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4944 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4945 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4946 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4947 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4948 DAG.getConstant(CnstVal, MVT::i32),
4949 DAG.getConstant(24, MVT::i32));
4950 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4953 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4954 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4955 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4956 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4957 DAG.getConstant(CnstVal, MVT::i32),
4958 DAG.getConstant(0, MVT::i32));
4959 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4962 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4963 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4964 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4965 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4966 DAG.getConstant(CnstVal, MVT::i32),
4967 DAG.getConstant(8, MVT::i32));
4968 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4975 CnstBits = ~UndefBits;
4979 // We can always fall back to a non-immediate AND.
4984 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4985 // consists of only the same constant int value, returned in reference arg
4987 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4988 uint64_t &ConstVal) {
4989 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4992 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4995 EVT VT = Bvec->getValueType(0);
4996 unsigned NumElts = VT.getVectorNumElements();
4997 for (unsigned i = 1; i < NumElts; ++i)
4998 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5000 ConstVal = FirstElt->getZExtValue();
5004 static unsigned getIntrinsicID(const SDNode *N) {
5005 unsigned Opcode = N->getOpcode();
5008 return Intrinsic::not_intrinsic;
5009 case ISD::INTRINSIC_WO_CHAIN: {
5010 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5011 if (IID < Intrinsic::num_intrinsics)
5013 return Intrinsic::not_intrinsic;
5018 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5019 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5020 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5021 // Also, logical shift right -> sri, with the same structure.
5022 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5023 EVT VT = N->getValueType(0);
5030 // Is the first op an AND?
5031 const SDValue And = N->getOperand(0);
5032 if (And.getOpcode() != ISD::AND)
5035 // Is the second op an shl or lshr?
5036 SDValue Shift = N->getOperand(1);
5037 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5038 // or AArch64ISD::VLSHR vector, #shift
5039 unsigned ShiftOpc = Shift.getOpcode();
5040 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5042 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5044 // Is the shift amount constant?
5045 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5049 // Is the and mask vector all constant?
5051 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5054 // Is C1 == ~C2, taking into account how much one can shift elements of a
5056 uint64_t C2 = C2node->getZExtValue();
5057 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5058 if (C2 > ElemSizeInBits)
5060 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5061 if ((C1 & ElemMask) != (~C2 & ElemMask))
5064 SDValue X = And.getOperand(0);
5065 SDValue Y = Shift.getOperand(0);
5068 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5070 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5071 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5073 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5074 DEBUG(N->dump(&DAG));
5075 DEBUG(dbgs() << "into: \n");
5076 DEBUG(ResultSLI->dump(&DAG));
5082 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5083 SelectionDAG &DAG) const {
5084 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5085 if (EnableAArch64SlrGeneration) {
5086 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5091 BuildVectorSDNode *BVN =
5092 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5093 SDValue LHS = Op.getOperand(1);
5095 EVT VT = Op.getValueType();
5097 // OR commutes, so try swapping the operands.
5099 LHS = Op.getOperand(0);
5100 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5105 APInt CnstBits(VT.getSizeInBits(), 0);
5106 APInt UndefBits(VT.getSizeInBits(), 0);
5107 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5108 // We make use of a little bit of goto ickiness in order to avoid having to
5109 // duplicate the immediate matching logic for the undef toggled case.
5110 bool SecondTry = false;
5113 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5114 CnstBits = CnstBits.zextOrTrunc(64);
5115 uint64_t CnstVal = CnstBits.getZExtValue();
5117 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5118 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5119 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5120 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5121 DAG.getConstant(CnstVal, MVT::i32),
5122 DAG.getConstant(0, MVT::i32));
5123 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5126 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5127 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5128 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5129 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5130 DAG.getConstant(CnstVal, MVT::i32),
5131 DAG.getConstant(8, MVT::i32));
5132 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5135 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5136 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5137 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5138 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5139 DAG.getConstant(CnstVal, MVT::i32),
5140 DAG.getConstant(16, MVT::i32));
5141 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5144 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5145 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5146 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5147 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5148 DAG.getConstant(CnstVal, MVT::i32),
5149 DAG.getConstant(24, MVT::i32));
5150 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5153 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5154 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5155 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5156 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5157 DAG.getConstant(CnstVal, MVT::i32),
5158 DAG.getConstant(0, MVT::i32));
5159 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5162 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5163 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5164 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5165 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5166 DAG.getConstant(CnstVal, MVT::i32),
5167 DAG.getConstant(8, MVT::i32));
5168 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5175 CnstBits = UndefBits;
5179 // We can always fall back to a non-immediate OR.
5184 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5185 SelectionDAG &DAG) const {
5186 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5188 EVT VT = Op.getValueType();
5190 APInt CnstBits(VT.getSizeInBits(), 0);
5191 APInt UndefBits(VT.getSizeInBits(), 0);
5192 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5193 // We make use of a little bit of goto ickiness in order to avoid having to
5194 // duplicate the immediate matching logic for the undef toggled case.
5195 bool SecondTry = false;
5198 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5199 CnstBits = CnstBits.zextOrTrunc(64);
5200 uint64_t CnstVal = CnstBits.getZExtValue();
5202 // Certain magic vector constants (used to express things like NOT
5203 // and NEG) are passed through unmodified. This allows codegen patterns
5204 // for these operations to match. Special-purpose patterns will lower
5205 // these immediates to MOVIs if it proves necessary.
5206 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5209 // The many faces of MOVI...
5210 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5211 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5212 if (VT.getSizeInBits() == 128) {
5213 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5214 DAG.getConstant(CnstVal, MVT::i32));
5215 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5218 // Support the V64 version via subregister insertion.
5219 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5220 DAG.getConstant(CnstVal, MVT::i32));
5221 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5224 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5225 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5226 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5227 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5228 DAG.getConstant(CnstVal, MVT::i32),
5229 DAG.getConstant(0, MVT::i32));
5230 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5233 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5234 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5235 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5236 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5237 DAG.getConstant(CnstVal, MVT::i32),
5238 DAG.getConstant(8, MVT::i32));
5239 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5242 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5243 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5244 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5245 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5246 DAG.getConstant(CnstVal, MVT::i32),
5247 DAG.getConstant(16, MVT::i32));
5248 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5251 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5252 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5253 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5254 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5255 DAG.getConstant(CnstVal, MVT::i32),
5256 DAG.getConstant(24, MVT::i32));
5257 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5260 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5261 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5262 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5263 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5264 DAG.getConstant(CnstVal, MVT::i32),
5265 DAG.getConstant(0, MVT::i32));
5266 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5269 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5270 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5271 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5272 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5273 DAG.getConstant(CnstVal, MVT::i32),
5274 DAG.getConstant(8, MVT::i32));
5275 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5278 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5279 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5280 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5281 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5282 DAG.getConstant(CnstVal, MVT::i32),
5283 DAG.getConstant(264, MVT::i32));
5284 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5287 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5288 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5289 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5290 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5291 DAG.getConstant(CnstVal, MVT::i32),
5292 DAG.getConstant(272, MVT::i32));
5293 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5296 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5297 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5298 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5299 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5300 DAG.getConstant(CnstVal, MVT::i32));
5301 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5304 // The few faces of FMOV...
5305 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5306 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5307 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5308 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5309 DAG.getConstant(CnstVal, MVT::i32));
5310 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5313 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5314 VT.getSizeInBits() == 128) {
5315 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5316 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5317 DAG.getConstant(CnstVal, MVT::i32));
5318 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5321 // The many faces of MVNI...
5323 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5324 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5325 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5326 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5327 DAG.getConstant(CnstVal, MVT::i32),
5328 DAG.getConstant(0, MVT::i32));
5329 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5332 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5333 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5334 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5335 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5336 DAG.getConstant(CnstVal, MVT::i32),
5337 DAG.getConstant(8, MVT::i32));
5338 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5341 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5342 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5343 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5344 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5345 DAG.getConstant(CnstVal, MVT::i32),
5346 DAG.getConstant(16, MVT::i32));
5347 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5350 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5351 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5352 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5353 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5354 DAG.getConstant(CnstVal, MVT::i32),
5355 DAG.getConstant(24, MVT::i32));
5356 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5359 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5360 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5361 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5362 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5363 DAG.getConstant(CnstVal, MVT::i32),
5364 DAG.getConstant(0, MVT::i32));
5365 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5368 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5369 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5370 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5371 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5372 DAG.getConstant(CnstVal, MVT::i32),
5373 DAG.getConstant(8, MVT::i32));
5374 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5377 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5378 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5379 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5380 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5381 DAG.getConstant(CnstVal, MVT::i32),
5382 DAG.getConstant(264, MVT::i32));
5383 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5386 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5387 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5388 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5389 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5390 DAG.getConstant(CnstVal, MVT::i32),
5391 DAG.getConstant(272, MVT::i32));
5392 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5399 CnstBits = UndefBits;
5404 // Scan through the operands to find some interesting properties we can
5406 // 1) If only one value is used, we can use a DUP, or
5407 // 2) if only the low element is not undef, we can just insert that, or
5408 // 3) if only one constant value is used (w/ some non-constant lanes),
5409 // we can splat the constant value into the whole vector then fill
5410 // in the non-constant lanes.
5411 // 4) FIXME: If different constant values are used, but we can intelligently
5412 // select the values we'll be overwriting for the non-constant
5413 // lanes such that we can directly materialize the vector
5414 // some other way (MOVI, e.g.), we can be sneaky.
5415 unsigned NumElts = VT.getVectorNumElements();
5416 bool isOnlyLowElement = true;
5417 bool usesOnlyOneValue = true;
5418 bool usesOnlyOneConstantValue = true;
5419 bool isConstant = true;
5420 unsigned NumConstantLanes = 0;
5422 SDValue ConstantValue;
5423 for (unsigned i = 0; i < NumElts; ++i) {
5424 SDValue V = Op.getOperand(i);
5425 if (V.getOpcode() == ISD::UNDEF)
5428 isOnlyLowElement = false;
5429 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5432 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5434 if (!ConstantValue.getNode())
5436 else if (ConstantValue != V)
5437 usesOnlyOneConstantValue = false;
5440 if (!Value.getNode())
5442 else if (V != Value)
5443 usesOnlyOneValue = false;
5446 if (!Value.getNode())
5447 return DAG.getUNDEF(VT);
5449 if (isOnlyLowElement)
5450 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5452 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5453 // i32 and try again.
5454 if (usesOnlyOneValue) {
5456 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5457 Value.getValueType() != VT)
5458 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5460 // This is actually a DUPLANExx operation, which keeps everything vectory.
5462 // DUPLANE works on 128-bit vectors, widen it if necessary.
5463 SDValue Lane = Value.getOperand(1);
5464 Value = Value.getOperand(0);
5465 if (Value.getValueType().getSizeInBits() == 64)
5466 Value = WidenVector(Value, DAG);
5468 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5469 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5472 if (VT.getVectorElementType().isFloatingPoint()) {
5473 SmallVector<SDValue, 8> Ops;
5475 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5476 for (unsigned i = 0; i < NumElts; ++i)
5477 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5478 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5479 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5480 Val = LowerBUILD_VECTOR(Val, DAG);
5482 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5486 // If there was only one constant value used and for more than one lane,
5487 // start by splatting that value, then replace the non-constant lanes. This
5488 // is better than the default, which will perform a separate initialization
5490 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5491 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5492 // Now insert the non-constant lanes.
5493 for (unsigned i = 0; i < NumElts; ++i) {
5494 SDValue V = Op.getOperand(i);
5495 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5496 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5497 // Note that type legalization likely mucked about with the VT of the
5498 // source operand, so we may have to convert it here before inserting.
5499 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5505 // If all elements are constants and the case above didn't get hit, fall back
5506 // to the default expansion, which will generate a load from the constant
5511 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5513 SDValue shuffle = ReconstructShuffle(Op, DAG);
5514 if (shuffle != SDValue())
5518 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5519 // know the default expansion would otherwise fall back on something even
5520 // worse. For a vector with one or two non-undef values, that's
5521 // scalar_to_vector for the elements followed by a shuffle (provided the
5522 // shuffle is valid for the target) and materialization element by element
5523 // on the stack followed by a load for everything else.
5524 if (!isConstant && !usesOnlyOneValue) {
5525 SDValue Vec = DAG.getUNDEF(VT);
5526 SDValue Op0 = Op.getOperand(0);
5527 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5529 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5530 // a) Avoid a RMW dependency on the full vector register, and
5531 // b) Allow the register coalescer to fold away the copy if the
5532 // value is already in an S or D register.
5533 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5534 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5536 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5537 DAG.getTargetConstant(SubIdx, MVT::i32));
5538 Vec = SDValue(N, 0);
5541 for (; i < NumElts; ++i) {
5542 SDValue V = Op.getOperand(i);
5543 if (V.getOpcode() == ISD::UNDEF)
5545 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5546 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5551 // Just use the default expansion. We failed to find a better alternative.
5555 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5556 SelectionDAG &DAG) const {
5557 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5559 // Check for non-constant lane.
5560 if (!isa<ConstantSDNode>(Op.getOperand(2)))
5563 EVT VT = Op.getOperand(0).getValueType();
5565 // Insertion/extraction are legal for V128 types.
5566 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5567 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5570 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5571 VT != MVT::v1i64 && VT != MVT::v2f32)
5574 // For V64 types, we perform insertion by expanding the value
5575 // to a V128 type and perform the insertion on that.
5577 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5578 EVT WideTy = WideVec.getValueType();
5580 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5581 Op.getOperand(1), Op.getOperand(2));
5582 // Re-narrow the resultant vector.
5583 return NarrowVector(Node, DAG);
5587 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5588 SelectionDAG &DAG) const {
5589 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5591 // Check for non-constant lane.
5592 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5595 EVT VT = Op.getOperand(0).getValueType();
5597 // Insertion/extraction are legal for V128 types.
5598 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5599 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5602 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5603 VT != MVT::v1i64 && VT != MVT::v2f32)
5606 // For V64 types, we perform extraction by expanding the value
5607 // to a V128 type and perform the extraction on that.
5609 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5610 EVT WideTy = WideVec.getValueType();
5612 EVT ExtrTy = WideTy.getVectorElementType();
5613 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5616 // For extractions, we just return the result directly.
5617 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5621 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5622 SelectionDAG &DAG) const {
5623 EVT VT = Op.getOperand(0).getValueType();
5629 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5632 unsigned Val = Cst->getZExtValue();
5634 unsigned Size = Op.getValueType().getSizeInBits();
5638 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5641 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5644 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5647 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5650 llvm_unreachable("Unexpected vector type in extract_subvector!");
5653 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5655 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5661 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5663 if (VT.getVectorNumElements() == 4 &&
5664 (VT.is128BitVector() || VT.is64BitVector())) {
5665 unsigned PFIndexes[4];
5666 for (unsigned i = 0; i != 4; ++i) {
5670 PFIndexes[i] = M[i];
5673 // Compute the index in the perfect shuffle table.
5674 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5675 PFIndexes[2] * 9 + PFIndexes[3];
5676 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5677 unsigned Cost = (PFEntry >> 30);
5685 unsigned DummyUnsigned;
5687 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5688 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5689 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5690 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5691 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5692 isZIPMask(M, VT, DummyUnsigned) ||
5693 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5694 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5695 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5696 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5697 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5700 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5701 /// operand of a vector shift operation, where all the elements of the
5702 /// build_vector must have the same constant integer value.
5703 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5704 // Ignore bit_converts.
5705 while (Op.getOpcode() == ISD::BITCAST)
5706 Op = Op.getOperand(0);
5707 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5708 APInt SplatBits, SplatUndef;
5709 unsigned SplatBitSize;
5711 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5712 HasAnyUndefs, ElementBits) ||
5713 SplatBitSize > ElementBits)
5715 Cnt = SplatBits.getSExtValue();
5719 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5720 /// operand of a vector shift left operation. That value must be in the range:
5721 /// 0 <= Value < ElementBits for a left shift; or
5722 /// 0 <= Value <= ElementBits for a long left shift.
5723 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5724 assert(VT.isVector() && "vector shift count is not a vector type");
5725 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5726 if (!getVShiftImm(Op, ElementBits, Cnt))
5728 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5731 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5732 /// operand of a vector shift right operation. For a shift opcode, the value
5733 /// is positive, but for an intrinsic the value count must be negative. The
5734 /// absolute value must be in the range:
5735 /// 1 <= |Value| <= ElementBits for a right shift; or
5736 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5737 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5739 assert(VT.isVector() && "vector shift count is not a vector type");
5740 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5741 if (!getVShiftImm(Op, ElementBits, Cnt))
5745 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5748 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5749 SelectionDAG &DAG) const {
5750 EVT VT = Op.getValueType();
5754 if (!Op.getOperand(1).getValueType().isVector())
5756 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5758 switch (Op.getOpcode()) {
5760 llvm_unreachable("unexpected shift opcode");
5763 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5764 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5765 DAG.getConstant(Cnt, MVT::i32));
5766 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5767 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5768 Op.getOperand(0), Op.getOperand(1));
5771 // Right shift immediate
5772 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5775 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5776 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5777 DAG.getConstant(Cnt, MVT::i32));
5780 // Right shift register. Note, there is not a shift right register
5781 // instruction, but the shift left register instruction takes a signed
5782 // value, where negative numbers specify a right shift.
5783 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5784 : Intrinsic::aarch64_neon_ushl;
5785 // negate the shift amount
5786 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5787 SDValue NegShiftLeft =
5788 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5789 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5790 return NegShiftLeft;
5796 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5797 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5798 SDLoc dl, SelectionDAG &DAG) {
5799 EVT SrcVT = LHS.getValueType();
5801 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5802 APInt CnstBits(VT.getSizeInBits(), 0);
5803 APInt UndefBits(VT.getSizeInBits(), 0);
5804 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5805 bool IsZero = IsCnst && (CnstBits == 0);
5807 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5811 case AArch64CC::NE: {
5814 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5816 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5817 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5821 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5822 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5825 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5826 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5829 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5830 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5833 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5834 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5838 // If we ignore NaNs then we can use to the MI implementation.
5842 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5843 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5850 case AArch64CC::NE: {
5853 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5855 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5856 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5860 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5861 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5864 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5865 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5868 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5869 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5872 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5873 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5875 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5877 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5880 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5881 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5883 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5885 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5889 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5890 SelectionDAG &DAG) const {
5891 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5892 SDValue LHS = Op.getOperand(0);
5893 SDValue RHS = Op.getOperand(1);
5896 if (LHS.getValueType().getVectorElementType().isInteger()) {
5897 assert(LHS.getValueType() == RHS.getValueType());
5898 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5899 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5903 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5904 LHS.getValueType().getVectorElementType() == MVT::f64);
5906 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5907 // clean. Some of them require two branches to implement.
5908 AArch64CC::CondCode CC1, CC2;
5910 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5912 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5914 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5918 if (CC2 != AArch64CC::AL) {
5920 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5921 if (!Cmp2.getNode())
5924 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5928 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5933 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5934 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5935 /// specified in the intrinsic calls.
5936 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5938 unsigned Intrinsic) const {
5939 switch (Intrinsic) {
5940 case Intrinsic::aarch64_neon_ld2:
5941 case Intrinsic::aarch64_neon_ld3:
5942 case Intrinsic::aarch64_neon_ld4:
5943 case Intrinsic::aarch64_neon_ld1x2:
5944 case Intrinsic::aarch64_neon_ld1x3:
5945 case Intrinsic::aarch64_neon_ld1x4:
5946 case Intrinsic::aarch64_neon_ld2lane:
5947 case Intrinsic::aarch64_neon_ld3lane:
5948 case Intrinsic::aarch64_neon_ld4lane:
5949 case Intrinsic::aarch64_neon_ld2r:
5950 case Intrinsic::aarch64_neon_ld3r:
5951 case Intrinsic::aarch64_neon_ld4r: {
5952 Info.opc = ISD::INTRINSIC_W_CHAIN;
5953 // Conservatively set memVT to the entire set of vectors loaded.
5954 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5955 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5956 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5959 Info.vol = false; // volatile loads with NEON intrinsics not supported
5960 Info.readMem = true;
5961 Info.writeMem = false;
5964 case Intrinsic::aarch64_neon_st2:
5965 case Intrinsic::aarch64_neon_st3:
5966 case Intrinsic::aarch64_neon_st4:
5967 case Intrinsic::aarch64_neon_st1x2:
5968 case Intrinsic::aarch64_neon_st1x3:
5969 case Intrinsic::aarch64_neon_st1x4:
5970 case Intrinsic::aarch64_neon_st2lane:
5971 case Intrinsic::aarch64_neon_st3lane:
5972 case Intrinsic::aarch64_neon_st4lane: {
5973 Info.opc = ISD::INTRINSIC_VOID;
5974 // Conservatively set memVT to the entire set of vectors stored.
5975 unsigned NumElts = 0;
5976 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5977 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5978 if (!ArgTy->isVectorTy())
5980 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5982 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5983 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5986 Info.vol = false; // volatile stores with NEON intrinsics not supported
5987 Info.readMem = false;
5988 Info.writeMem = true;
5991 case Intrinsic::aarch64_ldaxr:
5992 case Intrinsic::aarch64_ldxr: {
5993 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
5994 Info.opc = ISD::INTRINSIC_W_CHAIN;
5995 Info.memVT = MVT::getVT(PtrTy->getElementType());
5996 Info.ptrVal = I.getArgOperand(0);
5998 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6000 Info.readMem = true;
6001 Info.writeMem = false;
6004 case Intrinsic::aarch64_stlxr:
6005 case Intrinsic::aarch64_stxr: {
6006 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6007 Info.opc = ISD::INTRINSIC_W_CHAIN;
6008 Info.memVT = MVT::getVT(PtrTy->getElementType());
6009 Info.ptrVal = I.getArgOperand(1);
6011 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6013 Info.readMem = false;
6014 Info.writeMem = true;
6017 case Intrinsic::aarch64_ldaxp:
6018 case Intrinsic::aarch64_ldxp: {
6019 Info.opc = ISD::INTRINSIC_W_CHAIN;
6020 Info.memVT = MVT::i128;
6021 Info.ptrVal = I.getArgOperand(0);
6025 Info.readMem = true;
6026 Info.writeMem = false;
6029 case Intrinsic::aarch64_stlxp:
6030 case Intrinsic::aarch64_stxp: {
6031 Info.opc = ISD::INTRINSIC_W_CHAIN;
6032 Info.memVT = MVT::i128;
6033 Info.ptrVal = I.getArgOperand(2);
6037 Info.readMem = false;
6038 Info.writeMem = true;
6048 // Truncations from 64-bit GPR to 32-bit GPR is free.
6049 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6050 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6052 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6053 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6054 return NumBits1 > NumBits2;
6056 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6057 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6059 unsigned NumBits1 = VT1.getSizeInBits();
6060 unsigned NumBits2 = VT2.getSizeInBits();
6061 return NumBits1 > NumBits2;
6064 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6066 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6067 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6069 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6070 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6071 return NumBits1 == 32 && NumBits2 == 64;
6073 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6074 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6076 unsigned NumBits1 = VT1.getSizeInBits();
6077 unsigned NumBits2 = VT2.getSizeInBits();
6078 return NumBits1 == 32 && NumBits2 == 64;
6081 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6082 EVT VT1 = Val.getValueType();
6083 if (isZExtFree(VT1, VT2)) {
6087 if (Val.getOpcode() != ISD::LOAD)
6090 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6091 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6092 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6093 VT1.getSizeInBits() <= 32);
6096 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6097 unsigned &RequiredAligment) const {
6098 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6100 // Cyclone supports unaligned accesses.
6101 RequiredAligment = 0;
6102 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6103 return NumBits == 32 || NumBits == 64;
6106 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6107 unsigned &RequiredAligment) const {
6108 if (!LoadedType.isSimple() ||
6109 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6111 // Cyclone supports unaligned accesses.
6112 RequiredAligment = 0;
6113 unsigned NumBits = LoadedType.getSizeInBits();
6114 return NumBits == 32 || NumBits == 64;
6117 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6118 unsigned AlignCheck) {
6119 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6120 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6123 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6124 unsigned SrcAlign, bool IsMemset,
6127 MachineFunction &MF) const {
6128 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6129 // instruction to materialize the v2i64 zero and one store (with restrictive
6130 // addressing mode). Just do two i64 store of zero-registers.
6132 const Function *F = MF.getFunction();
6133 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6134 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6135 Attribute::NoImplicitFloat) &&
6136 (memOpAlign(SrcAlign, DstAlign, 16) ||
6137 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6140 return Size >= 8 ? MVT::i64 : MVT::i32;
6143 // 12-bit optionally shifted immediates are legal for adds.
6144 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6145 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6150 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6151 // immediates is the same as for an add or a sub.
6152 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6155 return isLegalAddImmediate(Immed);
6158 /// isLegalAddressingMode - Return true if the addressing mode represented
6159 /// by AM is legal for this target, for a load/store of the specified type.
6160 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6162 // AArch64 has five basic addressing modes:
6164 // reg + 9-bit signed offset
6165 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6167 // reg + SIZE_IN_BYTES * reg
6169 // No global is ever allowed as a base.
6173 // No reg+reg+imm addressing.
6174 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6177 // check reg + imm case:
6178 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6179 uint64_t NumBytes = 0;
6180 if (Ty->isSized()) {
6181 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6182 NumBytes = NumBits / 8;
6183 if (!isPowerOf2_64(NumBits))
6188 int64_t Offset = AM.BaseOffs;
6190 // 9-bit signed offset
6191 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6194 // 12-bit unsigned offset
6195 unsigned shift = Log2_64(NumBytes);
6196 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6197 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6198 (Offset >> shift) << shift == Offset)
6203 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6205 if (!AM.Scale || AM.Scale == 1 ||
6206 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6211 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6213 // Scaling factors are not free at all.
6214 // Operands | Rt Latency
6215 // -------------------------------------------
6217 // -------------------------------------------
6218 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6219 // Rt, [Xn, Wm, <extend> #imm] |
6220 if (isLegalAddressingMode(AM, Ty))
6221 // Scale represents reg2 * scale, thus account for 1 if
6222 // it is not equal to 0 or 1.
6223 return AM.Scale != 0 && AM.Scale != 1;
6227 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6228 VT = VT.getScalarType();
6233 switch (VT.getSimpleVT().SimpleTy) {
6245 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6246 // LR is a callee-save register, but we must treat it as clobbered by any call
6247 // site. Hence we include LR in the scratch registers, which are in turn added
6248 // as implicit-defs for stackmaps and patchpoints.
6249 static const MCPhysReg ScratchRegs[] = {
6250 AArch64::X16, AArch64::X17, AArch64::LR, 0
6256 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6257 EVT VT = N->getValueType(0);
6258 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6259 // it with shift to let it be lowered to UBFX.
6260 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6261 isa<ConstantSDNode>(N->getOperand(1))) {
6262 uint64_t TruncMask = N->getConstantOperandVal(1);
6263 if (isMask_64(TruncMask) &&
6264 N->getOperand(0).getOpcode() == ISD::SRL &&
6265 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6271 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6273 assert(Ty->isIntegerTy());
6275 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6279 int64_t Val = Imm.getSExtValue();
6280 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6283 if ((int64_t)Val < 0)
6286 Val &= (1LL << 32) - 1;
6288 unsigned LZ = countLeadingZeros((uint64_t)Val);
6289 unsigned Shift = (63 - LZ) / 16;
6290 // MOVZ is free so return true for one or fewer MOVK.
6291 return (Shift < 3) ? true : false;
6294 // Generate SUBS and CSEL for integer abs.
6295 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6296 EVT VT = N->getValueType(0);
6298 SDValue N0 = N->getOperand(0);
6299 SDValue N1 = N->getOperand(1);
6302 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6303 // and change it to SUB and CSEL.
6304 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6305 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6306 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6307 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6308 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6309 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6311 // Generate SUBS & CSEL.
6313 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6314 N0.getOperand(0), DAG.getConstant(0, VT));
6315 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6316 DAG.getConstant(AArch64CC::PL, MVT::i32),
6317 SDValue(Cmp.getNode(), 1));
6322 // performXorCombine - Attempts to handle integer ABS.
6323 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6324 TargetLowering::DAGCombinerInfo &DCI,
6325 const AArch64Subtarget *Subtarget) {
6326 if (DCI.isBeforeLegalizeOps())
6329 return performIntegerAbsCombine(N, DAG);
6332 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6333 TargetLowering::DAGCombinerInfo &DCI,
6334 const AArch64Subtarget *Subtarget) {
6335 if (DCI.isBeforeLegalizeOps())
6338 // Multiplication of a power of two plus/minus one can be done more
6339 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6340 // future CPUs have a cheaper MADD instruction, this may need to be
6341 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6342 // 64-bit is 5 cycles, so this is always a win.
6343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6344 APInt Value = C->getAPIntValue();
6345 EVT VT = N->getValueType(0);
6346 if (Value.isNonNegative()) {
6347 // (mul x, 2^N + 1) => (add (shl x, N), x)
6348 APInt VM1 = Value - 1;
6349 if (VM1.isPowerOf2()) {
6350 SDValue ShiftedVal =
6351 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6352 DAG.getConstant(VM1.logBase2(), MVT::i64));
6353 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6356 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6357 APInt VP1 = Value + 1;
6358 if (VP1.isPowerOf2()) {
6359 SDValue ShiftedVal =
6360 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6361 DAG.getConstant(VP1.logBase2(), MVT::i64));
6362 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6366 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6367 APInt VNM1 = -Value - 1;
6368 if (VNM1.isPowerOf2()) {
6369 SDValue ShiftedVal =
6370 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6371 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6373 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6374 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6376 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6377 APInt VNP1 = -Value + 1;
6378 if (VNP1.isPowerOf2()) {
6379 SDValue ShiftedVal =
6380 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6381 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6382 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6390 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6391 EVT VT = N->getValueType(0);
6392 if (VT != MVT::f32 && VT != MVT::f64)
6394 // Only optimize when the source and destination types have the same width.
6395 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6398 // If the result of an integer load is only used by an integer-to-float
6399 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6400 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6401 SDValue N0 = N->getOperand(0);
6402 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6403 // Do not change the width of a volatile load.
6404 !cast<LoadSDNode>(N0)->isVolatile()) {
6405 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6406 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6407 LN0->getPointerInfo(), LN0->isVolatile(),
6408 LN0->isNonTemporal(), LN0->isInvariant(),
6409 LN0->getAlignment());
6411 // Make sure successors of the original load stay after it by updating them
6412 // to use the new Chain.
6413 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6416 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6417 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6423 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6424 /// searches for and classifies those shifts.
6425 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6427 if (N.getOpcode() == ISD::SHL)
6429 else if (N.getOpcode() == ISD::SRL)
6434 if (!isa<ConstantSDNode>(N.getOperand(1)))
6437 ShiftAmount = N->getConstantOperandVal(1);
6438 Src = N->getOperand(0);
6442 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6443 /// registers viewed as a high/low pair. This function looks for the pattern:
6444 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6445 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6447 static SDValue tryCombineToEXTR(SDNode *N,
6448 TargetLowering::DAGCombinerInfo &DCI) {
6449 SelectionDAG &DAG = DCI.DAG;
6451 EVT VT = N->getValueType(0);
6453 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6455 if (VT != MVT::i32 && VT != MVT::i64)
6459 uint32_t ShiftLHS = 0;
6461 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6465 uint32_t ShiftRHS = 0;
6467 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6470 // If they're both trying to come from the high part of the register, they're
6471 // not really an EXTR.
6472 if (LHSFromHi == RHSFromHi)
6475 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6479 std::swap(LHS, RHS);
6480 std::swap(ShiftLHS, ShiftRHS);
6483 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6484 DAG.getConstant(ShiftRHS, MVT::i64));
6487 static SDValue tryCombineToBSL(SDNode *N,
6488 TargetLowering::DAGCombinerInfo &DCI) {
6489 EVT VT = N->getValueType(0);
6490 SelectionDAG &DAG = DCI.DAG;
6496 SDValue N0 = N->getOperand(0);
6497 if (N0.getOpcode() != ISD::AND)
6500 SDValue N1 = N->getOperand(1);
6501 if (N1.getOpcode() != ISD::AND)
6504 // We only have to look for constant vectors here since the general, variable
6505 // case can be handled in TableGen.
6506 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6507 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6508 for (int i = 1; i >= 0; --i)
6509 for (int j = 1; j >= 0; --j) {
6510 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6511 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6515 bool FoundMatch = true;
6516 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6517 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6518 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6520 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6527 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6528 N0->getOperand(1 - i), N1->getOperand(1 - j));
6534 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6535 const AArch64Subtarget *Subtarget) {
6536 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6537 if (!EnableAArch64ExtrGeneration)
6539 SelectionDAG &DAG = DCI.DAG;
6540 EVT VT = N->getValueType(0);
6542 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6545 SDValue Res = tryCombineToEXTR(N, DCI);
6549 Res = tryCombineToBSL(N, DCI);
6556 static SDValue performBitcastCombine(SDNode *N,
6557 TargetLowering::DAGCombinerInfo &DCI,
6558 SelectionDAG &DAG) {
6559 // Wait 'til after everything is legalized to try this. That way we have
6560 // legal vector types and such.
6561 if (DCI.isBeforeLegalizeOps())
6564 // Remove extraneous bitcasts around an extract_subvector.
6566 // (v4i16 (bitconvert
6567 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6569 // (extract_subvector ((v8i16 ...), (i64 4)))
6571 // Only interested in 64-bit vectors as the ultimate result.
6572 EVT VT = N->getValueType(0);
6575 if (VT.getSimpleVT().getSizeInBits() != 64)
6577 // Is the operand an extract_subvector starting at the beginning or halfway
6578 // point of the vector? A low half may also come through as an
6579 // EXTRACT_SUBREG, so look for that, too.
6580 SDValue Op0 = N->getOperand(0);
6581 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6582 !(Op0->isMachineOpcode() &&
6583 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6585 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6586 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6587 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6589 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6590 if (idx != AArch64::dsub)
6592 // The dsub reference is equivalent to a lane zero subvector reference.
6595 // Look through the bitcast of the input to the extract.
6596 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6598 SDValue Source = Op0->getOperand(0)->getOperand(0);
6599 // If the source type has twice the number of elements as our destination
6600 // type, we know this is an extract of the high or low half of the vector.
6601 EVT SVT = Source->getValueType(0);
6602 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6605 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6607 // Create the simplified form to just extract the low or high half of the
6608 // vector directly rather than bothering with the bitcasts.
6610 unsigned NumElements = VT.getVectorNumElements();
6612 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6613 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6615 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6616 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6622 static SDValue performConcatVectorsCombine(SDNode *N,
6623 TargetLowering::DAGCombinerInfo &DCI,
6624 SelectionDAG &DAG) {
6625 // Wait 'til after everything is legalized to try this. That way we have
6626 // legal vector types and such.
6627 if (DCI.isBeforeLegalizeOps())
6631 EVT VT = N->getValueType(0);
6633 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6634 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6635 // canonicalise to that.
6636 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6637 assert(VT.getVectorElementType().getSizeInBits() == 64);
6638 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6639 WidenVector(N->getOperand(0), DAG),
6640 DAG.getConstant(0, MVT::i64));
6643 // Canonicalise concat_vectors so that the right-hand vector has as few
6644 // bit-casts as possible before its real operation. The primary matching
6645 // destination for these operations will be the narrowing "2" instructions,
6646 // which depend on the operation being performed on this right-hand vector.
6648 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6650 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6652 SDValue Op1 = N->getOperand(1);
6653 if (Op1->getOpcode() != ISD::BITCAST)
6655 SDValue RHS = Op1->getOperand(0);
6656 MVT RHSTy = RHS.getValueType().getSimpleVT();
6657 // If the RHS is not a vector, this is not the pattern we're looking for.
6658 if (!RHSTy.isVector())
6661 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6663 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6664 RHSTy.getVectorNumElements() * 2);
6666 ISD::BITCAST, dl, VT,
6667 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6668 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6671 static SDValue tryCombineFixedPointConvert(SDNode *N,
6672 TargetLowering::DAGCombinerInfo &DCI,
6673 SelectionDAG &DAG) {
6674 // Wait 'til after everything is legalized to try this. That way we have
6675 // legal vector types and such.
6676 if (DCI.isBeforeLegalizeOps())
6678 // Transform a scalar conversion of a value from a lane extract into a
6679 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6680 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6681 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6683 // The second form interacts better with instruction selection and the
6684 // register allocator to avoid cross-class register copies that aren't
6685 // coalescable due to a lane reference.
6687 // Check the operand and see if it originates from a lane extract.
6688 SDValue Op1 = N->getOperand(1);
6689 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6690 // Yep, no additional predication needed. Perform the transform.
6691 SDValue IID = N->getOperand(0);
6692 SDValue Shift = N->getOperand(2);
6693 SDValue Vec = Op1.getOperand(0);
6694 SDValue Lane = Op1.getOperand(1);
6695 EVT ResTy = N->getValueType(0);
6699 // The vector width should be 128 bits by the time we get here, even
6700 // if it started as 64 bits (the extract_vector handling will have
6702 assert(Vec.getValueType().getSizeInBits() == 128 &&
6703 "unexpected vector size on extract_vector_elt!");
6704 if (Vec.getValueType() == MVT::v4i32)
6705 VecResTy = MVT::v4f32;
6706 else if (Vec.getValueType() == MVT::v2i64)
6707 VecResTy = MVT::v2f64;
6709 llvm_unreachable("unexpected vector type!");
6712 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6713 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6718 // AArch64 high-vector "long" operations are formed by performing the non-high
6719 // version on an extract_subvector of each operand which gets the high half:
6721 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6723 // However, there are cases which don't have an extract_high explicitly, but
6724 // have another operation that can be made compatible with one for free. For
6727 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6729 // This routine does the actual conversion of such DUPs, once outer routines
6730 // have determined that everything else is in order.
6731 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6732 // We can handle most types of duplicate, but the lane ones have an extra
6733 // operand saying *which* lane, so we need to know.
6735 switch (N.getOpcode()) {
6736 case AArch64ISD::DUP:
6739 case AArch64ISD::DUPLANE8:
6740 case AArch64ISD::DUPLANE16:
6741 case AArch64ISD::DUPLANE32:
6742 case AArch64ISD::DUPLANE64:
6749 MVT NarrowTy = N.getSimpleValueType();
6750 if (!NarrowTy.is64BitVector())
6753 MVT ElementTy = NarrowTy.getVectorElementType();
6754 unsigned NumElems = NarrowTy.getVectorNumElements();
6755 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6759 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6762 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6764 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6765 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6768 static bool isEssentiallyExtractSubvector(SDValue N) {
6769 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6772 return N.getOpcode() == ISD::BITCAST &&
6773 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6776 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6777 struct GenericSetCCInfo {
6778 const SDValue *Opnd0;
6779 const SDValue *Opnd1;
6783 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6784 struct AArch64SetCCInfo {
6786 AArch64CC::CondCode CC;
6789 /// \brief Helper structure to keep track of SetCC information.
6791 GenericSetCCInfo Generic;
6792 AArch64SetCCInfo AArch64;
6795 /// \brief Helper structure to be able to read SetCC information. If set to
6796 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6797 /// GenericSetCCInfo.
6798 struct SetCCInfoAndKind {
6803 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6805 /// AArch64 lowered one.
6806 /// \p SetCCInfo is filled accordingly.
6807 /// \post SetCCInfo is meanginfull only when this function returns true.
6808 /// \return True when Op is a kind of SET_CC operation.
6809 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6810 // If this is a setcc, this is straight forward.
6811 if (Op.getOpcode() == ISD::SETCC) {
6812 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6813 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6814 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6815 SetCCInfo.IsAArch64 = false;
6818 // Otherwise, check if this is a matching csel instruction.
6822 if (Op.getOpcode() != AArch64ISD::CSEL)
6824 // Set the information about the operands.
6825 // TODO: we want the operands of the Cmp not the csel
6826 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6827 SetCCInfo.IsAArch64 = true;
6828 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6829 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6831 // Check that the operands matches the constraints:
6832 // (1) Both operands must be constants.
6833 // (2) One must be 1 and the other must be 0.
6834 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6835 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6838 if (!TValue || !FValue)
6842 if (!TValue->isOne()) {
6843 // Update the comparison when we are interested in !cc.
6844 std::swap(TValue, FValue);
6845 SetCCInfo.Info.AArch64.CC =
6846 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6848 return TValue->isOne() && FValue->isNullValue();
6851 // Returns true if Op is setcc or zext of setcc.
6852 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6853 if (isSetCC(Op, Info))
6855 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6856 isSetCC(Op->getOperand(0), Info));
6859 // The folding we want to perform is:
6860 // (add x, [zext] (setcc cc ...) )
6862 // (csel x, (add x, 1), !cc ...)
6864 // The latter will get matched to a CSINC instruction.
6865 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6866 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6867 SDValue LHS = Op->getOperand(0);
6868 SDValue RHS = Op->getOperand(1);
6869 SetCCInfoAndKind InfoAndKind;
6871 // If neither operand is a SET_CC, give up.
6872 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6873 std::swap(LHS, RHS);
6874 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6878 // FIXME: This could be generatized to work for FP comparisons.
6879 EVT CmpVT = InfoAndKind.IsAArch64
6880 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
6881 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6882 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6888 if (InfoAndKind.IsAArch64) {
6889 CCVal = DAG.getConstant(
6890 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
6891 Cmp = *InfoAndKind.Info.AArch64.Cmp;
6893 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6894 *InfoAndKind.Info.Generic.Opnd1,
6895 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6898 EVT VT = Op->getValueType(0);
6899 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6900 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6903 // The basic add/sub long vector instructions have variants with "2" on the end
6904 // which act on the high-half of their inputs. They are normally matched by
6907 // (add (zeroext (extract_high LHS)),
6908 // (zeroext (extract_high RHS)))
6909 // -> uaddl2 vD, vN, vM
6911 // However, if one of the extracts is something like a duplicate, this
6912 // instruction can still be used profitably. This function puts the DAG into a
6913 // more appropriate form for those patterns to trigger.
6914 static SDValue performAddSubLongCombine(SDNode *N,
6915 TargetLowering::DAGCombinerInfo &DCI,
6916 SelectionDAG &DAG) {
6917 if (DCI.isBeforeLegalizeOps())
6920 MVT VT = N->getSimpleValueType(0);
6921 if (!VT.is128BitVector()) {
6922 if (N->getOpcode() == ISD::ADD)
6923 return performSetccAddFolding(N, DAG);
6927 // Make sure both branches are extended in the same way.
6928 SDValue LHS = N->getOperand(0);
6929 SDValue RHS = N->getOperand(1);
6930 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
6931 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
6932 LHS.getOpcode() != RHS.getOpcode())
6935 unsigned ExtType = LHS.getOpcode();
6937 // It's not worth doing if at least one of the inputs isn't already an
6938 // extract, but we don't know which it'll be so we have to try both.
6939 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
6940 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
6944 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6945 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
6946 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
6950 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
6953 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
6956 // Massage DAGs which we can use the high-half "long" operations on into
6957 // something isel will recognize better. E.g.
6959 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
6960 // (aarch64_neon_umull (extract_high (v2i64 vec)))
6961 // (extract_high (v2i64 (dup128 scalar)))))
6963 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
6964 TargetLowering::DAGCombinerInfo &DCI,
6965 SelectionDAG &DAG) {
6966 if (DCI.isBeforeLegalizeOps())
6969 SDValue LHS = N->getOperand(1);
6970 SDValue RHS = N->getOperand(2);
6971 assert(LHS.getValueType().is64BitVector() &&
6972 RHS.getValueType().is64BitVector() &&
6973 "unexpected shape for long operation");
6975 // Either node could be a DUP, but it's not worth doing both of them (you'd
6976 // just as well use the non-high version) so look for a corresponding extract
6977 // operation on the other "wing".
6978 if (isEssentiallyExtractSubvector(LHS)) {
6979 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
6982 } else if (isEssentiallyExtractSubvector(RHS)) {
6983 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
6988 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
6989 N->getOperand(0), LHS, RHS);
6992 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
6993 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
6994 unsigned ElemBits = ElemTy.getSizeInBits();
6996 int64_t ShiftAmount;
6997 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
6998 APInt SplatValue, SplatUndef;
6999 unsigned SplatBitSize;
7001 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7002 HasAnyUndefs, ElemBits) ||
7003 SplatBitSize != ElemBits)
7006 ShiftAmount = SplatValue.getSExtValue();
7007 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7008 ShiftAmount = CVN->getSExtValue();
7016 llvm_unreachable("Unknown shift intrinsic");
7017 case Intrinsic::aarch64_neon_sqshl:
7018 Opcode = AArch64ISD::SQSHL_I;
7019 IsRightShift = false;
7021 case Intrinsic::aarch64_neon_uqshl:
7022 Opcode = AArch64ISD::UQSHL_I;
7023 IsRightShift = false;
7025 case Intrinsic::aarch64_neon_srshl:
7026 Opcode = AArch64ISD::SRSHR_I;
7027 IsRightShift = true;
7029 case Intrinsic::aarch64_neon_urshl:
7030 Opcode = AArch64ISD::URSHR_I;
7031 IsRightShift = true;
7033 case Intrinsic::aarch64_neon_sqshlu:
7034 Opcode = AArch64ISD::SQSHLU_I;
7035 IsRightShift = false;
7039 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7040 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7041 DAG.getConstant(-ShiftAmount, MVT::i32));
7042 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7043 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7044 DAG.getConstant(ShiftAmount, MVT::i32));
7049 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7050 // the intrinsics must be legal and take an i32, this means there's almost
7051 // certainly going to be a zext in the DAG which we can eliminate.
7052 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7053 SDValue AndN = N->getOperand(2);
7054 if (AndN.getOpcode() != ISD::AND)
7057 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7058 if (!CMask || CMask->getZExtValue() != Mask)
7061 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7062 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7065 static SDValue performIntrinsicCombine(SDNode *N,
7066 TargetLowering::DAGCombinerInfo &DCI,
7067 const AArch64Subtarget *Subtarget) {
7068 SelectionDAG &DAG = DCI.DAG;
7069 unsigned IID = getIntrinsicID(N);
7073 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7074 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7075 return tryCombineFixedPointConvert(N, DCI, DAG);
7077 case Intrinsic::aarch64_neon_fmax:
7078 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7079 N->getOperand(1), N->getOperand(2));
7080 case Intrinsic::aarch64_neon_fmin:
7081 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7082 N->getOperand(1), N->getOperand(2));
7083 case Intrinsic::aarch64_neon_smull:
7084 case Intrinsic::aarch64_neon_umull:
7085 case Intrinsic::aarch64_neon_pmull:
7086 case Intrinsic::aarch64_neon_sqdmull:
7087 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7088 case Intrinsic::aarch64_neon_sqshl:
7089 case Intrinsic::aarch64_neon_uqshl:
7090 case Intrinsic::aarch64_neon_sqshlu:
7091 case Intrinsic::aarch64_neon_srshl:
7092 case Intrinsic::aarch64_neon_urshl:
7093 return tryCombineShiftImm(IID, N, DAG);
7094 case Intrinsic::aarch64_crc32b:
7095 case Intrinsic::aarch64_crc32cb:
7096 return tryCombineCRC32(0xff, N, DAG);
7097 case Intrinsic::aarch64_crc32h:
7098 case Intrinsic::aarch64_crc32ch:
7099 return tryCombineCRC32(0xffff, N, DAG);
7104 static SDValue performExtendCombine(SDNode *N,
7105 TargetLowering::DAGCombinerInfo &DCI,
7106 SelectionDAG &DAG) {
7107 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7108 // we can convert that DUP into another extract_high (of a bigger DUP), which
7109 // helps the backend to decide that an sabdl2 would be useful, saving a real
7110 // extract_high operation.
7111 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7112 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7113 SDNode *ABDNode = N->getOperand(0).getNode();
7114 unsigned IID = getIntrinsicID(ABDNode);
7115 if (IID == Intrinsic::aarch64_neon_sabd ||
7116 IID == Intrinsic::aarch64_neon_uabd) {
7117 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7118 if (!NewABD.getNode())
7121 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7126 // This is effectively a custom type legalization for AArch64.
7128 // Type legalization will split an extend of a small, legal, type to a larger
7129 // illegal type by first splitting the destination type, often creating
7130 // illegal source types, which then get legalized in isel-confusing ways,
7131 // leading to really terrible codegen. E.g.,
7132 // %result = v8i32 sext v8i8 %value
7134 // %losrc = extract_subreg %value, ...
7135 // %hisrc = extract_subreg %value, ...
7136 // %lo = v4i32 sext v4i8 %losrc
7137 // %hi = v4i32 sext v4i8 %hisrc
7138 // Things go rapidly downhill from there.
7140 // For AArch64, the [sz]ext vector instructions can only go up one element
7141 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7142 // take two instructions.
7144 // This implies that the most efficient way to do the extend from v8i8
7145 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7146 // the normal splitting to happen for the v8i16->v8i32.
7148 // This is pre-legalization to catch some cases where the default
7149 // type legalization will create ill-tempered code.
7150 if (!DCI.isBeforeLegalizeOps())
7153 // We're only interested in cleaning things up for non-legal vector types
7154 // here. If both the source and destination are legal, things will just
7155 // work naturally without any fiddling.
7156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7157 EVT ResVT = N->getValueType(0);
7158 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7160 // If the vector type isn't a simple VT, it's beyond the scope of what
7161 // we're worried about here. Let legalization do its thing and hope for
7163 if (!ResVT.isSimple())
7166 SDValue Src = N->getOperand(0);
7167 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7168 // If the source VT is a 64-bit vector, we can play games and get the
7169 // better results we want.
7170 if (SrcVT.getSizeInBits() != 64)
7173 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7174 unsigned ElementCount = SrcVT.getVectorNumElements();
7175 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7177 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7179 // Now split the rest of the operation into two halves, each with a 64
7183 unsigned NumElements = ResVT.getVectorNumElements();
7184 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7185 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7186 ResVT.getVectorElementType(), NumElements / 2);
7188 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7189 LoVT.getVectorNumElements());
7190 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7191 DAG.getIntPtrConstant(0));
7192 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7193 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7194 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7195 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7197 // Now combine the parts back together so we still have a single result
7198 // like the combiner expects.
7199 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7202 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7203 /// value. The load store optimizer pass will merge them to store pair stores.
7204 /// This has better performance than a splat of the scalar followed by a split
7205 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7206 /// followed by an ext.b and two stores.
7207 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7208 SDValue StVal = St->getValue();
7209 EVT VT = StVal.getValueType();
7211 // Don't replace floating point stores, they possibly won't be transformed to
7212 // stp because of the store pair suppress pass.
7213 if (VT.isFloatingPoint())
7216 // Check for insert vector elements.
7217 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7220 // We can express a splat as store pair(s) for 2 or 4 elements.
7221 unsigned NumVecElts = VT.getVectorNumElements();
7222 if (NumVecElts != 4 && NumVecElts != 2)
7224 SDValue SplatVal = StVal.getOperand(1);
7225 unsigned RemainInsertElts = NumVecElts - 1;
7227 // Check that this is a splat.
7228 while (--RemainInsertElts) {
7229 SDValue NextInsertElt = StVal.getOperand(0);
7230 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7232 if (NextInsertElt.getOperand(1) != SplatVal)
7234 StVal = NextInsertElt;
7236 unsigned OrigAlignment = St->getAlignment();
7237 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7238 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7240 // Create scalar stores. This is at least as good as the code sequence for a
7241 // split unaligned store wich is a dup.s, ext.b, and two stores.
7242 // Most of the time the three stores should be replaced by store pair
7243 // instructions (stp).
7245 SDValue BasePtr = St->getBasePtr();
7247 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7248 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7250 unsigned Offset = EltOffset;
7251 while (--NumVecElts) {
7252 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7253 DAG.getConstant(Offset, MVT::i64));
7254 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7255 St->getPointerInfo(), St->isVolatile(),
7256 St->isNonTemporal(), Alignment);
7257 Offset += EltOffset;
7262 static SDValue performSTORECombine(SDNode *N,
7263 TargetLowering::DAGCombinerInfo &DCI,
7265 const AArch64Subtarget *Subtarget) {
7266 if (!DCI.isBeforeLegalize())
7269 StoreSDNode *S = cast<StoreSDNode>(N);
7270 if (S->isVolatile())
7273 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7274 // page boundries. We want to split such stores.
7275 if (!Subtarget->isCyclone())
7278 // Don't split at Oz.
7279 MachineFunction &MF = DAG.getMachineFunction();
7280 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7281 AttributeSet::FunctionIndex, Attribute::MinSize);
7285 SDValue StVal = S->getValue();
7286 EVT VT = StVal.getValueType();
7288 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7289 // those up regresses performance on micro-benchmarks and olden/bh.
7290 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7293 // Split unaligned 16B stores. They are terrible for performance.
7294 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7295 // extensions can use this to mark that it does not want splitting to happen
7296 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7297 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7298 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7299 S->getAlignment() <= 2)
7302 // If we get a splat of a scalar convert this vector store to a store of
7303 // scalars. They will be merged into store pairs thereby removing two
7305 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7306 if (ReplacedSplat != SDValue())
7307 return ReplacedSplat;
7310 unsigned NumElts = VT.getVectorNumElements() / 2;
7311 // Split VT into two.
7313 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7314 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7315 DAG.getIntPtrConstant(0));
7316 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7317 DAG.getIntPtrConstant(NumElts));
7318 SDValue BasePtr = S->getBasePtr();
7320 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7321 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7322 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7323 DAG.getConstant(8, MVT::i64));
7324 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7325 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7329 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7330 /// post-increment LD1R.
7331 static SDValue performPostLD1Combine(SDNode *N,
7332 TargetLowering::DAGCombinerInfo &DCI,
7334 if (DCI.isBeforeLegalizeOps())
7337 SelectionDAG &DAG = DCI.DAG;
7338 EVT VT = N->getValueType(0);
7340 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7341 SDNode *LD = N->getOperand(LoadIdx).getNode();
7342 // If it is not LOAD, can not do such combine.
7343 if (LD->getOpcode() != ISD::LOAD)
7346 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7347 EVT MemVT = LoadSDN->getMemoryVT();
7348 // Check if memory operand is the same type as the vector element.
7349 if (MemVT != VT.getVectorElementType())
7352 // Check if there are other uses. If so, do not combine as it will introduce
7354 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7356 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7362 SDValue Addr = LD->getOperand(1);
7363 SDValue Vector = N->getOperand(0);
7364 // Search for a use of the address operand that is an increment.
7365 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7366 Addr.getNode()->use_end(); UI != UE; ++UI) {
7368 if (User->getOpcode() != ISD::ADD
7369 || UI.getUse().getResNo() != Addr.getResNo())
7372 // Check that the add is independent of the load. Otherwise, folding it
7373 // would create a cycle.
7374 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7376 // Also check that add is not used in the vector operand. This would also
7378 if (User->isPredecessorOf(Vector.getNode()))
7381 // If the increment is a constant, it must match the memory ref size.
7382 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7383 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7384 uint32_t IncVal = CInc->getZExtValue();
7385 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7386 if (IncVal != NumBytes)
7388 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7391 SmallVector<SDValue, 8> Ops;
7392 Ops.push_back(LD->getOperand(0)); // Chain
7394 Ops.push_back(Vector); // The vector to be inserted
7395 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7397 Ops.push_back(Addr);
7400 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7401 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7402 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7403 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7405 LoadSDN->getMemOperand());
7408 std::vector<SDValue> NewResults;
7409 NewResults.push_back(SDValue(LD, 0)); // The result of load
7410 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7411 DCI.CombineTo(LD, NewResults);
7412 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7413 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7420 /// Target-specific DAG combine function for NEON load/store intrinsics
7421 /// to merge base address updates.
7422 static SDValue performNEONPostLDSTCombine(SDNode *N,
7423 TargetLowering::DAGCombinerInfo &DCI,
7424 SelectionDAG &DAG) {
7425 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7428 unsigned AddrOpIdx = N->getNumOperands() - 1;
7429 SDValue Addr = N->getOperand(AddrOpIdx);
7431 // Search for a use of the address operand that is an increment.
7432 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7433 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7435 if (User->getOpcode() != ISD::ADD ||
7436 UI.getUse().getResNo() != Addr.getResNo())
7439 // Check that the add is independent of the load/store. Otherwise, folding
7440 // it would create a cycle.
7441 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7444 // Find the new opcode for the updating load/store.
7445 bool IsStore = false;
7446 bool IsLaneOp = false;
7447 bool IsDupOp = false;
7448 unsigned NewOpc = 0;
7449 unsigned NumVecs = 0;
7450 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7452 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7453 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7455 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7457 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7459 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7460 NumVecs = 2; IsStore = true; break;
7461 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7462 NumVecs = 3; IsStore = true; break;
7463 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7464 NumVecs = 4; IsStore = true; break;
7465 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7467 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7469 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7471 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7472 NumVecs = 2; IsStore = true; break;
7473 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7474 NumVecs = 3; IsStore = true; break;
7475 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7476 NumVecs = 4; IsStore = true; break;
7477 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7478 NumVecs = 2; IsDupOp = true; break;
7479 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7480 NumVecs = 3; IsDupOp = true; break;
7481 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7482 NumVecs = 4; IsDupOp = true; break;
7483 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7484 NumVecs = 2; IsLaneOp = true; break;
7485 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7486 NumVecs = 3; IsLaneOp = true; break;
7487 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7488 NumVecs = 4; IsLaneOp = true; break;
7489 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7490 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7491 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7492 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7493 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7494 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7499 VecTy = N->getOperand(2).getValueType();
7501 VecTy = N->getValueType(0);
7503 // If the increment is a constant, it must match the memory ref size.
7504 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7505 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7506 uint32_t IncVal = CInc->getZExtValue();
7507 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7508 if (IsLaneOp || IsDupOp)
7509 NumBytes /= VecTy.getVectorNumElements();
7510 if (IncVal != NumBytes)
7512 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7514 SmallVector<SDValue, 8> Ops;
7515 Ops.push_back(N->getOperand(0)); // Incoming chain
7516 // Load lane and store have vector list as input.
7517 if (IsLaneOp || IsStore)
7518 for (unsigned i = 2; i < AddrOpIdx; ++i)
7519 Ops.push_back(N->getOperand(i));
7520 Ops.push_back(Addr); // Base register
7525 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7527 for (n = 0; n < NumResultVecs; ++n)
7529 Tys[n++] = MVT::i64; // Type of write back register
7530 Tys[n] = MVT::Other; // Type of the chain
7531 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7533 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7534 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7535 MemInt->getMemoryVT(),
7536 MemInt->getMemOperand());
7539 std::vector<SDValue> NewResults;
7540 for (unsigned i = 0; i < NumResultVecs; ++i) {
7541 NewResults.push_back(SDValue(UpdN.getNode(), i));
7543 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7544 DCI.CombineTo(N, NewResults);
7545 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7552 // Optimize compare with zero and branch.
7553 static SDValue performBRCONDCombine(SDNode *N,
7554 TargetLowering::DAGCombinerInfo &DCI,
7555 SelectionDAG &DAG) {
7556 SDValue Chain = N->getOperand(0);
7557 SDValue Dest = N->getOperand(1);
7558 SDValue CCVal = N->getOperand(2);
7559 SDValue Cmp = N->getOperand(3);
7561 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7562 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7563 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7566 unsigned CmpOpc = Cmp.getOpcode();
7567 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7570 // Only attempt folding if there is only one use of the flag and no use of the
7572 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7575 SDValue LHS = Cmp.getOperand(0);
7576 SDValue RHS = Cmp.getOperand(1);
7578 assert(LHS.getValueType() == RHS.getValueType() &&
7579 "Expected the value type to be the same for both operands!");
7580 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7583 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7584 std::swap(LHS, RHS);
7586 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7589 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7590 LHS.getOpcode() == ISD::SRL)
7593 // Fold the compare into the branch instruction.
7595 if (CC == AArch64CC::EQ)
7596 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7598 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7600 // Do not add new nodes to DAG combiner worklist.
7601 DCI.CombineTo(N, BR, false);
7606 // vselect (v1i1 setcc) ->
7607 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7608 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7609 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7611 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7612 SDValue N0 = N->getOperand(0);
7613 EVT CCVT = N0.getValueType();
7615 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7616 CCVT.getVectorElementType() != MVT::i1)
7619 EVT ResVT = N->getValueType(0);
7620 EVT CmpVT = N0.getOperand(0).getValueType();
7621 // Only combine when the result type is of the same size as the compared
7623 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7626 SDValue IfTrue = N->getOperand(1);
7627 SDValue IfFalse = N->getOperand(2);
7629 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7630 N0.getOperand(0), N0.getOperand(1),
7631 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7632 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7636 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7637 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7638 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7639 /// with a vector one followed by a DUP shuffle on the result.
7640 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7641 SDValue N0 = N->getOperand(0);
7642 EVT ResVT = N->getValueType(0);
7644 if (!N->getOperand(1).getValueType().isVector())
7647 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7652 EVT SrcVT = N0.getOperand(0).getValueType();
7653 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7654 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7655 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7657 // First perform a vector comparison, where lane 0 is the one we're interested
7660 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7662 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7663 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7665 // Now duplicate the comparison mask we want across all other lanes.
7666 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7667 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7668 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7671 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7674 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7675 DAGCombinerInfo &DCI) const {
7676 SelectionDAG &DAG = DCI.DAG;
7677 switch (N->getOpcode()) {
7682 return performAddSubLongCombine(N, DCI, DAG);
7684 return performXorCombine(N, DAG, DCI, Subtarget);
7686 return performMulCombine(N, DAG, DCI, Subtarget);
7687 case ISD::SINT_TO_FP:
7688 case ISD::UINT_TO_FP:
7689 return performIntToFpCombine(N, DAG);
7691 return performORCombine(N, DCI, Subtarget);
7692 case ISD::INTRINSIC_WO_CHAIN:
7693 return performIntrinsicCombine(N, DCI, Subtarget);
7694 case ISD::ANY_EXTEND:
7695 case ISD::ZERO_EXTEND:
7696 case ISD::SIGN_EXTEND:
7697 return performExtendCombine(N, DCI, DAG);
7699 return performBitcastCombine(N, DCI, DAG);
7700 case ISD::CONCAT_VECTORS:
7701 return performConcatVectorsCombine(N, DCI, DAG);
7703 return performSelectCombine(N, DAG);
7705 return performVSelectCombine(N, DCI.DAG);
7707 return performSTORECombine(N, DCI, DAG, Subtarget);
7708 case AArch64ISD::BRCOND:
7709 return performBRCONDCombine(N, DCI, DAG);
7710 case AArch64ISD::DUP:
7711 return performPostLD1Combine(N, DCI, false);
7712 case ISD::INSERT_VECTOR_ELT:
7713 return performPostLD1Combine(N, DCI, true);
7714 case ISD::INTRINSIC_VOID:
7715 case ISD::INTRINSIC_W_CHAIN:
7716 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7717 case Intrinsic::aarch64_neon_ld2:
7718 case Intrinsic::aarch64_neon_ld3:
7719 case Intrinsic::aarch64_neon_ld4:
7720 case Intrinsic::aarch64_neon_ld1x2:
7721 case Intrinsic::aarch64_neon_ld1x3:
7722 case Intrinsic::aarch64_neon_ld1x4:
7723 case Intrinsic::aarch64_neon_ld2lane:
7724 case Intrinsic::aarch64_neon_ld3lane:
7725 case Intrinsic::aarch64_neon_ld4lane:
7726 case Intrinsic::aarch64_neon_ld2r:
7727 case Intrinsic::aarch64_neon_ld3r:
7728 case Intrinsic::aarch64_neon_ld4r:
7729 case Intrinsic::aarch64_neon_st2:
7730 case Intrinsic::aarch64_neon_st3:
7731 case Intrinsic::aarch64_neon_st4:
7732 case Intrinsic::aarch64_neon_st1x2:
7733 case Intrinsic::aarch64_neon_st1x3:
7734 case Intrinsic::aarch64_neon_st1x4:
7735 case Intrinsic::aarch64_neon_st2lane:
7736 case Intrinsic::aarch64_neon_st3lane:
7737 case Intrinsic::aarch64_neon_st4lane:
7738 return performNEONPostLDSTCombine(N, DCI, DAG);
7746 // Check if the return value is used as only a return value, as otherwise
7747 // we can't perform a tail-call. In particular, we need to check for
7748 // target ISD nodes that are returns and any other "odd" constructs
7749 // that the generic analysis code won't necessarily catch.
7750 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7751 SDValue &Chain) const {
7752 if (N->getNumValues() != 1)
7754 if (!N->hasNUsesOfValue(1, 0))
7757 SDValue TCChain = Chain;
7758 SDNode *Copy = *N->use_begin();
7759 if (Copy->getOpcode() == ISD::CopyToReg) {
7760 // If the copy has a glue operand, we conservatively assume it isn't safe to
7761 // perform a tail call.
7762 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7765 TCChain = Copy->getOperand(0);
7766 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7769 bool HasRet = false;
7770 for (SDNode *Node : Copy->uses()) {
7771 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7783 // Return whether the an instruction can potentially be optimized to a tail
7784 // call. This will cause the optimizers to attempt to move, or duplicate,
7785 // return instructions to help enable tail call optimizations for this
7787 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7788 if (!CI->isTailCall())
7794 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7796 ISD::MemIndexedMode &AM,
7798 SelectionDAG &DAG) const {
7799 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7802 Base = Op->getOperand(0);
7803 // All of the indexed addressing mode instructions take a signed
7804 // 9 bit immediate offset.
7805 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7806 int64_t RHSC = (int64_t)RHS->getZExtValue();
7807 if (RHSC >= 256 || RHSC <= -256)
7809 IsInc = (Op->getOpcode() == ISD::ADD);
7810 Offset = Op->getOperand(1);
7816 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7818 ISD::MemIndexedMode &AM,
7819 SelectionDAG &DAG) const {
7822 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7823 VT = LD->getMemoryVT();
7824 Ptr = LD->getBasePtr();
7825 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7826 VT = ST->getMemoryVT();
7827 Ptr = ST->getBasePtr();
7832 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7834 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7838 bool AArch64TargetLowering::getPostIndexedAddressParts(
7839 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7840 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7843 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7844 VT = LD->getMemoryVT();
7845 Ptr = LD->getBasePtr();
7846 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7847 VT = ST->getMemoryVT();
7848 Ptr = ST->getBasePtr();
7853 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7855 // Post-indexing updates the base, so it's not a valid transform
7856 // if that's not the same as the load's pointer.
7859 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7863 void AArch64TargetLowering::ReplaceNodeResults(
7864 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
7865 switch (N->getOpcode()) {
7867 llvm_unreachable("Don't know how to custom expand this");
7868 case ISD::FP_TO_UINT:
7869 case ISD::FP_TO_SINT:
7870 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7871 // Let normal code take care of it by not adding anything to Results.
7876 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7877 // Loads and stores less than 128-bits are already atomic; ones above that
7878 // are doomed anyway, so defer to the default libcall and blame the OS when
7880 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7881 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7882 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7883 return LI->getType()->getPrimitiveSizeInBits() == 128;
7885 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7886 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7889 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7890 AtomicOrdering Ord) const {
7891 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7892 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7894 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7896 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7897 // intrinsic must return {i64, i64} and we have to recombine them into a
7898 // single i128 here.
7899 if (ValTy->getPrimitiveSizeInBits() == 128) {
7901 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
7902 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7904 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7905 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
7907 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
7908 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
7909 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
7910 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
7911 return Builder.CreateOr(
7912 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
7915 Type *Tys[] = { Addr->getType() };
7917 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
7918 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
7920 return Builder.CreateTruncOrBitCast(
7921 Builder.CreateCall(Ldxr, Addr),
7922 cast<PointerType>(Addr->getType())->getElementType());
7925 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
7926 Value *Val, Value *Addr,
7927 AtomicOrdering Ord) const {
7928 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7930 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7932 // Since the intrinsics must have legal type, the i128 intrinsics take two
7933 // parameters: "i64, i64". We must marshal Val into the appropriate form
7935 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
7937 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
7938 Function *Stxr = Intrinsic::getDeclaration(M, Int);
7939 Type *Int64Ty = Type::getInt64Ty(M->getContext());
7941 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
7942 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
7943 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7944 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
7948 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
7949 Type *Tys[] = { Addr->getType() };
7950 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
7952 return Builder.CreateCall2(
7953 Stxr, Builder.CreateZExtOrBitCast(
7954 Val, Stxr->getFunctionType()->getParamType(0)),