1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 namespace AArch64ISD {
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
30 CALL, // Function call.
32 // Almost the same as a normal call node, except that a TLSDesc relocation is
33 // needed so the linker can relax it correctly if possible.
35 ADRP, // Page address of a TargetGlobalAddress operand.
36 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
37 LOADgot, // Load from automatically generated descriptor (e.g. Global
38 // Offset Table, TLS record).
39 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
40 BRCOND, // Conditional branch instruction; "b.cond".
42 FCSEL, // Conditional move instruction.
43 CSINV, // Conditional select invert.
44 CSNEG, // Conditional select negate.
45 CSINC, // Conditional select increment.
47 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
51 SBC, // adc, sbc instructions
53 // Arithmetic instructions which write flags.
60 // Floating point comparison
63 // Floating point max and min instructions.
70 // Scalar-to-vector duplication
77 // Vector immedate moves
86 // Vector immediate ops
90 // Vector bit select: similar to ISD::VSELECT but not all bits within an
91 // element must be identical.
94 // Vector arithmetic negation
109 // Vector shift by scalar
114 // Vector shift by scalar (again)
121 // Vector comparisons
131 // Vector zero comparisons
143 // Vector bitwise negation
146 // Vector bitwise selection
149 // Compare-and-branch
158 // Custom prefetch handling
161 // {s|u}int to FP within a FP register.
165 // NEON Load/Store with post-increment base updates
166 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
191 } // end namespace AArch64ISD
193 class AArch64Subtarget;
194 class AArch64TargetMachine;
196 class AArch64TargetLowering : public TargetLowering {
197 bool RequireStrictAlign;
200 explicit AArch64TargetLowering(TargetMachine &TM);
202 /// Selects the correct CCAssignFn for a given CallingConvention value.
203 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
205 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
206 /// Mask are known to be either zero or one and return them in the
207 /// KnownZero/KnownOne bitsets.
208 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
209 APInt &KnownOne, const SelectionDAG &DAG,
210 unsigned Depth = 0) const override;
212 MVT getScalarShiftAmountTy(EVT LHSTy) const override;
214 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
215 /// unaligned memory accesses. of the specified type.
216 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
218 bool *Fast = nullptr) const override {
219 if (RequireStrictAlign)
221 // FIXME: True for Cyclone, but not necessary others.
227 /// LowerOperation - Provide custom lowering hooks for some operations.
228 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
230 const char *getTargetNodeName(unsigned Opcode) const override;
232 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
234 /// getFunctionAlignment - Return the Log2 alignment of this function.
235 unsigned getFunctionAlignment(const Function *F) const;
237 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
238 /// be used for loads / stores from the global.
239 unsigned getMaximalGlobalOffset() const override;
241 /// Returns true if a cast between SrcAS and DestAS is a noop.
242 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
243 // Addrspacecasts are always noops.
247 /// createFastISel - This method returns a target specific FastISel object,
248 /// or null if the target does not support "fast" ISel.
249 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
250 const TargetLibraryInfo *libInfo) const override;
252 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
254 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
256 /// isShuffleMaskLegal - Return true if the given shuffle mask can be
257 /// codegen'd directly, or if it should be stack expanded.
258 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
260 /// getSetCCResultType - Return the ISD::SETCC ValueType
261 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
263 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
265 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
266 MachineBasicBlock *BB) const;
269 EmitInstrWithCustomInserter(MachineInstr *MI,
270 MachineBasicBlock *MBB) const override;
272 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
273 unsigned Intrinsic) const override;
275 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
276 bool isTruncateFree(EVT VT1, EVT VT2) const override;
278 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
279 bool isZExtFree(EVT VT1, EVT VT2) const override;
280 bool isZExtFree(SDValue Val, EVT VT2) const override;
282 bool hasPairedLoad(Type *LoadedType,
283 unsigned &RequiredAligment) const override;
284 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
286 bool isLegalAddImmediate(int64_t) const override;
287 bool isLegalICmpImmediate(int64_t) const override;
289 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
290 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
291 MachineFunction &MF) const override;
293 /// isLegalAddressingMode - Return true if the addressing mode represented
294 /// by AM is legal for this target, for a load/store of the specified type.
295 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
297 /// \brief Return the cost of the scaling factor used in the addressing
298 /// mode represented by AM for this target, for a load/store
299 /// of the specified type.
300 /// If the AM is supported, the return value must be >= 0.
301 /// If the AM is not supported, it returns a negative value.
302 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
304 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
305 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
306 /// expanded to FMAs when this method returns true, otherwise fmuladd is
307 /// expanded to fmul + fadd.
308 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
310 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
312 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
313 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
315 /// \brief Returns true if it is beneficial to convert a load of a constant
316 /// to just the constant itself.
317 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
318 Type *Ty) const override;
320 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
321 AtomicOrdering Ord) const override;
322 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
323 Value *Addr, AtomicOrdering Ord) const override;
325 bool shouldExpandAtomicInIR(Instruction *Inst) const override;
327 bool useLoadStackGuardNode() const override;
328 TargetLoweringBase::LegalizeTypeAction
329 getPreferredVectorAction(EVT VT) const override;
332 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
333 /// make the right decision when generating code for different targets.
334 const AArch64Subtarget *Subtarget;
336 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
337 void addDRTypeForNEON(MVT VT);
338 void addQRTypeForNEON(MVT VT);
341 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
342 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
344 SmallVectorImpl<SDValue> &InVals) const override;
346 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
347 SmallVectorImpl<SDValue> &InVals) const override;
349 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
350 CallingConv::ID CallConv, bool isVarArg,
351 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
352 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
353 bool isThisReturn, SDValue ThisVal) const;
355 bool isEligibleForTailCallOptimization(
356 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
357 bool isCalleeStructRet, bool isCallerStructRet,
358 const SmallVectorImpl<ISD::OutputArg> &Outs,
359 const SmallVectorImpl<SDValue> &OutVals,
360 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
362 /// Finds the incoming stack arguments which overlap the given fixed stack
363 /// object and incorporates their load into the current chain. This prevents
364 /// an upcoming store from clobbering the stack argument before it's used.
365 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
366 MachineFrameInfo *MFI, int ClobberedFI) const;
368 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
370 bool IsTailCallConvention(CallingConv::ID CallCC) const;
372 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
373 SDValue &Chain) const;
375 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
377 const SmallVectorImpl<ISD::OutputArg> &Outs,
378 LLVMContext &Context) const override;
380 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
381 const SmallVectorImpl<ISD::OutputArg> &Outs,
382 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
383 SelectionDAG &DAG) const override;
385 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
386 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
388 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
389 SDValue LowerELFTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
390 SelectionDAG &DAG) const;
391 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
393 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
394 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
395 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
396 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
397 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
398 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
399 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
401 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
407 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
411 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
412 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
413 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
414 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
417 RTLIB::Libcall Call) const;
418 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
426 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
428 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
429 std::vector<SDNode *> *Created) const;
432 getConstraintType(const std::string &Constraint) const override;
433 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
435 /// Examine constraint string and operand type and determine a weight value.
436 /// The operand object must already have been set up with the operand type.
438 getSingleConstraintMatchWeight(AsmOperandInfo &info,
439 const char *constraint) const override;
441 std::pair<unsigned, const TargetRegisterClass *>
442 getRegForInlineAsmConstraint(const std::string &Constraint,
443 MVT VT) const override;
444 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
445 std::vector<SDValue> &Ops,
446 SelectionDAG &DAG) const override;
448 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
449 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
450 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
451 ISD::MemIndexedMode &AM, bool &IsInc,
452 SelectionDAG &DAG) const;
453 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
454 ISD::MemIndexedMode &AM,
455 SelectionDAG &DAG) const override;
456 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
457 SDValue &Offset, ISD::MemIndexedMode &AM,
458 SelectionDAG &DAG) const override;
460 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
461 SelectionDAG &DAG) const override;
465 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
466 const TargetLibraryInfo *libInfo);
467 } // end namespace AArch64
469 } // end namespace llvm