1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 namespace AArch64ISD {
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
30 CALL, // Function call.
32 // Almost the same as a normal call node, except that a TLSDesc relocation is
33 // needed so the linker can relax it correctly if possible.
35 ADRP, // Page address of a TargetGlobalAddress operand.
36 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
37 LOADgot, // Load from automatically generated descriptor (e.g. Global
38 // Offset Table, TLS record).
39 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
40 BRCOND, // Conditional branch instruction; "b.cond".
42 FCSEL, // Conditional move instruction.
43 CSINV, // Conditional select invert.
44 CSNEG, // Conditional select negate.
45 CSINC, // Conditional select increment.
47 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
51 SBC, // adc, sbc instructions
53 // Arithmetic instructions which write flags.
60 // Floating point comparison
63 // Floating point max and min instructions.
70 // Scalar-to-vector duplication
77 // Vector immedate moves
86 // Vector immediate ops
90 // Vector bit select: similar to ISD::VSELECT but not all bits within an
91 // element must be identical.
94 // Vector arithmetic negation
109 // Vector shift by scalar
114 // Vector shift by scalar (again)
121 // Vector comparisons
131 // Vector zero comparisons
143 // Vector bitwise negation
146 // Vector bitwise selection
149 // Compare-and-branch
158 // Custom prefetch handling
161 // {s|u}int to FP within a FP register.
165 // NEON Load/Store with post-increment base updates
166 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
191 } // end namespace AArch64ISD
193 class AArch64Subtarget;
194 class AArch64TargetMachine;
196 class AArch64TargetLowering : public TargetLowering {
197 bool RequireStrictAlign;
200 explicit AArch64TargetLowering(TargetMachine &TM);
202 /// Selects the correct CCAssignFn for a the given CallingConvention
204 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
206 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
207 /// Mask are known to be either zero or one and return them in the
208 /// KnownZero/KnownOne bitsets.
209 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
210 APInt &KnownOne, const SelectionDAG &DAG,
211 unsigned Depth = 0) const override;
213 MVT getScalarShiftAmountTy(EVT LHSTy) const override;
215 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
216 /// unaligned memory accesses. of the specified type.
217 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
219 bool *Fast = nullptr) const override {
220 if (RequireStrictAlign)
222 // FIXME: True for Cyclone, but not necessary others.
228 /// LowerOperation - Provide custom lowering hooks for some operations.
229 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
231 const char *getTargetNodeName(unsigned Opcode) const override;
233 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
235 /// getFunctionAlignment - Return the Log2 alignment of this function.
236 unsigned getFunctionAlignment(const Function *F) const;
238 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
239 /// be used for loads / stores from the global.
240 unsigned getMaximalGlobalOffset() const override;
242 /// Returns true if a cast between SrcAS and DestAS is a noop.
243 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
244 // Addrspacecasts are always noops.
248 /// createFastISel - This method returns a target specific FastISel object,
249 /// or null if the target does not support "fast" ISel.
250 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
251 const TargetLibraryInfo *libInfo) const override;
253 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
255 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
257 /// isShuffleMaskLegal - Return true if the given shuffle mask can be
258 /// codegen'd directly, or if it should be stack expanded.
259 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
261 /// getSetCCResultType - Return the ISD::SETCC ValueType
262 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
264 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
266 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
267 MachineBasicBlock *BB) const;
270 EmitInstrWithCustomInserter(MachineInstr *MI,
271 MachineBasicBlock *MBB) const override;
273 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
274 unsigned Intrinsic) const override;
276 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
277 bool isTruncateFree(EVT VT1, EVT VT2) const override;
279 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
280 bool isZExtFree(EVT VT1, EVT VT2) const override;
281 bool isZExtFree(SDValue Val, EVT VT2) const override;
283 bool hasPairedLoad(Type *LoadedType,
284 unsigned &RequiredAligment) const override;
285 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
287 bool isLegalAddImmediate(int64_t) const override;
288 bool isLegalICmpImmediate(int64_t) const override;
290 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
291 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
292 MachineFunction &MF) const override;
294 /// isLegalAddressingMode - Return true if the addressing mode represented
295 /// by AM is legal for this target, for a load/store of the specified type.
296 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
298 /// \brief Return the cost of the scaling factor used in the addressing
299 /// mode represented by AM for this target, for a load/store
300 /// of the specified type.
301 /// If the AM is supported, the return value must be >= 0.
302 /// If the AM is not supported, it returns a negative value.
303 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
305 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
306 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
307 /// expanded to FMAs when this method returns true, otherwise fmuladd is
308 /// expanded to fmul + fadd.
309 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
311 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
313 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
314 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
316 /// \brief Returns true if it is beneficial to convert a load of a constant
317 /// to just the constant itself.
318 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
319 Type *Ty) const override;
321 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
322 AtomicOrdering Ord) const override;
323 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
324 Value *Addr, AtomicOrdering Ord) const override;
326 bool shouldExpandAtomicInIR(Instruction *Inst) const override;
328 bool useLoadStackGuardNode() const override;
329 TargetLoweringBase::LegalizeTypeAction
330 getPreferredVectorAction(EVT VT) const override;
333 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
334 /// make the right decision when generating code for different targets.
335 const AArch64Subtarget *Subtarget;
337 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
338 void addDRTypeForNEON(MVT VT);
339 void addQRTypeForNEON(MVT VT);
342 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
343 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
345 SmallVectorImpl<SDValue> &InVals) const override;
347 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
348 SmallVectorImpl<SDValue> &InVals) const override;
350 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
351 CallingConv::ID CallConv, bool isVarArg,
352 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
353 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
354 bool isThisReturn, SDValue ThisVal) const;
356 bool isEligibleForTailCallOptimization(
357 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
358 bool isCalleeStructRet, bool isCallerStructRet,
359 const SmallVectorImpl<ISD::OutputArg> &Outs,
360 const SmallVectorImpl<SDValue> &OutVals,
361 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
363 /// Finds the incoming stack arguments which overlap the given fixed stack
364 /// object and incorporates their load into the current chain. This prevents
365 /// an upcoming store from clobbering the stack argument before it's used.
366 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
367 MachineFrameInfo *MFI, int ClobberedFI) const;
369 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
371 bool IsTailCallConvention(CallingConv::ID CallCC) const;
373 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
374 SDValue &Chain) const;
376 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
378 const SmallVectorImpl<ISD::OutputArg> &Outs,
379 LLVMContext &Context) const override;
381 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
382 const SmallVectorImpl<ISD::OutputArg> &Outs,
383 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
384 SelectionDAG &DAG) const override;
386 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
388 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
389 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
390 SDValue LowerELFTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
391 SelectionDAG &DAG) const;
392 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
393 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
394 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
395 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
396 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
397 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
398 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
399 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
401 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
407 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
411 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
412 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
413 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
414 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
417 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
418 RTLIB::Libcall Call) const;
419 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
426 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
429 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
430 std::vector<SDNode *> *Created) const;
433 getConstraintType(const std::string &Constraint) const override;
434 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
436 /// Examine constraint string and operand type and determine a weight value.
437 /// The operand object must already have been set up with the operand type.
439 getSingleConstraintMatchWeight(AsmOperandInfo &info,
440 const char *constraint) const override;
442 std::pair<unsigned, const TargetRegisterClass *>
443 getRegForInlineAsmConstraint(const std::string &Constraint,
444 MVT VT) const override;
445 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
446 std::vector<SDValue> &Ops,
447 SelectionDAG &DAG) const override;
449 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
450 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
451 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
452 ISD::MemIndexedMode &AM, bool &IsInc,
453 SelectionDAG &DAG) const;
454 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
455 ISD::MemIndexedMode &AM,
456 SelectionDAG &DAG) const override;
457 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
458 SDValue &Offset, ISD::MemIndexedMode &AM,
459 SelectionDAG &DAG) const override;
461 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
462 SelectionDAG &DAG) const override;
466 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
467 const TargetLibraryInfo *libInfo);
468 } // end namespace AArch64
470 } // end namespace llvm