1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H
16 #define LLVM_TARGET_AARCH64_ISELLOWERING_H
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/IR/Intrinsics.h"
22 #include "llvm/Target/TargetLowering.h"
25 namespace AArch64ISD {
27 // Start the numbering from where ISD NodeType finishes.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 // This is a conditional branch which also notes the flag needed
31 // (eq/sgt/...). A64 puts this information on the branches rather than
32 // compares as LLVM does.
35 // A node to be selected to an actual call operation: either BL or BLR in
36 // the absence of tail calls.
39 // Indicates a floating-point immediate which fits into the format required
40 // by the FMOV instructions. First (and only) operand is the 8-bit encoded
41 // value of that immediate.
44 // Corresponds directly to an EXTR instruction. Operands are an LHS an RHS
48 // Wraps a load from the GOT, which should always be performed with a 64-bit
49 // load instruction. This prevents the DAG combiner folding a truncate to
50 // form a smaller memory access.
53 // Performs a bitfield insert. Arguments are: the value being inserted into;
54 // the value being inserted; least significant bit changed; width of the
58 // Simply a convenient node inserted during ISelLowering to represent
59 // procedure return. Will almost certainly be selected to "RET".
62 /// Extracts a field of contiguous bits from the source and sign extends
63 /// them into a single register. Arguments are: source; immr; imms. Note
64 /// these are pre-encoded since DAG matching can't cope with combining LSB
65 /// and Width into these values itself.
68 /// This is an A64-ification of the standard LLVM SELECT_CC operation. The
69 /// main difference is that it only has the values and an A64 condition,
70 /// which will be produced by a setcc instruction.
73 /// This serves most of the functions of the LLVM SETCC instruction, for two
74 /// purposes. First, it prevents optimisations from fiddling with the
75 /// compare after we've moved the CondCode information onto the SELECT_CC or
76 /// BR_CC instructions. Second, it gives a legal instruction for the actual
79 /// It keeps a record of the condition flags asked for because certain
80 /// instructions are only valid for a subset of condition codes.
83 // Designates a node which is a tail call: both a call and a return
84 // instruction as far as selction is concerned. It should be selected to an
85 // unconditional branch. Has the usual plethora of call operands, but: 1st
86 // is callee, 2nd is stack adjustment required immediately before branch.
89 // Designates a call used to support the TLS descriptor ABI. The call itself
90 // will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall
91 // var") must be attached somehow during code generation. It takes two
92 // operands: the callee and the symbol to be relocated against.
95 // Leaf node which will be lowered to an appropriate MRS to obtain the
96 // thread pointer: TPIDR_EL0.
99 /// Extracts a field of contiguous bits from the source and zero extends
100 /// them into a single register. Arguments are: source; immr; imms. Note
101 /// these are pre-encoded since DAG matching can't cope with combining LSB
102 /// and Width into these values itself.
105 // Wraps an address which the ISelLowering phase has decided should be
106 // created using the large memory model style: i.e. a sequence of four
107 // movz/movk instructions.
110 // Wraps an address which the ISelLowering phase has decided should be
111 // created using the small memory model style: i.e. adrp/add or
112 // adrp/mem-op. This exists to prevent bare TargetAddresses which may never
116 // Vector move immediate
119 // Vector Move Inverted Immediate
122 // Vector FP move immediate
133 // Vector Element reverse
141 // Vector compare zero
144 // Vector compare bitwise test
147 // Vector saturating shift
154 // Vector dup by lane
160 // NEON duplicate lane loads
161 NEON_LD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
165 // NEON loads with post-increment base updates:
174 // NEON stores with post-increment base updates:
183 // NEON duplicate lane loads with post-increment base updates:
188 // NEON lane loads with post-increment base updates:
193 // NEON lane store with post-increment base updates:
201 class AArch64Subtarget;
202 class AArch64TargetMachine;
204 class AArch64TargetLowering : public TargetLowering {
206 explicit AArch64TargetLowering(AArch64TargetMachine &TM);
208 const char *getTargetNodeName(unsigned Opcode) const;
210 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
212 SDValue LowerFormalArguments(SDValue Chain,
213 CallingConv::ID CallConv, bool isVarArg,
214 const SmallVectorImpl<ISD::InputArg> &Ins,
215 SDLoc dl, SelectionDAG &DAG,
216 SmallVectorImpl<SDValue> &InVals) const;
218 SDValue LowerReturn(SDValue Chain,
219 CallingConv::ID CallConv, bool isVarArg,
220 const SmallVectorImpl<ISD::OutputArg> &Outs,
221 const SmallVectorImpl<SDValue> &OutVals,
222 SDLoc dl, SelectionDAG &DAG) const;
224 virtual unsigned getByValTypeAlignment(Type *Ty) const override;
226 SDValue LowerCall(CallLoweringInfo &CLI,
227 SmallVectorImpl<SDValue> &InVals) const;
229 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
230 CallingConv::ID CallConv, bool IsVarArg,
231 const SmallVectorImpl<ISD::InputArg> &Ins,
232 SDLoc dl, SelectionDAG &DAG,
233 SmallVectorImpl<SDValue> &InVals) const;
235 bool isConcatVector(SDValue Op, SelectionDAG &DAG, SDValue V0, SDValue V1,
236 const int *Mask, SDValue &Res) const;
238 bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &V0,
239 SDValue &V1, int *Mask) const;
241 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
242 const AArch64Subtarget *ST) const;
244 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
246 void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
247 SDValue &Chain) const;
249 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
250 /// for tail call optimization. Targets which want to do tail call
251 /// optimization should implement this function.
252 bool IsEligibleForTailCallOptimization(SDValue Callee,
253 CallingConv::ID CalleeCC,
255 bool IsCalleeStructRet,
256 bool IsCallerStructRet,
257 const SmallVectorImpl<ISD::OutputArg> &Outs,
258 const SmallVectorImpl<SDValue> &OutVals,
259 const SmallVectorImpl<ISD::InputArg> &Ins,
260 SelectionDAG& DAG) const;
262 /// Finds the incoming stack arguments which overlap the given fixed stack
263 /// object and incorporates their load into the current chain. This prevents
264 /// an upcoming store from clobbering the stack argument before it's used.
265 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
266 MachineFrameInfo *MFI, int ClobberedFI) const;
268 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
270 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
272 bool IsTailCallConvention(CallingConv::ID CallCC) const;
274 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
276 bool isLegalICmpImmediate(int64_t Val) const;
277 SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
278 SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
280 virtual MachineBasicBlock *
281 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
284 emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
285 unsigned Size, unsigned Opcode) const;
288 emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB,
289 unsigned Size, unsigned CmpOp,
290 A64CC::CondCodes Cond) const;
292 emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB,
293 unsigned Size) const;
296 EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const;
298 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
299 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
300 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
301 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
302 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
303 SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
304 RTLIB::Libcall Call) const;
305 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
306 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
307 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
308 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
309 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
311 SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const;
312 SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const;
313 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
315 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
317 SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
318 SelectionDAG &DAG) const;
319 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
320 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
321 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
322 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
323 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
324 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
325 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
326 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
328 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
330 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
331 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
332 /// expanded to FMAs when this method returns true, otherwise fmuladd is
333 /// expanded to fmul + fadd.
334 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
336 ConstraintType getConstraintType(const std::string &Constraint) const;
338 ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
339 const char *Constraint) const;
340 void LowerAsmOperandForConstraint(SDValue Op,
341 std::string &Constraint,
342 std::vector<SDValue> &Ops,
343 SelectionDAG &DAG) const;
345 std::pair<unsigned, const TargetRegisterClass*>
346 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
348 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
349 unsigned Intrinsic) const override;
352 std::pair<const TargetRegisterClass*, uint8_t>
353 findRepresentativeClass(MVT VT) const;
356 const InstrItineraryData *Itins;
358 const AArch64Subtarget *getSubtarget() const {
359 return &getTargetMachine().getSubtarget<AArch64Subtarget>();
362 enum NeonModImmType {
367 extern SDValue ScanBUILD_VECTOR(SDValue Op, bool &isOnlyLowElement,
368 bool &usesOnlyOneValue, bool &hasDominantValue,
369 bool &isConstant, bool &isUNDEF);
372 #endif // LLVM_TARGET_AARCH64_ISELLOWERING_H