1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 namespace AArch64ISD {
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
30 CALL, // Function call.
32 // Almost the same as a normal call node, except that a TLSDesc relocation is
33 // needed so the linker can relax it correctly if possible.
35 ADRP, // Page address of a TargetGlobalAddress operand.
36 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
37 LOADgot, // Load from automatically generated descriptor (e.g. Global
38 // Offset Table, TLS record).
39 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
40 BRCOND, // Conditional branch instruction; "b.cond".
42 FCSEL, // Conditional move instruction.
43 CSINV, // Conditional select invert.
44 CSNEG, // Conditional select negate.
45 CSINC, // Conditional select increment.
47 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
51 SBC, // adc, sbc instructions
53 // Arithmetic instructions which write flags.
60 // Floating point comparison
63 // Floating point max and min instructions.
70 // Scalar-to-vector duplication
77 // Vector immedate moves
86 // Vector immediate ops
90 // Vector bit select: similar to ISD::VSELECT but not all bits within an
91 // element must be identical.
94 // Vector arithmetic negation
109 // Vector shift by scalar
114 // Vector shift by scalar (again)
121 // Vector comparisons
131 // Vector zero comparisons
143 // Vector bitwise negation
146 // Vector bitwise selection
149 // Compare-and-branch
158 // Custom prefetch handling
161 // {s|u}int to FP within a FP register.
165 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
166 /// world w.r.t vectors; which causes additional REV instructions to be
167 /// generated to compensate for the byte-swapping. But sometimes we do
168 /// need to re-interpret the data in SIMD vector registers in big-endian
169 /// mode without emitting such REV instructions.
175 // NEON Load/Store with post-increment base updates
176 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
201 } // end namespace AArch64ISD
203 class AArch64Subtarget;
204 class AArch64TargetMachine;
206 class AArch64TargetLowering : public TargetLowering {
207 bool RequireStrictAlign;
210 explicit AArch64TargetLowering(const TargetMachine &TM,
211 const AArch64Subtarget &STI);
213 /// Selects the correct CCAssignFn for a given CallingConvention value.
214 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
216 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
217 /// Mask are known to be either zero or one and return them in the
218 /// KnownZero/KnownOne bitsets.
219 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
220 APInt &KnownOne, const SelectionDAG &DAG,
221 unsigned Depth = 0) const override;
223 MVT getScalarShiftAmountTy(EVT LHSTy) const override;
225 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
226 /// unaligned memory accesses of the specified type.
227 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
229 bool *Fast = nullptr) const override {
230 if (RequireStrictAlign)
232 // FIXME: True for Cyclone, but not necessary others.
238 /// LowerOperation - Provide custom lowering hooks for some operations.
239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
241 const char *getTargetNodeName(unsigned Opcode) const override;
243 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
245 /// getFunctionAlignment - Return the Log2 alignment of this function.
246 unsigned getFunctionAlignment(const Function *F) const;
248 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
249 /// be used for loads / stores from the global.
250 unsigned getMaximalGlobalOffset() const override;
252 /// Returns true if a cast between SrcAS and DestAS is a noop.
253 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
254 // Addrspacecasts are always noops.
258 /// createFastISel - This method returns a target specific FastISel object,
259 /// or null if the target does not support "fast" ISel.
260 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
261 const TargetLibraryInfo *libInfo) const override;
263 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
265 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
267 /// isShuffleMaskLegal - Return true if the given shuffle mask can be
268 /// codegen'd directly, or if it should be stack expanded.
269 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
271 /// getSetCCResultType - Return the ISD::SETCC ValueType
272 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
274 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
276 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
277 MachineBasicBlock *BB) const;
280 EmitInstrWithCustomInserter(MachineInstr *MI,
281 MachineBasicBlock *MBB) const override;
283 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
284 unsigned Intrinsic) const override;
286 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
287 bool isTruncateFree(EVT VT1, EVT VT2) const override;
289 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
290 bool isZExtFree(EVT VT1, EVT VT2) const override;
291 bool isZExtFree(SDValue Val, EVT VT2) const override;
293 bool hasPairedLoad(Type *LoadedType,
294 unsigned &RequiredAligment) const override;
295 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
297 bool isLegalAddImmediate(int64_t) const override;
298 bool isLegalICmpImmediate(int64_t) const override;
300 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
301 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
302 MachineFunction &MF) const override;
304 /// isLegalAddressingMode - Return true if the addressing mode represented
305 /// by AM is legal for this target, for a load/store of the specified type.
306 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
308 /// \brief Return the cost of the scaling factor used in the addressing
309 /// mode represented by AM for this target, for a load/store
310 /// of the specified type.
311 /// If the AM is supported, the return value must be >= 0.
312 /// If the AM is not supported, it returns a negative value.
313 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
315 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
316 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
317 /// expanded to FMAs when this method returns true, otherwise fmuladd is
318 /// expanded to fmul + fadd.
319 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
321 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
323 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
324 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
326 /// \brief Returns true if it is beneficial to convert a load of a constant
327 /// to just the constant itself.
328 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
329 Type *Ty) const override;
331 bool hasLoadLinkedStoreConditional() const override;
332 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
333 AtomicOrdering Ord) const override;
334 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
335 Value *Addr, AtomicOrdering Ord) const override;
337 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
338 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
339 bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
341 bool useLoadStackGuardNode() const override;
342 TargetLoweringBase::LegalizeTypeAction
343 getPreferredVectorAction(EVT VT) const override;
346 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
347 /// make the right decision when generating code for different targets.
348 const AArch64Subtarget *Subtarget;
350 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
351 void addDRTypeForNEON(MVT VT);
352 void addQRTypeForNEON(MVT VT);
355 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
356 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
358 SmallVectorImpl<SDValue> &InVals) const override;
360 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
361 SmallVectorImpl<SDValue> &InVals) const override;
363 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
364 CallingConv::ID CallConv, bool isVarArg,
365 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
366 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
367 bool isThisReturn, SDValue ThisVal) const;
369 bool isEligibleForTailCallOptimization(
370 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
371 bool isCalleeStructRet, bool isCallerStructRet,
372 const SmallVectorImpl<ISD::OutputArg> &Outs,
373 const SmallVectorImpl<SDValue> &OutVals,
374 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
376 /// Finds the incoming stack arguments which overlap the given fixed stack
377 /// object and incorporates their load into the current chain. This prevents
378 /// an upcoming store from clobbering the stack argument before it's used.
379 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
380 MachineFrameInfo *MFI, int ClobberedFI) const;
382 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
384 bool IsTailCallConvention(CallingConv::ID CallCC) const;
386 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
387 SDValue &Chain) const;
389 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
391 const SmallVectorImpl<ISD::OutputArg> &Outs,
392 LLVMContext &Context) const override;
394 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
395 const SmallVectorImpl<ISD::OutputArg> &Outs,
396 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
397 SelectionDAG &DAG) const override;
399 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
401 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerELFTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
404 SelectionDAG &DAG) const;
405 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
407 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
411 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
412 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
413 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
414 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
417 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
418 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
426 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
431 RTLIB::Libcall Call) const;
432 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
433 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
442 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
443 std::vector<SDNode *> *Created) const override;
444 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
447 getConstraintType(const std::string &Constraint) const override;
448 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
450 /// Examine constraint string and operand type and determine a weight value.
451 /// The operand object must already have been set up with the operand type.
453 getSingleConstraintMatchWeight(AsmOperandInfo &info,
454 const char *constraint) const override;
456 std::pair<unsigned, const TargetRegisterClass *>
457 getRegForInlineAsmConstraint(const std::string &Constraint,
458 MVT VT) const override;
459 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
460 std::vector<SDValue> &Ops,
461 SelectionDAG &DAG) const override;
463 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
464 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
465 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
466 ISD::MemIndexedMode &AM, bool &IsInc,
467 SelectionDAG &DAG) const;
468 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
469 ISD::MemIndexedMode &AM,
470 SelectionDAG &DAG) const override;
471 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
472 SDValue &Offset, ISD::MemIndexedMode &AM,
473 SelectionDAG &DAG) const override;
475 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
476 SelectionDAG &DAG) const override;
478 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
479 CallingConv::ID CallConv,
480 bool isVarArg) const override;
484 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
485 const TargetLibraryInfo *libInfo);
486 } // end namespace AArch64
488 } // end namespace llvm