1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file describes AArch64 instruction formats, down to the level of the
10 // instruction's overall class.
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // A64 Instruction Format Definitions.
16 //===----------------------------------------------------------------------===//
18 // A64 is currently the only instruction set supported by the AArch64
20 class A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns,
23 // All A64 instructions are 32-bit. This field will be filled in
24 // gradually going down the hierarchy.
27 field bits<32> Unpredictable = 0;
28 // SoftFail is the generic name for this field, but we alias it so
29 // as to make it more obvious what it means in ARM-land.
30 field bits<32> SoftFail = Unpredictable;
32 // LLVM-level model of the AArch64/A64 distinction.
33 let Namespace = "AArch64";
34 let DecoderNamespace = "A64";
37 // Set the templated fields
38 let OutOperandList = outs;
39 let InOperandList = ins;
40 let AsmString = asmstr;
41 let Pattern = patterns;
45 class PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction {
46 let Namespace = "AArch64";
48 let OutOperandList = outs;
49 let InOperandList= ins;
50 let Pattern = patterns;
51 let isCodeGenOnly = 1;
55 // Represents a pseudo-instruction that represents a single A64 instruction for
56 // whatever reason, the eventual result will be a 32-bit real instruction.
57 class A64PseudoInst<dag outs, dag ins, list<dag> patterns>
58 : PseudoInst<outs, ins, patterns> {
62 // As above, this will be a single A64 instruction, but we can actually give the
63 // expansion in TableGen.
64 class A64PseudoExpand<dag outs, dag ins, list<dag> patterns, dag Result>
65 : A64PseudoInst<outs, ins, patterns>,
66 PseudoInstExpansion<Result>;
69 // First, some common cross-hierarchy register formats.
71 class A64InstRd<dag outs, dag ins, string asmstr,
72 list<dag> patterns, InstrItinClass itin>
73 : A64Inst<outs, ins, asmstr, patterns, itin> {
79 class A64InstRt<dag outs, dag ins, string asmstr,
80 list<dag> patterns, InstrItinClass itin>
81 : A64Inst<outs, ins, asmstr, patterns, itin> {
88 class A64InstRdn<dag outs, dag ins, string asmstr,
89 list<dag> patterns, InstrItinClass itin>
90 : A64InstRd<outs, ins, asmstr, patterns, itin> {
97 class A64InstRtn<dag outs, dag ins, string asmstr,
98 list<dag> patterns, InstrItinClass itin>
99 : A64InstRt<outs, ins, asmstr, patterns, itin> {
106 // Instructions taking Rt,Rt2,Rn
107 class A64InstRtt2n<dag outs, dag ins, string asmstr,
108 list<dag> patterns, InstrItinClass itin>
109 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
112 let Inst{14-10} = Rt2;
115 class A64InstRdnm<dag outs, dag ins, string asmstr,
116 list<dag> patterns, InstrItinClass itin>
117 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
120 let Inst{20-16} = Rm;
123 class A64InstRtnm<dag outs, dag ins, string asmstr,
124 list<dag> patterns, InstrItinClass itin>
125 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
128 let Inst{20-16} = Rm;
131 //===----------------------------------------------------------------------===//
133 // Actual A64 Instruction Formats
136 // Format for Add-subtract (extended register) instructions.
137 class A64I_addsubext<bit sf, bit op, bit S, bits<2> opt, bits<3> option,
138 dag outs, dag ins, string asmstr, list<dag> patterns,
140 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
146 let Inst{28-24} = 0b01011;
147 let Inst{23-22} = opt;
149 // Rm inherited in 20-16
150 let Inst{15-13} = option;
151 let Inst{12-10} = Imm3;
152 // Rn inherited in 9-5
153 // Rd inherited in 4-0
156 // Format for Add-subtract (immediate) instructions.
157 class A64I_addsubimm<bit sf, bit op, bit S, bits<2> shift,
158 dag outs, dag ins, string asmstr,
159 list<dag> patterns, InstrItinClass itin>
160 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
166 let Inst{28-24} = 0b10001;
167 let Inst{23-22} = shift;
168 let Inst{21-10} = Imm12;
171 // Format for Add-subtract (shifted register) instructions.
172 class A64I_addsubshift<bit sf, bit op, bit S, bits<2> shift,
173 dag outs, dag ins, string asmstr, list<dag> patterns,
175 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
181 let Inst{28-24} = 0b01011;
182 let Inst{23-22} = shift;
184 // Rm inherited in 20-16
185 let Inst{15-10} = Imm6;
186 // Rn inherited in 9-5
187 // Rd inherited in 4-0
190 // Format for Add-subtract (with carry) instructions.
191 class A64I_addsubcarry<bit sf, bit op, bit S, bits<6> opcode2,
192 dag outs, dag ins, string asmstr, list<dag> patterns,
194 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
198 let Inst{28-21} = 0b11010000;
199 // Rm inherited in 20-16
200 let Inst{15-10} = opcode2;
201 // Rn inherited in 9-5
202 // Rd inherited in 4-0
206 // Format for Bitfield instructions
207 class A64I_bitfield<bit sf, bits<2> opc, bit n,
208 dag outs, dag ins, string asmstr,
209 list<dag> patterns, InstrItinClass itin>
210 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
215 let Inst{30-29} = opc;
216 let Inst{28-23} = 0b100110;
218 let Inst{21-16} = ImmR;
219 let Inst{15-10} = ImmS;
224 // Format for compare and branch (immediate) instructions.
225 class A64I_cmpbr<bit sf, bit op,
226 dag outs, dag ins, string asmstr,
227 list<dag> patterns, InstrItinClass itin>
228 : A64InstRt<outs, ins, asmstr, patterns, itin> {
232 let Inst{30-25} = 0b011010;
234 let Inst{23-5} = Label;
238 // Format for conditional branch (immediate) instructions.
239 class A64I_condbr<bit o1, bit o0,
240 dag outs, dag ins, string asmstr,
241 list<dag> patterns, InstrItinClass itin>
242 : A64Inst<outs, ins, asmstr, patterns, itin> {
246 let Inst{31-25} = 0b0101010;
248 let Inst{23-5} = Label;
250 let Inst{3-0} = Cond;
253 // Format for conditional compare (immediate) instructions.
254 class A64I_condcmpimm<bit sf, bit op, bit o2, bit o3, bit s,
255 dag outs, dag ins, string asmstr,
256 list<dag> patterns, InstrItinClass itin>
257 : A64Inst<outs, ins, asmstr, patterns, itin> {
266 let Inst{28-21} = 0b11010010;
267 let Inst{20-16} = UImm5;
268 let Inst{15-12} = Cond;
273 let Inst{3-0} = NZCVImm;
276 // Format for conditional compare (register) instructions.
277 class A64I_condcmpreg<bit sf, bit op, bit o2, bit o3, bit s,
278 dag outs, dag ins, string asmstr,
279 list<dag> patterns, InstrItinClass itin>
280 : A64Inst<outs, ins, asmstr, patterns, itin> {
290 let Inst{28-21} = 0b11010010;
291 let Inst{20-16} = Rm;
292 let Inst{15-12} = Cond;
297 let Inst{3-0} = NZCVImm;
300 // Format for conditional select instructions.
301 class A64I_condsel<bit sf, bit op, bit s, bits<2> op2,
302 dag outs, dag ins, string asmstr,
303 list<dag> patterns, InstrItinClass itin>
304 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
310 let Inst{28-21} = 0b11010100;
311 // Inherit Rm in 20-16
312 let Inst{15-12} = Cond;
313 let Inst{11-10} = op2;
318 // Format for data processing (1 source) instructions
319 class A64I_dp_1src<bit sf, bit S, bits<5> opcode2, bits<6> opcode,
320 string asmstr, dag outs, dag ins,
321 list<dag> patterns, InstrItinClass itin>
322 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
326 let Inst{28-21} = 0b11010110;
327 let Inst{20-16} = opcode2;
328 let Inst{15-10} = opcode;
331 // Format for data processing (2 source) instructions
332 class A64I_dp_2src<bit sf, bits<6> opcode, bit S,
333 string asmstr, dag outs, dag ins,
334 list<dag> patterns, InstrItinClass itin>
335 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
339 let Inst{28-21} = 0b11010110;
340 let Inst{15-10} = opcode;
343 // Format for data-processing (3 source) instructions
345 class A64I_dp3<bit sf, bits<6> opcode,
346 dag outs, dag ins, string asmstr,
347 list<dag> patterns, InstrItinClass itin>
348 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
352 let Inst{30-29} = opcode{5-4};
353 let Inst{28-24} = 0b11011;
354 let Inst{23-21} = opcode{3-1};
355 // Inherits Rm in 20-16
356 let Inst{15} = opcode{0};
357 let Inst{14-10} = Ra;
358 // Inherits Rn in 9-5
359 // Inherits Rd in 4-0
362 // Format for exception generation instructions
363 class A64I_exception<bits<3> opc, bits<3> op2, bits<2> ll,
364 dag outs, dag ins, string asmstr,
365 list<dag> patterns, InstrItinClass itin>
366 : A64Inst<outs, ins, asmstr, patterns, itin> {
369 let Inst{31-24} = 0b11010100;
370 let Inst{23-21} = opc;
371 let Inst{20-5} = UImm16;
376 // Format for extract (immediate) instructions
377 class A64I_extract<bit sf, bits<3> op, bit n,
378 dag outs, dag ins, string asmstr,
379 list<dag> patterns, InstrItinClass itin>
380 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
384 let Inst{30-29} = op{2-1};
385 let Inst{28-23} = 0b100111;
387 let Inst{21} = op{0};
388 // Inherits Rm in bits 20-16
389 let Inst{15-10} = LSB;
390 // Inherits Rn in 9-5
391 // Inherits Rd in 4-0
394 let Predicates = [HasFPARMv8] in {
396 // Format for floating-point compare instructions.
397 class A64I_fpcmp<bit m, bit s, bits<2> type, bits<2> op, bits<5> opcode2,
398 dag outs, dag ins, string asmstr,
399 list<dag> patterns, InstrItinClass itin>
400 : A64Inst<outs, ins, asmstr, patterns, itin> {
407 let Inst{28-24} = 0b11110;
408 let Inst{23-22} = type;
410 let Inst{20-16} = Rm;
411 let Inst{15-14} = op;
412 let Inst{13-10} = 0b1000;
414 let Inst{4-0} = opcode2;
417 // Format for floating-point conditional compare instructions.
418 class A64I_fpccmp<bit m, bit s, bits<2> type, bit op,
419 dag outs, dag ins, string asmstr,
420 list<dag> patterns, InstrItinClass itin>
421 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
430 let Inst{28-24} = 0b11110;
431 let Inst{23-22} = type;
433 let Inst{20-16} = Rm;
434 let Inst{15-12} = Cond;
435 let Inst{11-10} = 0b01;
438 let Inst{3-0} = NZCVImm;
441 // Format for floating-point conditional select instructions.
442 class A64I_fpcondsel<bit m, bit s, bits<2> type,
443 dag outs, dag ins, string asmstr,
444 list<dag> patterns, InstrItinClass itin>
445 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
451 let Inst{28-24} = 0b11110;
452 let Inst{23-22} = type;
454 // Inherit Rm in 20-16
455 let Inst{15-12} = Cond;
456 let Inst{11-10} = 0b11;
462 // Format for floating-point data-processing (1 source) instructions.
463 class A64I_fpdp1<bit m, bit s, bits<2> type, bits<6> opcode,
464 dag outs, dag ins, string asmstr,
465 list<dag> patterns, InstrItinClass itin>
466 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
470 let Inst{28-24} = 0b11110;
471 let Inst{23-22} = type;
473 let Inst{20-15} = opcode;
474 let Inst{14-10} = 0b10000;
479 // Format for floating-point data-processing (2 sources) instructions.
480 class A64I_fpdp2<bit m, bit s, bits<2> type, bits<4> opcode,
481 dag outs, dag ins, string asmstr,
482 list<dag> patterns, InstrItinClass itin>
483 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
487 let Inst{28-24} = 0b11110;
488 let Inst{23-22} = type;
490 // Inherit Rm in 20-16
491 let Inst{15-12} = opcode;
492 let Inst{11-10} = 0b10;
497 // Format for floating-point data-processing (3 sources) instructions.
498 class A64I_fpdp3<bit m, bit s, bits<2> type, bit o1, bit o0,
499 dag outs, dag ins, string asmstr,
500 list<dag> patterns, InstrItinClass itin>
501 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
507 let Inst{28-24} = 0b11111;
508 let Inst{23-22} = type;
510 // Inherit Rm in 20-16
512 let Inst{14-10} = Ra;
517 // Format for floating-point <-> fixed-point conversion instructions.
518 class A64I_fpfixed<bit sf, bit s, bits<2> type, bits<2> mode, bits<3> opcode,
519 dag outs, dag ins, string asmstr,
520 list<dag> patterns, InstrItinClass itin>
521 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
527 let Inst{28-24} = 0b11110;
528 let Inst{23-22} = type;
530 let Inst{20-19} = mode;
531 let Inst{18-16} = opcode;
532 let Inst{15-10} = Scale;
537 // Format for floating-point <-> integer conversion instructions.
538 class A64I_fpint<bit sf, bit s, bits<2> type, bits<2> rmode, bits<3> opcode,
539 dag outs, dag ins, string asmstr,
540 list<dag> patterns, InstrItinClass itin>
541 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
545 let Inst{28-24} = 0b11110;
546 let Inst{23-22} = type;
548 let Inst{20-19} = rmode;
549 let Inst{18-16} = opcode;
550 let Inst{15-10} = 0b000000;
556 // Format for floating-point immediate instructions.
557 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
558 dag outs, dag ins, string asmstr,
559 list<dag> patterns, InstrItinClass itin>
560 : A64InstRd<outs, ins, asmstr, patterns, itin> {
566 let Inst{28-24} = 0b11110;
567 let Inst{23-22} = type;
569 let Inst{20-13} = Imm8;
570 let Inst{12-10} = 0b100;
571 let Inst{9-5} = imm5;
577 // Format for load-register (literal) instructions.
578 class A64I_LDRlit<bits<2> opc, bit v,
579 dag outs, dag ins, string asmstr,
580 list<dag> patterns, InstrItinClass itin>
581 : A64InstRt<outs, ins, asmstr, patterns, itin> {
584 let Inst{31-30} = opc;
585 let Inst{29-27} = 0b011;
587 let Inst{25-24} = 0b00;
588 let Inst{23-5} = Imm19;
592 // Format for load-store exclusive instructions.
593 class A64I_LDSTex_tn<bits<2> size, bit o2, bit L, bit o1, bit o0,
594 dag outs, dag ins, string asmstr,
595 list <dag> patterns, InstrItinClass itin>
596 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
597 let Inst{31-30} = size;
598 let Inst{29-24} = 0b001000;
605 class A64I_LDSTex_tt2n<bits<2> size, bit o2, bit L, bit o1, bit o0,
606 dag outs, dag ins, string asmstr,
607 list <dag> patterns, InstrItinClass itin>:
608 A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
610 let Inst{14-10} = Rt2;
613 class A64I_LDSTex_stn<bits<2> size, bit o2, bit L, bit o1, bit o0,
614 dag outs, dag ins, string asmstr,
615 list <dag> patterns, InstrItinClass itin>:
616 A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
618 let Inst{20-16} = Rs;
621 class A64I_LDSTex_stt2n<bits<2> size, bit o2, bit L, bit o1, bit o0,
622 dag outs, dag ins, string asmstr,
623 list <dag> patterns, InstrItinClass itin>:
624 A64I_LDSTex_stn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
626 let Inst{14-10} = Rt2;
629 // Format for load-store register (immediate post-indexed) instructions
630 class A64I_LSpostind<bits<2> size, bit v, bits<2> opc,
631 dag outs, dag ins, string asmstr,
632 list<dag> patterns, InstrItinClass itin>
633 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
636 let Inst{31-30} = size;
637 let Inst{29-27} = 0b111;
639 let Inst{25-24} = 0b00;
640 let Inst{23-22} = opc;
642 let Inst{20-12} = SImm9;
643 let Inst{11-10} = 0b01;
648 // Format for load-store register (immediate pre-indexed) instructions
649 class A64I_LSpreind<bits<2> size, bit v, bits<2> opc,
650 dag outs, dag ins, string asmstr,
651 list<dag> patterns, InstrItinClass itin>
652 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
656 let Inst{31-30} = size;
657 let Inst{29-27} = 0b111;
659 let Inst{25-24} = 0b00;
660 let Inst{23-22} = opc;
662 let Inst{20-12} = SImm9;
663 let Inst{11-10} = 0b11;
668 // Format for load-store register (unprivileged) instructions
669 class A64I_LSunpriv<bits<2> size, bit v, bits<2> opc,
670 dag outs, dag ins, string asmstr,
671 list<dag> patterns, InstrItinClass itin>
672 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
676 let Inst{31-30} = size;
677 let Inst{29-27} = 0b111;
679 let Inst{25-24} = 0b00;
680 let Inst{23-22} = opc;
682 let Inst{20-12} = SImm9;
683 let Inst{11-10} = 0b10;
688 // Format for load-store (unscaled immediate) instructions.
689 class A64I_LSunalimm<bits<2> size, bit v, bits<2> opc,
690 dag outs, dag ins, string asmstr,
691 list<dag> patterns, InstrItinClass itin>
692 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
695 let Inst{31-30} = size;
696 let Inst{29-27} = 0b111;
698 let Inst{25-24} = 0b00;
699 let Inst{23-22} = opc;
701 let Inst{20-12} = SImm9;
702 let Inst{11-10} = 0b00;
708 // Format for load-store (unsigned immediate) instructions.
709 class A64I_LSunsigimm<bits<2> size, bit v, bits<2> opc,
710 dag outs, dag ins, string asmstr,
711 list<dag> patterns, InstrItinClass itin>
712 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
715 let Inst{31-30} = size;
716 let Inst{29-27} = 0b111;
718 let Inst{25-24} = 0b01;
719 let Inst{23-22} = opc;
720 let Inst{21-10} = UImm12;
723 // Format for load-store register (register offset) instructions.
724 class A64I_LSregoff<bits<2> size, bit v, bits<2> opc, bit optionlo,
725 dag outs, dag ins, string asmstr,
726 list<dag> patterns, InstrItinClass itin>
727 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
730 // Complex operand selection needed for these instructions, so they
731 // need an "addr" field for encoding/decoding to be generated.
733 // OptionHi = Ext{2-1}
736 let Inst{31-30} = size;
737 let Inst{29-27} = 0b111;
739 let Inst{25-24} = 0b00;
740 let Inst{23-22} = opc;
742 let Inst{20-16} = Rm;
743 let Inst{15-14} = Ext{2-1};
744 let Inst{13} = optionlo;
745 let Inst{12} = Ext{0};
746 let Inst{11-10} = 0b10;
747 // Inherits Rn in 9-5
748 // Inherits Rt in 4-0
750 let AddedComplexity = 50;
753 // Format for Load-store register pair (offset) instructions
754 class A64I_LSPoffset<bits<2> opc, bit v, bit l,
755 dag outs, dag ins, string asmstr,
756 list<dag> patterns, InstrItinClass itin>
757 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
760 let Inst{31-30} = opc;
761 let Inst{29-27} = 0b101;
763 let Inst{25-23} = 0b010;
765 let Inst{21-15} = SImm7;
766 // Inherit Rt2 in 14-10
771 // Format for Load-store register pair (post-indexed) instructions
772 class A64I_LSPpostind<bits<2> opc, bit v, bit l,
773 dag outs, dag ins, string asmstr,
774 list<dag> patterns, InstrItinClass itin>
775 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
778 let Inst{31-30} = opc;
779 let Inst{29-27} = 0b101;
781 let Inst{25-23} = 0b001;
783 let Inst{21-15} = SImm7;
784 // Inherit Rt2 in 14-10
789 // Format for Load-store register pair (pre-indexed) instructions
790 class A64I_LSPpreind<bits<2> opc, bit v, bit l,
791 dag outs, dag ins, string asmstr,
792 list<dag> patterns, InstrItinClass itin>
793 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
796 let Inst{31-30} = opc;
797 let Inst{29-27} = 0b101;
799 let Inst{25-23} = 0b011;
801 let Inst{21-15} = SImm7;
802 // Inherit Rt2 in 14-10
807 // Format for Load-store non-temporal register pair (offset) instructions
808 class A64I_LSPnontemp<bits<2> opc, bit v, bit l,
809 dag outs, dag ins, string asmstr,
810 list<dag> patterns, InstrItinClass itin>
811 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
814 let Inst{31-30} = opc;
815 let Inst{29-27} = 0b101;
817 let Inst{25-23} = 0b000;
819 let Inst{21-15} = SImm7;
820 // Inherit Rt2 in 14-10
825 // Format for Logical (immediate) instructions
826 class A64I_logicalimm<bit sf, bits<2> opc,
827 dag outs, dag ins, string asmstr,
828 list<dag> patterns, InstrItinClass itin>
829 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
834 // N, ImmR and ImmS have no separate existence in any assembly syntax (or for
835 // selection), so we'll combine them into a single field here.
842 let Inst{30-29} = opc;
843 let Inst{28-23} = 0b100100;
844 let Inst{22} = Imm{12};
845 let Inst{21-16} = Imm{11-6};
846 let Inst{15-10} = Imm{5-0};
847 // Rn inherited in 9-5
848 // Rd inherited in 4-0
851 // Format for Logical (shifted register) instructions
852 class A64I_logicalshift<bit sf, bits<2> opc, bits<2> shift, bit N,
853 dag outs, dag ins, string asmstr,
854 list<dag> patterns, InstrItinClass itin>
855 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
859 let Inst{30-29} = opc;
860 let Inst{28-24} = 0b01010;
861 let Inst{23-22} = shift;
864 let Inst{15-10} = Imm6;
869 // Format for Move wide (immediate)
870 class A64I_movw<bit sf, bits<2> opc,
871 dag outs, dag ins, string asmstr,
872 list<dag> patterns, InstrItinClass itin>
873 : A64InstRd<outs, ins, asmstr, patterns, itin> {
875 bits<2> Shift; // Called "hw" officially
878 let Inst{30-29} = opc;
879 let Inst{28-23} = 0b100101;
880 let Inst{22-21} = Shift;
881 let Inst{20-5} = UImm16;
882 // Inherits Rd in 4-0
885 // Format for PC-relative addressing instructions, ADR and ADRP.
886 class A64I_PCADR<bit op,
887 dag outs, dag ins, string asmstr,
888 list<dag> patterns, InstrItinClass itin>
889 : A64InstRd<outs, ins, asmstr, patterns, itin> {
893 let Inst{30-29} = Label{1-0};
894 let Inst{28-24} = 0b10000;
895 let Inst{23-5} = Label{20-2};
898 // Format for system instructions
899 class A64I_system<bit l,
900 dag outs, dag ins, string asmstr,
901 list<dag> patterns, InstrItinClass itin>
902 : A64Inst<outs, ins, asmstr, patterns, itin> {
910 let Inst{31-22} = 0b1101010100;
912 let Inst{20-19} = Op0;
913 let Inst{18-16} = Op1;
914 let Inst{15-12} = CRn;
915 let Inst{11-8} = CRm;
919 // These instructions can do horrible things.
920 let hasSideEffects = 1;
923 // Format for unconditional branch (immediate) instructions
924 class A64I_Bimm<bit op,
925 dag outs, dag ins, string asmstr,
926 list<dag> patterns, InstrItinClass itin>
927 : A64Inst<outs, ins, asmstr, patterns, itin> {
928 // Doubly special in not even sharing register fields with other
929 // instructions, so we create our own Rn here.
933 let Inst{30-26} = 0b00101;
934 let Inst{25-0} = Label;
937 // Format for Test & branch (immediate) instructions
938 class A64I_TBimm<bit op,
939 dag outs, dag ins, string asmstr,
940 list<dag> patterns, InstrItinClass itin>
941 : A64InstRt<outs, ins, asmstr, patterns, itin> {
942 // Doubly special in not even sharing register fields with other
943 // instructions, so we create our own Rn here.
947 let Inst{31} = Imm{5};
948 let Inst{30-25} = 0b011011;
950 let Inst{23-19} = Imm{4-0};
951 let Inst{18-5} = Label;
955 // Format for Unconditional branch (register) instructions, including
956 // RET. Shares no fields with instructions further up the hierarchy
958 class A64I_Breg<bits<4> opc, bits<5> op2, bits<6> op3, bits<5> op4,
959 dag outs, dag ins, string asmstr,
960 list<dag> patterns, InstrItinClass itin>
961 : A64Inst<outs, ins, asmstr, patterns, itin> {
962 // Doubly special in not even sharing register fields with other
963 // instructions, so we create our own Rn here.
966 let Inst{31-25} = 0b1101011;
967 let Inst{24-21} = opc;
968 let Inst{20-16} = op2;
969 let Inst{15-10} = op3;
975 //===----------------------------------------------------------------------===//
977 // Neon Instruction Format Definitions.
980 let Predicates = [HasNEON] in {
982 class NeonInstAlias<string Asm, dag Result, bit Emit = 0b1>
983 : InstAlias<Asm, Result, Emit> {
986 // Format AdvSIMD bitwise extract
987 class NeonI_BitExtract<bit q, bits<2> op2,
988 dag outs, dag ins, string asmstr,
989 list<dag> patterns, InstrItinClass itin>
990 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
993 let Inst{29-24} = 0b101110;
994 let Inst{23-22} = op2;
996 // Inherit Rm in 20-16
1000 // Inherit Rn in 9-5
1001 // Inherit Rd in 4-0
1004 // Format AdvSIMD perm
1005 class NeonI_Perm<bit q, bits<2> size, bits<3> opcode,
1006 dag outs, dag ins, string asmstr,
1007 list<dag> patterns, InstrItinClass itin>
1008 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1011 let Inst{29-24} = 0b001110;
1012 let Inst{23-22} = size;
1014 // Inherit Rm in 20-16
1016 let Inst{14-12} = opcode;
1017 let Inst{11-10} = 0b10;
1018 // Inherit Rn in 9-5
1019 // Inherit Rd in 4-0
1022 // Format AdvSIMD table lookup
1023 class NeonI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
1024 dag outs, dag ins, string asmstr,
1025 list<dag> patterns, InstrItinClass itin>
1026 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1029 let Inst{29-24} = 0b001110;
1030 let Inst{23-22} = op2;
1032 // Inherit Rm in 20-16
1034 let Inst{14-13} = len;
1036 let Inst{11-10} = 0b00;
1037 // Inherit Rn in 9-5
1038 // Inherit Rd in 4-0
1041 // Format AdvSIMD 3 vector registers with same vector type
1042 class NeonI_3VSame<bit q, bit u, bits<2> size, bits<5> opcode,
1043 dag outs, dag ins, string asmstr,
1044 list<dag> patterns, InstrItinClass itin>
1045 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1049 let Inst{28-24} = 0b01110;
1050 let Inst{23-22} = size;
1052 // Inherit Rm in 20-16
1053 let Inst{15-11} = opcode;
1055 // Inherit Rn in 9-5
1056 // Inherit Rd in 4-0
1059 // Format AdvSIMD 3 vector registers with different vector type
1060 class NeonI_3VDiff<bit q, bit u, bits<2> size, bits<4> opcode,
1061 dag outs, dag ins, string asmstr,
1062 list<dag> patterns, InstrItinClass itin>
1063 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1067 let Inst{28-24} = 0b01110;
1068 let Inst{23-22} = size;
1070 // Inherit Rm in 20-16
1071 let Inst{15-12} = opcode;
1074 // Inherit Rn in 9-5
1075 // Inherit Rd in 4-0
1078 // Format AdvSIMD two registers and an element
1079 class NeonI_2VElem<bit q, bit u, bits<2> size, bits<4> opcode,
1080 dag outs, dag ins, string asmstr,
1081 list<dag> patterns, InstrItinClass itin>
1082 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1086 let Inst{28-24} = 0b01111;
1087 let Inst{23-22} = size;
1090 // Inherit Rm in 19-16
1091 let Inst{15-12} = opcode;
1094 // Inherit Rn in 9-5
1095 // Inherit Rd in 4-0
1098 // Format AdvSIMD 1 vector register with modified immediate
1099 class NeonI_1VModImm<bit q, bit op,
1100 dag outs, dag ins, string asmstr,
1101 list<dag> patterns, InstrItinClass itin>
1102 : A64InstRd<outs,ins, asmstr, patterns, itin> {
1108 let Inst{28-19} = 0b0111100000;
1109 let Inst{15-12} = cmode;
1110 let Inst{11} = 0b0; // o2
1112 // Inherit Rd in 4-0
1113 let Inst{18-16} = Imm{7-5}; // imm a:b:c
1114 let Inst{9-5} = Imm{4-0}; // imm d:e:f:g:h
1117 // Format AdvSIMD 3 scalar registers with same type
1119 class NeonI_Scalar3Same<bit u, bits<2> size, bits<5> opcode,
1120 dag outs, dag ins, string asmstr,
1121 list<dag> patterns, InstrItinClass itin>
1122 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1126 let Inst{28-24} = 0b11110;
1127 let Inst{23-22} = size;
1129 // Inherit Rm in 20-16
1130 let Inst{15-11} = opcode;
1132 // Inherit Rn in 9-5
1133 // Inherit Rd in 4-0
1137 // Format AdvSIMD 2 vector registers miscellaneous
1138 class NeonI_2VMisc<bit q, bit u, bits<2> size, bits<5> opcode,
1139 dag outs, dag ins, string asmstr,
1140 list<dag> patterns, InstrItinClass itin>
1141 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1145 let Inst{28-24} = 0b01110;
1146 let Inst{23-22} = size;
1147 let Inst{21-17} = 0b10000;
1148 let Inst{16-12} = opcode;
1149 let Inst{11-10} = 0b10;
1151 // Inherit Rn in 9-5
1152 // Inherit Rd in 4-0
1155 // Format AdvSIMD 2 vector 1 immediate shift
1156 class NeonI_2VShiftImm<bit q, bit u, bits<5> opcode,
1157 dag outs, dag ins, string asmstr,
1158 list<dag> patterns, InstrItinClass itin>
1159 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1164 let Inst{28-23} = 0b011110;
1165 let Inst{22-16} = Imm;
1166 let Inst{15-11} = opcode;
1169 // Inherit Rn in 9-5
1170 // Inherit Rd in 4-0
1173 // Format AdvSIMD duplicate and insert
1174 class NeonI_copy<bit q, bit op, bits<4> imm4,
1175 dag outs, dag ins, string asmstr,
1176 list<dag> patterns, InstrItinClass itin>
1177 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1182 let Inst{28-21} = 0b01110000;
1183 let Inst{20-16} = Imm5;
1185 let Inst{14-11} = imm4;
1188 // Inherit Rn in 9-5
1189 // Inherit Rd in 4-0
1191 // Format AdvSIMD insert from element to vector
1192 class NeonI_insert<bit q, bit op,
1193 dag outs, dag ins, string asmstr,
1194 list<dag> patterns, InstrItinClass itin>
1195 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1201 let Inst{28-21} = 0b01110000;
1202 let Inst{20-16} = Imm5;
1204 let Inst{14-11} = Imm4;
1207 // Inherit Rn in 9-5
1208 // Inherit Rd in 4-0
1211 // Format AdvSIMD scalar pairwise
1212 class NeonI_ScalarPair<bit u, bits<2> size, bits<5> opcode,
1213 dag outs, dag ins, string asmstr,
1214 list<dag> patterns, InstrItinClass itin>
1215 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1219 let Inst{28-24} = 0b11110;
1220 let Inst{23-22} = size;
1221 let Inst{21-17} = 0b11000;
1222 let Inst{16-12} = opcode;
1223 let Inst{11-10} = 0b10;
1225 // Inherit Rn in 9-5
1226 // Inherit Rd in 4-0
1229 // Format AdvSIMD 2 vector across lanes
1230 class NeonI_2VAcross<bit q, bit u, bits<2> size, bits<5> opcode,
1231 dag outs, dag ins, string asmstr,
1232 list<dag> patterns, InstrItinClass itin>
1233 : A64InstRdn<outs, ins, asmstr, patterns, itin>
1238 let Inst{28-24} = 0b01110;
1239 let Inst{23-22} = size;
1240 let Inst{21-17} = 0b11000;
1241 let Inst{16-12} = opcode;
1242 let Inst{11-10} = 0b10;
1244 // Inherit Rn in 9-5
1245 // Inherit Rd in 4-0
1248 // Format AdvSIMD scalar two registers miscellaneous
1249 class NeonI_Scalar2SameMisc<bit u, bits<2> size, bits<5> opcode, dag outs, dag ins,
1250 string asmstr, list<dag> patterns, InstrItinClass itin>
1251 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1255 let Inst{28-24} = 0b11110;
1256 let Inst{23-22} = size;
1257 let Inst{21-17} = 0b10000;
1258 let Inst{16-12} = opcode;
1259 let Inst{11-10} = 0b10;
1260 // Inherit Rn in 9-5
1261 // Inherit Rd in 4-0
1264 // Format AdvSIMD vector load/store multiple N-element structure
1265 class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size,
1266 dag outs, dag ins, string asmstr,
1267 list<dag> patterns, InstrItinClass itin>
1268 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1272 let Inst{29-23} = 0b0011000;
1274 let Inst{21-16} = 0b000000;
1275 let Inst{15-12} = opcode;
1276 let Inst{11-10} = size;
1278 // Inherit Rn in 9-5
1279 // Inherit Rt in 4-0
1282 // Format AdvSIMD vector load/store multiple N-element structure (post-index)
1283 class NeonI_LdStMult_Post<bit q, bit l, bits<4> opcode, bits<2> size,
1284 dag outs, dag ins, string asmstr,
1285 list<dag> patterns, InstrItinClass itin>
1286 : A64InstRtnm<outs, ins, asmstr, patterns, itin>
1290 let Inst{29-23} = 0b0011001;
1293 // Inherit Rm in 20-16
1294 let Inst{15-12} = opcode;
1295 let Inst{11-10} = size;
1296 // Inherit Rn in 9-5
1297 // Inherit Rt in 4-0
1300 // Format AdvSIMD vector load Single N-element structure to all lanes
1301 class NeonI_LdOne_Dup<bit q, bit r, bits<3> opcode, bits<2> size, dag outs,
1302 dag ins, string asmstr, list<dag> patterns,
1303 InstrItinClass itin>
1304 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1308 let Inst{29-23} = 0b0011010;
1311 let Inst{20-16} = 0b00000;
1312 let Inst{15-13} = opcode;
1314 let Inst{11-10} = size;
1316 // Inherit Rn in 9-5
1317 // Inherit Rt in 4-0
1320 // Format AdvSIMD vector load/store Single N-element structure to/from one lane
1321 class NeonI_LdStOne_Lane<bit l, bit r, bits<2> op2_1, bit op0, dag outs,
1322 dag ins, string asmstr,
1323 list<dag> patterns, InstrItinClass itin>
1324 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1328 let Inst{29-23} = 0b0011010;
1331 let Inst{20-16} = 0b00000;
1332 let Inst{15-14} = op2_1;
1335 // Inherit Rn in 9-5
1336 // Inherit Rt in 4-0
1339 // Format AdvSIMD post-index vector load Single N-element structure to all lanes
1340 class NeonI_LdOne_Dup_Post<bit q, bit r, bits<3> opcode, bits<2> size, dag outs,
1341 dag ins, string asmstr, list<dag> patterns,
1342 InstrItinClass itin>
1343 : A64InstRtnm<outs, ins, asmstr, patterns, itin>
1347 let Inst{29-23} = 0b0011011;
1350 // Inherit Rm in 20-16
1351 let Inst{15-13} = opcode;
1353 let Inst{11-10} = size;
1355 // Inherit Rn in 9-5
1356 // Inherit Rt in 4-0
1359 // Format AdvSIMD post-index vector load/store Single N-element structure
1361 class NeonI_LdStOne_Lane_Post<bit l, bit r, bits<2> op2_1, bit op0, dag outs,
1362 dag ins, string asmstr,
1363 list<dag> patterns, InstrItinClass itin>
1364 : A64InstRtnm<outs, ins, asmstr, patterns, itin>
1368 let Inst{29-23} = 0b0011011;
1371 // Inherit Rm in 20-16
1372 let Inst{15-14} = op2_1;
1375 // Inherit Rn in 9-5
1376 // Inherit Rt in 4-0
1379 // Format AdvSIMD 3 scalar registers with different type
1381 class NeonI_Scalar3Diff<bit u, bits<2> size, bits<4> opcode,
1382 dag outs, dag ins, string asmstr,
1383 list<dag> patterns, InstrItinClass itin>
1384 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1385 let Inst{31-30} = 0b01;
1387 let Inst{28-24} = 0b11110;
1388 let Inst{23-22} = size;
1390 // Inherit Rm in 20-16
1391 let Inst{15-12} = opcode;
1392 let Inst{11-10} = 0b00;
1393 // Inherit Rn in 9-5
1394 // Inherit Rd in 4-0
1397 // Format AdvSIMD scalar shift by immediate
1399 class NeonI_ScalarShiftImm<bit u, bits<5> opcode,
1400 dag outs, dag ins, string asmstr,
1401 list<dag> patterns, InstrItinClass itin>
1402 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1405 let Inst{31-30} = 0b01;
1407 let Inst{28-23} = 0b111110;
1408 let Inst{22-19} = Imm4;
1409 let Inst{18-16} = Imm3;
1410 let Inst{15-11} = opcode;
1412 // Inherit Rn in 9-5
1413 // Inherit Rd in 4-0
1416 // Format AdvSIMD crypto AES
1417 class NeonI_Crypto_AES<bits<2> size, bits<5> opcode,
1418 dag outs, dag ins, string asmstr,
1419 list<dag> patterns, InstrItinClass itin>
1420 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1421 let Inst{31-24} = 0b01001110;
1422 let Inst{23-22} = size;
1423 let Inst{21-17} = 0b10100;
1424 let Inst{16-12} = opcode;
1425 let Inst{11-10} = 0b10;
1426 // Inherit Rn in 9-5
1427 // Inherit Rd in 4-0
1430 // Format AdvSIMD crypto SHA
1431 class NeonI_Crypto_SHA<bits<2> size, bits<5> opcode,
1432 dag outs, dag ins, string asmstr,
1433 list<dag> patterns, InstrItinClass itin>
1434 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1435 let Inst{31-24} = 0b01011110;
1436 let Inst{23-22} = size;
1437 let Inst{21-17} = 0b10100;
1438 let Inst{16-12} = opcode;
1439 let Inst{11-10} = 0b10;
1440 // Inherit Rn in 9-5
1441 // Inherit Rd in 4-0
1444 // Format AdvSIMD crypto 3V SHA
1445 class NeonI_Crypto_3VSHA<bits<2> size, bits<3> opcode,
1446 dag outs, dag ins, string asmstr,
1447 list<dag> patterns, InstrItinClass itin>
1448 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1449 let Inst{31-24} = 0b01011110;
1450 let Inst{23-22} = size;
1452 // Inherit Rm in 20-16
1454 let Inst{14-12} = opcode;
1455 let Inst{11-10} = 0b00;
1456 // Inherit Rn in 9-5
1457 // Inherit Rd in 4-0
1460 // Format AdvSIMD scalar x indexed element
1461 class NeonI_ScalarXIndexedElem<bit u, bit szhi, bit szlo,
1462 bits<4> opcode, dag outs, dag ins,
1463 string asmstr, list<dag> patterns,
1464 InstrItinClass itin>
1465 : A64InstRdnm<outs, ins, asmstr, patterns, itin>
1470 let Inst{28-24} = 0b11111;
1471 let Inst{23} = szhi;
1472 let Inst{22} = szlo;
1475 // Inherit Rm in 19-16
1476 let Inst{15-12} = opcode;
1479 // Inherit Rn in 9-5
1480 // Inherit Rd in 4-0
1482 // Format AdvSIMD scalar copy - insert from element to scalar
1483 class NeonI_ScalarCopy<dag outs, dag ins, string asmstr,
1484 list<dag> patterns, InstrItinClass itin>
1485 : NeonI_copy<0b1, 0b0, 0b0000, outs, ins, asmstr, patterns, itin> {