1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file describes AArch64 instruction formats, down to the level of the
10 // instruction's overall class.
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // A64 Instruction Format Definitions.
16 //===----------------------------------------------------------------------===//
18 // A64 is currently the only instruction set supported by the AArch64
20 class A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns,
23 // All A64 instructions are 32-bit. This field will be filled in
24 // gradually going down the hierarchy.
27 field bits<32> Unpredictable = 0;
28 // SoftFail is the generic name for this field, but we alias it so
29 // as to make it more obvious what it means in ARM-land.
30 field bits<32> SoftFail = Unpredictable;
32 // LLVM-level model of the AArch64/A64 distinction.
33 let Namespace = "AArch64";
34 let DecoderNamespace = "A64";
37 // Set the templated fields
38 let OutOperandList = outs;
39 let InOperandList = ins;
40 let AsmString = asmstr;
41 let Pattern = patterns;
45 class PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction {
46 let Namespace = "AArch64";
48 let OutOperandList = outs;
49 let InOperandList= ins;
50 let Pattern = patterns;
51 let isCodeGenOnly = 1;
55 // Represents a pseudo-instruction that represents a single A64 instruction for
56 // whatever reason, the eventual result will be a 32-bit real instruction.
57 class A64PseudoInst<dag outs, dag ins, list<dag> patterns>
58 : PseudoInst<outs, ins, patterns> {
62 // As above, this will be a single A64 instruction, but we can actually give the
63 // expansion in TableGen.
64 class A64PseudoExpand<dag outs, dag ins, list<dag> patterns, dag Result>
65 : A64PseudoInst<outs, ins, patterns>,
66 PseudoInstExpansion<Result>;
69 // First, some common cross-hierarchy register formats.
71 class A64InstRd<dag outs, dag ins, string asmstr,
72 list<dag> patterns, InstrItinClass itin>
73 : A64Inst<outs, ins, asmstr, patterns, itin> {
79 class A64InstRt<dag outs, dag ins, string asmstr,
80 list<dag> patterns, InstrItinClass itin>
81 : A64Inst<outs, ins, asmstr, patterns, itin> {
88 class A64InstRdn<dag outs, dag ins, string asmstr,
89 list<dag> patterns, InstrItinClass itin>
90 : A64InstRd<outs, ins, asmstr, patterns, itin> {
97 class A64InstRtn<dag outs, dag ins, string asmstr,
98 list<dag> patterns, InstrItinClass itin>
99 : A64InstRt<outs, ins, asmstr, patterns, itin> {
106 // Instructions taking Rt,Rt2,Rn
107 class A64InstRtt2n<dag outs, dag ins, string asmstr,
108 list<dag> patterns, InstrItinClass itin>
109 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
112 let Inst{14-10} = Rt2;
115 class A64InstRdnm<dag outs, dag ins, string asmstr,
116 list<dag> patterns, InstrItinClass itin>
117 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
120 let Inst{20-16} = Rm;
123 class A64InstRtnm<dag outs, dag ins, string asmstr,
124 list<dag> patterns, InstrItinClass itin>
125 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
128 let Inst{20-16} = Rm;
131 //===----------------------------------------------------------------------===//
133 // Actual A64 Instruction Formats
136 // Format for Add-subtract (extended register) instructions.
137 class A64I_addsubext<bit sf, bit op, bit S, bits<2> opt, bits<3> option,
138 dag outs, dag ins, string asmstr, list<dag> patterns,
140 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
146 let Inst{28-24} = 0b01011;
147 let Inst{23-22} = opt;
149 // Rm inherited in 20-16
150 let Inst{15-13} = option;
151 let Inst{12-10} = Imm3;
152 // Rn inherited in 9-5
153 // Rd inherited in 4-0
156 // Format for Add-subtract (immediate) instructions.
157 class A64I_addsubimm<bit sf, bit op, bit S, bits<2> shift,
158 dag outs, dag ins, string asmstr,
159 list<dag> patterns, InstrItinClass itin>
160 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
166 let Inst{28-24} = 0b10001;
167 let Inst{23-22} = shift;
168 let Inst{21-10} = Imm12;
171 // Format for Add-subtract (shifted register) instructions.
172 class A64I_addsubshift<bit sf, bit op, bit S, bits<2> shift,
173 dag outs, dag ins, string asmstr, list<dag> patterns,
175 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
181 let Inst{28-24} = 0b01011;
182 let Inst{23-22} = shift;
184 // Rm inherited in 20-16
185 let Inst{15-10} = Imm6;
186 // Rn inherited in 9-5
187 // Rd inherited in 4-0
190 // Format for Add-subtract (with carry) instructions.
191 class A64I_addsubcarry<bit sf, bit op, bit S, bits<6> opcode2,
192 dag outs, dag ins, string asmstr, list<dag> patterns,
194 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
198 let Inst{28-21} = 0b11010000;
199 // Rm inherited in 20-16
200 let Inst{15-10} = opcode2;
201 // Rn inherited in 9-5
202 // Rd inherited in 4-0
206 // Format for Bitfield instructions
207 class A64I_bitfield<bit sf, bits<2> opc, bit n,
208 dag outs, dag ins, string asmstr,
209 list<dag> patterns, InstrItinClass itin>
210 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
215 let Inst{30-29} = opc;
216 let Inst{28-23} = 0b100110;
218 let Inst{21-16} = ImmR;
219 let Inst{15-10} = ImmS;
224 // Format for compare and branch (immediate) instructions.
225 class A64I_cmpbr<bit sf, bit op,
226 dag outs, dag ins, string asmstr,
227 list<dag> patterns, InstrItinClass itin>
228 : A64InstRt<outs, ins, asmstr, patterns, itin> {
232 let Inst{30-25} = 0b011010;
234 let Inst{23-5} = Label;
238 // Format for conditional branch (immediate) instructions.
239 class A64I_condbr<bit o1, bit o0,
240 dag outs, dag ins, string asmstr,
241 list<dag> patterns, InstrItinClass itin>
242 : A64Inst<outs, ins, asmstr, patterns, itin> {
246 let Inst{31-25} = 0b0101010;
248 let Inst{23-5} = Label;
250 let Inst{3-0} = Cond;
253 // Format for conditional compare (immediate) instructions.
254 class A64I_condcmpimm<bit sf, bit op, bit o2, bit o3, bit s,
255 dag outs, dag ins, string asmstr,
256 list<dag> patterns, InstrItinClass itin>
257 : A64Inst<outs, ins, asmstr, patterns, itin> {
266 let Inst{28-21} = 0b11010010;
267 let Inst{20-16} = UImm5;
268 let Inst{15-12} = Cond;
273 let Inst{3-0} = NZCVImm;
276 // Format for conditional compare (register) instructions.
277 class A64I_condcmpreg<bit sf, bit op, bit o2, bit o3, bit s,
278 dag outs, dag ins, string asmstr,
279 list<dag> patterns, InstrItinClass itin>
280 : A64Inst<outs, ins, asmstr, patterns, itin> {
290 let Inst{28-21} = 0b11010010;
291 let Inst{20-16} = Rm;
292 let Inst{15-12} = Cond;
297 let Inst{3-0} = NZCVImm;
300 // Format for conditional select instructions.
301 class A64I_condsel<bit sf, bit op, bit s, bits<2> op2,
302 dag outs, dag ins, string asmstr,
303 list<dag> patterns, InstrItinClass itin>
304 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
310 let Inst{28-21} = 0b11010100;
311 // Inherit Rm in 20-16
312 let Inst{15-12} = Cond;
313 let Inst{11-10} = op2;
318 // Format for data processing (1 source) instructions
319 class A64I_dp_1src<bit sf, bit S, bits<5> opcode2, bits<6> opcode,
320 string asmstr, dag outs, dag ins,
321 list<dag> patterns, InstrItinClass itin>
322 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
326 let Inst{28-21} = 0b11010110;
327 let Inst{20-16} = opcode2;
328 let Inst{15-10} = opcode;
331 // Format for data processing (2 source) instructions
332 class A64I_dp_2src<bit sf, bits<6> opcode, bit S,
333 string asmstr, dag outs, dag ins,
334 list<dag> patterns, InstrItinClass itin>
335 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
339 let Inst{28-21} = 0b11010110;
340 let Inst{15-10} = opcode;
343 // Format for data-processing (3 source) instructions
345 class A64I_dp3<bit sf, bits<6> opcode,
346 dag outs, dag ins, string asmstr,
347 list<dag> patterns, InstrItinClass itin>
348 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
350 let Inst{30-29} = opcode{5-4};
351 let Inst{28-24} = 0b11011;
352 let Inst{23-21} = opcode{3-1};
353 // Inherits Rm in 20-16
354 let Inst{15} = opcode{0};
355 // {14-10} mostly Ra, but unspecified for SMULH/UMULH
356 // Inherits Rn in 9-5
357 // Inherits Rd in 4-0
360 // Format for exception generation instructions
361 class A64I_exception<bits<3> opc, bits<3> op2, bits<2> ll,
362 dag outs, dag ins, string asmstr,
363 list<dag> patterns, InstrItinClass itin>
364 : A64Inst<outs, ins, asmstr, patterns, itin> {
367 let Inst{31-24} = 0b11010100;
368 let Inst{23-21} = opc;
369 let Inst{20-5} = UImm16;
374 // Format for extract (immediate) instructions
375 class A64I_extract<bit sf, bits<3> op, bit n,
376 dag outs, dag ins, string asmstr,
377 list<dag> patterns, InstrItinClass itin>
378 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
382 let Inst{30-29} = op{2-1};
383 let Inst{28-23} = 0b100111;
385 let Inst{21} = op{0};
386 // Inherits Rm in bits 20-16
387 let Inst{15-10} = LSB;
388 // Inherits Rn in 9-5
389 // Inherits Rd in 4-0
392 let Predicates = [HasFPARMv8] in {
394 // Format for floating-point compare instructions.
395 class A64I_fpcmp<bit m, bit s, bits<2> type, bits<2> op, bits<5> opcode2,
396 dag outs, dag ins, string asmstr,
397 list<dag> patterns, InstrItinClass itin>
398 : A64Inst<outs, ins, asmstr, patterns, itin> {
405 let Inst{28-24} = 0b11110;
406 let Inst{23-22} = type;
408 let Inst{20-16} = Rm;
409 let Inst{15-14} = op;
410 let Inst{13-10} = 0b1000;
412 let Inst{4-0} = opcode2;
415 // Format for floating-point conditional compare instructions.
416 class A64I_fpccmp<bit m, bit s, bits<2> type, bit op,
417 dag outs, dag ins, string asmstr,
418 list<dag> patterns, InstrItinClass itin>
419 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
428 let Inst{28-24} = 0b11110;
429 let Inst{23-22} = type;
431 let Inst{20-16} = Rm;
432 let Inst{15-12} = Cond;
433 let Inst{11-10} = 0b01;
436 let Inst{3-0} = NZCVImm;
439 // Format for floating-point conditional select instructions.
440 class A64I_fpcondsel<bit m, bit s, bits<2> type,
441 dag outs, dag ins, string asmstr,
442 list<dag> patterns, InstrItinClass itin>
443 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
449 let Inst{28-24} = 0b11110;
450 let Inst{23-22} = type;
452 // Inherit Rm in 20-16
453 let Inst{15-12} = Cond;
454 let Inst{11-10} = 0b11;
460 // Format for floating-point data-processing (1 source) instructions.
461 class A64I_fpdp1<bit m, bit s, bits<2> type, bits<6> opcode,
462 dag outs, dag ins, string asmstr,
463 list<dag> patterns, InstrItinClass itin>
464 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
468 let Inst{28-24} = 0b11110;
469 let Inst{23-22} = type;
471 let Inst{20-15} = opcode;
472 let Inst{14-10} = 0b10000;
477 // Format for floating-point data-processing (2 sources) instructions.
478 class A64I_fpdp2<bit m, bit s, bits<2> type, bits<4> opcode,
479 dag outs, dag ins, string asmstr,
480 list<dag> patterns, InstrItinClass itin>
481 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
485 let Inst{28-24} = 0b11110;
486 let Inst{23-22} = type;
488 // Inherit Rm in 20-16
489 let Inst{15-12} = opcode;
490 let Inst{11-10} = 0b10;
495 // Format for floating-point data-processing (3 sources) instructions.
496 class A64I_fpdp3<bit m, bit s, bits<2> type, bit o1, bit o0,
497 dag outs, dag ins, string asmstr,
498 list<dag> patterns, InstrItinClass itin>
499 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
505 let Inst{28-24} = 0b11111;
506 let Inst{23-22} = type;
508 // Inherit Rm in 20-16
510 let Inst{14-10} = Ra;
515 // Format for floating-point <-> fixed-point conversion instructions.
516 class A64I_fpfixed<bit sf, bit s, bits<2> type, bits<2> mode, bits<3> opcode,
517 dag outs, dag ins, string asmstr,
518 list<dag> patterns, InstrItinClass itin>
519 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
525 let Inst{28-24} = 0b11110;
526 let Inst{23-22} = type;
528 let Inst{20-19} = mode;
529 let Inst{18-16} = opcode;
530 let Inst{15-10} = Scale;
535 // Format for floating-point <-> integer conversion instructions.
536 class A64I_fpint<bit sf, bit s, bits<2> type, bits<2> rmode, bits<3> opcode,
537 dag outs, dag ins, string asmstr,
538 list<dag> patterns, InstrItinClass itin>
539 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
543 let Inst{28-24} = 0b11110;
544 let Inst{23-22} = type;
546 let Inst{20-19} = rmode;
547 let Inst{18-16} = opcode;
548 let Inst{15-10} = 0b000000;
554 // Format for floating-point immediate instructions.
555 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
556 dag outs, dag ins, string asmstr,
557 list<dag> patterns, InstrItinClass itin>
558 : A64InstRd<outs, ins, asmstr, patterns, itin> {
564 let Inst{28-24} = 0b11110;
565 let Inst{23-22} = type;
567 let Inst{20-13} = Imm8;
568 let Inst{12-10} = 0b100;
569 let Inst{9-5} = imm5;
575 // Format for load-register (literal) instructions.
576 class A64I_LDRlit<bits<2> opc, bit v,
577 dag outs, dag ins, string asmstr,
578 list<dag> patterns, InstrItinClass itin>
579 : A64InstRt<outs, ins, asmstr, patterns, itin> {
582 let Inst{31-30} = opc;
583 let Inst{29-27} = 0b011;
585 let Inst{25-24} = 0b00;
586 let Inst{23-5} = Imm19;
590 // Format for load-store exclusive instructions.
591 class A64I_LDSTex_tn<bits<2> size, bit o2, bit L, bit o1, bit o0,
592 dag outs, dag ins, string asmstr,
593 list <dag> patterns, InstrItinClass itin>
594 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
595 let Inst{31-30} = size;
596 let Inst{29-24} = 0b001000;
603 class A64I_LDSTex_tt2n<bits<2> size, bit o2, bit L, bit o1, bit o0,
604 dag outs, dag ins, string asmstr,
605 list <dag> patterns, InstrItinClass itin>:
606 A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
608 let Inst{14-10} = Rt2;
611 class A64I_LDSTex_stn<bits<2> size, bit o2, bit L, bit o1, bit o0,
612 dag outs, dag ins, string asmstr,
613 list <dag> patterns, InstrItinClass itin>:
614 A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
616 let Inst{20-16} = Rs;
619 class A64I_LDSTex_stt2n<bits<2> size, bit o2, bit L, bit o1, bit o0,
620 dag outs, dag ins, string asmstr,
621 list <dag> patterns, InstrItinClass itin>:
622 A64I_LDSTex_stn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
624 let Inst{14-10} = Rt2;
627 // Format for load-store register (immediate post-indexed) instructions
628 class A64I_LSpostind<bits<2> size, bit v, bits<2> opc,
629 dag outs, dag ins, string asmstr,
630 list<dag> patterns, InstrItinClass itin>
631 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
634 let Inst{31-30} = size;
635 let Inst{29-27} = 0b111;
637 let Inst{25-24} = 0b00;
638 let Inst{23-22} = opc;
640 let Inst{20-12} = SImm9;
641 let Inst{11-10} = 0b01;
646 // Format for load-store register (immediate pre-indexed) instructions
647 class A64I_LSpreind<bits<2> size, bit v, bits<2> opc,
648 dag outs, dag ins, string asmstr,
649 list<dag> patterns, InstrItinClass itin>
650 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
654 let Inst{31-30} = size;
655 let Inst{29-27} = 0b111;
657 let Inst{25-24} = 0b00;
658 let Inst{23-22} = opc;
660 let Inst{20-12} = SImm9;
661 let Inst{11-10} = 0b11;
666 // Format for load-store register (unprivileged) instructions
667 class A64I_LSunpriv<bits<2> size, bit v, bits<2> opc,
668 dag outs, dag ins, string asmstr,
669 list<dag> patterns, InstrItinClass itin>
670 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
674 let Inst{31-30} = size;
675 let Inst{29-27} = 0b111;
677 let Inst{25-24} = 0b00;
678 let Inst{23-22} = opc;
680 let Inst{20-12} = SImm9;
681 let Inst{11-10} = 0b10;
686 // Format for load-store (unscaled immediate) instructions.
687 class A64I_LSunalimm<bits<2> size, bit v, bits<2> opc,
688 dag outs, dag ins, string asmstr,
689 list<dag> patterns, InstrItinClass itin>
690 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
693 let Inst{31-30} = size;
694 let Inst{29-27} = 0b111;
696 let Inst{25-24} = 0b00;
697 let Inst{23-22} = opc;
699 let Inst{20-12} = SImm9;
700 let Inst{11-10} = 0b00;
706 // Format for load-store (unsigned immediate) instructions.
707 class A64I_LSunsigimm<bits<2> size, bit v, bits<2> opc,
708 dag outs, dag ins, string asmstr,
709 list<dag> patterns, InstrItinClass itin>
710 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
713 let Inst{31-30} = size;
714 let Inst{29-27} = 0b111;
716 let Inst{25-24} = 0b01;
717 let Inst{23-22} = opc;
718 let Inst{21-10} = UImm12;
721 // Format for load-store register (register offset) instructions.
722 class A64I_LSregoff<bits<2> size, bit v, bits<2> opc, bit optionlo,
723 dag outs, dag ins, string asmstr,
724 list<dag> patterns, InstrItinClass itin>
725 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
728 // Complex operand selection needed for these instructions, so they
729 // need an "addr" field for encoding/decoding to be generated.
731 // OptionHi = Ext{2-1}
734 let Inst{31-30} = size;
735 let Inst{29-27} = 0b111;
737 let Inst{25-24} = 0b00;
738 let Inst{23-22} = opc;
740 let Inst{20-16} = Rm;
741 let Inst{15-14} = Ext{2-1};
742 let Inst{13} = optionlo;
743 let Inst{12} = Ext{0};
744 let Inst{11-10} = 0b10;
745 // Inherits Rn in 9-5
746 // Inherits Rt in 4-0
748 let AddedComplexity = 50;
751 // Format for Load-store register pair (offset) instructions
752 class A64I_LSPoffset<bits<2> opc, bit v, bit l,
753 dag outs, dag ins, string asmstr,
754 list<dag> patterns, InstrItinClass itin>
755 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
758 let Inst{31-30} = opc;
759 let Inst{29-27} = 0b101;
761 let Inst{25-23} = 0b010;
763 let Inst{21-15} = SImm7;
764 // Inherit Rt2 in 14-10
769 // Format for Load-store register pair (post-indexed) instructions
770 class A64I_LSPpostind<bits<2> opc, bit v, bit l,
771 dag outs, dag ins, string asmstr,
772 list<dag> patterns, InstrItinClass itin>
773 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
776 let Inst{31-30} = opc;
777 let Inst{29-27} = 0b101;
779 let Inst{25-23} = 0b001;
781 let Inst{21-15} = SImm7;
782 // Inherit Rt2 in 14-10
787 // Format for Load-store register pair (pre-indexed) instructions
788 class A64I_LSPpreind<bits<2> opc, bit v, bit l,
789 dag outs, dag ins, string asmstr,
790 list<dag> patterns, InstrItinClass itin>
791 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
794 let Inst{31-30} = opc;
795 let Inst{29-27} = 0b101;
797 let Inst{25-23} = 0b011;
799 let Inst{21-15} = SImm7;
800 // Inherit Rt2 in 14-10
805 // Format for Load-store non-temporal register pair (offset) instructions
806 class A64I_LSPnontemp<bits<2> opc, bit v, bit l,
807 dag outs, dag ins, string asmstr,
808 list<dag> patterns, InstrItinClass itin>
809 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
812 let Inst{31-30} = opc;
813 let Inst{29-27} = 0b101;
815 let Inst{25-23} = 0b000;
817 let Inst{21-15} = SImm7;
818 // Inherit Rt2 in 14-10
823 // Format for Logical (immediate) instructions
824 class A64I_logicalimm<bit sf, bits<2> opc,
825 dag outs, dag ins, string asmstr,
826 list<dag> patterns, InstrItinClass itin>
827 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
832 // N, ImmR and ImmS have no separate existence in any assembly syntax (or for
833 // selection), so we'll combine them into a single field here.
840 let Inst{30-29} = opc;
841 let Inst{28-23} = 0b100100;
842 let Inst{22} = Imm{12};
843 let Inst{21-16} = Imm{11-6};
844 let Inst{15-10} = Imm{5-0};
845 // Rn inherited in 9-5
846 // Rd inherited in 4-0
849 // Format for Logical (shifted register) instructions
850 class A64I_logicalshift<bit sf, bits<2> opc, bits<2> shift, bit N,
851 dag outs, dag ins, string asmstr,
852 list<dag> patterns, InstrItinClass itin>
853 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
857 let Inst{30-29} = opc;
858 let Inst{28-24} = 0b01010;
859 let Inst{23-22} = shift;
862 let Inst{15-10} = Imm6;
867 // Format for Move wide (immediate)
868 class A64I_movw<bit sf, bits<2> opc,
869 dag outs, dag ins, string asmstr,
870 list<dag> patterns, InstrItinClass itin>
871 : A64InstRd<outs, ins, asmstr, patterns, itin> {
873 bits<2> Shift; // Called "hw" officially
876 let Inst{30-29} = opc;
877 let Inst{28-23} = 0b100101;
878 let Inst{22-21} = Shift;
879 let Inst{20-5} = UImm16;
880 // Inherits Rd in 4-0
883 // Format for PC-relative addressing instructions, ADR and ADRP.
884 class A64I_PCADR<bit op,
885 dag outs, dag ins, string asmstr,
886 list<dag> patterns, InstrItinClass itin>
887 : A64InstRd<outs, ins, asmstr, patterns, itin> {
891 let Inst{30-29} = Label{1-0};
892 let Inst{28-24} = 0b10000;
893 let Inst{23-5} = Label{20-2};
896 // Format for system instructions
897 class A64I_system<bit l,
898 dag outs, dag ins, string asmstr,
899 list<dag> patterns, InstrItinClass itin>
900 : A64Inst<outs, ins, asmstr, patterns, itin> {
908 let Inst{31-22} = 0b1101010100;
910 let Inst{20-19} = Op0;
911 let Inst{18-16} = Op1;
912 let Inst{15-12} = CRn;
913 let Inst{11-8} = CRm;
917 // These instructions can do horrible things.
918 let hasSideEffects = 1;
921 // Format for unconditional branch (immediate) instructions
922 class A64I_Bimm<bit op,
923 dag outs, dag ins, string asmstr,
924 list<dag> patterns, InstrItinClass itin>
925 : A64Inst<outs, ins, asmstr, patterns, itin> {
926 // Doubly special in not even sharing register fields with other
927 // instructions, so we create our own Rn here.
931 let Inst{30-26} = 0b00101;
932 let Inst{25-0} = Label;
935 // Format for Test & branch (immediate) instructions
936 class A64I_TBimm<bit op,
937 dag outs, dag ins, string asmstr,
938 list<dag> patterns, InstrItinClass itin>
939 : A64InstRt<outs, ins, asmstr, patterns, itin> {
940 // Doubly special in not even sharing register fields with other
941 // instructions, so we create our own Rn here.
945 let Inst{31} = Imm{5};
946 let Inst{30-25} = 0b011011;
948 let Inst{23-19} = Imm{4-0};
949 let Inst{18-5} = Label;
953 // Format for Unconditional branch (register) instructions, including
954 // RET. Shares no fields with instructions further up the hierarchy
956 class A64I_Breg<bits<4> opc, bits<5> op2, bits<6> op3, bits<5> op4,
957 dag outs, dag ins, string asmstr,
958 list<dag> patterns, InstrItinClass itin>
959 : A64Inst<outs, ins, asmstr, patterns, itin> {
960 // Doubly special in not even sharing register fields with other
961 // instructions, so we create our own Rn here.
964 let Inst{31-25} = 0b1101011;
965 let Inst{24-21} = opc;
966 let Inst{20-16} = op2;
967 let Inst{15-10} = op3;
973 //===----------------------------------------------------------------------===//
975 // Neon Instruction Format Definitions.
978 let Predicates = [HasNEON] in {
980 class NeonInstAlias<string Asm, dag Result, bit Emit = 0b1>
981 : InstAlias<Asm, Result, Emit> {
984 // Format AdvSIMD bitwise extract
985 class NeonI_BitExtract<bit q, bits<2> op2,
986 dag outs, dag ins, string asmstr,
987 list<dag> patterns, InstrItinClass itin>
988 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
991 let Inst{29-24} = 0b101110;
992 let Inst{23-22} = op2;
994 // Inherit Rm in 20-16
1002 // Format AdvSIMD perm
1003 class NeonI_Perm<bit q, bits<2> size, bits<3> opcode,
1004 dag outs, dag ins, string asmstr,
1005 list<dag> patterns, InstrItinClass itin>
1006 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1009 let Inst{29-24} = 0b001110;
1010 let Inst{23-22} = size;
1012 // Inherit Rm in 20-16
1014 let Inst{14-12} = opcode;
1015 let Inst{11-10} = 0b10;
1016 // Inherit Rn in 9-5
1017 // Inherit Rd in 4-0
1020 // Format AdvSIMD table lookup
1021 class NeonI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
1022 dag outs, dag ins, string asmstr,
1023 list<dag> patterns, InstrItinClass itin>
1024 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1027 let Inst{29-24} = 0b001110;
1028 let Inst{23-22} = op2;
1030 // Inherit Rm in 20-16
1032 let Inst{14-13} = len;
1034 let Inst{11-10} = 0b00;
1035 // Inherit Rn in 9-5
1036 // Inherit Rd in 4-0
1039 // Format AdvSIMD 3 vector registers with same vector type
1040 class NeonI_3VSame<bit q, bit u, bits<2> size, bits<5> opcode,
1041 dag outs, dag ins, string asmstr,
1042 list<dag> patterns, InstrItinClass itin>
1043 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1047 let Inst{28-24} = 0b01110;
1048 let Inst{23-22} = size;
1050 // Inherit Rm in 20-16
1051 let Inst{15-11} = opcode;
1053 // Inherit Rn in 9-5
1054 // Inherit Rd in 4-0
1057 // Format AdvSIMD 3 vector registers with different vector type
1058 class NeonI_3VDiff<bit q, bit u, bits<2> size, bits<4> opcode,
1059 dag outs, dag ins, string asmstr,
1060 list<dag> patterns, InstrItinClass itin>
1061 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1065 let Inst{28-24} = 0b01110;
1066 let Inst{23-22} = size;
1068 // Inherit Rm in 20-16
1069 let Inst{15-12} = opcode;
1072 // Inherit Rn in 9-5
1073 // Inherit Rd in 4-0
1076 // Format AdvSIMD two registers and an element
1077 class NeonI_2VElem<bit q, bit u, bits<2> size, bits<4> opcode,
1078 dag outs, dag ins, string asmstr,
1079 list<dag> patterns, InstrItinClass itin>
1080 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1084 let Inst{28-24} = 0b01111;
1085 let Inst{23-22} = size;
1088 // Inherit Rm in 19-16
1089 let Inst{15-12} = opcode;
1092 // Inherit Rn in 9-5
1093 // Inherit Rd in 4-0
1096 // Format AdvSIMD 1 vector register with modified immediate
1097 class NeonI_1VModImm<bit q, bit op,
1098 dag outs, dag ins, string asmstr,
1099 list<dag> patterns, InstrItinClass itin>
1100 : A64InstRd<outs,ins, asmstr, patterns, itin> {
1106 let Inst{28-19} = 0b0111100000;
1107 let Inst{15-12} = cmode;
1108 let Inst{11} = 0b0; // o2
1110 // Inherit Rd in 4-0
1111 let Inst{18-16} = Imm{7-5}; // imm a:b:c
1112 let Inst{9-5} = Imm{4-0}; // imm d:e:f:g:h
1115 // Format AdvSIMD 3 scalar registers with same type
1117 class NeonI_Scalar3Same<bit u, bits<2> size, bits<5> opcode,
1118 dag outs, dag ins, string asmstr,
1119 list<dag> patterns, InstrItinClass itin>
1120 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1124 let Inst{28-24} = 0b11110;
1125 let Inst{23-22} = size;
1127 // Inherit Rm in 20-16
1128 let Inst{15-11} = opcode;
1130 // Inherit Rn in 9-5
1131 // Inherit Rd in 4-0
1135 // Format AdvSIMD 2 vector registers miscellaneous
1136 class NeonI_2VMisc<bit q, bit u, bits<2> size, bits<5> opcode,
1137 dag outs, dag ins, string asmstr,
1138 list<dag> patterns, InstrItinClass itin>
1139 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1143 let Inst{28-24} = 0b01110;
1144 let Inst{23-22} = size;
1145 let Inst{21-17} = 0b10000;
1146 let Inst{16-12} = opcode;
1147 let Inst{11-10} = 0b10;
1149 // Inherit Rn in 9-5
1150 // Inherit Rd in 4-0
1153 // Format AdvSIMD 2 vector 1 immediate shift
1154 class NeonI_2VShiftImm<bit q, bit u, bits<5> opcode,
1155 dag outs, dag ins, string asmstr,
1156 list<dag> patterns, InstrItinClass itin>
1157 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1162 let Inst{28-23} = 0b011110;
1163 let Inst{22-16} = Imm;
1164 let Inst{15-11} = opcode;
1167 // Inherit Rn in 9-5
1168 // Inherit Rd in 4-0
1171 // Format AdvSIMD duplicate and insert
1172 class NeonI_copy<bit q, bit op, bits<4> imm4,
1173 dag outs, dag ins, string asmstr,
1174 list<dag> patterns, InstrItinClass itin>
1175 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1180 let Inst{28-21} = 0b01110000;
1181 let Inst{20-16} = Imm5;
1183 let Inst{14-11} = imm4;
1186 // Inherit Rn in 9-5
1187 // Inherit Rd in 4-0
1189 // Format AdvSIMD insert from element to vector
1190 class NeonI_insert<bit q, bit op,
1191 dag outs, dag ins, string asmstr,
1192 list<dag> patterns, InstrItinClass itin>
1193 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1199 let Inst{28-21} = 0b01110000;
1200 let Inst{20-16} = Imm5;
1202 let Inst{14-11} = Imm4;
1205 // Inherit Rn in 9-5
1206 // Inherit Rd in 4-0
1209 // Format AdvSIMD scalar pairwise
1210 class NeonI_ScalarPair<bit u, bits<2> size, bits<5> opcode,
1211 dag outs, dag ins, string asmstr,
1212 list<dag> patterns, InstrItinClass itin>
1213 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1217 let Inst{28-24} = 0b11110;
1218 let Inst{23-22} = size;
1219 let Inst{21-17} = 0b11000;
1220 let Inst{16-12} = opcode;
1221 let Inst{11-10} = 0b10;
1223 // Inherit Rn in 9-5
1224 // Inherit Rd in 4-0
1227 // Format AdvSIMD 2 vector across lanes
1228 class NeonI_2VAcross<bit q, bit u, bits<2> size, bits<5> opcode,
1229 dag outs, dag ins, string asmstr,
1230 list<dag> patterns, InstrItinClass itin>
1231 : A64InstRdn<outs, ins, asmstr, patterns, itin>
1236 let Inst{28-24} = 0b01110;
1237 let Inst{23-22} = size;
1238 let Inst{21-17} = 0b11000;
1239 let Inst{16-12} = opcode;
1240 let Inst{11-10} = 0b10;
1242 // Inherit Rn in 9-5
1243 // Inherit Rd in 4-0
1246 // Format AdvSIMD scalar two registers miscellaneous
1247 class NeonI_Scalar2SameMisc<bit u, bits<2> size, bits<5> opcode, dag outs, dag ins,
1248 string asmstr, list<dag> patterns, InstrItinClass itin>
1249 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1253 let Inst{28-24} = 0b11110;
1254 let Inst{23-22} = size;
1255 let Inst{21-17} = 0b10000;
1256 let Inst{16-12} = opcode;
1257 let Inst{11-10} = 0b10;
1258 // Inherit Rn in 9-5
1259 // Inherit Rd in 4-0
1262 // Format AdvSIMD vector load/store multiple N-element structure
1263 class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size,
1264 dag outs, dag ins, string asmstr,
1265 list<dag> patterns, InstrItinClass itin>
1266 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1270 let Inst{29-23} = 0b0011000;
1272 let Inst{21-16} = 0b000000;
1273 let Inst{15-12} = opcode;
1274 let Inst{11-10} = size;
1276 // Inherit Rn in 9-5
1277 // Inherit Rt in 4-0
1280 // Format AdvSIMD vector load/store multiple N-element structure (post-index)
1281 class NeonI_LdStMult_Post<bit q, bit l, bits<4> opcode, bits<2> size,
1282 dag outs, dag ins, string asmstr,
1283 list<dag> patterns, InstrItinClass itin>
1284 : A64InstRtnm<outs, ins, asmstr, patterns, itin>
1288 let Inst{29-23} = 0b0011001;
1291 // Inherit Rm in 20-16
1292 let Inst{15-12} = opcode;
1293 let Inst{11-10} = size;
1294 // Inherit Rn in 9-5
1295 // Inherit Rt in 4-0
1298 // Format AdvSIMD vector load Single N-element structure to all lanes
1299 class NeonI_LdOne_Dup<bit q, bit r, bits<3> opcode, bits<2> size, dag outs,
1300 dag ins, string asmstr, list<dag> patterns,
1301 InstrItinClass itin>
1302 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1306 let Inst{29-23} = 0b0011010;
1309 let Inst{20-16} = 0b00000;
1310 let Inst{15-13} = opcode;
1312 let Inst{11-10} = size;
1314 // Inherit Rn in 9-5
1315 // Inherit Rt in 4-0
1318 // Format AdvSIMD vector load/store Single N-element structure to/from one lane
1319 class NeonI_LdStOne_Lane<bit l, bit r, bits<2> op2_1, bit op0, dag outs,
1320 dag ins, string asmstr,
1321 list<dag> patterns, InstrItinClass itin>
1322 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1326 let Inst{29-23} = 0b0011010;
1329 let Inst{20-16} = 0b00000;
1330 let Inst{15-14} = op2_1;
1333 // Inherit Rn in 9-5
1334 // Inherit Rt in 4-0
1337 // Format AdvSIMD post-index vector load Single N-element structure to all lanes
1338 class NeonI_LdOne_Dup_Post<bit q, bit r, bits<3> opcode, bits<2> size, dag outs,
1339 dag ins, string asmstr, list<dag> patterns,
1340 InstrItinClass itin>
1341 : A64InstRtnm<outs, ins, asmstr, patterns, itin>
1345 let Inst{29-23} = 0b0011011;
1348 // Inherit Rm in 20-16
1349 let Inst{15-13} = opcode;
1351 let Inst{11-10} = size;
1353 // Inherit Rn in 9-5
1354 // Inherit Rt in 4-0
1357 // Format AdvSIMD post-index vector load/store Single N-element structure
1359 class NeonI_LdStOne_Lane_Post<bit l, bit r, bits<2> op2_1, bit op0, dag outs,
1360 dag ins, string asmstr,
1361 list<dag> patterns, InstrItinClass itin>
1362 : A64InstRtnm<outs, ins, asmstr, patterns, itin>
1366 let Inst{29-23} = 0b0011011;
1369 // Inherit Rm in 20-16
1370 let Inst{15-14} = op2_1;
1373 // Inherit Rn in 9-5
1374 // Inherit Rt in 4-0
1377 // Format AdvSIMD 3 scalar registers with different type
1379 class NeonI_Scalar3Diff<bit u, bits<2> size, bits<4> opcode,
1380 dag outs, dag ins, string asmstr,
1381 list<dag> patterns, InstrItinClass itin>
1382 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1383 let Inst{31-30} = 0b01;
1385 let Inst{28-24} = 0b11110;
1386 let Inst{23-22} = size;
1388 // Inherit Rm in 20-16
1389 let Inst{15-12} = opcode;
1390 let Inst{11-10} = 0b00;
1391 // Inherit Rn in 9-5
1392 // Inherit Rd in 4-0
1395 // Format AdvSIMD scalar shift by immediate
1397 class NeonI_ScalarShiftImm<bit u, bits<5> opcode,
1398 dag outs, dag ins, string asmstr,
1399 list<dag> patterns, InstrItinClass itin>
1400 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1403 let Inst{31-30} = 0b01;
1405 let Inst{28-23} = 0b111110;
1406 let Inst{22-19} = Imm4;
1407 let Inst{18-16} = Imm3;
1408 let Inst{15-11} = opcode;
1410 // Inherit Rn in 9-5
1411 // Inherit Rd in 4-0
1414 // Format AdvSIMD crypto AES
1415 class NeonI_Crypto_AES<bits<2> size, bits<5> opcode,
1416 dag outs, dag ins, string asmstr,
1417 list<dag> patterns, InstrItinClass itin>
1418 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1419 let Inst{31-24} = 0b01001110;
1420 let Inst{23-22} = size;
1421 let Inst{21-17} = 0b10100;
1422 let Inst{16-12} = opcode;
1423 let Inst{11-10} = 0b10;
1424 // Inherit Rn in 9-5
1425 // Inherit Rd in 4-0
1428 // Format AdvSIMD crypto SHA
1429 class NeonI_Crypto_SHA<bits<2> size, bits<5> opcode,
1430 dag outs, dag ins, string asmstr,
1431 list<dag> patterns, InstrItinClass itin>
1432 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1433 let Inst{31-24} = 0b01011110;
1434 let Inst{23-22} = size;
1435 let Inst{21-17} = 0b10100;
1436 let Inst{16-12} = opcode;
1437 let Inst{11-10} = 0b10;
1438 // Inherit Rn in 9-5
1439 // Inherit Rd in 4-0
1442 // Format AdvSIMD crypto 3V SHA
1443 class NeonI_Crypto_3VSHA<bits<2> size, bits<3> opcode,
1444 dag outs, dag ins, string asmstr,
1445 list<dag> patterns, InstrItinClass itin>
1446 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1447 let Inst{31-24} = 0b01011110;
1448 let Inst{23-22} = size;
1450 // Inherit Rm in 20-16
1452 let Inst{14-12} = opcode;
1453 let Inst{11-10} = 0b00;
1454 // Inherit Rn in 9-5
1455 // Inherit Rd in 4-0
1458 // Format AdvSIMD scalar x indexed element
1459 class NeonI_ScalarXIndexedElem<bit u, bit szhi, bit szlo,
1460 bits<4> opcode, dag outs, dag ins,
1461 string asmstr, list<dag> patterns,
1462 InstrItinClass itin>
1463 : A64InstRdnm<outs, ins, asmstr, patterns, itin>
1468 let Inst{28-24} = 0b11111;
1469 let Inst{23} = szhi;
1470 let Inst{22} = szlo;
1473 // Inherit Rm in 19-16
1474 let Inst{15-12} = opcode;
1477 // Inherit Rn in 9-5
1478 // Inherit Rd in 4-0
1480 // Format AdvSIMD scalar copy - insert from element to scalar
1481 class NeonI_ScalarCopy<dag outs, dag ins, string asmstr,
1482 list<dag> patterns, InstrItinClass itin>
1483 : NeonI_copy<0b1, 0b0, 0b0000, outs, ins, asmstr, patterns, itin> {