1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 class AsmImmRange<int Low, int High> : AsmOperandClass {
252 let Name = "Imm" # Low # "_" # High;
253 let DiagnosticType = "InvalidImm" # Low # "_" # High;
256 def Imm1_8Operand : AsmImmRange<1, 8>;
257 def Imm1_16Operand : AsmImmRange<1, 16>;
258 def Imm1_32Operand : AsmImmRange<1, 32>;
259 def Imm1_64Operand : AsmImmRange<1, 64>;
261 def MovZSymbolG3AsmOperand : AsmOperandClass {
262 let Name = "MovZSymbolG3";
263 let RenderMethod = "addImmOperands";
266 def movz_symbol_g3 : Operand<i32> {
267 let ParserMatchClass = MovZSymbolG3AsmOperand;
270 def MovZSymbolG2AsmOperand : AsmOperandClass {
271 let Name = "MovZSymbolG2";
272 let RenderMethod = "addImmOperands";
275 def movz_symbol_g2 : Operand<i32> {
276 let ParserMatchClass = MovZSymbolG2AsmOperand;
279 def MovZSymbolG1AsmOperand : AsmOperandClass {
280 let Name = "MovZSymbolG1";
281 let RenderMethod = "addImmOperands";
284 def movz_symbol_g1 : Operand<i32> {
285 let ParserMatchClass = MovZSymbolG1AsmOperand;
288 def MovZSymbolG0AsmOperand : AsmOperandClass {
289 let Name = "MovZSymbolG0";
290 let RenderMethod = "addImmOperands";
293 def movz_symbol_g0 : Operand<i32> {
294 let ParserMatchClass = MovZSymbolG0AsmOperand;
297 def MovKSymbolG3AsmOperand : AsmOperandClass {
298 let Name = "MovKSymbolG3";
299 let RenderMethod = "addImmOperands";
302 def movk_symbol_g3 : Operand<i32> {
303 let ParserMatchClass = MovKSymbolG3AsmOperand;
306 def MovKSymbolG2AsmOperand : AsmOperandClass {
307 let Name = "MovKSymbolG2";
308 let RenderMethod = "addImmOperands";
311 def movk_symbol_g2 : Operand<i32> {
312 let ParserMatchClass = MovKSymbolG2AsmOperand;
315 def MovKSymbolG1AsmOperand : AsmOperandClass {
316 let Name = "MovKSymbolG1";
317 let RenderMethod = "addImmOperands";
320 def movk_symbol_g1 : Operand<i32> {
321 let ParserMatchClass = MovKSymbolG1AsmOperand;
324 def MovKSymbolG0AsmOperand : AsmOperandClass {
325 let Name = "MovKSymbolG0";
326 let RenderMethod = "addImmOperands";
329 def movk_symbol_g0 : Operand<i32> {
330 let ParserMatchClass = MovKSymbolG0AsmOperand;
333 class fixedpoint_i32<ValueType FloatVT>
335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
336 let EncoderMethod = "getFixedPointScaleOpValue";
337 let DecoderMethod = "DecodeFixedPointScaleImm32";
338 let ParserMatchClass = Imm1_32Operand;
341 class fixedpoint_i64<ValueType FloatVT>
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
344 let EncoderMethod = "getFixedPointScaleOpValue";
345 let DecoderMethod = "DecodeFixedPointScaleImm64";
346 let ParserMatchClass = Imm1_64Operand;
349 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
350 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
352 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
353 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
355 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
358 let EncoderMethod = "getVecShiftR8OpValue";
359 let DecoderMethod = "DecodeVecShiftR8Imm";
360 let ParserMatchClass = Imm1_8Operand;
362 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
363 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
365 let EncoderMethod = "getVecShiftR16OpValue";
366 let DecoderMethod = "DecodeVecShiftR16Imm";
367 let ParserMatchClass = Imm1_16Operand;
369 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
370 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
372 let EncoderMethod = "getVecShiftR16OpValue";
373 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
374 let ParserMatchClass = Imm1_8Operand;
376 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
377 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
379 let EncoderMethod = "getVecShiftR32OpValue";
380 let DecoderMethod = "DecodeVecShiftR32Imm";
381 let ParserMatchClass = Imm1_32Operand;
383 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
384 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
386 let EncoderMethod = "getVecShiftR32OpValue";
387 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
388 let ParserMatchClass = Imm1_16Operand;
390 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
391 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
393 let EncoderMethod = "getVecShiftR64OpValue";
394 let DecoderMethod = "DecodeVecShiftR64Imm";
395 let ParserMatchClass = Imm1_64Operand;
397 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
398 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
400 let EncoderMethod = "getVecShiftR64OpValue";
401 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
402 let ParserMatchClass = Imm1_32Operand;
405 def Imm0_7Operand : AsmImmRange<0, 7>;
406 def Imm0_15Operand : AsmImmRange<0, 15>;
407 def Imm0_31Operand : AsmImmRange<0, 31>;
408 def Imm0_63Operand : AsmImmRange<0, 63>;
410 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
411 return (((uint32_t)Imm) < 8);
413 let EncoderMethod = "getVecShiftL8OpValue";
414 let DecoderMethod = "DecodeVecShiftL8Imm";
415 let ParserMatchClass = Imm0_7Operand;
417 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
418 return (((uint32_t)Imm) < 16);
420 let EncoderMethod = "getVecShiftL16OpValue";
421 let DecoderMethod = "DecodeVecShiftL16Imm";
422 let ParserMatchClass = Imm0_15Operand;
424 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
425 return (((uint32_t)Imm) < 32);
427 let EncoderMethod = "getVecShiftL32OpValue";
428 let DecoderMethod = "DecodeVecShiftL32Imm";
429 let ParserMatchClass = Imm0_31Operand;
431 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
432 return (((uint32_t)Imm) < 64);
434 let EncoderMethod = "getVecShiftL64OpValue";
435 let DecoderMethod = "DecodeVecShiftL64Imm";
436 let ParserMatchClass = Imm0_63Operand;
440 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
441 // instructions for splatting repeating bit patterns across the immediate.
442 def logical_imm32_XFORM : SDNodeXForm<imm, [{
443 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
444 return CurDAG->getTargetConstant(enc, MVT::i32);
446 def logical_imm64_XFORM : SDNodeXForm<imm, [{
447 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
448 return CurDAG->getTargetConstant(enc, MVT::i32);
451 let DiagnosticType = "LogicalSecondSource" in {
452 def LogicalImm32Operand : AsmOperandClass {
453 let Name = "LogicalImm32";
455 def LogicalImm64Operand : AsmOperandClass {
456 let Name = "LogicalImm64";
458 def LogicalImm32NotOperand : AsmOperandClass {
459 let Name = "LogicalImm32Not";
461 def LogicalImm64NotOperand : AsmOperandClass {
462 let Name = "LogicalImm64Not";
465 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
466 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
467 }], logical_imm32_XFORM> {
468 let PrintMethod = "printLogicalImm32";
469 let ParserMatchClass = LogicalImm32Operand;
471 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
472 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
473 }], logical_imm64_XFORM> {
474 let PrintMethod = "printLogicalImm64";
475 let ParserMatchClass = LogicalImm64Operand;
477 def logical_imm32_not : Operand<i32> {
478 let ParserMatchClass = LogicalImm32NotOperand;
480 def logical_imm64_not : Operand<i64> {
481 let ParserMatchClass = LogicalImm64NotOperand;
484 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
485 def Imm0_65535Operand : AsmImmRange<0, 65535>;
486 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
487 return ((uint32_t)Imm) < 65536;
489 let ParserMatchClass = Imm0_65535Operand;
490 let PrintMethod = "printHexImm";
493 // imm0_255 predicate - True if the immediate is in the range [0,255].
494 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
495 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
496 return ((uint32_t)Imm) < 256;
498 let ParserMatchClass = Imm0_255Operand;
499 let PrintMethod = "printHexImm";
502 // imm0_127 predicate - True if the immediate is in the range [0,127]
503 def Imm0_127Operand : AsmImmRange<0, 127>;
504 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
505 return ((uint32_t)Imm) < 128;
507 let ParserMatchClass = Imm0_127Operand;
508 let PrintMethod = "printHexImm";
511 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
512 // for all shift-amounts.
514 // imm0_63 predicate - True if the immediate is in the range [0,63]
515 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
516 return ((uint64_t)Imm) < 64;
518 let ParserMatchClass = Imm0_63Operand;
521 // imm0_31 predicate - True if the immediate is in the range [0,31]
522 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
523 return ((uint64_t)Imm) < 32;
525 let ParserMatchClass = Imm0_31Operand;
528 // imm0_15 predicate - True if the immediate is in the range [0,15]
529 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
530 return ((uint64_t)Imm) < 16;
532 let ParserMatchClass = Imm0_15Operand;
535 // imm0_7 predicate - True if the immediate is in the range [0,7]
536 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
537 return ((uint64_t)Imm) < 8;
539 let ParserMatchClass = Imm0_7Operand;
542 // imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
543 def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
544 return ((uint32_t)Imm) < 16;
547 // An arithmetic shifter operand:
548 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
550 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
551 let PrintMethod = "printShifter";
552 let ParserMatchClass = !cast<AsmOperandClass>(
553 "ArithmeticShifterOperand" # width);
556 def arith_shift32 : arith_shift<i32, 32>;
557 def arith_shift64 : arith_shift<i64, 64>;
559 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
561 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
562 let PrintMethod = "printShiftedRegister";
563 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
566 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
567 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
569 // An arithmetic shifter operand:
570 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
572 class logical_shift<int width> : Operand<i32> {
573 let PrintMethod = "printShifter";
574 let ParserMatchClass = !cast<AsmOperandClass>(
575 "LogicalShifterOperand" # width);
578 def logical_shift32 : logical_shift<32>;
579 def logical_shift64 : logical_shift<64>;
581 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
583 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
584 let PrintMethod = "printShiftedRegister";
585 let MIOperandInfo = (ops regclass, shiftop);
588 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
589 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
591 // A logical vector shifter operand:
592 // {7-6} - shift type: 00 = lsl
593 // {5-0} - imm6: #0, #8, #16, or #24
594 def logical_vec_shift : Operand<i32> {
595 let PrintMethod = "printShifter";
596 let EncoderMethod = "getVecShifterOpValue";
597 let ParserMatchClass = LogicalVecShifterOperand;
600 // A logical vector half-word shifter operand:
601 // {7-6} - shift type: 00 = lsl
602 // {5-0} - imm6: #0 or #8
603 def logical_vec_hw_shift : Operand<i32> {
604 let PrintMethod = "printShifter";
605 let EncoderMethod = "getVecShifterOpValue";
606 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
609 // A vector move shifter operand:
610 // {0} - imm1: #8 or #16
611 def move_vec_shift : Operand<i32> {
612 let PrintMethod = "printShifter";
613 let EncoderMethod = "getMoveVecShifterOpValue";
614 let ParserMatchClass = MoveVecShifterOperand;
617 def AddSubImmOperand : AsmOperandClass {
618 let Name = "AddSubImm";
619 let ParserMethod = "tryParseAddSubImm";
620 let DiagnosticType = "AddSubSecondSource";
622 // An ADD/SUB immediate shifter operand:
624 // {7-6} - shift type: 00 = lsl
625 // {5-0} - imm6: #0 or #12
626 class addsub_shifted_imm<ValueType Ty>
627 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
628 let PrintMethod = "printAddSubImm";
629 let EncoderMethod = "getAddSubImmOpValue";
630 let ParserMatchClass = AddSubImmOperand;
631 let MIOperandInfo = (ops i32imm, i32imm);
634 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
635 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
637 class neg_addsub_shifted_imm<ValueType Ty>
638 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
639 let PrintMethod = "printAddSubImm";
640 let EncoderMethod = "getAddSubImmOpValue";
641 let ParserMatchClass = AddSubImmOperand;
642 let MIOperandInfo = (ops i32imm, i32imm);
645 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
646 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
648 // An extend operand:
649 // {5-3} - extend type
651 def arith_extend : Operand<i32> {
652 let PrintMethod = "printArithExtend";
653 let ParserMatchClass = ExtendOperand;
655 def arith_extend64 : Operand<i32> {
656 let PrintMethod = "printArithExtend";
657 let ParserMatchClass = ExtendOperand64;
660 // 'extend' that's a lsl of a 64-bit register.
661 def arith_extendlsl64 : Operand<i32> {
662 let PrintMethod = "printArithExtend";
663 let ParserMatchClass = ExtendOperandLSL64;
666 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
667 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
668 let PrintMethod = "printExtendedRegister";
669 let MIOperandInfo = (ops GPR32, arith_extend);
672 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
673 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
674 let PrintMethod = "printExtendedRegister";
675 let MIOperandInfo = (ops GPR32, arith_extend64);
678 // Floating-point immediate.
679 def fpimm32 : Operand<f32>,
680 PatLeaf<(f32 fpimm), [{
681 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
682 }], SDNodeXForm<fpimm, [{
683 APFloat InVal = N->getValueAPF();
684 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
685 return CurDAG->getTargetConstant(enc, MVT::i32);
687 let ParserMatchClass = FPImmOperand;
688 let PrintMethod = "printFPImmOperand";
690 def fpimm64 : Operand<f64>,
691 PatLeaf<(f64 fpimm), [{
692 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
693 }], SDNodeXForm<fpimm, [{
694 APFloat InVal = N->getValueAPF();
695 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
696 return CurDAG->getTargetConstant(enc, MVT::i32);
698 let ParserMatchClass = FPImmOperand;
699 let PrintMethod = "printFPImmOperand";
702 def fpimm8 : Operand<i32> {
703 let ParserMatchClass = FPImmOperand;
704 let PrintMethod = "printFPImmOperand";
707 def fpimm0 : PatLeaf<(fpimm), [{
708 return N->isExactlyValue(+0.0);
711 // Vector lane operands
712 class AsmVectorIndex<string Suffix> : AsmOperandClass {
713 let Name = "VectorIndex" # Suffix;
714 let DiagnosticType = "InvalidIndex" # Suffix;
716 def VectorIndex1Operand : AsmVectorIndex<"1">;
717 def VectorIndexBOperand : AsmVectorIndex<"B">;
718 def VectorIndexHOperand : AsmVectorIndex<"H">;
719 def VectorIndexSOperand : AsmVectorIndex<"S">;
720 def VectorIndexDOperand : AsmVectorIndex<"D">;
722 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
723 return ((uint64_t)Imm) == 1;
725 let ParserMatchClass = VectorIndex1Operand;
726 let PrintMethod = "printVectorIndex";
727 let MIOperandInfo = (ops i64imm);
729 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
730 return ((uint64_t)Imm) < 16;
732 let ParserMatchClass = VectorIndexBOperand;
733 let PrintMethod = "printVectorIndex";
734 let MIOperandInfo = (ops i64imm);
736 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
737 return ((uint64_t)Imm) < 8;
739 let ParserMatchClass = VectorIndexHOperand;
740 let PrintMethod = "printVectorIndex";
741 let MIOperandInfo = (ops i64imm);
743 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
744 return ((uint64_t)Imm) < 4;
746 let ParserMatchClass = VectorIndexSOperand;
747 let PrintMethod = "printVectorIndex";
748 let MIOperandInfo = (ops i64imm);
750 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
751 return ((uint64_t)Imm) < 2;
753 let ParserMatchClass = VectorIndexDOperand;
754 let PrintMethod = "printVectorIndex";
755 let MIOperandInfo = (ops i64imm);
758 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
759 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
760 // are encoded as the eight bit value 'abcdefgh'.
761 def simdimmtype10 : Operand<i32>,
762 PatLeaf<(f64 fpimm), [{
763 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
766 }], SDNodeXForm<fpimm, [{
767 APFloat InVal = N->getValueAPF();
768 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
771 return CurDAG->getTargetConstant(enc, MVT::i32);
773 let ParserMatchClass = SIMDImmType10Operand;
774 let PrintMethod = "printSIMDType10Operand";
782 // Base encoding for system instruction operands.
783 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
784 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
785 list<dag> pattern = []>
786 : I<oops, iops, asm, operands, "", pattern> {
787 let Inst{31-22} = 0b1101010100;
791 // System instructions which do not have an Rt register.
792 class SimpleSystemI<bit L, dag iops, string asm, string operands,
793 list<dag> pattern = []>
794 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
795 let Inst{4-0} = 0b11111;
798 // System instructions which have an Rt register.
799 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
800 : BaseSystemI<L, oops, iops, asm, operands>,
806 // Hint instructions that take both a CRm and a 3-bit immediate.
807 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
808 // model patterns with sufficiently fine granularity
809 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
810 class HintI<string mnemonic>
811 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "",
812 [(int_aarch64_hint imm0_127:$imm)]>,
815 let Inst{20-12} = 0b000110010;
816 let Inst{11-5} = imm;
819 // System instructions taking a single literal operand which encodes into
820 // CRm. op2 differentiates the opcodes.
821 def BarrierAsmOperand : AsmOperandClass {
822 let Name = "Barrier";
823 let ParserMethod = "tryParseBarrierOperand";
825 def barrier_op : Operand<i32> {
826 let PrintMethod = "printBarrierOption";
827 let ParserMatchClass = BarrierAsmOperand;
829 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
830 list<dag> pattern = []>
831 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
832 Sched<[WriteBarrier]> {
834 let Inst{20-12} = 0b000110011;
835 let Inst{11-8} = CRm;
839 // MRS/MSR system instructions. These have different operand classes because
840 // a different subset of registers can be accessed through each instruction.
841 def MRSSystemRegisterOperand : AsmOperandClass {
842 let Name = "MRSSystemRegister";
843 let ParserMethod = "tryParseSysReg";
844 let DiagnosticType = "MRS";
846 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
847 def mrs_sysreg_op : Operand<i32> {
848 let ParserMatchClass = MRSSystemRegisterOperand;
849 let DecoderMethod = "DecodeMRSSystemRegister";
850 let PrintMethod = "printMRSSystemRegister";
853 def MSRSystemRegisterOperand : AsmOperandClass {
854 let Name = "MSRSystemRegister";
855 let ParserMethod = "tryParseSysReg";
856 let DiagnosticType = "MSR";
858 def msr_sysreg_op : Operand<i32> {
859 let ParserMatchClass = MSRSystemRegisterOperand;
860 let DecoderMethod = "DecodeMSRSystemRegister";
861 let PrintMethod = "printMSRSystemRegister";
864 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
865 "mrs", "\t$Rt, $systemreg"> {
868 let Inst{19-5} = systemreg;
871 // FIXME: Some of these def NZCV, others don't. Best way to model that?
872 // Explicitly modeling each of the system register as a register class
873 // would do it, but feels like overkill at this point.
874 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
875 "msr", "\t$systemreg, $Rt"> {
878 let Inst{19-5} = systemreg;
881 def SystemPStateFieldOperand : AsmOperandClass {
882 let Name = "SystemPStateField";
883 let ParserMethod = "tryParseSysReg";
885 def pstatefield_op : Operand<i32> {
886 let ParserMatchClass = SystemPStateFieldOperand;
887 let PrintMethod = "printSystemPStateField";
892 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
893 "msr", "\t$pstate_field, $imm">,
897 let Inst{20-19} = 0b00;
898 let Inst{18-16} = pstatefield{5-3};
899 let Inst{15-12} = 0b0100;
900 let Inst{11-8} = imm;
901 let Inst{7-5} = pstatefield{2-0};
903 let DecoderMethod = "DecodeSystemPStateInstruction";
906 // SYS and SYSL generic system instructions.
907 def SysCRAsmOperand : AsmOperandClass {
909 let ParserMethod = "tryParseSysCROperand";
912 def sys_cr_op : Operand<i32> {
913 let PrintMethod = "printSysCROperand";
914 let ParserMatchClass = SysCRAsmOperand;
917 class SystemXtI<bit L, string asm>
918 : RtSystemI<L, (outs),
919 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
920 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
925 let Inst{20-19} = 0b01;
926 let Inst{18-16} = op1;
927 let Inst{15-12} = Cn;
932 class SystemLXtI<bit L, string asm>
933 : RtSystemI<L, (outs),
934 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
935 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
940 let Inst{20-19} = 0b01;
941 let Inst{18-16} = op1;
942 let Inst{15-12} = Cn;
948 // Branch (register) instructions:
956 // otherwise UNDEFINED
957 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
958 string operands, list<dag> pattern>
959 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
960 let Inst{31-25} = 0b1101011;
961 let Inst{24-21} = opc;
962 let Inst{20-16} = 0b11111;
963 let Inst{15-10} = 0b000000;
964 let Inst{4-0} = 0b00000;
967 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
968 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
973 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
974 class SpecialReturn<bits<4> opc, string asm>
975 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
976 let Inst{9-5} = 0b11111;
980 // Conditional branch instruction.
984 // 4-bit immediate. Pretty-printed as <cc>
985 def ccode : Operand<i32> {
986 let PrintMethod = "printCondCode";
987 let ParserMatchClass = CondCode;
989 def inv_ccode : Operand<i32> {
990 // AL and NV are invalid in the aliases which use inv_ccode
991 let PrintMethod = "printInverseCondCode";
992 let ParserMatchClass = CondCode;
993 let MCOperandPredicate = [{
994 return MCOp.isImm() &&
995 MCOp.getImm() != AArch64CC::AL &&
996 MCOp.getImm() != AArch64CC::NV;
1000 // Conditional branch target. 19-bit immediate. The low two bits of the target
1001 // offset are implied zero and so are not part of the immediate.
1002 def PCRelLabel19Operand : AsmOperandClass {
1003 let Name = "PCRelLabel19";
1004 let DiagnosticType = "InvalidLabel";
1006 def am_brcond : Operand<OtherVT> {
1007 let EncoderMethod = "getCondBranchTargetOpValue";
1008 let DecoderMethod = "DecodePCRelLabel19";
1009 let PrintMethod = "printAlignedLabel";
1010 let ParserMatchClass = PCRelLabel19Operand;
1013 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
1014 "b", ".$cond\t$target", "",
1015 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1018 let isTerminator = 1;
1023 let Inst{31-24} = 0b01010100;
1024 let Inst{23-5} = target;
1026 let Inst{3-0} = cond;
1030 // Compare-and-branch instructions.
1032 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1033 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1034 asm, "\t$Rt, $target", "",
1035 [(node regtype:$Rt, bb:$target)]>,
1038 let isTerminator = 1;
1042 let Inst{30-25} = 0b011010;
1044 let Inst{23-5} = target;
1048 multiclass CmpBranch<bit op, string asm, SDNode node> {
1049 def W : BaseCmpBranch<GPR32, op, asm, node> {
1052 def X : BaseCmpBranch<GPR64, op, asm, node> {
1058 // Test-bit-and-branch instructions.
1060 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1061 // the target offset are implied zero and so are not part of the immediate.
1062 def BranchTarget14Operand : AsmOperandClass {
1063 let Name = "BranchTarget14";
1065 def am_tbrcond : Operand<OtherVT> {
1066 let EncoderMethod = "getTestBranchTargetOpValue";
1067 let PrintMethod = "printAlignedLabel";
1068 let ParserMatchClass = BranchTarget14Operand;
1071 // AsmOperand classes to emit (or not) special diagnostics
1072 def TBZImm0_31Operand : AsmOperandClass {
1073 let Name = "TBZImm0_31";
1074 let PredicateMethod = "isImm0_31";
1075 let RenderMethod = "addImm0_31Operands";
1077 def TBZImm32_63Operand : AsmOperandClass {
1078 let Name = "Imm32_63";
1079 let DiagnosticType = "InvalidImm0_63";
1082 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1083 return (((uint32_t)Imm) < 32);
1085 let ParserMatchClass = matcher;
1088 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1089 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1091 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1092 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1094 let ParserMatchClass = TBZImm32_63Operand;
1097 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1098 bit op, string asm, SDNode node>
1099 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1100 asm, "\t$Rt, $bit_off, $target", "",
1101 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1104 let isTerminator = 1;
1110 let Inst{30-25} = 0b011011;
1112 let Inst{23-19} = bit_off{4-0};
1113 let Inst{18-5} = target;
1116 let DecoderMethod = "DecodeTestAndBranch";
1119 multiclass TestBranch<bit op, string asm, SDNode node> {
1120 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1124 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1128 // Alias X-reg with 0-31 imm to W-Reg.
1129 def : InstAlias<asm # "\t$Rd, $imm, $target",
1130 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1131 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1132 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1133 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1134 tbz_imm0_31_diag:$imm, bb:$target)>;
1138 // Unconditional branch (immediate) instructions.
1140 def BranchTarget26Operand : AsmOperandClass {
1141 let Name = "BranchTarget26";
1142 let DiagnosticType = "InvalidLabel";
1144 def am_b_target : Operand<OtherVT> {
1145 let EncoderMethod = "getBranchTargetOpValue";
1146 let PrintMethod = "printAlignedLabel";
1147 let ParserMatchClass = BranchTarget26Operand;
1149 def am_bl_target : Operand<i64> {
1150 let EncoderMethod = "getBranchTargetOpValue";
1151 let PrintMethod = "printAlignedLabel";
1152 let ParserMatchClass = BranchTarget26Operand;
1155 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1156 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1159 let Inst{30-26} = 0b00101;
1160 let Inst{25-0} = addr;
1162 let DecoderMethod = "DecodeUnconditionalBranch";
1165 class BranchImm<bit op, string asm, list<dag> pattern>
1166 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1167 class CallImm<bit op, string asm, list<dag> pattern>
1168 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1171 // Basic one-operand data processing instructions.
1174 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1175 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1176 SDPatternOperator node>
1177 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1178 [(set regtype:$Rd, (node regtype:$Rn))]>,
1179 Sched<[WriteI, ReadI]> {
1183 let Inst{30-13} = 0b101101011000000000;
1184 let Inst{12-10} = opc;
1189 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1190 multiclass OneOperandData<bits<3> opc, string asm,
1191 SDPatternOperator node = null_frag> {
1192 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1196 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1201 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1202 : BaseOneOperandData<opc, GPR32, asm, node> {
1206 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1207 : BaseOneOperandData<opc, GPR64, asm, node> {
1212 // Basic two-operand data processing instructions.
1214 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1216 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1217 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1218 Sched<[WriteI, ReadI, ReadI]> {
1223 let Inst{30} = isSub;
1224 let Inst{28-21} = 0b11010000;
1225 let Inst{20-16} = Rm;
1226 let Inst{15-10} = 0;
1231 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1233 : BaseBaseAddSubCarry<isSub, regtype, asm,
1234 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1236 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1238 : BaseBaseAddSubCarry<isSub, regtype, asm,
1239 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1244 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1245 SDNode OpNode, SDNode OpNode_setflags> {
1246 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1250 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1256 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1261 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1268 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1269 SDPatternOperator OpNode>
1270 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1271 asm, "\t$Rd, $Rn, $Rm", "",
1272 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1276 let Inst{30-21} = 0b0011010110;
1277 let Inst{20-16} = Rm;
1278 let Inst{15-14} = 0b00;
1279 let Inst{13-10} = opc;
1284 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1285 SDPatternOperator OpNode>
1286 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1287 let Inst{10} = isSigned;
1290 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1291 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1292 Sched<[WriteID32, ReadID, ReadID]> {
1295 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1296 Sched<[WriteID64, ReadID, ReadID]> {
1301 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1302 SDPatternOperator OpNode = null_frag>
1303 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1304 Sched<[WriteIS, ReadI]> {
1305 let Inst{11-10} = shift_type;
1308 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1309 def Wr : BaseShift<shift_type, GPR32, asm> {
1313 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1317 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1318 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1319 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1321 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1322 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1324 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1325 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1327 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1328 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1331 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1332 : InstAlias<asm#" $dst, $src1, $src2",
1333 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1335 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1336 RegisterClass addtype, string asm,
1338 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1339 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1344 let Inst{30-24} = 0b0011011;
1345 let Inst{23-21} = opc;
1346 let Inst{20-16} = Rm;
1347 let Inst{15} = isSub;
1348 let Inst{14-10} = Ra;
1353 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1354 // MADD/MSUB generation is decided by MachineCombiner.cpp
1355 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1356 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1357 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1361 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1362 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1363 Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
1368 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1369 SDNode AccNode, SDNode ExtNode>
1370 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1371 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1372 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1373 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1377 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1378 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1379 asm, "\t$Rd, $Rn, $Rm", "",
1380 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1381 Sched<[WriteIM64, ReadIM, ReadIM]> {
1385 let Inst{31-24} = 0b10011011;
1386 let Inst{23-21} = opc;
1387 let Inst{20-16} = Rm;
1392 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1393 // (i.e. all bits 1) but is ignored by the processor.
1394 let PostEncoderMethod = "fixMulHigh";
1397 class MulAccumWAlias<string asm, Instruction inst>
1398 : InstAlias<asm#" $dst, $src1, $src2",
1399 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1400 class MulAccumXAlias<string asm, Instruction inst>
1401 : InstAlias<asm#" $dst, $src1, $src2",
1402 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1403 class WideMulAccumAlias<string asm, Instruction inst>
1404 : InstAlias<asm#" $dst, $src1, $src2",
1405 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1407 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1408 SDPatternOperator OpNode, string asm>
1409 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1410 asm, "\t$Rd, $Rn, $Rm", "",
1411 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1412 Sched<[WriteISReg, ReadI, ReadISReg]> {
1418 let Inst{30-21} = 0b0011010110;
1419 let Inst{20-16} = Rm;
1420 let Inst{15-13} = 0b010;
1422 let Inst{11-10} = sz;
1425 let Predicates = [HasCRC];
1429 // Address generation.
1432 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1433 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1438 let Inst{31} = page;
1439 let Inst{30-29} = label{1-0};
1440 let Inst{28-24} = 0b10000;
1441 let Inst{23-5} = label{20-2};
1444 let DecoderMethod = "DecodeAdrInstruction";
1451 def movimm32_imm : Operand<i32> {
1452 let ParserMatchClass = Imm0_65535Operand;
1453 let EncoderMethod = "getMoveWideImmOpValue";
1454 let PrintMethod = "printHexImm";
1456 def movimm32_shift : Operand<i32> {
1457 let PrintMethod = "printShifter";
1458 let ParserMatchClass = MovImm32ShifterOperand;
1460 def movimm64_shift : Operand<i32> {
1461 let PrintMethod = "printShifter";
1462 let ParserMatchClass = MovImm64ShifterOperand;
1465 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1466 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1468 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1469 asm, "\t$Rd, $imm$shift", "", []>,
1474 let Inst{30-29} = opc;
1475 let Inst{28-23} = 0b100101;
1476 let Inst{22-21} = shift{5-4};
1477 let Inst{20-5} = imm;
1480 let DecoderMethod = "DecodeMoveImmInstruction";
1483 multiclass MoveImmediate<bits<2> opc, string asm> {
1484 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1488 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1493 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1494 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1496 : I<(outs regtype:$Rd),
1497 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1498 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1499 Sched<[WriteI, ReadI]> {
1503 let Inst{30-29} = opc;
1504 let Inst{28-23} = 0b100101;
1505 let Inst{22-21} = shift{5-4};
1506 let Inst{20-5} = imm;
1509 let DecoderMethod = "DecodeMoveImmInstruction";
1512 multiclass InsertImmediate<bits<2> opc, string asm> {
1513 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1517 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1526 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1527 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1528 string asm, SDPatternOperator OpNode>
1529 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1530 asm, "\t$Rd, $Rn, $imm", "",
1531 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1532 Sched<[WriteI, ReadI]> {
1536 let Inst{30} = isSub;
1537 let Inst{29} = setFlags;
1538 let Inst{28-24} = 0b10001;
1539 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1540 let Inst{21-10} = imm{11-0};
1543 let DecoderMethod = "DecodeBaseAddSubImm";
1546 class BaseAddSubRegPseudo<RegisterClass regtype,
1547 SDPatternOperator OpNode>
1548 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1549 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1550 Sched<[WriteI, ReadI, ReadI]>;
1552 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1553 arith_shifted_reg shifted_regtype, string asm,
1554 SDPatternOperator OpNode>
1555 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1556 asm, "\t$Rd, $Rn, $Rm", "",
1557 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1558 Sched<[WriteISReg, ReadI, ReadISReg]> {
1559 // The operands are in order to match the 'addr' MI operands, so we
1560 // don't need an encoder method and by-name matching. Just use the default
1561 // in-order handling. Since we're using by-order, make sure the names
1567 let Inst{30} = isSub;
1568 let Inst{29} = setFlags;
1569 let Inst{28-24} = 0b01011;
1570 let Inst{23-22} = shift{7-6};
1572 let Inst{20-16} = src2;
1573 let Inst{15-10} = shift{5-0};
1574 let Inst{9-5} = src1;
1575 let Inst{4-0} = dst;
1577 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1580 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1581 RegisterClass src1Regtype, Operand src2Regtype,
1582 string asm, SDPatternOperator OpNode>
1583 : I<(outs dstRegtype:$R1),
1584 (ins src1Regtype:$R2, src2Regtype:$R3),
1585 asm, "\t$R1, $R2, $R3", "",
1586 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1587 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1592 let Inst{30} = isSub;
1593 let Inst{29} = setFlags;
1594 let Inst{28-24} = 0b01011;
1595 let Inst{23-21} = 0b001;
1596 let Inst{20-16} = Rm;
1597 let Inst{15-13} = ext{5-3};
1598 let Inst{12-10} = ext{2-0};
1602 let DecoderMethod = "DecodeAddSubERegInstruction";
1605 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1606 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1607 RegisterClass src1Regtype, RegisterClass src2Regtype,
1608 Operand ext_op, string asm>
1609 : I<(outs dstRegtype:$Rd),
1610 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1611 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1612 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1617 let Inst{30} = isSub;
1618 let Inst{29} = setFlags;
1619 let Inst{28-24} = 0b01011;
1620 let Inst{23-21} = 0b001;
1621 let Inst{20-16} = Rm;
1622 let Inst{15} = ext{5};
1623 let Inst{12-10} = ext{2-0};
1627 let DecoderMethod = "DecodeAddSubERegInstruction";
1630 // Aliases for register+register add/subtract.
1631 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1632 RegisterClass src1Regtype, RegisterClass src2Regtype,
1634 : InstAlias<asm#" $dst, $src1, $src2",
1635 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1638 multiclass AddSub<bit isSub, string mnemonic,
1639 SDPatternOperator OpNode = null_frag> {
1640 let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1641 // Add/Subtract immediate
1642 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1646 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1651 // Add/Subtract register - Only used for CodeGen
1652 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1653 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1655 // Add/Subtract shifted register
1656 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1660 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1666 // Add/Subtract extended register
1667 let AddedComplexity = 1, hasSideEffects = 0 in {
1668 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1669 arith_extended_reg32<i32>, mnemonic, OpNode> {
1672 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1673 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1678 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1679 arith_extendlsl64, mnemonic> {
1680 // UXTX and SXTX only.
1681 let Inst{14-13} = 0b11;
1685 // Register/register aliases with no shift when SP is not used.
1686 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1687 GPR32, GPR32, GPR32, 0>;
1688 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1689 GPR64, GPR64, GPR64, 0>;
1691 // Register/register aliases with no shift when either the destination or
1692 // first source register is SP.
1693 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1694 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1695 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1696 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1697 def : AddSubRegAlias<mnemonic,
1698 !cast<Instruction>(NAME#"Xrx64"),
1699 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1700 def : AddSubRegAlias<mnemonic,
1701 !cast<Instruction>(NAME#"Xrx64"),
1702 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1705 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
1706 let isCompare = 1, Defs = [NZCV] in {
1707 // Add/Subtract immediate
1708 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1712 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1717 // Add/Subtract register
1718 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1719 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1721 // Add/Subtract shifted register
1722 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1726 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1731 // Add/Subtract extended register
1732 let AddedComplexity = 1 in {
1733 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1734 arith_extended_reg32<i32>, mnemonic, OpNode> {
1737 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1738 arith_extended_reg32<i64>, mnemonic, OpNode> {
1743 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1744 arith_extendlsl64, mnemonic> {
1745 // UXTX and SXTX only.
1746 let Inst{14-13} = 0b11;
1752 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Wri")
1753 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1754 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Xri")
1755 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1756 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1757 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1758 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1759 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1760 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1761 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1762 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1763 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1764 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1765 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1767 // Compare shorthands
1768 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1769 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1770 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1771 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1772 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrx")
1773 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1774 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
1775 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1777 // Register/register aliases with no shift when SP is not used.
1778 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1779 GPR32, GPR32, GPR32, 0>;
1780 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1781 GPR64, GPR64, GPR64, 0>;
1783 // Register/register aliases with no shift when the first source register
1785 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1786 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1787 def : AddSubRegAlias<mnemonic,
1788 !cast<Instruction>(NAME#"Xrx64"),
1789 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1795 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1797 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1799 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1801 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1802 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1803 Sched<[WriteExtr, ReadExtrHi]> {
1809 let Inst{30-23} = 0b00100111;
1811 let Inst{20-16} = Rm;
1812 let Inst{15-10} = imm;
1817 multiclass ExtractImm<string asm> {
1818 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1820 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1823 // imm<5> must be zero.
1826 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1828 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1839 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1840 class BaseBitfieldImm<bits<2> opc,
1841 RegisterClass regtype, Operand imm_type, string asm>
1842 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1843 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1844 Sched<[WriteIS, ReadI]> {
1850 let Inst{30-29} = opc;
1851 let Inst{28-23} = 0b100110;
1852 let Inst{21-16} = immr;
1853 let Inst{15-10} = imms;
1858 multiclass BitfieldImm<bits<2> opc, string asm> {
1859 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1862 // imms<5> and immr<5> must be zero, else ReservedValue().
1866 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1872 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1873 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1874 RegisterClass regtype, Operand imm_type, string asm>
1875 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1877 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1878 Sched<[WriteIS, ReadI]> {
1884 let Inst{30-29} = opc;
1885 let Inst{28-23} = 0b100110;
1886 let Inst{21-16} = immr;
1887 let Inst{15-10} = imms;
1892 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1893 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1896 // imms<5> and immr<5> must be zero, else ReservedValue().
1900 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1910 // Logical (immediate)
1911 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1912 RegisterClass sregtype, Operand imm_type, string asm,
1914 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1915 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1916 Sched<[WriteI, ReadI]> {
1920 let Inst{30-29} = opc;
1921 let Inst{28-23} = 0b100100;
1922 let Inst{22} = imm{12};
1923 let Inst{21-16} = imm{11-6};
1924 let Inst{15-10} = imm{5-0};
1928 let DecoderMethod = "DecodeLogicalImmInstruction";
1931 // Logical (shifted register)
1932 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1933 logical_shifted_reg shifted_regtype, string asm,
1935 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1936 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1937 Sched<[WriteISReg, ReadI, ReadISReg]> {
1938 // The operands are in order to match the 'addr' MI operands, so we
1939 // don't need an encoder method and by-name matching. Just use the default
1940 // in-order handling. Since we're using by-order, make sure the names
1946 let Inst{30-29} = opc;
1947 let Inst{28-24} = 0b01010;
1948 let Inst{23-22} = shift{7-6};
1950 let Inst{20-16} = src2;
1951 let Inst{15-10} = shift{5-0};
1952 let Inst{9-5} = src1;
1953 let Inst{4-0} = dst;
1955 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1958 // Aliases for register+register logical instructions.
1959 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1960 : InstAlias<asm#" $dst, $src1, $src2",
1961 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1963 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
1965 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1966 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1967 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1968 logical_imm32:$imm))]> {
1970 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1972 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1973 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1974 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1975 logical_imm64:$imm))]> {
1979 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1980 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
1981 logical_imm32_not:$imm), 0>;
1982 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1983 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
1984 logical_imm64_not:$imm), 0>;
1987 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
1989 let isCompare = 1, Defs = [NZCV] in {
1990 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1991 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1993 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1995 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
1996 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
1999 } // end Defs = [NZCV]
2001 def : InstAlias<Alias # " $Rd, $Rn, $imm",
2002 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2003 logical_imm32_not:$imm), 0>;
2004 def : InstAlias<Alias # " $Rd, $Rn, $imm",
2005 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2006 logical_imm64_not:$imm), 0>;
2009 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
2010 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2011 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2012 Sched<[WriteI, ReadI, ReadI]>;
2014 // Split from LogicalImm as not all instructions have both.
2015 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
2016 SDPatternOperator OpNode> {
2017 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2018 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2019 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2022 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2023 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2024 logical_shifted_reg32:$Rm))]> {
2027 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2028 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2029 logical_shifted_reg64:$Rm))]> {
2033 def : LogicalRegAlias<mnemonic,
2034 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2035 def : LogicalRegAlias<mnemonic,
2036 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2039 // Split from LogicalReg to allow setting NZCV Defs
2040 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
2041 SDPatternOperator OpNode = null_frag> {
2042 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
2043 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2044 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2046 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2047 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2050 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2051 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2056 def : LogicalRegAlias<mnemonic,
2057 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2058 def : LogicalRegAlias<mnemonic,
2059 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2063 // Conditionally set flags
2066 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2067 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
2068 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
2069 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
2070 Sched<[WriteI, ReadI]> {
2080 let Inst{29-21} = 0b111010010;
2081 let Inst{20-16} = imm;
2082 let Inst{15-12} = cond;
2083 let Inst{11-10} = 0b10;
2086 let Inst{3-0} = nzcv;
2089 multiclass CondSetFlagsImm<bit op, string asm> {
2090 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
2093 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
2098 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2099 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
2100 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
2101 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
2102 Sched<[WriteI, ReadI, ReadI]> {
2112 let Inst{29-21} = 0b111010010;
2113 let Inst{20-16} = Rm;
2114 let Inst{15-12} = cond;
2115 let Inst{11-10} = 0b00;
2118 let Inst{3-0} = nzcv;
2121 multiclass CondSetFlagsReg<bit op, string asm> {
2122 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
2125 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
2131 // Conditional select
2134 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2135 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2136 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2138 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2139 Sched<[WriteI, ReadI, ReadI]> {
2148 let Inst{29-21} = 0b011010100;
2149 let Inst{20-16} = Rm;
2150 let Inst{15-12} = cond;
2151 let Inst{11-10} = op2;
2156 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2157 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2160 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2165 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2167 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2168 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2170 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2171 (i32 imm:$cond), NZCV))]>,
2172 Sched<[WriteI, ReadI, ReadI]> {
2181 let Inst{29-21} = 0b011010100;
2182 let Inst{20-16} = Rm;
2183 let Inst{15-12} = cond;
2184 let Inst{11-10} = op2;
2189 def inv_cond_XFORM : SDNodeXForm<imm, [{
2190 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2191 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), MVT::i32);
2194 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2195 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2198 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2202 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2203 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2204 (inv_cond_XFORM imm:$cond))>;
2206 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2207 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2208 (inv_cond_XFORM imm:$cond))>;
2212 // Special Mask Value
2214 def maski8_or_more : Operand<i32>,
2215 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2217 def maski16_or_more : Operand<i32>,
2218 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2226 // (unsigned immediate)
2227 // Indexed for 8-bit registers. offset is in range [0,4095].
2228 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2229 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2230 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2231 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2232 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2234 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2235 let Name = "UImm12Offset" # Scale;
2236 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2237 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2238 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2241 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2242 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2243 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2244 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2245 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2247 class uimm12_scaled<int Scale> : Operand<i64> {
2248 let ParserMatchClass
2249 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2251 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2252 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2255 def uimm12s1 : uimm12_scaled<1>;
2256 def uimm12s2 : uimm12_scaled<2>;
2257 def uimm12s4 : uimm12_scaled<4>;
2258 def uimm12s8 : uimm12_scaled<8>;
2259 def uimm12s16 : uimm12_scaled<16>;
2261 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2262 string asm, list<dag> pattern>
2263 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2269 let Inst{31-30} = sz;
2270 let Inst{29-27} = 0b111;
2272 let Inst{25-24} = 0b01;
2273 let Inst{23-22} = opc;
2274 let Inst{21-10} = offset;
2278 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2281 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2282 Operand indextype, string asm, list<dag> pattern> {
2283 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2284 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2285 (ins GPR64sp:$Rn, indextype:$offset),
2289 def : InstAlias<asm # " $Rt, [$Rn]",
2290 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2293 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2294 Operand indextype, string asm, list<dag> pattern> {
2295 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2296 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2297 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2301 def : InstAlias<asm # " $Rt, [$Rn]",
2302 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2305 def PrefetchOperand : AsmOperandClass {
2306 let Name = "Prefetch";
2307 let ParserMethod = "tryParsePrefetch";
2309 def prfop : Operand<i32> {
2310 let PrintMethod = "printPrefetchOp";
2311 let ParserMatchClass = PrefetchOperand;
2314 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2315 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2316 : BaseLoadStoreUI<sz, V, opc,
2317 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2325 // Load literal address: 19-bit immediate. The low two bits of the target
2326 // offset are implied zero and so are not part of the immediate.
2327 def am_ldrlit : Operand<OtherVT> {
2328 let EncoderMethod = "getLoadLiteralOpValue";
2329 let DecoderMethod = "DecodePCRelLabel19";
2330 let PrintMethod = "printAlignedLabel";
2331 let ParserMatchClass = PCRelLabel19Operand;
2334 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2335 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2336 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2337 asm, "\t$Rt, $label", "", []>,
2341 let Inst{31-30} = opc;
2342 let Inst{29-27} = 0b011;
2344 let Inst{25-24} = 0b00;
2345 let Inst{23-5} = label;
2349 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2350 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2351 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2352 asm, "\t$Rt, $label", "", pat>,
2356 let Inst{31-30} = opc;
2357 let Inst{29-27} = 0b011;
2359 let Inst{25-24} = 0b00;
2360 let Inst{23-5} = label;
2365 // Load/store register offset
2368 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2369 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2370 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2371 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2372 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2374 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2375 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2376 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2377 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2378 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2380 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2381 let Name = "Mem" # Reg # "Extend" # Width;
2382 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2383 let RenderMethod = "addMemExtendOperands";
2384 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2387 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2388 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2389 // the trivial shift.
2390 let RenderMethod = "addMemExtend8Operands";
2392 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2393 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2394 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2395 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2397 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2398 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2399 // the trivial shift.
2400 let RenderMethod = "addMemExtend8Operands";
2402 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2403 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2404 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2405 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2407 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2409 let ParserMatchClass = ParserClass;
2410 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2411 let DecoderMethod = "DecodeMemExtend";
2412 let EncoderMethod = "getMemExtendOpValue";
2413 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2416 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2417 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2418 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2419 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2420 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2422 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2423 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2424 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2425 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2426 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2428 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2429 Operand wextend, Operand xextend> {
2430 // CodeGen-level pattern covering the entire addressing mode.
2431 ComplexPattern Wpat = windex;
2432 ComplexPattern Xpat = xindex;
2434 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2435 Operand Wext = wextend;
2436 Operand Xext = xextend;
2439 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2440 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2441 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2442 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2443 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2446 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2447 string asm, dag ins, dag outs, list<dag> pat>
2448 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2453 let Inst{31-30} = sz;
2454 let Inst{29-27} = 0b111;
2456 let Inst{25-24} = 0b00;
2457 let Inst{23-22} = opc;
2459 let Inst{20-16} = Rm;
2460 let Inst{15} = extend{1}; // sign extend Rm?
2462 let Inst{12} = extend{0}; // do shift?
2463 let Inst{11-10} = 0b10;
2468 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2469 : InstAlias<asm # " $Rt, [$Rn, $Rm]",
2470 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2472 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2473 string asm, ValueType Ty, SDPatternOperator loadop> {
2474 let AddedComplexity = 10 in
2475 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2477 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2478 [(set (Ty regtype:$Rt),
2479 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2480 ro_Wextend8:$extend)))]>,
2481 Sched<[WriteLDIdx, ReadAdrBase]> {
2485 let AddedComplexity = 10 in
2486 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2488 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2489 [(set (Ty regtype:$Rt),
2490 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2491 ro_Xextend8:$extend)))]>,
2492 Sched<[WriteLDIdx, ReadAdrBase]> {
2496 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2499 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2500 string asm, ValueType Ty, SDPatternOperator storeop> {
2501 let AddedComplexity = 10 in
2502 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2503 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2504 [(storeop (Ty regtype:$Rt),
2505 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2506 ro_Wextend8:$extend))]>,
2507 Sched<[WriteSTIdx, ReadAdrBase]> {
2511 let AddedComplexity = 10 in
2512 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2513 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2514 [(storeop (Ty regtype:$Rt),
2515 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2516 ro_Xextend8:$extend))]>,
2517 Sched<[WriteSTIdx, ReadAdrBase]> {
2521 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2524 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2525 string asm, dag ins, dag outs, list<dag> pat>
2526 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2531 let Inst{31-30} = sz;
2532 let Inst{29-27} = 0b111;
2534 let Inst{25-24} = 0b00;
2535 let Inst{23-22} = opc;
2537 let Inst{20-16} = Rm;
2538 let Inst{15} = extend{1}; // sign extend Rm?
2540 let Inst{12} = extend{0}; // do shift?
2541 let Inst{11-10} = 0b10;
2546 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2547 string asm, ValueType Ty, SDPatternOperator loadop> {
2548 let AddedComplexity = 10 in
2549 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2550 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2551 [(set (Ty regtype:$Rt),
2552 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2553 ro_Wextend16:$extend)))]>,
2554 Sched<[WriteLDIdx, ReadAdrBase]> {
2558 let AddedComplexity = 10 in
2559 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2560 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2561 [(set (Ty regtype:$Rt),
2562 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2563 ro_Xextend16:$extend)))]>,
2564 Sched<[WriteLDIdx, ReadAdrBase]> {
2568 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2571 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2572 string asm, ValueType Ty, SDPatternOperator storeop> {
2573 let AddedComplexity = 10 in
2574 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2575 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2576 [(storeop (Ty regtype:$Rt),
2577 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2578 ro_Wextend16:$extend))]>,
2579 Sched<[WriteSTIdx, ReadAdrBase]> {
2583 let AddedComplexity = 10 in
2584 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2585 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2586 [(storeop (Ty regtype:$Rt),
2587 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2588 ro_Xextend16:$extend))]>,
2589 Sched<[WriteSTIdx, ReadAdrBase]> {
2593 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2596 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2597 string asm, dag ins, dag outs, list<dag> pat>
2598 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2603 let Inst{31-30} = sz;
2604 let Inst{29-27} = 0b111;
2606 let Inst{25-24} = 0b00;
2607 let Inst{23-22} = opc;
2609 let Inst{20-16} = Rm;
2610 let Inst{15} = extend{1}; // sign extend Rm?
2612 let Inst{12} = extend{0}; // do shift?
2613 let Inst{11-10} = 0b10;
2618 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2619 string asm, ValueType Ty, SDPatternOperator loadop> {
2620 let AddedComplexity = 10 in
2621 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2622 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2623 [(set (Ty regtype:$Rt),
2624 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2625 ro_Wextend32:$extend)))]>,
2626 Sched<[WriteLDIdx, ReadAdrBase]> {
2630 let AddedComplexity = 10 in
2631 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2632 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2633 [(set (Ty regtype:$Rt),
2634 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2635 ro_Xextend32:$extend)))]>,
2636 Sched<[WriteLDIdx, ReadAdrBase]> {
2640 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2643 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2644 string asm, ValueType Ty, SDPatternOperator storeop> {
2645 let AddedComplexity = 10 in
2646 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2647 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2648 [(storeop (Ty regtype:$Rt),
2649 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2650 ro_Wextend32:$extend))]>,
2651 Sched<[WriteSTIdx, ReadAdrBase]> {
2655 let AddedComplexity = 10 in
2656 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2657 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2658 [(storeop (Ty regtype:$Rt),
2659 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2660 ro_Xextend32:$extend))]>,
2661 Sched<[WriteSTIdx, ReadAdrBase]> {
2665 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2668 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2669 string asm, dag ins, dag outs, list<dag> pat>
2670 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2675 let Inst{31-30} = sz;
2676 let Inst{29-27} = 0b111;
2678 let Inst{25-24} = 0b00;
2679 let Inst{23-22} = opc;
2681 let Inst{20-16} = Rm;
2682 let Inst{15} = extend{1}; // sign extend Rm?
2684 let Inst{12} = extend{0}; // do shift?
2685 let Inst{11-10} = 0b10;
2690 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2691 string asm, ValueType Ty, SDPatternOperator loadop> {
2692 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2693 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2694 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2695 [(set (Ty regtype:$Rt),
2696 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2697 ro_Wextend64:$extend)))]>,
2698 Sched<[WriteLDIdx, ReadAdrBase]> {
2702 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2703 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2704 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2705 [(set (Ty regtype:$Rt),
2706 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2707 ro_Xextend64:$extend)))]>,
2708 Sched<[WriteLDIdx, ReadAdrBase]> {
2712 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2715 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2716 string asm, ValueType Ty, SDPatternOperator storeop> {
2717 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2718 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2719 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2720 [(storeop (Ty regtype:$Rt),
2721 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2722 ro_Wextend64:$extend))]>,
2723 Sched<[WriteSTIdx, ReadAdrBase]> {
2727 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2728 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2729 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2730 [(storeop (Ty regtype:$Rt),
2731 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2732 ro_Xextend64:$extend))]>,
2733 Sched<[WriteSTIdx, ReadAdrBase]> {
2737 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2740 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2741 string asm, dag ins, dag outs, list<dag> pat>
2742 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2747 let Inst{31-30} = sz;
2748 let Inst{29-27} = 0b111;
2750 let Inst{25-24} = 0b00;
2751 let Inst{23-22} = opc;
2753 let Inst{20-16} = Rm;
2754 let Inst{15} = extend{1}; // sign extend Rm?
2756 let Inst{12} = extend{0}; // do shift?
2757 let Inst{11-10} = 0b10;
2762 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2763 string asm, ValueType Ty, SDPatternOperator loadop> {
2764 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2765 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2766 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2767 [(set (Ty regtype:$Rt),
2768 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2769 ro_Wextend128:$extend)))]>,
2770 Sched<[WriteLDIdx, ReadAdrBase]> {
2774 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2775 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2776 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2777 [(set (Ty regtype:$Rt),
2778 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2779 ro_Xextend128:$extend)))]>,
2780 Sched<[WriteLDIdx, ReadAdrBase]> {
2784 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2787 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2788 string asm, ValueType Ty, SDPatternOperator storeop> {
2789 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2790 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2791 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2792 [(storeop (Ty regtype:$Rt),
2793 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2794 ro_Wextend128:$extend))]>,
2795 Sched<[WriteSTIdx, ReadAdrBase]> {
2799 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2800 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2801 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2802 [(storeop (Ty regtype:$Rt),
2803 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2804 ro_Xextend128:$extend))]>,
2805 Sched<[WriteSTIdx, ReadAdrBase]> {
2809 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2812 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2813 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2814 string asm, list<dag> pat>
2815 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2821 let Inst{31-30} = sz;
2822 let Inst{29-27} = 0b111;
2824 let Inst{25-24} = 0b00;
2825 let Inst{23-22} = opc;
2827 let Inst{20-16} = Rm;
2828 let Inst{15} = extend{1}; // sign extend Rm?
2830 let Inst{12} = extend{0}; // do shift?
2831 let Inst{11-10} = 0b10;
2836 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2837 def roW : BasePrefetchRO<sz, V, opc, (outs),
2838 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2839 asm, [(AArch64Prefetch imm:$Rt,
2840 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2841 ro_Wextend64:$extend))]> {
2845 def roX : BasePrefetchRO<sz, V, opc, (outs),
2846 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2847 asm, [(AArch64Prefetch imm:$Rt,
2848 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2849 ro_Xextend64:$extend))]> {
2853 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2854 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2855 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2859 // Load/store unscaled immediate
2862 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2863 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2864 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2865 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2866 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2868 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2869 string asm, list<dag> pattern>
2870 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2874 let Inst{31-30} = sz;
2875 let Inst{29-27} = 0b111;
2877 let Inst{25-24} = 0b00;
2878 let Inst{23-22} = opc;
2880 let Inst{20-12} = offset;
2881 let Inst{11-10} = 0b00;
2885 let DecoderMethod = "DecodeSignedLdStInstruction";
2888 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2889 string asm, list<dag> pattern> {
2890 let AddedComplexity = 1 in // try this before LoadUI
2891 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2892 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2895 def : InstAlias<asm # " $Rt, [$Rn]",
2896 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2899 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2900 string asm, list<dag> pattern> {
2901 let AddedComplexity = 1 in // try this before StoreUI
2902 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2903 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2907 def : InstAlias<asm # " $Rt, [$Rn]",
2908 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2911 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
2913 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2914 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2915 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2919 def : InstAlias<asm # " $Rt, [$Rn]",
2920 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2924 // Load/store unscaled immediate, unprivileged
2927 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2928 dag oops, dag iops, string asm>
2929 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2933 let Inst{31-30} = sz;
2934 let Inst{29-27} = 0b111;
2936 let Inst{25-24} = 0b00;
2937 let Inst{23-22} = opc;
2939 let Inst{20-12} = offset;
2940 let Inst{11-10} = 0b10;
2944 let DecoderMethod = "DecodeSignedLdStInstruction";
2947 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
2948 RegisterClass regtype, string asm> {
2949 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
2950 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
2951 (ins GPR64sp:$Rn, simm9:$offset), asm>,
2954 def : InstAlias<asm # " $Rt, [$Rn]",
2955 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2958 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2959 RegisterClass regtype, string asm> {
2960 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2961 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
2962 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2966 def : InstAlias<asm # " $Rt, [$Rn]",
2967 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2971 // Load/store pre-indexed
2974 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2975 string asm, string cstr, list<dag> pat>
2976 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
2980 let Inst{31-30} = sz;
2981 let Inst{29-27} = 0b111;
2983 let Inst{25-24} = 0;
2984 let Inst{23-22} = opc;
2986 let Inst{20-12} = offset;
2987 let Inst{11-10} = 0b11;
2991 let DecoderMethod = "DecodeSignedLdStInstruction";
2994 let hasSideEffects = 0 in {
2995 let mayStore = 0, mayLoad = 1 in
2996 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2998 : BaseLoadStorePreIdx<sz, V, opc,
2999 (outs GPR64sp:$wback, regtype:$Rt),
3000 (ins GPR64sp:$Rn, simm9:$offset), asm,
3001 "$Rn = $wback,@earlyclobber $wback", []>,
3002 Sched<[WriteLD, WriteAdr]>;
3004 let mayStore = 1, mayLoad = 0 in
3005 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3006 string asm, SDPatternOperator storeop, ValueType Ty>
3007 : BaseLoadStorePreIdx<sz, V, opc,
3008 (outs GPR64sp:$wback),
3009 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3010 asm, "$Rn = $wback,@earlyclobber $wback",
3011 [(set GPR64sp:$wback,
3012 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3013 Sched<[WriteAdr, WriteST]>;
3014 } // hasSideEffects = 0
3017 // Load/store post-indexed
3020 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3021 string asm, string cstr, list<dag> pat>
3022 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
3026 let Inst{31-30} = sz;
3027 let Inst{29-27} = 0b111;
3029 let Inst{25-24} = 0b00;
3030 let Inst{23-22} = opc;
3032 let Inst{20-12} = offset;
3033 let Inst{11-10} = 0b01;
3037 let DecoderMethod = "DecodeSignedLdStInstruction";
3040 let hasSideEffects = 0 in {
3041 let mayStore = 0, mayLoad = 1 in
3042 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3044 : BaseLoadStorePostIdx<sz, V, opc,
3045 (outs GPR64sp:$wback, regtype:$Rt),
3046 (ins GPR64sp:$Rn, simm9:$offset),
3047 asm, "$Rn = $wback,@earlyclobber $wback", []>,
3048 Sched<[WriteLD, WriteI]>;
3050 let mayStore = 1, mayLoad = 0 in
3051 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3052 string asm, SDPatternOperator storeop, ValueType Ty>
3053 : BaseLoadStorePostIdx<sz, V, opc,
3054 (outs GPR64sp:$wback),
3055 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3056 asm, "$Rn = $wback,@earlyclobber $wback",
3057 [(set GPR64sp:$wback,
3058 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3059 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3060 } // hasSideEffects = 0
3067 // (indexed, offset)
3069 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3071 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3076 let Inst{31-30} = opc;
3077 let Inst{29-27} = 0b101;
3079 let Inst{25-23} = 0b010;
3081 let Inst{21-15} = offset;
3082 let Inst{14-10} = Rt2;
3086 let DecoderMethod = "DecodePairLdStInstruction";
3089 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3090 Operand indextype, string asm> {
3091 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3092 def i : BaseLoadStorePairOffset<opc, V, 1,
3093 (outs regtype:$Rt, regtype:$Rt2),
3094 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3095 Sched<[WriteLD, WriteLDHi]>;
3097 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3098 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3103 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3104 Operand indextype, string asm> {
3105 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3106 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3107 (ins regtype:$Rt, regtype:$Rt2,
3108 GPR64sp:$Rn, indextype:$offset),
3112 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3113 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3118 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3120 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
3125 let Inst{31-30} = opc;
3126 let Inst{29-27} = 0b101;
3128 let Inst{25-23} = 0b011;
3130 let Inst{21-15} = offset;
3131 let Inst{14-10} = Rt2;
3135 let DecoderMethod = "DecodePairLdStInstruction";
3138 let hasSideEffects = 0 in {
3139 let mayStore = 0, mayLoad = 1 in
3140 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3141 Operand indextype, string asm>
3142 : BaseLoadStorePairPreIdx<opc, V, 1,
3143 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3144 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3145 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3147 let mayStore = 1, mayLoad = 0 in
3148 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3149 Operand indextype, string asm>
3150 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3151 (ins regtype:$Rt, regtype:$Rt2,
3152 GPR64sp:$Rn, indextype:$offset),
3154 Sched<[WriteAdr, WriteSTP]>;
3155 } // hasSideEffects = 0
3159 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3161 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
3166 let Inst{31-30} = opc;
3167 let Inst{29-27} = 0b101;
3169 let Inst{25-23} = 0b001;
3171 let Inst{21-15} = offset;
3172 let Inst{14-10} = Rt2;
3176 let DecoderMethod = "DecodePairLdStInstruction";
3179 let hasSideEffects = 0 in {
3180 let mayStore = 0, mayLoad = 1 in
3181 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3182 Operand idxtype, string asm>
3183 : BaseLoadStorePairPostIdx<opc, V, 1,
3184 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3185 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3186 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3188 let mayStore = 1, mayLoad = 0 in
3189 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3190 Operand idxtype, string asm>
3191 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
3192 (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
3193 GPR64sp:$Rn, idxtype:$offset),
3195 Sched<[WriteAdr, WriteSTP]>;
3196 } // hasSideEffects = 0
3200 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3202 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3207 let Inst{31-30} = opc;
3208 let Inst{29-27} = 0b101;
3210 let Inst{25-23} = 0b000;
3212 let Inst{21-15} = offset;
3213 let Inst{14-10} = Rt2;
3217 let DecoderMethod = "DecodePairLdStInstruction";
3220 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3221 Operand indextype, string asm> {
3222 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3223 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3224 (outs regtype:$Rt, regtype:$Rt2),
3225 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3226 Sched<[WriteLD, WriteLDHi]>;
3229 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3230 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3234 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3235 Operand indextype, string asm> {
3236 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3237 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3238 (ins regtype:$Rt, regtype:$Rt2,
3239 GPR64sp:$Rn, indextype:$offset),
3243 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3244 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3249 // Load/store exclusive
3252 // True exclusive operations write to and/or read from the system's exclusive
3253 // monitors, which as far as a compiler is concerned can be modelled as a
3254 // random shared memory address. Hence LoadExclusive mayStore.
3256 // Since these instructions have the undefined register bits set to 1 in
3257 // their canonical form, we need a post encoder method to set those bits
3258 // to 1 when encoding these instructions. We do this using the
3259 // fixLoadStoreExclusive function. This function has template parameters:
3261 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3263 // hasRs indicates that the instruction uses the Rs field, so we won't set
3264 // it to 1 (and the same for Rt2). We don't need template parameters for
3265 // the other register fields since Rt and Rn are always used.
3267 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3268 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3269 dag oops, dag iops, string asm, string operands>
3270 : I<oops, iops, asm, operands, "", []> {
3271 let Inst{31-30} = sz;
3272 let Inst{29-24} = 0b001000;
3278 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3281 // Neither Rs nor Rt2 operands.
3282 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3283 dag oops, dag iops, string asm, string operands>
3284 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3290 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3293 // Simple load acquires don't set the exclusive monitor
3294 let mayLoad = 1, mayStore = 0 in
3295 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3296 RegisterClass regtype, string asm>
3297 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3298 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3301 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3302 RegisterClass regtype, string asm>
3303 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3304 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3307 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3308 RegisterClass regtype, string asm>
3309 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3310 (outs regtype:$Rt, regtype:$Rt2),
3311 (ins GPR64sp0:$Rn), asm,
3312 "\t$Rt, $Rt2, [$Rn]">,
3313 Sched<[WriteLD, WriteLDHi]> {
3317 let Inst{14-10} = Rt2;
3321 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3324 // Simple store release operations do not check the exclusive monitor.
3325 let mayLoad = 0, mayStore = 1 in
3326 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3327 RegisterClass regtype, string asm>
3328 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3329 (ins regtype:$Rt, GPR64sp0:$Rn),
3330 asm, "\t$Rt, [$Rn]">,
3333 let mayLoad = 1, mayStore = 1 in
3334 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3335 RegisterClass regtype, string asm>
3336 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3337 (ins regtype:$Rt, GPR64sp0:$Rn),
3338 asm, "\t$Ws, $Rt, [$Rn]">,
3343 let Inst{20-16} = Ws;
3347 let Constraints = "@earlyclobber $Ws";
3348 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3351 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3352 RegisterClass regtype, string asm>
3353 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3355 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3356 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3362 let Inst{20-16} = Ws;
3363 let Inst{14-10} = Rt2;
3367 let Constraints = "@earlyclobber $Ws";
3371 // Exception generation
3374 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3375 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3376 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3379 let Inst{31-24} = 0b11010100;
3380 let Inst{23-21} = op1;
3381 let Inst{20-5} = imm;
3382 let Inst{4-2} = 0b000;
3386 let Predicates = [HasFPARMv8] in {
3389 // Floating point to integer conversion
3392 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3393 RegisterClass srcType, RegisterClass dstType,
3394 string asm, list<dag> pattern>
3395 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3396 asm, "\t$Rd, $Rn", "", pattern>,
3397 Sched<[WriteFCvt]> {
3400 let Inst{30-29} = 0b00;
3401 let Inst{28-24} = 0b11110;
3402 let Inst{23-22} = type;
3404 let Inst{20-19} = rmode;
3405 let Inst{18-16} = opcode;
3406 let Inst{15-10} = 0;
3411 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3412 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3413 RegisterClass srcType, RegisterClass dstType,
3414 Operand immType, string asm, list<dag> pattern>
3415 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3416 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3417 Sched<[WriteFCvt]> {
3421 let Inst{30-29} = 0b00;
3422 let Inst{28-24} = 0b11110;
3423 let Inst{23-22} = type;
3425 let Inst{20-19} = rmode;
3426 let Inst{18-16} = opcode;
3427 let Inst{15-10} = scale;
3432 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3433 SDPatternOperator OpN> {
3434 // Unscaled single-precision to 32-bit
3435 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3436 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3437 let Inst{31} = 0; // 32-bit GPR flag
3440 // Unscaled single-precision to 64-bit
3441 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3442 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3443 let Inst{31} = 1; // 64-bit GPR flag
3446 // Unscaled double-precision to 32-bit
3447 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3448 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3449 let Inst{31} = 0; // 32-bit GPR flag
3452 // Unscaled double-precision to 64-bit
3453 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3454 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3455 let Inst{31} = 1; // 64-bit GPR flag
3459 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3460 SDPatternOperator OpN> {
3461 // Scaled single-precision to 32-bit
3462 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3463 fixedpoint_f32_i32, asm,
3464 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3465 fixedpoint_f32_i32:$scale)))]> {
3466 let Inst{31} = 0; // 32-bit GPR flag
3470 // Scaled single-precision to 64-bit
3471 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3472 fixedpoint_f32_i64, asm,
3473 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3474 fixedpoint_f32_i64:$scale)))]> {
3475 let Inst{31} = 1; // 64-bit GPR flag
3478 // Scaled double-precision to 32-bit
3479 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3480 fixedpoint_f64_i32, asm,
3481 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3482 fixedpoint_f64_i32:$scale)))]> {
3483 let Inst{31} = 0; // 32-bit GPR flag
3487 // Scaled double-precision to 64-bit
3488 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3489 fixedpoint_f64_i64, asm,
3490 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3491 fixedpoint_f64_i64:$scale)))]> {
3492 let Inst{31} = 1; // 64-bit GPR flag
3497 // Integer to floating point conversion
3500 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3501 class BaseIntegerToFP<bit isUnsigned,
3502 RegisterClass srcType, RegisterClass dstType,
3503 Operand immType, string asm, list<dag> pattern>
3504 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3505 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3506 Sched<[WriteFCvt]> {
3510 let Inst{30-23} = 0b00111100;
3511 let Inst{21-17} = 0b00001;
3512 let Inst{16} = isUnsigned;
3513 let Inst{15-10} = scale;
3518 class BaseIntegerToFPUnscaled<bit isUnsigned,
3519 RegisterClass srcType, RegisterClass dstType,
3520 ValueType dvt, string asm, SDNode node>
3521 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3522 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3523 Sched<[WriteFCvt]> {
3527 let Inst{30-23} = 0b00111100;
3528 let Inst{21-17} = 0b10001;
3529 let Inst{16} = isUnsigned;
3530 let Inst{15-10} = 0b000000;
3535 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3537 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3538 let Inst{31} = 0; // 32-bit GPR flag
3539 let Inst{22} = 0; // 32-bit FPR flag
3542 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3543 let Inst{31} = 0; // 32-bit GPR flag
3544 let Inst{22} = 1; // 64-bit FPR flag
3547 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3548 let Inst{31} = 1; // 64-bit GPR flag
3549 let Inst{22} = 0; // 32-bit FPR flag
3552 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3553 let Inst{31} = 1; // 64-bit GPR flag
3554 let Inst{22} = 1; // 64-bit FPR flag
3558 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3560 (fdiv (node GPR32:$Rn),
3561 fixedpoint_f32_i32:$scale))]> {
3562 let Inst{31} = 0; // 32-bit GPR flag
3563 let Inst{22} = 0; // 32-bit FPR flag
3567 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3569 (fdiv (node GPR32:$Rn),
3570 fixedpoint_f64_i32:$scale))]> {
3571 let Inst{31} = 0; // 32-bit GPR flag
3572 let Inst{22} = 1; // 64-bit FPR flag
3576 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3578 (fdiv (node GPR64:$Rn),
3579 fixedpoint_f32_i64:$scale))]> {
3580 let Inst{31} = 1; // 64-bit GPR flag
3581 let Inst{22} = 0; // 32-bit FPR flag
3584 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3586 (fdiv (node GPR64:$Rn),
3587 fixedpoint_f64_i64:$scale))]> {
3588 let Inst{31} = 1; // 64-bit GPR flag
3589 let Inst{22} = 1; // 64-bit FPR flag
3594 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3597 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3598 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3599 RegisterClass srcType, RegisterClass dstType,
3601 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3602 // We use COPY_TO_REGCLASS for these bitconvert operations.
3603 // copyPhysReg() expands the resultant COPY instructions after
3604 // regalloc is done. This gives greater freedom for the allocator
3605 // and related passes (coalescing, copy propagation, et. al.) to
3606 // be more effective.
3607 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3608 Sched<[WriteFCopy]> {
3611 let Inst{30-23} = 0b00111100;
3613 let Inst{20-19} = rmode;
3614 let Inst{18-16} = opcode;
3615 let Inst{15-10} = 0b000000;
3620 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3621 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3622 RegisterClass srcType, RegisterOperand dstType, string asm,
3624 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3625 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3626 Sched<[WriteFCopy]> {
3629 let Inst{30-23} = 0b00111101;
3631 let Inst{20-19} = rmode;
3632 let Inst{18-16} = opcode;
3633 let Inst{15-10} = 0b000000;
3637 let DecoderMethod = "DecodeFMOVLaneInstruction";
3640 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3641 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3642 RegisterOperand srcType, RegisterClass dstType, string asm,
3644 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3645 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3646 Sched<[WriteFCopy]> {
3649 let Inst{30-23} = 0b00111101;
3651 let Inst{20-19} = rmode;
3652 let Inst{18-16} = opcode;
3653 let Inst{15-10} = 0b000000;
3657 let DecoderMethod = "DecodeFMOVLaneInstruction";
3662 multiclass UnscaledConversion<string asm> {
3663 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3664 let Inst{31} = 0; // 32-bit GPR flag
3665 let Inst{22} = 0; // 32-bit FPR flag
3668 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3669 let Inst{31} = 1; // 64-bit GPR flag
3670 let Inst{22} = 1; // 64-bit FPR flag
3673 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3674 let Inst{31} = 0; // 32-bit GPR flag
3675 let Inst{22} = 0; // 32-bit FPR flag
3678 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3679 let Inst{31} = 1; // 64-bit GPR flag
3680 let Inst{22} = 1; // 64-bit FPR flag
3683 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3689 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3697 // Floating point conversion
3700 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3701 RegisterClass srcType, string asm, list<dag> pattern>
3702 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3703 Sched<[WriteFCvt]> {
3706 let Inst{31-24} = 0b00011110;
3707 let Inst{23-22} = type;
3708 let Inst{21-17} = 0b10001;
3709 let Inst{16-15} = opcode;
3710 let Inst{14-10} = 0b10000;
3715 multiclass FPConversion<string asm> {
3716 // Double-precision to Half-precision
3717 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3718 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3720 // Double-precision to Single-precision
3721 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3722 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3724 // Half-precision to Double-precision
3725 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3726 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3728 // Half-precision to Single-precision
3729 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3730 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3732 // Single-precision to Double-precision
3733 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3734 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3736 // Single-precision to Half-precision
3737 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3738 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3742 // Single operand floating point data processing
3745 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3746 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3747 ValueType vt, string asm, SDPatternOperator node>
3748 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3749 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3753 let Inst{31-23} = 0b000111100;
3754 let Inst{21-19} = 0b100;
3755 let Inst{18-15} = opcode;
3756 let Inst{14-10} = 0b10000;
3761 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3762 SDPatternOperator node = null_frag> {
3763 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3764 let Inst{22} = 0; // 32-bit size flag
3767 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3768 let Inst{22} = 1; // 64-bit size flag
3773 // Two operand floating point data processing
3776 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3777 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3778 string asm, list<dag> pat>
3779 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3780 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3785 let Inst{31-23} = 0b000111100;
3787 let Inst{20-16} = Rm;
3788 let Inst{15-12} = opcode;
3789 let Inst{11-10} = 0b10;
3794 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3795 SDPatternOperator node = null_frag> {
3796 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3797 [(set (f32 FPR32:$Rd),
3798 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3799 let Inst{22} = 0; // 32-bit size flag
3802 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3803 [(set (f64 FPR64:$Rd),
3804 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3805 let Inst{22} = 1; // 64-bit size flag
3809 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3810 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3811 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3812 let Inst{22} = 0; // 32-bit size flag
3815 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3816 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3817 let Inst{22} = 1; // 64-bit size flag
3823 // Three operand floating point data processing
3826 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3827 RegisterClass regtype, string asm, list<dag> pat>
3828 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3829 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3830 Sched<[WriteFMul]> {
3835 let Inst{31-23} = 0b000111110;
3836 let Inst{21} = isNegated;
3837 let Inst{20-16} = Rm;
3838 let Inst{15} = isSub;
3839 let Inst{14-10} = Ra;
3844 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3845 SDPatternOperator node> {
3846 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3848 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3849 let Inst{22} = 0; // 32-bit size flag
3852 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3854 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3855 let Inst{22} = 1; // 64-bit size flag
3860 // Floating point data comparisons
3863 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3864 class BaseOneOperandFPComparison<bit signalAllNans,
3865 RegisterClass regtype, string asm,
3867 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3868 Sched<[WriteFCmp]> {
3870 let Inst{31-23} = 0b000111100;
3873 let Inst{15-10} = 0b001000;
3875 let Inst{4} = signalAllNans;
3876 let Inst{3-0} = 0b1000;
3878 // Rm should be 0b00000 canonically, but we need to accept any value.
3879 let PostEncoderMethod = "fixOneOperandFPComparison";
3882 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3883 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3884 string asm, list<dag> pat>
3885 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3886 Sched<[WriteFCmp]> {
3889 let Inst{31-23} = 0b000111100;
3891 let Inst{20-16} = Rm;
3892 let Inst{15-10} = 0b001000;
3894 let Inst{4} = signalAllNans;
3895 let Inst{3-0} = 0b0000;
3898 multiclass FPComparison<bit signalAllNans, string asm,
3899 SDPatternOperator OpNode = null_frag> {
3900 let Defs = [NZCV] in {
3901 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3902 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3906 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3907 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3911 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3912 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3916 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3917 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3924 // Floating point conditional comparisons
3927 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3928 class BaseFPCondComparison<bit signalAllNans,
3929 RegisterClass regtype, string asm>
3930 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3931 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3932 Sched<[WriteFCmp]> {
3938 let Inst{31-23} = 0b000111100;
3940 let Inst{20-16} = Rm;
3941 let Inst{15-12} = cond;
3942 let Inst{11-10} = 0b01;
3944 let Inst{4} = signalAllNans;
3945 let Inst{3-0} = nzcv;
3948 multiclass FPCondComparison<bit signalAllNans, string asm> {
3949 let Defs = [NZCV], Uses = [NZCV] in {
3950 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3954 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3957 } // Defs = [NZCV], Uses = [NZCV]
3961 // Floating point conditional select
3964 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3965 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3966 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3968 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
3969 (i32 imm:$cond), NZCV))]>,
3976 let Inst{31-23} = 0b000111100;
3978 let Inst{20-16} = Rm;
3979 let Inst{15-12} = cond;
3980 let Inst{11-10} = 0b11;
3985 multiclass FPCondSelect<string asm> {
3986 let Uses = [NZCV] in {
3987 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3991 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
3998 // Floating move immediate
4001 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
4002 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
4003 [(set regtype:$Rd, fpimmtype:$imm)]>,
4004 Sched<[WriteFImm]> {
4007 let Inst{31-23} = 0b000111100;
4009 let Inst{20-13} = imm;
4010 let Inst{12-5} = 0b10000000;
4014 multiclass FPMoveImmediate<string asm> {
4015 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
4019 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
4023 } // end of 'let Predicates = [HasFPARMv8]'
4025 //----------------------------------------------------------------------------
4027 //----------------------------------------------------------------------------
4029 let Predicates = [HasNEON] in {
4031 //----------------------------------------------------------------------------
4032 // AdvSIMD three register vector instructions
4033 //----------------------------------------------------------------------------
4035 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4036 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4037 RegisterOperand regtype, string asm, string kind,
4039 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4040 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4041 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4049 let Inst{28-24} = 0b01110;
4050 let Inst{23-22} = size;
4052 let Inst{20-16} = Rm;
4053 let Inst{15-11} = opcode;
4059 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4060 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4061 RegisterOperand regtype, string asm, string kind,
4063 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4064 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4065 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4073 let Inst{28-24} = 0b01110;
4074 let Inst{23-22} = size;
4076 let Inst{20-16} = Rm;
4077 let Inst{15-11} = opcode;
4083 // All operand sizes distinguished in the encoding.
4084 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4085 SDPatternOperator OpNode> {
4086 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4088 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4089 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4091 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4092 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4094 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4095 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4097 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4098 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4100 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4101 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4103 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4104 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4106 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4109 // As above, but D sized elements unsupported.
4110 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4111 SDPatternOperator OpNode> {
4112 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4114 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4115 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4117 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4118 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4120 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4121 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4123 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4124 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4126 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4127 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4129 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4132 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4133 SDPatternOperator OpNode> {
4134 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4136 [(set (v8i8 V64:$dst),
4137 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4138 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4140 [(set (v16i8 V128:$dst),
4141 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4142 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4144 [(set (v4i16 V64:$dst),
4145 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4146 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4148 [(set (v8i16 V128:$dst),
4149 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4150 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4152 [(set (v2i32 V64:$dst),
4153 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4154 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4156 [(set (v4i32 V128:$dst),
4157 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4160 // As above, but only B sized elements supported.
4161 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4162 SDPatternOperator OpNode> {
4163 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4165 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4166 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4168 [(set (v16i8 V128:$Rd),
4169 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4172 // As above, but only S and D sized floating point elements supported.
4173 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4174 string asm, SDPatternOperator OpNode> {
4175 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4177 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4178 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4180 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4181 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4183 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4186 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4188 SDPatternOperator OpNode> {
4189 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4191 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4192 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4194 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4195 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4197 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4200 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4201 string asm, SDPatternOperator OpNode> {
4202 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4204 [(set (v2f32 V64:$dst),
4205 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4206 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4208 [(set (v4f32 V128:$dst),
4209 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4210 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4212 [(set (v2f64 V128:$dst),
4213 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4216 // As above, but D and B sized elements unsupported.
4217 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4218 SDPatternOperator OpNode> {
4219 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4221 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4222 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4224 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4225 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4227 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4228 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4230 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4233 // Logical three vector ops share opcode bits, and only use B sized elements.
4234 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4235 SDPatternOperator OpNode = null_frag> {
4236 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4238 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4239 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4241 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4243 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4244 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4245 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4246 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4247 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4248 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4250 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4251 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4252 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4253 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4254 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4255 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4258 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4259 string asm, SDPatternOperator OpNode> {
4260 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4262 [(set (v8i8 V64:$dst),
4263 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4264 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4266 [(set (v16i8 V128:$dst),
4267 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4268 (v16i8 V128:$Rm)))]>;
4270 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4272 (!cast<Instruction>(NAME#"v8i8")
4273 V64:$LHS, V64:$MHS, V64:$RHS)>;
4274 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4276 (!cast<Instruction>(NAME#"v8i8")
4277 V64:$LHS, V64:$MHS, V64:$RHS)>;
4278 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4280 (!cast<Instruction>(NAME#"v8i8")
4281 V64:$LHS, V64:$MHS, V64:$RHS)>;
4283 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4284 (v8i16 V128:$RHS))),
4285 (!cast<Instruction>(NAME#"v16i8")
4286 V128:$LHS, V128:$MHS, V128:$RHS)>;
4287 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4288 (v4i32 V128:$RHS))),
4289 (!cast<Instruction>(NAME#"v16i8")
4290 V128:$LHS, V128:$MHS, V128:$RHS)>;
4291 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4292 (v2i64 V128:$RHS))),
4293 (!cast<Instruction>(NAME#"v16i8")
4294 V128:$LHS, V128:$MHS, V128:$RHS)>;
4298 //----------------------------------------------------------------------------
4299 // AdvSIMD two register vector instructions.
4300 //----------------------------------------------------------------------------
4302 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4303 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4304 RegisterOperand regtype, string asm, string dstkind,
4305 string srckind, list<dag> pattern>
4306 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4307 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4308 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4315 let Inst{28-24} = 0b01110;
4316 let Inst{23-22} = size;
4317 let Inst{21-17} = 0b10000;
4318 let Inst{16-12} = opcode;
4319 let Inst{11-10} = 0b10;
4324 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4325 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4326 RegisterOperand regtype, string asm, string dstkind,
4327 string srckind, list<dag> pattern>
4328 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4329 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4330 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4337 let Inst{28-24} = 0b01110;
4338 let Inst{23-22} = size;
4339 let Inst{21-17} = 0b10000;
4340 let Inst{16-12} = opcode;
4341 let Inst{11-10} = 0b10;
4346 // Supports B, H, and S element sizes.
4347 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4348 SDPatternOperator OpNode> {
4349 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4351 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4352 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4353 asm, ".16b", ".16b",
4354 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4355 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4357 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4358 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4360 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4361 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4363 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4364 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4366 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4369 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4370 RegisterOperand regtype, string asm, string dstkind,
4371 string srckind, string amount>
4372 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4373 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4374 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4380 let Inst{29-24} = 0b101110;
4381 let Inst{23-22} = size;
4382 let Inst{21-10} = 0b100001001110;
4387 multiclass SIMDVectorLShiftLongBySizeBHS {
4388 let neverHasSideEffects = 1 in {
4389 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4390 "shll", ".8h", ".8b", "8">;
4391 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4392 "shll2", ".8h", ".16b", "8">;
4393 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4394 "shll", ".4s", ".4h", "16">;
4395 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4396 "shll2", ".4s", ".8h", "16">;
4397 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4398 "shll", ".2d", ".2s", "32">;
4399 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4400 "shll2", ".2d", ".4s", "32">;
4404 // Supports all element sizes.
4405 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4406 SDPatternOperator OpNode> {
4407 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4409 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4410 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4412 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4413 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4415 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4416 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4418 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4419 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4421 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4422 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4424 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4427 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4428 SDPatternOperator OpNode> {
4429 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4431 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4433 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4435 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4436 (v16i8 V128:$Rn)))]>;
4437 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4439 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4440 (v4i16 V64:$Rn)))]>;
4441 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4443 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4444 (v8i16 V128:$Rn)))]>;
4445 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4447 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4448 (v2i32 V64:$Rn)))]>;
4449 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4451 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4452 (v4i32 V128:$Rn)))]>;
4455 // Supports all element sizes, except 1xD.
4456 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4457 SDPatternOperator OpNode> {
4458 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4460 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4461 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4462 asm, ".16b", ".16b",
4463 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4464 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4466 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4467 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4469 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4470 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4472 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4473 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4475 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4476 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4478 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4481 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4482 SDPatternOperator OpNode = null_frag> {
4483 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4485 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4486 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4487 asm, ".16b", ".16b",
4488 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4489 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4491 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4492 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4494 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4495 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4497 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4498 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4500 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4501 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4503 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4507 // Supports only B element sizes.
4508 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4509 SDPatternOperator OpNode> {
4510 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4512 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4513 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4514 asm, ".16b", ".16b",
4515 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4519 // Supports only B and H element sizes.
4520 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4521 SDPatternOperator OpNode> {
4522 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4524 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4525 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4526 asm, ".16b", ".16b",
4527 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4528 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4530 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4531 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4533 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4536 // Supports only S and D element sizes, uses high bit of the size field
4537 // as an extra opcode bit.
4538 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4539 SDPatternOperator OpNode> {
4540 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4542 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4543 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4545 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4546 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4548 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4551 // Supports only S element size.
4552 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4553 SDPatternOperator OpNode> {
4554 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4556 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4557 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4559 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4563 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4564 SDPatternOperator OpNode> {
4565 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4567 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4568 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4570 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4571 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4573 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4576 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4577 SDPatternOperator OpNode> {
4578 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4580 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4581 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4583 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4584 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4586 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4590 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4591 RegisterOperand inreg, RegisterOperand outreg,
4592 string asm, string outkind, string inkind,
4594 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4595 "{\t$Rd" # outkind # ", $Rn" # inkind #
4596 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4603 let Inst{28-24} = 0b01110;
4604 let Inst{23-22} = size;
4605 let Inst{21-17} = 0b10000;
4606 let Inst{16-12} = opcode;
4607 let Inst{11-10} = 0b10;
4612 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4613 RegisterOperand inreg, RegisterOperand outreg,
4614 string asm, string outkind, string inkind,
4616 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4617 "{\t$Rd" # outkind # ", $Rn" # inkind #
4618 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4625 let Inst{28-24} = 0b01110;
4626 let Inst{23-22} = size;
4627 let Inst{21-17} = 0b10000;
4628 let Inst{16-12} = opcode;
4629 let Inst{11-10} = 0b10;
4634 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4635 SDPatternOperator OpNode> {
4636 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4638 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4639 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4640 asm#"2", ".16b", ".8h", []>;
4641 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4643 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4644 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4645 asm#"2", ".8h", ".4s", []>;
4646 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4648 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4649 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4650 asm#"2", ".4s", ".2d", []>;
4652 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4653 (!cast<Instruction>(NAME # "v16i8")
4654 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4655 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4656 (!cast<Instruction>(NAME # "v8i16")
4657 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4658 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4659 (!cast<Instruction>(NAME # "v4i32")
4660 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4663 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4664 RegisterOperand regtype,
4665 string asm, string kind, string zero,
4666 ValueType dty, ValueType sty, SDNode OpNode>
4667 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4668 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4669 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4670 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4677 let Inst{28-24} = 0b01110;
4678 let Inst{23-22} = size;
4679 let Inst{21-17} = 0b10000;
4680 let Inst{16-12} = opcode;
4681 let Inst{11-10} = 0b10;
4686 // Comparisons support all element sizes, except 1xD.
4687 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4689 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4691 v8i8, v8i8, OpNode>;
4692 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4694 v16i8, v16i8, OpNode>;
4695 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4697 v4i16, v4i16, OpNode>;
4698 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4700 v8i16, v8i16, OpNode>;
4701 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4703 v2i32, v2i32, OpNode>;
4704 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4706 v4i32, v4i32, OpNode>;
4707 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4709 v2i64, v2i64, OpNode>;
4712 // FP Comparisons support only S and D element sizes.
4713 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4714 string asm, SDNode OpNode> {
4716 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4718 v2i32, v2f32, OpNode>;
4719 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4721 v4i32, v4f32, OpNode>;
4722 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4724 v2i64, v2f64, OpNode>;
4726 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4727 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4728 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4729 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4730 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4731 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4732 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4733 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4734 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4735 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4736 def : InstAlias<asm # ".2d $Vd, $Vn, #0",
4737 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4740 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4741 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4742 RegisterOperand outtype, RegisterOperand intype,
4743 string asm, string VdTy, string VnTy,
4745 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4746 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4753 let Inst{28-24} = 0b01110;
4754 let Inst{23-22} = size;
4755 let Inst{21-17} = 0b10000;
4756 let Inst{16-12} = opcode;
4757 let Inst{11-10} = 0b10;
4762 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4763 RegisterOperand outtype, RegisterOperand intype,
4764 string asm, string VdTy, string VnTy,
4766 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4767 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4774 let Inst{28-24} = 0b01110;
4775 let Inst{23-22} = size;
4776 let Inst{21-17} = 0b10000;
4777 let Inst{16-12} = opcode;
4778 let Inst{11-10} = 0b10;
4783 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4784 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4785 asm, ".4s", ".4h", []>;
4786 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4787 asm#"2", ".4s", ".8h", []>;
4788 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4789 asm, ".2d", ".2s", []>;
4790 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4791 asm#"2", ".2d", ".4s", []>;
4794 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4795 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4796 asm, ".4h", ".4s", []>;
4797 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4798 asm#"2", ".8h", ".4s", []>;
4799 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4800 asm, ".2s", ".2d", []>;
4801 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4802 asm#"2", ".4s", ".2d", []>;
4805 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4807 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4809 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4810 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4811 asm#"2", ".4s", ".2d", []>;
4813 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4814 (!cast<Instruction>(NAME # "v4f32")
4815 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4818 //----------------------------------------------------------------------------
4819 // AdvSIMD three register different-size vector instructions.
4820 //----------------------------------------------------------------------------
4822 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4823 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4824 RegisterOperand outtype, RegisterOperand intype1,
4825 RegisterOperand intype2, string asm,
4826 string outkind, string inkind1, string inkind2,
4828 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4829 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4830 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4836 let Inst{30} = size{0};
4838 let Inst{28-24} = 0b01110;
4839 let Inst{23-22} = size{2-1};
4841 let Inst{20-16} = Rm;
4842 let Inst{15-12} = opcode;
4843 let Inst{11-10} = 0b00;
4848 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4849 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4850 RegisterOperand outtype, RegisterOperand intype1,
4851 RegisterOperand intype2, string asm,
4852 string outkind, string inkind1, string inkind2,
4854 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4855 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4856 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4862 let Inst{30} = size{0};
4864 let Inst{28-24} = 0b01110;
4865 let Inst{23-22} = size{2-1};
4867 let Inst{20-16} = Rm;
4868 let Inst{15-12} = opcode;
4869 let Inst{11-10} = 0b00;
4874 // FIXME: TableGen doesn't know how to deal with expanded types that also
4875 // change the element count (in this case, placing the results in
4876 // the high elements of the result register rather than the low
4877 // elements). Until that's fixed, we can't code-gen those.
4878 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4880 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4882 asm, ".8b", ".8h", ".8h",
4883 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4884 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4886 asm#"2", ".16b", ".8h", ".8h",
4888 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4890 asm, ".4h", ".4s", ".4s",
4891 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4892 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4894 asm#"2", ".8h", ".4s", ".4s",
4896 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4898 asm, ".2s", ".2d", ".2d",
4899 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4900 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4902 asm#"2", ".4s", ".2d", ".2d",
4906 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4907 // a version attached to an instruction.
4908 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4910 (!cast<Instruction>(NAME # "v8i16_v16i8")
4911 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4912 V128:$Rn, V128:$Rm)>;
4913 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4915 (!cast<Instruction>(NAME # "v4i32_v8i16")
4916 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4917 V128:$Rn, V128:$Rm)>;
4918 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4920 (!cast<Instruction>(NAME # "v2i64_v4i32")
4921 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4922 V128:$Rn, V128:$Rm)>;
4925 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4927 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4929 asm, ".8h", ".8b", ".8b",
4930 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4931 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4933 asm#"2", ".8h", ".16b", ".16b", []>;
4934 let Predicates = [HasCrypto] in {
4935 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4937 asm, ".1q", ".1d", ".1d", []>;
4938 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4940 asm#"2", ".1q", ".2d", ".2d", []>;
4943 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4944 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4945 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4948 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4949 SDPatternOperator OpNode> {
4950 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4952 asm, ".4s", ".4h", ".4h",
4953 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4954 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4956 asm#"2", ".4s", ".8h", ".8h",
4957 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4958 (extract_high_v8i16 V128:$Rm)))]>;
4959 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4961 asm, ".2d", ".2s", ".2s",
4962 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4963 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4965 asm#"2", ".2d", ".4s", ".4s",
4966 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4967 (extract_high_v4i32 V128:$Rm)))]>;
4970 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4971 SDPatternOperator OpNode = null_frag> {
4972 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4974 asm, ".8h", ".8b", ".8b",
4975 [(set (v8i16 V128:$Rd),
4976 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4977 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4979 asm#"2", ".8h", ".16b", ".16b",
4980 [(set (v8i16 V128:$Rd),
4981 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4982 (extract_high_v16i8 V128:$Rm)))))]>;
4983 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4985 asm, ".4s", ".4h", ".4h",
4986 [(set (v4i32 V128:$Rd),
4987 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4988 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4990 asm#"2", ".4s", ".8h", ".8h",
4991 [(set (v4i32 V128:$Rd),
4992 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4993 (extract_high_v8i16 V128:$Rm)))))]>;
4994 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4996 asm, ".2d", ".2s", ".2s",
4997 [(set (v2i64 V128:$Rd),
4998 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
4999 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5001 asm#"2", ".2d", ".4s", ".4s",
5002 [(set (v2i64 V128:$Rd),
5003 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5004 (extract_high_v4i32 V128:$Rm)))))]>;
5007 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
5009 SDPatternOperator OpNode> {
5010 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5012 asm, ".8h", ".8b", ".8b",
5013 [(set (v8i16 V128:$dst),
5014 (add (v8i16 V128:$Rd),
5015 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
5016 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5018 asm#"2", ".8h", ".16b", ".16b",
5019 [(set (v8i16 V128:$dst),
5020 (add (v8i16 V128:$Rd),
5021 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5022 (extract_high_v16i8 V128:$Rm))))))]>;
5023 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5025 asm, ".4s", ".4h", ".4h",
5026 [(set (v4i32 V128:$dst),
5027 (add (v4i32 V128:$Rd),
5028 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
5029 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5031 asm#"2", ".4s", ".8h", ".8h",
5032 [(set (v4i32 V128:$dst),
5033 (add (v4i32 V128:$Rd),
5034 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5035 (extract_high_v8i16 V128:$Rm))))))]>;
5036 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5038 asm, ".2d", ".2s", ".2s",
5039 [(set (v2i64 V128:$dst),
5040 (add (v2i64 V128:$Rd),
5041 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
5042 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5044 asm#"2", ".2d", ".4s", ".4s",
5045 [(set (v2i64 V128:$dst),
5046 (add (v2i64 V128:$Rd),
5047 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5048 (extract_high_v4i32 V128:$Rm))))))]>;
5051 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5052 SDPatternOperator OpNode = null_frag> {
5053 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5055 asm, ".8h", ".8b", ".8b",
5056 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5057 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5059 asm#"2", ".8h", ".16b", ".16b",
5060 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5061 (extract_high_v16i8 V128:$Rm)))]>;
5062 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5064 asm, ".4s", ".4h", ".4h",
5065 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5066 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5068 asm#"2", ".4s", ".8h", ".8h",
5069 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5070 (extract_high_v8i16 V128:$Rm)))]>;
5071 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5073 asm, ".2d", ".2s", ".2s",
5074 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5075 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5077 asm#"2", ".2d", ".4s", ".4s",
5078 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5079 (extract_high_v4i32 V128:$Rm)))]>;
5082 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5084 SDPatternOperator OpNode> {
5085 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5087 asm, ".8h", ".8b", ".8b",
5088 [(set (v8i16 V128:$dst),
5089 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5090 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5092 asm#"2", ".8h", ".16b", ".16b",
5093 [(set (v8i16 V128:$dst),
5094 (OpNode (v8i16 V128:$Rd),
5095 (extract_high_v16i8 V128:$Rn),
5096 (extract_high_v16i8 V128:$Rm)))]>;
5097 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5099 asm, ".4s", ".4h", ".4h",
5100 [(set (v4i32 V128:$dst),
5101 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5102 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5104 asm#"2", ".4s", ".8h", ".8h",
5105 [(set (v4i32 V128:$dst),
5106 (OpNode (v4i32 V128:$Rd),
5107 (extract_high_v8i16 V128:$Rn),
5108 (extract_high_v8i16 V128:$Rm)))]>;
5109 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5111 asm, ".2d", ".2s", ".2s",
5112 [(set (v2i64 V128:$dst),
5113 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5114 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5116 asm#"2", ".2d", ".4s", ".4s",
5117 [(set (v2i64 V128:$dst),
5118 (OpNode (v2i64 V128:$Rd),
5119 (extract_high_v4i32 V128:$Rn),
5120 (extract_high_v4i32 V128:$Rm)))]>;
5123 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5124 SDPatternOperator Accum> {
5125 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5127 asm, ".4s", ".4h", ".4h",
5128 [(set (v4i32 V128:$dst),
5129 (Accum (v4i32 V128:$Rd),
5130 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5131 (v4i16 V64:$Rm)))))]>;
5132 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5134 asm#"2", ".4s", ".8h", ".8h",
5135 [(set (v4i32 V128:$dst),
5136 (Accum (v4i32 V128:$Rd),
5137 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5138 (extract_high_v8i16 V128:$Rm)))))]>;
5139 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5141 asm, ".2d", ".2s", ".2s",
5142 [(set (v2i64 V128:$dst),
5143 (Accum (v2i64 V128:$Rd),
5144 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5145 (v2i32 V64:$Rm)))))]>;
5146 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5148 asm#"2", ".2d", ".4s", ".4s",
5149 [(set (v2i64 V128:$dst),
5150 (Accum (v2i64 V128:$Rd),
5151 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5152 (extract_high_v4i32 V128:$Rm)))))]>;
5155 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5156 SDPatternOperator OpNode> {
5157 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5159 asm, ".8h", ".8h", ".8b",
5160 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5161 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5163 asm#"2", ".8h", ".8h", ".16b",
5164 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5165 (extract_high_v16i8 V128:$Rm)))]>;
5166 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5168 asm, ".4s", ".4s", ".4h",
5169 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5170 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5172 asm#"2", ".4s", ".4s", ".8h",
5173 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5174 (extract_high_v8i16 V128:$Rm)))]>;
5175 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5177 asm, ".2d", ".2d", ".2s",
5178 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5179 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5181 asm#"2", ".2d", ".2d", ".4s",
5182 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5183 (extract_high_v4i32 V128:$Rm)))]>;
5186 //----------------------------------------------------------------------------
5187 // AdvSIMD bitwise extract from vector
5188 //----------------------------------------------------------------------------
5190 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5191 string asm, string kind>
5192 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5193 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5194 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5195 [(set (vty regtype:$Rd),
5196 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5203 let Inst{30} = size;
5204 let Inst{29-21} = 0b101110000;
5205 let Inst{20-16} = Rm;
5207 let Inst{14-11} = imm;
5214 multiclass SIMDBitwiseExtract<string asm> {
5215 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5218 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5221 //----------------------------------------------------------------------------
5222 // AdvSIMD zip vector
5223 //----------------------------------------------------------------------------
5225 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5226 string asm, string kind, SDNode OpNode, ValueType valty>
5227 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5228 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5229 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5230 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5236 let Inst{30} = size{0};
5237 let Inst{29-24} = 0b001110;
5238 let Inst{23-22} = size{2-1};
5240 let Inst{20-16} = Rm;
5242 let Inst{14-12} = opc;
5243 let Inst{11-10} = 0b10;
5248 multiclass SIMDZipVector<bits<3>opc, string asm,
5250 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5251 asm, ".8b", OpNode, v8i8>;
5252 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5253 asm, ".16b", OpNode, v16i8>;
5254 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5255 asm, ".4h", OpNode, v4i16>;
5256 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5257 asm, ".8h", OpNode, v8i16>;
5258 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5259 asm, ".2s", OpNode, v2i32>;
5260 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5261 asm, ".4s", OpNode, v4i32>;
5262 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5263 asm, ".2d", OpNode, v2i64>;
5265 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5266 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5267 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5268 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5269 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5270 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5273 //----------------------------------------------------------------------------
5274 // AdvSIMD three register scalar instructions
5275 //----------------------------------------------------------------------------
5277 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5278 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5279 RegisterClass regtype, string asm,
5281 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5282 "\t$Rd, $Rn, $Rm", "", pattern>,
5287 let Inst{31-30} = 0b01;
5289 let Inst{28-24} = 0b11110;
5290 let Inst{23-22} = size;
5292 let Inst{20-16} = Rm;
5293 let Inst{15-11} = opcode;
5299 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5300 SDPatternOperator OpNode> {
5301 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5302 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5305 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5306 SDPatternOperator OpNode> {
5307 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5308 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5309 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5310 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5311 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5313 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5314 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5315 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5316 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5319 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5320 SDPatternOperator OpNode> {
5321 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5322 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5323 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5326 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5327 SDPatternOperator OpNode = null_frag> {
5328 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5329 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5330 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5331 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5332 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5335 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5336 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5339 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5340 SDPatternOperator OpNode = null_frag> {
5341 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5342 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5343 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5344 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5345 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5348 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5349 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5352 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5353 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5354 : I<oops, iops, asm,
5355 "\t$Rd, $Rn, $Rm", cstr, pat>,
5360 let Inst{31-30} = 0b01;
5362 let Inst{28-24} = 0b11110;
5363 let Inst{23-22} = size;
5365 let Inst{20-16} = Rm;
5366 let Inst{15-11} = opcode;
5372 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5373 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5374 SDPatternOperator OpNode = null_frag> {
5375 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5377 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5378 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5380 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5381 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5384 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5385 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5386 SDPatternOperator OpNode = null_frag> {
5387 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5389 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5390 asm, "$Rd = $dst", []>;
5391 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5393 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5395 [(set (i64 FPR64:$dst),
5396 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5399 //----------------------------------------------------------------------------
5400 // AdvSIMD two register scalar instructions
5401 //----------------------------------------------------------------------------
5403 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5404 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5405 RegisterClass regtype, RegisterClass regtype2,
5406 string asm, list<dag> pat>
5407 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5408 "\t$Rd, $Rn", "", pat>,
5412 let Inst{31-30} = 0b01;
5414 let Inst{28-24} = 0b11110;
5415 let Inst{23-22} = size;
5416 let Inst{21-17} = 0b10000;
5417 let Inst{16-12} = opcode;
5418 let Inst{11-10} = 0b10;
5423 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5424 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5425 RegisterClass regtype, RegisterClass regtype2,
5426 string asm, list<dag> pat>
5427 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5428 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5432 let Inst{31-30} = 0b01;
5434 let Inst{28-24} = 0b11110;
5435 let Inst{23-22} = size;
5436 let Inst{21-17} = 0b10000;
5437 let Inst{16-12} = opcode;
5438 let Inst{11-10} = 0b10;
5444 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5445 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5446 RegisterClass regtype, string asm, string zero>
5447 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5448 "\t$Rd, $Rn, #" # zero, "", []>,
5452 let Inst{31-30} = 0b01;
5454 let Inst{28-24} = 0b11110;
5455 let Inst{23-22} = size;
5456 let Inst{21-17} = 0b10000;
5457 let Inst{16-12} = opcode;
5458 let Inst{11-10} = 0b10;
5463 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5464 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5465 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5469 let Inst{31-17} = 0b011111100110000;
5470 let Inst{16-12} = opcode;
5471 let Inst{11-10} = 0b10;
5476 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5477 SDPatternOperator OpNode> {
5478 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5480 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5481 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5484 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5485 SDPatternOperator OpNode> {
5486 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5487 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5489 def : InstAlias<asm # " $Rd, $Rn, #0",
5490 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5491 def : InstAlias<asm # " $Rd, $Rn, #0",
5492 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5494 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5495 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5498 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5499 SDPatternOperator OpNode = null_frag> {
5500 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5501 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5503 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5504 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5507 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5508 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5509 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5512 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5513 SDPatternOperator OpNode> {
5514 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5515 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5516 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5517 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5520 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5521 SDPatternOperator OpNode = null_frag> {
5522 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5523 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5524 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5525 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5526 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5527 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5528 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5531 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5532 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5535 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5537 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5538 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5539 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5540 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5541 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5542 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5543 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5546 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5547 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5552 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5553 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5554 SDPatternOperator OpNode = null_frag> {
5555 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5556 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5557 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5558 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5561 //----------------------------------------------------------------------------
5562 // AdvSIMD scalar pairwise instructions
5563 //----------------------------------------------------------------------------
5565 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5566 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5567 RegisterOperand regtype, RegisterOperand vectype,
5568 string asm, string kind>
5569 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5570 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5574 let Inst{31-30} = 0b01;
5576 let Inst{28-24} = 0b11110;
5577 let Inst{23-22} = size;
5578 let Inst{21-17} = 0b11000;
5579 let Inst{16-12} = opcode;
5580 let Inst{11-10} = 0b10;
5585 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5586 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5590 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5591 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5593 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5597 //----------------------------------------------------------------------------
5598 // AdvSIMD across lanes instructions
5599 //----------------------------------------------------------------------------
5601 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5602 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5603 RegisterClass regtype, RegisterOperand vectype,
5604 string asm, string kind, list<dag> pattern>
5605 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5606 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5613 let Inst{28-24} = 0b01110;
5614 let Inst{23-22} = size;
5615 let Inst{21-17} = 0b11000;
5616 let Inst{16-12} = opcode;
5617 let Inst{11-10} = 0b10;
5622 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5624 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5626 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5628 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5630 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5632 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5636 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5637 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5639 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5641 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5643 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5645 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5649 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5651 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5653 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5656 //----------------------------------------------------------------------------
5657 // AdvSIMD INS/DUP instructions
5658 //----------------------------------------------------------------------------
5660 // FIXME: There has got to be a better way to factor these. ugh.
5662 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5663 string operands, string constraints, list<dag> pattern>
5664 : I<outs, ins, asm, operands, constraints, pattern>,
5671 let Inst{28-21} = 0b01110000;
5678 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5679 RegisterOperand vecreg, RegisterClass regtype>
5680 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5681 "{\t$Rd" # size # ", $Rn" #
5682 "|" # size # "\t$Rd, $Rn}", "",
5683 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5684 let Inst{20-16} = imm5;
5685 let Inst{14-11} = 0b0001;
5688 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5689 ValueType vectype, ValueType insreg,
5690 RegisterOperand vecreg, Operand idxtype,
5691 ValueType elttype, SDNode OpNode>
5692 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5693 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5694 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5695 [(set (vectype vecreg:$Rd),
5696 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5697 let Inst{14-11} = 0b0000;
5700 class SIMDDup64FromElement
5701 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5702 VectorIndexD, i64, AArch64duplane64> {
5705 let Inst{19-16} = 0b1000;
5708 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5709 RegisterOperand vecreg>
5710 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5711 VectorIndexS, i64, AArch64duplane32> {
5713 let Inst{20-19} = idx;
5714 let Inst{18-16} = 0b100;
5717 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5718 RegisterOperand vecreg>
5719 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5720 VectorIndexH, i64, AArch64duplane16> {
5722 let Inst{20-18} = idx;
5723 let Inst{17-16} = 0b10;
5726 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5727 RegisterOperand vecreg>
5728 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5729 VectorIndexB, i64, AArch64duplane8> {
5731 let Inst{20-17} = idx;
5735 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5736 Operand idxtype, string asm, list<dag> pattern>
5737 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5738 "{\t$Rd, $Rn" # size # "$idx" #
5739 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5740 let Inst{14-11} = imm4;
5743 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5745 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5746 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5748 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5749 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5751 class SIMDMovAlias<string asm, string size, Instruction inst,
5752 RegisterClass regtype, Operand idxtype>
5753 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5754 "|" # size # "\t$dst, $src$idx}",
5755 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5758 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5760 let Inst{20-17} = idx;
5763 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5765 let Inst{20-17} = idx;
5768 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5770 let Inst{20-18} = idx;
5771 let Inst{17-16} = 0b10;
5773 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5775 let Inst{20-18} = idx;
5776 let Inst{17-16} = 0b10;
5778 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5780 let Inst{20-19} = idx;
5781 let Inst{18-16} = 0b100;
5786 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5788 let Inst{20-17} = idx;
5791 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5793 let Inst{20-18} = idx;
5794 let Inst{17-16} = 0b10;
5796 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5798 let Inst{20-19} = idx;
5799 let Inst{18-16} = 0b100;
5801 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5804 let Inst{19-16} = 0b1000;
5806 def : SIMDMovAlias<"mov", ".s",
5807 !cast<Instruction>(NAME#"vi32"),
5808 GPR32, VectorIndexS>;
5809 def : SIMDMovAlias<"mov", ".d",
5810 !cast<Instruction>(NAME#"vi64"),
5811 GPR64, VectorIndexD>;
5814 class SIMDInsFromMain<string size, ValueType vectype,
5815 RegisterClass regtype, Operand idxtype>
5816 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5817 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5818 "{\t$Rd" # size # "$idx, $Rn" #
5819 "|" # size # "\t$Rd$idx, $Rn}",
5822 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5823 let Inst{14-11} = 0b0011;
5826 class SIMDInsFromElement<string size, ValueType vectype,
5827 ValueType elttype, Operand idxtype>
5828 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5829 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5830 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5831 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5836 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5839 class SIMDInsMainMovAlias<string size, Instruction inst,
5840 RegisterClass regtype, Operand idxtype>
5841 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5842 "|" # size #"\t$dst$idx, $src}",
5843 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5844 class SIMDInsElementMovAlias<string size, Instruction inst,
5846 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5847 # "|" # size #" $dst$idx, $src$idx2}",
5848 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5851 multiclass SIMDIns {
5852 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5854 let Inst{20-17} = idx;
5857 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5859 let Inst{20-18} = idx;
5860 let Inst{17-16} = 0b10;
5862 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5864 let Inst{20-19} = idx;
5865 let Inst{18-16} = 0b100;
5867 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5870 let Inst{19-16} = 0b1000;
5873 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5876 let Inst{20-17} = idx;
5878 let Inst{14-11} = idx2;
5880 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5883 let Inst{20-18} = idx;
5884 let Inst{17-16} = 0b10;
5885 let Inst{14-12} = idx2;
5888 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5891 let Inst{20-19} = idx;
5892 let Inst{18-16} = 0b100;
5893 let Inst{14-13} = idx2;
5894 let Inst{12-11} = 0;
5896 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5900 let Inst{19-16} = 0b1000;
5901 let Inst{14} = idx2;
5902 let Inst{13-11} = 0;
5905 // For all forms of the INS instruction, the "mov" mnemonic is the
5906 // preferred alias. Why they didn't just call the instruction "mov" in
5907 // the first place is a very good question indeed...
5908 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5909 GPR32, VectorIndexB>;
5910 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5911 GPR32, VectorIndexH>;
5912 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5913 GPR32, VectorIndexS>;
5914 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5915 GPR64, VectorIndexD>;
5917 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5919 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5921 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5923 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5927 //----------------------------------------------------------------------------
5929 //----------------------------------------------------------------------------
5931 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5932 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5933 RegisterOperand listtype, string asm, string kind>
5934 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5935 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5942 let Inst{29-21} = 0b001110000;
5943 let Inst{20-16} = Vm;
5945 let Inst{14-13} = len;
5947 let Inst{11-10} = 0b00;
5952 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5953 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5954 RegisterOperand listtype, string asm, string kind>
5955 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5956 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
5963 let Inst{29-21} = 0b001110000;
5964 let Inst{20-16} = Vm;
5966 let Inst{14-13} = len;
5968 let Inst{11-10} = 0b00;
5973 class SIMDTableLookupAlias<string asm, Instruction inst,
5974 RegisterOperand vectype, RegisterOperand listtype>
5975 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
5976 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
5978 multiclass SIMDTableLookup<bit op, string asm> {
5979 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
5981 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
5983 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
5985 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
5987 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
5989 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
5991 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
5993 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
5996 def : SIMDTableLookupAlias<asm # ".8b",
5997 !cast<Instruction>(NAME#"v8i8One"),
5998 V64, VecListOne128>;
5999 def : SIMDTableLookupAlias<asm # ".8b",
6000 !cast<Instruction>(NAME#"v8i8Two"),
6001 V64, VecListTwo128>;
6002 def : SIMDTableLookupAlias<asm # ".8b",
6003 !cast<Instruction>(NAME#"v8i8Three"),
6004 V64, VecListThree128>;
6005 def : SIMDTableLookupAlias<asm # ".8b",
6006 !cast<Instruction>(NAME#"v8i8Four"),
6007 V64, VecListFour128>;
6008 def : SIMDTableLookupAlias<asm # ".16b",
6009 !cast<Instruction>(NAME#"v16i8One"),
6010 V128, VecListOne128>;
6011 def : SIMDTableLookupAlias<asm # ".16b",
6012 !cast<Instruction>(NAME#"v16i8Two"),
6013 V128, VecListTwo128>;
6014 def : SIMDTableLookupAlias<asm # ".16b",
6015 !cast<Instruction>(NAME#"v16i8Three"),
6016 V128, VecListThree128>;
6017 def : SIMDTableLookupAlias<asm # ".16b",
6018 !cast<Instruction>(NAME#"v16i8Four"),
6019 V128, VecListFour128>;
6022 multiclass SIMDTableLookupTied<bit op, string asm> {
6023 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6025 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
6027 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
6029 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
6031 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6033 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
6035 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
6037 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
6040 def : SIMDTableLookupAlias<asm # ".8b",
6041 !cast<Instruction>(NAME#"v8i8One"),
6042 V64, VecListOne128>;
6043 def : SIMDTableLookupAlias<asm # ".8b",
6044 !cast<Instruction>(NAME#"v8i8Two"),
6045 V64, VecListTwo128>;
6046 def : SIMDTableLookupAlias<asm # ".8b",
6047 !cast<Instruction>(NAME#"v8i8Three"),
6048 V64, VecListThree128>;
6049 def : SIMDTableLookupAlias<asm # ".8b",
6050 !cast<Instruction>(NAME#"v8i8Four"),
6051 V64, VecListFour128>;
6052 def : SIMDTableLookupAlias<asm # ".16b",
6053 !cast<Instruction>(NAME#"v16i8One"),
6054 V128, VecListOne128>;
6055 def : SIMDTableLookupAlias<asm # ".16b",
6056 !cast<Instruction>(NAME#"v16i8Two"),
6057 V128, VecListTwo128>;
6058 def : SIMDTableLookupAlias<asm # ".16b",
6059 !cast<Instruction>(NAME#"v16i8Three"),
6060 V128, VecListThree128>;
6061 def : SIMDTableLookupAlias<asm # ".16b",
6062 !cast<Instruction>(NAME#"v16i8Four"),
6063 V128, VecListFour128>;
6067 //----------------------------------------------------------------------------
6068 // AdvSIMD scalar CPY
6069 //----------------------------------------------------------------------------
6070 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6071 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6072 string kind, Operand idxtype>
6073 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6074 "{\t$dst, $src" # kind # "$idx" #
6075 "|\t$dst, $src$idx}", "", []>,
6079 let Inst{31-21} = 0b01011110000;
6080 let Inst{15-10} = 0b000001;
6081 let Inst{9-5} = src;
6082 let Inst{4-0} = dst;
6085 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6086 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6087 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6088 # "|\t$dst, $src$index}",
6089 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6092 multiclass SIMDScalarCPY<string asm> {
6093 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6095 let Inst{20-17} = idx;
6098 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6100 let Inst{20-18} = idx;
6101 let Inst{17-16} = 0b10;
6103 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6105 let Inst{20-19} = idx;
6106 let Inst{18-16} = 0b100;
6108 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6111 let Inst{19-16} = 0b1000;
6114 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6115 VectorIndexD:$idx)))),
6116 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6118 // 'DUP' mnemonic aliases.
6119 def : SIMDScalarCPYAlias<"dup", ".b",
6120 !cast<Instruction>(NAME#"i8"),
6121 FPR8, V128, VectorIndexB>;
6122 def : SIMDScalarCPYAlias<"dup", ".h",
6123 !cast<Instruction>(NAME#"i16"),
6124 FPR16, V128, VectorIndexH>;
6125 def : SIMDScalarCPYAlias<"dup", ".s",
6126 !cast<Instruction>(NAME#"i32"),
6127 FPR32, V128, VectorIndexS>;
6128 def : SIMDScalarCPYAlias<"dup", ".d",
6129 !cast<Instruction>(NAME#"i64"),
6130 FPR64, V128, VectorIndexD>;
6133 //----------------------------------------------------------------------------
6134 // AdvSIMD modified immediate instructions
6135 //----------------------------------------------------------------------------
6137 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6138 string asm, string op_string,
6139 string cstr, list<dag> pattern>
6140 : I<oops, iops, asm, op_string, cstr, pattern>,
6147 let Inst{28-19} = 0b0111100000;
6148 let Inst{18-16} = imm8{7-5};
6149 let Inst{11-10} = 0b01;
6150 let Inst{9-5} = imm8{4-0};
6154 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6155 Operand immtype, dag opt_shift_iop,
6156 string opt_shift, string asm, string kind,
6158 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6159 !con((ins immtype:$imm8), opt_shift_iop), asm,
6160 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6161 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6163 let DecoderMethod = "DecodeModImmInstruction";
6166 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6167 Operand immtype, dag opt_shift_iop,
6168 string opt_shift, string asm, string kind,
6170 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6171 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6172 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6173 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6174 "$Rd = $dst", pattern> {
6175 let DecoderMethod = "DecodeModImmTiedInstruction";
6178 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6179 RegisterOperand vectype, string asm,
6180 string kind, list<dag> pattern>
6181 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6182 (ins logical_vec_shift:$shift),
6183 "$shift", asm, kind, pattern> {
6185 let Inst{15} = b15_b12{1};
6186 let Inst{14-13} = shift;
6187 let Inst{12} = b15_b12{0};
6190 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6191 RegisterOperand vectype, string asm,
6192 string kind, list<dag> pattern>
6193 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6194 (ins logical_vec_shift:$shift),
6195 "$shift", asm, kind, pattern> {
6197 let Inst{15} = b15_b12{1};
6198 let Inst{14-13} = shift;
6199 let Inst{12} = b15_b12{0};
6203 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6204 RegisterOperand vectype, string asm,
6205 string kind, list<dag> pattern>
6206 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6207 (ins logical_vec_hw_shift:$shift),
6208 "$shift", asm, kind, pattern> {
6210 let Inst{15} = b15_b12{1};
6212 let Inst{13} = shift{0};
6213 let Inst{12} = b15_b12{0};
6216 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6217 RegisterOperand vectype, string asm,
6218 string kind, list<dag> pattern>
6219 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6220 (ins logical_vec_hw_shift:$shift),
6221 "$shift", asm, kind, pattern> {
6223 let Inst{15} = b15_b12{1};
6225 let Inst{13} = shift{0};
6226 let Inst{12} = b15_b12{0};
6229 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6231 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6233 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6236 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6238 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6242 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6243 bits<2> w_cmode, string asm,
6245 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6247 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6249 (i32 imm:$shift)))]>;
6250 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6252 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6254 (i32 imm:$shift)))]>;
6256 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6258 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6260 (i32 imm:$shift)))]>;
6261 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6263 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6265 (i32 imm:$shift)))]>;
6268 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6269 RegisterOperand vectype, string asm,
6270 string kind, list<dag> pattern>
6271 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6272 (ins move_vec_shift:$shift),
6273 "$shift", asm, kind, pattern> {
6275 let Inst{15-13} = cmode{3-1};
6276 let Inst{12} = shift;
6279 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6280 RegisterOperand vectype,
6281 Operand imm_type, string asm,
6282 string kind, list<dag> pattern>
6283 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6284 asm, kind, pattern> {
6285 let Inst{15-12} = cmode;
6288 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6290 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6291 "\t$Rd, $imm8", "", pattern> {
6292 let Inst{15-12} = cmode;
6293 let DecoderMethod = "DecodeModImmInstruction";
6296 //----------------------------------------------------------------------------
6297 // AdvSIMD indexed element
6298 //----------------------------------------------------------------------------
6300 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6301 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6302 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6303 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6304 string apple_kind, string dst_kind, string lhs_kind,
6305 string rhs_kind, list<dag> pattern>
6306 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6308 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6309 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6318 let Inst{28} = Scalar;
6319 let Inst{27-24} = 0b1111;
6320 let Inst{23-22} = size;
6321 // Bit 21 must be set by the derived class.
6322 let Inst{20-16} = Rm;
6323 let Inst{15-12} = opc;
6324 // Bit 11 must be set by the derived class.
6330 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6331 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6332 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6333 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6334 string apple_kind, string dst_kind, string lhs_kind,
6335 string rhs_kind, list<dag> pattern>
6336 : I<(outs dst_reg:$dst),
6337 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6338 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6339 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6348 let Inst{28} = Scalar;
6349 let Inst{27-24} = 0b1111;
6350 let Inst{23-22} = size;
6351 // Bit 21 must be set by the derived class.
6352 let Inst{20-16} = Rm;
6353 let Inst{15-12} = opc;
6354 // Bit 11 must be set by the derived class.
6360 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
6361 SDPatternOperator OpNode> {
6362 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6365 asm, ".2s", ".2s", ".2s", ".s",
6366 [(set (v2f32 V64:$Rd),
6367 (OpNode (v2f32 V64:$Rn),
6368 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6370 let Inst{11} = idx{1};
6371 let Inst{21} = idx{0};
6374 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6377 asm, ".4s", ".4s", ".4s", ".s",
6378 [(set (v4f32 V128:$Rd),
6379 (OpNode (v4f32 V128:$Rn),
6380 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6382 let Inst{11} = idx{1};
6383 let Inst{21} = idx{0};
6386 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6389 asm, ".2d", ".2d", ".2d", ".d",
6390 [(set (v2f64 V128:$Rd),
6391 (OpNode (v2f64 V128:$Rn),
6392 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6394 let Inst{11} = idx{0};
6398 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6399 FPR32Op, FPR32Op, V128, VectorIndexS,
6400 asm, ".s", "", "", ".s",
6401 [(set (f32 FPR32Op:$Rd),
6402 (OpNode (f32 FPR32Op:$Rn),
6403 (f32 (vector_extract (v4f32 V128:$Rm),
6404 VectorIndexS:$idx))))]> {
6406 let Inst{11} = idx{1};
6407 let Inst{21} = idx{0};
6410 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6411 FPR64Op, FPR64Op, V128, VectorIndexD,
6412 asm, ".d", "", "", ".d",
6413 [(set (f64 FPR64Op:$Rd),
6414 (OpNode (f64 FPR64Op:$Rn),
6415 (f64 (vector_extract (v2f64 V128:$Rm),
6416 VectorIndexD:$idx))))]> {
6418 let Inst{11} = idx{0};
6423 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6424 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6425 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6426 (AArch64duplane32 (v4f32 V128:$Rm),
6427 VectorIndexS:$idx))),
6428 (!cast<Instruction>(INST # v2i32_indexed)
6429 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6430 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6431 (AArch64dup (f32 FPR32Op:$Rm)))),
6432 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6433 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6436 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6437 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6438 (AArch64duplane32 (v4f32 V128:$Rm),
6439 VectorIndexS:$idx))),
6440 (!cast<Instruction>(INST # "v4i32_indexed")
6441 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6442 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6443 (AArch64dup (f32 FPR32Op:$Rm)))),
6444 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6445 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6447 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6448 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6449 (AArch64duplane64 (v2f64 V128:$Rm),
6450 VectorIndexD:$idx))),
6451 (!cast<Instruction>(INST # "v2i64_indexed")
6452 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6453 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6454 (AArch64dup (f64 FPR64Op:$Rm)))),
6455 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6456 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6458 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6459 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6460 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6461 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6462 V128:$Rm, VectorIndexS:$idx)>;
6463 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6464 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6465 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6466 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6468 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6469 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6470 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6471 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6472 V128:$Rm, VectorIndexD:$idx)>;
6475 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6476 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6478 asm, ".2s", ".2s", ".2s", ".s", []> {
6480 let Inst{11} = idx{1};
6481 let Inst{21} = idx{0};
6484 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6487 asm, ".4s", ".4s", ".4s", ".s", []> {
6489 let Inst{11} = idx{1};
6490 let Inst{21} = idx{0};
6493 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6496 asm, ".2d", ".2d", ".2d", ".d", []> {
6498 let Inst{11} = idx{0};
6503 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6504 FPR32Op, FPR32Op, V128, VectorIndexS,
6505 asm, ".s", "", "", ".s", []> {
6507 let Inst{11} = idx{1};
6508 let Inst{21} = idx{0};
6511 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6512 FPR64Op, FPR64Op, V128, VectorIndexD,
6513 asm, ".d", "", "", ".d", []> {
6515 let Inst{11} = idx{0};
6520 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6521 SDPatternOperator OpNode> {
6522 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6523 V128_lo, VectorIndexH,
6524 asm, ".4h", ".4h", ".4h", ".h",
6525 [(set (v4i16 V64:$Rd),
6526 (OpNode (v4i16 V64:$Rn),
6527 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6529 let Inst{11} = idx{2};
6530 let Inst{21} = idx{1};
6531 let Inst{20} = idx{0};
6534 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6536 V128_lo, VectorIndexH,
6537 asm, ".8h", ".8h", ".8h", ".h",
6538 [(set (v8i16 V128:$Rd),
6539 (OpNode (v8i16 V128:$Rn),
6540 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6542 let Inst{11} = idx{2};
6543 let Inst{21} = idx{1};
6544 let Inst{20} = idx{0};
6547 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6550 asm, ".2s", ".2s", ".2s", ".s",
6551 [(set (v2i32 V64:$Rd),
6552 (OpNode (v2i32 V64:$Rn),
6553 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6555 let Inst{11} = idx{1};
6556 let Inst{21} = idx{0};
6559 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6562 asm, ".4s", ".4s", ".4s", ".s",
6563 [(set (v4i32 V128:$Rd),
6564 (OpNode (v4i32 V128:$Rn),
6565 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6567 let Inst{11} = idx{1};
6568 let Inst{21} = idx{0};
6571 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6572 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6573 asm, ".h", "", "", ".h", []> {
6575 let Inst{11} = idx{2};
6576 let Inst{21} = idx{1};
6577 let Inst{20} = idx{0};
6580 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6581 FPR32Op, FPR32Op, V128, VectorIndexS,
6582 asm, ".s", "", "", ".s",
6583 [(set (i32 FPR32Op:$Rd),
6584 (OpNode FPR32Op:$Rn,
6585 (i32 (vector_extract (v4i32 V128:$Rm),
6586 VectorIndexS:$idx))))]> {
6588 let Inst{11} = idx{1};
6589 let Inst{21} = idx{0};
6593 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6594 SDPatternOperator OpNode> {
6595 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6597 V128_lo, VectorIndexH,
6598 asm, ".4h", ".4h", ".4h", ".h",
6599 [(set (v4i16 V64:$Rd),
6600 (OpNode (v4i16 V64:$Rn),
6601 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6603 let Inst{11} = idx{2};
6604 let Inst{21} = idx{1};
6605 let Inst{20} = idx{0};
6608 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6610 V128_lo, VectorIndexH,
6611 asm, ".8h", ".8h", ".8h", ".h",
6612 [(set (v8i16 V128:$Rd),
6613 (OpNode (v8i16 V128:$Rn),
6614 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6616 let Inst{11} = idx{2};
6617 let Inst{21} = idx{1};
6618 let Inst{20} = idx{0};
6621 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6624 asm, ".2s", ".2s", ".2s", ".s",
6625 [(set (v2i32 V64:$Rd),
6626 (OpNode (v2i32 V64:$Rn),
6627 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6629 let Inst{11} = idx{1};
6630 let Inst{21} = idx{0};
6633 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6636 asm, ".4s", ".4s", ".4s", ".s",
6637 [(set (v4i32 V128:$Rd),
6638 (OpNode (v4i32 V128:$Rn),
6639 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6641 let Inst{11} = idx{1};
6642 let Inst{21} = idx{0};
6646 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6647 SDPatternOperator OpNode> {
6648 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6649 V128_lo, VectorIndexH,
6650 asm, ".4h", ".4h", ".4h", ".h",
6651 [(set (v4i16 V64:$dst),
6652 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6653 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6655 let Inst{11} = idx{2};
6656 let Inst{21} = idx{1};
6657 let Inst{20} = idx{0};
6660 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6662 V128_lo, VectorIndexH,
6663 asm, ".8h", ".8h", ".8h", ".h",
6664 [(set (v8i16 V128:$dst),
6665 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6666 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6668 let Inst{11} = idx{2};
6669 let Inst{21} = idx{1};
6670 let Inst{20} = idx{0};
6673 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6676 asm, ".2s", ".2s", ".2s", ".s",
6677 [(set (v2i32 V64:$dst),
6678 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6679 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6681 let Inst{11} = idx{1};
6682 let Inst{21} = idx{0};
6685 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6688 asm, ".4s", ".4s", ".4s", ".s",
6689 [(set (v4i32 V128:$dst),
6690 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6691 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6693 let Inst{11} = idx{1};
6694 let Inst{21} = idx{0};
6698 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6699 SDPatternOperator OpNode> {
6700 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6702 V128_lo, VectorIndexH,
6703 asm, ".4s", ".4s", ".4h", ".h",
6704 [(set (v4i32 V128:$Rd),
6705 (OpNode (v4i16 V64:$Rn),
6706 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6708 let Inst{11} = idx{2};
6709 let Inst{21} = idx{1};
6710 let Inst{20} = idx{0};
6713 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6715 V128_lo, VectorIndexH,
6716 asm#"2", ".4s", ".4s", ".8h", ".h",
6717 [(set (v4i32 V128:$Rd),
6718 (OpNode (extract_high_v8i16 V128:$Rn),
6719 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6720 VectorIndexH:$idx))))]> {
6723 let Inst{11} = idx{2};
6724 let Inst{21} = idx{1};
6725 let Inst{20} = idx{0};
6728 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6731 asm, ".2d", ".2d", ".2s", ".s",
6732 [(set (v2i64 V128:$Rd),
6733 (OpNode (v2i32 V64:$Rn),
6734 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6736 let Inst{11} = idx{1};
6737 let Inst{21} = idx{0};
6740 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6743 asm#"2", ".2d", ".2d", ".4s", ".s",
6744 [(set (v2i64 V128:$Rd),
6745 (OpNode (extract_high_v4i32 V128:$Rn),
6746 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6747 VectorIndexS:$idx))))]> {
6749 let Inst{11} = idx{1};
6750 let Inst{21} = idx{0};
6753 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6754 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6755 asm, ".h", "", "", ".h", []> {
6757 let Inst{11} = idx{2};
6758 let Inst{21} = idx{1};
6759 let Inst{20} = idx{0};
6762 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6763 FPR64Op, FPR32Op, V128, VectorIndexS,
6764 asm, ".s", "", "", ".s", []> {
6766 let Inst{11} = idx{1};
6767 let Inst{21} = idx{0};
6771 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6772 SDPatternOperator Accum> {
6773 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6775 V128_lo, VectorIndexH,
6776 asm, ".4s", ".4s", ".4h", ".h",
6777 [(set (v4i32 V128:$dst),
6778 (Accum (v4i32 V128:$Rd),
6779 (v4i32 (int_aarch64_neon_sqdmull
6781 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6782 VectorIndexH:$idx))))))]> {
6784 let Inst{11} = idx{2};
6785 let Inst{21} = idx{1};
6786 let Inst{20} = idx{0};
6789 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6790 // intermediate EXTRACT_SUBREG would be untyped.
6791 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6792 (i32 (vector_extract (v4i32
6793 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6794 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6795 VectorIndexH:$idx)))),
6798 (!cast<Instruction>(NAME # v4i16_indexed)
6799 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6800 V128_lo:$Rm, VectorIndexH:$idx),
6803 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6805 V128_lo, VectorIndexH,
6806 asm#"2", ".4s", ".4s", ".8h", ".h",
6807 [(set (v4i32 V128:$dst),
6808 (Accum (v4i32 V128:$Rd),
6809 (v4i32 (int_aarch64_neon_sqdmull
6810 (extract_high_v8i16 V128:$Rn),
6812 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6813 VectorIndexH:$idx))))))]> {
6815 let Inst{11} = idx{2};
6816 let Inst{21} = idx{1};
6817 let Inst{20} = idx{0};
6820 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6823 asm, ".2d", ".2d", ".2s", ".s",
6824 [(set (v2i64 V128:$dst),
6825 (Accum (v2i64 V128:$Rd),
6826 (v2i64 (int_aarch64_neon_sqdmull
6828 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
6829 VectorIndexS:$idx))))))]> {
6831 let Inst{11} = idx{1};
6832 let Inst{21} = idx{0};
6835 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6838 asm#"2", ".2d", ".2d", ".4s", ".s",
6839 [(set (v2i64 V128:$dst),
6840 (Accum (v2i64 V128:$Rd),
6841 (v2i64 (int_aarch64_neon_sqdmull
6842 (extract_high_v4i32 V128:$Rn),
6844 (AArch64duplane32 (v4i32 V128:$Rm),
6845 VectorIndexS:$idx))))))]> {
6847 let Inst{11} = idx{1};
6848 let Inst{21} = idx{0};
6851 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6852 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6853 asm, ".h", "", "", ".h", []> {
6855 let Inst{11} = idx{2};
6856 let Inst{21} = idx{1};
6857 let Inst{20} = idx{0};
6861 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6862 FPR64Op, FPR32Op, V128, VectorIndexS,
6863 asm, ".s", "", "", ".s",
6864 [(set (i64 FPR64Op:$dst),
6865 (Accum (i64 FPR64Op:$Rd),
6866 (i64 (int_aarch64_neon_sqdmulls_scalar
6868 (i32 (vector_extract (v4i32 V128:$Rm),
6869 VectorIndexS:$idx))))))]> {
6872 let Inst{11} = idx{1};
6873 let Inst{21} = idx{0};
6877 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6878 SDPatternOperator OpNode> {
6879 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6880 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6882 V128_lo, VectorIndexH,
6883 asm, ".4s", ".4s", ".4h", ".h",
6884 [(set (v4i32 V128:$Rd),
6885 (OpNode (v4i16 V64:$Rn),
6886 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6888 let Inst{11} = idx{2};
6889 let Inst{21} = idx{1};
6890 let Inst{20} = idx{0};
6893 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6895 V128_lo, VectorIndexH,
6896 asm#"2", ".4s", ".4s", ".8h", ".h",
6897 [(set (v4i32 V128:$Rd),
6898 (OpNode (extract_high_v8i16 V128:$Rn),
6899 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6900 VectorIndexH:$idx))))]> {
6903 let Inst{11} = idx{2};
6904 let Inst{21} = idx{1};
6905 let Inst{20} = idx{0};
6908 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6911 asm, ".2d", ".2d", ".2s", ".s",
6912 [(set (v2i64 V128:$Rd),
6913 (OpNode (v2i32 V64:$Rn),
6914 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6916 let Inst{11} = idx{1};
6917 let Inst{21} = idx{0};
6920 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6923 asm#"2", ".2d", ".2d", ".4s", ".s",
6924 [(set (v2i64 V128:$Rd),
6925 (OpNode (extract_high_v4i32 V128:$Rn),
6926 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6927 VectorIndexS:$idx))))]> {
6929 let Inst{11} = idx{1};
6930 let Inst{21} = idx{0};
6935 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6936 SDPatternOperator OpNode> {
6937 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6938 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6940 V128_lo, VectorIndexH,
6941 asm, ".4s", ".4s", ".4h", ".h",
6942 [(set (v4i32 V128:$dst),
6943 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6944 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6946 let Inst{11} = idx{2};
6947 let Inst{21} = idx{1};
6948 let Inst{20} = idx{0};
6951 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6953 V128_lo, VectorIndexH,
6954 asm#"2", ".4s", ".4s", ".8h", ".h",
6955 [(set (v4i32 V128:$dst),
6956 (OpNode (v4i32 V128:$Rd),
6957 (extract_high_v8i16 V128:$Rn),
6958 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6959 VectorIndexH:$idx))))]> {
6961 let Inst{11} = idx{2};
6962 let Inst{21} = idx{1};
6963 let Inst{20} = idx{0};
6966 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6969 asm, ".2d", ".2d", ".2s", ".s",
6970 [(set (v2i64 V128:$dst),
6971 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
6972 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6974 let Inst{11} = idx{1};
6975 let Inst{21} = idx{0};
6978 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6981 asm#"2", ".2d", ".2d", ".4s", ".s",
6982 [(set (v2i64 V128:$dst),
6983 (OpNode (v2i64 V128:$Rd),
6984 (extract_high_v4i32 V128:$Rn),
6985 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6986 VectorIndexS:$idx))))]> {
6988 let Inst{11} = idx{1};
6989 let Inst{21} = idx{0};
6994 //----------------------------------------------------------------------------
6995 // AdvSIMD scalar shift by immediate
6996 //----------------------------------------------------------------------------
6998 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6999 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
7000 RegisterClass regtype1, RegisterClass regtype2,
7001 Operand immtype, string asm, list<dag> pattern>
7002 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7003 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7008 let Inst{31-30} = 0b01;
7010 let Inst{28-23} = 0b111110;
7011 let Inst{22-16} = fixed_imm;
7012 let Inst{15-11} = opc;
7018 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7019 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
7020 RegisterClass regtype1, RegisterClass regtype2,
7021 Operand immtype, string asm, list<dag> pattern>
7022 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7023 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7028 let Inst{31-30} = 0b01;
7030 let Inst{28-23} = 0b111110;
7031 let Inst{22-16} = fixed_imm;
7032 let Inst{15-11} = opc;
7039 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
7040 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7041 FPR32, FPR32, vecshiftR32, asm, []> {
7042 let Inst{20-16} = imm{4-0};
7045 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7046 FPR64, FPR64, vecshiftR64, asm, []> {
7047 let Inst{21-16} = imm{5-0};
7051 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7052 SDPatternOperator OpNode> {
7053 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7054 FPR64, FPR64, vecshiftR64, asm,
7055 [(set (i64 FPR64:$Rd),
7056 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7057 let Inst{21-16} = imm{5-0};
7060 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7061 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7064 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7065 SDPatternOperator OpNode = null_frag> {
7066 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7067 FPR64, FPR64, vecshiftR64, asm,
7068 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7069 (i32 vecshiftR64:$imm)))]> {
7070 let Inst{21-16} = imm{5-0};
7073 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7074 (i32 vecshiftR64:$imm))),
7075 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7079 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7080 SDPatternOperator OpNode> {
7081 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7082 FPR64, FPR64, vecshiftL64, asm,
7083 [(set (v1i64 FPR64:$Rd),
7084 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7085 let Inst{21-16} = imm{5-0};
7089 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7090 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7091 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7092 FPR64, FPR64, vecshiftL64, asm, []> {
7093 let Inst{21-16} = imm{5-0};
7097 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7098 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7099 SDPatternOperator OpNode = null_frag> {
7100 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7101 FPR8, FPR16, vecshiftR8, asm, []> {
7102 let Inst{18-16} = imm{2-0};
7105 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7106 FPR16, FPR32, vecshiftR16, asm, []> {
7107 let Inst{19-16} = imm{3-0};
7110 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7111 FPR32, FPR64, vecshiftR32, asm,
7112 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7113 let Inst{20-16} = imm{4-0};
7117 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7118 SDPatternOperator OpNode> {
7119 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7120 FPR8, FPR8, vecshiftL8, asm, []> {
7121 let Inst{18-16} = imm{2-0};
7124 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7125 FPR16, FPR16, vecshiftL16, asm, []> {
7126 let Inst{19-16} = imm{3-0};
7129 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7130 FPR32, FPR32, vecshiftL32, asm,
7131 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7132 let Inst{20-16} = imm{4-0};
7135 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7136 FPR64, FPR64, vecshiftL64, asm,
7137 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7138 let Inst{21-16} = imm{5-0};
7141 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7142 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7145 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7146 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7147 FPR8, FPR8, vecshiftR8, asm, []> {
7148 let Inst{18-16} = imm{2-0};
7151 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7152 FPR16, FPR16, vecshiftR16, asm, []> {
7153 let Inst{19-16} = imm{3-0};
7156 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7157 FPR32, FPR32, vecshiftR32, asm, []> {
7158 let Inst{20-16} = imm{4-0};
7161 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7162 FPR64, FPR64, vecshiftR64, asm, []> {
7163 let Inst{21-16} = imm{5-0};
7167 //----------------------------------------------------------------------------
7168 // AdvSIMD vector x indexed element
7169 //----------------------------------------------------------------------------
7171 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7172 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7173 RegisterOperand dst_reg, RegisterOperand src_reg,
7175 string asm, string dst_kind, string src_kind,
7177 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7178 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7179 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7186 let Inst{28-23} = 0b011110;
7187 let Inst{22-16} = fixed_imm;
7188 let Inst{15-11} = opc;
7194 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7195 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7196 RegisterOperand vectype1, RegisterOperand vectype2,
7198 string asm, string dst_kind, string src_kind,
7200 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7201 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7202 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7209 let Inst{28-23} = 0b011110;
7210 let Inst{22-16} = fixed_imm;
7211 let Inst{15-11} = opc;
7217 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7219 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7220 V64, V64, vecshiftR32,
7222 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7224 let Inst{20-16} = imm;
7227 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7228 V128, V128, vecshiftR32,
7230 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7232 let Inst{20-16} = imm;
7235 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7236 V128, V128, vecshiftR64,
7238 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7240 let Inst{21-16} = imm;
7244 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7246 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7247 V64, V64, vecshiftR32,
7249 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7251 let Inst{20-16} = imm;
7254 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7255 V128, V128, vecshiftR32,
7257 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7259 let Inst{20-16} = imm;
7262 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7263 V128, V128, vecshiftR64,
7265 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7267 let Inst{21-16} = imm;
7271 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7272 SDPatternOperator OpNode> {
7273 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7274 V64, V128, vecshiftR16Narrow,
7276 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7278 let Inst{18-16} = imm;
7281 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7282 V128, V128, vecshiftR16Narrow,
7283 asm#"2", ".16b", ".8h", []> {
7285 let Inst{18-16} = imm;
7286 let hasSideEffects = 0;
7289 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7290 V64, V128, vecshiftR32Narrow,
7292 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7294 let Inst{19-16} = imm;
7297 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7298 V128, V128, vecshiftR32Narrow,
7299 asm#"2", ".8h", ".4s", []> {
7301 let Inst{19-16} = imm;
7302 let hasSideEffects = 0;
7305 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7306 V64, V128, vecshiftR64Narrow,
7308 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7310 let Inst{20-16} = imm;
7313 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7314 V128, V128, vecshiftR64Narrow,
7315 asm#"2", ".4s", ".2d", []> {
7317 let Inst{20-16} = imm;
7318 let hasSideEffects = 0;
7321 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7322 // themselves, so put them here instead.
7324 // Patterns involving what's effectively an insert high and a normal
7325 // intrinsic, represented by CONCAT_VECTORS.
7326 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7327 vecshiftR16Narrow:$imm)),
7328 (!cast<Instruction>(NAME # "v16i8_shift")
7329 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7330 V128:$Rn, vecshiftR16Narrow:$imm)>;
7331 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7332 vecshiftR32Narrow:$imm)),
7333 (!cast<Instruction>(NAME # "v8i16_shift")
7334 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7335 V128:$Rn, vecshiftR32Narrow:$imm)>;
7336 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7337 vecshiftR64Narrow:$imm)),
7338 (!cast<Instruction>(NAME # "v4i32_shift")
7339 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7340 V128:$Rn, vecshiftR64Narrow:$imm)>;
7343 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7344 SDPatternOperator OpNode> {
7345 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7346 V64, V64, vecshiftL8,
7348 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7349 (i32 vecshiftL8:$imm)))]> {
7351 let Inst{18-16} = imm;
7354 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7355 V128, V128, vecshiftL8,
7356 asm, ".16b", ".16b",
7357 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7358 (i32 vecshiftL8:$imm)))]> {
7360 let Inst{18-16} = imm;
7363 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7364 V64, V64, vecshiftL16,
7366 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7367 (i32 vecshiftL16:$imm)))]> {
7369 let Inst{19-16} = imm;
7372 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7373 V128, V128, vecshiftL16,
7375 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7376 (i32 vecshiftL16:$imm)))]> {
7378 let Inst{19-16} = imm;
7381 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7382 V64, V64, vecshiftL32,
7384 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7385 (i32 vecshiftL32:$imm)))]> {
7387 let Inst{20-16} = imm;
7390 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7391 V128, V128, vecshiftL32,
7393 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7394 (i32 vecshiftL32:$imm)))]> {
7396 let Inst{20-16} = imm;
7399 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7400 V128, V128, vecshiftL64,
7402 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7403 (i32 vecshiftL64:$imm)))]> {
7405 let Inst{21-16} = imm;
7409 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7410 SDPatternOperator OpNode> {
7411 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7412 V64, V64, vecshiftR8,
7414 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7415 (i32 vecshiftR8:$imm)))]> {
7417 let Inst{18-16} = imm;
7420 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7421 V128, V128, vecshiftR8,
7422 asm, ".16b", ".16b",
7423 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7424 (i32 vecshiftR8:$imm)))]> {
7426 let Inst{18-16} = imm;
7429 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7430 V64, V64, vecshiftR16,
7432 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7433 (i32 vecshiftR16:$imm)))]> {
7435 let Inst{19-16} = imm;
7438 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7439 V128, V128, vecshiftR16,
7441 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7442 (i32 vecshiftR16:$imm)))]> {
7444 let Inst{19-16} = imm;
7447 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7448 V64, V64, vecshiftR32,
7450 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7451 (i32 vecshiftR32:$imm)))]> {
7453 let Inst{20-16} = imm;
7456 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7457 V128, V128, vecshiftR32,
7459 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7460 (i32 vecshiftR32:$imm)))]> {
7462 let Inst{20-16} = imm;
7465 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7466 V128, V128, vecshiftR64,
7468 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7469 (i32 vecshiftR64:$imm)))]> {
7471 let Inst{21-16} = imm;
7475 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7476 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7477 SDPatternOperator OpNode = null_frag> {
7478 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7479 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7480 [(set (v8i8 V64:$dst),
7481 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7482 (i32 vecshiftR8:$imm)))]> {
7484 let Inst{18-16} = imm;
7487 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7488 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7489 [(set (v16i8 V128:$dst),
7490 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7491 (i32 vecshiftR8:$imm)))]> {
7493 let Inst{18-16} = imm;
7496 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7497 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7498 [(set (v4i16 V64:$dst),
7499 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7500 (i32 vecshiftR16:$imm)))]> {
7502 let Inst{19-16} = imm;
7505 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7506 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7507 [(set (v8i16 V128:$dst),
7508 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7509 (i32 vecshiftR16:$imm)))]> {
7511 let Inst{19-16} = imm;
7514 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7515 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7516 [(set (v2i32 V64:$dst),
7517 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7518 (i32 vecshiftR32:$imm)))]> {
7520 let Inst{20-16} = imm;
7523 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7524 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7525 [(set (v4i32 V128:$dst),
7526 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7527 (i32 vecshiftR32:$imm)))]> {
7529 let Inst{20-16} = imm;
7532 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7533 V128, V128, vecshiftR64,
7534 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7535 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7536 (i32 vecshiftR64:$imm)))]> {
7538 let Inst{21-16} = imm;
7542 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7543 SDPatternOperator OpNode = null_frag> {
7544 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7545 V64, V64, vecshiftL8,
7547 [(set (v8i8 V64:$dst),
7548 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7549 (i32 vecshiftL8:$imm)))]> {
7551 let Inst{18-16} = imm;
7554 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7555 V128, V128, vecshiftL8,
7556 asm, ".16b", ".16b",
7557 [(set (v16i8 V128:$dst),
7558 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7559 (i32 vecshiftL8:$imm)))]> {
7561 let Inst{18-16} = imm;
7564 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7565 V64, V64, vecshiftL16,
7567 [(set (v4i16 V64:$dst),
7568 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7569 (i32 vecshiftL16:$imm)))]> {
7571 let Inst{19-16} = imm;
7574 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7575 V128, V128, vecshiftL16,
7577 [(set (v8i16 V128:$dst),
7578 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7579 (i32 vecshiftL16:$imm)))]> {
7581 let Inst{19-16} = imm;
7584 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7585 V64, V64, vecshiftL32,
7587 [(set (v2i32 V64:$dst),
7588 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7589 (i32 vecshiftL32:$imm)))]> {
7591 let Inst{20-16} = imm;
7594 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7595 V128, V128, vecshiftL32,
7597 [(set (v4i32 V128:$dst),
7598 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7599 (i32 vecshiftL32:$imm)))]> {
7601 let Inst{20-16} = imm;
7604 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7605 V128, V128, vecshiftL64,
7607 [(set (v2i64 V128:$dst),
7608 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7609 (i32 vecshiftL64:$imm)))]> {
7611 let Inst{21-16} = imm;
7615 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7616 SDPatternOperator OpNode> {
7617 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7618 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7619 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7621 let Inst{18-16} = imm;
7624 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7625 V128, V128, vecshiftL8,
7626 asm#"2", ".8h", ".16b",
7627 [(set (v8i16 V128:$Rd),
7628 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7630 let Inst{18-16} = imm;
7633 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7634 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7635 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7637 let Inst{19-16} = imm;
7640 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7641 V128, V128, vecshiftL16,
7642 asm#"2", ".4s", ".8h",
7643 [(set (v4i32 V128:$Rd),
7644 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7647 let Inst{19-16} = imm;
7650 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7651 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7652 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7654 let Inst{20-16} = imm;
7657 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7658 V128, V128, vecshiftL32,
7659 asm#"2", ".2d", ".4s",
7660 [(set (v2i64 V128:$Rd),
7661 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7663 let Inst{20-16} = imm;
7669 // Vector load/store
7671 // SIMD ldX/stX no-index memory references don't allow the optional
7672 // ", #0" constant and handle post-indexing explicitly, so we use
7673 // a more specialized parse method for them. Otherwise, it's the same as
7674 // the general GPR64sp handling.
7676 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7677 string asm, dag oops, dag iops, list<dag> pattern>
7678 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7683 let Inst{29-23} = 0b0011000;
7685 let Inst{21-16} = 0b000000;
7686 let Inst{15-12} = opcode;
7687 let Inst{11-10} = size;
7692 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7693 string asm, dag oops, dag iops>
7694 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7700 let Inst{29-23} = 0b0011001;
7703 let Inst{20-16} = Xm;
7704 let Inst{15-12} = opcode;
7705 let Inst{11-10} = size;
7710 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7711 // register post-index addressing from the zero register.
7712 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7713 int Offset, int Size> {
7714 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7715 // "ld1\t$Vt, [$Rn], #16"
7716 // may get mapped to
7717 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7718 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7719 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7721 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7724 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7725 // "ld1.8b\t$Vt, [$Rn], #16"
7726 // may get mapped to
7727 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7728 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7729 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7731 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7734 // E.g. "ld1.8b { v0, v1 }, [x1]"
7735 // "ld1\t$Vt, [$Rn]"
7736 // may get mapped to
7737 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7738 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7739 (!cast<Instruction>(NAME # Count # "v" # layout)
7740 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7743 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7744 // "ld1\t$Vt, [$Rn], $Xm"
7745 // may get mapped to
7746 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7747 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7748 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7750 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7751 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7754 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7755 int Offset64, bits<4> opcode> {
7756 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7757 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7758 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7759 (ins GPR64sp:$Rn), []>;
7760 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7761 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7762 (ins GPR64sp:$Rn), []>;
7763 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7764 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7765 (ins GPR64sp:$Rn), []>;
7766 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7767 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7768 (ins GPR64sp:$Rn), []>;
7769 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7770 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7771 (ins GPR64sp:$Rn), []>;
7772 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7773 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7774 (ins GPR64sp:$Rn), []>;
7775 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7776 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7777 (ins GPR64sp:$Rn), []>;
7780 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7781 (outs GPR64sp:$wback,
7782 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7784 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7785 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7786 (outs GPR64sp:$wback,
7787 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7789 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7790 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7791 (outs GPR64sp:$wback,
7792 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7794 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7795 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7796 (outs GPR64sp:$wback,
7797 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7799 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7800 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7801 (outs GPR64sp:$wback,
7802 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7804 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7805 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7806 (outs GPR64sp:$wback,
7807 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7809 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7810 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7811 (outs GPR64sp:$wback,
7812 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7814 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7817 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7818 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7819 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7820 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7821 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7822 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7823 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7826 // Only ld1/st1 has a v1d version.
7827 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7828 int Offset64, bits<4> opcode> {
7829 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7830 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7831 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7833 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7834 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7836 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7837 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7839 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7840 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7842 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7843 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7845 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7846 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7848 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7849 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7852 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7853 (outs GPR64sp:$wback),
7854 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7856 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7857 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7858 (outs GPR64sp:$wback),
7859 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7861 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7862 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7863 (outs GPR64sp:$wback),
7864 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7866 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7867 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7868 (outs GPR64sp:$wback),
7869 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7871 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7872 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7873 (outs GPR64sp:$wback),
7874 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7876 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7877 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7878 (outs GPR64sp:$wback),
7879 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7881 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7882 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7883 (outs GPR64sp:$wback),
7884 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7886 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7889 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7890 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7891 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7892 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7893 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7894 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7895 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7898 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7899 int Offset128, int Offset64, bits<4> opcode>
7900 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7902 // LD1 instructions have extra "1d" variants.
7903 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7904 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7905 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7906 (ins GPR64sp:$Rn), []>;
7908 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7909 (outs GPR64sp:$wback,
7910 !cast<RegisterOperand>(veclist # "1d"):$Vt),
7912 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7915 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7918 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7919 int Offset128, int Offset64, bits<4> opcode>
7920 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7922 // ST1 instructions have extra "1d" variants.
7923 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7924 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7925 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7928 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
7929 (outs GPR64sp:$wback),
7930 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7932 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7935 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7938 multiclass SIMDLd1Multiple<string asm> {
7939 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7940 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7941 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7942 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7945 multiclass SIMDSt1Multiple<string asm> {
7946 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7947 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7948 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7949 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7952 multiclass SIMDLd2Multiple<string asm> {
7953 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7956 multiclass SIMDSt2Multiple<string asm> {
7957 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7960 multiclass SIMDLd3Multiple<string asm> {
7961 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7964 multiclass SIMDSt3Multiple<string asm> {
7965 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7968 multiclass SIMDLd4Multiple<string asm> {
7969 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7972 multiclass SIMDSt4Multiple<string asm> {
7973 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7977 // AdvSIMD Load/store single-element
7980 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
7981 string asm, string operands, string cst,
7982 dag oops, dag iops, list<dag> pattern>
7983 : I<oops, iops, asm, operands, cst, pattern> {
7987 let Inst{29-24} = 0b001101;
7990 let Inst{15-13} = opcode;
7995 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
7996 string asm, string operands, string cst,
7997 dag oops, dag iops, list<dag> pattern>
7998 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
8002 let Inst{29-24} = 0b001101;
8005 let Inst{15-13} = opcode;
8011 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8012 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
8014 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8015 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8019 let Inst{20-16} = 0b00000;
8021 let Inst{11-10} = size;
8023 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8024 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
8025 string asm, Operand listtype, Operand GPR64pi>
8026 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8028 (outs GPR64sp:$wback, listtype:$Vt),
8029 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
8033 let Inst{20-16} = Xm;
8035 let Inst{11-10} = size;
8038 multiclass SIMDLdrAliases<string asm, string layout, string Count,
8039 int Offset, int Size> {
8040 // E.g. "ld1r { v0.8b }, [x1], #1"
8041 // "ld1r.8b\t$Vt, [$Rn], #1"
8042 // may get mapped to
8043 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8044 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8045 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8047 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8050 // E.g. "ld1r.8b { v0 }, [x1], #1"
8051 // "ld1r.8b\t$Vt, [$Rn], #1"
8052 // may get mapped to
8053 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8054 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8055 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8057 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8060 // E.g. "ld1r.8b { v0 }, [x1]"
8061 // "ld1r.8b\t$Vt, [$Rn]"
8062 // may get mapped to
8063 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8064 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8065 (!cast<Instruction>(NAME # "v" # layout)
8066 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8069 // E.g. "ld1r.8b { v0 }, [x1], x2"
8070 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8071 // may get mapped to
8072 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8073 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8074 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8076 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8077 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8080 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8081 int Offset1, int Offset2, int Offset4, int Offset8> {
8082 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8083 !cast<Operand>("VecList" # Count # "8b")>;
8084 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8085 !cast<Operand>("VecList" # Count #"16b")>;
8086 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8087 !cast<Operand>("VecList" # Count #"4h")>;
8088 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8089 !cast<Operand>("VecList" # Count #"8h")>;
8090 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8091 !cast<Operand>("VecList" # Count #"2s")>;
8092 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8093 !cast<Operand>("VecList" # Count #"4s")>;
8094 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8095 !cast<Operand>("VecList" # Count #"1d")>;
8096 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8097 !cast<Operand>("VecList" # Count #"2d")>;
8099 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8100 !cast<Operand>("VecList" # Count # "8b"),
8101 !cast<Operand>("GPR64pi" # Offset1)>;
8102 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8103 !cast<Operand>("VecList" # Count # "16b"),
8104 !cast<Operand>("GPR64pi" # Offset1)>;
8105 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8106 !cast<Operand>("VecList" # Count # "4h"),
8107 !cast<Operand>("GPR64pi" # Offset2)>;
8108 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8109 !cast<Operand>("VecList" # Count # "8h"),
8110 !cast<Operand>("GPR64pi" # Offset2)>;
8111 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8112 !cast<Operand>("VecList" # Count # "2s"),
8113 !cast<Operand>("GPR64pi" # Offset4)>;
8114 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8115 !cast<Operand>("VecList" # Count # "4s"),
8116 !cast<Operand>("GPR64pi" # Offset4)>;
8117 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8118 !cast<Operand>("VecList" # Count # "1d"),
8119 !cast<Operand>("GPR64pi" # Offset8)>;
8120 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8121 !cast<Operand>("VecList" # Count # "2d"),
8122 !cast<Operand>("GPR64pi" # Offset8)>;
8124 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8125 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8126 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8127 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8128 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8129 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8130 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8131 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8134 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8135 dag oops, dag iops, list<dag> pattern>
8136 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8138 // idx encoded in Q:S:size fields.
8140 let Inst{30} = idx{3};
8142 let Inst{20-16} = 0b00000;
8143 let Inst{12} = idx{2};
8144 let Inst{11-10} = idx{1-0};
8146 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8147 dag oops, dag iops, list<dag> pattern>
8148 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8149 oops, iops, pattern> {
8150 // idx encoded in Q:S:size fields.
8152 let Inst{30} = idx{3};
8154 let Inst{20-16} = 0b00000;
8155 let Inst{12} = idx{2};
8156 let Inst{11-10} = idx{1-0};
8158 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8160 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8161 "$Rn = $wback", oops, iops, []> {
8162 // idx encoded in Q:S:size fields.
8165 let Inst{30} = idx{3};
8167 let Inst{20-16} = Xm;
8168 let Inst{12} = idx{2};
8169 let Inst{11-10} = idx{1-0};
8171 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8173 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8174 "$Rn = $wback", oops, iops, []> {
8175 // idx encoded in Q:S:size fields.
8178 let Inst{30} = idx{3};
8180 let Inst{20-16} = Xm;
8181 let Inst{12} = idx{2};
8182 let Inst{11-10} = idx{1-0};
8185 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8186 dag oops, dag iops, list<dag> pattern>
8187 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8189 // idx encoded in Q:S:size<1> fields.
8191 let Inst{30} = idx{2};
8193 let Inst{20-16} = 0b00000;
8194 let Inst{12} = idx{1};
8195 let Inst{11} = idx{0};
8196 let Inst{10} = size;
8198 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8199 dag oops, dag iops, list<dag> pattern>
8200 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8201 oops, iops, pattern> {
8202 // idx encoded in Q:S:size<1> fields.
8204 let Inst{30} = idx{2};
8206 let Inst{20-16} = 0b00000;
8207 let Inst{12} = idx{1};
8208 let Inst{11} = idx{0};
8209 let Inst{10} = size;
8212 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8214 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8215 "$Rn = $wback", oops, iops, []> {
8216 // idx encoded in Q:S:size<1> fields.
8219 let Inst{30} = idx{2};
8221 let Inst{20-16} = Xm;
8222 let Inst{12} = idx{1};
8223 let Inst{11} = idx{0};
8224 let Inst{10} = size;
8226 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8228 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8229 "$Rn = $wback", oops, iops, []> {
8230 // idx encoded in Q:S:size<1> fields.
8233 let Inst{30} = idx{2};
8235 let Inst{20-16} = Xm;
8236 let Inst{12} = idx{1};
8237 let Inst{11} = idx{0};
8238 let Inst{10} = size;
8240 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8241 dag oops, dag iops, list<dag> pattern>
8242 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8244 // idx encoded in Q:S fields.
8246 let Inst{30} = idx{1};
8248 let Inst{20-16} = 0b00000;
8249 let Inst{12} = idx{0};
8250 let Inst{11-10} = size;
8252 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8253 dag oops, dag iops, list<dag> pattern>
8254 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8255 oops, iops, pattern> {
8256 // idx encoded in Q:S fields.
8258 let Inst{30} = idx{1};
8260 let Inst{20-16} = 0b00000;
8261 let Inst{12} = idx{0};
8262 let Inst{11-10} = size;
8264 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8265 string asm, dag oops, dag iops>
8266 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8267 "$Rn = $wback", oops, iops, []> {
8268 // idx encoded in Q:S fields.
8271 let Inst{30} = idx{1};
8273 let Inst{20-16} = Xm;
8274 let Inst{12} = idx{0};
8275 let Inst{11-10} = size;
8277 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8278 string asm, dag oops, dag iops>
8279 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8280 "$Rn = $wback", oops, iops, []> {
8281 // idx encoded in Q:S fields.
8284 let Inst{30} = idx{1};
8286 let Inst{20-16} = Xm;
8287 let Inst{12} = idx{0};
8288 let Inst{11-10} = size;
8290 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8291 dag oops, dag iops, list<dag> pattern>
8292 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8294 // idx encoded in Q field.
8298 let Inst{20-16} = 0b00000;
8300 let Inst{11-10} = size;
8302 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8303 dag oops, dag iops, list<dag> pattern>
8304 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8305 oops, iops, pattern> {
8306 // idx encoded in Q field.
8310 let Inst{20-16} = 0b00000;
8312 let Inst{11-10} = size;
8314 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8315 string asm, dag oops, dag iops>
8316 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8317 "$Rn = $wback", oops, iops, []> {
8318 // idx encoded in Q field.
8323 let Inst{20-16} = Xm;
8325 let Inst{11-10} = size;
8327 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8328 string asm, dag oops, dag iops>
8329 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8330 "$Rn = $wback", oops, iops, []> {
8331 // idx encoded in Q field.
8336 let Inst{20-16} = Xm;
8338 let Inst{11-10} = size;
8341 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8342 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8343 RegisterOperand listtype,
8344 RegisterOperand GPR64pi> {
8345 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8346 (outs listtype:$dst),
8347 (ins listtype:$Vt, VectorIndexB:$idx,
8350 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8351 (outs GPR64sp:$wback, listtype:$dst),
8352 (ins listtype:$Vt, VectorIndexB:$idx,
8353 GPR64sp:$Rn, GPR64pi:$Xm)>;
8355 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8356 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8357 RegisterOperand listtype,
8358 RegisterOperand GPR64pi> {
8359 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8360 (outs listtype:$dst),
8361 (ins listtype:$Vt, VectorIndexH:$idx,
8364 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8365 (outs GPR64sp:$wback, listtype:$dst),
8366 (ins listtype:$Vt, VectorIndexH:$idx,
8367 GPR64sp:$Rn, GPR64pi:$Xm)>;
8369 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8370 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8371 RegisterOperand listtype,
8372 RegisterOperand GPR64pi> {
8373 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8374 (outs listtype:$dst),
8375 (ins listtype:$Vt, VectorIndexS:$idx,
8378 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8379 (outs GPR64sp:$wback, listtype:$dst),
8380 (ins listtype:$Vt, VectorIndexS:$idx,
8381 GPR64sp:$Rn, GPR64pi:$Xm)>;
8383 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8384 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8385 RegisterOperand listtype, RegisterOperand GPR64pi> {
8386 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8387 (outs listtype:$dst),
8388 (ins listtype:$Vt, VectorIndexD:$idx,
8391 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8392 (outs GPR64sp:$wback, listtype:$dst),
8393 (ins listtype:$Vt, VectorIndexD:$idx,
8394 GPR64sp:$Rn, GPR64pi:$Xm)>;
8396 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8397 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8398 RegisterOperand listtype, RegisterOperand GPR64pi> {
8399 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8400 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8403 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8404 (outs GPR64sp:$wback),
8405 (ins listtype:$Vt, VectorIndexB:$idx,
8406 GPR64sp:$Rn, GPR64pi:$Xm)>;
8408 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8409 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8410 RegisterOperand listtype, RegisterOperand GPR64pi> {
8411 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8412 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8415 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8416 (outs GPR64sp:$wback),
8417 (ins listtype:$Vt, VectorIndexH:$idx,
8418 GPR64sp:$Rn, GPR64pi:$Xm)>;
8420 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8421 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8422 RegisterOperand listtype, RegisterOperand GPR64pi> {
8423 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8424 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8427 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8428 (outs GPR64sp:$wback),
8429 (ins listtype:$Vt, VectorIndexS:$idx,
8430 GPR64sp:$Rn, GPR64pi:$Xm)>;
8432 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8433 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8434 RegisterOperand listtype, RegisterOperand GPR64pi> {
8435 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8436 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8439 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8440 (outs GPR64sp:$wback),
8441 (ins listtype:$Vt, VectorIndexD:$idx,
8442 GPR64sp:$Rn, GPR64pi:$Xm)>;
8445 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8446 string Count, int Offset, Operand idxtype> {
8447 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8448 // "ld1\t$Vt, [$Rn], #1"
8449 // may get mapped to
8450 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8451 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8452 (!cast<Instruction>(NAME # Type # "_POST")
8454 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8455 idxtype:$idx, XZR), 1>;
8457 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8458 // "ld1.8b\t$Vt, [$Rn], #1"
8459 // may get mapped to
8460 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8461 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8462 (!cast<Instruction>(NAME # Type # "_POST")
8464 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8465 idxtype:$idx, XZR), 0>;
8467 // E.g. "ld1.8b { v0 }[0], [x1]"
8468 // "ld1.8b\t$Vt, [$Rn]"
8469 // may get mapped to
8470 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8471 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8472 (!cast<Instruction>(NAME # Type)
8473 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8474 idxtype:$idx, GPR64sp:$Rn), 0>;
8476 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8477 // "ld1.8b\t$Vt, [$Rn], $Xm"
8478 // may get mapped to
8479 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8480 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8481 (!cast<Instruction>(NAME # Type # "_POST")
8483 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8485 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8488 multiclass SIMDLdSt1SingleAliases<string asm> {
8489 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8490 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8491 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8492 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8495 multiclass SIMDLdSt2SingleAliases<string asm> {
8496 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8497 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8498 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8499 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8502 multiclass SIMDLdSt3SingleAliases<string asm> {
8503 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8504 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8505 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8506 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8509 multiclass SIMDLdSt4SingleAliases<string asm> {
8510 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8511 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8512 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8513 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8515 } // end of 'let Predicates = [HasNEON]'
8517 //----------------------------------------------------------------------------
8518 // Crypto extensions
8519 //----------------------------------------------------------------------------
8521 let Predicates = [HasCrypto] in {
8522 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8523 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8525 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8529 let Inst{31-16} = 0b0100111000101000;
8530 let Inst{15-12} = opc;
8531 let Inst{11-10} = 0b10;
8536 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8537 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8538 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8540 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8541 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8543 [(set (v16i8 V128:$dst),
8544 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8546 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8547 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8548 dag oops, dag iops, list<dag> pat>
8549 : I<oops, iops, asm,
8550 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8551 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8556 let Inst{31-21} = 0b01011110000;
8557 let Inst{20-16} = Rm;
8559 let Inst{14-12} = opc;
8560 let Inst{11-10} = 0b00;
8565 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8566 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8567 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8568 [(set (v4i32 FPR128:$dst),
8569 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8570 (v4i32 V128:$Rm)))]>;
8572 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8573 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8574 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8575 [(set (v4i32 V128:$dst),
8576 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8577 (v4i32 V128:$Rm)))]>;
8579 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8580 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8581 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8582 [(set (v4i32 FPR128:$dst),
8583 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8584 (v4i32 V128:$Rm)))]>;
8586 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8587 class SHA2OpInst<bits<4> opc, string asm, string kind,
8588 string cstr, dag oops, dag iops,
8590 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8591 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8595 let Inst{31-16} = 0b0101111000101000;
8596 let Inst{15-12} = opc;
8597 let Inst{11-10} = 0b10;
8602 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8603 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8604 (ins V128:$Rd, V128:$Rn),
8605 [(set (v4i32 V128:$dst),
8606 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8608 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8609 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8610 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8611 } // end of 'let Predicates = [HasCrypto]'
8613 // Allow the size specifier tokens to be upper case, not just lower.
8614 def : TokenAlias<".8B", ".8b">;
8615 def : TokenAlias<".4H", ".4h">;
8616 def : TokenAlias<".2S", ".2s">;
8617 def : TokenAlias<".1D", ".1d">;
8618 def : TokenAlias<".16B", ".16b">;
8619 def : TokenAlias<".8H", ".8h">;
8620 def : TokenAlias<".4S", ".4s">;
8621 def : TokenAlias<".2D", ".2d">;
8622 def : TokenAlias<".1Q", ".1q">;
8623 def : TokenAlias<".B", ".b">;
8624 def : TokenAlias<".H", ".h">;
8625 def : TokenAlias<".S", ".s">;
8626 def : TokenAlias<".D", ".d">;
8627 def : TokenAlias<".Q", ".q">;