1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 class AsmImmRange<int Low, int High> : AsmOperandClass {
252 let Name = "Imm" # Low # "_" # High;
253 let DiagnosticType = "InvalidImm" # Low # "_" # High;
256 def Imm1_8Operand : AsmImmRange<1, 8>;
257 def Imm1_16Operand : AsmImmRange<1, 16>;
258 def Imm1_32Operand : AsmImmRange<1, 32>;
259 def Imm1_64Operand : AsmImmRange<1, 64>;
261 def MovZSymbolG3AsmOperand : AsmOperandClass {
262 let Name = "MovZSymbolG3";
263 let RenderMethod = "addImmOperands";
266 def movz_symbol_g3 : Operand<i32> {
267 let ParserMatchClass = MovZSymbolG3AsmOperand;
270 def MovZSymbolG2AsmOperand : AsmOperandClass {
271 let Name = "MovZSymbolG2";
272 let RenderMethod = "addImmOperands";
275 def movz_symbol_g2 : Operand<i32> {
276 let ParserMatchClass = MovZSymbolG2AsmOperand;
279 def MovZSymbolG1AsmOperand : AsmOperandClass {
280 let Name = "MovZSymbolG1";
281 let RenderMethod = "addImmOperands";
284 def movz_symbol_g1 : Operand<i32> {
285 let ParserMatchClass = MovZSymbolG1AsmOperand;
288 def MovZSymbolG0AsmOperand : AsmOperandClass {
289 let Name = "MovZSymbolG0";
290 let RenderMethod = "addImmOperands";
293 def movz_symbol_g0 : Operand<i32> {
294 let ParserMatchClass = MovZSymbolG0AsmOperand;
297 def MovKSymbolG3AsmOperand : AsmOperandClass {
298 let Name = "MovKSymbolG3";
299 let RenderMethod = "addImmOperands";
302 def movk_symbol_g3 : Operand<i32> {
303 let ParserMatchClass = MovKSymbolG3AsmOperand;
306 def MovKSymbolG2AsmOperand : AsmOperandClass {
307 let Name = "MovKSymbolG2";
308 let RenderMethod = "addImmOperands";
311 def movk_symbol_g2 : Operand<i32> {
312 let ParserMatchClass = MovKSymbolG2AsmOperand;
315 def MovKSymbolG1AsmOperand : AsmOperandClass {
316 let Name = "MovKSymbolG1";
317 let RenderMethod = "addImmOperands";
320 def movk_symbol_g1 : Operand<i32> {
321 let ParserMatchClass = MovKSymbolG1AsmOperand;
324 def MovKSymbolG0AsmOperand : AsmOperandClass {
325 let Name = "MovKSymbolG0";
326 let RenderMethod = "addImmOperands";
329 def movk_symbol_g0 : Operand<i32> {
330 let ParserMatchClass = MovKSymbolG0AsmOperand;
333 class fixedpoint_i32<ValueType FloatVT>
335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
336 let EncoderMethod = "getFixedPointScaleOpValue";
337 let DecoderMethod = "DecodeFixedPointScaleImm32";
338 let ParserMatchClass = Imm1_32Operand;
341 class fixedpoint_i64<ValueType FloatVT>
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
344 let EncoderMethod = "getFixedPointScaleOpValue";
345 let DecoderMethod = "DecodeFixedPointScaleImm64";
346 let ParserMatchClass = Imm1_64Operand;
349 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
350 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
352 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
353 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
355 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
358 let EncoderMethod = "getVecShiftR8OpValue";
359 let DecoderMethod = "DecodeVecShiftR8Imm";
360 let ParserMatchClass = Imm1_8Operand;
362 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
363 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
365 let EncoderMethod = "getVecShiftR16OpValue";
366 let DecoderMethod = "DecodeVecShiftR16Imm";
367 let ParserMatchClass = Imm1_16Operand;
369 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
370 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
372 let EncoderMethod = "getVecShiftR16OpValue";
373 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
374 let ParserMatchClass = Imm1_8Operand;
376 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
377 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
379 let EncoderMethod = "getVecShiftR32OpValue";
380 let DecoderMethod = "DecodeVecShiftR32Imm";
381 let ParserMatchClass = Imm1_32Operand;
383 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
384 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
386 let EncoderMethod = "getVecShiftR32OpValue";
387 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
388 let ParserMatchClass = Imm1_16Operand;
390 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
391 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
393 let EncoderMethod = "getVecShiftR64OpValue";
394 let DecoderMethod = "DecodeVecShiftR64Imm";
395 let ParserMatchClass = Imm1_64Operand;
397 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
398 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
400 let EncoderMethod = "getVecShiftR64OpValue";
401 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
402 let ParserMatchClass = Imm1_32Operand;
405 def Imm0_7Operand : AsmImmRange<0, 7>;
406 def Imm0_15Operand : AsmImmRange<0, 15>;
407 def Imm0_31Operand : AsmImmRange<0, 31>;
408 def Imm0_63Operand : AsmImmRange<0, 63>;
410 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
411 return (((uint32_t)Imm) < 8);
413 let EncoderMethod = "getVecShiftL8OpValue";
414 let DecoderMethod = "DecodeVecShiftL8Imm";
415 let ParserMatchClass = Imm0_7Operand;
417 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
418 return (((uint32_t)Imm) < 16);
420 let EncoderMethod = "getVecShiftL16OpValue";
421 let DecoderMethod = "DecodeVecShiftL16Imm";
422 let ParserMatchClass = Imm0_15Operand;
424 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
425 return (((uint32_t)Imm) < 32);
427 let EncoderMethod = "getVecShiftL32OpValue";
428 let DecoderMethod = "DecodeVecShiftL32Imm";
429 let ParserMatchClass = Imm0_31Operand;
431 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
432 return (((uint32_t)Imm) < 64);
434 let EncoderMethod = "getVecShiftL64OpValue";
435 let DecoderMethod = "DecodeVecShiftL64Imm";
436 let ParserMatchClass = Imm0_63Operand;
440 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
441 // instructions for splatting repeating bit patterns across the immediate.
442 def logical_imm32_XFORM : SDNodeXForm<imm, [{
443 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
444 return CurDAG->getTargetConstant(enc, MVT::i32);
446 def logical_imm64_XFORM : SDNodeXForm<imm, [{
447 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
448 return CurDAG->getTargetConstant(enc, MVT::i32);
451 def LogicalImm32Operand : AsmOperandClass {
452 let Name = "LogicalImm32";
453 let DiagnosticType = "LogicalSecondSource";
455 def LogicalImm64Operand : AsmOperandClass {
456 let Name = "LogicalImm64";
457 let DiagnosticType = "LogicalSecondSource";
459 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
460 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
461 }], logical_imm32_XFORM> {
462 let PrintMethod = "printLogicalImm32";
463 let ParserMatchClass = LogicalImm32Operand;
465 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
466 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
467 }], logical_imm64_XFORM> {
468 let PrintMethod = "printLogicalImm64";
469 let ParserMatchClass = LogicalImm64Operand;
472 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
473 def Imm0_65535Operand : AsmImmRange<0, 65535>;
474 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
475 return ((uint32_t)Imm) < 65536;
477 let ParserMatchClass = Imm0_65535Operand;
478 let PrintMethod = "printHexImm";
481 // imm0_255 predicate - True if the immediate is in the range [0,255].
482 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
483 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
484 return ((uint32_t)Imm) < 256;
486 let ParserMatchClass = Imm0_255Operand;
487 let PrintMethod = "printHexImm";
490 // imm0_127 predicate - True if the immediate is in the range [0,127]
491 def Imm0_127Operand : AsmImmRange<0, 127>;
492 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
493 return ((uint32_t)Imm) < 128;
495 let ParserMatchClass = Imm0_127Operand;
496 let PrintMethod = "printHexImm";
499 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
500 // for all shift-amounts.
502 // imm0_63 predicate - True if the immediate is in the range [0,63]
503 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
504 return ((uint64_t)Imm) < 64;
506 let ParserMatchClass = Imm0_63Operand;
509 // imm0_31 predicate - True if the immediate is in the range [0,31]
510 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
511 return ((uint64_t)Imm) < 32;
513 let ParserMatchClass = Imm0_31Operand;
516 // imm0_15 predicate - True if the immediate is in the range [0,15]
517 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
518 return ((uint64_t)Imm) < 16;
520 let ParserMatchClass = Imm0_15Operand;
523 // imm0_7 predicate - True if the immediate is in the range [0,7]
524 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
525 return ((uint64_t)Imm) < 8;
527 let ParserMatchClass = Imm0_7Operand;
530 // An arithmetic shifter operand:
531 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
533 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
534 let PrintMethod = "printShifter";
535 let ParserMatchClass = !cast<AsmOperandClass>(
536 "ArithmeticShifterOperand" # width);
539 def arith_shift32 : arith_shift<i32, 32>;
540 def arith_shift64 : arith_shift<i64, 64>;
542 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
544 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
545 let PrintMethod = "printShiftedRegister";
546 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
549 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
550 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
552 // An arithmetic shifter operand:
553 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
555 class logical_shift<int width> : Operand<i32> {
556 let PrintMethod = "printShifter";
557 let ParserMatchClass = !cast<AsmOperandClass>(
558 "LogicalShifterOperand" # width);
561 def logical_shift32 : logical_shift<32>;
562 def logical_shift64 : logical_shift<64>;
564 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
566 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
567 let PrintMethod = "printShiftedRegister";
568 let MIOperandInfo = (ops regclass, shiftop);
571 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
572 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
574 // A logical vector shifter operand:
575 // {7-6} - shift type: 00 = lsl
576 // {5-0} - imm6: #0, #8, #16, or #24
577 def logical_vec_shift : Operand<i32> {
578 let PrintMethod = "printShifter";
579 let EncoderMethod = "getVecShifterOpValue";
580 let ParserMatchClass = LogicalVecShifterOperand;
583 // A logical vector half-word shifter operand:
584 // {7-6} - shift type: 00 = lsl
585 // {5-0} - imm6: #0 or #8
586 def logical_vec_hw_shift : Operand<i32> {
587 let PrintMethod = "printShifter";
588 let EncoderMethod = "getVecShifterOpValue";
589 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
592 // A vector move shifter operand:
593 // {0} - imm1: #8 or #16
594 def move_vec_shift : Operand<i32> {
595 let PrintMethod = "printShifter";
596 let EncoderMethod = "getMoveVecShifterOpValue";
597 let ParserMatchClass = MoveVecShifterOperand;
600 def AddSubImmOperand : AsmOperandClass {
601 let Name = "AddSubImm";
602 let ParserMethod = "tryParseAddSubImm";
603 let DiagnosticType = "AddSubSecondSource";
605 // An ADD/SUB immediate shifter operand:
607 // {7-6} - shift type: 00 = lsl
608 // {5-0} - imm6: #0 or #12
609 class addsub_shifted_imm<ValueType Ty>
610 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
611 let PrintMethod = "printAddSubImm";
612 let EncoderMethod = "getAddSubImmOpValue";
613 let ParserMatchClass = AddSubImmOperand;
614 let MIOperandInfo = (ops i32imm, i32imm);
617 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
618 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
620 class neg_addsub_shifted_imm<ValueType Ty>
621 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
622 let PrintMethod = "printAddSubImm";
623 let EncoderMethod = "getAddSubImmOpValue";
624 let ParserMatchClass = AddSubImmOperand;
625 let MIOperandInfo = (ops i32imm, i32imm);
628 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
629 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
631 // An extend operand:
632 // {5-3} - extend type
634 def arith_extend : Operand<i32> {
635 let PrintMethod = "printArithExtend";
636 let ParserMatchClass = ExtendOperand;
638 def arith_extend64 : Operand<i32> {
639 let PrintMethod = "printArithExtend";
640 let ParserMatchClass = ExtendOperand64;
643 // 'extend' that's a lsl of a 64-bit register.
644 def arith_extendlsl64 : Operand<i32> {
645 let PrintMethod = "printArithExtend";
646 let ParserMatchClass = ExtendOperandLSL64;
649 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
650 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
651 let PrintMethod = "printExtendedRegister";
652 let MIOperandInfo = (ops GPR32, arith_extend);
655 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
656 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
657 let PrintMethod = "printExtendedRegister";
658 let MIOperandInfo = (ops GPR32, arith_extend64);
661 // Floating-point immediate.
662 def fpimm32 : Operand<f32>,
663 PatLeaf<(f32 fpimm), [{
664 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
665 }], SDNodeXForm<fpimm, [{
666 APFloat InVal = N->getValueAPF();
667 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
668 return CurDAG->getTargetConstant(enc, MVT::i32);
670 let ParserMatchClass = FPImmOperand;
671 let PrintMethod = "printFPImmOperand";
673 def fpimm64 : Operand<f64>,
674 PatLeaf<(f64 fpimm), [{
675 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
676 }], SDNodeXForm<fpimm, [{
677 APFloat InVal = N->getValueAPF();
678 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
679 return CurDAG->getTargetConstant(enc, MVT::i32);
681 let ParserMatchClass = FPImmOperand;
682 let PrintMethod = "printFPImmOperand";
685 def fpimm8 : Operand<i32> {
686 let ParserMatchClass = FPImmOperand;
687 let PrintMethod = "printFPImmOperand";
690 def fpimm0 : PatLeaf<(fpimm), [{
691 return N->isExactlyValue(+0.0);
694 // Vector lane operands
695 class AsmVectorIndex<string Suffix> : AsmOperandClass {
696 let Name = "VectorIndex" # Suffix;
697 let DiagnosticType = "InvalidIndex" # Suffix;
699 def VectorIndex1Operand : AsmVectorIndex<"1">;
700 def VectorIndexBOperand : AsmVectorIndex<"B">;
701 def VectorIndexHOperand : AsmVectorIndex<"H">;
702 def VectorIndexSOperand : AsmVectorIndex<"S">;
703 def VectorIndexDOperand : AsmVectorIndex<"D">;
705 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
706 return ((uint64_t)Imm) == 1;
708 let ParserMatchClass = VectorIndex1Operand;
709 let PrintMethod = "printVectorIndex";
710 let MIOperandInfo = (ops i64imm);
712 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
713 return ((uint64_t)Imm) < 16;
715 let ParserMatchClass = VectorIndexBOperand;
716 let PrintMethod = "printVectorIndex";
717 let MIOperandInfo = (ops i64imm);
719 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
720 return ((uint64_t)Imm) < 8;
722 let ParserMatchClass = VectorIndexHOperand;
723 let PrintMethod = "printVectorIndex";
724 let MIOperandInfo = (ops i64imm);
726 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
727 return ((uint64_t)Imm) < 4;
729 let ParserMatchClass = VectorIndexSOperand;
730 let PrintMethod = "printVectorIndex";
731 let MIOperandInfo = (ops i64imm);
733 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
734 return ((uint64_t)Imm) < 2;
736 let ParserMatchClass = VectorIndexDOperand;
737 let PrintMethod = "printVectorIndex";
738 let MIOperandInfo = (ops i64imm);
741 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
742 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
743 // are encoded as the eight bit value 'abcdefgh'.
744 def simdimmtype10 : Operand<i32>,
745 PatLeaf<(f64 fpimm), [{
746 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
749 }], SDNodeXForm<fpimm, [{
750 APFloat InVal = N->getValueAPF();
751 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
754 return CurDAG->getTargetConstant(enc, MVT::i32);
756 let ParserMatchClass = SIMDImmType10Operand;
757 let PrintMethod = "printSIMDType10Operand";
765 // Base encoding for system instruction operands.
766 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
767 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands>
768 : I<oops, iops, asm, operands, "", []> {
769 let Inst{31-22} = 0b1101010100;
773 // System instructions which do not have an Rt register.
774 class SimpleSystemI<bit L, dag iops, string asm, string operands>
775 : BaseSystemI<L, (outs), iops, asm, operands> {
776 let Inst{4-0} = 0b11111;
779 // System instructions which have an Rt register.
780 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
781 : BaseSystemI<L, oops, iops, asm, operands>,
787 // Hint instructions that take both a CRm and a 3-bit immediate.
788 class HintI<string mnemonic>
789 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
792 let Inst{20-12} = 0b000110010;
793 let Inst{11-5} = imm;
796 // System instructions taking a single literal operand which encodes into
797 // CRm. op2 differentiates the opcodes.
798 def BarrierAsmOperand : AsmOperandClass {
799 let Name = "Barrier";
800 let ParserMethod = "tryParseBarrierOperand";
802 def barrier_op : Operand<i32> {
803 let PrintMethod = "printBarrierOption";
804 let ParserMatchClass = BarrierAsmOperand;
806 class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
807 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm">,
808 Sched<[WriteBarrier]> {
810 let Inst{20-12} = 0b000110011;
811 let Inst{11-8} = CRm;
815 // MRS/MSR system instructions. These have different operand classes because
816 // a different subset of registers can be accessed through each instruction.
817 def MRSSystemRegisterOperand : AsmOperandClass {
818 let Name = "MRSSystemRegister";
819 let ParserMethod = "tryParseSysReg";
820 let DiagnosticType = "MRS";
822 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
823 def mrs_sysreg_op : Operand<i32> {
824 let ParserMatchClass = MRSSystemRegisterOperand;
825 let DecoderMethod = "DecodeMRSSystemRegister";
826 let PrintMethod = "printMRSSystemRegister";
829 def MSRSystemRegisterOperand : AsmOperandClass {
830 let Name = "MSRSystemRegister";
831 let ParserMethod = "tryParseSysReg";
832 let DiagnosticType = "MSR";
834 def msr_sysreg_op : Operand<i32> {
835 let ParserMatchClass = MSRSystemRegisterOperand;
836 let DecoderMethod = "DecodeMSRSystemRegister";
837 let PrintMethod = "printMSRSystemRegister";
840 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
841 "mrs", "\t$Rt, $systemreg"> {
844 let Inst{19-5} = systemreg;
847 // FIXME: Some of these def NZCV, others don't. Best way to model that?
848 // Explicitly modeling each of the system register as a register class
849 // would do it, but feels like overkill at this point.
850 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
851 "msr", "\t$systemreg, $Rt"> {
854 let Inst{19-5} = systemreg;
857 def SystemPStateFieldOperand : AsmOperandClass {
858 let Name = "SystemPStateField";
859 let ParserMethod = "tryParseSysReg";
861 def pstatefield_op : Operand<i32> {
862 let ParserMatchClass = SystemPStateFieldOperand;
863 let PrintMethod = "printSystemPStateField";
868 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
869 "msr", "\t$pstate_field, $imm">,
873 let Inst{20-19} = 0b00;
874 let Inst{18-16} = pstatefield{5-3};
875 let Inst{15-12} = 0b0100;
876 let Inst{11-8} = imm;
877 let Inst{7-5} = pstatefield{2-0};
879 let DecoderMethod = "DecodeSystemPStateInstruction";
882 // SYS and SYSL generic system instructions.
883 def SysCRAsmOperand : AsmOperandClass {
885 let ParserMethod = "tryParseSysCROperand";
888 def sys_cr_op : Operand<i32> {
889 let PrintMethod = "printSysCROperand";
890 let ParserMatchClass = SysCRAsmOperand;
893 class SystemXtI<bit L, string asm>
894 : RtSystemI<L, (outs),
895 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
896 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
901 let Inst{20-19} = 0b01;
902 let Inst{18-16} = op1;
903 let Inst{15-12} = Cn;
908 class SystemLXtI<bit L, string asm>
909 : RtSystemI<L, (outs),
910 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
911 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
916 let Inst{20-19} = 0b01;
917 let Inst{18-16} = op1;
918 let Inst{15-12} = Cn;
924 // Branch (register) instructions:
932 // otherwise UNDEFINED
933 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
934 string operands, list<dag> pattern>
935 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
936 let Inst{31-25} = 0b1101011;
937 let Inst{24-21} = opc;
938 let Inst{20-16} = 0b11111;
939 let Inst{15-10} = 0b000000;
940 let Inst{4-0} = 0b00000;
943 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
944 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
949 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
950 class SpecialReturn<bits<4> opc, string asm>
951 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
952 let Inst{9-5} = 0b11111;
956 // Conditional branch instruction.
960 // 4-bit immediate. Pretty-printed as <cc>
961 def ccode : Operand<i32> {
962 let PrintMethod = "printCondCode";
963 let ParserMatchClass = CondCode;
965 def inv_ccode : Operand<i32> {
966 let PrintMethod = "printInverseCondCode";
967 let ParserMatchClass = CondCode;
970 // Conditional branch target. 19-bit immediate. The low two bits of the target
971 // offset are implied zero and so are not part of the immediate.
972 def PCRelLabel19Operand : AsmOperandClass {
973 let Name = "PCRelLabel19";
974 let DiagnosticType = "InvalidLabel";
976 def am_brcond : Operand<OtherVT> {
977 let EncoderMethod = "getCondBranchTargetOpValue";
978 let DecoderMethod = "DecodePCRelLabel19";
979 let PrintMethod = "printAlignedLabel";
980 let ParserMatchClass = PCRelLabel19Operand;
983 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
984 "b", ".$cond\t$target", "",
985 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
988 let isTerminator = 1;
993 let Inst{31-24} = 0b01010100;
994 let Inst{23-5} = target;
996 let Inst{3-0} = cond;
1000 // Compare-and-branch instructions.
1002 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1003 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1004 asm, "\t$Rt, $target", "",
1005 [(node regtype:$Rt, bb:$target)]>,
1008 let isTerminator = 1;
1012 let Inst{30-25} = 0b011010;
1014 let Inst{23-5} = target;
1018 multiclass CmpBranch<bit op, string asm, SDNode node> {
1019 def W : BaseCmpBranch<GPR32, op, asm, node> {
1022 def X : BaseCmpBranch<GPR64, op, asm, node> {
1028 // Test-bit-and-branch instructions.
1030 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1031 // the target offset are implied zero and so are not part of the immediate.
1032 def BranchTarget14Operand : AsmOperandClass {
1033 let Name = "BranchTarget14";
1035 def am_tbrcond : Operand<OtherVT> {
1036 let EncoderMethod = "getTestBranchTargetOpValue";
1037 let PrintMethod = "printAlignedLabel";
1038 let ParserMatchClass = BranchTarget14Operand;
1041 // AsmOperand classes to emit (or not) special diagnostics
1042 def TBZImm0_31Operand : AsmOperandClass {
1043 let Name = "TBZImm0_31";
1044 let PredicateMethod = "isImm0_31";
1045 let RenderMethod = "addImm0_31Operands";
1047 def TBZImm32_63Operand : AsmOperandClass {
1048 let Name = "Imm32_63";
1049 let DiagnosticType = "InvalidImm0_63";
1052 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1053 return (((uint32_t)Imm) < 32);
1055 let ParserMatchClass = matcher;
1058 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1059 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1061 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1062 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1064 let ParserMatchClass = TBZImm32_63Operand;
1067 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1068 bit op, string asm, SDNode node>
1069 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1070 asm, "\t$Rt, $bit_off, $target", "",
1071 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1074 let isTerminator = 1;
1080 let Inst{30-25} = 0b011011;
1082 let Inst{23-19} = bit_off{4-0};
1083 let Inst{18-5} = target;
1086 let DecoderMethod = "DecodeTestAndBranch";
1089 multiclass TestBranch<bit op, string asm, SDNode node> {
1090 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1094 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1098 // Alias X-reg with 0-31 imm to W-Reg.
1099 def : InstAlias<asm # "\t$Rd, $imm, $target",
1100 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1101 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1102 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1103 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1104 tbz_imm0_31_diag:$imm, bb:$target)>;
1108 // Unconditional branch (immediate) instructions.
1110 def BranchTarget26Operand : AsmOperandClass {
1111 let Name = "BranchTarget26";
1112 let DiagnosticType = "InvalidLabel";
1114 def am_b_target : Operand<OtherVT> {
1115 let EncoderMethod = "getBranchTargetOpValue";
1116 let PrintMethod = "printAlignedLabel";
1117 let ParserMatchClass = BranchTarget26Operand;
1119 def am_bl_target : Operand<i64> {
1120 let EncoderMethod = "getBranchTargetOpValue";
1121 let PrintMethod = "printAlignedLabel";
1122 let ParserMatchClass = BranchTarget26Operand;
1125 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1126 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1129 let Inst{30-26} = 0b00101;
1130 let Inst{25-0} = addr;
1132 let DecoderMethod = "DecodeUnconditionalBranch";
1135 class BranchImm<bit op, string asm, list<dag> pattern>
1136 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1137 class CallImm<bit op, string asm, list<dag> pattern>
1138 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1141 // Basic one-operand data processing instructions.
1144 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1145 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1146 SDPatternOperator node>
1147 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1148 [(set regtype:$Rd, (node regtype:$Rn))]>,
1149 Sched<[WriteI, ReadI]> {
1153 let Inst{30-13} = 0b101101011000000000;
1154 let Inst{12-10} = opc;
1159 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1160 multiclass OneOperandData<bits<3> opc, string asm,
1161 SDPatternOperator node = null_frag> {
1162 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1166 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1171 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1172 : BaseOneOperandData<opc, GPR32, asm, node> {
1176 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1177 : BaseOneOperandData<opc, GPR64, asm, node> {
1182 // Basic two-operand data processing instructions.
1184 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1186 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1187 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1188 Sched<[WriteI, ReadI, ReadI]> {
1193 let Inst{30} = isSub;
1194 let Inst{28-21} = 0b11010000;
1195 let Inst{20-16} = Rm;
1196 let Inst{15-10} = 0;
1201 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1203 : BaseBaseAddSubCarry<isSub, regtype, asm,
1204 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1206 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1208 : BaseBaseAddSubCarry<isSub, regtype, asm,
1209 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1214 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1215 SDNode OpNode, SDNode OpNode_setflags> {
1216 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1220 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1226 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1231 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1238 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1239 SDPatternOperator OpNode>
1240 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1241 asm, "\t$Rd, $Rn, $Rm", "",
1242 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1246 let Inst{30-21} = 0b0011010110;
1247 let Inst{20-16} = Rm;
1248 let Inst{15-14} = 0b00;
1249 let Inst{13-10} = opc;
1254 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1255 SDPatternOperator OpNode>
1256 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1257 let Inst{10} = isSigned;
1260 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1261 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1262 Sched<[WriteID32, ReadID, ReadID]> {
1265 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1266 Sched<[WriteID64, ReadID, ReadID]> {
1271 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1272 SDPatternOperator OpNode = null_frag>
1273 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1274 Sched<[WriteIS, ReadI]> {
1275 let Inst{11-10} = shift_type;
1278 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1279 def Wr : BaseShift<shift_type, GPR32, asm> {
1283 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1287 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1288 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1289 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1291 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1292 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1294 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1295 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1297 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1298 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1301 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1302 : InstAlias<asm#" $dst, $src1, $src2",
1303 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1305 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1306 RegisterClass addtype, string asm,
1308 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1309 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1314 let Inst{30-24} = 0b0011011;
1315 let Inst{23-21} = opc;
1316 let Inst{20-16} = Rm;
1317 let Inst{15} = isSub;
1318 let Inst{14-10} = Ra;
1323 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1324 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1325 [(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
1326 Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> {
1330 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1331 [(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
1332 Sched<[WriteIM64, ReadIMA, ReadIM, ReadIM]> {
1337 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1338 SDNode AccNode, SDNode ExtNode>
1339 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1340 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1341 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1342 Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> {
1346 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1347 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1348 asm, "\t$Rd, $Rn, $Rm", "",
1349 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1350 Sched<[WriteIM64, ReadIM, ReadIM]> {
1354 let Inst{31-24} = 0b10011011;
1355 let Inst{23-21} = opc;
1356 let Inst{20-16} = Rm;
1361 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1362 // (i.e. all bits 1) but is ignored by the processor.
1363 let PostEncoderMethod = "fixMulHigh";
1366 class MulAccumWAlias<string asm, Instruction inst>
1367 : InstAlias<asm#" $dst, $src1, $src2",
1368 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1369 class MulAccumXAlias<string asm, Instruction inst>
1370 : InstAlias<asm#" $dst, $src1, $src2",
1371 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1372 class WideMulAccumAlias<string asm, Instruction inst>
1373 : InstAlias<asm#" $dst, $src1, $src2",
1374 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1376 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1377 SDPatternOperator OpNode, string asm>
1378 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1379 asm, "\t$Rd, $Rn, $Rm", "",
1380 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1381 Sched<[WriteISReg, ReadI, ReadISReg]> {
1387 let Inst{30-21} = 0b0011010110;
1388 let Inst{20-16} = Rm;
1389 let Inst{15-13} = 0b010;
1391 let Inst{11-10} = sz;
1394 let Predicates = [HasCRC];
1398 // Address generation.
1401 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1402 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1407 let Inst{31} = page;
1408 let Inst{30-29} = label{1-0};
1409 let Inst{28-24} = 0b10000;
1410 let Inst{23-5} = label{20-2};
1413 let DecoderMethod = "DecodeAdrInstruction";
1420 def movimm32_imm : Operand<i32> {
1421 let ParserMatchClass = Imm0_65535Operand;
1422 let EncoderMethod = "getMoveWideImmOpValue";
1423 let PrintMethod = "printHexImm";
1425 def movimm32_shift : Operand<i32> {
1426 let PrintMethod = "printShifter";
1427 let ParserMatchClass = MovImm32ShifterOperand;
1429 def movimm64_shift : Operand<i32> {
1430 let PrintMethod = "printShifter";
1431 let ParserMatchClass = MovImm64ShifterOperand;
1434 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1435 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1437 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1438 asm, "\t$Rd, $imm$shift", "", []>,
1443 let Inst{30-29} = opc;
1444 let Inst{28-23} = 0b100101;
1445 let Inst{22-21} = shift{5-4};
1446 let Inst{20-5} = imm;
1449 let DecoderMethod = "DecodeMoveImmInstruction";
1452 multiclass MoveImmediate<bits<2> opc, string asm> {
1453 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1457 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1462 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1463 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1465 : I<(outs regtype:$Rd),
1466 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1467 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1468 Sched<[WriteI, ReadI]> {
1472 let Inst{30-29} = opc;
1473 let Inst{28-23} = 0b100101;
1474 let Inst{22-21} = shift{5-4};
1475 let Inst{20-5} = imm;
1478 let DecoderMethod = "DecodeMoveImmInstruction";
1481 multiclass InsertImmediate<bits<2> opc, string asm> {
1482 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1486 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1495 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1496 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1497 string asm, SDPatternOperator OpNode>
1498 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1499 asm, "\t$Rd, $Rn, $imm", "",
1500 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1501 Sched<[WriteI, ReadI]> {
1505 let Inst{30} = isSub;
1506 let Inst{29} = setFlags;
1507 let Inst{28-24} = 0b10001;
1508 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1509 let Inst{21-10} = imm{11-0};
1512 let DecoderMethod = "DecodeBaseAddSubImm";
1515 class BaseAddSubRegPseudo<RegisterClass regtype,
1516 SDPatternOperator OpNode>
1517 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1518 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1519 Sched<[WriteI, ReadI, ReadI]>;
1521 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1522 arith_shifted_reg shifted_regtype, string asm,
1523 SDPatternOperator OpNode>
1524 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1525 asm, "\t$Rd, $Rn, $Rm", "",
1526 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1527 Sched<[WriteISReg, ReadI, ReadISReg]> {
1528 // The operands are in order to match the 'addr' MI operands, so we
1529 // don't need an encoder method and by-name matching. Just use the default
1530 // in-order handling. Since we're using by-order, make sure the names
1536 let Inst{30} = isSub;
1537 let Inst{29} = setFlags;
1538 let Inst{28-24} = 0b01011;
1539 let Inst{23-22} = shift{7-6};
1541 let Inst{20-16} = src2;
1542 let Inst{15-10} = shift{5-0};
1543 let Inst{9-5} = src1;
1544 let Inst{4-0} = dst;
1546 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1549 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1550 RegisterClass src1Regtype, Operand src2Regtype,
1551 string asm, SDPatternOperator OpNode>
1552 : I<(outs dstRegtype:$R1),
1553 (ins src1Regtype:$R2, src2Regtype:$R3),
1554 asm, "\t$R1, $R2, $R3", "",
1555 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1556 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1561 let Inst{30} = isSub;
1562 let Inst{29} = setFlags;
1563 let Inst{28-24} = 0b01011;
1564 let Inst{23-21} = 0b001;
1565 let Inst{20-16} = Rm;
1566 let Inst{15-13} = ext{5-3};
1567 let Inst{12-10} = ext{2-0};
1571 let DecoderMethod = "DecodeAddSubERegInstruction";
1574 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1575 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1576 RegisterClass src1Regtype, RegisterClass src2Regtype,
1577 Operand ext_op, string asm>
1578 : I<(outs dstRegtype:$Rd),
1579 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1580 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1581 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1586 let Inst{30} = isSub;
1587 let Inst{29} = setFlags;
1588 let Inst{28-24} = 0b01011;
1589 let Inst{23-21} = 0b001;
1590 let Inst{20-16} = Rm;
1591 let Inst{15} = ext{5};
1592 let Inst{12-10} = ext{2-0};
1596 let DecoderMethod = "DecodeAddSubERegInstruction";
1599 // Aliases for register+register add/subtract.
1600 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1601 RegisterClass src1Regtype, RegisterClass src2Regtype,
1603 : InstAlias<asm#" $dst, $src1, $src2",
1604 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1607 multiclass AddSub<bit isSub, string mnemonic,
1608 SDPatternOperator OpNode = null_frag> {
1609 let hasSideEffects = 0 in {
1610 // Add/Subtract immediate
1611 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1615 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1620 // Add/Subtract register - Only used for CodeGen
1621 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1622 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1624 // Add/Subtract shifted register
1625 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1629 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1635 // Add/Subtract extended register
1636 let AddedComplexity = 1, hasSideEffects = 0 in {
1637 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1638 arith_extended_reg32<i32>, mnemonic, OpNode> {
1641 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1642 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1647 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1648 arith_extendlsl64, mnemonic> {
1649 // UXTX and SXTX only.
1650 let Inst{14-13} = 0b11;
1654 // Register/register aliases with no shift when SP is not used.
1655 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1656 GPR32, GPR32, GPR32, 0>;
1657 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1658 GPR64, GPR64, GPR64, 0>;
1660 // Register/register aliases with no shift when either the destination or
1661 // first source register is SP.
1662 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1663 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1664 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1665 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1666 def : AddSubRegAlias<mnemonic,
1667 !cast<Instruction>(NAME#"Xrx64"),
1668 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1669 def : AddSubRegAlias<mnemonic,
1670 !cast<Instruction>(NAME#"Xrx64"),
1671 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1674 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
1675 let isCompare = 1, Defs = [NZCV] in {
1676 // Add/Subtract immediate
1677 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1681 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1686 // Add/Subtract register
1687 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1688 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1690 // Add/Subtract shifted register
1691 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1695 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1700 // Add/Subtract extended register
1701 let AddedComplexity = 1 in {
1702 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1703 arith_extended_reg32<i32>, mnemonic, OpNode> {
1706 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1707 arith_extended_reg32<i64>, mnemonic, OpNode> {
1712 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1713 arith_extendlsl64, mnemonic> {
1714 // UXTX and SXTX only.
1715 let Inst{14-13} = 0b11;
1721 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Wri")
1722 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1723 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Xri")
1724 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1725 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1726 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1727 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1728 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1729 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1730 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1731 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1732 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1733 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1734 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1736 // Compare shorthands
1737 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1738 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1739 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1740 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1742 // Register/register aliases with no shift when SP is not used.
1743 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1744 GPR32, GPR32, GPR32, 0>;
1745 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1746 GPR64, GPR64, GPR64, 0>;
1748 // Register/register aliases with no shift when the first source register
1750 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1751 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1752 def : AddSubRegAlias<mnemonic,
1753 !cast<Instruction>(NAME#"Xrx64"),
1754 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1760 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1762 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1764 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1766 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1767 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1768 Sched<[WriteExtr, ReadExtrHi]> {
1774 let Inst{30-23} = 0b00100111;
1776 let Inst{20-16} = Rm;
1777 let Inst{15-10} = imm;
1782 multiclass ExtractImm<string asm> {
1783 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1785 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1788 // imm<5> must be zero.
1791 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1793 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1804 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1805 class BaseBitfieldImm<bits<2> opc,
1806 RegisterClass regtype, Operand imm_type, string asm>
1807 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1808 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1809 Sched<[WriteIS, ReadI]> {
1815 let Inst{30-29} = opc;
1816 let Inst{28-23} = 0b100110;
1817 let Inst{21-16} = immr;
1818 let Inst{15-10} = imms;
1823 multiclass BitfieldImm<bits<2> opc, string asm> {
1824 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1827 // imms<5> and immr<5> must be zero, else ReservedValue().
1831 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1837 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1838 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1839 RegisterClass regtype, Operand imm_type, string asm>
1840 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1842 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1843 Sched<[WriteIS, ReadI]> {
1849 let Inst{30-29} = opc;
1850 let Inst{28-23} = 0b100110;
1851 let Inst{21-16} = immr;
1852 let Inst{15-10} = imms;
1857 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1858 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1861 // imms<5> and immr<5> must be zero, else ReservedValue().
1865 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1875 // Logical (immediate)
1876 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1877 RegisterClass sregtype, Operand imm_type, string asm,
1879 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1880 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1881 Sched<[WriteI, ReadI]> {
1885 let Inst{30-29} = opc;
1886 let Inst{28-23} = 0b100100;
1887 let Inst{22} = imm{12};
1888 let Inst{21-16} = imm{11-6};
1889 let Inst{15-10} = imm{5-0};
1893 let DecoderMethod = "DecodeLogicalImmInstruction";
1896 // Logical (shifted register)
1897 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1898 logical_shifted_reg shifted_regtype, string asm,
1900 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1901 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1902 Sched<[WriteISReg, ReadI, ReadISReg]> {
1903 // The operands are in order to match the 'addr' MI operands, so we
1904 // don't need an encoder method and by-name matching. Just use the default
1905 // in-order handling. Since we're using by-order, make sure the names
1911 let Inst{30-29} = opc;
1912 let Inst{28-24} = 0b01010;
1913 let Inst{23-22} = shift{7-6};
1915 let Inst{20-16} = src2;
1916 let Inst{15-10} = shift{5-0};
1917 let Inst{9-5} = src1;
1918 let Inst{4-0} = dst;
1920 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1923 // Aliases for register+register logical instructions.
1924 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1925 : InstAlias<asm#" $dst, $src1, $src2",
1926 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1928 let AddedComplexity = 6 in
1929 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode> {
1930 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1931 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1932 logical_imm32:$imm))]> {
1934 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1936 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1937 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1938 logical_imm64:$imm))]> {
1943 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
1944 let isCompare = 1, Defs = [NZCV] in {
1945 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1946 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1948 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1950 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
1951 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
1954 } // end Defs = [NZCV]
1957 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
1958 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1959 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1960 Sched<[WriteI, ReadI, ReadI]>;
1962 // Split from LogicalImm as not all instructions have both.
1963 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
1964 SDPatternOperator OpNode> {
1965 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1966 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1968 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1969 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
1970 logical_shifted_reg32:$Rm))]> {
1973 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
1974 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
1975 logical_shifted_reg64:$Rm))]> {
1979 def : LogicalRegAlias<mnemonic,
1980 !cast<Instruction>(NAME#"Wrs"), GPR32>;
1981 def : LogicalRegAlias<mnemonic,
1982 !cast<Instruction>(NAME#"Xrs"), GPR64>;
1985 // Split from LogicalReg to allow setting NZCV Defs
1986 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
1987 SDPatternOperator OpNode = null_frag> {
1988 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1989 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1990 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1992 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1993 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
1996 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
1997 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2002 def : LogicalRegAlias<mnemonic,
2003 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2004 def : LogicalRegAlias<mnemonic,
2005 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2009 // Conditionally set flags
2012 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2013 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
2014 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
2015 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
2016 Sched<[WriteI, ReadI]> {
2026 let Inst{29-21} = 0b111010010;
2027 let Inst{20-16} = imm;
2028 let Inst{15-12} = cond;
2029 let Inst{11-10} = 0b10;
2032 let Inst{3-0} = nzcv;
2035 multiclass CondSetFlagsImm<bit op, string asm> {
2036 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
2039 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
2044 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2045 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
2046 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
2047 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
2048 Sched<[WriteI, ReadI, ReadI]> {
2058 let Inst{29-21} = 0b111010010;
2059 let Inst{20-16} = Rm;
2060 let Inst{15-12} = cond;
2061 let Inst{11-10} = 0b00;
2064 let Inst{3-0} = nzcv;
2067 multiclass CondSetFlagsReg<bit op, string asm> {
2068 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
2071 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
2077 // Conditional select
2080 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2081 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2082 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2084 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2085 Sched<[WriteI, ReadI, ReadI]> {
2094 let Inst{29-21} = 0b011010100;
2095 let Inst{20-16} = Rm;
2096 let Inst{15-12} = cond;
2097 let Inst{11-10} = op2;
2102 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2103 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2106 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2111 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2113 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2114 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2116 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2117 (i32 imm:$cond), NZCV))]>,
2118 Sched<[WriteI, ReadI, ReadI]> {
2127 let Inst{29-21} = 0b011010100;
2128 let Inst{20-16} = Rm;
2129 let Inst{15-12} = cond;
2130 let Inst{11-10} = op2;
2135 def inv_cond_XFORM : SDNodeXForm<imm, [{
2136 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2137 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), MVT::i32);
2140 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2141 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2144 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2148 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2149 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2150 (inv_cond_XFORM imm:$cond))>;
2152 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2153 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2154 (inv_cond_XFORM imm:$cond))>;
2158 // Special Mask Value
2160 def maski8_or_more : Operand<i32>,
2161 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2163 def maski16_or_more : Operand<i32>,
2164 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2172 // (unsigned immediate)
2173 // Indexed for 8-bit registers. offset is in range [0,4095].
2174 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2175 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2176 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2177 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2178 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2180 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2181 let Name = "UImm12Offset" # Scale;
2182 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2183 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2184 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2187 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2188 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2189 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2190 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2191 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2193 class uimm12_scaled<int Scale> : Operand<i64> {
2194 let ParserMatchClass
2195 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2197 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2198 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2201 def uimm12s1 : uimm12_scaled<1>;
2202 def uimm12s2 : uimm12_scaled<2>;
2203 def uimm12s4 : uimm12_scaled<4>;
2204 def uimm12s8 : uimm12_scaled<8>;
2205 def uimm12s16 : uimm12_scaled<16>;
2207 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2208 string asm, list<dag> pattern>
2209 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2215 let Inst{31-30} = sz;
2216 let Inst{29-27} = 0b111;
2218 let Inst{25-24} = 0b01;
2219 let Inst{23-22} = opc;
2220 let Inst{21-10} = offset;
2224 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2227 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2228 Operand indextype, string asm, list<dag> pattern> {
2229 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2230 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2231 (ins GPR64sp:$Rn, indextype:$offset),
2235 def : InstAlias<asm # " $Rt, [$Rn]",
2236 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2239 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2240 Operand indextype, string asm, list<dag> pattern> {
2241 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2242 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2243 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2247 def : InstAlias<asm # " $Rt, [$Rn]",
2248 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2251 def PrefetchOperand : AsmOperandClass {
2252 let Name = "Prefetch";
2253 let ParserMethod = "tryParsePrefetch";
2255 def prfop : Operand<i32> {
2256 let PrintMethod = "printPrefetchOp";
2257 let ParserMatchClass = PrefetchOperand;
2260 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2261 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2262 : BaseLoadStoreUI<sz, V, opc,
2263 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2271 // Load literal address: 19-bit immediate. The low two bits of the target
2272 // offset are implied zero and so are not part of the immediate.
2273 def am_ldrlit : Operand<OtherVT> {
2274 let EncoderMethod = "getLoadLiteralOpValue";
2275 let DecoderMethod = "DecodePCRelLabel19";
2276 let PrintMethod = "printAlignedLabel";
2277 let ParserMatchClass = PCRelLabel19Operand;
2280 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2281 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2282 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2283 asm, "\t$Rt, $label", "", []>,
2287 let Inst{31-30} = opc;
2288 let Inst{29-27} = 0b011;
2290 let Inst{25-24} = 0b00;
2291 let Inst{23-5} = label;
2295 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2296 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2297 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2298 asm, "\t$Rt, $label", "", pat>,
2302 let Inst{31-30} = opc;
2303 let Inst{29-27} = 0b011;
2305 let Inst{25-24} = 0b00;
2306 let Inst{23-5} = label;
2311 // Load/store register offset
2314 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2315 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2316 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2317 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2318 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2320 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2321 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2322 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2323 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2324 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2326 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2327 let Name = "Mem" # Reg # "Extend" # Width;
2328 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2329 let RenderMethod = "addMemExtendOperands";
2330 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2333 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2334 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2335 // the trivial shift.
2336 let RenderMethod = "addMemExtend8Operands";
2338 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2339 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2340 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2341 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2343 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2344 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2345 // the trivial shift.
2346 let RenderMethod = "addMemExtend8Operands";
2348 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2349 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2350 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2351 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2353 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2355 let ParserMatchClass = ParserClass;
2356 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2357 let DecoderMethod = "DecodeMemExtend";
2358 let EncoderMethod = "getMemExtendOpValue";
2359 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2362 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2363 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2364 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2365 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2366 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2368 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2369 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2370 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2371 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2372 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2374 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2375 Operand wextend, Operand xextend> {
2376 // CodeGen-level pattern covering the entire addressing mode.
2377 ComplexPattern Wpat = windex;
2378 ComplexPattern Xpat = xindex;
2380 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2381 Operand Wext = wextend;
2382 Operand Xext = xextend;
2385 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2386 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2387 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2388 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2389 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2392 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2393 string asm, dag ins, dag outs, list<dag> pat>
2394 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2399 let Inst{31-30} = sz;
2400 let Inst{29-27} = 0b111;
2402 let Inst{25-24} = 0b00;
2403 let Inst{23-22} = opc;
2405 let Inst{20-16} = Rm;
2406 let Inst{15} = extend{1}; // sign extend Rm?
2408 let Inst{12} = extend{0}; // do shift?
2409 let Inst{11-10} = 0b10;
2414 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2415 : InstAlias<asm # " $Rt, [$Rn, $Rm]",
2416 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2418 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2419 string asm, ValueType Ty, SDPatternOperator loadop> {
2420 let AddedComplexity = 10 in
2421 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2423 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2424 [(set (Ty regtype:$Rt),
2425 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2426 ro_Wextend8:$extend)))]>,
2427 Sched<[WriteLDIdx, ReadAdrBase]> {
2431 let AddedComplexity = 10 in
2432 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2434 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2435 [(set (Ty regtype:$Rt),
2436 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2437 ro_Xextend8:$extend)))]>,
2438 Sched<[WriteLDIdx, ReadAdrBase]> {
2442 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2445 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2446 string asm, ValueType Ty, SDPatternOperator storeop> {
2447 let AddedComplexity = 10 in
2448 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2449 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2450 [(storeop (Ty regtype:$Rt),
2451 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2452 ro_Wextend8:$extend))]>,
2453 Sched<[WriteSTIdx, ReadAdrBase]> {
2457 let AddedComplexity = 10 in
2458 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2459 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2460 [(storeop (Ty regtype:$Rt),
2461 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2462 ro_Xextend8:$extend))]>,
2463 Sched<[WriteSTIdx, ReadAdrBase]> {
2467 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2470 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2471 string asm, dag ins, dag outs, list<dag> pat>
2472 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2477 let Inst{31-30} = sz;
2478 let Inst{29-27} = 0b111;
2480 let Inst{25-24} = 0b00;
2481 let Inst{23-22} = opc;
2483 let Inst{20-16} = Rm;
2484 let Inst{15} = extend{1}; // sign extend Rm?
2486 let Inst{12} = extend{0}; // do shift?
2487 let Inst{11-10} = 0b10;
2492 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2493 string asm, ValueType Ty, SDPatternOperator loadop> {
2494 let AddedComplexity = 10 in
2495 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2496 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2497 [(set (Ty regtype:$Rt),
2498 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2499 ro_Wextend16:$extend)))]>,
2500 Sched<[WriteLDIdx, ReadAdrBase]> {
2504 let AddedComplexity = 10 in
2505 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2506 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2507 [(set (Ty regtype:$Rt),
2508 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2509 ro_Xextend16:$extend)))]>,
2510 Sched<[WriteLDIdx, ReadAdrBase]> {
2514 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2517 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2518 string asm, ValueType Ty, SDPatternOperator storeop> {
2519 let AddedComplexity = 10 in
2520 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2521 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2522 [(storeop (Ty regtype:$Rt),
2523 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2524 ro_Wextend16:$extend))]>,
2525 Sched<[WriteSTIdx, ReadAdrBase]> {
2529 let AddedComplexity = 10 in
2530 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2531 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2532 [(storeop (Ty regtype:$Rt),
2533 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2534 ro_Xextend16:$extend))]>,
2535 Sched<[WriteSTIdx, ReadAdrBase]> {
2539 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2542 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2543 string asm, dag ins, dag outs, list<dag> pat>
2544 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2549 let Inst{31-30} = sz;
2550 let Inst{29-27} = 0b111;
2552 let Inst{25-24} = 0b00;
2553 let Inst{23-22} = opc;
2555 let Inst{20-16} = Rm;
2556 let Inst{15} = extend{1}; // sign extend Rm?
2558 let Inst{12} = extend{0}; // do shift?
2559 let Inst{11-10} = 0b10;
2564 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2565 string asm, ValueType Ty, SDPatternOperator loadop> {
2566 let AddedComplexity = 10 in
2567 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2568 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2569 [(set (Ty regtype:$Rt),
2570 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2571 ro_Wextend32:$extend)))]>,
2572 Sched<[WriteLDIdx, ReadAdrBase]> {
2576 let AddedComplexity = 10 in
2577 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2578 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2579 [(set (Ty regtype:$Rt),
2580 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2581 ro_Xextend32:$extend)))]>,
2582 Sched<[WriteLDIdx, ReadAdrBase]> {
2586 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2589 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2590 string asm, ValueType Ty, SDPatternOperator storeop> {
2591 let AddedComplexity = 10 in
2592 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2593 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2594 [(storeop (Ty regtype:$Rt),
2595 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2596 ro_Wextend32:$extend))]>,
2597 Sched<[WriteSTIdx, ReadAdrBase]> {
2601 let AddedComplexity = 10 in
2602 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2603 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2604 [(storeop (Ty regtype:$Rt),
2605 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2606 ro_Xextend32:$extend))]>,
2607 Sched<[WriteSTIdx, ReadAdrBase]> {
2611 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2614 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2615 string asm, dag ins, dag outs, list<dag> pat>
2616 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2621 let Inst{31-30} = sz;
2622 let Inst{29-27} = 0b111;
2624 let Inst{25-24} = 0b00;
2625 let Inst{23-22} = opc;
2627 let Inst{20-16} = Rm;
2628 let Inst{15} = extend{1}; // sign extend Rm?
2630 let Inst{12} = extend{0}; // do shift?
2631 let Inst{11-10} = 0b10;
2636 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2637 string asm, ValueType Ty, SDPatternOperator loadop> {
2638 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2639 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2640 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2641 [(set (Ty regtype:$Rt),
2642 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2643 ro_Wextend64:$extend)))]>,
2644 Sched<[WriteLDIdx, ReadAdrBase]> {
2648 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2649 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2650 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2651 [(set (Ty regtype:$Rt),
2652 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2653 ro_Xextend64:$extend)))]>,
2654 Sched<[WriteLDIdx, ReadAdrBase]> {
2658 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2661 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2662 string asm, ValueType Ty, SDPatternOperator storeop> {
2663 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2664 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2665 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2666 [(storeop (Ty regtype:$Rt),
2667 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2668 ro_Wextend64:$extend))]>,
2669 Sched<[WriteSTIdx, ReadAdrBase]> {
2673 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2674 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2675 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2676 [(storeop (Ty regtype:$Rt),
2677 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2678 ro_Xextend64:$extend))]>,
2679 Sched<[WriteSTIdx, ReadAdrBase]> {
2683 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2686 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2687 string asm, dag ins, dag outs, list<dag> pat>
2688 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2693 let Inst{31-30} = sz;
2694 let Inst{29-27} = 0b111;
2696 let Inst{25-24} = 0b00;
2697 let Inst{23-22} = opc;
2699 let Inst{20-16} = Rm;
2700 let Inst{15} = extend{1}; // sign extend Rm?
2702 let Inst{12} = extend{0}; // do shift?
2703 let Inst{11-10} = 0b10;
2708 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2709 string asm, ValueType Ty, SDPatternOperator loadop> {
2710 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2711 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2712 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2713 [(set (Ty regtype:$Rt),
2714 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2715 ro_Wextend128:$extend)))]>,
2716 Sched<[WriteLDIdx, ReadAdrBase]> {
2720 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2721 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2722 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2723 [(set (Ty regtype:$Rt),
2724 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2725 ro_Xextend128:$extend)))]>,
2726 Sched<[WriteLDIdx, ReadAdrBase]> {
2730 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2733 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2734 string asm, ValueType Ty, SDPatternOperator storeop> {
2735 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2736 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2737 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2738 [(storeop (Ty regtype:$Rt),
2739 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2740 ro_Wextend128:$extend))]>,
2741 Sched<[WriteSTIdx, ReadAdrBase]> {
2745 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2746 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2747 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2748 [(storeop (Ty regtype:$Rt),
2749 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2750 ro_Xextend128:$extend))]>,
2751 Sched<[WriteSTIdx, ReadAdrBase]> {
2755 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2758 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2759 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2760 string asm, list<dag> pat>
2761 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2767 let Inst{31-30} = sz;
2768 let Inst{29-27} = 0b111;
2770 let Inst{25-24} = 0b00;
2771 let Inst{23-22} = opc;
2773 let Inst{20-16} = Rm;
2774 let Inst{15} = extend{1}; // sign extend Rm?
2776 let Inst{12} = extend{0}; // do shift?
2777 let Inst{11-10} = 0b10;
2782 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2783 def roW : BasePrefetchRO<sz, V, opc, (outs),
2784 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2785 asm, [(AArch64Prefetch imm:$Rt,
2786 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2787 ro_Wextend64:$extend))]> {
2791 def roX : BasePrefetchRO<sz, V, opc, (outs),
2792 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2793 asm, [(AArch64Prefetch imm:$Rt,
2794 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2795 ro_Xextend64:$extend))]> {
2799 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2800 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2801 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2805 // Load/store unscaled immediate
2808 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2809 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2810 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2811 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2812 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2814 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2815 string asm, list<dag> pattern>
2816 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2820 let Inst{31-30} = sz;
2821 let Inst{29-27} = 0b111;
2823 let Inst{25-24} = 0b00;
2824 let Inst{23-22} = opc;
2826 let Inst{20-12} = offset;
2827 let Inst{11-10} = 0b00;
2831 let DecoderMethod = "DecodeSignedLdStInstruction";
2834 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2835 string asm, list<dag> pattern> {
2836 let AddedComplexity = 1 in // try this before LoadUI
2837 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2838 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2841 def : InstAlias<asm # " $Rt, [$Rn]",
2842 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2845 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2846 string asm, list<dag> pattern> {
2847 let AddedComplexity = 1 in // try this before StoreUI
2848 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2849 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2853 def : InstAlias<asm # " $Rt, [$Rn]",
2854 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2857 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
2859 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2860 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2861 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2865 def : InstAlias<asm # " $Rt, [$Rn]",
2866 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2870 // Load/store unscaled immediate, unprivileged
2873 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2874 dag oops, dag iops, string asm>
2875 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2879 let Inst{31-30} = sz;
2880 let Inst{29-27} = 0b111;
2882 let Inst{25-24} = 0b00;
2883 let Inst{23-22} = opc;
2885 let Inst{20-12} = offset;
2886 let Inst{11-10} = 0b10;
2890 let DecoderMethod = "DecodeSignedLdStInstruction";
2893 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
2894 RegisterClass regtype, string asm> {
2895 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
2896 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
2897 (ins GPR64sp:$Rn, simm9:$offset), asm>,
2900 def : InstAlias<asm # " $Rt, [$Rn]",
2901 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2904 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2905 RegisterClass regtype, string asm> {
2906 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2907 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
2908 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2912 def : InstAlias<asm # " $Rt, [$Rn]",
2913 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2917 // Load/store pre-indexed
2920 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2921 string asm, string cstr, list<dag> pat>
2922 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
2926 let Inst{31-30} = sz;
2927 let Inst{29-27} = 0b111;
2929 let Inst{25-24} = 0;
2930 let Inst{23-22} = opc;
2932 let Inst{20-12} = offset;
2933 let Inst{11-10} = 0b11;
2937 let DecoderMethod = "DecodeSignedLdStInstruction";
2940 let hasSideEffects = 0 in {
2941 let mayStore = 0, mayLoad = 1 in
2942 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2944 : BaseLoadStorePreIdx<sz, V, opc,
2945 (outs GPR64sp:$wback, regtype:$Rt),
2946 (ins GPR64sp:$Rn, simm9:$offset), asm,
2947 "$Rn = $wback", []>,
2948 Sched<[WriteLD, WriteAdr]>;
2950 let mayStore = 1, mayLoad = 0 in
2951 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2952 string asm, SDPatternOperator storeop, ValueType Ty>
2953 : BaseLoadStorePreIdx<sz, V, opc,
2954 (outs GPR64sp:$wback),
2955 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2956 asm, "$Rn = $wback",
2957 [(set GPR64sp:$wback,
2958 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
2959 Sched<[WriteAdr, WriteST]>;
2960 } // hasSideEffects = 0
2963 // Load/store post-indexed
2966 // (pre-index) load/stores.
2967 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2968 string asm, string cstr, list<dag> pat>
2969 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
2973 let Inst{31-30} = sz;
2974 let Inst{29-27} = 0b111;
2976 let Inst{25-24} = 0b00;
2977 let Inst{23-22} = opc;
2979 let Inst{20-12} = offset;
2980 let Inst{11-10} = 0b01;
2984 let DecoderMethod = "DecodeSignedLdStInstruction";
2987 let hasSideEffects = 0 in {
2988 let mayStore = 0, mayLoad = 1 in
2989 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2991 : BaseLoadStorePostIdx<sz, V, opc,
2992 (outs GPR64sp:$wback, regtype:$Rt),
2993 (ins GPR64sp:$Rn, simm9:$offset),
2994 asm, "$Rn = $wback", []>,
2995 Sched<[WriteLD, WriteI]>;
2997 let mayStore = 1, mayLoad = 0 in
2998 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2999 string asm, SDPatternOperator storeop, ValueType Ty>
3000 : BaseLoadStorePostIdx<sz, V, opc,
3001 (outs GPR64sp:$wback),
3002 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3003 asm, "$Rn = $wback",
3004 [(set GPR64sp:$wback,
3005 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3006 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3007 } // hasSideEffects = 0
3014 // (indexed, offset)
3016 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3018 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3023 let Inst{31-30} = opc;
3024 let Inst{29-27} = 0b101;
3026 let Inst{25-23} = 0b010;
3028 let Inst{21-15} = offset;
3029 let Inst{14-10} = Rt2;
3033 let DecoderMethod = "DecodePairLdStInstruction";
3036 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3037 Operand indextype, string asm> {
3038 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3039 def i : BaseLoadStorePairOffset<opc, V, 1,
3040 (outs regtype:$Rt, regtype:$Rt2),
3041 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3042 Sched<[WriteLD, WriteLDHi]>;
3044 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3045 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3050 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3051 Operand indextype, string asm> {
3052 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3053 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3054 (ins regtype:$Rt, regtype:$Rt2,
3055 GPR64sp:$Rn, indextype:$offset),
3059 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3060 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3065 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3067 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback", []> {
3072 let Inst{31-30} = opc;
3073 let Inst{29-27} = 0b101;
3075 let Inst{25-23} = 0b011;
3077 let Inst{21-15} = offset;
3078 let Inst{14-10} = Rt2;
3082 let DecoderMethod = "DecodePairLdStInstruction";
3085 let hasSideEffects = 0 in {
3086 let mayStore = 0, mayLoad = 1 in
3087 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3088 Operand indextype, string asm>
3089 : BaseLoadStorePairPreIdx<opc, V, 1,
3090 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3091 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3092 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3094 let mayStore = 1, mayLoad = 0 in
3095 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3096 Operand indextype, string asm>
3097 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3098 (ins regtype:$Rt, regtype:$Rt2,
3099 GPR64sp:$Rn, indextype:$offset),
3101 Sched<[WriteAdr, WriteSTP]>;
3102 } // hasSideEffects = 0
3106 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3108 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback", []> {
3113 let Inst{31-30} = opc;
3114 let Inst{29-27} = 0b101;
3116 let Inst{25-23} = 0b001;
3118 let Inst{21-15} = offset;
3119 let Inst{14-10} = Rt2;
3123 let DecoderMethod = "DecodePairLdStInstruction";
3126 let hasSideEffects = 0 in {
3127 let mayStore = 0, mayLoad = 1 in
3128 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3129 Operand idxtype, string asm>
3130 : BaseLoadStorePairPostIdx<opc, V, 1,
3131 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3132 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3133 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3135 let mayStore = 1, mayLoad = 0 in
3136 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3137 Operand idxtype, string asm>
3138 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
3139 (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
3140 GPR64sp:$Rn, idxtype:$offset),
3142 Sched<[WriteAdr, WriteSTP]>;
3143 } // hasSideEffects = 0
3147 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3149 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3154 let Inst{31-30} = opc;
3155 let Inst{29-27} = 0b101;
3157 let Inst{25-23} = 0b000;
3159 let Inst{21-15} = offset;
3160 let Inst{14-10} = Rt2;
3164 let DecoderMethod = "DecodePairLdStInstruction";
3167 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3168 Operand indextype, string asm> {
3169 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3170 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3171 (outs regtype:$Rt, regtype:$Rt2),
3172 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3173 Sched<[WriteLD, WriteLDHi]>;
3176 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3177 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3181 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3182 Operand indextype, string asm> {
3183 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3184 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3185 (ins regtype:$Rt, regtype:$Rt2,
3186 GPR64sp:$Rn, indextype:$offset),
3190 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3191 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3196 // Load/store exclusive
3199 // True exclusive operations write to and/or read from the system's exclusive
3200 // monitors, which as far as a compiler is concerned can be modelled as a
3201 // random shared memory address. Hence LoadExclusive mayStore.
3203 // Since these instructions have the undefined register bits set to 1 in
3204 // their canonical form, we need a post encoder method to set those bits
3205 // to 1 when encoding these instructions. We do this using the
3206 // fixLoadStoreExclusive function. This function has template parameters:
3208 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3210 // hasRs indicates that the instruction uses the Rs field, so we won't set
3211 // it to 1 (and the same for Rt2). We don't need template parameters for
3212 // the other register fields since Rt and Rn are always used.
3214 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3215 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3216 dag oops, dag iops, string asm, string operands>
3217 : I<oops, iops, asm, operands, "", []> {
3218 let Inst{31-30} = sz;
3219 let Inst{29-24} = 0b001000;
3225 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3228 // Neither Rs nor Rt2 operands.
3229 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3230 dag oops, dag iops, string asm, string operands>
3231 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3237 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3240 // Simple load acquires don't set the exclusive monitor
3241 let mayLoad = 1, mayStore = 0 in
3242 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3243 RegisterClass regtype, string asm>
3244 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3245 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3248 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3249 RegisterClass regtype, string asm>
3250 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3251 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3254 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3255 RegisterClass regtype, string asm>
3256 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3257 (outs regtype:$Rt, regtype:$Rt2),
3258 (ins GPR64sp0:$Rn), asm,
3259 "\t$Rt, $Rt2, [$Rn]">,
3260 Sched<[WriteLD, WriteLDHi]> {
3264 let Inst{14-10} = Rt2;
3268 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3271 // Simple store release operations do not check the exclusive monitor.
3272 let mayLoad = 0, mayStore = 1 in
3273 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3274 RegisterClass regtype, string asm>
3275 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3276 (ins regtype:$Rt, GPR64sp0:$Rn),
3277 asm, "\t$Rt, [$Rn]">,
3280 let mayLoad = 1, mayStore = 1 in
3281 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3282 RegisterClass regtype, string asm>
3283 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3284 (ins regtype:$Rt, GPR64sp0:$Rn),
3285 asm, "\t$Ws, $Rt, [$Rn]">,
3290 let Inst{20-16} = Ws;
3294 let Constraints = "@earlyclobber $Ws";
3295 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3298 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3299 RegisterClass regtype, string asm>
3300 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3302 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3303 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3309 let Inst{20-16} = Ws;
3310 let Inst{14-10} = Rt2;
3314 let Constraints = "@earlyclobber $Ws";
3318 // Exception generation
3321 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3322 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3323 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3326 let Inst{31-24} = 0b11010100;
3327 let Inst{23-21} = op1;
3328 let Inst{20-5} = imm;
3329 let Inst{4-2} = 0b000;
3333 let Predicates = [HasFPARMv8] in {
3336 // Floating point to integer conversion
3339 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3340 RegisterClass srcType, RegisterClass dstType,
3341 string asm, list<dag> pattern>
3342 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3343 asm, "\t$Rd, $Rn", "", pattern>,
3344 Sched<[WriteFCvt]> {
3347 let Inst{30-29} = 0b00;
3348 let Inst{28-24} = 0b11110;
3349 let Inst{23-22} = type;
3351 let Inst{20-19} = rmode;
3352 let Inst{18-16} = opcode;
3353 let Inst{15-10} = 0;
3358 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3359 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3360 RegisterClass srcType, RegisterClass dstType,
3361 Operand immType, string asm, list<dag> pattern>
3362 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3363 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3364 Sched<[WriteFCvt]> {
3368 let Inst{30-29} = 0b00;
3369 let Inst{28-24} = 0b11110;
3370 let Inst{23-22} = type;
3372 let Inst{20-19} = rmode;
3373 let Inst{18-16} = opcode;
3374 let Inst{15-10} = scale;
3379 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3380 SDPatternOperator OpN> {
3381 // Unscaled single-precision to 32-bit
3382 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3383 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3384 let Inst{31} = 0; // 32-bit GPR flag
3387 // Unscaled single-precision to 64-bit
3388 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3389 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3390 let Inst{31} = 1; // 64-bit GPR flag
3393 // Unscaled double-precision to 32-bit
3394 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3395 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3396 let Inst{31} = 0; // 32-bit GPR flag
3399 // Unscaled double-precision to 64-bit
3400 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3401 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3402 let Inst{31} = 1; // 64-bit GPR flag
3406 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3407 SDPatternOperator OpN> {
3408 // Scaled single-precision to 32-bit
3409 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3410 fixedpoint_f32_i32, asm,
3411 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3412 fixedpoint_f32_i32:$scale)))]> {
3413 let Inst{31} = 0; // 32-bit GPR flag
3417 // Scaled single-precision to 64-bit
3418 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3419 fixedpoint_f32_i64, asm,
3420 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3421 fixedpoint_f32_i64:$scale)))]> {
3422 let Inst{31} = 1; // 64-bit GPR flag
3425 // Scaled double-precision to 32-bit
3426 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3427 fixedpoint_f64_i32, asm,
3428 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3429 fixedpoint_f64_i32:$scale)))]> {
3430 let Inst{31} = 0; // 32-bit GPR flag
3434 // Scaled double-precision to 64-bit
3435 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3436 fixedpoint_f64_i64, asm,
3437 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3438 fixedpoint_f64_i64:$scale)))]> {
3439 let Inst{31} = 1; // 64-bit GPR flag
3444 // Integer to floating point conversion
3447 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3448 class BaseIntegerToFP<bit isUnsigned,
3449 RegisterClass srcType, RegisterClass dstType,
3450 Operand immType, string asm, list<dag> pattern>
3451 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3452 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3453 Sched<[WriteFCvt]> {
3457 let Inst{30-23} = 0b00111100;
3458 let Inst{21-17} = 0b00001;
3459 let Inst{16} = isUnsigned;
3460 let Inst{15-10} = scale;
3465 class BaseIntegerToFPUnscaled<bit isUnsigned,
3466 RegisterClass srcType, RegisterClass dstType,
3467 ValueType dvt, string asm, SDNode node>
3468 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3469 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3470 Sched<[WriteFCvt]> {
3474 let Inst{30-23} = 0b00111100;
3475 let Inst{21-17} = 0b10001;
3476 let Inst{16} = isUnsigned;
3477 let Inst{15-10} = 0b000000;
3482 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3484 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3485 let Inst{31} = 0; // 32-bit GPR flag
3486 let Inst{22} = 0; // 32-bit FPR flag
3489 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3490 let Inst{31} = 0; // 32-bit GPR flag
3491 let Inst{22} = 1; // 64-bit FPR flag
3494 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3495 let Inst{31} = 1; // 64-bit GPR flag
3496 let Inst{22} = 0; // 32-bit FPR flag
3499 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3500 let Inst{31} = 1; // 64-bit GPR flag
3501 let Inst{22} = 1; // 64-bit FPR flag
3505 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3507 (fdiv (node GPR32:$Rn),
3508 fixedpoint_f32_i32:$scale))]> {
3509 let Inst{31} = 0; // 32-bit GPR flag
3510 let Inst{22} = 0; // 32-bit FPR flag
3514 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3516 (fdiv (node GPR32:$Rn),
3517 fixedpoint_f64_i32:$scale))]> {
3518 let Inst{31} = 0; // 32-bit GPR flag
3519 let Inst{22} = 1; // 64-bit FPR flag
3523 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3525 (fdiv (node GPR64:$Rn),
3526 fixedpoint_f32_i64:$scale))]> {
3527 let Inst{31} = 1; // 64-bit GPR flag
3528 let Inst{22} = 0; // 32-bit FPR flag
3531 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3533 (fdiv (node GPR64:$Rn),
3534 fixedpoint_f64_i64:$scale))]> {
3535 let Inst{31} = 1; // 64-bit GPR flag
3536 let Inst{22} = 1; // 64-bit FPR flag
3541 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3544 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3545 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3546 RegisterClass srcType, RegisterClass dstType,
3548 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3549 // We use COPY_TO_REGCLASS for these bitconvert operations.
3550 // copyPhysReg() expands the resultant COPY instructions after
3551 // regalloc is done. This gives greater freedom for the allocator
3552 // and related passes (coalescing, copy propagation, et. al.) to
3553 // be more effective.
3554 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3555 Sched<[WriteFCopy]> {
3558 let Inst{30-23} = 0b00111100;
3560 let Inst{20-19} = rmode;
3561 let Inst{18-16} = opcode;
3562 let Inst{15-10} = 0b000000;
3567 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3568 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3569 RegisterClass srcType, RegisterOperand dstType, string asm,
3571 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3572 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3573 Sched<[WriteFCopy]> {
3576 let Inst{30-23} = 0b00111101;
3578 let Inst{20-19} = rmode;
3579 let Inst{18-16} = opcode;
3580 let Inst{15-10} = 0b000000;
3584 let DecoderMethod = "DecodeFMOVLaneInstruction";
3587 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3588 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3589 RegisterOperand srcType, RegisterClass dstType, string asm,
3591 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3592 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3593 Sched<[WriteFCopy]> {
3596 let Inst{30-23} = 0b00111101;
3598 let Inst{20-19} = rmode;
3599 let Inst{18-16} = opcode;
3600 let Inst{15-10} = 0b000000;
3604 let DecoderMethod = "DecodeFMOVLaneInstruction";
3609 multiclass UnscaledConversion<string asm> {
3610 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3611 let Inst{31} = 0; // 32-bit GPR flag
3612 let Inst{22} = 0; // 32-bit FPR flag
3615 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3616 let Inst{31} = 1; // 64-bit GPR flag
3617 let Inst{22} = 1; // 64-bit FPR flag
3620 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3621 let Inst{31} = 0; // 32-bit GPR flag
3622 let Inst{22} = 0; // 32-bit FPR flag
3625 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3626 let Inst{31} = 1; // 64-bit GPR flag
3627 let Inst{22} = 1; // 64-bit FPR flag
3630 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3636 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3644 // Floating point conversion
3647 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3648 RegisterClass srcType, string asm, list<dag> pattern>
3649 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3650 Sched<[WriteFCvt]> {
3653 let Inst{31-24} = 0b00011110;
3654 let Inst{23-22} = type;
3655 let Inst{21-17} = 0b10001;
3656 let Inst{16-15} = opcode;
3657 let Inst{14-10} = 0b10000;
3662 multiclass FPConversion<string asm> {
3663 // Double-precision to Half-precision
3664 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3665 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3667 // Double-precision to Single-precision
3668 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3669 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3671 // Half-precision to Double-precision
3672 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3673 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3675 // Half-precision to Single-precision
3676 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3677 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3679 // Single-precision to Double-precision
3680 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3681 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3683 // Single-precision to Half-precision
3684 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3685 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3689 // Single operand floating point data processing
3692 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3693 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3694 ValueType vt, string asm, SDPatternOperator node>
3695 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3696 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3700 let Inst{31-23} = 0b000111100;
3701 let Inst{21-19} = 0b100;
3702 let Inst{18-15} = opcode;
3703 let Inst{14-10} = 0b10000;
3708 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3709 SDPatternOperator node = null_frag> {
3710 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3711 let Inst{22} = 0; // 32-bit size flag
3714 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3715 let Inst{22} = 1; // 64-bit size flag
3720 // Two operand floating point data processing
3723 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3724 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3725 string asm, list<dag> pat>
3726 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3727 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3732 let Inst{31-23} = 0b000111100;
3734 let Inst{20-16} = Rm;
3735 let Inst{15-12} = opcode;
3736 let Inst{11-10} = 0b10;
3741 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3742 SDPatternOperator node = null_frag> {
3743 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3744 [(set (f32 FPR32:$Rd),
3745 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3746 let Inst{22} = 0; // 32-bit size flag
3749 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3750 [(set (f64 FPR64:$Rd),
3751 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3752 let Inst{22} = 1; // 64-bit size flag
3756 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3757 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3758 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3759 let Inst{22} = 0; // 32-bit size flag
3762 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3763 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3764 let Inst{22} = 1; // 64-bit size flag
3770 // Three operand floating point data processing
3773 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3774 RegisterClass regtype, string asm, list<dag> pat>
3775 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3776 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3777 Sched<[WriteFMul]> {
3782 let Inst{31-23} = 0b000111110;
3783 let Inst{21} = isNegated;
3784 let Inst{20-16} = Rm;
3785 let Inst{15} = isSub;
3786 let Inst{14-10} = Ra;
3791 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3792 SDPatternOperator node> {
3793 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3795 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3796 let Inst{22} = 0; // 32-bit size flag
3799 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3801 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3802 let Inst{22} = 1; // 64-bit size flag
3807 // Floating point data comparisons
3810 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3811 class BaseOneOperandFPComparison<bit signalAllNans,
3812 RegisterClass regtype, string asm,
3814 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3815 Sched<[WriteFCmp]> {
3817 let Inst{31-23} = 0b000111100;
3820 let Inst{15-10} = 0b001000;
3822 let Inst{4} = signalAllNans;
3823 let Inst{3-0} = 0b1000;
3825 // Rm should be 0b00000 canonically, but we need to accept any value.
3826 let PostEncoderMethod = "fixOneOperandFPComparison";
3829 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3830 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3831 string asm, list<dag> pat>
3832 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3833 Sched<[WriteFCmp]> {
3836 let Inst{31-23} = 0b000111100;
3838 let Inst{20-16} = Rm;
3839 let Inst{15-10} = 0b001000;
3841 let Inst{4} = signalAllNans;
3842 let Inst{3-0} = 0b0000;
3845 multiclass FPComparison<bit signalAllNans, string asm,
3846 SDPatternOperator OpNode = null_frag> {
3847 let Defs = [NZCV] in {
3848 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3849 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3853 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3854 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3858 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3859 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3863 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3864 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3871 // Floating point conditional comparisons
3874 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3875 class BaseFPCondComparison<bit signalAllNans,
3876 RegisterClass regtype, string asm>
3877 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3878 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3879 Sched<[WriteFCmp]> {
3885 let Inst{31-23} = 0b000111100;
3887 let Inst{20-16} = Rm;
3888 let Inst{15-12} = cond;
3889 let Inst{11-10} = 0b01;
3891 let Inst{4} = signalAllNans;
3892 let Inst{3-0} = nzcv;
3895 multiclass FPCondComparison<bit signalAllNans, string asm> {
3896 let Defs = [NZCV], Uses = [NZCV] in {
3897 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3901 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3904 } // Defs = [NZCV], Uses = [NZCV]
3908 // Floating point conditional select
3911 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3912 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3913 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3915 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
3916 (i32 imm:$cond), NZCV))]>,
3923 let Inst{31-23} = 0b000111100;
3925 let Inst{20-16} = Rm;
3926 let Inst{15-12} = cond;
3927 let Inst{11-10} = 0b11;
3932 multiclass FPCondSelect<string asm> {
3933 let Uses = [NZCV] in {
3934 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3938 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
3945 // Floating move immediate
3948 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
3949 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
3950 [(set regtype:$Rd, fpimmtype:$imm)]>,
3951 Sched<[WriteFImm]> {
3954 let Inst{31-23} = 0b000111100;
3956 let Inst{20-13} = imm;
3957 let Inst{12-5} = 0b10000000;
3961 multiclass FPMoveImmediate<string asm> {
3962 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
3966 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
3970 } // end of 'let Predicates = [HasFPARMv8]'
3972 //----------------------------------------------------------------------------
3974 //----------------------------------------------------------------------------
3976 let Predicates = [HasNEON] in {
3978 //----------------------------------------------------------------------------
3979 // AdvSIMD three register vector instructions
3980 //----------------------------------------------------------------------------
3982 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3983 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
3984 RegisterOperand regtype, string asm, string kind,
3986 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
3987 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
3988 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
3996 let Inst{28-24} = 0b01110;
3997 let Inst{23-22} = size;
3999 let Inst{20-16} = Rm;
4000 let Inst{15-11} = opcode;
4006 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4007 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4008 RegisterOperand regtype, string asm, string kind,
4010 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4011 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4012 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4020 let Inst{28-24} = 0b01110;
4021 let Inst{23-22} = size;
4023 let Inst{20-16} = Rm;
4024 let Inst{15-11} = opcode;
4030 // All operand sizes distinguished in the encoding.
4031 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4032 SDPatternOperator OpNode> {
4033 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4035 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4036 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4038 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4039 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4041 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4042 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4044 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4045 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4047 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4048 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4050 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4051 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4053 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4056 // As above, but D sized elements unsupported.
4057 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4058 SDPatternOperator OpNode> {
4059 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4061 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4062 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4064 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4065 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4067 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4068 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4070 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4071 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4073 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4074 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4076 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4079 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4080 SDPatternOperator OpNode> {
4081 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4083 [(set (v8i8 V64:$dst),
4084 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4085 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4087 [(set (v16i8 V128:$dst),
4088 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4089 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4091 [(set (v4i16 V64:$dst),
4092 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4093 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4095 [(set (v8i16 V128:$dst),
4096 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4097 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4099 [(set (v2i32 V64:$dst),
4100 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4101 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4103 [(set (v4i32 V128:$dst),
4104 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4107 // As above, but only B sized elements supported.
4108 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4109 SDPatternOperator OpNode> {
4110 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4112 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4113 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4115 [(set (v16i8 V128:$Rd),
4116 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4119 // As above, but only S and D sized floating point elements supported.
4120 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4121 string asm, SDPatternOperator OpNode> {
4122 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4124 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4125 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4127 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4128 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4130 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4133 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4135 SDPatternOperator OpNode> {
4136 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4138 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4139 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4141 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4142 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4144 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4147 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4148 string asm, SDPatternOperator OpNode> {
4149 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4151 [(set (v2f32 V64:$dst),
4152 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4153 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4155 [(set (v4f32 V128:$dst),
4156 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4157 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4159 [(set (v2f64 V128:$dst),
4160 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4163 // As above, but D and B sized elements unsupported.
4164 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4165 SDPatternOperator OpNode> {
4166 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4168 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4169 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4171 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4172 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4174 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4175 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4177 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4180 // Logical three vector ops share opcode bits, and only use B sized elements.
4181 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4182 SDPatternOperator OpNode = null_frag> {
4183 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4185 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4186 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4188 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4190 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4191 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4192 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4193 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4194 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4195 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4197 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4198 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4199 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4200 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4201 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4202 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4205 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4206 string asm, SDPatternOperator OpNode> {
4207 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4209 [(set (v8i8 V64:$dst),
4210 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4211 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4213 [(set (v16i8 V128:$dst),
4214 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4215 (v16i8 V128:$Rm)))]>;
4217 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4219 (!cast<Instruction>(NAME#"v8i8")
4220 V64:$LHS, V64:$MHS, V64:$RHS)>;
4221 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4223 (!cast<Instruction>(NAME#"v8i8")
4224 V64:$LHS, V64:$MHS, V64:$RHS)>;
4225 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4227 (!cast<Instruction>(NAME#"v8i8")
4228 V64:$LHS, V64:$MHS, V64:$RHS)>;
4230 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4231 (v8i16 V128:$RHS))),
4232 (!cast<Instruction>(NAME#"v16i8")
4233 V128:$LHS, V128:$MHS, V128:$RHS)>;
4234 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4235 (v4i32 V128:$RHS))),
4236 (!cast<Instruction>(NAME#"v16i8")
4237 V128:$LHS, V128:$MHS, V128:$RHS)>;
4238 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4239 (v2i64 V128:$RHS))),
4240 (!cast<Instruction>(NAME#"v16i8")
4241 V128:$LHS, V128:$MHS, V128:$RHS)>;
4245 //----------------------------------------------------------------------------
4246 // AdvSIMD two register vector instructions.
4247 //----------------------------------------------------------------------------
4249 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4250 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4251 RegisterOperand regtype, string asm, string dstkind,
4252 string srckind, list<dag> pattern>
4253 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4254 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4255 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4262 let Inst{28-24} = 0b01110;
4263 let Inst{23-22} = size;
4264 let Inst{21-17} = 0b10000;
4265 let Inst{16-12} = opcode;
4266 let Inst{11-10} = 0b10;
4271 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4272 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4273 RegisterOperand regtype, string asm, string dstkind,
4274 string srckind, list<dag> pattern>
4275 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4276 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4277 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4284 let Inst{28-24} = 0b01110;
4285 let Inst{23-22} = size;
4286 let Inst{21-17} = 0b10000;
4287 let Inst{16-12} = opcode;
4288 let Inst{11-10} = 0b10;
4293 // Supports B, H, and S element sizes.
4294 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4295 SDPatternOperator OpNode> {
4296 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4298 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4299 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4300 asm, ".16b", ".16b",
4301 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4302 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4304 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4305 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4307 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4308 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4310 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4311 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4313 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4316 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4317 RegisterOperand regtype, string asm, string dstkind,
4318 string srckind, string amount>
4319 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4320 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4321 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4327 let Inst{29-24} = 0b101110;
4328 let Inst{23-22} = size;
4329 let Inst{21-10} = 0b100001001110;
4334 multiclass SIMDVectorLShiftLongBySizeBHS {
4335 let neverHasSideEffects = 1 in {
4336 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4337 "shll", ".8h", ".8b", "8">;
4338 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4339 "shll2", ".8h", ".16b", "8">;
4340 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4341 "shll", ".4s", ".4h", "16">;
4342 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4343 "shll2", ".4s", ".8h", "16">;
4344 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4345 "shll", ".2d", ".2s", "32">;
4346 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4347 "shll2", ".2d", ".4s", "32">;
4351 // Supports all element sizes.
4352 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4353 SDPatternOperator OpNode> {
4354 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4356 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4357 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4359 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4360 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4362 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4363 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4365 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4366 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4368 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4369 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4371 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4374 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4375 SDPatternOperator OpNode> {
4376 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4378 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4380 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4382 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4383 (v16i8 V128:$Rn)))]>;
4384 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4386 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4387 (v4i16 V64:$Rn)))]>;
4388 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4390 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4391 (v8i16 V128:$Rn)))]>;
4392 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4394 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4395 (v2i32 V64:$Rn)))]>;
4396 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4398 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4399 (v4i32 V128:$Rn)))]>;
4402 // Supports all element sizes, except 1xD.
4403 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4404 SDPatternOperator OpNode> {
4405 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4407 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4408 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4409 asm, ".16b", ".16b",
4410 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4411 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4413 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4414 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4416 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4417 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4419 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4420 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4422 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4423 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4425 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4428 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4429 SDPatternOperator OpNode = null_frag> {
4430 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4432 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4433 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4434 asm, ".16b", ".16b",
4435 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4436 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4438 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4439 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4441 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4442 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4444 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4445 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4447 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4448 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4450 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4454 // Supports only B element sizes.
4455 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4456 SDPatternOperator OpNode> {
4457 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4459 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4460 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4461 asm, ".16b", ".16b",
4462 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4466 // Supports only B and H element sizes.
4467 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4468 SDPatternOperator OpNode> {
4469 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4471 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4472 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4473 asm, ".16b", ".16b",
4474 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4475 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4477 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4478 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4480 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4483 // Supports only S and D element sizes, uses high bit of the size field
4484 // as an extra opcode bit.
4485 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4486 SDPatternOperator OpNode> {
4487 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4489 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4490 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4492 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4493 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4495 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4498 // Supports only S element size.
4499 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4500 SDPatternOperator OpNode> {
4501 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4503 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4504 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4506 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4510 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4511 SDPatternOperator OpNode> {
4512 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4514 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4515 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4517 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4518 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4520 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4523 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4524 SDPatternOperator OpNode> {
4525 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4527 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4528 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4530 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4531 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4533 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4537 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4538 RegisterOperand inreg, RegisterOperand outreg,
4539 string asm, string outkind, string inkind,
4541 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4542 "{\t$Rd" # outkind # ", $Rn" # inkind #
4543 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4550 let Inst{28-24} = 0b01110;
4551 let Inst{23-22} = size;
4552 let Inst{21-17} = 0b10000;
4553 let Inst{16-12} = opcode;
4554 let Inst{11-10} = 0b10;
4559 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4560 RegisterOperand inreg, RegisterOperand outreg,
4561 string asm, string outkind, string inkind,
4563 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4564 "{\t$Rd" # outkind # ", $Rn" # inkind #
4565 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4572 let Inst{28-24} = 0b01110;
4573 let Inst{23-22} = size;
4574 let Inst{21-17} = 0b10000;
4575 let Inst{16-12} = opcode;
4576 let Inst{11-10} = 0b10;
4581 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4582 SDPatternOperator OpNode> {
4583 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4585 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4586 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4587 asm#"2", ".16b", ".8h", []>;
4588 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4590 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4591 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4592 asm#"2", ".8h", ".4s", []>;
4593 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4595 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4596 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4597 asm#"2", ".4s", ".2d", []>;
4599 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4600 (!cast<Instruction>(NAME # "v16i8")
4601 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4602 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4603 (!cast<Instruction>(NAME # "v8i16")
4604 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4605 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4606 (!cast<Instruction>(NAME # "v4i32")
4607 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4610 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4611 RegisterOperand regtype,
4612 string asm, string kind, string zero,
4613 ValueType dty, ValueType sty, SDNode OpNode>
4614 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4615 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4616 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4617 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4624 let Inst{28-24} = 0b01110;
4625 let Inst{23-22} = size;
4626 let Inst{21-17} = 0b10000;
4627 let Inst{16-12} = opcode;
4628 let Inst{11-10} = 0b10;
4633 // Comparisons support all element sizes, except 1xD.
4634 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4636 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4638 v8i8, v8i8, OpNode>;
4639 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4641 v16i8, v16i8, OpNode>;
4642 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4644 v4i16, v4i16, OpNode>;
4645 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4647 v8i16, v8i16, OpNode>;
4648 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4650 v2i32, v2i32, OpNode>;
4651 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4653 v4i32, v4i32, OpNode>;
4654 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4656 v2i64, v2i64, OpNode>;
4659 // FP Comparisons support only S and D element sizes.
4660 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4661 string asm, SDNode OpNode> {
4663 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4665 v2i32, v2f32, OpNode>;
4666 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4668 v4i32, v4f32, OpNode>;
4669 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4671 v2i64, v2f64, OpNode>;
4673 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4674 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4675 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4676 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4677 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4678 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4679 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4680 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4681 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4682 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4683 def : InstAlias<asm # ".2d $Vd, $Vn, #0",
4684 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4687 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4688 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4689 RegisterOperand outtype, RegisterOperand intype,
4690 string asm, string VdTy, string VnTy,
4692 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4693 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4700 let Inst{28-24} = 0b01110;
4701 let Inst{23-22} = size;
4702 let Inst{21-17} = 0b10000;
4703 let Inst{16-12} = opcode;
4704 let Inst{11-10} = 0b10;
4709 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4710 RegisterOperand outtype, RegisterOperand intype,
4711 string asm, string VdTy, string VnTy,
4713 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4714 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4721 let Inst{28-24} = 0b01110;
4722 let Inst{23-22} = size;
4723 let Inst{21-17} = 0b10000;
4724 let Inst{16-12} = opcode;
4725 let Inst{11-10} = 0b10;
4730 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4731 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4732 asm, ".4s", ".4h", []>;
4733 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4734 asm#"2", ".4s", ".8h", []>;
4735 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4736 asm, ".2d", ".2s", []>;
4737 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4738 asm#"2", ".2d", ".4s", []>;
4741 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4742 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4743 asm, ".4h", ".4s", []>;
4744 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4745 asm#"2", ".8h", ".4s", []>;
4746 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4747 asm, ".2s", ".2d", []>;
4748 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4749 asm#"2", ".4s", ".2d", []>;
4752 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4754 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4756 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4757 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4758 asm#"2", ".4s", ".2d", []>;
4760 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4761 (!cast<Instruction>(NAME # "v4f32")
4762 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4765 //----------------------------------------------------------------------------
4766 // AdvSIMD three register different-size vector instructions.
4767 //----------------------------------------------------------------------------
4769 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4770 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4771 RegisterOperand outtype, RegisterOperand intype1,
4772 RegisterOperand intype2, string asm,
4773 string outkind, string inkind1, string inkind2,
4775 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4776 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4777 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4783 let Inst{30} = size{0};
4785 let Inst{28-24} = 0b01110;
4786 let Inst{23-22} = size{2-1};
4788 let Inst{20-16} = Rm;
4789 let Inst{15-12} = opcode;
4790 let Inst{11-10} = 0b00;
4795 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4796 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4797 RegisterOperand outtype, RegisterOperand intype1,
4798 RegisterOperand intype2, string asm,
4799 string outkind, string inkind1, string inkind2,
4801 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4802 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4803 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4809 let Inst{30} = size{0};
4811 let Inst{28-24} = 0b01110;
4812 let Inst{23-22} = size{2-1};
4814 let Inst{20-16} = Rm;
4815 let Inst{15-12} = opcode;
4816 let Inst{11-10} = 0b00;
4821 // FIXME: TableGen doesn't know how to deal with expanded types that also
4822 // change the element count (in this case, placing the results in
4823 // the high elements of the result register rather than the low
4824 // elements). Until that's fixed, we can't code-gen those.
4825 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4827 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4829 asm, ".8b", ".8h", ".8h",
4830 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4831 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4833 asm#"2", ".16b", ".8h", ".8h",
4835 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4837 asm, ".4h", ".4s", ".4s",
4838 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4839 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4841 asm#"2", ".8h", ".4s", ".4s",
4843 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4845 asm, ".2s", ".2d", ".2d",
4846 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4847 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4849 asm#"2", ".4s", ".2d", ".2d",
4853 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4854 // a version attached to an instruction.
4855 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4857 (!cast<Instruction>(NAME # "v8i16_v16i8")
4858 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4859 V128:$Rn, V128:$Rm)>;
4860 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4862 (!cast<Instruction>(NAME # "v4i32_v8i16")
4863 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4864 V128:$Rn, V128:$Rm)>;
4865 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4867 (!cast<Instruction>(NAME # "v2i64_v4i32")
4868 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4869 V128:$Rn, V128:$Rm)>;
4872 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4874 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4876 asm, ".8h", ".8b", ".8b",
4877 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4878 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4880 asm#"2", ".8h", ".16b", ".16b", []>;
4881 let Predicates = [HasCrypto] in {
4882 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4884 asm, ".1q", ".1d", ".1d", []>;
4885 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4887 asm#"2", ".1q", ".2d", ".2d", []>;
4890 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4891 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4892 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4895 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4896 SDPatternOperator OpNode> {
4897 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4899 asm, ".4s", ".4h", ".4h",
4900 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4901 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4903 asm#"2", ".4s", ".8h", ".8h",
4904 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4905 (extract_high_v8i16 V128:$Rm)))]>;
4906 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4908 asm, ".2d", ".2s", ".2s",
4909 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4910 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4912 asm#"2", ".2d", ".4s", ".4s",
4913 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4914 (extract_high_v4i32 V128:$Rm)))]>;
4917 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4918 SDPatternOperator OpNode = null_frag> {
4919 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4921 asm, ".8h", ".8b", ".8b",
4922 [(set (v8i16 V128:$Rd),
4923 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4924 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4926 asm#"2", ".8h", ".16b", ".16b",
4927 [(set (v8i16 V128:$Rd),
4928 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4929 (extract_high_v16i8 V128:$Rm)))))]>;
4930 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4932 asm, ".4s", ".4h", ".4h",
4933 [(set (v4i32 V128:$Rd),
4934 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4935 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4937 asm#"2", ".4s", ".8h", ".8h",
4938 [(set (v4i32 V128:$Rd),
4939 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4940 (extract_high_v8i16 V128:$Rm)))))]>;
4941 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4943 asm, ".2d", ".2s", ".2s",
4944 [(set (v2i64 V128:$Rd),
4945 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
4946 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4948 asm#"2", ".2d", ".4s", ".4s",
4949 [(set (v2i64 V128:$Rd),
4950 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4951 (extract_high_v4i32 V128:$Rm)))))]>;
4954 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
4956 SDPatternOperator OpNode> {
4957 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4959 asm, ".8h", ".8b", ".8b",
4960 [(set (v8i16 V128:$dst),
4961 (add (v8i16 V128:$Rd),
4962 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
4963 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4965 asm#"2", ".8h", ".16b", ".16b",
4966 [(set (v8i16 V128:$dst),
4967 (add (v8i16 V128:$Rd),
4968 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4969 (extract_high_v16i8 V128:$Rm))))))]>;
4970 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4972 asm, ".4s", ".4h", ".4h",
4973 [(set (v4i32 V128:$dst),
4974 (add (v4i32 V128:$Rd),
4975 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
4976 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4978 asm#"2", ".4s", ".8h", ".8h",
4979 [(set (v4i32 V128:$dst),
4980 (add (v4i32 V128:$Rd),
4981 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4982 (extract_high_v8i16 V128:$Rm))))))]>;
4983 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4985 asm, ".2d", ".2s", ".2s",
4986 [(set (v2i64 V128:$dst),
4987 (add (v2i64 V128:$Rd),
4988 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
4989 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4991 asm#"2", ".2d", ".4s", ".4s",
4992 [(set (v2i64 V128:$dst),
4993 (add (v2i64 V128:$Rd),
4994 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4995 (extract_high_v4i32 V128:$Rm))))))]>;
4998 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
4999 SDPatternOperator OpNode = null_frag> {
5000 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5002 asm, ".8h", ".8b", ".8b",
5003 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5004 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5006 asm#"2", ".8h", ".16b", ".16b",
5007 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5008 (extract_high_v16i8 V128:$Rm)))]>;
5009 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5011 asm, ".4s", ".4h", ".4h",
5012 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5013 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5015 asm#"2", ".4s", ".8h", ".8h",
5016 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5017 (extract_high_v8i16 V128:$Rm)))]>;
5018 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5020 asm, ".2d", ".2s", ".2s",
5021 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5022 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5024 asm#"2", ".2d", ".4s", ".4s",
5025 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5026 (extract_high_v4i32 V128:$Rm)))]>;
5029 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5031 SDPatternOperator OpNode> {
5032 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5034 asm, ".8h", ".8b", ".8b",
5035 [(set (v8i16 V128:$dst),
5036 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5037 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5039 asm#"2", ".8h", ".16b", ".16b",
5040 [(set (v8i16 V128:$dst),
5041 (OpNode (v8i16 V128:$Rd),
5042 (extract_high_v16i8 V128:$Rn),
5043 (extract_high_v16i8 V128:$Rm)))]>;
5044 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5046 asm, ".4s", ".4h", ".4h",
5047 [(set (v4i32 V128:$dst),
5048 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5049 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5051 asm#"2", ".4s", ".8h", ".8h",
5052 [(set (v4i32 V128:$dst),
5053 (OpNode (v4i32 V128:$Rd),
5054 (extract_high_v8i16 V128:$Rn),
5055 (extract_high_v8i16 V128:$Rm)))]>;
5056 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5058 asm, ".2d", ".2s", ".2s",
5059 [(set (v2i64 V128:$dst),
5060 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5061 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5063 asm#"2", ".2d", ".4s", ".4s",
5064 [(set (v2i64 V128:$dst),
5065 (OpNode (v2i64 V128:$Rd),
5066 (extract_high_v4i32 V128:$Rn),
5067 (extract_high_v4i32 V128:$Rm)))]>;
5070 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5071 SDPatternOperator Accum> {
5072 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5074 asm, ".4s", ".4h", ".4h",
5075 [(set (v4i32 V128:$dst),
5076 (Accum (v4i32 V128:$Rd),
5077 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5078 (v4i16 V64:$Rm)))))]>;
5079 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5081 asm#"2", ".4s", ".8h", ".8h",
5082 [(set (v4i32 V128:$dst),
5083 (Accum (v4i32 V128:$Rd),
5084 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5085 (extract_high_v8i16 V128:$Rm)))))]>;
5086 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5088 asm, ".2d", ".2s", ".2s",
5089 [(set (v2i64 V128:$dst),
5090 (Accum (v2i64 V128:$Rd),
5091 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5092 (v2i32 V64:$Rm)))))]>;
5093 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5095 asm#"2", ".2d", ".4s", ".4s",
5096 [(set (v2i64 V128:$dst),
5097 (Accum (v2i64 V128:$Rd),
5098 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5099 (extract_high_v4i32 V128:$Rm)))))]>;
5102 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5103 SDPatternOperator OpNode> {
5104 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5106 asm, ".8h", ".8h", ".8b",
5107 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5108 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5110 asm#"2", ".8h", ".8h", ".16b",
5111 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5112 (extract_high_v16i8 V128:$Rm)))]>;
5113 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5115 asm, ".4s", ".4s", ".4h",
5116 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5117 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5119 asm#"2", ".4s", ".4s", ".8h",
5120 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5121 (extract_high_v8i16 V128:$Rm)))]>;
5122 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5124 asm, ".2d", ".2d", ".2s",
5125 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5126 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5128 asm#"2", ".2d", ".2d", ".4s",
5129 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5130 (extract_high_v4i32 V128:$Rm)))]>;
5133 //----------------------------------------------------------------------------
5134 // AdvSIMD bitwise extract from vector
5135 //----------------------------------------------------------------------------
5137 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5138 string asm, string kind>
5139 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5140 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5141 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5142 [(set (vty regtype:$Rd),
5143 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5150 let Inst{30} = size;
5151 let Inst{29-21} = 0b101110000;
5152 let Inst{20-16} = Rm;
5154 let Inst{14-11} = imm;
5161 multiclass SIMDBitwiseExtract<string asm> {
5162 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5165 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5168 //----------------------------------------------------------------------------
5169 // AdvSIMD zip vector
5170 //----------------------------------------------------------------------------
5172 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5173 string asm, string kind, SDNode OpNode, ValueType valty>
5174 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5175 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5176 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5177 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5183 let Inst{30} = size{0};
5184 let Inst{29-24} = 0b001110;
5185 let Inst{23-22} = size{2-1};
5187 let Inst{20-16} = Rm;
5189 let Inst{14-12} = opc;
5190 let Inst{11-10} = 0b10;
5195 multiclass SIMDZipVector<bits<3>opc, string asm,
5197 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5198 asm, ".8b", OpNode, v8i8>;
5199 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5200 asm, ".16b", OpNode, v16i8>;
5201 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5202 asm, ".4h", OpNode, v4i16>;
5203 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5204 asm, ".8h", OpNode, v8i16>;
5205 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5206 asm, ".2s", OpNode, v2i32>;
5207 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5208 asm, ".4s", OpNode, v4i32>;
5209 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5210 asm, ".2d", OpNode, v2i64>;
5212 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5213 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5214 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5215 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5216 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5217 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5220 //----------------------------------------------------------------------------
5221 // AdvSIMD three register scalar instructions
5222 //----------------------------------------------------------------------------
5224 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5225 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5226 RegisterClass regtype, string asm,
5228 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5229 "\t$Rd, $Rn, $Rm", "", pattern>,
5234 let Inst{31-30} = 0b01;
5236 let Inst{28-24} = 0b11110;
5237 let Inst{23-22} = size;
5239 let Inst{20-16} = Rm;
5240 let Inst{15-11} = opcode;
5246 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5247 SDPatternOperator OpNode> {
5248 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5249 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5252 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5253 SDPatternOperator OpNode> {
5254 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5255 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5256 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5257 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5258 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5260 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5261 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5262 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5263 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5266 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5267 SDPatternOperator OpNode> {
5268 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5269 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5270 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5273 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5274 SDPatternOperator OpNode = null_frag> {
5275 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5276 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5277 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5278 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5279 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5282 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5283 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5286 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5287 SDPatternOperator OpNode = null_frag> {
5288 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5289 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5290 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5291 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5292 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5295 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5296 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5299 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5300 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5301 : I<oops, iops, asm,
5302 "\t$Rd, $Rn, $Rm", cstr, pat>,
5307 let Inst{31-30} = 0b01;
5309 let Inst{28-24} = 0b11110;
5310 let Inst{23-22} = size;
5312 let Inst{20-16} = Rm;
5313 let Inst{15-11} = opcode;
5319 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5320 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5321 SDPatternOperator OpNode = null_frag> {
5322 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5324 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5325 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5327 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5328 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5331 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5332 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5333 SDPatternOperator OpNode = null_frag> {
5334 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5336 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5337 asm, "$Rd = $dst", []>;
5338 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5340 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5342 [(set (i64 FPR64:$dst),
5343 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5346 //----------------------------------------------------------------------------
5347 // AdvSIMD two register scalar instructions
5348 //----------------------------------------------------------------------------
5350 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5351 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5352 RegisterClass regtype, RegisterClass regtype2,
5353 string asm, list<dag> pat>
5354 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5355 "\t$Rd, $Rn", "", pat>,
5359 let Inst{31-30} = 0b01;
5361 let Inst{28-24} = 0b11110;
5362 let Inst{23-22} = size;
5363 let Inst{21-17} = 0b10000;
5364 let Inst{16-12} = opcode;
5365 let Inst{11-10} = 0b10;
5370 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5371 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5372 RegisterClass regtype, RegisterClass regtype2,
5373 string asm, list<dag> pat>
5374 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5375 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5379 let Inst{31-30} = 0b01;
5381 let Inst{28-24} = 0b11110;
5382 let Inst{23-22} = size;
5383 let Inst{21-17} = 0b10000;
5384 let Inst{16-12} = opcode;
5385 let Inst{11-10} = 0b10;
5391 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5392 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5393 RegisterClass regtype, string asm, string zero>
5394 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5395 "\t$Rd, $Rn, #" # zero, "", []>,
5399 let Inst{31-30} = 0b01;
5401 let Inst{28-24} = 0b11110;
5402 let Inst{23-22} = size;
5403 let Inst{21-17} = 0b10000;
5404 let Inst{16-12} = opcode;
5405 let Inst{11-10} = 0b10;
5410 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5411 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5412 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5416 let Inst{31-17} = 0b011111100110000;
5417 let Inst{16-12} = opcode;
5418 let Inst{11-10} = 0b10;
5423 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5424 SDPatternOperator OpNode> {
5425 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5427 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5428 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5431 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5432 SDPatternOperator OpNode> {
5433 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5434 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5436 def : InstAlias<asm # " $Rd, $Rn, #0",
5437 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5438 def : InstAlias<asm # " $Rd, $Rn, #0",
5439 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5441 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5442 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5445 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5446 SDPatternOperator OpNode = null_frag> {
5447 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5448 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5450 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5451 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5454 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5455 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5456 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5459 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5460 SDPatternOperator OpNode> {
5461 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5462 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5463 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5464 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5467 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5468 SDPatternOperator OpNode = null_frag> {
5469 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5470 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5471 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5472 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5473 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5474 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5475 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5478 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5479 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5482 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5484 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5485 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5486 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5487 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5488 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5489 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5490 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5493 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5494 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5499 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5500 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5501 SDPatternOperator OpNode = null_frag> {
5502 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5503 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5504 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5505 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5508 //----------------------------------------------------------------------------
5509 // AdvSIMD scalar pairwise instructions
5510 //----------------------------------------------------------------------------
5512 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5513 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5514 RegisterOperand regtype, RegisterOperand vectype,
5515 string asm, string kind>
5516 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5517 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5521 let Inst{31-30} = 0b01;
5523 let Inst{28-24} = 0b11110;
5524 let Inst{23-22} = size;
5525 let Inst{21-17} = 0b11000;
5526 let Inst{16-12} = opcode;
5527 let Inst{11-10} = 0b10;
5532 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5533 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5537 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5538 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5540 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5544 //----------------------------------------------------------------------------
5545 // AdvSIMD across lanes instructions
5546 //----------------------------------------------------------------------------
5548 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5549 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5550 RegisterClass regtype, RegisterOperand vectype,
5551 string asm, string kind, list<dag> pattern>
5552 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5553 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5560 let Inst{28-24} = 0b01110;
5561 let Inst{23-22} = size;
5562 let Inst{21-17} = 0b11000;
5563 let Inst{16-12} = opcode;
5564 let Inst{11-10} = 0b10;
5569 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5571 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5573 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5575 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5577 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5579 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5583 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5584 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5586 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5588 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5590 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5592 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5596 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5598 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5600 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5603 //----------------------------------------------------------------------------
5604 // AdvSIMD INS/DUP instructions
5605 //----------------------------------------------------------------------------
5607 // FIXME: There has got to be a better way to factor these. ugh.
5609 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5610 string operands, string constraints, list<dag> pattern>
5611 : I<outs, ins, asm, operands, constraints, pattern>,
5618 let Inst{28-21} = 0b01110000;
5625 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5626 RegisterOperand vecreg, RegisterClass regtype>
5627 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5628 "{\t$Rd" # size # ", $Rn" #
5629 "|" # size # "\t$Rd, $Rn}", "",
5630 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5631 let Inst{20-16} = imm5;
5632 let Inst{14-11} = 0b0001;
5635 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5636 ValueType vectype, ValueType insreg,
5637 RegisterOperand vecreg, Operand idxtype,
5638 ValueType elttype, SDNode OpNode>
5639 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5640 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5641 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5642 [(set (vectype vecreg:$Rd),
5643 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5644 let Inst{14-11} = 0b0000;
5647 class SIMDDup64FromElement
5648 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5649 VectorIndexD, i64, AArch64duplane64> {
5652 let Inst{19-16} = 0b1000;
5655 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5656 RegisterOperand vecreg>
5657 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5658 VectorIndexS, i64, AArch64duplane32> {
5660 let Inst{20-19} = idx;
5661 let Inst{18-16} = 0b100;
5664 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5665 RegisterOperand vecreg>
5666 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5667 VectorIndexH, i64, AArch64duplane16> {
5669 let Inst{20-18} = idx;
5670 let Inst{17-16} = 0b10;
5673 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5674 RegisterOperand vecreg>
5675 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5676 VectorIndexB, i64, AArch64duplane8> {
5678 let Inst{20-17} = idx;
5682 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5683 Operand idxtype, string asm, list<dag> pattern>
5684 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5685 "{\t$Rd, $Rn" # size # "$idx" #
5686 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5687 let Inst{14-11} = imm4;
5690 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5692 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5693 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5695 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5696 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5698 class SIMDMovAlias<string asm, string size, Instruction inst,
5699 RegisterClass regtype, Operand idxtype>
5700 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5701 "|" # size # "\t$dst, $src$idx}",
5702 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5705 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5707 let Inst{20-17} = idx;
5710 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5712 let Inst{20-17} = idx;
5715 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5717 let Inst{20-18} = idx;
5718 let Inst{17-16} = 0b10;
5720 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5722 let Inst{20-18} = idx;
5723 let Inst{17-16} = 0b10;
5725 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5727 let Inst{20-19} = idx;
5728 let Inst{18-16} = 0b100;
5733 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5735 let Inst{20-17} = idx;
5738 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5740 let Inst{20-18} = idx;
5741 let Inst{17-16} = 0b10;
5743 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5745 let Inst{20-19} = idx;
5746 let Inst{18-16} = 0b100;
5748 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5751 let Inst{19-16} = 0b1000;
5753 def : SIMDMovAlias<"mov", ".s",
5754 !cast<Instruction>(NAME#"vi32"),
5755 GPR32, VectorIndexS>;
5756 def : SIMDMovAlias<"mov", ".d",
5757 !cast<Instruction>(NAME#"vi64"),
5758 GPR64, VectorIndexD>;
5761 class SIMDInsFromMain<string size, ValueType vectype,
5762 RegisterClass regtype, Operand idxtype>
5763 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5764 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5765 "{\t$Rd" # size # "$idx, $Rn" #
5766 "|" # size # "\t$Rd$idx, $Rn}",
5769 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5770 let Inst{14-11} = 0b0011;
5773 class SIMDInsFromElement<string size, ValueType vectype,
5774 ValueType elttype, Operand idxtype>
5775 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5776 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5777 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5778 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5783 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5786 class SIMDInsMainMovAlias<string size, Instruction inst,
5787 RegisterClass regtype, Operand idxtype>
5788 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5789 "|" # size #"\t$dst$idx, $src}",
5790 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5791 class SIMDInsElementMovAlias<string size, Instruction inst,
5793 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5794 # "|" # size #" $dst$idx, $src$idx2}",
5795 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5798 multiclass SIMDIns {
5799 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5801 let Inst{20-17} = idx;
5804 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5806 let Inst{20-18} = idx;
5807 let Inst{17-16} = 0b10;
5809 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5811 let Inst{20-19} = idx;
5812 let Inst{18-16} = 0b100;
5814 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5817 let Inst{19-16} = 0b1000;
5820 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5823 let Inst{20-17} = idx;
5825 let Inst{14-11} = idx2;
5827 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5830 let Inst{20-18} = idx;
5831 let Inst{17-16} = 0b10;
5832 let Inst{14-12} = idx2;
5835 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5838 let Inst{20-19} = idx;
5839 let Inst{18-16} = 0b100;
5840 let Inst{14-13} = idx2;
5841 let Inst{12-11} = 0;
5843 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5847 let Inst{19-16} = 0b1000;
5848 let Inst{14} = idx2;
5849 let Inst{13-11} = 0;
5852 // For all forms of the INS instruction, the "mov" mnemonic is the
5853 // preferred alias. Why they didn't just call the instruction "mov" in
5854 // the first place is a very good question indeed...
5855 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5856 GPR32, VectorIndexB>;
5857 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5858 GPR32, VectorIndexH>;
5859 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5860 GPR32, VectorIndexS>;
5861 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5862 GPR64, VectorIndexD>;
5864 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5866 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5868 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5870 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5874 //----------------------------------------------------------------------------
5876 //----------------------------------------------------------------------------
5878 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5879 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5880 RegisterOperand listtype, string asm, string kind>
5881 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5882 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5889 let Inst{29-21} = 0b001110000;
5890 let Inst{20-16} = Vm;
5892 let Inst{14-13} = len;
5894 let Inst{11-10} = 0b00;
5899 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5900 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5901 RegisterOperand listtype, string asm, string kind>
5902 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5903 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
5910 let Inst{29-21} = 0b001110000;
5911 let Inst{20-16} = Vm;
5913 let Inst{14-13} = len;
5915 let Inst{11-10} = 0b00;
5920 class SIMDTableLookupAlias<string asm, Instruction inst,
5921 RegisterOperand vectype, RegisterOperand listtype>
5922 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
5923 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
5925 multiclass SIMDTableLookup<bit op, string asm> {
5926 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
5928 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
5930 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
5932 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
5934 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
5936 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
5938 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
5940 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
5943 def : SIMDTableLookupAlias<asm # ".8b",
5944 !cast<Instruction>(NAME#"v8i8One"),
5945 V64, VecListOne128>;
5946 def : SIMDTableLookupAlias<asm # ".8b",
5947 !cast<Instruction>(NAME#"v8i8Two"),
5948 V64, VecListTwo128>;
5949 def : SIMDTableLookupAlias<asm # ".8b",
5950 !cast<Instruction>(NAME#"v8i8Three"),
5951 V64, VecListThree128>;
5952 def : SIMDTableLookupAlias<asm # ".8b",
5953 !cast<Instruction>(NAME#"v8i8Four"),
5954 V64, VecListFour128>;
5955 def : SIMDTableLookupAlias<asm # ".16b",
5956 !cast<Instruction>(NAME#"v16i8One"),
5957 V128, VecListOne128>;
5958 def : SIMDTableLookupAlias<asm # ".16b",
5959 !cast<Instruction>(NAME#"v16i8Two"),
5960 V128, VecListTwo128>;
5961 def : SIMDTableLookupAlias<asm # ".16b",
5962 !cast<Instruction>(NAME#"v16i8Three"),
5963 V128, VecListThree128>;
5964 def : SIMDTableLookupAlias<asm # ".16b",
5965 !cast<Instruction>(NAME#"v16i8Four"),
5966 V128, VecListFour128>;
5969 multiclass SIMDTableLookupTied<bit op, string asm> {
5970 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
5972 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
5974 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
5976 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
5978 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
5980 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
5982 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
5984 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
5987 def : SIMDTableLookupAlias<asm # ".8b",
5988 !cast<Instruction>(NAME#"v8i8One"),
5989 V64, VecListOne128>;
5990 def : SIMDTableLookupAlias<asm # ".8b",
5991 !cast<Instruction>(NAME#"v8i8Two"),
5992 V64, VecListTwo128>;
5993 def : SIMDTableLookupAlias<asm # ".8b",
5994 !cast<Instruction>(NAME#"v8i8Three"),
5995 V64, VecListThree128>;
5996 def : SIMDTableLookupAlias<asm # ".8b",
5997 !cast<Instruction>(NAME#"v8i8Four"),
5998 V64, VecListFour128>;
5999 def : SIMDTableLookupAlias<asm # ".16b",
6000 !cast<Instruction>(NAME#"v16i8One"),
6001 V128, VecListOne128>;
6002 def : SIMDTableLookupAlias<asm # ".16b",
6003 !cast<Instruction>(NAME#"v16i8Two"),
6004 V128, VecListTwo128>;
6005 def : SIMDTableLookupAlias<asm # ".16b",
6006 !cast<Instruction>(NAME#"v16i8Three"),
6007 V128, VecListThree128>;
6008 def : SIMDTableLookupAlias<asm # ".16b",
6009 !cast<Instruction>(NAME#"v16i8Four"),
6010 V128, VecListFour128>;
6014 //----------------------------------------------------------------------------
6015 // AdvSIMD scalar CPY
6016 //----------------------------------------------------------------------------
6017 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6018 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6019 string kind, Operand idxtype>
6020 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6021 "{\t$dst, $src" # kind # "$idx" #
6022 "|\t$dst, $src$idx}", "", []>,
6026 let Inst{31-21} = 0b01011110000;
6027 let Inst{15-10} = 0b000001;
6028 let Inst{9-5} = src;
6029 let Inst{4-0} = dst;
6032 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6033 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6034 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6035 # "|\t$dst, $src$index}",
6036 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6039 multiclass SIMDScalarCPY<string asm> {
6040 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6042 let Inst{20-17} = idx;
6045 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6047 let Inst{20-18} = idx;
6048 let Inst{17-16} = 0b10;
6050 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6052 let Inst{20-19} = idx;
6053 let Inst{18-16} = 0b100;
6055 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6058 let Inst{19-16} = 0b1000;
6061 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6062 VectorIndexD:$idx)))),
6063 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6065 // 'DUP' mnemonic aliases.
6066 def : SIMDScalarCPYAlias<"dup", ".b",
6067 !cast<Instruction>(NAME#"i8"),
6068 FPR8, V128, VectorIndexB>;
6069 def : SIMDScalarCPYAlias<"dup", ".h",
6070 !cast<Instruction>(NAME#"i16"),
6071 FPR16, V128, VectorIndexH>;
6072 def : SIMDScalarCPYAlias<"dup", ".s",
6073 !cast<Instruction>(NAME#"i32"),
6074 FPR32, V128, VectorIndexS>;
6075 def : SIMDScalarCPYAlias<"dup", ".d",
6076 !cast<Instruction>(NAME#"i64"),
6077 FPR64, V128, VectorIndexD>;
6080 //----------------------------------------------------------------------------
6081 // AdvSIMD modified immediate instructions
6082 //----------------------------------------------------------------------------
6084 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6085 string asm, string op_string,
6086 string cstr, list<dag> pattern>
6087 : I<oops, iops, asm, op_string, cstr, pattern>,
6094 let Inst{28-19} = 0b0111100000;
6095 let Inst{18-16} = imm8{7-5};
6096 let Inst{11-10} = 0b01;
6097 let Inst{9-5} = imm8{4-0};
6101 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6102 Operand immtype, dag opt_shift_iop,
6103 string opt_shift, string asm, string kind,
6105 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6106 !con((ins immtype:$imm8), opt_shift_iop), asm,
6107 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6108 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6110 let DecoderMethod = "DecodeModImmInstruction";
6113 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6114 Operand immtype, dag opt_shift_iop,
6115 string opt_shift, string asm, string kind,
6117 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6118 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6119 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6120 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6121 "$Rd = $dst", pattern> {
6122 let DecoderMethod = "DecodeModImmTiedInstruction";
6125 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6126 RegisterOperand vectype, string asm,
6127 string kind, list<dag> pattern>
6128 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6129 (ins logical_vec_shift:$shift),
6130 "$shift", asm, kind, pattern> {
6132 let Inst{15} = b15_b12{1};
6133 let Inst{14-13} = shift;
6134 let Inst{12} = b15_b12{0};
6137 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6138 RegisterOperand vectype, string asm,
6139 string kind, list<dag> pattern>
6140 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6141 (ins logical_vec_shift:$shift),
6142 "$shift", asm, kind, pattern> {
6144 let Inst{15} = b15_b12{1};
6145 let Inst{14-13} = shift;
6146 let Inst{12} = b15_b12{0};
6150 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6151 RegisterOperand vectype, string asm,
6152 string kind, list<dag> pattern>
6153 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6154 (ins logical_vec_hw_shift:$shift),
6155 "$shift", asm, kind, pattern> {
6157 let Inst{15} = b15_b12{1};
6159 let Inst{13} = shift{0};
6160 let Inst{12} = b15_b12{0};
6163 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6164 RegisterOperand vectype, string asm,
6165 string kind, list<dag> pattern>
6166 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6167 (ins logical_vec_hw_shift:$shift),
6168 "$shift", asm, kind, pattern> {
6170 let Inst{15} = b15_b12{1};
6172 let Inst{13} = shift{0};
6173 let Inst{12} = b15_b12{0};
6176 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6178 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6180 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6183 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6185 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6189 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6190 bits<2> w_cmode, string asm,
6192 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6194 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6196 (i32 imm:$shift)))]>;
6197 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6199 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6201 (i32 imm:$shift)))]>;
6203 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6205 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6207 (i32 imm:$shift)))]>;
6208 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6210 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6212 (i32 imm:$shift)))]>;
6215 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6216 RegisterOperand vectype, string asm,
6217 string kind, list<dag> pattern>
6218 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6219 (ins move_vec_shift:$shift),
6220 "$shift", asm, kind, pattern> {
6222 let Inst{15-13} = cmode{3-1};
6223 let Inst{12} = shift;
6226 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6227 RegisterOperand vectype,
6228 Operand imm_type, string asm,
6229 string kind, list<dag> pattern>
6230 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6231 asm, kind, pattern> {
6232 let Inst{15-12} = cmode;
6235 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6237 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6238 "\t$Rd, $imm8", "", pattern> {
6239 let Inst{15-12} = cmode;
6240 let DecoderMethod = "DecodeModImmInstruction";
6243 //----------------------------------------------------------------------------
6244 // AdvSIMD indexed element
6245 //----------------------------------------------------------------------------
6247 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6248 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6249 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6250 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6251 string apple_kind, string dst_kind, string lhs_kind,
6252 string rhs_kind, list<dag> pattern>
6253 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6255 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6256 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6265 let Inst{28} = Scalar;
6266 let Inst{27-24} = 0b1111;
6267 let Inst{23-22} = size;
6268 // Bit 21 must be set by the derived class.
6269 let Inst{20-16} = Rm;
6270 let Inst{15-12} = opc;
6271 // Bit 11 must be set by the derived class.
6277 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6278 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6279 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6280 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6281 string apple_kind, string dst_kind, string lhs_kind,
6282 string rhs_kind, list<dag> pattern>
6283 : I<(outs dst_reg:$dst),
6284 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6285 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6286 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6295 let Inst{28} = Scalar;
6296 let Inst{27-24} = 0b1111;
6297 let Inst{23-22} = size;
6298 // Bit 21 must be set by the derived class.
6299 let Inst{20-16} = Rm;
6300 let Inst{15-12} = opc;
6301 // Bit 11 must be set by the derived class.
6307 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
6308 SDPatternOperator OpNode> {
6309 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6312 asm, ".2s", ".2s", ".2s", ".s",
6313 [(set (v2f32 V64:$Rd),
6314 (OpNode (v2f32 V64:$Rn),
6315 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6317 let Inst{11} = idx{1};
6318 let Inst{21} = idx{0};
6321 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6324 asm, ".4s", ".4s", ".4s", ".s",
6325 [(set (v4f32 V128:$Rd),
6326 (OpNode (v4f32 V128:$Rn),
6327 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6329 let Inst{11} = idx{1};
6330 let Inst{21} = idx{0};
6333 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6336 asm, ".2d", ".2d", ".2d", ".d",
6337 [(set (v2f64 V128:$Rd),
6338 (OpNode (v2f64 V128:$Rn),
6339 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6341 let Inst{11} = idx{0};
6345 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6346 FPR32Op, FPR32Op, V128, VectorIndexS,
6347 asm, ".s", "", "", ".s",
6348 [(set (f32 FPR32Op:$Rd),
6349 (OpNode (f32 FPR32Op:$Rn),
6350 (f32 (vector_extract (v4f32 V128:$Rm),
6351 VectorIndexS:$idx))))]> {
6353 let Inst{11} = idx{1};
6354 let Inst{21} = idx{0};
6357 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6358 FPR64Op, FPR64Op, V128, VectorIndexD,
6359 asm, ".d", "", "", ".d",
6360 [(set (f64 FPR64Op:$Rd),
6361 (OpNode (f64 FPR64Op:$Rn),
6362 (f64 (vector_extract (v2f64 V128:$Rm),
6363 VectorIndexD:$idx))))]> {
6365 let Inst{11} = idx{0};
6370 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6371 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6372 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6373 (AArch64duplane32 (v4f32 V128:$Rm),
6374 VectorIndexS:$idx))),
6375 (!cast<Instruction>(INST # v2i32_indexed)
6376 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6377 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6378 (AArch64dup (f32 FPR32Op:$Rm)))),
6379 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6380 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6383 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6384 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6385 (AArch64duplane32 (v4f32 V128:$Rm),
6386 VectorIndexS:$idx))),
6387 (!cast<Instruction>(INST # "v4i32_indexed")
6388 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6389 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6390 (AArch64dup (f32 FPR32Op:$Rm)))),
6391 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6392 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6394 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6395 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6396 (AArch64duplane64 (v2f64 V128:$Rm),
6397 VectorIndexD:$idx))),
6398 (!cast<Instruction>(INST # "v2i64_indexed")
6399 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6400 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6401 (AArch64dup (f64 FPR64Op:$Rm)))),
6402 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6403 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6405 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6406 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6407 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6408 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6409 V128:$Rm, VectorIndexS:$idx)>;
6410 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6411 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6412 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6413 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6415 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6416 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6417 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6418 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6419 V128:$Rm, VectorIndexD:$idx)>;
6422 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6423 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6425 asm, ".2s", ".2s", ".2s", ".s", []> {
6427 let Inst{11} = idx{1};
6428 let Inst{21} = idx{0};
6431 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6434 asm, ".4s", ".4s", ".4s", ".s", []> {
6436 let Inst{11} = idx{1};
6437 let Inst{21} = idx{0};
6440 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6443 asm, ".2d", ".2d", ".2d", ".d", []> {
6445 let Inst{11} = idx{0};
6450 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6451 FPR32Op, FPR32Op, V128, VectorIndexS,
6452 asm, ".s", "", "", ".s", []> {
6454 let Inst{11} = idx{1};
6455 let Inst{21} = idx{0};
6458 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6459 FPR64Op, FPR64Op, V128, VectorIndexD,
6460 asm, ".d", "", "", ".d", []> {
6462 let Inst{11} = idx{0};
6467 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6468 SDPatternOperator OpNode> {
6469 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6470 V128_lo, VectorIndexH,
6471 asm, ".4h", ".4h", ".4h", ".h",
6472 [(set (v4i16 V64:$Rd),
6473 (OpNode (v4i16 V64:$Rn),
6474 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6476 let Inst{11} = idx{2};
6477 let Inst{21} = idx{1};
6478 let Inst{20} = idx{0};
6481 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6483 V128_lo, VectorIndexH,
6484 asm, ".8h", ".8h", ".8h", ".h",
6485 [(set (v8i16 V128:$Rd),
6486 (OpNode (v8i16 V128:$Rn),
6487 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6489 let Inst{11} = idx{2};
6490 let Inst{21} = idx{1};
6491 let Inst{20} = idx{0};
6494 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6497 asm, ".2s", ".2s", ".2s", ".s",
6498 [(set (v2i32 V64:$Rd),
6499 (OpNode (v2i32 V64:$Rn),
6500 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6502 let Inst{11} = idx{1};
6503 let Inst{21} = idx{0};
6506 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6509 asm, ".4s", ".4s", ".4s", ".s",
6510 [(set (v4i32 V128:$Rd),
6511 (OpNode (v4i32 V128:$Rn),
6512 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6514 let Inst{11} = idx{1};
6515 let Inst{21} = idx{0};
6518 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6519 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6520 asm, ".h", "", "", ".h", []> {
6522 let Inst{11} = idx{2};
6523 let Inst{21} = idx{1};
6524 let Inst{20} = idx{0};
6527 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6528 FPR32Op, FPR32Op, V128, VectorIndexS,
6529 asm, ".s", "", "", ".s",
6530 [(set (i32 FPR32Op:$Rd),
6531 (OpNode FPR32Op:$Rn,
6532 (i32 (vector_extract (v4i32 V128:$Rm),
6533 VectorIndexS:$idx))))]> {
6535 let Inst{11} = idx{1};
6536 let Inst{21} = idx{0};
6540 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6541 SDPatternOperator OpNode> {
6542 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6544 V128_lo, VectorIndexH,
6545 asm, ".4h", ".4h", ".4h", ".h",
6546 [(set (v4i16 V64:$Rd),
6547 (OpNode (v4i16 V64:$Rn),
6548 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6550 let Inst{11} = idx{2};
6551 let Inst{21} = idx{1};
6552 let Inst{20} = idx{0};
6555 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6557 V128_lo, VectorIndexH,
6558 asm, ".8h", ".8h", ".8h", ".h",
6559 [(set (v8i16 V128:$Rd),
6560 (OpNode (v8i16 V128:$Rn),
6561 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6563 let Inst{11} = idx{2};
6564 let Inst{21} = idx{1};
6565 let Inst{20} = idx{0};
6568 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6571 asm, ".2s", ".2s", ".2s", ".s",
6572 [(set (v2i32 V64:$Rd),
6573 (OpNode (v2i32 V64:$Rn),
6574 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6576 let Inst{11} = idx{1};
6577 let Inst{21} = idx{0};
6580 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6583 asm, ".4s", ".4s", ".4s", ".s",
6584 [(set (v4i32 V128:$Rd),
6585 (OpNode (v4i32 V128:$Rn),
6586 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6588 let Inst{11} = idx{1};
6589 let Inst{21} = idx{0};
6593 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6594 SDPatternOperator OpNode> {
6595 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6596 V128_lo, VectorIndexH,
6597 asm, ".4h", ".4h", ".4h", ".h",
6598 [(set (v4i16 V64:$dst),
6599 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6600 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6602 let Inst{11} = idx{2};
6603 let Inst{21} = idx{1};
6604 let Inst{20} = idx{0};
6607 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6609 V128_lo, VectorIndexH,
6610 asm, ".8h", ".8h", ".8h", ".h",
6611 [(set (v8i16 V128:$dst),
6612 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6613 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6615 let Inst{11} = idx{2};
6616 let Inst{21} = idx{1};
6617 let Inst{20} = idx{0};
6620 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6623 asm, ".2s", ".2s", ".2s", ".s",
6624 [(set (v2i32 V64:$dst),
6625 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6626 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6628 let Inst{11} = idx{1};
6629 let Inst{21} = idx{0};
6632 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6635 asm, ".4s", ".4s", ".4s", ".s",
6636 [(set (v4i32 V128:$dst),
6637 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6638 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6640 let Inst{11} = idx{1};
6641 let Inst{21} = idx{0};
6645 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6646 SDPatternOperator OpNode> {
6647 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6649 V128_lo, VectorIndexH,
6650 asm, ".4s", ".4s", ".4h", ".h",
6651 [(set (v4i32 V128:$Rd),
6652 (OpNode (v4i16 V64:$Rn),
6653 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6655 let Inst{11} = idx{2};
6656 let Inst{21} = idx{1};
6657 let Inst{20} = idx{0};
6660 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6662 V128_lo, VectorIndexH,
6663 asm#"2", ".4s", ".4s", ".8h", ".h",
6664 [(set (v4i32 V128:$Rd),
6665 (OpNode (extract_high_v8i16 V128:$Rn),
6666 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6667 VectorIndexH:$idx))))]> {
6670 let Inst{11} = idx{2};
6671 let Inst{21} = idx{1};
6672 let Inst{20} = idx{0};
6675 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6678 asm, ".2d", ".2d", ".2s", ".s",
6679 [(set (v2i64 V128:$Rd),
6680 (OpNode (v2i32 V64:$Rn),
6681 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6683 let Inst{11} = idx{1};
6684 let Inst{21} = idx{0};
6687 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6690 asm#"2", ".2d", ".2d", ".4s", ".s",
6691 [(set (v2i64 V128:$Rd),
6692 (OpNode (extract_high_v4i32 V128:$Rn),
6693 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6694 VectorIndexS:$idx))))]> {
6696 let Inst{11} = idx{1};
6697 let Inst{21} = idx{0};
6700 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6701 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6702 asm, ".h", "", "", ".h", []> {
6704 let Inst{11} = idx{2};
6705 let Inst{21} = idx{1};
6706 let Inst{20} = idx{0};
6709 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6710 FPR64Op, FPR32Op, V128, VectorIndexS,
6711 asm, ".s", "", "", ".s", []> {
6713 let Inst{11} = idx{1};
6714 let Inst{21} = idx{0};
6718 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6719 SDPatternOperator Accum> {
6720 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6722 V128_lo, VectorIndexH,
6723 asm, ".4s", ".4s", ".4h", ".h",
6724 [(set (v4i32 V128:$dst),
6725 (Accum (v4i32 V128:$Rd),
6726 (v4i32 (int_aarch64_neon_sqdmull
6728 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6729 VectorIndexH:$idx))))))]> {
6731 let Inst{11} = idx{2};
6732 let Inst{21} = idx{1};
6733 let Inst{20} = idx{0};
6736 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6737 // intermediate EXTRACT_SUBREG would be untyped.
6738 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6739 (i32 (vector_extract (v4i32
6740 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6741 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6742 VectorIndexH:$idx)))),
6745 (!cast<Instruction>(NAME # v4i16_indexed)
6746 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6747 V128_lo:$Rm, VectorIndexH:$idx),
6750 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6752 V128_lo, VectorIndexH,
6753 asm#"2", ".4s", ".4s", ".8h", ".h",
6754 [(set (v4i32 V128:$dst),
6755 (Accum (v4i32 V128:$Rd),
6756 (v4i32 (int_aarch64_neon_sqdmull
6757 (extract_high_v8i16 V128:$Rn),
6759 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6760 VectorIndexH:$idx))))))]> {
6762 let Inst{11} = idx{2};
6763 let Inst{21} = idx{1};
6764 let Inst{20} = idx{0};
6767 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6770 asm, ".2d", ".2d", ".2s", ".s",
6771 [(set (v2i64 V128:$dst),
6772 (Accum (v2i64 V128:$Rd),
6773 (v2i64 (int_aarch64_neon_sqdmull
6775 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
6776 VectorIndexS:$idx))))))]> {
6778 let Inst{11} = idx{1};
6779 let Inst{21} = idx{0};
6782 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6785 asm#"2", ".2d", ".2d", ".4s", ".s",
6786 [(set (v2i64 V128:$dst),
6787 (Accum (v2i64 V128:$Rd),
6788 (v2i64 (int_aarch64_neon_sqdmull
6789 (extract_high_v4i32 V128:$Rn),
6791 (AArch64duplane32 (v4i32 V128:$Rm),
6792 VectorIndexS:$idx))))))]> {
6794 let Inst{11} = idx{1};
6795 let Inst{21} = idx{0};
6798 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6799 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6800 asm, ".h", "", "", ".h", []> {
6802 let Inst{11} = idx{2};
6803 let Inst{21} = idx{1};
6804 let Inst{20} = idx{0};
6808 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6809 FPR64Op, FPR32Op, V128, VectorIndexS,
6810 asm, ".s", "", "", ".s",
6811 [(set (i64 FPR64Op:$dst),
6812 (Accum (i64 FPR64Op:$Rd),
6813 (i64 (int_aarch64_neon_sqdmulls_scalar
6815 (i32 (vector_extract (v4i32 V128:$Rm),
6816 VectorIndexS:$idx))))))]> {
6819 let Inst{11} = idx{1};
6820 let Inst{21} = idx{0};
6824 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6825 SDPatternOperator OpNode> {
6826 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6827 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6829 V128_lo, VectorIndexH,
6830 asm, ".4s", ".4s", ".4h", ".h",
6831 [(set (v4i32 V128:$Rd),
6832 (OpNode (v4i16 V64:$Rn),
6833 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6835 let Inst{11} = idx{2};
6836 let Inst{21} = idx{1};
6837 let Inst{20} = idx{0};
6840 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6842 V128_lo, VectorIndexH,
6843 asm#"2", ".4s", ".4s", ".8h", ".h",
6844 [(set (v4i32 V128:$Rd),
6845 (OpNode (extract_high_v8i16 V128:$Rn),
6846 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6847 VectorIndexH:$idx))))]> {
6850 let Inst{11} = idx{2};
6851 let Inst{21} = idx{1};
6852 let Inst{20} = idx{0};
6855 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6858 asm, ".2d", ".2d", ".2s", ".s",
6859 [(set (v2i64 V128:$Rd),
6860 (OpNode (v2i32 V64:$Rn),
6861 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6863 let Inst{11} = idx{1};
6864 let Inst{21} = idx{0};
6867 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6870 asm#"2", ".2d", ".2d", ".4s", ".s",
6871 [(set (v2i64 V128:$Rd),
6872 (OpNode (extract_high_v4i32 V128:$Rn),
6873 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6874 VectorIndexS:$idx))))]> {
6876 let Inst{11} = idx{1};
6877 let Inst{21} = idx{0};
6882 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6883 SDPatternOperator OpNode> {
6884 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6885 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6887 V128_lo, VectorIndexH,
6888 asm, ".4s", ".4s", ".4h", ".h",
6889 [(set (v4i32 V128:$dst),
6890 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6891 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6893 let Inst{11} = idx{2};
6894 let Inst{21} = idx{1};
6895 let Inst{20} = idx{0};
6898 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6900 V128_lo, VectorIndexH,
6901 asm#"2", ".4s", ".4s", ".8h", ".h",
6902 [(set (v4i32 V128:$dst),
6903 (OpNode (v4i32 V128:$Rd),
6904 (extract_high_v8i16 V128:$Rn),
6905 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6906 VectorIndexH:$idx))))]> {
6908 let Inst{11} = idx{2};
6909 let Inst{21} = idx{1};
6910 let Inst{20} = idx{0};
6913 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6916 asm, ".2d", ".2d", ".2s", ".s",
6917 [(set (v2i64 V128:$dst),
6918 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
6919 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6921 let Inst{11} = idx{1};
6922 let Inst{21} = idx{0};
6925 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6928 asm#"2", ".2d", ".2d", ".4s", ".s",
6929 [(set (v2i64 V128:$dst),
6930 (OpNode (v2i64 V128:$Rd),
6931 (extract_high_v4i32 V128:$Rn),
6932 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6933 VectorIndexS:$idx))))]> {
6935 let Inst{11} = idx{1};
6936 let Inst{21} = idx{0};
6941 //----------------------------------------------------------------------------
6942 // AdvSIMD scalar shift by immediate
6943 //----------------------------------------------------------------------------
6945 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6946 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
6947 RegisterClass regtype1, RegisterClass regtype2,
6948 Operand immtype, string asm, list<dag> pattern>
6949 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
6950 asm, "\t$Rd, $Rn, $imm", "", pattern>,
6955 let Inst{31-30} = 0b01;
6957 let Inst{28-23} = 0b111110;
6958 let Inst{22-16} = fixed_imm;
6959 let Inst{15-11} = opc;
6965 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6966 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
6967 RegisterClass regtype1, RegisterClass regtype2,
6968 Operand immtype, string asm, list<dag> pattern>
6969 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
6970 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
6975 let Inst{31-30} = 0b01;
6977 let Inst{28-23} = 0b111110;
6978 let Inst{22-16} = fixed_imm;
6979 let Inst{15-11} = opc;
6986 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
6987 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6988 FPR32, FPR32, vecshiftR32, asm, []> {
6989 let Inst{20-16} = imm{4-0};
6992 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6993 FPR64, FPR64, vecshiftR64, asm, []> {
6994 let Inst{21-16} = imm{5-0};
6998 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
6999 SDPatternOperator OpNode> {
7000 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7001 FPR64, FPR64, vecshiftR64, asm,
7002 [(set (i64 FPR64:$Rd),
7003 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7004 let Inst{21-16} = imm{5-0};
7007 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7008 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7011 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7012 SDPatternOperator OpNode = null_frag> {
7013 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7014 FPR64, FPR64, vecshiftR64, asm,
7015 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7016 (i32 vecshiftR64:$imm)))]> {
7017 let Inst{21-16} = imm{5-0};
7020 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7021 (i32 vecshiftR64:$imm))),
7022 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7026 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7027 SDPatternOperator OpNode> {
7028 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7029 FPR64, FPR64, vecshiftL64, asm,
7030 [(set (v1i64 FPR64:$Rd),
7031 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7032 let Inst{21-16} = imm{5-0};
7036 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7037 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7038 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7039 FPR64, FPR64, vecshiftL64, asm, []> {
7040 let Inst{21-16} = imm{5-0};
7044 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7045 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7046 SDPatternOperator OpNode = null_frag> {
7047 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7048 FPR8, FPR16, vecshiftR8, asm, []> {
7049 let Inst{18-16} = imm{2-0};
7052 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7053 FPR16, FPR32, vecshiftR16, asm, []> {
7054 let Inst{19-16} = imm{3-0};
7057 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7058 FPR32, FPR64, vecshiftR32, asm,
7059 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7060 let Inst{20-16} = imm{4-0};
7064 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7065 SDPatternOperator OpNode> {
7066 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7067 FPR8, FPR8, vecshiftL8, asm, []> {
7068 let Inst{18-16} = imm{2-0};
7071 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7072 FPR16, FPR16, vecshiftL16, asm, []> {
7073 let Inst{19-16} = imm{3-0};
7076 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7077 FPR32, FPR32, vecshiftL32, asm,
7078 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7079 let Inst{20-16} = imm{4-0};
7082 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7083 FPR64, FPR64, vecshiftL64, asm,
7084 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7085 let Inst{21-16} = imm{5-0};
7088 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7089 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7092 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7093 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7094 FPR8, FPR8, vecshiftR8, asm, []> {
7095 let Inst{18-16} = imm{2-0};
7098 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7099 FPR16, FPR16, vecshiftR16, asm, []> {
7100 let Inst{19-16} = imm{3-0};
7103 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7104 FPR32, FPR32, vecshiftR32, asm, []> {
7105 let Inst{20-16} = imm{4-0};
7108 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7109 FPR64, FPR64, vecshiftR64, asm, []> {
7110 let Inst{21-16} = imm{5-0};
7114 //----------------------------------------------------------------------------
7115 // AdvSIMD vector x indexed element
7116 //----------------------------------------------------------------------------
7118 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7119 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7120 RegisterOperand dst_reg, RegisterOperand src_reg,
7122 string asm, string dst_kind, string src_kind,
7124 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7125 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7126 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7133 let Inst{28-23} = 0b011110;
7134 let Inst{22-16} = fixed_imm;
7135 let Inst{15-11} = opc;
7141 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7142 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7143 RegisterOperand vectype1, RegisterOperand vectype2,
7145 string asm, string dst_kind, string src_kind,
7147 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7148 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7149 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7156 let Inst{28-23} = 0b011110;
7157 let Inst{22-16} = fixed_imm;
7158 let Inst{15-11} = opc;
7164 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7166 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7167 V64, V64, vecshiftR32,
7169 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7171 let Inst{20-16} = imm;
7174 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7175 V128, V128, vecshiftR32,
7177 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7179 let Inst{20-16} = imm;
7182 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7183 V128, V128, vecshiftR64,
7185 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7187 let Inst{21-16} = imm;
7191 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7193 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7194 V64, V64, vecshiftR32,
7196 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7198 let Inst{20-16} = imm;
7201 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7202 V128, V128, vecshiftR32,
7204 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7206 let Inst{20-16} = imm;
7209 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7210 V128, V128, vecshiftR64,
7212 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7214 let Inst{21-16} = imm;
7218 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7219 SDPatternOperator OpNode> {
7220 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7221 V64, V128, vecshiftR16Narrow,
7223 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7225 let Inst{18-16} = imm;
7228 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7229 V128, V128, vecshiftR16Narrow,
7230 asm#"2", ".16b", ".8h", []> {
7232 let Inst{18-16} = imm;
7233 let hasSideEffects = 0;
7236 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7237 V64, V128, vecshiftR32Narrow,
7239 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7241 let Inst{19-16} = imm;
7244 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7245 V128, V128, vecshiftR32Narrow,
7246 asm#"2", ".8h", ".4s", []> {
7248 let Inst{19-16} = imm;
7249 let hasSideEffects = 0;
7252 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7253 V64, V128, vecshiftR64Narrow,
7255 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7257 let Inst{20-16} = imm;
7260 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7261 V128, V128, vecshiftR64Narrow,
7262 asm#"2", ".4s", ".2d", []> {
7264 let Inst{20-16} = imm;
7265 let hasSideEffects = 0;
7268 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7269 // themselves, so put them here instead.
7271 // Patterns involving what's effectively an insert high and a normal
7272 // intrinsic, represented by CONCAT_VECTORS.
7273 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7274 vecshiftR16Narrow:$imm)),
7275 (!cast<Instruction>(NAME # "v16i8_shift")
7276 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7277 V128:$Rn, vecshiftR16Narrow:$imm)>;
7278 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7279 vecshiftR32Narrow:$imm)),
7280 (!cast<Instruction>(NAME # "v8i16_shift")
7281 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7282 V128:$Rn, vecshiftR32Narrow:$imm)>;
7283 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7284 vecshiftR64Narrow:$imm)),
7285 (!cast<Instruction>(NAME # "v4i32_shift")
7286 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7287 V128:$Rn, vecshiftR64Narrow:$imm)>;
7290 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7291 SDPatternOperator OpNode> {
7292 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7293 V64, V64, vecshiftL8,
7295 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7296 (i32 vecshiftL8:$imm)))]> {
7298 let Inst{18-16} = imm;
7301 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7302 V128, V128, vecshiftL8,
7303 asm, ".16b", ".16b",
7304 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7305 (i32 vecshiftL8:$imm)))]> {
7307 let Inst{18-16} = imm;
7310 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7311 V64, V64, vecshiftL16,
7313 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7314 (i32 vecshiftL16:$imm)))]> {
7316 let Inst{19-16} = imm;
7319 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7320 V128, V128, vecshiftL16,
7322 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7323 (i32 vecshiftL16:$imm)))]> {
7325 let Inst{19-16} = imm;
7328 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7329 V64, V64, vecshiftL32,
7331 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7332 (i32 vecshiftL32:$imm)))]> {
7334 let Inst{20-16} = imm;
7337 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7338 V128, V128, vecshiftL32,
7340 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7341 (i32 vecshiftL32:$imm)))]> {
7343 let Inst{20-16} = imm;
7346 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7347 V128, V128, vecshiftL64,
7349 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7350 (i32 vecshiftL64:$imm)))]> {
7352 let Inst{21-16} = imm;
7356 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7357 SDPatternOperator OpNode> {
7358 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7359 V64, V64, vecshiftR8,
7361 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7362 (i32 vecshiftR8:$imm)))]> {
7364 let Inst{18-16} = imm;
7367 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7368 V128, V128, vecshiftR8,
7369 asm, ".16b", ".16b",
7370 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7371 (i32 vecshiftR8:$imm)))]> {
7373 let Inst{18-16} = imm;
7376 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7377 V64, V64, vecshiftR16,
7379 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7380 (i32 vecshiftR16:$imm)))]> {
7382 let Inst{19-16} = imm;
7385 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7386 V128, V128, vecshiftR16,
7388 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7389 (i32 vecshiftR16:$imm)))]> {
7391 let Inst{19-16} = imm;
7394 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7395 V64, V64, vecshiftR32,
7397 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7398 (i32 vecshiftR32:$imm)))]> {
7400 let Inst{20-16} = imm;
7403 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7404 V128, V128, vecshiftR32,
7406 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7407 (i32 vecshiftR32:$imm)))]> {
7409 let Inst{20-16} = imm;
7412 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7413 V128, V128, vecshiftR64,
7415 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7416 (i32 vecshiftR64:$imm)))]> {
7418 let Inst{21-16} = imm;
7422 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7423 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7424 SDPatternOperator OpNode = null_frag> {
7425 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7426 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7427 [(set (v8i8 V64:$dst),
7428 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7429 (i32 vecshiftR8:$imm)))]> {
7431 let Inst{18-16} = imm;
7434 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7435 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7436 [(set (v16i8 V128:$dst),
7437 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7438 (i32 vecshiftR8:$imm)))]> {
7440 let Inst{18-16} = imm;
7443 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7444 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7445 [(set (v4i16 V64:$dst),
7446 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7447 (i32 vecshiftR16:$imm)))]> {
7449 let Inst{19-16} = imm;
7452 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7453 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7454 [(set (v8i16 V128:$dst),
7455 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7456 (i32 vecshiftR16:$imm)))]> {
7458 let Inst{19-16} = imm;
7461 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7462 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7463 [(set (v2i32 V64:$dst),
7464 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7465 (i32 vecshiftR32:$imm)))]> {
7467 let Inst{20-16} = imm;
7470 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7471 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7472 [(set (v4i32 V128:$dst),
7473 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7474 (i32 vecshiftR32:$imm)))]> {
7476 let Inst{20-16} = imm;
7479 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7480 V128, V128, vecshiftR64,
7481 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7482 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7483 (i32 vecshiftR64:$imm)))]> {
7485 let Inst{21-16} = imm;
7489 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7490 SDPatternOperator OpNode = null_frag> {
7491 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7492 V64, V64, vecshiftL8,
7494 [(set (v8i8 V64:$dst),
7495 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7496 (i32 vecshiftL8:$imm)))]> {
7498 let Inst{18-16} = imm;
7501 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7502 V128, V128, vecshiftL8,
7503 asm, ".16b", ".16b",
7504 [(set (v16i8 V128:$dst),
7505 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7506 (i32 vecshiftL8:$imm)))]> {
7508 let Inst{18-16} = imm;
7511 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7512 V64, V64, vecshiftL16,
7514 [(set (v4i16 V64:$dst),
7515 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7516 (i32 vecshiftL16:$imm)))]> {
7518 let Inst{19-16} = imm;
7521 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7522 V128, V128, vecshiftL16,
7524 [(set (v8i16 V128:$dst),
7525 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7526 (i32 vecshiftL16:$imm)))]> {
7528 let Inst{19-16} = imm;
7531 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7532 V64, V64, vecshiftL32,
7534 [(set (v2i32 V64:$dst),
7535 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7536 (i32 vecshiftL32:$imm)))]> {
7538 let Inst{20-16} = imm;
7541 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7542 V128, V128, vecshiftL32,
7544 [(set (v4i32 V128:$dst),
7545 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7546 (i32 vecshiftL32:$imm)))]> {
7548 let Inst{20-16} = imm;
7551 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7552 V128, V128, vecshiftL64,
7554 [(set (v2i64 V128:$dst),
7555 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7556 (i32 vecshiftL64:$imm)))]> {
7558 let Inst{21-16} = imm;
7562 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7563 SDPatternOperator OpNode> {
7564 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7565 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7566 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7568 let Inst{18-16} = imm;
7571 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7572 V128, V128, vecshiftL8,
7573 asm#"2", ".8h", ".16b",
7574 [(set (v8i16 V128:$Rd),
7575 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7577 let Inst{18-16} = imm;
7580 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7581 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7582 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7584 let Inst{19-16} = imm;
7587 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7588 V128, V128, vecshiftL16,
7589 asm#"2", ".4s", ".8h",
7590 [(set (v4i32 V128:$Rd),
7591 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7594 let Inst{19-16} = imm;
7597 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7598 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7599 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7601 let Inst{20-16} = imm;
7604 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7605 V128, V128, vecshiftL32,
7606 asm#"2", ".2d", ".4s",
7607 [(set (v2i64 V128:$Rd),
7608 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7610 let Inst{20-16} = imm;
7616 // Vector load/store
7618 // SIMD ldX/stX no-index memory references don't allow the optional
7619 // ", #0" constant and handle post-indexing explicitly, so we use
7620 // a more specialized parse method for them. Otherwise, it's the same as
7621 // the general GPR64sp handling.
7623 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7624 string asm, dag oops, dag iops, list<dag> pattern>
7625 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7630 let Inst{29-23} = 0b0011000;
7632 let Inst{21-16} = 0b000000;
7633 let Inst{15-12} = opcode;
7634 let Inst{11-10} = size;
7639 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7640 string asm, dag oops, dag iops>
7641 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7647 let Inst{29-23} = 0b0011001;
7650 let Inst{20-16} = Xm;
7651 let Inst{15-12} = opcode;
7652 let Inst{11-10} = size;
7657 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7658 // register post-index addressing from the zero register.
7659 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7660 int Offset, int Size> {
7661 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7662 // "ld1\t$Vt, [$Rn], #16"
7663 // may get mapped to
7664 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7665 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7666 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7668 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7671 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7672 // "ld1.8b\t$Vt, [$Rn], #16"
7673 // may get mapped to
7674 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7675 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7676 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7678 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7681 // E.g. "ld1.8b { v0, v1 }, [x1]"
7682 // "ld1\t$Vt, [$Rn]"
7683 // may get mapped to
7684 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7685 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7686 (!cast<Instruction>(NAME # Count # "v" # layout)
7687 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7690 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7691 // "ld1\t$Vt, [$Rn], $Xm"
7692 // may get mapped to
7693 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7694 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7695 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7697 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7698 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7701 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7702 int Offset64, bits<4> opcode> {
7703 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7704 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7705 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7706 (ins GPR64sp:$Rn), []>;
7707 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7708 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7709 (ins GPR64sp:$Rn), []>;
7710 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7711 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7712 (ins GPR64sp:$Rn), []>;
7713 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7714 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7715 (ins GPR64sp:$Rn), []>;
7716 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7717 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7718 (ins GPR64sp:$Rn), []>;
7719 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7720 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7721 (ins GPR64sp:$Rn), []>;
7722 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7723 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7724 (ins GPR64sp:$Rn), []>;
7727 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7728 (outs GPR64sp:$wback,
7729 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7731 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7732 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7733 (outs GPR64sp:$wback,
7734 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7736 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7737 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7738 (outs GPR64sp:$wback,
7739 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7741 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7742 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7743 (outs GPR64sp:$wback,
7744 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7746 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7747 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7748 (outs GPR64sp:$wback,
7749 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7751 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7752 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7753 (outs GPR64sp:$wback,
7754 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7756 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7757 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7758 (outs GPR64sp:$wback,
7759 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7761 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7764 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7765 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7766 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7767 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7768 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7769 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7770 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7773 // Only ld1/st1 has a v1d version.
7774 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7775 int Offset64, bits<4> opcode> {
7776 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7777 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7778 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7780 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7781 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7783 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7784 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7786 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7787 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7789 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7790 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7792 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7793 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7795 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7796 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7799 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7800 (outs GPR64sp:$wback),
7801 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7803 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7804 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7805 (outs GPR64sp:$wback),
7806 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7808 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7809 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7810 (outs GPR64sp:$wback),
7811 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7813 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7814 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7815 (outs GPR64sp:$wback),
7816 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7818 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7819 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7820 (outs GPR64sp:$wback),
7821 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7823 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7824 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7825 (outs GPR64sp:$wback),
7826 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7828 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7829 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7830 (outs GPR64sp:$wback),
7831 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7833 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7836 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7837 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7838 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7839 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7840 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7841 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7842 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7845 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7846 int Offset128, int Offset64, bits<4> opcode>
7847 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7849 // LD1 instructions have extra "1d" variants.
7850 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7851 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7852 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7853 (ins GPR64sp:$Rn), []>;
7855 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7856 (outs GPR64sp:$wback,
7857 !cast<RegisterOperand>(veclist # "1d"):$Vt),
7859 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7862 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7865 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7866 int Offset128, int Offset64, bits<4> opcode>
7867 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7869 // ST1 instructions have extra "1d" variants.
7870 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7871 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7872 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7875 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
7876 (outs GPR64sp:$wback),
7877 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7879 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7882 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7885 multiclass SIMDLd1Multiple<string asm> {
7886 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7887 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7888 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7889 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7892 multiclass SIMDSt1Multiple<string asm> {
7893 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7894 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7895 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7896 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7899 multiclass SIMDLd2Multiple<string asm> {
7900 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7903 multiclass SIMDSt2Multiple<string asm> {
7904 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7907 multiclass SIMDLd3Multiple<string asm> {
7908 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7911 multiclass SIMDSt3Multiple<string asm> {
7912 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7915 multiclass SIMDLd4Multiple<string asm> {
7916 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7919 multiclass SIMDSt4Multiple<string asm> {
7920 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7924 // AdvSIMD Load/store single-element
7927 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
7928 string asm, string operands, string cst,
7929 dag oops, dag iops, list<dag> pattern>
7930 : I<oops, iops, asm, operands, cst, pattern> {
7934 let Inst{29-24} = 0b001101;
7937 let Inst{15-13} = opcode;
7942 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
7943 string asm, string operands, string cst,
7944 dag oops, dag iops, list<dag> pattern>
7945 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
7949 let Inst{29-24} = 0b001101;
7952 let Inst{15-13} = opcode;
7958 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7959 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
7961 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
7962 (outs listtype:$Vt), (ins GPR64sp:$Rn),
7966 let Inst{20-16} = 0b00000;
7968 let Inst{11-10} = size;
7970 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7971 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
7972 string asm, Operand listtype, Operand GPR64pi>
7973 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
7975 (outs GPR64sp:$wback, listtype:$Vt),
7976 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
7980 let Inst{20-16} = Xm;
7982 let Inst{11-10} = size;
7985 multiclass SIMDLdrAliases<string asm, string layout, string Count,
7986 int Offset, int Size> {
7987 // E.g. "ld1r { v0.8b }, [x1], #1"
7988 // "ld1r.8b\t$Vt, [$Rn], #1"
7989 // may get mapped to
7990 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
7991 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7992 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7994 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7997 // E.g. "ld1r.8b { v0 }, [x1], #1"
7998 // "ld1r.8b\t$Vt, [$Rn], #1"
7999 // may get mapped to
8000 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8001 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8002 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8004 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8007 // E.g. "ld1r.8b { v0 }, [x1]"
8008 // "ld1r.8b\t$Vt, [$Rn]"
8009 // may get mapped to
8010 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8011 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8012 (!cast<Instruction>(NAME # "v" # layout)
8013 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8016 // E.g. "ld1r.8b { v0 }, [x1], x2"
8017 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8018 // may get mapped to
8019 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8020 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8021 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8023 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8024 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8027 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8028 int Offset1, int Offset2, int Offset4, int Offset8> {
8029 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8030 !cast<Operand>("VecList" # Count # "8b")>;
8031 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8032 !cast<Operand>("VecList" # Count #"16b")>;
8033 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8034 !cast<Operand>("VecList" # Count #"4h")>;
8035 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8036 !cast<Operand>("VecList" # Count #"8h")>;
8037 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8038 !cast<Operand>("VecList" # Count #"2s")>;
8039 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8040 !cast<Operand>("VecList" # Count #"4s")>;
8041 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8042 !cast<Operand>("VecList" # Count #"1d")>;
8043 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8044 !cast<Operand>("VecList" # Count #"2d")>;
8046 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8047 !cast<Operand>("VecList" # Count # "8b"),
8048 !cast<Operand>("GPR64pi" # Offset1)>;
8049 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8050 !cast<Operand>("VecList" # Count # "16b"),
8051 !cast<Operand>("GPR64pi" # Offset1)>;
8052 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8053 !cast<Operand>("VecList" # Count # "4h"),
8054 !cast<Operand>("GPR64pi" # Offset2)>;
8055 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8056 !cast<Operand>("VecList" # Count # "8h"),
8057 !cast<Operand>("GPR64pi" # Offset2)>;
8058 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8059 !cast<Operand>("VecList" # Count # "2s"),
8060 !cast<Operand>("GPR64pi" # Offset4)>;
8061 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8062 !cast<Operand>("VecList" # Count # "4s"),
8063 !cast<Operand>("GPR64pi" # Offset4)>;
8064 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8065 !cast<Operand>("VecList" # Count # "1d"),
8066 !cast<Operand>("GPR64pi" # Offset8)>;
8067 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8068 !cast<Operand>("VecList" # Count # "2d"),
8069 !cast<Operand>("GPR64pi" # Offset8)>;
8071 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8072 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8073 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8074 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8075 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8076 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8077 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8078 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8081 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8082 dag oops, dag iops, list<dag> pattern>
8083 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8085 // idx encoded in Q:S:size fields.
8087 let Inst{30} = idx{3};
8089 let Inst{20-16} = 0b00000;
8090 let Inst{12} = idx{2};
8091 let Inst{11-10} = idx{1-0};
8093 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8094 dag oops, dag iops, list<dag> pattern>
8095 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8096 oops, iops, pattern> {
8097 // idx encoded in Q:S:size fields.
8099 let Inst{30} = idx{3};
8101 let Inst{20-16} = 0b00000;
8102 let Inst{12} = idx{2};
8103 let Inst{11-10} = idx{1-0};
8105 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8107 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8108 "$Rn = $wback", oops, iops, []> {
8109 // idx encoded in Q:S:size fields.
8112 let Inst{30} = idx{3};
8114 let Inst{20-16} = Xm;
8115 let Inst{12} = idx{2};
8116 let Inst{11-10} = idx{1-0};
8118 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8120 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8121 "$Rn = $wback", oops, iops, []> {
8122 // idx encoded in Q:S:size fields.
8125 let Inst{30} = idx{3};
8127 let Inst{20-16} = Xm;
8128 let Inst{12} = idx{2};
8129 let Inst{11-10} = idx{1-0};
8132 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8133 dag oops, dag iops, list<dag> pattern>
8134 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8136 // idx encoded in Q:S:size<1> fields.
8138 let Inst{30} = idx{2};
8140 let Inst{20-16} = 0b00000;
8141 let Inst{12} = idx{1};
8142 let Inst{11} = idx{0};
8143 let Inst{10} = size;
8145 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8146 dag oops, dag iops, list<dag> pattern>
8147 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8148 oops, iops, pattern> {
8149 // idx encoded in Q:S:size<1> fields.
8151 let Inst{30} = idx{2};
8153 let Inst{20-16} = 0b00000;
8154 let Inst{12} = idx{1};
8155 let Inst{11} = idx{0};
8156 let Inst{10} = size;
8159 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8161 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8162 "$Rn = $wback", oops, iops, []> {
8163 // idx encoded in Q:S:size<1> fields.
8166 let Inst{30} = idx{2};
8168 let Inst{20-16} = Xm;
8169 let Inst{12} = idx{1};
8170 let Inst{11} = idx{0};
8171 let Inst{10} = size;
8173 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8175 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8176 "$Rn = $wback", oops, iops, []> {
8177 // idx encoded in Q:S:size<1> fields.
8180 let Inst{30} = idx{2};
8182 let Inst{20-16} = Xm;
8183 let Inst{12} = idx{1};
8184 let Inst{11} = idx{0};
8185 let Inst{10} = size;
8187 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8188 dag oops, dag iops, list<dag> pattern>
8189 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8191 // idx encoded in Q:S fields.
8193 let Inst{30} = idx{1};
8195 let Inst{20-16} = 0b00000;
8196 let Inst{12} = idx{0};
8197 let Inst{11-10} = size;
8199 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8200 dag oops, dag iops, list<dag> pattern>
8201 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8202 oops, iops, pattern> {
8203 // idx encoded in Q:S fields.
8205 let Inst{30} = idx{1};
8207 let Inst{20-16} = 0b00000;
8208 let Inst{12} = idx{0};
8209 let Inst{11-10} = size;
8211 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8212 string asm, dag oops, dag iops>
8213 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8214 "$Rn = $wback", oops, iops, []> {
8215 // idx encoded in Q:S fields.
8218 let Inst{30} = idx{1};
8220 let Inst{20-16} = Xm;
8221 let Inst{12} = idx{0};
8222 let Inst{11-10} = size;
8224 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8225 string asm, dag oops, dag iops>
8226 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8227 "$Rn = $wback", oops, iops, []> {
8228 // idx encoded in Q:S fields.
8231 let Inst{30} = idx{1};
8233 let Inst{20-16} = Xm;
8234 let Inst{12} = idx{0};
8235 let Inst{11-10} = size;
8237 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8238 dag oops, dag iops, list<dag> pattern>
8239 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8241 // idx encoded in Q field.
8245 let Inst{20-16} = 0b00000;
8247 let Inst{11-10} = size;
8249 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8250 dag oops, dag iops, list<dag> pattern>
8251 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8252 oops, iops, pattern> {
8253 // idx encoded in Q field.
8257 let Inst{20-16} = 0b00000;
8259 let Inst{11-10} = size;
8261 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8262 string asm, dag oops, dag iops>
8263 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8264 "$Rn = $wback", oops, iops, []> {
8265 // idx encoded in Q field.
8270 let Inst{20-16} = Xm;
8272 let Inst{11-10} = size;
8274 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8275 string asm, dag oops, dag iops>
8276 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8277 "$Rn = $wback", oops, iops, []> {
8278 // idx encoded in Q field.
8283 let Inst{20-16} = Xm;
8285 let Inst{11-10} = size;
8288 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8289 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8290 RegisterOperand listtype,
8291 RegisterOperand GPR64pi> {
8292 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8293 (outs listtype:$dst),
8294 (ins listtype:$Vt, VectorIndexB:$idx,
8297 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8298 (outs GPR64sp:$wback, listtype:$dst),
8299 (ins listtype:$Vt, VectorIndexB:$idx,
8300 GPR64sp:$Rn, GPR64pi:$Xm)>;
8302 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8303 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8304 RegisterOperand listtype,
8305 RegisterOperand GPR64pi> {
8306 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8307 (outs listtype:$dst),
8308 (ins listtype:$Vt, VectorIndexH:$idx,
8311 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8312 (outs GPR64sp:$wback, listtype:$dst),
8313 (ins listtype:$Vt, VectorIndexH:$idx,
8314 GPR64sp:$Rn, GPR64pi:$Xm)>;
8316 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8317 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8318 RegisterOperand listtype,
8319 RegisterOperand GPR64pi> {
8320 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8321 (outs listtype:$dst),
8322 (ins listtype:$Vt, VectorIndexS:$idx,
8325 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8326 (outs GPR64sp:$wback, listtype:$dst),
8327 (ins listtype:$Vt, VectorIndexS:$idx,
8328 GPR64sp:$Rn, GPR64pi:$Xm)>;
8330 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8331 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8332 RegisterOperand listtype, RegisterOperand GPR64pi> {
8333 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8334 (outs listtype:$dst),
8335 (ins listtype:$Vt, VectorIndexD:$idx,
8338 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8339 (outs GPR64sp:$wback, listtype:$dst),
8340 (ins listtype:$Vt, VectorIndexD:$idx,
8341 GPR64sp:$Rn, GPR64pi:$Xm)>;
8343 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8344 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8345 RegisterOperand listtype, RegisterOperand GPR64pi> {
8346 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8347 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8350 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8351 (outs GPR64sp:$wback),
8352 (ins listtype:$Vt, VectorIndexB:$idx,
8353 GPR64sp:$Rn, GPR64pi:$Xm)>;
8355 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8356 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8357 RegisterOperand listtype, RegisterOperand GPR64pi> {
8358 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8359 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8362 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8363 (outs GPR64sp:$wback),
8364 (ins listtype:$Vt, VectorIndexH:$idx,
8365 GPR64sp:$Rn, GPR64pi:$Xm)>;
8367 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8368 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8369 RegisterOperand listtype, RegisterOperand GPR64pi> {
8370 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8371 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8374 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8375 (outs GPR64sp:$wback),
8376 (ins listtype:$Vt, VectorIndexS:$idx,
8377 GPR64sp:$Rn, GPR64pi:$Xm)>;
8379 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8380 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8381 RegisterOperand listtype, RegisterOperand GPR64pi> {
8382 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8383 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8386 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8387 (outs GPR64sp:$wback),
8388 (ins listtype:$Vt, VectorIndexD:$idx,
8389 GPR64sp:$Rn, GPR64pi:$Xm)>;
8392 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8393 string Count, int Offset, Operand idxtype> {
8394 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8395 // "ld1\t$Vt, [$Rn], #1"
8396 // may get mapped to
8397 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8398 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8399 (!cast<Instruction>(NAME # Type # "_POST")
8401 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8402 idxtype:$idx, XZR), 1>;
8404 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8405 // "ld1.8b\t$Vt, [$Rn], #1"
8406 // may get mapped to
8407 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8408 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8409 (!cast<Instruction>(NAME # Type # "_POST")
8411 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8412 idxtype:$idx, XZR), 0>;
8414 // E.g. "ld1.8b { v0 }[0], [x1]"
8415 // "ld1.8b\t$Vt, [$Rn]"
8416 // may get mapped to
8417 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8418 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8419 (!cast<Instruction>(NAME # Type)
8420 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8421 idxtype:$idx, GPR64sp:$Rn), 0>;
8423 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8424 // "ld1.8b\t$Vt, [$Rn], $Xm"
8425 // may get mapped to
8426 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8427 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8428 (!cast<Instruction>(NAME # Type # "_POST")
8430 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8432 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8435 multiclass SIMDLdSt1SingleAliases<string asm> {
8436 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8437 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8438 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8439 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8442 multiclass SIMDLdSt2SingleAliases<string asm> {
8443 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8444 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8445 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8446 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8449 multiclass SIMDLdSt3SingleAliases<string asm> {
8450 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8451 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8452 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8453 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8456 multiclass SIMDLdSt4SingleAliases<string asm> {
8457 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8458 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8459 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8460 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8462 } // end of 'let Predicates = [HasNEON]'
8464 //----------------------------------------------------------------------------
8465 // Crypto extensions
8466 //----------------------------------------------------------------------------
8468 let Predicates = [HasCrypto] in {
8469 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8470 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8472 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8476 let Inst{31-16} = 0b0100111000101000;
8477 let Inst{15-12} = opc;
8478 let Inst{11-10} = 0b10;
8483 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8484 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8485 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8487 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8488 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8490 [(set (v16i8 V128:$dst),
8491 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8493 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8494 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8495 dag oops, dag iops, list<dag> pat>
8496 : I<oops, iops, asm,
8497 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8498 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8503 let Inst{31-21} = 0b01011110000;
8504 let Inst{20-16} = Rm;
8506 let Inst{14-12} = opc;
8507 let Inst{11-10} = 0b00;
8512 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8513 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8514 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8515 [(set (v4i32 FPR128:$dst),
8516 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8517 (v4i32 V128:$Rm)))]>;
8519 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8520 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8521 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8522 [(set (v4i32 V128:$dst),
8523 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8524 (v4i32 V128:$Rm)))]>;
8526 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8527 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8528 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8529 [(set (v4i32 FPR128:$dst),
8530 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8531 (v4i32 V128:$Rm)))]>;
8533 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8534 class SHA2OpInst<bits<4> opc, string asm, string kind,
8535 string cstr, dag oops, dag iops,
8537 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8538 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8542 let Inst{31-16} = 0b0101111000101000;
8543 let Inst{15-12} = opc;
8544 let Inst{11-10} = 0b10;
8549 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8550 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8551 (ins V128:$Rd, V128:$Rn),
8552 [(set (v4i32 V128:$dst),
8553 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8555 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8556 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8557 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8558 } // end of 'let Predicates = [HasCrypto]'
8560 // Allow the size specifier tokens to be upper case, not just lower.
8561 def : TokenAlias<".8B", ".8b">;
8562 def : TokenAlias<".4H", ".4h">;
8563 def : TokenAlias<".2S", ".2s">;
8564 def : TokenAlias<".1D", ".1d">;
8565 def : TokenAlias<".16B", ".16b">;
8566 def : TokenAlias<".8H", ".8h">;
8567 def : TokenAlias<".4S", ".4s">;
8568 def : TokenAlias<".2D", ".2d">;
8569 def : TokenAlias<".1Q", ".1q">;
8570 def : TokenAlias<".B", ".b">;
8571 def : TokenAlias<".H", ".h">;
8572 def : TokenAlias<".S", ".s">;
8573 def : TokenAlias<".D", ".d">;
8574 def : TokenAlias<".Q", ".q">;